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spi: versal2: Enable spi drivers for Versal Gen 2

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Enable and update OSPI/QSPI/GQSPI drivers to support Versal Gen 2 SoCs.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/691782470f56f7d49a3204f6757296f2752d4156.1716994063.git.michal.simek@amd.com
This commit is contained in:
Michal Simek
2024-05-29 16:48:01 +02:00
parent 4950a98d14
commit 9bf522cd5c
4 changed files with 10 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
configs/amd_versal2_virt_defconfig
View File

@@ -5,7 +5,6 @@ CONFIG_SYS_INIT_SP_BSS_OFFSET=1572864
CONFIG_ARCH_VERSAL2=y
CONFIG_TEXT_BASE=0x8000000
CONFIG_SYS_MALLOC_F_LEN=0x100000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="amd-versal2-virt"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
@@ -124,7 +123,10 @@ CONFIG_SOC_DEVICE=y
CONFIG_SOC_AMD_VERSAL2=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_CADENCE_QSPI=y
CONFIG_CADENCE_OSPI_VERSAL=y
CONFIG_ZYNQ_SPI=y
CONFIG_ZYNQMP_GQSPI=y
CONFIG_TPM2_TIS_SPI=y
CONFIG_USB=y
CONFIG_DM_USB_GADGET=y

2
drivers/spi/Kconfig
View File

@@ -156,7 +156,7 @@ config CQSPI_REF_CLK
config CADENCE_OSPI_VERSAL
bool "Configure Versal OSPI"
depends on (ARCH_VERSAL || ARCH_VERSAL_NET) && CADENCE_QSPI
depends on (ARCH_VERSAL || ARCH_VERSAL_NET || ARCH_VERSAL2) && CADENCE_QSPI
imply DM_GPIO
help
This option is used to enable Versal OSPI DMA operations which

3
drivers/spi/cadence_qspi.c
View File

@@ -253,7 +253,8 @@ static int cadence_spi_probe(struct udevice *bus)
/* Versal and Versal-NET use spi calibration to set read delay */
if (CONFIG_IS_ENABLED(ARCH_VERSAL) ||
CONFIG_IS_ENABLED(ARCH_VERSAL_NET))
CONFIG_IS_ENABLED(ARCH_VERSAL_NET) ||
CONFIG_IS_ENABLED(ARCH_VERSAL2))
if (priv->read_delay >= 0)
priv->read_delay = -1;

6
drivers/spi/zynqmp_gqspi.c
View File

@@ -106,7 +106,8 @@
#define TAP_DLY_BYPASS_LQSPI_RX_SHIFT 2
#define GQSPI_DATA_DLY_ADJ_OFST 0x000001F8
#define IOU_TAPDLY_BYPASS_OFST !(IS_ENABLED(CONFIG_ARCH_VERSAL) || \
IS_ENABLED(CONFIG_ARCH_VERSAL_NET)) ? \
IS_ENABLED(CONFIG_ARCH_VERSAL_NET) || \
IS_ENABLED(CONFIG_ARCH_VERSAL2)) ? \
0xFF180390 : 0xF103003C
#define GQSPI_LPBK_DLY_ADJ_LPBK_MASK 0x00000020
#define GQSPI_FREQ_37_5MHZ 37500000
@@ -316,7 +317,8 @@ static void zynqmp_qspi_set_tapdelay(struct udevice *bus, u32 baudrateval)
__func__, clk_rate, baudrateval, reqhz);
if (!(IS_ENABLED(CONFIG_ARCH_VERSAL) ||
IS_ENABLED(CONFIG_ARCH_VERSAL_NET))) {
IS_ENABLED(CONFIG_ARCH_VERSAL_NET) ||
IS_ENABLED(CONFIG_ARCH_VERSAL2))) {
if (reqhz <= GQSPI_FREQ_40MHZ) {
tapdlybypass = TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
TAP_DLY_BYPASS_LQSPI_RX_SHIFT;