Mirrors/u-boot
1
0
Fork 0
mirror of https://source.denx.de/u-boot/u-boot.git synced 2026-06-13 15:03:58 +03:00
Code Issues Packages Projects Releases Wiki Activity

Merge tag 'for-v2023-07-rc1' of https://source.denx.de/u-boot/custodians/u-boot-i2c

Browse Source 
i2c updates for v2023-07-rc1

- designware_i2c: remove apparently redundant read of 'i2c, speeds' DT property
  from Rasmus Villemoes

- fix: correct I2C deblock logic from Haibo Chen

- imx_lpi2c: Fix misuse the IS_ENABLED for DM clock from Ye Li

- m68k: convert to DM from Angelo Dureghello
This commit is contained in:
Tom Rini
2023-04-11 09:29:28 -04:00
parent 11c25c6df0 5cf0086372
commit 9e804638bf
44 changed files with 325 additions and 66 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
arch/m68k/cpu/mcf5445x/cpu_init.c
View File

@@ -159,14 +159,14 @@ void cpu_init_f(void)
/* NAND */
out_8(&pm->pmcr0, 63);
#ifdef CONFIG_SYS_I2C_0
#ifdef CFG_SYS_I2C_0
out_8(&gpio->par_cani2c, 0xF0);
/* I2C0 pull up */
out_be16(&gpio->pcr_b, 0x003C);
/* I2C0 max speed */
out_8(&gpio->srcr_cani2c, 0x03);
#endif
#ifdef CONFIG_SYS_I2C_2
#ifdef CFG_SYS_I2C_2
/* I2C2 */
out_8(&gpio->par_ssi0h, 0xA0);
/* I2C2, UART7 */
@@ -184,7 +184,7 @@ void cpu_init_f(void)
/* I2C2 pull up */
out_be16(&gpio->pcr_h, 0xF000);
#endif
#ifdef CONFIG_SYS_I2C_5
#ifdef CFG_SYS_I2C_5
/* I2C5 */
out_8(&gpio->par_uart1, 0x0A);
/* I2C5 pull up */

5
arch/m68k/cpu/mcf5445x/speed.c
View File

@@ -129,9 +129,8 @@ int get_clocks(void)
setup_5441x_clocks();
#endif
#ifdef CONFIG_SYS_FSL_I2C
gd->arch.i2c1_clk = gd->bus_clk;
#endif
if (IS_ENABLED(CONFIG_SYS_I2C_FSL))
gd->arch.i2c1_clk = gd->bus_clk;
return (0);
}

6
arch/m68k/dts/M5208EVBE.dts
View File

@@ -23,3 +23,9 @@
&fec0 {
status = "okay";
};
&i2c0 {
clock-frequency = <80000>;
u-boot,i2c-slave-addr = <0x7f>;
status = "okay";
};

5
arch/m68k/dts/M5253DEMO.dts
View File

@@ -20,3 +20,8 @@
status = "okay";
};
&i2c0 {
clock-frequency = <80000>;
u-boot,i2c-slave-addr = <0x7f>;
status = "okay";
};

6
arch/m68k/dts/M5275EVB.dts
View File

@@ -27,3 +27,9 @@
&fec1 {
status = "okay";
};
&i2c0 {
clock-frequency = <80000>;
u-boot,i2c-slave-addr = <0x7f>;
status = "okay";
};

6
arch/m68k/dts/M53017EVB.dts
View File

@@ -27,3 +27,9 @@
&fec1 {
status = "okay";
};
&i2c0 {
clock-frequency = <80000>;
u-boot,i2c-slave-addr = <0x7f>;
status = "okay";
};

6
arch/m68k/dts/M5329AFEE.dts
View File

@@ -23,3 +23,9 @@
&fec0 {
status = "okay";
};
&i2c0 {
clock-frequency = <80000>;
u-boot,i2c-slave-addr = <0x7f>;
status = "okay";
};

6
arch/m68k/dts/M5329BFEE.dts
View File

@@ -23,3 +23,9 @@
&fec0 {
status = "okay";
};
&i2c0 {
clock-frequency = <80000>;
u-boot,i2c-slave-addr = <0x7f>;
status = "okay";
};

4
arch/m68k/dts/M5373EVB.dts
View File

@@ -23,3 +23,7 @@
&fec0 {
status = "okay";
};
&i2c0 {
status = "okay";
};

5
arch/m68k/dts/astro_mcf5373l.dts
View File

@@ -20,3 +20,8 @@
status = "okay";
};
&i2c0 {
clock-frequency = <80000>;
u-boot,i2c-slave-addr = <0x7f>;
status = "okay";
};

9
arch/m68k/dts/eb_cpu5282.dts
View File

@@ -23,3 +23,12 @@
&fec0 {
status = "okay";
};
&i2c0 {
status = "okay";
rtc@68 {
compatible = "dallas,ds1338";
reg = <0x68>;
};
};

9
arch/m68k/dts/eb_cpu5282_internal.dts
View File

@@ -23,3 +23,12 @@
&fec0 {
status = "okay";
};
&i2c0 {
status = "okay";
rtc@68 {
compatible = "dallas,ds1338";
reg = <0x68>;
};
};

10
arch/m68k/dts/mcf5208.dtsi
View File

@@ -42,5 +42,15 @@
timeout-loop = <50000>;
status = "disabled";
};
i2c0: i2c@fc058000 {
compatible = "fsl-i2c";
#address-cells=<1>;
#size-cells=<0>;
cell-index = <0>;
reg = <0xfc058000 0x14>;
clock-frequency = <100000>;
status = "disabled";
};
};
};

10
arch/m68k/dts/mcf523x.dtsi
View File

@@ -51,6 +51,16 @@
timeout-loop = <50000>;
status = "disabled";
};
i2c0: i2c@300 {
compatible = "fsl-i2c";
#address-cells=<1>;
#size-cells=<0>;
cell-index = <0>;
reg = <0x300 0x14>;
clock-frequency = <100000>;
status = "disabled";
};
};
};
};

28
arch/m68k/dts/mcf5249.dtsi
View File

@@ -33,6 +33,34 @@
reg = <0x200 0x40>;
status = "disabled";
};
i2c0: i2c@280 {
compatible = "fsl-i2c";
#address-cells=<1>;
#size-cells=<0>;
cell-index = <0>;
reg = <0x280 0x14>;
clock-frequency = <100000>;
status = "disabled";
};
};
mbar2: mbar2@80000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 0x80000000 0x10000>;
reg = <0x80000000 0x10000>;
i2c1: i2c@440 {
compatible = "fsl-i2c";
#address-cells=<1>;
#size-cells=<0>;
cell-index = <0>;
reg = <0x440 0x14>;
clock-frequency = <100000>;
status = "disabled";
};
};
};
};

28
arch/m68k/dts/mcf5253.dtsi
View File

@@ -39,6 +39,34 @@
reg = <0xc00 0x40>;
status = "disabled";
};
i2c0: i2c@280 {
compatible = "fsl-i2c";
#address-cells=<1>;
#size-cells=<0>;
cell-index = <0>;
reg = <0x280 0x14>;
clock-frequency = <100000>;
status = "disabled";
};
};
mbar2: mbar2@80000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 0x80000000 0x10000>;
reg = <0x80000000 0x10000>;
i2c1: i2c@440 {
compatible = "fsl-i2c";
#address-cells=<1>;
#size-cells=<0>;
cell-index = <0>;
reg = <0x440 0x14>;
clock-frequency = <100000>;
status = "disabled";
};
};
};
};

10
arch/m68k/dts/mcf5271.dtsi
View File

@@ -49,6 +49,16 @@
timeout-loop = <50000>;
status = "disabled";
};
i2c0: i2c@300 {
compatible = "fsl-i2c";
#address-cells=<1>;
#size-cells=<0>;
cell-index = <0>;
reg = <0x300 0x14>;
clock-frequency = <100000>;
status = "disabled";
};
};
};
};

10
arch/m68k/dts/mcf5275.dtsi
View File

@@ -59,6 +59,16 @@
timeout-loop = <50000>;
status = "disabled";
};
i2c0: i2c@300 {
compatible = "fsl-i2c";
#address-cells=<1>;
#size-cells=<0>;
cell-index = <0>;
reg = <0x300 0x14>;
clock-frequency = <100000>;
status = "disabled";
};
};
};
};

10
arch/m68k/dts/mcf5282.dtsi
View File

@@ -49,6 +49,16 @@
timeout-loop = <50000>;
status = "disabled";
};
i2c0: i2c@300 {
compatible = "fsl-i2c";
#address-cells=<1>;
#size-cells=<0>;
cell-index = <0>;
reg = <0x300 0x14>;
clock-frequency = <100000>;
status = "disabled";
};
};
};
};

10
arch/m68k/dts/mcf5301x.dtsi
View File

@@ -65,5 +65,15 @@
timeout-loop = <50000>;
status = "disabled";
};
i2c0: i2c@0xfc058000 {
compatible = "fsl-i2c";
#address-cells=<1>;
#size-cells=<0>;
cell-index = <0>;
reg = <0xfc058000 0x100>;
clock-frequency = <100000>;
status = "disabled";
};
};
};

10
arch/m68k/dts/mcf5307.dtsi
View File

@@ -34,6 +34,16 @@
reg = <0x200 0x40>;
status = "disabled";
};
i2c0: i2c@280 {
compatible = "fsl-i2c";
#address-cells=<1>;
#size-cells=<0>;
cell-index = <0>;
reg = <0x280 0x14>;
clock-frequency = <100000>;
status = "disabled";
};
};
};
};

10
arch/m68k/dts/mcf5329.dtsi
View File

@@ -42,5 +42,15 @@
timeout-loop = <50000>;
status = "disabled";
};
i2c0: i2c@0xfc058000 {
compatible = "fsl-i2c";
#address-cells=<1>;
#size-cells=<0>;
cell-index = <0>;
reg = <0xfc058000 0x100>;
clock-frequency = <100000>;
status = "disabled";
};
};
};

10
arch/m68k/dts/mcf537x.dtsi
View File

@@ -42,5 +42,15 @@
timeout-loop = <50000>;
status = "disabled";
};
i2c0: i2c@0xfc058000 {
compatible = "fsl-i2c";
#address-cells=<1>;
#size-cells=<0>;
cell-index = <0>;
reg = <0xfc058000 0x100>;
clock-frequency = <100000>;
status = "disabled";
};
};
};

60
arch/m68k/dts/mcf5441x.dtsi
View File

@@ -103,5 +103,65 @@
timeout-loop = <50000>;
status = "disabled";
};
i2c0: i2c@0xfc058000 {
compatible = "fsl-i2c";
#address-cells=<1>;
#size-cells=<0>;
cell-index = <0>;
reg = <0xfc058000 0x100>;
clock-frequency = <100000>;
status = "disabled";
};
i2c1: i2c@0xfc038000 {
compatible = "fsl-i2c";
#address-cells=<1>;
#size-cells=<0>;
cell-index = <1>;
reg = <0xfc038000 0x100>;
clock-frequency = <100000>;
status = "disabled";
};
i2c2: i2c@0xfc010000 {
compatible = "fsl-i2c";
#address-cells=<1>;
#size-cells=<0>;
cell-index = <2>;
reg = <0xfc010000 0x100>;
clock-frequency = <100000>;
status = "disabled";
};
i2c3: i2c@0xfc014000 {
compatible = "fsl-i2c";
#address-cells=<1>;
#size-cells=<0>;
cell-index = <3>;
reg = <0xfc014000 0x100>;
clock-frequency = <100000>;
status = "disabled";
};
i2c4: i2c@0xfc018000 {
compatible = "fsl-i2c";
#address-cells=<1>;
#size-cells=<0>;
cell-index = <4>;
reg = <0xfc018000 0x100>;
clock-frequency = <100000>;
status = "disabled";
};
i2c5: i2c@0xfc01c000 {
compatible = "fsl-i2c";
#address-cells=<1>;
#size-cells=<0>;
cell-index = <5>;
reg = <0xfc01c000 0x100>;
clock-frequency = <100000>;
status = "disabled";
};
};
};

4
arch/m68k/dts/stmark2.dts
View File

@@ -41,3 +41,7 @@
status = "okay";
mii-base = <0>;
};
&i2c0 {
status = "okay";
};

10
arch/m68k/include/asm/fsl_i2c.h
View File

@@ -57,4 +57,14 @@ typedef struct fsl_i2c_base {
#define I2C_DR_RES ~(I2C_DR)
} fsl_i2c_t;
#if CONFIG_IS_ENABLED(DM_I2C)
struct fsl_i2c_dev {
struct fsl_i2c_base __iomem *base; /* register base */
u32 i2c_clk;
u32 index;
u8 slaveadd;
uint speed;
};
#endif
#endif /* _ASM_I2C_H_ */

5
configs/M5208EVBE_defconfig
View File

@@ -38,11 +38,8 @@ CONFIG_NETMASK="255.255.255.0"
CONFIG_USE_SERVERIP=y
CONFIG_SERVERIP="192.162.1.1"
CONFIG_SYS_RX_ETH_BUFFER=8
CONFIG_SYS_I2C_LEGACY=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_FSL_I2C_OFFSET=0x58000
CONFIG_SYS_I2C_SLAVE=0x7F
CONFIG_SYS_I2C_SPEED=80000
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y

1
configs/M5235EVB_Flash32_defconfig
View File

@@ -61,3 +61,4 @@ CONFIG_MCFFEC=y
CONFIG_MII=y
CONFIG_MCFUART=y
CONFIG_WATCHDOG_TIMEOUT_MSECS=5000
CONFIG_DM_I2C=y

1
configs/M5235EVB_defconfig
View File

@@ -61,3 +61,4 @@ CONFIG_MCFFEC=y
CONFIG_MII=y
CONFIG_MCFUART=y
CONFIG_WATCHDOG_TIMEOUT_MSECS=5000
CONFIG_DM_I2C=y

5
configs/M5253DEMO_defconfig
View File

@@ -37,11 +37,8 @@ CONFIG_SYS_ATA_ALT_OFFSET=0xC0
CONFIG_SYS_ATA_IDE0_OFFSET=0
CONFIG_ATAPI=y
CONFIG_IDE_RESET=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_FSL_I2C_OFFSET=0x280
CONFIG_SYS_I2C_SLAVE=0x7F
CONFIG_SYS_I2C_SPEED=80000
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_MAX_FLASH_SECT=2048
CONFIG_USE_SYS_MAX_FLASH_BANKS=y

5
configs/M5275EVB_defconfig
View File

@@ -34,11 +34,8 @@ CONFIG_OVERWRITE_ETHADDR_ONCE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
CONFIG_SYS_RX_ETH_BUFFER=8
CONFIG_SYS_I2C_LEGACY=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_FSL_I2C_OFFSET=0x300
CONFIG_SYS_I2C_SLAVE=0x7F
CONFIG_SYS_I2C_SPEED=80000
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_FLASH_SHOW_PROGRESS=0

6
configs/M53017EVB_defconfig
View File

@@ -40,11 +40,8 @@ CONFIG_NETMASK="255.255.255.0"
CONFIG_USE_SERVERIP=y
CONFIG_SERVERIP="192.162.1.1"
CONFIG_SYS_RX_ETH_BUFFER=8
CONFIG_SYS_I2C_LEGACY=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_FSL_I2C_OFFSET=0x58000
CONFIG_SYS_I2C_SLAVE=0x7F
CONFIG_SYS_I2C_SPEED=80000
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y
@@ -57,6 +54,7 @@ CONFIG_SYS_MAX_FLASH_SECT=137
CONFIG_MCFFEC=y
CONFIG_SYS_UNIFY_CACHE=y
CONFIG_MII=y
CONFIG_DM_RTC=y
CONFIG_MCFRTC=y
CONFIG_SYS_MCFRTC_BASE=0xFC0A8000
CONFIG_MCFUART=y

6
configs/M5329AFEE_defconfig
View File

@@ -39,11 +39,8 @@ CONFIG_NETMASK="255.255.255.0"
CONFIG_USE_SERVERIP=y
CONFIG_SERVERIP="192.162.1.1"
CONFIG_SYS_RX_ETH_BUFFER=8
CONFIG_SYS_I2C_LEGACY=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_FSL_I2C_OFFSET=0x58000
CONFIG_SYS_I2C_SLAVE=0x7F
CONFIG_SYS_I2C_SPEED=80000
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
@@ -55,6 +52,7 @@ CONFIG_SYS_MAX_FLASH_SECT=137
CONFIG_MCFFEC=y
CONFIG_SYS_UNIFY_CACHE=y
CONFIG_MII=y
CONFIG_DM_RTC=y
CONFIG_MCFRTC=y
CONFIG_SYS_MCFRTC_BASE=0xFC0A8000
CONFIG_MCFUART=y

6
configs/M5329BFEE_defconfig
View File

@@ -40,11 +40,8 @@ CONFIG_NETMASK="255.255.255.0"
CONFIG_USE_SERVERIP=y
CONFIG_SERVERIP="192.162.1.1"
CONFIG_SYS_RX_ETH_BUFFER=8
CONFIG_SYS_I2C_LEGACY=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_FSL_I2C_OFFSET=0x58000
CONFIG_SYS_I2C_SLAVE=0x7F
CONFIG_SYS_I2C_SPEED=80000
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
@@ -57,6 +54,7 @@ CONFIG_MTD_RAW_NAND=y
CONFIG_MCFFEC=y
CONFIG_SYS_UNIFY_CACHE=y
CONFIG_MII=y
CONFIG_DM_RTC=y
CONFIG_MCFRTC=y
CONFIG_SYS_MCFRTC_BASE=0xFC0A8000
CONFIG_MCFUART=y

3
configs/M5373EVB_defconfig
View File

@@ -40,7 +40,8 @@ CONFIG_NETMASK="255.255.255.0"
CONFIG_USE_SERVERIP=y
CONFIG_SERVERIP="192.162.1.1"
CONFIG_SYS_RX_ETH_BUFFER=8
CONFIG_SYS_I2C_LEGACY=y
CONFIG_DM_I2C=y
CONFIG_DM_RTC=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_FSL_I2C_OFFSET=0x58000
CONFIG_SYS_I2C_SLAVE=0x7F

6
configs/astro_mcf5373l_defconfig
View File

@@ -34,11 +34,8 @@ CONFIG_FPGA_CYCLON2=y
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_SPARTAN3=y
CONFIG_SYS_FPGA_PROG_FEEDBACK=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_FSL_I2C_OFFSET=0x58000
CONFIG_SYS_I2C_SLAVE=0x7F
CONFIG_SYS_I2C_SPEED=80000
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_FLASH_SHOW_PROGRESS=0
@@ -46,6 +43,7 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_SYS_MAX_FLASH_SECT=259
CONFIG_DM_RTC=y
CONFIG_MCFRTC=y
CONFIG_SYS_MCFRTC_BASE=0xFC0A8000
CONFIG_MCFUART=y

5
configs/eb_cpu5282_defconfig
View File

@@ -34,10 +34,9 @@ CONFIG_CMD_DATE=y
CONFIG_OVERWRITE_ETHADDR_ONCE=y
CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
CONFIG_SYS_RX_ETH_BUFFER=8
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_FSL_I2C_OFFSET=0x300
CONFIG_SYS_I2C_SLAVE=0
CONFIG_DM_I2C=y
CONFIG_DM_RTC=y
CONFIG_LED_STATUS=y
CONFIG_LED_STATUS0=y
CONFIG_LED_STATUS_BIT=8

5
configs/eb_cpu5282_internal_defconfig
View File

@@ -32,10 +32,8 @@ CONFIG_CMD_DATE=y
CONFIG_OVERWRITE_ETHADDR_ONCE=y
CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
CONFIG_SYS_RX_ETH_BUFFER=8
CONFIG_SYS_I2C_LEGACY=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_FSL_I2C_OFFSET=0x300
CONFIG_SYS_I2C_SLAVE=0
CONFIG_LED_STATUS=y
CONFIG_LED_STATUS0=y
CONFIG_LED_STATUS_BIT=8
@@ -50,5 +48,6 @@ CONFIG_SYS_FLASH_CFI=y
CONFIG_SYS_MAX_FLASH_SECT=128
CONFIG_MCFFEC=y
CONFIG_MII=y
CONFIG_DM_RTC=y
CONFIG_RTC_DS1338=y
CONFIG_MCFUART=y

4
configs/stmark2_defconfig
View File

@@ -49,3 +49,7 @@ CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_CF_SPI=y
CONFIG_REGEX=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_DM_I2C=y
CONFIG_CMD_I2C=y
CONFIG_SYS_I2C_FSL=y

14
drivers/i2c/designware_i2c_pci.c
View File

@@ -147,9 +147,7 @@ static int dw_i2c_acpi_fill_ssdt(const struct udevice *dev,
{
struct dw_i2c_speed_config config;
char path[ACPI_PATH_MAX];
u32 speeds[4];
uint speed;
int size;
int ret;
/* If no device-tree node, ignore this since we assume it isn't used */
@@ -160,18 +158,6 @@ static int dw_i2c_acpi_fill_ssdt(const struct udevice *dev,
if (ret)
return log_msg_ret("path", ret);
size = dev_read_size(dev, "i2c,speeds");
if (size < 0)
return log_msg_ret("i2c,speeds", -EINVAL);
size /= sizeof(u32);
if (size > ARRAY_SIZE(speeds))
return log_msg_ret("array", -E2BIG);
ret = dev_read_u32_array(dev, "i2c,speeds", speeds, size);
if (ret)
return log_msg_ret("read", -E2BIG);
speed = dev_read_u32_default(dev, "clock-frequency", 100000);
acpigen_write_scope(ctx, path);
ret = dw_i2c_gen_speed_config(dev, speed, &config);

16
drivers/i2c/fsl_i2c.c
View File

@@ -278,7 +278,8 @@ static void __i2c_init(const struct fsl_i2c_base *base, int speed, int
set_i2c_bus_speed(base, i2c_clk, speed);
writeb(slaveadd << 1, &base->adr);/* write slave address */
writeb(0x0, &base->sr); /* clear status register */
writeb(I2C_CR_MEN, &base->cr); /* start I2C controller */
/* start I2C controller */
writeb(I2C_CR_MEN | I2C_CR_MIEN, &base->cr);
timeval = get_ticks();
while (readb(&base->sr) & I2C_SR_MBB) {
@@ -346,7 +347,7 @@ static int i2c_wait(const struct fsl_i2c_base *base, int write)
static int i2c_write_addr(const struct fsl_i2c_base *base, u8 dev,
u8 dir, int rsta)
{
writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX
writeb(I2C_CR_MEN | I2C_CR_MIEN | I2C_CR_MSTA | I2C_CR_MTX
| (rsta ? I2C_CR_RSTA : 0),
&base->cr);
@@ -378,7 +379,8 @@ static int __i2c_read_data(const struct fsl_i2c_base *base, u8 *data,
{
int i;
writeb(I2C_CR_MEN | I2C_CR_MSTA | ((length == 1) ? I2C_CR_TXAK : 0),
writeb(I2C_CR_MEN | I2C_CR_MIEN |
I2C_CR_MSTA | ((length == 1) ? I2C_CR_TXAK : 0),
&base->cr);
/* dummy read */
@@ -390,13 +392,13 @@ static int __i2c_read_data(const struct fsl_i2c_base *base, u8 *data,
/* Generate ack on last next to last byte */
if (i == length - 2)
writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_TXAK,
&base->cr);
writeb(I2C_CR_MEN | I2C_CR_MIEN | I2C_CR_MSTA |
I2C_CR_TXAK, &base->cr);
/* Do not generate stop on last byte */
if (i == length - 1)
writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX,
&base->cr);
writeb(I2C_CR_MEN | I2C_CR_MIEN | I2C_CR_MSTA |
I2C_CR_MTX, &base->cr);
data[i] = readb(&base->dr);
}

4
drivers/i2c/i2c-uclass.c
View File

@@ -508,13 +508,13 @@ static void i2c_gpio_set_pin(struct gpio_desc *pin, int bit)
dm_gpio_set_dir_flags(pin, GPIOD_IS_IN);
else
dm_gpio_set_dir_flags(pin, GPIOD_IS_OUT |
GPIOD_ACTIVE_LOW |
GPIOD_IS_OUT_ACTIVE);
}
static int i2c_gpio_get_pin(struct gpio_desc *pin)
{
return dm_gpio_get_value(pin);
/* DTS need config GPIO_ACTIVE_LOW */
return !dm_gpio_get_value(pin);
}
int i2c_deblock_gpio_loop(struct gpio_desc *sda_pin,

4
drivers/i2c/imx_lpi2c.c
View File

@@ -282,7 +282,7 @@ static int bus_i2c_set_bus_speed(struct udevice *bus, int speed)
bool mode;
int i;
if (IS_ENABLED(CONFIG_CLK)) {
if (CONFIG_IS_ENABLED(CLK)) {
clock_rate = clk_get_rate(&i2c_bus->per_clk);
if (clock_rate <= 0) {
dev_err(bus, "Failed to get i2c clk: %d\n", clock_rate);
@@ -462,7 +462,7 @@ static int imx_lpi2c_probe(struct udevice *bus)
return ret;
}
if (IS_ENABLED(CONFIG_CLK)) {
if (CONFIG_IS_ENABLED(CLK)) {
ret = clk_get_by_name(bus, "per", &i2c_bus->per_clk);
if (ret) {
dev_err(bus, "Failed to get per clk\n");

2
include/configs/stmark2.h
View File

@@ -97,4 +97,6 @@
#define CFG_MCFTMR
#define CFG_SYS_I2C_0
#endif /* __STMARK2_CONFIG_H */