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clk: rockchip: rk3568: Fix clk selection in rk3568_pwm_get_clk

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Fix use of wrong clk selection for CLK_PWM1 on RK3568.

Fixes: 4a262feba3 ("rockchip: rk3568: add clock driver")
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Damon Ding
2023-08-04 09:33:57 +00:00
committed by Kever Yang
parent 6e710897aa
commit acb9812034
1 changed files with 1 additions and 1 deletions
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2
drivers/clk/rockchip/clk_rk3568.c
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@@ -1142,7 +1142,7 @@ static ulong rk3568_pwm_get_clk(struct rk3568_clk_priv *priv, ulong clk_id)
switch (clk_id) {
case CLK_PWM1:
sel = (con & CLK_PWM1_SEL_MASK) >> CLK_PWM3_SEL_SHIFT;
sel = (con & CLK_PWM1_SEL_MASK) >> CLK_PWM1_SEL_SHIFT;
break;
case CLK_PWM2:
sel = (con & CLK_PWM2_SEL_MASK) >> CLK_PWM2_SEL_SHIFT;