power: pmic: pca9450: Add support for reset status

PCA9450 PMIC supports reading the reset status from the PWRON_STAT
register. Bits 7-4 give indication of the PMIC reset cause:

 - PWRON (BIT7) - Power ON triggered by PMIC_ON_REQ input line,
 - WDOGB (BIT6) - Boot after cold reset by WDOGB pin (watchdog reset),
 - SW_RST (BIT5) - Boot after cold reset initiated by the software,
 - PMIC_RST (BIT4) - Boot after PMIC_RST_B input line trigger.

Add support for reading reset status via the sysreset framework in a
convenient printable format.

Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
Reviewed-by: Paul Geurts <paul.geurts@prodrive-technologies.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
Primoz Fiser
2025-08-28 13:24:05 +02:00
committed by Peng Fan
parent 9065b87f35
commit ad197b31b3
2 changed files with 43 additions and 0 deletions

View File

@@ -146,8 +146,46 @@ static int pca9450_sysreset_request(struct udevice *dev, enum sysreset_t type)
return -EINPROGRESS;
}
int pca9450_sysreset_get_status(struct udevice *dev, char *buf, int size)
{
const char *reason;
int ret;
u8 reg;
ret = pmic_read(dev->parent, PCA9450_PWRON_STAT, &reg, 1);
if (ret)
return ret;
switch (reg) {
case PCA9450_PWRON_STAT_PWRON_MASK:
reason = "PWRON";
break;
case PCA9450_PWRON_STAT_WDOG_MASK:
reason = "WDOGB";
break;
case PCA9450_PWRON_STAT_SW_RST_MASK:
reason = "SW_RST";
break;
case PCA9450_PWRON_STAT_PMIC_RST_MASK:
reason = "PMIC_RST";
break;
default:
reason = "UNKNOWN";
break;
}
ret = snprintf(buf, size, "Reset Status: %s\n", reason);
if (ret < 0) {
dev_err(dev, "Write reset status error (err = %d)\n", ret);
return -EIO;
}
return 0;
}
static struct sysreset_ops pca9450_sysreset_ops = {
.request = pca9450_sysreset_request,
.get_status = pca9450_sysreset_get_status,
};
U_BOOT_DRIVER(pca9450_sysreset) = {

View File

@@ -75,6 +75,11 @@ enum {
#define PCA9450_PMIC_RESET_WDOG_B_CFG_WARM 0x40
#define PCA9450_PMIC_RESET_WDOG_B_CFG_COLD_LDO12 0x80
#define PCA9450_PWRON_STAT_PWRON_MASK 0x80
#define PCA9450_PWRON_STAT_WDOG_MASK 0x40
#define PCA9450_PWRON_STAT_SW_RST_MASK 0x20
#define PCA9450_PWRON_STAT_PMIC_RST_MASK 0x10
#define PCA9450_SW_RST_COLD_RST 0x14
#endif