mirror of
https://source.denx.de/u-boot/u-boot.git
synced 2026-06-13 15:03:58 +03:00
Merge patch series "omap3: igep0x00: Fix boot failure and modernize the boards support"
Javier Martinez Canillas <javier@dowhile0.org> says: Hello, I noticed that the IGEPv2 board did not boot anymore with mainline U-Boot. This was caused by a driver change to allocate its platform data before relocation and U-Boot not having enough pre-relocation heap size for this. This series fixes this issue and also makes the board support more modern, by enabling DM for SPL and migrating the IGEP boards to use upstream DTBs.
This commit is contained in:
Tom Rini
@@ -1027,9 +1027,6 @@ dtb-$(CONFIG_TARGET_OMAP3_BEAGLE) += \
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dtb-$(CONFIG_TARGET_DEVKIT8000) += omap3-devkit8000.dtb
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dtb-$(CONFIG_TARGET_OMAP3_IGEP00X0) += \
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omap3-igep0020.dtb
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dtb-$(CONFIG_TARGET_OMAP4_PANDA) += \
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omap4-panda.dtb \
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omap4-panda-es.dtb
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@@ -1,247 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Common device tree for IGEP boards based on AM/DM37x
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*
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* Copyright (C) 2012 Javier Martinez Canillas <javier@dowhile0.org>
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* Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com>
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*/
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/dts-v1/;
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#include "omap36xx.dtsi"
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/ {
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memory@80000000 {
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device_type = "memory";
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reg = <0x80000000 0x20000000>; /* 512 MB */
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};
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chosen {
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stdout-path = &uart3;
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};
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sound {
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compatible = "ti,omap-twl4030";
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ti,model = "igep2";
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ti,mcbsp = <&mcbsp2>;
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};
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vdd33: regulator-vdd33 {
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compatible = "regulator-fixed";
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regulator-name = "vdd33";
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regulator-always-on;
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};
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};
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&omap3_pmx_core {
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gpmc_pins: pinmux_gpmc_pins {
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pinctrl-single,pins = <
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/* OneNAND seems to require PIN_INPUT on clock. */
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OMAP3_CORE1_IOPAD(0x20be, PIN_INPUT | MUX_MODE0) /* gpmc_clk.gpmc_clk */
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>;
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};
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uart1_pins: pinmux_uart1_pins {
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pinctrl-single,pins = <
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OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */
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OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_tx */
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>;
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};
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uart3_pins: pinmux_uart3_pins {
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pinctrl-single,pins = <
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OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx.uart3_rx */
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OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx.uart3_tx */
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>;
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};
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mcbsp2_pins: pinmux_mcbsp2_pins {
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pinctrl-single,pins = <
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OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx.mcbsp2_fsx */
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OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0) /* mcbsp2_clkx.mcbsp2_clkx */
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OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0) /* mcbsp2_dr.mcbsp2.dr */
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OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0) /* mcbsp2_dx.mcbsp2_dx */
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>;
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};
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mmc1_pins: pinmux_mmc1_pins {
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pinctrl-single,pins = <
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OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */
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OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */
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OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */
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OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */
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OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */
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OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */
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>;
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};
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mmc2_pins: pinmux_mmc2_pins {
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pinctrl-single,pins = <
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OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */
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OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */
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OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */
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OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */
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OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */
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OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */
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>;
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};
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i2c1_pins: pinmux_i2c1_pins {
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pinctrl-single,pins = <
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OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
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OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */
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>;
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};
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i2c3_pins: pinmux_i2c3_pins {
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pinctrl-single,pins = <
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OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl.i2c3_scl */
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OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda.i2c3_sda */
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>;
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};
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};
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&gpmc {
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pinctrl-names = "default";
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pinctrl-0 = <&gpmc_pins>;
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nand@0,0 {
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compatible = "ti,omap2-nand";
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reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
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interrupt-parent = <&gpmc>;
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interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
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<1 IRQ_TYPE_NONE>; /* termcount */
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linux,mtd-name = "micron,mt29c4g96maz";
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nand-bus-width = <16>;
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gpmc,device-width = <2>;
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ti,nand-ecc-opt = "bch8";
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gpmc,sync-clk-ps = <0>;
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gpmc,cs-on-ns = <0>;
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gpmc,cs-rd-off-ns = <44>;
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gpmc,cs-wr-off-ns = <44>;
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gpmc,adv-on-ns = <6>;
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gpmc,adv-rd-off-ns = <34>;
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gpmc,adv-wr-off-ns = <44>;
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gpmc,we-off-ns = <40>;
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gpmc,oe-off-ns = <54>;
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gpmc,access-ns = <64>;
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gpmc,rd-cycle-ns = <82>;
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gpmc,wr-cycle-ns = <82>;
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gpmc,wr-access-ns = <40>;
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gpmc,wr-data-mux-bus-ns = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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status = "okay";
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};
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onenand@0,0 {
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compatible = "ti,omap2-onenand";
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reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */
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gpmc,sync-read;
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gpmc,sync-write;
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gpmc,burst-length = <16>;
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gpmc,burst-wrap;
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gpmc,burst-read;
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gpmc,burst-write;
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gpmc,device-width = <2>; /* GPMC_DEVWIDTH_16BIT */
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gpmc,mux-add-data = <2>; /* GPMC_MUX_AD */
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gpmc,cs-on-ns = <0>;
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gpmc,cs-rd-off-ns = <96>;
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gpmc,cs-wr-off-ns = <96>;
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gpmc,adv-on-ns = <0>;
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gpmc,adv-rd-off-ns = <12>;
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gpmc,adv-wr-off-ns = <12>;
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gpmc,oe-on-ns = <18>;
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gpmc,oe-off-ns = <96>;
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gpmc,we-on-ns = <0>;
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gpmc,we-off-ns = <96>;
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gpmc,rd-cycle-ns = <114>;
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gpmc,wr-cycle-ns = <114>;
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gpmc,access-ns = <90>;
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gpmc,page-burst-access-ns = <12>;
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gpmc,bus-turnaround-ns = <0>;
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gpmc,cycle2cycle-delay-ns = <0>;
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gpmc,wait-monitoring-ns = <0>;
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gpmc,clk-activation-ns = <6>;
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gpmc,wr-data-mux-bus-ns = <30>;
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gpmc,wr-access-ns = <90>;
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gpmc,sync-clk-ps = <12000>;
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#address-cells = <1>;
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#size-cells = <1>;
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status = "disabled";
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};
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};
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&i2c1 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c1_pins>;
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clock-frequency = <2600000>;
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twl: twl@48 {
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reg = <0x48>;
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interrupts = <7>; /* SYS_NIRQ cascaded to intc */
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interrupt-parent = <&intc>;
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twl_audio: audio {
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compatible = "ti,twl4030-audio";
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codec {
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};
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};
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};
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};
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#include "twl4030.dtsi"
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#include "twl4030_omap3.dtsi"
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&i2c3 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c3_pins>;
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};
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&mcbsp2 {
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pinctrl-names = "default";
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pinctrl-0 = <&mcbsp2_pins>;
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status = "okay";
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};
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&mmc1 {
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pinctrl-names = "default";
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pinctrl-0 = <&mmc1_pins>;
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vmmc-supply = <&vmmc1>;
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vmmc_aux-supply = <&vsim>;
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bus-width = <4>;
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cd-gpios = <&twl_gpio 0 GPIO_ACTIVE_LOW>;
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};
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&mmc3 {
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status = "disabled";
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};
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart1_pins>;
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};
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&uart3 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart3_pins>;
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};
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&twl_gpio {
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ti,use-leds;
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};
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&usb_otg_hs {
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interface-type = <0>;
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usb-phy = <&usb2_phy>;
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phys = <&usb2_phy>;
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phy-names = "usb2-phy";
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mode = <3>;
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power = <50>;
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};
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@@ -1,261 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Common Device Tree Source for IGEPv2
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*
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* Copyright (C) 2014 Javier Martinez Canillas <javier@dowhile0.org>
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* Copyright (C) 2014 Enric Balletbo i Serra <eballetbo@gmail.com>
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*/
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#include "omap3-igep.dtsi"
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#include "omap-gpmc-smsc9221.dtsi"
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/ {
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leds {
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pinctrl-names = "default";
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pinctrl-0 = <&leds_pins>;
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compatible = "gpio-leds";
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boot {
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label = "omap3:green:boot";
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gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
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default-state = "on";
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};
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user0 {
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label = "omap3:red:user0";
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gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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user1 {
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label = "omap3:red:user1";
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gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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user2 {
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label = "omap3:green:user1";
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gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>;
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};
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};
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/* HS USB Port 1 Power */
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hsusb1_power: hsusb1_power_reg {
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compatible = "regulator-fixed";
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regulator-name = "hsusb1_vbus";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* GPIO LEDA */
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startup-delay-us = <70000>;
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};
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/* HS USB Host PHY on PORT 1 */
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hsusb1_phy: hsusb1_phy {
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compatible = "usb-nop-xceiv";
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reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; /* gpio_24 */
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vcc-supply = <&hsusb1_power>;
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#phy-cells = <0>;
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};
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tfp410: encoder {
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compatible = "ti,tfp410";
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powerdown-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; /* gpio_170 */
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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tfp410_in: endpoint {
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remote-endpoint = <&dpi_out>;
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};
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};
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port@1 {
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reg = <1>;
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tfp410_out: endpoint {
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remote-endpoint = <&dvi_connector_in>;
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};
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};
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};
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};
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dvi0: connector {
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compatible = "dvi-connector";
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label = "dvi";
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digital;
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ddc-i2c-bus = <&i2c3>;
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port {
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dvi_connector_in: endpoint {
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remote-endpoint = <&tfp410_out>;
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};
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};
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};
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};
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&omap3_pmx_core {
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pinctrl-names = "default";
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pinctrl-0 = <
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&tfp410_pins
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&dss_dpi_pins
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>;
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tfp410_pins: pinmux_tfp410_pins {
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pinctrl-single,pins = <
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OMAP3_CORE1_IOPAD(0x21c6, PIN_OUTPUT | MUX_MODE4) /* hdq_sio.gpio_170 */
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>;
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};
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dss_dpi_pins: pinmux_dss_dpi_pins {
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pinctrl-single,pins = <
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OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */
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OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */
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OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */
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OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */
|
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OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */
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OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */
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OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */
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OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */
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OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */
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OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */
|
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OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */
|
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OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */
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OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */
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OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */
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OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */
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OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */
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OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */
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OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */
|
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OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */
|
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OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */
|
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OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */
|
||||
OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */
|
||||
OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */
|
||||
OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */
|
||||
OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */
|
||||
OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */
|
||||
OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */
|
||||
OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */
|
||||
>;
|
||||
};
|
||||
|
||||
uart2_pins: pinmux_uart2_pins {
|
||||
pinctrl-single,pins = <
|
||||
OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT | MUX_MODE0) /* uart2_cts.uart2_cts */
|
||||
OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts .uart2_rts*/
|
||||
OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */
|
||||
OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */
|
||||
>;
|
||||
};
|
||||
|
||||
smsc9221_pins: pinmux_smsc9221_pins {
|
||||
pinctrl-single,pins = <
|
||||
OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT | MUX_MODE4) /* mcspi1_cs2.gpio_176 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&omap3_pmx_core2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <
|
||||
&hsusbb1_pins
|
||||
>;
|
||||
|
||||
hsusbb1_pins: pinmux_hsusbb1_pins {
|
||||
pinctrl-single,pins = <
|
||||
OMAP3630_CORE2_IOPAD(0x25da, PIN_OUTPUT | MUX_MODE3) /* etk_ctl.hsusb1_clk */
|
||||
OMAP3630_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE3) /* etk_clk.hsusb1_stp */
|
||||
OMAP3630_CORE2_IOPAD(0x25ec, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d8.hsusb1_dir */
|
||||
OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d9.hsusb1_nxt */
|
||||
OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d0.hsusb1_data0 */
|
||||
OMAP3630_CORE2_IOPAD(0x25de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d1.hsusb1_data1 */
|
||||
OMAP3630_CORE2_IOPAD(0x25e0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d2.hsusb1_data2 */
|
||||
OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d3.hsusb1_data7 */
|
||||
OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d4.hsusb1_data4 */
|
||||
OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d5.hsusb1_data5 */
|
||||
OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d6.hsusb1_data6 */
|
||||
OMAP3630_CORE2_IOPAD(0x25ea, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d7.hsusb1_data3 */
|
||||
>;
|
||||
};
|
||||
|
||||
leds_pins: pinmux_leds_pins {
|
||||
pinctrl-single,pins = <
|
||||
OMAP3630_CORE2_IOPAD(0x25f4, PIN_OUTPUT | MUX_MODE4) /* etk_d12.gpio_26 */
|
||||
OMAP3630_CORE2_IOPAD(0x25f6, PIN_OUTPUT | MUX_MODE4) /* etk_d13.gpio_27 */
|
||||
OMAP3630_CORE2_IOPAD(0x25f8, PIN_OUTPUT | MUX_MODE4) /* etk_d14.gpio_28 */
|
||||
>;
|
||||
};
|
||||
|
||||
mmc1_wp_pins: pinmux_mmc1_cd_pins {
|
||||
pinctrl-single,pins = <
|
||||
OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT | MUX_MODE4) /* etk_d15.gpio_29 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
clock-frequency = <100000>;
|
||||
|
||||
/*
|
||||
* Display monitor features are burnt in the EEPROM
|
||||
* as EDID data.
|
||||
*/
|
||||
eeprom@50 {
|
||||
compatible = "ti,eeprom";
|
||||
reg = <0x50>;
|
||||
};
|
||||
};
|
||||
|
||||
&gpmc {
|
||||
ranges = <0 0 0x30000000 0x01000000>, /* CS0: 16MB for NAND */
|
||||
<5 0 0x2c000000 0x01000000>; /* CS5: 16MB for ethernet */
|
||||
|
||||
ethernet@gpmc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&smsc9221_pins>;
|
||||
reg = <5 0 0xff>;
|
||||
interrupt-parent = <&gpio6>;
|
||||
interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart2_pins>;
|
||||
};
|
||||
|
||||
&usbhshost {
|
||||
port1-mode = "ehci-phy";
|
||||
};
|
||||
|
||||
&usbhsehci {
|
||||
phys = <&hsusb1_phy>;
|
||||
};
|
||||
|
||||
&vpll2 {
|
||||
/* Needed for DSS */
|
||||
regulator-name = "vdds_dsi";
|
||||
};
|
||||
|
||||
&dss {
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
dpi_out: endpoint {
|
||||
remote-endpoint = <&tfp410_in>;
|
||||
data-lines = <24>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mmc1 {
|
||||
pinctrl-0 = <&mmc1_pins &mmc1_wp_pins>;
|
||||
wp-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; /* gpio_29 */
|
||||
};
|
||||
@@ -5,20 +5,10 @@
|
||||
* (C) Copyright 2017 Derald D. Woods <woods.technical@gmail.com>
|
||||
*/
|
||||
|
||||
#include "omap3-u-boot.dtsi"
|
||||
|
||||
/ {
|
||||
chosen {
|
||||
stdout-path = &uart3;
|
||||
};
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
reg-shift = <2>;
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
reg-shift = <2>;
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
reg-shift = <2>;
|
||||
};
|
||||
|
||||
@@ -1,47 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Device Tree Source for IGEPv2 Rev. C (TI OMAP AM/DM37x)
|
||||
*
|
||||
* Copyright (C) 2012 Javier Martinez Canillas <javier@dowhile0.org>
|
||||
* Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com>
|
||||
*/
|
||||
|
||||
#include "omap3-igep0020-common.dtsi"
|
||||
|
||||
/ {
|
||||
model = "IGEPv2 Rev. C (TI OMAP AM/DM37x)";
|
||||
compatible = "isee,omap3-igep0020", "ti,omap36xx", "ti,omap3";
|
||||
|
||||
vmmcsdio_fixed: fixedregulator-mmcsdio {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vmmcsdio_fixed";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
mmc2_pwrseq: mmc2_pwrseq {
|
||||
compatible = "mmc-pwrseq-simple";
|
||||
reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>, /* gpio_139 - RESET_N_W */
|
||||
<&gpio5 10 GPIO_ACTIVE_LOW>; /* gpio_138 - WIFI_PDN */
|
||||
};
|
||||
};
|
||||
|
||||
&omap3_pmx_core {
|
||||
lbee1usjyc_pins: pinmux_lbee1usjyc_pins {
|
||||
pinctrl-single,pins = <
|
||||
OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat5.gpio_137 - RESET_N_W */
|
||||
OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat6.gpio_138 - WIFI_PDN */
|
||||
OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 - RST_N_B */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
/* On board Wifi module */
|
||||
&mmc2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mmc2_pins &lbee1usjyc_pins>;
|
||||
vmmc-supply = <&vmmcsdio_fixed>;
|
||||
mmc-pwrseq = <&mmc2_pwrseq>;
|
||||
bus-width = <4>;
|
||||
non-removable;
|
||||
};
|
||||
@@ -29,18 +29,6 @@
|
||||
#include <fdt_support.h>
|
||||
#include "igep00x0.h"
|
||||
|
||||
static const struct ns16550_plat igep_serial = {
|
||||
.base = OMAP34XX_UART3,
|
||||
.reg_shift = 2,
|
||||
.clock = V_NS16550_CLK,
|
||||
.fcr = UART_FCR_DEFVAL,
|
||||
};
|
||||
|
||||
U_BOOT_DRVINFO(igep_uart) = {
|
||||
"ns16550_serial",
|
||||
&igep_serial
|
||||
};
|
||||
|
||||
/*
|
||||
* Routine: get_board_revision
|
||||
* Description: GPIO_28 and GPIO_129 are used to read board and revision from
|
||||
|
||||
@@ -1,15 +1,18 @@
|
||||
CONFIG_ARM=y
|
||||
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
|
||||
# CONFIG_SPL_USE_ARCH_MEMSET is not set
|
||||
CONFIG_ARCH_OMAP2PLUS=y
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x400
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x4000
|
||||
CONFIG_TI_COMMON_CMD_OPTIONS=y
|
||||
CONFIG_NR_DRAM_BANKS=2
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4020ff00
|
||||
CONFIG_ENV_SIZE=0x8000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="omap3-igep0020"
|
||||
CONFIG_DEFAULT_DEVICE_TREE="ti/omap/omap3-igep0020"
|
||||
CONFIG_SPL_TEXT_BASE=0x40200000
|
||||
CONFIG_TARGET_OMAP3_IGEP00X0=y
|
||||
CONFIG_SYS_MONITOR_LEN=262144
|
||||
CONFIG_SPL_SYS_MALLOC_F_LEN=0x400
|
||||
CONFIG_SPL=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_BOOTDELAY=3
|
||||
@@ -39,16 +42,7 @@ CONFIG_SPL_UBI_LEB_START=2048
|
||||
CONFIG_SPL_UBI_INFO_ADDR=0x88080000
|
||||
CONFIG_SPL_UBI_VOL_IDS=8
|
||||
CONFIG_SPL_UBI_LOAD_MONITOR_ID=0
|
||||
CONFIG_SPL_UBI_LOAD_KERNEL_ID=3
|
||||
CONFIG_SPL_UBI_LOAD_ARGS_ID=4
|
||||
CONFIG_SPL_ONENAND_SUPPORT=y
|
||||
CONFIG_SPL_OS_BOOT=y
|
||||
CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x84000000
|
||||
CONFIG_SYS_NAND_SPL_KERNEL_OFFS=0x280000
|
||||
CONFIG_SPL_FALCON_BOOT_MMCSD=y
|
||||
CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x1700
|
||||
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x1500
|
||||
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x200
|
||||
CONFIG_CMD_SPL=y
|
||||
CONFIG_CMD_NAND=y
|
||||
CONFIG_CMD_ONENAND=y
|
||||
@@ -58,7 +52,12 @@ CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_MTDPARTS=y
|
||||
CONFIG_CMD_UBI=y
|
||||
# CONFIG_CMD_UBIFS is not set
|
||||
# CONFIG_SPL_EFI_PARTITION is not set
|
||||
CONFIG_SPL_PARTITION_UUIDS=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_OF_UPSTREAM=y
|
||||
CONFIG_OF_SPL_REMOVE_PROPS="clocks clock-names interrupt-parent"
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_UBI=y
|
||||
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
|
||||
@@ -68,6 +67,7 @@ CONFIG_ENV_UBI_VOLUME_REDUND="config_r"
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_VERSION_VARIABLE=y
|
||||
# CONFIG_NET is not set
|
||||
CONFIG_SPL_DM=y
|
||||
CONFIG_SYS_I2C_LEGACY=y
|
||||
CONFIG_SPL_SYS_I2C_LEGACY=y
|
||||
CONFIG_MMC_OMAP_HS=y
|
||||
@@ -80,8 +80,6 @@ CONFIG_SYS_NAND_PAGE_SIZE=0x800
|
||||
CONFIG_SYS_NAND_OOBSIZE=0x40
|
||||
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
|
||||
CONFIG_MTD_UBI_FASTMAP=y
|
||||
CONFIG_SPECIFY_CONSOLE_INDEX=y
|
||||
CONFIG_CONS_INDEX=3
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_OMAP3_SPI=y
|
||||
CONFIG_BCH=y
|
||||
|
||||
Reference in New Issue
Block a user