Merge tag 'u-boot-at91-2026.01-a' of https://source.denx.de/u-boot/custodians/u-boot-at91

First set of u-boot-at91 features for the 2026.01 cycle:

This small fixes set includes a change on clocks register value and a
fix for the sam9x60ek default timer.

arch/arm/dts/sam9x60ek-u-boot.dtsi

@@ -8,6 +8,7 @@
 / {
 	chosen {
 		bootph-all;
+		tick-timer = &pit;
 	};
 
 	ahb {

drivers/clk/at91/clk-sam9x60-pll.c

@@ -183,11 +183,8 @@ static int sam9x60_frac_pll_enable(struct clk *clk)
 			AT91_PMC_PLL_UPDT_ID_MSK,
 			AT91_PMC_PLL_UPDT_STUPTIM(0x3f) | pll->id);
 
-	/* Recommended value for AT91_PMC_PLL_ACR */
-	if (pll->characteristics->upll)
-		val = AT91_PMC_PLL_ACR_DEFAULT_UPLL;
-	else
-		val = AT91_PMC_PLL_ACR_DEFAULT_PLLA;
+	/* Load recommended value for PMC_PLL_ACR */
+	val = pll->characteristics->acr;
 	pmc_write(base, AT91_PMC_PLL_ACR, val);
 
 	if (pll->characteristics->upll) {

drivers/clk/at91/pmc.h

@@ -42,6 +42,7 @@ struct clk_pll_characteristics {
 	u16 *icpll;
 	u8 *out;
 	u8 upll : 1;
+	u32 acr;
 };
 
 struct clk_pll_layout {

drivers/clk/at91/sam9x60.c

@@ -123,6 +123,7 @@ static const struct clk_pll_characteristics apll_characteristics = {
 	.num_output = ARRAY_SIZE(plla_outputs),
 	.output = plla_outputs,
 	.core_output = core_outputs,
+	.acr = 0x00020010UL,
 };
 
 static const struct clk_pll_characteristics upll_characteristics = {
@@ -131,6 +132,7 @@ static const struct clk_pll_characteristics upll_characteristics = {
 	.output = upll_outputs,
 	.core_output = core_outputs,
 	.upll = true,
+	.acr = 0x12023010UL, /* fIN = [18 MHz, 32 MHz]*/
 };
 
 /* Layout for fractional PLLs. */

drivers/clk/at91/sam9x7.c

@@ -164,6 +164,7 @@ static const struct clk_pll_characteristics plla_characteristics = {
 	.num_output = ARRAY_SIZE(plla_outputs),
 	.output = plla_outputs,
 	.core_output = plla_core_outputs,
+	.acr = 0x00020010UL, /* Old ACR_DEFAULT_PLLA value */
 };
 
 static const struct clk_pll_characteristics upll_characteristics = {
@@ -172,6 +173,7 @@ static const struct clk_pll_characteristics upll_characteristics = {
 	.output = upll_outputs,
 	.core_output = upll_core_outputs,
 	.upll = true,
+	.acr = 0x12023010UL, /* fIN=[20 MHz, 32 MHz] */
 };
 
 static const struct clk_pll_characteristics lvdspll_characteristics = {
@@ -179,6 +181,7 @@ static const struct clk_pll_characteristics lvdspll_characteristics = {
 	.num_output = ARRAY_SIZE(lvdspll_outputs),
 	.output = lvdspll_outputs,
 	.core_output = lvdspll_core_outputs,
+	.acr = 0x12023010UL, /* fIN=[20 MHz, 32 MHz] */
 };
 
 static const struct clk_pll_characteristics audiopll_characteristics = {
@@ -186,6 +189,7 @@ static const struct clk_pll_characteristics audiopll_characteristics = {
 	.num_output = ARRAY_SIZE(audiopll_outputs),
 	.output = audiopll_outputs,
 	.core_output = audiopll_core_outputs,
+	.acr = 0x12023010UL, /* fIN=[20 MHz, 32 MHz] */
 };
 
 static const struct clk_pll_characteristics plladiv2_characteristics = {
@@ -193,6 +197,7 @@ static const struct clk_pll_characteristics plladiv2_characteristics = {
 	.num_output = ARRAY_SIZE(plladiv2_outputs),
 	.output = plladiv2_outputs,
 	.core_output = plladiv2_core_outputs,
+	.acr = 0x00020010UL,  /* Old ACR_DEFAULT_PLLA value */
 };
 
 /* Layout for fractional PLLs. */

drivers/clk/at91/sama7d65.c

@@ -184,6 +184,7 @@ static const struct clk_pll_characteristics pll_characteristics = {
 	.num_output = ARRAY_SIZE(pll_outputs),
 	.output = pll_outputs,
 	.core_output = core_outputs,
+	.acr = 0x00070010UL,
 };
 
 /* Layout for fractional PLLs. */

drivers/clk/at91/sama7g5.c

@@ -169,6 +169,7 @@ static const struct clk_pll_characteristics pll_characteristics = {
 	.num_output = ARRAY_SIZE(pll_outputs),
 	.output = pll_outputs,
 	.core_output = core_outputs,
+	.acr = 0x00070010UL,
 };
 
 /* Layout for fractional PLLs. */

include/linux/clk/at91_pmc.h

@@ -45,8 +45,6 @@
 #define	AT91_PMC_PCSR		0x18			/* Peripheral Clock Status Register */
 
 #define AT91_PMC_PLL_ACR	0x18			/* PLL Analog Control Register [for SAM9X60] */
-#define		AT91_PMC_PLL_ACR_DEFAULT_UPLL	0x12020010UL	/* Default PLL ACR value for UPLL */
-#define		AT91_PMC_PLL_ACR_DEFAULT_PLLA	0x00020010UL	/* Default PLL ACR value for PLLA */
 #define		AT91_PMC_PLL_ACR_UTMIVR		(1 << 12)	/* UPLL Voltage regulator Control */
 #define		AT91_PMC_PLL_ACR_UTMIBG		(1 << 13)	/* UPLL Bandgap Control */