mirror of
https://source.denx.de/u-boot/u-boot.git
synced 2026-06-13 15:03:58 +03:00
Merge tag 'u-boot-rockchip-20250110' of https://source.denx.de/u-boot/custodians/u-boot-rockchip
CI: https://source.denx.de/u-boot/custodians/u-boot-rockchip/-/pipelines/24129 - Add boards: rk3566: FriendlyARM NanoPi R3S rk3588s: Radxa ROCK 5C, rk3588: Khadas Edge2 - Migrate to OF_UPSTREAM: rk3066a/rk3188; rk3288: tinker, miqi, firefly; - Migrate to TPL: rk3399 kevin and bob;
This commit is contained in:
Tom Rini
@@ -55,27 +55,17 @@ dtb-$(CONFIG_MACH_S700) += \
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dtb-$(CONFIG_ROCKCHIP_RK3036) += \
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rk3036-sdk.dtb
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dtb-$(CONFIG_ROCKCHIP_RK3066) += \
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rk3066a-mk808.dtb
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dtb-$(CONFIG_ROCKCHIP_RK3128) += \
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rk3128-evb.dtb
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dtb-$(CONFIG_ROCKCHIP_RK3188) += \
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rk3188-radxarock.dtb
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dtb-$(CONFIG_ROCKCHIP_RK322X) += \
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rk3229-evb.dtb
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dtb-$(CONFIG_ROCKCHIP_RK3288) += \
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rk3288-evb.dtb \
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rk3288-firefly.dtb \
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rk3288-miqi.dtb \
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rk3288-popmetal.dtb \
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rk3288-rock2-square.dtb \
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rk3288-rock-pi-n8.dtb \
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rk3288-tinker.dtb \
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rk3288-tinker-s.dtb \
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rk3288-veyron-jerry.dtb \
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rk3288-veyron-mickey.dtb \
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rk3288-veyron-minnie.dtb \
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@@ -1,241 +0,0 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2016 Paweł Jarosz <paweljarosz3691@gmail.com>
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*/
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/dts-v1/;
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#include <dt-bindings/input/input.h>
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#include "rk3066a.dtsi"
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/ {
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model = "Rikomagic MK808";
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compatible = "rikomagic,mk808", "rockchip,rk3066a";
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aliases {
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mmc0 = &mmc0;
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mmc1 = &mmc1;
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};
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chosen {
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stdout-path = "serial2:115200n8";
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};
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memory@60000000 {
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reg = <0x60000000 0x40000000>;
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device_type = "memory";
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};
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adc-keys {
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compatible = "adc-keys";
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io-channels = <&saradc 1>;
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io-channel-names = "buttons";
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keyup-threshold-microvolt = <2500000>;
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poll-interval = <100>;
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button-recovery {
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label = "recovery";
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linux,code = <KEY_VENDOR>;
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press-threshold-microvolt = <0>;
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};
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};
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gpio-leds {
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compatible = "gpio-leds";
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blue_led: led-0 {
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label = "mk808:blue:power";
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gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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linux,default-trigger = "default-on";
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};
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};
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hdmi_con {
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compatible = "hdmi-connector";
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type = "c";
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port {
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hdmi_con_in: endpoint {
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remote-endpoint = <&hdmi_out_con>;
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};
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};
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};
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vcc_2v5: vcc-2v5 {
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compatible = "regulator-fixed";
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regulator-name = "vcc_2v5";
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regulator-min-microvolt = <2500000>;
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regulator-max-microvolt = <2500000>;
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};
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vcc_io: vcc-io {
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compatible = "regulator-fixed";
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regulator-name = "vcc_io";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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vcc_host: usb-host-regulator {
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compatible = "regulator-fixed";
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enable-active-high;
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gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
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pinctrl-0 = <&host_drv>;
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pinctrl-names = "default";
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regulator-always-on;
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regulator-name = "host-pwr";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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startup-delay-us = <100000>;
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vin-supply = <&vcc_io>;
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};
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vcc_otg: usb-otg-regulator {
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compatible = "regulator-fixed";
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enable-active-high;
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gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
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pinctrl-0 = <&otg_drv>;
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pinctrl-names = "default";
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regulator-always-on;
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regulator-name = "vcc_otg";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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startup-delay-us = <100000>;
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vin-supply = <&vcc_io>;
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};
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vcc_sd: sdmmc-regulator {
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compatible = "regulator-fixed";
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gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>;
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pinctrl-0 = <&sdmmc_pwr>;
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pinctrl-names = "default";
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regulator-name = "vcc_sd";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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startup-delay-us = <100000>;
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vin-supply = <&vcc_io>;
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};
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vcc_wifi: sdio-regulator {
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compatible = "regulator-fixed";
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enable-active-high;
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gpio = <&gpio3 RK_PD0 GPIO_ACTIVE_HIGH>;
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pinctrl-0 = <&wifi_pwr>;
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pinctrl-names = "default";
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regulator-name = "vcc_wifi";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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startup-delay-us = <100000>;
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vin-supply = <&vcc_io>;
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};
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};
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&hdmi {
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status = "okay";
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};
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&hdmi_in_vop1 {
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status = "disabled";
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};
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&hdmi_out {
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hdmi_out_con: endpoint {
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remote-endpoint = <&hdmi_con_in>;
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};
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};
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&mmc0 {
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bus-width = <4>;
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cap-mmc-highspeed;
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cap-sd-highspeed;
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vmmc-supply = <&vcc_sd>;
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status = "okay";
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};
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&mmc1 {
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bus-width = <4>;
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non-removable;
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pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus4>;
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pinctrl-names = "default";
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vmmc-supply = <&vcc_wifi>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "okay";
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brcmf: wifi@1 {
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compatible = "brcm,bcm4329-fmac";
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reg = <1>;
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};
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};
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&nfc {
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#address-cells = <1>;
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#size-cells = <0>;
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status = "okay";
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nand@0 {
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reg = <0>;
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label = "rk-nand";
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nand-bus-width = <8>;
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nand-ecc-mode = "hw";
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nand-ecc-step-size = <1024>;
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nand-ecc-strength = <40>;
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nand-is-boot-medium;
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rockchip,boot-blks = <8>;
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rockchip,boot-ecc-strength = <24>;
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};
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};
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&pinctrl {
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usb-host {
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host_drv: host-drv {
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rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_default>;
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};
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};
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usb-otg {
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otg_drv: otg-drv {
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rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_default>;
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};
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};
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sdmmc {
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sdmmc_pwr: sdmmc-pwr {
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rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_default>;
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};
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};
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sdio {
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wifi_pwr: wifi-pwr {
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rockchip,pins = <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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};
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&saradc {
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vref-supply = <&vcc_2v5>;
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status = "okay";
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};
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&uart2 {
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status = "okay";
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};
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&usb_host {
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status = "okay";
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};
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&usb_otg {
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status = "okay";
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};
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&usbphy {
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status = "okay";
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};
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&vop0 {
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status = "okay";
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};
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&wdt {
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status = "okay";
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};
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@@ -3,26 +3,6 @@
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#include "rockchip-u-boot.dtsi"
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#include "rk3xxx-u-boot.dtsi"
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&gpio0 {
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gpio-ranges = <&pinctrl 0 0 32>;
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};
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&gpio1 {
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gpio-ranges = <&pinctrl 0 32 32>;
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};
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&gpio2 {
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gpio-ranges = <&pinctrl 0 64 32>;
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};
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&gpio3 {
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gpio-ranges = <&pinctrl 0 96 32>;
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};
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&gpio4 {
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gpio-ranges = <&pinctrl 0 128 32>;
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};
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&gpio6 {
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status = "disabled";
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};
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@@ -1,880 +0,0 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2013 MundoReader S.L.
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* Author: Heiko Stuebner <heiko@sntech.de>
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/pinctrl/rockchip.h>
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#include <dt-bindings/clock/rk3066a-cru.h>
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#include <dt-bindings/power/rk3066-power.h>
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#include "rk3xxx.dtsi"
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/ {
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compatible = "rockchip,rk3066a";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "rockchip,rk3066-smp";
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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next-level-cache = <&L2>;
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reg = <0x0>;
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operating-points =
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/* kHz uV */
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<1416000 1300000>,
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<1200000 1175000>,
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<1008000 1125000>,
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<816000 1125000>,
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<600000 1100000>,
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<504000 1100000>,
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<312000 1075000>;
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clock-latency = <40000>;
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clocks = <&cru ARMCLK>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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next-level-cache = <&L2>;
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reg = <0x1>;
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};
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};
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display-subsystem {
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compatible = "rockchip,display-subsystem";
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ports = <&vop0_out>, <&vop1_out>;
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};
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||||
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sram: sram@10080000 {
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compatible = "mmio-sram";
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||||
reg = <0x10080000 0x10000>;
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#address-cells = <1>;
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||||
#size-cells = <1>;
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ranges = <0 0x10080000 0x10000>;
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||||
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smp-sram@0 {
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compatible = "rockchip,rk3066-smp-sram";
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reg = <0x0 0x50>;
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||||
};
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||||
};
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||||
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||||
vop0: vop@1010c000 {
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compatible = "rockchip,rk3066-vop";
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||||
reg = <0x1010c000 0x19c>;
|
||||
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru ACLK_LCDC0>,
|
||||
<&cru DCLK_LCDC0>,
|
||||
<&cru HCLK_LCDC0>;
|
||||
clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
|
||||
power-domains = <&power RK3066_PD_VIO>;
|
||||
resets = <&cru SRST_LCDC0_AXI>,
|
||||
<&cru SRST_LCDC0_AHB>,
|
||||
<&cru SRST_LCDC0_DCLK>;
|
||||
reset-names = "axi", "ahb", "dclk";
|
||||
status = "disabled";
|
||||
|
||||
vop0_out: port {
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||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
vop0_out_hdmi: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&hdmi_in_vop0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
vop1: vop@1010e000 {
|
||||
compatible = "rockchip,rk3066-vop";
|
||||
reg = <0x1010e000 0x19c>;
|
||||
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru ACLK_LCDC1>,
|
||||
<&cru DCLK_LCDC1>,
|
||||
<&cru HCLK_LCDC1>;
|
||||
clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
|
||||
power-domains = <&power RK3066_PD_VIO>;
|
||||
resets = <&cru SRST_LCDC1_AXI>,
|
||||
<&cru SRST_LCDC1_AHB>,
|
||||
<&cru SRST_LCDC1_DCLK>;
|
||||
reset-names = "axi", "ahb", "dclk";
|
||||
status = "disabled";
|
||||
|
||||
vop1_out: port {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
vop1_out_hdmi: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&hdmi_in_vop1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
hdmi: hdmi@10116000 {
|
||||
compatible = "rockchip,rk3066-hdmi";
|
||||
reg = <0x10116000 0x2000>;
|
||||
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru HCLK_HDMI>;
|
||||
clock-names = "hclk";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hdmii2c_xfer>, <&hdmi_hpd>;
|
||||
power-domains = <&power RK3066_PD_VIO>;
|
||||
rockchip,grf = <&grf>;
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
hdmi_in: port@0 {
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
hdmi_in_vop0: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&vop0_out_hdmi>;
|
||||
};
|
||||
|
||||
hdmi_in_vop1: endpoint@1 {
|
||||
reg = <1>;
|
||||
remote-endpoint = <&vop1_out_hdmi>;
|
||||
};
|
||||
};
|
||||
|
||||
hdmi_out: port@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
i2s0: i2s@10118000 {
|
||||
compatible = "rockchip,rk3066-i2s";
|
||||
reg = <0x10118000 0x2000>;
|
||||
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2s0_bus>;
|
||||
clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>;
|
||||
clock-names = "i2s_clk", "i2s_hclk";
|
||||
dmas = <&dmac1_s 4>, <&dmac1_s 5>;
|
||||
dma-names = "tx", "rx";
|
||||
rockchip,playback-channels = <8>;
|
||||
rockchip,capture-channels = <2>;
|
||||
#sound-dai-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2s1: i2s@1011a000 {
|
||||
compatible = "rockchip,rk3066-i2s";
|
||||
reg = <0x1011a000 0x2000>;
|
||||
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2s1_bus>;
|
||||
clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>;
|
||||
clock-names = "i2s_clk", "i2s_hclk";
|
||||
dmas = <&dmac1_s 6>, <&dmac1_s 7>;
|
||||
dma-names = "tx", "rx";
|
||||
rockchip,playback-channels = <2>;
|
||||
rockchip,capture-channels = <2>;
|
||||
#sound-dai-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2s2: i2s@1011c000 {
|
||||
compatible = "rockchip,rk3066-i2s";
|
||||
reg = <0x1011c000 0x2000>;
|
||||
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2s2_bus>;
|
||||
clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>;
|
||||
clock-names = "i2s_clk", "i2s_hclk";
|
||||
dmas = <&dmac1_s 9>, <&dmac1_s 10>;
|
||||
dma-names = "tx", "rx";
|
||||
rockchip,playback-channels = <2>;
|
||||
rockchip,capture-channels = <2>;
|
||||
#sound-dai-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
cru: clock-controller@20000000 {
|
||||
compatible = "rockchip,rk3066a-cru";
|
||||
reg = <0x20000000 0x1000>;
|
||||
clocks = <&xin24m>;
|
||||
clock-names = "xin24m";
|
||||
rockchip,grf = <&grf>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
assigned-clocks = <&cru PLL_CPLL>, <&cru PLL_GPLL>,
|
||||
<&cru ACLK_CPU>, <&cru HCLK_CPU>,
|
||||
<&cru PCLK_CPU>, <&cru ACLK_PERI>,
|
||||
<&cru HCLK_PERI>, <&cru PCLK_PERI>;
|
||||
assigned-clock-rates = <400000000>, <594000000>,
|
||||
<300000000>, <150000000>,
|
||||
<75000000>, <300000000>,
|
||||
<150000000>, <75000000>;
|
||||
};
|
||||
|
||||
timer2: timer@2000e000 {
|
||||
compatible = "snps,dw-apb-timer";
|
||||
reg = <0x2000e000 0x100>;
|
||||
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>;
|
||||
clock-names = "timer", "pclk";
|
||||
};
|
||||
|
||||
efuse: efuse@20010000 {
|
||||
compatible = "rockchip,rk3066a-efuse";
|
||||
reg = <0x20010000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
clocks = <&cru PCLK_EFUSE>;
|
||||
clock-names = "pclk_efuse";
|
||||
|
||||
cpu_leakage: cpu_leakage@17 {
|
||||
reg = <0x17 0x1>;
|
||||
};
|
||||
};
|
||||
|
||||
timer0: timer@20038000 {
|
||||
compatible = "snps,dw-apb-timer";
|
||||
reg = <0x20038000 0x100>;
|
||||
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>;
|
||||
clock-names = "timer", "pclk";
|
||||
};
|
||||
|
||||
timer1: timer@2003a000 {
|
||||
compatible = "snps,dw-apb-timer";
|
||||
reg = <0x2003a000 0x100>;
|
||||
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>;
|
||||
clock-names = "timer", "pclk";
|
||||
};
|
||||
|
||||
tsadc: tsadc@20060000 {
|
||||
compatible = "rockchip,rk3066-tsadc";
|
||||
reg = <0x20060000 0x100>;
|
||||
clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
|
||||
clock-names = "saradc", "apb_pclk";
|
||||
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#io-channel-cells = <1>;
|
||||
resets = <&cru SRST_TSADC>;
|
||||
reset-names = "saradc-apb";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pinctrl: pinctrl {
|
||||
compatible = "rockchip,rk3066a-pinctrl";
|
||||
rockchip,grf = <&grf>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
gpio0: gpio@20034000 {
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x20034000 0x100>;
|
||||
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru PCLK_GPIO0>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio1: gpio@2003c000 {
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x2003c000 0x100>;
|
||||
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru PCLK_GPIO1>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio2: gpio@2003e000 {
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x2003e000 0x100>;
|
||||
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru PCLK_GPIO2>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio3: gpio@20080000 {
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x20080000 0x100>;
|
||||
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru PCLK_GPIO3>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio4: gpio@20084000 {
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x20084000 0x100>;
|
||||
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru PCLK_GPIO4>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio6: gpio@2000a000 {
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x2000a000 0x100>;
|
||||
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru PCLK_GPIO6>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
pcfg_pull_default: pcfg-pull-default {
|
||||
bias-pull-pin-default;
|
||||
};
|
||||
|
||||
pcfg_pull_none: pcfg-pull-none {
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
emac {
|
||||
emac_xfer: emac-xfer {
|
||||
rockchip,pins = <1 RK_PC0 2 &pcfg_pull_none>, /* mac_clk */
|
||||
<1 RK_PC1 2 &pcfg_pull_none>, /* tx_en */
|
||||
<1 RK_PC2 2 &pcfg_pull_none>, /* txd1 */
|
||||
<1 RK_PC3 2 &pcfg_pull_none>, /* txd0 */
|
||||
<1 RK_PC4 2 &pcfg_pull_none>, /* rx_err */
|
||||
<1 RK_PC5 2 &pcfg_pull_none>, /* crs_dvalid */
|
||||
<1 RK_PC6 2 &pcfg_pull_none>, /* rxd1 */
|
||||
<1 RK_PC7 2 &pcfg_pull_none>; /* rxd0 */
|
||||
};
|
||||
|
||||
emac_mdio: emac-mdio {
|
||||
rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>, /* mac_md */
|
||||
<1 RK_PD1 2 &pcfg_pull_none>; /* mac_mdclk */
|
||||
};
|
||||
};
|
||||
|
||||
emmc {
|
||||
emmc_clk: emmc-clk {
|
||||
rockchip,pins = <3 RK_PD7 2 &pcfg_pull_default>;
|
||||
};
|
||||
|
||||
emmc_cmd: emmc-cmd {
|
||||
rockchip,pins = <4 RK_PB1 2 &pcfg_pull_default>;
|
||||
};
|
||||
|
||||
emmc_rst: emmc-rst {
|
||||
rockchip,pins = <4 RK_PB2 2 &pcfg_pull_default>;
|
||||
};
|
||||
|
||||
/*
|
||||
* The data pins are shared between nandc and emmc and
|
||||
* not accessible through pinctrl. Also they should've
|
||||
* been already set correctly by firmware, as
|
||||
* flash/emmc is the boot-device.
|
||||
*/
|
||||
};
|
||||
|
||||
hdmi {
|
||||
hdmi_hpd: hdmi-hpd {
|
||||
rockchip,pins = <0 RK_PA0 1 &pcfg_pull_default>;
|
||||
};
|
||||
|
||||
hdmii2c_xfer: hdmii2c-xfer {
|
||||
rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>,
|
||||
<0 RK_PA2 1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c0 {
|
||||
i2c0_xfer: i2c0-xfer {
|
||||
rockchip,pins = <2 RK_PD4 1 &pcfg_pull_none>,
|
||||
<2 RK_PD5 1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c1 {
|
||||
i2c1_xfer: i2c1-xfer {
|
||||
rockchip,pins = <2 RK_PD6 1 &pcfg_pull_none>,
|
||||
<2 RK_PD7 1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c2 {
|
||||
i2c2_xfer: i2c2-xfer {
|
||||
rockchip,pins = <3 RK_PA0 1 &pcfg_pull_none>,
|
||||
<3 RK_PA1 1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c3 {
|
||||
i2c3_xfer: i2c3-xfer {
|
||||
rockchip,pins = <3 RK_PA2 2 &pcfg_pull_none>,
|
||||
<3 RK_PA3 2 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c4 {
|
||||
i2c4_xfer: i2c4-xfer {
|
||||
rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>,
|
||||
<3 RK_PA5 1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pwm0 {
|
||||
pwm0_out: pwm0-out {
|
||||
rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pwm1 {
|
||||
pwm1_out: pwm1-out {
|
||||
rockchip,pins = <0 RK_PA4 1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pwm2 {
|
||||
pwm2_out: pwm2-out {
|
||||
rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pwm3 {
|
||||
pwm3_out: pwm3-out {
|
||||
rockchip,pins = <0 RK_PD7 1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
spi0 {
|
||||
spi0_clk: spi0-clk {
|
||||
rockchip,pins = <1 RK_PA5 2 &pcfg_pull_default>;
|
||||
};
|
||||
spi0_cs0: spi0-cs0 {
|
||||
rockchip,pins = <1 RK_PA4 2 &pcfg_pull_default>;
|
||||
};
|
||||
spi0_tx: spi0-tx {
|
||||
rockchip,pins = <1 RK_PA7 2 &pcfg_pull_default>;
|
||||
};
|
||||
spi0_rx: spi0-rx {
|
||||
rockchip,pins = <1 RK_PA6 2 &pcfg_pull_default>;
|
||||
};
|
||||
spi0_cs1: spi0-cs1 {
|
||||
rockchip,pins = <4 RK_PB7 1 &pcfg_pull_default>;
|
||||
};
|
||||
};
|
||||
|
||||
spi1 {
|
||||
spi1_clk: spi1-clk {
|
||||
rockchip,pins = <2 RK_PC3 2 &pcfg_pull_default>;
|
||||
};
|
||||
spi1_cs0: spi1-cs0 {
|
||||
rockchip,pins = <2 RK_PC4 2 &pcfg_pull_default>;
|
||||
};
|
||||
spi1_rx: spi1-rx {
|
||||
rockchip,pins = <2 RK_PC6 2 &pcfg_pull_default>;
|
||||
};
|
||||
spi1_tx: spi1-tx {
|
||||
rockchip,pins = <2 RK_PC5 2 &pcfg_pull_default>;
|
||||
};
|
||||
spi1_cs1: spi1-cs1 {
|
||||
rockchip,pins = <2 RK_PC7 2 &pcfg_pull_default>;
|
||||
};
|
||||
};
|
||||
|
||||
uart0 {
|
||||
uart0_xfer: uart0-xfer {
|
||||
rockchip,pins = <1 RK_PA0 1 &pcfg_pull_default>,
|
||||
<1 RK_PA1 1 &pcfg_pull_default>;
|
||||
};
|
||||
|
||||
uart0_cts: uart0-cts {
|
||||
rockchip,pins = <1 RK_PA2 1 &pcfg_pull_default>;
|
||||
};
|
||||
|
||||
uart0_rts: uart0-rts {
|
||||
rockchip,pins = <1 RK_PA3 1 &pcfg_pull_default>;
|
||||
};
|
||||
};
|
||||
|
||||
uart1 {
|
||||
uart1_xfer: uart1-xfer {
|
||||
rockchip,pins = <1 RK_PA4 1 &pcfg_pull_default>,
|
||||
<1 RK_PA5 1 &pcfg_pull_default>;
|
||||
};
|
||||
|
||||
uart1_cts: uart1-cts {
|
||||
rockchip,pins = <1 RK_PA6 1 &pcfg_pull_default>;
|
||||
};
|
||||
|
||||
uart1_rts: uart1-rts {
|
||||
rockchip,pins = <1 RK_PA7 1 &pcfg_pull_default>;
|
||||
};
|
||||
};
|
||||
|
||||
uart2 {
|
||||
uart2_xfer: uart2-xfer {
|
||||
rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>,
|
||||
<1 RK_PB1 1 &pcfg_pull_default>;
|
||||
};
|
||||
/* no rts / cts for uart2 */
|
||||
};
|
||||
|
||||
uart3 {
|
||||
uart3_xfer: uart3-xfer {
|
||||
rockchip,pins = <3 RK_PD3 1 &pcfg_pull_default>,
|
||||
<3 RK_PD4 1 &pcfg_pull_default>;
|
||||
};
|
||||
|
||||
uart3_cts: uart3-cts {
|
||||
rockchip,pins = <3 RK_PD5 1 &pcfg_pull_default>;
|
||||
};
|
||||
|
||||
uart3_rts: uart3-rts {
|
||||
rockchip,pins = <3 RK_PD6 1 &pcfg_pull_default>;
|
||||
};
|
||||
};
|
||||
|
||||
sd0 {
|
||||
sd0_clk: sd0-clk {
|
||||
rockchip,pins = <3 RK_PB0 1 &pcfg_pull_default>;
|
||||
};
|
||||
|
||||
sd0_cmd: sd0-cmd {
|
||||
rockchip,pins = <3 RK_PB1 1 &pcfg_pull_default>;
|
||||
};
|
||||
|
||||
sd0_cd: sd0-cd {
|
||||
rockchip,pins = <3 RK_PB6 1 &pcfg_pull_default>;
|
||||
};
|
||||
|
||||
sd0_wp: sd0-wp {
|
||||
rockchip,pins = <3 RK_PB7 1 &pcfg_pull_default>;
|
||||
};
|
||||
|
||||
sd0_bus1: sd0-bus-width1 {
|
||||
rockchip,pins = <3 RK_PB2 1 &pcfg_pull_default>;
|
||||
};
|
||||
|
||||
sd0_bus4: sd0-bus-width4 {
|
||||
rockchip,pins = <3 RK_PB2 1 &pcfg_pull_default>,
|
||||
<3 RK_PB3 1 &pcfg_pull_default>,
|
||||
<3 RK_PB4 1 &pcfg_pull_default>,
|
||||
<3 RK_PB5 1 &pcfg_pull_default>;
|
||||
};
|
||||
};
|
||||
|
||||
sd1 {
|
||||
sd1_clk: sd1-clk {
|
||||
rockchip,pins = <3 RK_PC5 1 &pcfg_pull_default>;
|
||||
};
|
||||
|
||||
sd1_cmd: sd1-cmd {
|
||||
rockchip,pins = <3 RK_PC0 1 &pcfg_pull_default>;
|
||||
};
|
||||
|
||||
sd1_cd: sd1-cd {
|
||||
rockchip,pins = <3 RK_PC6 1 &pcfg_pull_default>;
|
||||
};
|
||||
|
||||
sd1_wp: sd1-wp {
|
||||
rockchip,pins = <3 RK_PC7 1 &pcfg_pull_default>;
|
||||
};
|
||||
|
||||
sd1_bus1: sd1-bus-width1 {
|
||||
rockchip,pins = <3 RK_PC1 1 &pcfg_pull_default>;
|
||||
};
|
||||
|
||||
sd1_bus4: sd1-bus-width4 {
|
||||
rockchip,pins = <3 RK_PC1 1 &pcfg_pull_default>,
|
||||
<3 RK_PC2 1 &pcfg_pull_default>,
|
||||
<3 RK_PC3 1 &pcfg_pull_default>,
|
||||
<3 RK_PC4 1 &pcfg_pull_default>;
|
||||
};
|
||||
};
|
||||
|
||||
i2s0 {
|
||||
i2s0_bus: i2s0-bus {
|
||||
rockchip,pins = <0 RK_PA7 1 &pcfg_pull_default>,
|
||||
<0 RK_PB0 1 &pcfg_pull_default>,
|
||||
<0 RK_PB1 1 &pcfg_pull_default>,
|
||||
<0 RK_PB2 1 &pcfg_pull_default>,
|
||||
<0 RK_PB3 1 &pcfg_pull_default>,
|
||||
<0 RK_PB4 1 &pcfg_pull_default>,
|
||||
<0 RK_PB5 1 &pcfg_pull_default>,
|
||||
<0 RK_PB6 1 &pcfg_pull_default>,
|
||||
<0 RK_PB7 1 &pcfg_pull_default>;
|
||||
};
|
||||
};
|
||||
|
||||
i2s1 {
|
||||
i2s1_bus: i2s1-bus {
|
||||
rockchip,pins = <0 RK_PC0 1 &pcfg_pull_default>,
|
||||
<0 RK_PC1 1 &pcfg_pull_default>,
|
||||
<0 RK_PC2 1 &pcfg_pull_default>,
|
||||
<0 RK_PC3 1 &pcfg_pull_default>,
|
||||
<0 RK_PC4 1 &pcfg_pull_default>,
|
||||
<0 RK_PC5 1 &pcfg_pull_default>;
|
||||
};
|
||||
};
|
||||
|
||||
i2s2 {
|
||||
i2s2_bus: i2s2-bus {
|
||||
rockchip,pins = <0 RK_PD0 1 &pcfg_pull_default>,
|
||||
<0 RK_PD1 1 &pcfg_pull_default>,
|
||||
<0 RK_PD2 1 &pcfg_pull_default>,
|
||||
<0 RK_PD3 1 &pcfg_pull_default>,
|
||||
<0 RK_PD4 1 &pcfg_pull_default>,
|
||||
<0 RK_PD5 1 &pcfg_pull_default>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gpu {
|
||||
compatible = "rockchip,rk3066-mali", "arm,mali-400";
|
||||
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "gp",
|
||||
"gpmmu",
|
||||
"pp0",
|
||||
"ppmmu0",
|
||||
"pp1",
|
||||
"ppmmu1",
|
||||
"pp2",
|
||||
"ppmmu2",
|
||||
"pp3",
|
||||
"ppmmu3";
|
||||
power-domains = <&power RK3066_PD_GPU>;
|
||||
};
|
||||
|
||||
&grf {
|
||||
compatible = "rockchip,rk3066-grf", "syscon", "simple-mfd";
|
||||
|
||||
usbphy: usbphy {
|
||||
compatible = "rockchip,rk3066a-usb-phy";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
|
||||
usbphy0: usb-phy@17c {
|
||||
reg = <0x17c>;
|
||||
clocks = <&cru SCLK_OTGPHY0>;
|
||||
clock-names = "phyclk";
|
||||
#clock-cells = <0>;
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
usbphy1: usb-phy@188 {
|
||||
reg = <0x188>;
|
||||
clocks = <&cru SCLK_OTGPHY1>;
|
||||
clock-names = "phyclk";
|
||||
#clock-cells = <0>;
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c0_xfer>;
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c1_xfer>;
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c2_xfer>;
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c3_xfer>;
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c4_xfer>;
|
||||
};
|
||||
|
||||
&mmc0 {
|
||||
clock-frequency = <50000000>;
|
||||
dmas = <&dmac2 1>;
|
||||
dma-names = "rx-tx";
|
||||
max-frequency = <50000000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>;
|
||||
};
|
||||
|
||||
&mmc1 {
|
||||
dmas = <&dmac2 3>;
|
||||
dma-names = "rx-tx";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>;
|
||||
};
|
||||
|
||||
&emmc {
|
||||
dmas = <&dmac2 4>;
|
||||
dma-names = "rx-tx";
|
||||
};
|
||||
|
||||
&pmu {
|
||||
power: power-controller {
|
||||
compatible = "rockchip,rk3066-power-controller";
|
||||
#power-domain-cells = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
power-domain@RK3066_PD_VIO {
|
||||
reg = <RK3066_PD_VIO>;
|
||||
clocks = <&cru ACLK_LCDC0>,
|
||||
<&cru ACLK_LCDC1>,
|
||||
<&cru DCLK_LCDC0>,
|
||||
<&cru DCLK_LCDC1>,
|
||||
<&cru HCLK_LCDC0>,
|
||||
<&cru HCLK_LCDC1>,
|
||||
<&cru SCLK_CIF1>,
|
||||
<&cru ACLK_CIF1>,
|
||||
<&cru HCLK_CIF1>,
|
||||
<&cru SCLK_CIF0>,
|
||||
<&cru ACLK_CIF0>,
|
||||
<&cru HCLK_CIF0>,
|
||||
<&cru HCLK_HDMI>,
|
||||
<&cru ACLK_IPP>,
|
||||
<&cru HCLK_IPP>,
|
||||
<&cru ACLK_RGA>,
|
||||
<&cru HCLK_RGA>;
|
||||
pm_qos = <&qos_lcdc0>,
|
||||
<&qos_lcdc1>,
|
||||
<&qos_cif0>,
|
||||
<&qos_cif1>,
|
||||
<&qos_ipp>,
|
||||
<&qos_rga>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
power-domain@RK3066_PD_VIDEO {
|
||||
reg = <RK3066_PD_VIDEO>;
|
||||
clocks = <&cru ACLK_VDPU>,
|
||||
<&cru ACLK_VEPU>,
|
||||
<&cru HCLK_VDPU>,
|
||||
<&cru HCLK_VEPU>;
|
||||
pm_qos = <&qos_vpu>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
power-domain@RK3066_PD_GPU {
|
||||
reg = <RK3066_PD_GPU>;
|
||||
clocks = <&cru ACLK_GPU>;
|
||||
pm_qos = <&qos_gpu>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pwm0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm0_out>;
|
||||
};
|
||||
|
||||
&pwm1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm1_out>;
|
||||
};
|
||||
|
||||
&pwm2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm2_out>;
|
||||
};
|
||||
|
||||
&pwm3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm3_out>;
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
|
||||
};
|
||||
|
||||
&spi1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
|
||||
dmas = <&dmac1_s 0>, <&dmac1_s 1>;
|
||||
dma-names = "tx", "rx";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0_xfer>;
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
|
||||
dmas = <&dmac1_s 2>, <&dmac1_s 3>;
|
||||
dma-names = "tx", "rx";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart1_xfer>;
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
|
||||
dmas = <&dmac2 6>, <&dmac2 7>;
|
||||
dma-names = "tx", "rx";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart2_xfer>;
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
|
||||
dmas = <&dmac2 8>, <&dmac2 9>;
|
||||
dma-names = "tx", "rx";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart3_xfer>;
|
||||
};
|
||||
|
||||
&vpu {
|
||||
power-domains = <&power RK3066_PD_VIDEO>;
|
||||
};
|
||||
|
||||
&wdt {
|
||||
compatible = "rockchip,rk3066-wdt", "snps,dw-wdt";
|
||||
};
|
||||
|
||||
&emac {
|
||||
compatible = "rockchip,rk3066-emac";
|
||||
};
|
||||
@@ -1,389 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include "rk3188.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Radxa Rock";
|
||||
compatible = "radxa,rock", "rockchip,rk3188";
|
||||
|
||||
aliases {
|
||||
mmc0 = &mmc0;
|
||||
};
|
||||
|
||||
memory@60000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x60000000 0x80000000>;
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
autorepeat;
|
||||
|
||||
key-power {
|
||||
gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_POWER>;
|
||||
label = "GPIO Key Power";
|
||||
linux,input-type = <1>;
|
||||
wakeup-source;
|
||||
debounce-interval = <100>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
green_led: led-0 {
|
||||
label = "rock:green:user1";
|
||||
gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_LOW>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
blue_led: led-1 {
|
||||
label = "rock:blue:user2";
|
||||
gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
sleep_led: led-2 {
|
||||
label = "rock:red:power";
|
||||
gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,name = "SPDIF";
|
||||
|
||||
simple-audio-card,dai-link@1 { /* S/PDIF - S/PDIF */
|
||||
cpu { sound-dai = <&spdif>; };
|
||||
codec { sound-dai = <&spdif_out>; };
|
||||
};
|
||||
};
|
||||
|
||||
spdif_out: spdif-out {
|
||||
compatible = "linux,spdif-dit";
|
||||
#sound-dai-cells = <0>;
|
||||
};
|
||||
|
||||
ir_recv: ir-receiver {
|
||||
compatible = "gpio-ir-receiver";
|
||||
gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ir_recv_pin>;
|
||||
};
|
||||
|
||||
vcc_otg: usb-otg-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio2 RK_PD7 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&otg_vbus_drv>;
|
||||
regulator-name = "otg-vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vcc_sd0: sdmmc-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "sdmmc-supply";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc_pwr>;
|
||||
startup-delay-us = <100000>;
|
||||
vin-supply = <&vcc_io>;
|
||||
};
|
||||
|
||||
vcc_host: usb-host-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&host_vbus_drv>;
|
||||
regulator-name = "host-pwr";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vsys: vsys-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vsys";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-boot-on;
|
||||
};
|
||||
};
|
||||
|
||||
&emac {
|
||||
phy = <&phy0>;
|
||||
phy-supply = <&vcc_rmii>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&phy_int>;
|
||||
status = "okay";
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
interrupt-parent = <&gpio3>;
|
||||
interrupts = <RK_PD2 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu-supply = <&vdd_arm>;
|
||||
};
|
||||
|
||||
&cpu1 {
|
||||
cpu-supply = <&vdd_arm>;
|
||||
};
|
||||
|
||||
&cpu2 {
|
||||
cpu-supply = <&vdd_arm>;
|
||||
};
|
||||
|
||||
&cpu3 {
|
||||
cpu-supply = <&vdd_arm>;
|
||||
};
|
||||
|
||||
&gpu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
rtc@51 {
|
||||
compatible = "haoyu,hym8563";
|
||||
reg = <0x51>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <RK_PB5 IRQ_TYPE_EDGE_FALLING>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&rtc_int>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "xin32k";
|
||||
};
|
||||
|
||||
act8846: act8846@5a {
|
||||
compatible = "active-semi,act8846";
|
||||
reg = <0x5a>;
|
||||
status = "okay";
|
||||
system-power-controller;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&act8846_dvs0_ctl>;
|
||||
|
||||
vp1-supply = <&vsys>;
|
||||
vp2-supply = <&vsys>;
|
||||
vp3-supply = <&vsys>;
|
||||
vp4-supply = <&vsys>;
|
||||
inl1-supply = <&vcc_io>;
|
||||
inl2-supply = <&vsys>;
|
||||
inl3-supply = <&vsys>;
|
||||
|
||||
regulators {
|
||||
vcc_ddr: REG1 {
|
||||
regulator-name = "VCC_DDR";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdd_log: REG2 {
|
||||
regulator-name = "VDD_LOG";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdd_arm: REG3 {
|
||||
regulator-name = "VDD_ARM";
|
||||
regulator-min-microvolt = <875000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vcc_io: REG4 {
|
||||
regulator-name = "VCC_IO";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdd_10: REG5 {
|
||||
regulator-name = "VDD_10";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdd_hdmi: REG6 {
|
||||
regulator-name = "VDD_HDMI";
|
||||
regulator-min-microvolt = <2500000>;
|
||||
regulator-max-microvolt = <2500000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vcc18: REG7 {
|
||||
regulator-name = "VCC_18";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vcca_33: REG8 {
|
||||
regulator-name = "VCCA_33";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vcc_rmii: REG9 {
|
||||
regulator-name = "VCC_RMII";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
vccio_wl: REG10 {
|
||||
regulator-name = "VCCIO_WL";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vcc_18: REG11 {
|
||||
regulator-name = "VCC18_IO";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vcc28: REG12 {
|
||||
regulator-name = "VCC_28";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mmc0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>;
|
||||
vmmc-supply = <&vcc_sd0>;
|
||||
|
||||
bus-width = <4>;
|
||||
cap-mmc-highspeed;
|
||||
cap-sd-highspeed;
|
||||
disable-wp;
|
||||
};
|
||||
|
||||
&pwm1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
pcfg_output_low: pcfg-output-low {
|
||||
output-low;
|
||||
};
|
||||
|
||||
act8846 {
|
||||
act8846_dvs0_ctl: act8846-dvs0-ctl {
|
||||
rockchip,pins = <3 RK_PD3 RK_FUNC_GPIO &pcfg_output_low>;
|
||||
};
|
||||
};
|
||||
|
||||
hym8563 {
|
||||
rtc_int: rtc-int {
|
||||
rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
lan8720a {
|
||||
phy_int: phy-int {
|
||||
rockchip,pins = <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
ir-receiver {
|
||||
ir_recv_pin: ir-recv-pin {
|
||||
rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
sd0 {
|
||||
sdmmc_pwr: sdmmc-pwr {
|
||||
rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
usb {
|
||||
host_vbus_drv: host-vbus-drv {
|
||||
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
otg_vbus_drv: otg-vbus-drv {
|
||||
rockchip,pins = <2 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&spdif {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbphy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_otg {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wdt {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -6,25 +6,8 @@
|
||||
#include "rockchip-u-boot.dtsi"
|
||||
#include "rk3xxx-u-boot.dtsi"
|
||||
|
||||
&global_timer {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio0 {
|
||||
compatible = "rockchip,gpio-bank";
|
||||
gpio-ranges = <&pinctrl 0 0 32>;
|
||||
};
|
||||
|
||||
&gpio1 {
|
||||
gpio-ranges = <&pinctrl 0 32 32>;
|
||||
};
|
||||
|
||||
&gpio2 {
|
||||
gpio-ranges = <&pinctrl 0 64 32>;
|
||||
};
|
||||
|
||||
&gpio3 {
|
||||
gpio-ranges = <&pinctrl 0 96 32>;
|
||||
};
|
||||
|
||||
&pmu {
|
||||
|
||||
@@ -1,815 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2013 MundoReader S.L.
|
||||
* Author: Heiko Stuebner <heiko@sntech.de>
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/pinctrl/rockchip.h>
|
||||
#include <dt-bindings/clock/rk3188-cru.h>
|
||||
#include <dt-bindings/power/rk3188-power.h>
|
||||
#include "rk3xxx.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "rockchip,rk3188";
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
enable-method = "rockchip,rk3066-smp";
|
||||
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
next-level-cache = <&L2>;
|
||||
reg = <0x0>;
|
||||
clock-latency = <40000>;
|
||||
clocks = <&cru ARMCLK>;
|
||||
operating-points-v2 = <&cpu0_opp_table>;
|
||||
resets = <&cru SRST_CORE0>;
|
||||
};
|
||||
cpu1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
next-level-cache = <&L2>;
|
||||
reg = <0x1>;
|
||||
operating-points-v2 = <&cpu0_opp_table>;
|
||||
resets = <&cru SRST_CORE1>;
|
||||
};
|
||||
cpu2: cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
next-level-cache = <&L2>;
|
||||
reg = <0x2>;
|
||||
operating-points-v2 = <&cpu0_opp_table>;
|
||||
resets = <&cru SRST_CORE2>;
|
||||
};
|
||||
cpu3: cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
next-level-cache = <&L2>;
|
||||
reg = <0x3>;
|
||||
operating-points-v2 = <&cpu0_opp_table>;
|
||||
resets = <&cru SRST_CORE3>;
|
||||
};
|
||||
};
|
||||
|
||||
cpu0_opp_table: opp-table-0 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp-312000000 {
|
||||
opp-hz = /bits/ 64 <312000000>;
|
||||
opp-microvolt = <875000>;
|
||||
clock-latency-ns = <40000>;
|
||||
};
|
||||
opp-504000000 {
|
||||
opp-hz = /bits/ 64 <504000000>;
|
||||
opp-microvolt = <925000>;
|
||||
};
|
||||
opp-600000000 {
|
||||
opp-hz = /bits/ 64 <600000000>;
|
||||
opp-microvolt = <950000>;
|
||||
opp-suspend;
|
||||
};
|
||||
opp-816000000 {
|
||||
opp-hz = /bits/ 64 <816000000>;
|
||||
opp-microvolt = <975000>;
|
||||
};
|
||||
opp-1008000000 {
|
||||
opp-hz = /bits/ 64 <1008000000>;
|
||||
opp-microvolt = <1075000>;
|
||||
};
|
||||
opp-1200000000 {
|
||||
opp-hz = /bits/ 64 <1200000000>;
|
||||
opp-microvolt = <1150000>;
|
||||
};
|
||||
opp-1416000000 {
|
||||
opp-hz = /bits/ 64 <1416000000>;
|
||||
opp-microvolt = <1250000>;
|
||||
};
|
||||
opp-1608000000 {
|
||||
opp-hz = /bits/ 64 <1608000000>;
|
||||
opp-microvolt = <1350000>;
|
||||
};
|
||||
};
|
||||
|
||||
display-subsystem {
|
||||
compatible = "rockchip,display-subsystem";
|
||||
ports = <&vop0_out>, <&vop1_out>;
|
||||
};
|
||||
|
||||
sram: sram@10080000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x10080000 0x8000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x10080000 0x8000>;
|
||||
|
||||
smp-sram@0 {
|
||||
compatible = "rockchip,rk3066-smp-sram";
|
||||
reg = <0x0 0x50>;
|
||||
};
|
||||
};
|
||||
|
||||
vop0: vop@1010c000 {
|
||||
compatible = "rockchip,rk3188-vop";
|
||||
reg = <0x1010c000 0x1000>;
|
||||
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru ACLK_LCDC0>, <&cru DCLK_LCDC0>, <&cru HCLK_LCDC0>;
|
||||
clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
|
||||
power-domains = <&power RK3188_PD_VIO>;
|
||||
resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
|
||||
reset-names = "axi", "ahb", "dclk";
|
||||
status = "disabled";
|
||||
|
||||
vop0_out: port {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
vop1: vop@1010e000 {
|
||||
compatible = "rockchip,rk3188-vop";
|
||||
reg = <0x1010e000 0x1000>;
|
||||
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru ACLK_LCDC1>, <&cru DCLK_LCDC1>, <&cru HCLK_LCDC1>;
|
||||
clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
|
||||
power-domains = <&power RK3188_PD_VIO>;
|
||||
resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
|
||||
reset-names = "axi", "ahb", "dclk";
|
||||
status = "disabled";
|
||||
|
||||
vop1_out: port {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
timer3: timer@2000e000 {
|
||||
compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
|
||||
reg = <0x2000e000 0x20>;
|
||||
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru PCLK_TIMER3>, <&cru SCLK_TIMER3>;
|
||||
clock-names = "pclk", "timer";
|
||||
};
|
||||
|
||||
timer6: timer@200380a0 {
|
||||
compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
|
||||
reg = <0x200380a0 0x20>;
|
||||
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER6>;
|
||||
clock-names = "pclk", "timer";
|
||||
};
|
||||
|
||||
i2s0: i2s@1011a000 {
|
||||
compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s";
|
||||
reg = <0x1011a000 0x2000>;
|
||||
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2s0_bus>;
|
||||
clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>;
|
||||
clock-names = "i2s_clk", "i2s_hclk";
|
||||
dmas = <&dmac1_s 6>, <&dmac1_s 7>;
|
||||
dma-names = "tx", "rx";
|
||||
rockchip,playback-channels = <2>;
|
||||
rockchip,capture-channels = <2>;
|
||||
#sound-dai-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spdif: sound@1011e000 {
|
||||
compatible = "rockchip,rk3188-spdif", "rockchip,rk3066-spdif";
|
||||
reg = <0x1011e000 0x2000>;
|
||||
#sound-dai-cells = <0>;
|
||||
clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF>;
|
||||
clock-names = "mclk", "hclk";
|
||||
dmas = <&dmac1_s 8>;
|
||||
dma-names = "tx";
|
||||
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spdif_tx>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
cru: clock-controller@20000000 {
|
||||
compatible = "rockchip,rk3188-cru";
|
||||
reg = <0x20000000 0x1000>;
|
||||
clocks = <&xin24m>;
|
||||
clock-names = "xin24m";
|
||||
rockchip,grf = <&grf>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
efuse: efuse@20010000 {
|
||||
compatible = "rockchip,rk3188-efuse";
|
||||
reg = <0x20010000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
clocks = <&cru PCLK_EFUSE>;
|
||||
clock-names = "pclk_efuse";
|
||||
|
||||
cpu_leakage: cpu_leakage@17 {
|
||||
reg = <0x17 0x1>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl: pinctrl {
|
||||
compatible = "rockchip,rk3188-pinctrl";
|
||||
rockchip,grf = <&grf>;
|
||||
rockchip,pmu = <&pmu>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
gpio0: gpio@2000a000 {
|
||||
compatible = "rockchip,rk3188-gpio-bank0";
|
||||
reg = <0x2000a000 0x100>;
|
||||
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru PCLK_GPIO0>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio1: gpio@2003c000 {
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x2003c000 0x100>;
|
||||
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru PCLK_GPIO1>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio2: gpio@2003e000 {
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x2003e000 0x100>;
|
||||
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru PCLK_GPIO2>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio3: gpio@20080000 {
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x20080000 0x100>;
|
||||
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru PCLK_GPIO3>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
pcfg_pull_up: pcfg-pull-up {
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
pcfg_pull_down: pcfg-pull-down {
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
pcfg_pull_none: pcfg-pull-none {
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
emmc {
|
||||
emmc_clk: emmc-clk {
|
||||
rockchip,pins = <0 RK_PD0 2 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
emmc_cmd: emmc-cmd {
|
||||
rockchip,pins = <0 RK_PD2 2 &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
emmc_rst: emmc-rst {
|
||||
rockchip,pins = <0 RK_PD3 2 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/*
|
||||
* The data pins are shared between nandc and emmc and
|
||||
* not accessible through pinctrl. Also they should've
|
||||
* been already set correctly by firmware, as
|
||||
* flash/emmc is the boot-device.
|
||||
*/
|
||||
};
|
||||
|
||||
emac {
|
||||
emac_xfer: emac-xfer {
|
||||
rockchip,pins = <3 RK_PC0 2 &pcfg_pull_none>, /* tx_en */
|
||||
<3 RK_PC1 2 &pcfg_pull_none>, /* txd1 */
|
||||
<3 RK_PC2 2 &pcfg_pull_none>, /* txd0 */
|
||||
<3 RK_PC3 2 &pcfg_pull_none>, /* rxd0 */
|
||||
<3 RK_PC4 2 &pcfg_pull_none>, /* rxd1 */
|
||||
<3 RK_PC5 2 &pcfg_pull_none>, /* mac_clk */
|
||||
<3 RK_PC6 2 &pcfg_pull_none>, /* rx_err */
|
||||
<3 RK_PC7 2 &pcfg_pull_none>; /* crs_dvalid */
|
||||
};
|
||||
|
||||
emac_mdio: emac-mdio {
|
||||
rockchip,pins = <3 RK_PD0 2 &pcfg_pull_none>,
|
||||
<3 RK_PD1 2 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c0 {
|
||||
i2c0_xfer: i2c0-xfer {
|
||||
rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>,
|
||||
<1 RK_PD1 1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c1 {
|
||||
i2c1_xfer: i2c1-xfer {
|
||||
rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>,
|
||||
<1 RK_PD3 1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c2 {
|
||||
i2c2_xfer: i2c2-xfer {
|
||||
rockchip,pins = <1 RK_PD4 1 &pcfg_pull_none>,
|
||||
<1 RK_PD5 1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c3 {
|
||||
i2c3_xfer: i2c3-xfer {
|
||||
rockchip,pins = <3 RK_PB6 2 &pcfg_pull_none>,
|
||||
<3 RK_PB7 2 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c4 {
|
||||
i2c4_xfer: i2c4-xfer {
|
||||
rockchip,pins = <1 RK_PD6 1 &pcfg_pull_none>,
|
||||
<1 RK_PD7 1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
lcdc1 {
|
||||
lcdc1_dclk: lcdc1-dclk {
|
||||
rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
lcdc1_den: lcdc1-den {
|
||||
rockchip,pins = <2 RK_PD1 1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
lcdc1_hsync: lcdc1-hsync {
|
||||
rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
lcdc1_vsync: lcdc1-vsync {
|
||||
rockchip,pins = <2 RK_PD3 1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
lcdc1_rgb24: lcdc1-rgb24 {
|
||||
rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>,
|
||||
<2 RK_PA1 1 &pcfg_pull_none>,
|
||||
<2 RK_PA2 1 &pcfg_pull_none>,
|
||||
<2 RK_PA3 1 &pcfg_pull_none>,
|
||||
<2 RK_PA4 1 &pcfg_pull_none>,
|
||||
<2 RK_PA5 1 &pcfg_pull_none>,
|
||||
<2 RK_PA6 1 &pcfg_pull_none>,
|
||||
<2 RK_PA7 1 &pcfg_pull_none>,
|
||||
<2 RK_PB0 1 &pcfg_pull_none>,
|
||||
<2 RK_PB1 1 &pcfg_pull_none>,
|
||||
<2 RK_PB2 1 &pcfg_pull_none>,
|
||||
<2 RK_PB3 1 &pcfg_pull_none>,
|
||||
<2 RK_PB4 1 &pcfg_pull_none>,
|
||||
<2 RK_PB5 1 &pcfg_pull_none>,
|
||||
<2 RK_PB6 1 &pcfg_pull_none>,
|
||||
<2 RK_PB7 1 &pcfg_pull_none>,
|
||||
<2 RK_PC0 1 &pcfg_pull_none>,
|
||||
<2 RK_PC1 1 &pcfg_pull_none>,
|
||||
<2 RK_PC2 1 &pcfg_pull_none>,
|
||||
<2 RK_PC3 1 &pcfg_pull_none>,
|
||||
<2 RK_PC4 1 &pcfg_pull_none>,
|
||||
<2 RK_PC5 1 &pcfg_pull_none>,
|
||||
<2 RK_PC6 1 &pcfg_pull_none>,
|
||||
<2 RK_PC7 1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pwm0 {
|
||||
pwm0_out: pwm0-out {
|
||||
rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pwm1 {
|
||||
pwm1_out: pwm1-out {
|
||||
rockchip,pins = <3 RK_PD4 1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pwm2 {
|
||||
pwm2_out: pwm2-out {
|
||||
rockchip,pins = <3 RK_PD5 1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pwm3 {
|
||||
pwm3_out: pwm3-out {
|
||||
rockchip,pins = <3 RK_PD6 1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
spi0 {
|
||||
spi0_clk: spi0-clk {
|
||||
rockchip,pins = <1 RK_PA6 2 &pcfg_pull_up>;
|
||||
};
|
||||
spi0_cs0: spi0-cs0 {
|
||||
rockchip,pins = <1 RK_PA7 2 &pcfg_pull_up>;
|
||||
};
|
||||
spi0_tx: spi0-tx {
|
||||
rockchip,pins = <1 RK_PA5 2 &pcfg_pull_up>;
|
||||
};
|
||||
spi0_rx: spi0-rx {
|
||||
rockchip,pins = <1 RK_PA4 2 &pcfg_pull_up>;
|
||||
};
|
||||
spi0_cs1: spi0-cs1 {
|
||||
rockchip,pins = <1 RK_PB7 1 &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
spi1 {
|
||||
spi1_clk: spi1-clk {
|
||||
rockchip,pins = <0 RK_PD6 1 &pcfg_pull_up>;
|
||||
};
|
||||
spi1_cs0: spi1-cs0 {
|
||||
rockchip,pins = <0 RK_PD7 1 &pcfg_pull_up>;
|
||||
};
|
||||
spi1_rx: spi1-rx {
|
||||
rockchip,pins = <0 RK_PD4 1 &pcfg_pull_up>;
|
||||
};
|
||||
spi1_tx: spi1-tx {
|
||||
rockchip,pins = <0 RK_PD5 1 &pcfg_pull_up>;
|
||||
};
|
||||
spi1_cs1: spi1-cs1 {
|
||||
rockchip,pins = <1 RK_PB6 2 &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
uart0 {
|
||||
uart0_xfer: uart0-xfer {
|
||||
rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up>,
|
||||
<1 RK_PA1 1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
uart0_cts: uart0-cts {
|
||||
rockchip,pins = <1 RK_PA2 1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
uart0_rts: uart0-rts {
|
||||
rockchip,pins = <1 RK_PA3 1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
uart1 {
|
||||
uart1_xfer: uart1-xfer {
|
||||
rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up>,
|
||||
<1 RK_PA5 1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
uart1_cts: uart1-cts {
|
||||
rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
uart1_rts: uart1-rts {
|
||||
rockchip,pins = <1 RK_PA7 1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
uart2 {
|
||||
uart2_xfer: uart2-xfer {
|
||||
rockchip,pins = <1 RK_PB0 1 &pcfg_pull_up>,
|
||||
<1 RK_PB1 1 &pcfg_pull_none>;
|
||||
};
|
||||
/* no rts / cts for uart2 */
|
||||
};
|
||||
|
||||
uart3 {
|
||||
uart3_xfer: uart3-xfer {
|
||||
rockchip,pins = <1 RK_PB2 1 &pcfg_pull_up>,
|
||||
<1 RK_PB3 1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
uart3_cts: uart3-cts {
|
||||
rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
uart3_rts: uart3-rts {
|
||||
rockchip,pins = <1 RK_PB5 1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
sd0 {
|
||||
sd0_clk: sd0-clk {
|
||||
rockchip,pins = <3 RK_PA2 1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
sd0_cmd: sd0-cmd {
|
||||
rockchip,pins = <3 RK_PA3 1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
sd0_cd: sd0-cd {
|
||||
rockchip,pins = <3 RK_PB0 1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
sd0_wp: sd0-wp {
|
||||
rockchip,pins = <3 RK_PB1 1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
sd0_pwr: sd0-pwr {
|
||||
rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
sd0_bus1: sd0-bus-width1 {
|
||||
rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
sd0_bus4: sd0-bus-width4 {
|
||||
rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>,
|
||||
<3 RK_PA5 1 &pcfg_pull_none>,
|
||||
<3 RK_PA6 1 &pcfg_pull_none>,
|
||||
<3 RK_PA7 1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
sd1 {
|
||||
sd1_clk: sd1-clk {
|
||||
rockchip,pins = <3 RK_PC5 1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
sd1_cmd: sd1-cmd {
|
||||
rockchip,pins = <3 RK_PC0 1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
sd1_cd: sd1-cd {
|
||||
rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
sd1_wp: sd1-wp {
|
||||
rockchip,pins = <3 RK_PC7 1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
sd1_bus1: sd1-bus-width1 {
|
||||
rockchip,pins = <3 RK_PC1 1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
sd1_bus4: sd1-bus-width4 {
|
||||
rockchip,pins = <3 RK_PC1 1 &pcfg_pull_none>,
|
||||
<3 RK_PC2 1 &pcfg_pull_none>,
|
||||
<3 RK_PC3 1 &pcfg_pull_none>,
|
||||
<3 RK_PC4 1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
i2s0 {
|
||||
i2s0_bus: i2s0-bus {
|
||||
rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>,
|
||||
<1 RK_PC1 1 &pcfg_pull_none>,
|
||||
<1 RK_PC2 1 &pcfg_pull_none>,
|
||||
<1 RK_PC3 1 &pcfg_pull_none>,
|
||||
<1 RK_PC4 1 &pcfg_pull_none>,
|
||||
<1 RK_PC5 1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
spdif {
|
||||
spdif_tx: spdif-tx {
|
||||
rockchip,pins = <1 RK_PB6 1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&emac {
|
||||
compatible = "rockchip,rk3188-emac";
|
||||
};
|
||||
|
||||
&global_timer {
|
||||
interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
|
||||
};
|
||||
|
||||
&local_timer {
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
|
||||
};
|
||||
|
||||
&gpu {
|
||||
compatible = "rockchip,rk3188-mali", "arm,mali-400";
|
||||
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "gp",
|
||||
"gpmmu",
|
||||
"pp0",
|
||||
"ppmmu0",
|
||||
"pp1",
|
||||
"ppmmu1",
|
||||
"pp2",
|
||||
"ppmmu2",
|
||||
"pp3",
|
||||
"ppmmu3";
|
||||
power-domains = <&power RK3188_PD_GPU>;
|
||||
};
|
||||
|
||||
&grf {
|
||||
compatible = "rockchip,rk3188-grf", "syscon", "simple-mfd";
|
||||
|
||||
io_domains: io-domains {
|
||||
compatible = "rockchip,rk3188-io-voltage-domain";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbphy: usbphy {
|
||||
compatible = "rockchip,rk3188-usb-phy";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
|
||||
usbphy0: usb-phy@10c {
|
||||
reg = <0x10c>;
|
||||
clocks = <&cru SCLK_OTGPHY0>;
|
||||
clock-names = "phyclk";
|
||||
#clock-cells = <0>;
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
usbphy1: usb-phy@11c {
|
||||
reg = <0x11c>;
|
||||
clocks = <&cru SCLK_OTGPHY1>;
|
||||
clock-names = "phyclk";
|
||||
#clock-cells = <0>;
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
compatible = "rockchip,rk3188-i2c";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c0_xfer>;
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
compatible = "rockchip,rk3188-i2c";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c1_xfer>;
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
compatible = "rockchip,rk3188-i2c";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c2_xfer>;
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
compatible = "rockchip,rk3188-i2c";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c3_xfer>;
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
compatible = "rockchip,rk3188-i2c";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c4_xfer>;
|
||||
};
|
||||
|
||||
&pmu {
|
||||
power: power-controller {
|
||||
compatible = "rockchip,rk3188-power-controller";
|
||||
#power-domain-cells = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
power-domain@RK3188_PD_VIO {
|
||||
reg = <RK3188_PD_VIO>;
|
||||
clocks = <&cru ACLK_LCDC0>,
|
||||
<&cru ACLK_LCDC1>,
|
||||
<&cru DCLK_LCDC0>,
|
||||
<&cru DCLK_LCDC1>,
|
||||
<&cru HCLK_LCDC0>,
|
||||
<&cru HCLK_LCDC1>,
|
||||
<&cru SCLK_CIF0>,
|
||||
<&cru ACLK_CIF0>,
|
||||
<&cru HCLK_CIF0>,
|
||||
<&cru ACLK_IPP>,
|
||||
<&cru HCLK_IPP>,
|
||||
<&cru ACLK_RGA>,
|
||||
<&cru HCLK_RGA>;
|
||||
pm_qos = <&qos_lcdc0>,
|
||||
<&qos_lcdc1>,
|
||||
<&qos_cif0>,
|
||||
<&qos_ipp>,
|
||||
<&qos_rga>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
power-domain@RK3188_PD_VIDEO {
|
||||
reg = <RK3188_PD_VIDEO>;
|
||||
clocks = <&cru ACLK_VDPU>,
|
||||
<&cru ACLK_VEPU>,
|
||||
<&cru HCLK_VDPU>,
|
||||
<&cru HCLK_VEPU>;
|
||||
pm_qos = <&qos_vpu>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
power-domain@RK3188_PD_GPU {
|
||||
reg = <RK3188_PD_GPU>;
|
||||
clocks = <&cru ACLK_GPU>;
|
||||
pm_qos = <&qos_gpu>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pwm0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm0_out>;
|
||||
};
|
||||
|
||||
&pwm1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm1_out>;
|
||||
};
|
||||
|
||||
&pwm2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm2_out>;
|
||||
};
|
||||
|
||||
&pwm3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm3_out>;
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
|
||||
};
|
||||
|
||||
&spi1 {
|
||||
compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0_xfer>;
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart1_xfer>;
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart2_xfer>;
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart3_xfer>;
|
||||
};
|
||||
|
||||
&vpu {
|
||||
compatible = "rockchip,rk3188-vpu", "rockchip,rk3066-vpu";
|
||||
power-domains = <&power RK3188_PD_VIDEO>;
|
||||
};
|
||||
|
||||
&wdt {
|
||||
compatible = "rockchip,rk3188-wdt", "snps,dw-wdt";
|
||||
};
|
||||
@@ -6,21 +6,8 @@
|
||||
#include "rk3288-u-boot.dtsi"
|
||||
|
||||
/ {
|
||||
config {
|
||||
bootph-all;
|
||||
u-boot,boot-led = "firefly:green:power";
|
||||
};
|
||||
|
||||
leds {
|
||||
bootph-all;
|
||||
|
||||
work {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
power {
|
||||
bootph-all;
|
||||
};
|
||||
chosen {
|
||||
stdout-path = "serial2:115200n8";
|
||||
};
|
||||
};
|
||||
|
||||
@@ -36,46 +23,100 @@
|
||||
rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
&emmc {
|
||||
bootph-pre-ram;
|
||||
bootph-some-ram;
|
||||
};
|
||||
|
||||
&emmc_bus8 {
|
||||
bootph-pre-ram;
|
||||
bootph-some-ram;
|
||||
};
|
||||
|
||||
&emmc_clk {
|
||||
bootph-pre-ram;
|
||||
bootph-some-ram;
|
||||
};
|
||||
|
||||
&emmc_cmd {
|
||||
bootph-pre-ram;
|
||||
bootph-some-ram;
|
||||
};
|
||||
|
||||
&emmc_pwr {
|
||||
bootph-pre-ram;
|
||||
bootph-some-ram;
|
||||
};
|
||||
|
||||
&gmac {
|
||||
snps,reset-delays-us = <0 10000 80000>;
|
||||
};
|
||||
|
||||
&gpio7 {
|
||||
/delete-property/ bootph-all;
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&pcfg_pull_none {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&pcfg_pull_none_12ma {
|
||||
bootph-pre-ram;
|
||||
bootph-some-ram;
|
||||
};
|
||||
|
||||
&pcfg_pull_up {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&pcfg_pull_up_drv_12ma {
|
||||
bootph-pre-ram;
|
||||
bootph-some-ram;
|
||||
};
|
||||
|
||||
&power_led {
|
||||
default-state = "on";
|
||||
};
|
||||
|
||||
&sdmmc {
|
||||
bootph-pre-ram;
|
||||
bootph-some-ram;
|
||||
};
|
||||
|
||||
&sdmmc_bus4 {
|
||||
bootph-pre-ram;
|
||||
bootph-some-ram;
|
||||
};
|
||||
|
||||
&sdmmc_cd {
|
||||
bootph-pre-ram;
|
||||
bootph-some-ram;
|
||||
};
|
||||
|
||||
&sdmmc_clk {
|
||||
bootph-pre-ram;
|
||||
bootph-some-ram;
|
||||
};
|
||||
|
||||
&sdmmc_cmd {
|
||||
bootph-pre-ram;
|
||||
bootph-some-ram;
|
||||
};
|
||||
|
||||
&sdmmc_pwr {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&sdmmc {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&emmc {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&gpio3 {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&gpio8 {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&pcfg_pull_up_drv_12ma {
|
||||
&uart2_xfer {
|
||||
bootph-pre-sram;
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&sdmmc_bus4 {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&sdmmc_clk {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&sdmmc_cmd {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&sdmmc_pwr {
|
||||
&vcc_sd {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
@@ -1,43 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
||||
/*
|
||||
* Copyright (c) 2014, 2015 FUKAUMI Naoki <naobsd@gmail.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "rk3288-firefly.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Firefly-RK3288";
|
||||
compatible = "firefly,firefly-rk3288", "rockchip,rk3288";
|
||||
|
||||
chosen {
|
||||
stdout-path = &uart2;
|
||||
};
|
||||
};
|
||||
|
||||
&ir {
|
||||
gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
act8846 {
|
||||
pmic_vsel: pmic-vsel {
|
||||
rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_output_low>;
|
||||
};
|
||||
};
|
||||
|
||||
ir {
|
||||
ir_int: ir-int {
|
||||
rockchip,pins = <7 0 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
usb_host {
|
||||
host_vbus_drv: host-vbus-drv {
|
||||
rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pwm1 {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -1,491 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
||||
/*
|
||||
* Copyright (c) 2014, 2015 FUKAUMI Naoki <naobsd@gmail.com>
|
||||
*/
|
||||
|
||||
#include "rk3288.dtsi"
|
||||
|
||||
/ {
|
||||
memory {
|
||||
reg = <0x0 0x0 0x0 0x80000000>;
|
||||
};
|
||||
|
||||
ext_gmac: external-gmac-clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <125000000>;
|
||||
clock-output-names = "ext_gmac";
|
||||
};
|
||||
|
||||
ir: ir-receiver {
|
||||
compatible = "gpio-ir-receiver";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ir_int>;
|
||||
};
|
||||
|
||||
keys: gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
button@0 {
|
||||
gpio-key,wakeup = <1>;
|
||||
gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
|
||||
label = "GPIO Power";
|
||||
linux,code = <116>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwr_key>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
work {
|
||||
gpios = <&gpio8 1 GPIO_ACTIVE_LOW>;
|
||||
label = "firefly:blue:user";
|
||||
linux,default-trigger = "rc-feedback";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&work_led>;
|
||||
};
|
||||
|
||||
power {
|
||||
gpios = <&gpio8 2 GPIO_ACTIVE_LOW>;
|
||||
label = "firefly:green:power";
|
||||
linux,default-trigger = "default-on";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&power_led>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_sys: vsys-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_sys";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vcc_sd: sdmmc-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
gpio = <&gpio7 11 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc_pwr>;
|
||||
regulator-name = "vcc_sd";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
startup-delay-us = <100000>;
|
||||
vin-supply = <&vcc_io>;
|
||||
};
|
||||
|
||||
vcc_flash: flash-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_flash";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
vin-supply = <&vcc_io>;
|
||||
};
|
||||
|
||||
vcc_5v: usb-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_5v";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
vin-supply = <&vcc_sys>;
|
||||
};
|
||||
|
||||
vcc_host_5v: usb-host-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&host_vbus_drv>;
|
||||
regulator-name = "vcc_host_5v";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
vin-supply = <&vcc_5v>;
|
||||
};
|
||||
|
||||
vcc_otg_5v: usb-otg-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&otg_vbus_drv>;
|
||||
regulator-name = "vcc_otg_5v";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
vin-supply = <&vcc_5v>;
|
||||
};
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu0-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&emmc {
|
||||
broken-cd;
|
||||
bus-width = <8>;
|
||||
cap-mmc-highspeed;
|
||||
disable-wp;
|
||||
non-removable;
|
||||
num-slots = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_pwr>, <&emmc_bus8>;
|
||||
vmmc-supply = <&vcc_io>;
|
||||
vqmmc-supply = <&vcc_flash>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gmac {
|
||||
assigned-clocks = <&cru SCLK_MAC>;
|
||||
assigned-clock-parents = <&ext_gmac>;
|
||||
clock_in_out = "input";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>;
|
||||
phy-supply = <&vcc_lan>;
|
||||
phy-mode = "rgmii";
|
||||
snps,reset-active-low;
|
||||
snps,reset-delays-us = <0 10000 1000000>;
|
||||
snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_LOW>;
|
||||
tx_delay = <0x30>;
|
||||
rx_delay = <0x10>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
ddc-i2c-bus = <&i2c5>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
|
||||
vdd_cpu: syr827@40 {
|
||||
compatible = "silergy,syr827";
|
||||
fcs,suspend-voltage-selector = <1>;
|
||||
reg = <0x40>;
|
||||
regulator-name = "vdd_cpu";
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
vin-supply = <&vcc_sys>;
|
||||
};
|
||||
|
||||
vdd_gpu: syr828@41 {
|
||||
compatible = "silergy,syr828";
|
||||
fcs,suspend-voltage-selector = <1>;
|
||||
reg = <0x41>;
|
||||
regulator-name = "vdd_gpu";
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-always-on;
|
||||
vin-supply = <&vcc_sys>;
|
||||
};
|
||||
|
||||
hym8563: hym8563@51 {
|
||||
compatible = "haoyu,hym8563";
|
||||
reg = <0x51>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
clock-output-names = "xin32k";
|
||||
interrupt-parent = <&gpio7>;
|
||||
interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&rtc_int>;
|
||||
};
|
||||
|
||||
act8846: act8846@5a {
|
||||
compatible = "active-semi,act8846";
|
||||
reg = <0x5a>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_vsel>, <&pwr_hold>;
|
||||
system-power-controller;
|
||||
|
||||
regulators {
|
||||
vcc_ddr: REG1 {
|
||||
regulator-name = "vcc_ddr";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vcc_io: REG2 {
|
||||
regulator-name = "vcc_io";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdd_log: REG3 {
|
||||
regulator-name = "vdd_log";
|
||||
regulator-min-microvolt = <1100000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vcc_20: REG4 {
|
||||
regulator-name = "vcc_20";
|
||||
regulator-min-microvolt = <2000000>;
|
||||
regulator-max-microvolt = <2000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vccio_sd: REG5 {
|
||||
regulator-name = "vccio_sd";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdd10_lcd: REG6 {
|
||||
regulator-name = "vdd10_lcd";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vcca_18: REG7 {
|
||||
regulator-name = "vcca_18";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
vcca_33: REG8 {
|
||||
regulator-name = "vcca_33";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
vcc_lan: REG9 {
|
||||
regulator-name = "vcc_lan";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
vdd_10: REG10 {
|
||||
regulator-name = "vdd_10";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vcc_18: REG11 {
|
||||
regulator-name = "vcc_18";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vcc18_lcd: REG12 {
|
||||
regulator-name = "vcc18_lcd";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c5 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
pcfg_output_high: pcfg-output-high {
|
||||
output-high;
|
||||
};
|
||||
|
||||
pcfg_output_low: pcfg-output-low {
|
||||
output-low;
|
||||
};
|
||||
|
||||
pcfg_pull_up_drv_12ma: pcfg-pull-up-drv-12ma {
|
||||
bias-pull-up;
|
||||
drive-strength = <12>;
|
||||
};
|
||||
|
||||
act8846 {
|
||||
pwr_hold: pwr-hold {
|
||||
rockchip,pins = <0 1 RK_FUNC_GPIO &pcfg_output_high>;
|
||||
};
|
||||
};
|
||||
|
||||
gmac {
|
||||
phy_int: phy-int {
|
||||
rockchip,pins = <0 9 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
phy_pmeb: phy-pmeb {
|
||||
rockchip,pins = <0 8 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
phy_rst: phy-rst {
|
||||
rockchip,pins = <4 8 RK_FUNC_GPIO &pcfg_output_high>;
|
||||
};
|
||||
};
|
||||
|
||||
hym8563 {
|
||||
rtc_int: rtc-int {
|
||||
rockchip,pins = <7 4 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
keys {
|
||||
pwr_key: pwr-key {
|
||||
rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
power_led: power-led {
|
||||
rockchip,pins = <8 2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
work_led: work-led {
|
||||
rockchip,pins = <8 1 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
sdmmc {
|
||||
/*
|
||||
* Default drive strength isn't enough to achieve even
|
||||
* high-speed mode on firefly board so bump up to 12ma.
|
||||
*/
|
||||
sdmmc_bus4: sdmmc-bus4 {
|
||||
rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up_drv_12ma>,
|
||||
<6 RK_PC1 1 &pcfg_pull_up_drv_12ma>,
|
||||
<6 RK_PC2 1 &pcfg_pull_up_drv_12ma>,
|
||||
<6 RK_PC3 1 &pcfg_pull_up_drv_12ma>;
|
||||
};
|
||||
|
||||
sdmmc_clk: sdmmc-clk {
|
||||
rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_12ma>;
|
||||
};
|
||||
|
||||
sdmmc_cmd: sdmmc-cmd {
|
||||
rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up_drv_12ma>;
|
||||
};
|
||||
|
||||
sdmmc_pwr: sdmmc-pwr {
|
||||
rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
usb_host {
|
||||
host_vbus_drv: host-vbus-drv {
|
||||
rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
usbhub_rst: usbhub-rst {
|
||||
rockchip,pins = <8 3 RK_FUNC_GPIO &pcfg_output_high>;
|
||||
};
|
||||
};
|
||||
|
||||
usb_otg {
|
||||
otg_vbus_drv: otg-vbus-drv {
|
||||
rockchip,pins = <0 12 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&saradc {
|
||||
vref-supply = <&vcc_18>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdio0 {
|
||||
broken-cd;
|
||||
bus-width = <4>;
|
||||
disable-wp;
|
||||
non-removable;
|
||||
num-slots = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdio0_bus4>, <&sdio0_cmd>, <&sdio0_clk>;
|
||||
vmmc-supply = <&vcc_18>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&sdmmc {
|
||||
bus-width = <4>;
|
||||
cap-mmc-highspeed;
|
||||
cap-sd-highspeed;
|
||||
card-detect-delay = <200>;
|
||||
disable-wp;
|
||||
num-slots = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>;
|
||||
vmmc-supply = <&vcc_sd>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi0_clk>, <&spi0_cs0>, <&spi0_tx>, <&spi0_rx>, <&spi0_cs1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0_xfer>, <&uart0_cts>, <&uart0_rts>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usbhub_rst>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_otg {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopb {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopb_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopl {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopl_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wdt {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -4,15 +4,6 @@
|
||||
*/
|
||||
|
||||
#include "rk3288-u-boot.dtsi"
|
||||
/ {
|
||||
leds {
|
||||
bootph-all;
|
||||
|
||||
work {
|
||||
bootph-all;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dmc {
|
||||
rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
|
||||
@@ -25,34 +16,96 @@
|
||||
rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
&emmc {
|
||||
bootph-pre-ram;
|
||||
bootph-some-ram;
|
||||
};
|
||||
|
||||
&emmc_bus8 {
|
||||
bootph-pre-ram;
|
||||
bootph-some-ram;
|
||||
};
|
||||
|
||||
&emmc_clk {
|
||||
bootph-pre-ram;
|
||||
bootph-some-ram;
|
||||
};
|
||||
|
||||
&emmc_cmd {
|
||||
bootph-pre-ram;
|
||||
bootph-some-ram;
|
||||
};
|
||||
|
||||
&emmc_pwr {
|
||||
bootph-pre-ram;
|
||||
bootph-some-ram;
|
||||
};
|
||||
|
||||
&gmac {
|
||||
snps,reset-delays-us = <0 10000 80000>;
|
||||
};
|
||||
|
||||
&gpio7 {
|
||||
/delete-property/ bootph-all;
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&pcfg_pull_none {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&pcfg_pull_none_12ma {
|
||||
bootph-pre-ram;
|
||||
bootph-some-ram;
|
||||
};
|
||||
|
||||
&pcfg_pull_up {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&pcfg_pull_up_drv_12ma {
|
||||
bootph-pre-ram;
|
||||
bootph-some-ram;
|
||||
};
|
||||
|
||||
&sdmmc {
|
||||
bootph-pre-ram;
|
||||
bootph-some-ram;
|
||||
};
|
||||
|
||||
&sdmmc_bus4 {
|
||||
bootph-pre-ram;
|
||||
bootph-some-ram;
|
||||
};
|
||||
|
||||
&sdmmc_cd {
|
||||
bootph-pre-ram;
|
||||
bootph-some-ram;
|
||||
};
|
||||
|
||||
&sdmmc_clk {
|
||||
bootph-pre-ram;
|
||||
bootph-some-ram;
|
||||
};
|
||||
|
||||
&sdmmc_cmd {
|
||||
bootph-pre-ram;
|
||||
bootph-some-ram;
|
||||
};
|
||||
|
||||
&sdmmc_pwr {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&sdmmc {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&emmc {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&sdmmc_bus4 {
|
||||
&uart2_xfer {
|
||||
bootph-pre-sram;
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&sdmmc_clk {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&sdmmc_cmd {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&sdmmc_pwr {
|
||||
&vcc_sd {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
@@ -1,16 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
||||
/*
|
||||
* (C) Copyright 2016 Rockchip Electronics Co., Ltd
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "rk3288-miqi.dtsi"
|
||||
|
||||
/ {
|
||||
model = "mqmaker MiQi";
|
||||
compatible = "mqmaker,miqi", "rockchip,rk3288";
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial2:115200n8";
|
||||
};
|
||||
};
|
||||
@@ -1,417 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
||||
/*
|
||||
* Copyright (c) 2016 Heiko Stuebner <heiko@sntech.de>
|
||||
*/
|
||||
|
||||
#include "rk3288.dtsi"
|
||||
|
||||
/ {
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0 0x0 0x80000000>;
|
||||
};
|
||||
|
||||
ext_gmac: external-gmac-clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <125000000>;
|
||||
clock-output-names = "ext_gmac";
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
work {
|
||||
gpios = <&gpio7 4 GPIO_ACTIVE_LOW>;
|
||||
label = "miqi:green:user";
|
||||
linux,default-trigger = "default-on";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&led_ctl>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_flash: flash-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_flash";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
vin-supply = <&vcc_io>;
|
||||
};
|
||||
|
||||
vcc_host: usb-host-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&host_vbus_drv>;
|
||||
regulator-name = "vcc_host";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
vin-supply = <&vcc_sys>;
|
||||
};
|
||||
|
||||
vcc_sd: sdmmc-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
gpio = <&gpio7 11 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc_pwr>;
|
||||
regulator-name = "vcc_sd";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
startup-delay-us = <100000>;
|
||||
vin-supply = <&vcc_io>;
|
||||
};
|
||||
|
||||
vcc_sys: vsys-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_sys";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu0-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&emmc {
|
||||
bus-width = <8>;
|
||||
cap-mmc-highspeed;
|
||||
disable-wp;
|
||||
non-removable;
|
||||
num-slots = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_pwr>, <&emmc_bus8>;
|
||||
vmmc-supply = <&vcc_io>;
|
||||
vqmmc-supply = <&vcc_flash>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gmac {
|
||||
assigned-clocks = <&cru SCLK_MAC>;
|
||||
assigned-clock-parents = <&ext_gmac>;
|
||||
clock_in_out = "input";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>;
|
||||
phy-supply = <&vcc_lan>;
|
||||
phy-mode = "rgmii";
|
||||
snps,reset-active-low;
|
||||
snps,reset-delays-us = <0 10000 1000000>;
|
||||
snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_LOW>;
|
||||
tx_delay = <0x30>;
|
||||
rx_delay = <0x10>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
ddc-i2c-bus = <&i2c5>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
|
||||
vdd_cpu: syr827@40 {
|
||||
compatible = "silergy,syr827";
|
||||
fcs,suspend-voltage-selector = <1>;
|
||||
reg = <0x40>;
|
||||
regulator-name = "vdd_cpu";
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-enable-ramp-delay = <300>;
|
||||
regulator-ramp-delay = <8000>;
|
||||
vin-supply = <&vcc_sys>;
|
||||
};
|
||||
|
||||
vdd_gpu: syr828@41 {
|
||||
compatible = "silergy,syr828";
|
||||
fcs,suspend-voltage-selector = <1>;
|
||||
reg = <0x41>;
|
||||
regulator-name = "vdd_gpu";
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-always-on;
|
||||
vin-supply = <&vcc_sys>;
|
||||
};
|
||||
|
||||
hym8563: hym8563@51 {
|
||||
compatible = "haoyu,hym8563";
|
||||
reg = <0x51>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
clock-output-names = "xin32k";
|
||||
};
|
||||
|
||||
act8846: act8846@5a {
|
||||
compatible = "active-semi,act8846";
|
||||
reg = <0x5a>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_vsel>;
|
||||
system-power-controller;
|
||||
|
||||
vp1-supply = <&vcc_sys>;
|
||||
vp2-supply = <&vcc_sys>;
|
||||
vp3-supply = <&vcc_sys>;
|
||||
vp4-supply = <&vcc_sys>;
|
||||
inl1-supply = <&vcc_sys>;
|
||||
inl2-supply = <&vcc_sys>;
|
||||
inl3-supply = <&vcc_20>;
|
||||
|
||||
regulators {
|
||||
vcc_ddr: REG1 {
|
||||
regulator-name = "vcc_ddr";
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vcc_io: REG2 {
|
||||
regulator-name = "vcc_io";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdd_log: REG3 {
|
||||
regulator-name = "vdd_log";
|
||||
regulator-min-microvolt = <1100000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vcc_20: REG4 {
|
||||
regulator-name = "vcc_20";
|
||||
regulator-min-microvolt = <2000000>;
|
||||
regulator-max-microvolt = <2000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vccio_sd: REG5 {
|
||||
regulator-name = "vccio_sd";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdd10_lcd: REG6 {
|
||||
regulator-name = "vdd10_lcd";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vcca_18: REG7 {
|
||||
regulator-name = "vcca_18";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
vcca_33: REG8 {
|
||||
regulator-name = "vcca_33";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
vcc_lan: REG9 {
|
||||
regulator-name = "vcc_lan";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
vdd_10: REG10 {
|
||||
regulator-name = "vdd_10";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vcc_18: REG11 {
|
||||
regulator-name = "vcc_18";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vcc18_lcd: REG12 {
|
||||
regulator-name = "vcc18_lcd";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c5 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&io_domains {
|
||||
audio-supply = <&vcca_33>;
|
||||
flash0-supply = <&vcc_flash>;
|
||||
flash1-supply = <&vcc_lan>;
|
||||
gpio30-supply = <&vcc_io>;
|
||||
gpio1830-supply = <&vcc_io>;
|
||||
lcdc-supply = <&vcc_io>;
|
||||
sdcard-supply = <&vccio_sd>;
|
||||
wifi-supply = <&vcc_18>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
pcfg_output_high: pcfg-output-high {
|
||||
output-high;
|
||||
};
|
||||
|
||||
pcfg_output_low: pcfg-output-low {
|
||||
output-low;
|
||||
};
|
||||
|
||||
pcfg_pull_up_drv_12ma: pcfg-pull-up-drv-12ma {
|
||||
bias-pull-up;
|
||||
drive-strength = <12>;
|
||||
};
|
||||
|
||||
act8846 {
|
||||
pmic_int: pmic-int {
|
||||
rockchip,pins = <0 4 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
pmic_sleep: pmic-sleep {
|
||||
rockchip,pins = <0 0 RK_FUNC_GPIO &pcfg_output_low>;
|
||||
};
|
||||
|
||||
pmic_vsel: pmic-vsel {
|
||||
rockchip,pins = <7 1 RK_FUNC_GPIO &pcfg_output_low>;
|
||||
};
|
||||
};
|
||||
|
||||
gmac {
|
||||
phy_int: phy-int {
|
||||
rockchip,pins = <0 9 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
phy_pmeb: phy-pmeb {
|
||||
rockchip,pins = <0 8 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
phy_rst: phy-rst {
|
||||
rockchip,pins = <4 8 RK_FUNC_GPIO &pcfg_output_high>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
led_ctl: led-ctl {
|
||||
rockchip,pins = <7 4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
sdmmc {
|
||||
/*
|
||||
* Default drive strength isn't enough to achieve even
|
||||
* high-speed mode on firefly board so bump up to 12ma.
|
||||
*/
|
||||
sdmmc_bus4: sdmmc-bus4 {
|
||||
rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_12ma>,
|
||||
<6 17 RK_FUNC_1 &pcfg_pull_up_drv_12ma>,
|
||||
<6 18 RK_FUNC_1 &pcfg_pull_up_drv_12ma>,
|
||||
<6 19 RK_FUNC_1 &pcfg_pull_up_drv_12ma>;
|
||||
};
|
||||
|
||||
sdmmc_clk: sdmmc-clk {
|
||||
rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_12ma>;
|
||||
};
|
||||
|
||||
sdmmc_cmd: sdmmc-cmd {
|
||||
rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up_drv_12ma>;
|
||||
};
|
||||
|
||||
sdmmc_pwr: sdmmc-pwr {
|
||||
rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
usb_host {
|
||||
host_vbus_drv: host-vbus-drv {
|
||||
rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&saradc {
|
||||
vref-supply = <&vcc_18>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc {
|
||||
bus-width = <4>;
|
||||
cap-mmc-highspeed;
|
||||
cap-sd-highspeed;
|
||||
card-detect-delay = <200>;
|
||||
disable-wp;
|
||||
num-slots = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>;
|
||||
vmmc-supply = <&vcc_sd>;
|
||||
vqmmc-supply = <&vccio_sd>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tsadc {
|
||||
rockchip,hw-tshut-mode = <0>;
|
||||
rockchip,hw-tshut-polarity = <0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbphy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1 {
|
||||
vbus-supply = <&vcc_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopb {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopb_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopl {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopl_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wdt {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -15,20 +15,25 @@
|
||||
|
||||
&emmc {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&emmc_clk {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&emmc_cmd {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&emmc_pwr {
|
||||
bootph-pre-ram;
|
||||
bootph-some-ram;
|
||||
};
|
||||
|
||||
&emmc_bus8 {
|
||||
bootph-pre-ram;
|
||||
bootph-some-ram;
|
||||
};
|
||||
|
||||
&emmc_clk {
|
||||
bootph-pre-ram;
|
||||
bootph-some-ram;
|
||||
};
|
||||
|
||||
&emmc_cmd {
|
||||
bootph-pre-ram;
|
||||
bootph-some-ram;
|
||||
};
|
||||
|
||||
&emmc_pwr {
|
||||
bootph-pre-ram;
|
||||
bootph-some-ram;
|
||||
};
|
||||
|
||||
@@ -1,29 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "rk3288-tinker.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Rockchip RK3288 Asus Tinker Board S";
|
||||
compatible = "asus,rk3288-tinker-s", "rockchip,rk3288";
|
||||
|
||||
chosen {
|
||||
stdout-path = &uart2;
|
||||
};
|
||||
};
|
||||
|
||||
&emmc {
|
||||
bus-width = <8>;
|
||||
cap-mmc-highspeed;
|
||||
non-removable;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>;
|
||||
max-frequency = <150000000>;
|
||||
mmc-hs200-1_8v;
|
||||
mmc-ddr-1_8v;
|
||||
status = "okay";
|
||||
};
|
||||
@@ -6,7 +6,6 @@
|
||||
#include "rk3288-u-boot.dtsi"
|
||||
|
||||
&dmc {
|
||||
bootph-all;
|
||||
rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
|
||||
0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6
|
||||
0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0
|
||||
@@ -17,6 +16,14 @@
|
||||
rockchip,sdram-params = <0x20d266a4 0x5b6 2 533000000 6 9 0>;
|
||||
};
|
||||
|
||||
&gmac {
|
||||
snps,reset-delays-us = <0 10000 80000>;
|
||||
};
|
||||
|
||||
&gpio7 {
|
||||
/delete-property/ bootph-all;
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
m24c08@50 {
|
||||
compatible = "at,24c08", "i2c-eeprom";
|
||||
@@ -24,62 +31,54 @@
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
&pcfg_pull_none {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&pcfg_pull_none_drv_8ma {
|
||||
bootph-pre-ram;
|
||||
bootph-some-ram;
|
||||
};
|
||||
|
||||
&pcfg_pull_up {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&pcfg_pull_up_drv_8ma {
|
||||
bootph-pre-ram;
|
||||
bootph-some-ram;
|
||||
};
|
||||
|
||||
&sdmmc {
|
||||
bootph-pre-ram;
|
||||
bootph-some-ram;
|
||||
};
|
||||
|
||||
&sdmmc_bus4 {
|
||||
bootph-pre-ram;
|
||||
bootph-some-ram;
|
||||
};
|
||||
|
||||
&sdmmc_cd {
|
||||
bootph-pre-ram;
|
||||
bootph-some-ram;
|
||||
};
|
||||
|
||||
&sdmmc_clk {
|
||||
bootph-pre-ram;
|
||||
bootph-some-ram;
|
||||
};
|
||||
|
||||
&sdmmc_cmd {
|
||||
bootph-pre-ram;
|
||||
bootph-some-ram;
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&uart2_xfer {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&sdmmc {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&gpio7 {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&vcc_sd {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&pcfg_pull_none_drv_8ma {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&pcfg_pull_up_drv_8ma {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&pcfg_pull_none {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&pcfg_pull_up {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&sdmmc_bus4 {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&sdmmc_cd {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&sdmmc_clk {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&sdmmc_cmd {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&sdmmc_pwr {
|
||||
bootph-pre-sram;
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
@@ -1,33 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
||||
/*
|
||||
* (C) Copyright 2016 Rockchip Electronics Co., Ltd
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "rk3288-tinker.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Tinker-RK3288";
|
||||
compatible = "rockchip,rk3288-tinker", "rockchip,rk3288";
|
||||
|
||||
chosen {
|
||||
stdout-path = &uart2;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
usb {
|
||||
host_vbus_drv: host-vbus-drv {
|
||||
rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pwm1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1 {
|
||||
vbus-supply = <&vcc5v0_host>;
|
||||
status = "okay";
|
||||
};
|
||||
@@ -1,533 +0,0 @@
|
||||
/*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include "rk3288.dtsi"
|
||||
|
||||
/ {
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0 0x0 0x80000000>;
|
||||
};
|
||||
|
||||
ext_gmac: external-gmac-clock {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <125000000>;
|
||||
clock-output-names = "ext_gmac";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
autorepeat;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwrbtn>;
|
||||
|
||||
button@0 {
|
||||
gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
|
||||
label = "GPIO Key Power";
|
||||
linux,code = <KEY_POWER>;
|
||||
linux,input-type = <1>;
|
||||
gpio-key,wakeup = <1>;
|
||||
debounce-interval = <100>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
pwr-led {
|
||||
gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "default-on";
|
||||
};
|
||||
|
||||
act-led {
|
||||
gpios=<&gpio2 3 GPIO_ACTIVE_LOW>;
|
||||
linux,default-trigger="mmc0";
|
||||
};
|
||||
};
|
||||
|
||||
vcc_sys: vsys-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_sys";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
/*
|
||||
* NOTE: vcc_sd isn't hooked up on v1.0 boards where power comes from
|
||||
* vcc_io directly. Those boards won't be able to power cycle SD cards
|
||||
* but it shouldn't hurt to toggle this pin there anyway.
|
||||
*/
|
||||
vcc_sd: sdmmc-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
gpio = <&gpio7 11 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc_pwr>;
|
||||
regulator-name = "vcc_sd";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
startup-delay-us = <100000>;
|
||||
vin-supply = <&vcc_io>;
|
||||
};
|
||||
|
||||
vcc5v0_host: usb-host-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&host_vbus_drv>;
|
||||
regulator-name = "vcc5v0_host";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu0-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&sdmmc {
|
||||
bus-width = <4>;
|
||||
cap-mmc-highspeed;
|
||||
cap-sd-highspeed;
|
||||
card-detect-delay = <200>;
|
||||
disable-wp; /* wp not hooked up */
|
||||
num-slots = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
|
||||
status = "okay";
|
||||
supports-sd;
|
||||
vmmc-supply = <&vcc_sd>;
|
||||
vqmmc-supply = <&vccio_sd>;
|
||||
};
|
||||
|
||||
&gpu {
|
||||
mali-supply = <&vdd_gpu>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gmac {
|
||||
phy-supply = <&vcc33_lan>;
|
||||
phy-mode = "rgmii";
|
||||
clock_in_out = "input";
|
||||
snps,reset-gpio = <&gpio4 7 0>;
|
||||
snps,reset-active-low;
|
||||
snps,reset-delays-us = <0 10000 1000000>;
|
||||
assigned-clocks = <&cru SCLK_MAC>;
|
||||
assigned-clock-parents = <&ext_gmac>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&rgmii_pins>;
|
||||
tx_delay = <0x30>;
|
||||
rx_delay = <0x10>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
ddc-i2c-bus = <&i2c5>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
rk808: pmic@1b {
|
||||
compatible = "rockchip,rk808";
|
||||
reg = <0x1b>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_int &global_pwroff>;
|
||||
rockchip,system-power-controller;
|
||||
wakeup-source;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "xin32k", "rk808-clkout2";
|
||||
|
||||
vcc1-supply = <&vcc_sys>;
|
||||
vcc2-supply = <&vcc_sys>;
|
||||
vcc3-supply = <&vcc_sys>;
|
||||
vcc4-supply = <&vcc_sys>;
|
||||
vcc6-supply = <&vcc_sys>;
|
||||
vcc7-supply = <&vcc_sys>;
|
||||
vcc8-supply = <&vcc_18>;
|
||||
vcc9-supply = <&vcc_io>;
|
||||
vcc10-supply = <&vcc_io>;
|
||||
vcc11-supply = <&vcc_sys>;
|
||||
vcc12-supply = <&vcc_io>;
|
||||
vddio-supply = <&vcc18_ldo1>;
|
||||
|
||||
regulators {
|
||||
vdd_cpu: DCDC_REG1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-name = "vdd_arm";
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_gpu: DCDC_REG2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <1250000>;
|
||||
regulator-name = "vdd_gpu";
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1000000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_ddr: DCDC_REG3 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vcc_ddr";
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_io: DCDC_REG4 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcc_io";
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc18_ldo1: LDO_REG1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcc18_ldo1";
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc33_mipi: LDO_REG2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcc33_mipi";
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_10: LDO_REG3 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-name = "vdd_10";
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1000000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc18_codec: LDO_REG4 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcc18_codec";
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_sd: LDO_REG5 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vccio_sd";
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vdd10_lcd: LDO_REG6 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-name = "vdd10_lcd";
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1000000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_18: LDO_REG7 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcc_18";
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc18_lcd: LDO_REG8 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcc18_lcd";
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc33_sd: SWITCH_REG1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vcc33_sd";
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc33_lan: SWITCH_REG2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vcc33_lan";
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
status = "okay";
|
||||
headset: nau8825@1a {
|
||||
compatible = "nuvoton,nau8825";
|
||||
#sound-dai-cells = <0>;
|
||||
reg = <0x1a>;
|
||||
interrupt-parent = <&gpio6>;
|
||||
interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
|
||||
nuvoton,jkdet-enable = <1>;
|
||||
nuvoton,jkdet-pull-enable = <1>;
|
||||
nuvoton,jkdet-pull-up = <0>;
|
||||
nuvoton,jkdet-polarity = <1>;
|
||||
nuvoton,vref-impedance = <2>;
|
||||
nuvoton,micbias-voltage = <6>;
|
||||
nuvoton,sar-threshold-num = <4>;
|
||||
nuvoton,sar-threshold = <0xa 0x14 0x26 0x73>;
|
||||
nuvoton,sar-hysteresis = <0>;
|
||||
nuvoton,sar-voltage = <6>;
|
||||
nuvoton,sar-compare-time = <0>;
|
||||
nuvoton,sar-sampling-time = <0>;
|
||||
nuvoton,short-key-debounce = <3>;
|
||||
nuvoton,jack-insert-debounce = <7>;
|
||||
nuvoton,jack-eject-debounce = <7>;
|
||||
clock-names = "mclk";
|
||||
clocks = <&cru SCLK_I2S0_OUT>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c5 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wdt {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&saradc {
|
||||
vref-supply = <&vcc18_ldo1>;
|
||||
status ="okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tsadc {
|
||||
rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
|
||||
rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbphy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_otg {
|
||||
status= "okay";
|
||||
};
|
||||
|
||||
&vopb {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopb_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopl {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopl_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
|
||||
drive-strength = <8>;
|
||||
};
|
||||
|
||||
pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
|
||||
bias-pull-up;
|
||||
drive-strength = <8>;
|
||||
};
|
||||
|
||||
backlight {
|
||||
bl_en: bl-en {
|
||||
rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
buttons {
|
||||
pwrbtn: pwrbtn {
|
||||
rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
eth_phy {
|
||||
eth_phy_pwr: eth-phy-pwr {
|
||||
rockchip,pins = <0 6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pmic {
|
||||
pmic_int: pmic-int {
|
||||
rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
sdmmc {
|
||||
/*
|
||||
* Default drive strength isn't enough to achieve even
|
||||
* high-speed mode on EVB board so bump up to 8ma.
|
||||
*/
|
||||
sdmmc_bus4: sdmmc-bus4 {
|
||||
rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
|
||||
<6 17 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
|
||||
<6 18 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
|
||||
<6 19 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
|
||||
};
|
||||
|
||||
sdmmc_clk: sdmmc-clk {
|
||||
rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
|
||||
};
|
||||
|
||||
sdmmc_cmd: sdmmc-cmd {
|
||||
rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
|
||||
};
|
||||
|
||||
sdmmc_pwr: sdmmc-pwr {
|
||||
rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
usb {
|
||||
host_vbus_drv: host-vbus-drv {
|
||||
rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
pwr_3g: pwr-3g {
|
||||
rockchip,pins = <7 8 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -7,15 +7,6 @@
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
gpio0 = &gpio0;
|
||||
gpio1 = &gpio1;
|
||||
gpio2 = &gpio2;
|
||||
gpio3 = &gpio3;
|
||||
gpio4 = &gpio4;
|
||||
gpio5 = &gpio5;
|
||||
gpio6 = &gpio6;
|
||||
gpio7 = &gpio7;
|
||||
gpio8 = &gpio8;
|
||||
mmc0 = &emmc;
|
||||
mmc1 = &sdmmc;
|
||||
mmc2 = &sdio0;
|
||||
@@ -128,11 +119,11 @@
|
||||
};
|
||||
|
||||
&vopb {
|
||||
bootph-all;
|
||||
bootph-some-ram;
|
||||
};
|
||||
|
||||
&vopl {
|
||||
bootph-all;
|
||||
bootph-some-ram;
|
||||
};
|
||||
|
||||
&xin24m {
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -11,7 +11,7 @@
|
||||
};
|
||||
|
||||
config {
|
||||
u-boot,spl-payload-offset = <0x40000>;
|
||||
u-boot,spl-payload-offset = <CONFIG_SYS_SPI_U_BOOT_OFFS>;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -29,11 +29,35 @@
|
||||
rockchip,panel = <&edp_panel>;
|
||||
};
|
||||
|
||||
&emmc_phy {
|
||||
/delete-property/ bootph-pre-ram;
|
||||
};
|
||||
|
||||
&gpio0 {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&pp1500_ap_io {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&pp1800_audio {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
&pp1500_en {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&pp3000 {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&pp3000_en {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&ppvar_bigcpu_pwm {
|
||||
regulator-init-microvolt = <900000>;
|
||||
};
|
||||
@@ -80,7 +104,8 @@
|
||||
|
||||
&spi1 {
|
||||
spi_flash: flash@0 {
|
||||
bootph-all;
|
||||
bootph-pre-ram;
|
||||
bootph-some-ram;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@@ -7,6 +7,10 @@
|
||||
#include "rk3399-sdram-lpddr4-100.dtsi"
|
||||
|
||||
/ {
|
||||
config {
|
||||
sysreset-gpio = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
vcc_hub_en: vcc_hub_en-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
@@ -36,6 +40,10 @@
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&gpio1 {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&spi1 {
|
||||
flash@0 {
|
||||
bootph-pre-ram;
|
||||
|
||||
@@ -7,6 +7,10 @@
|
||||
#include "rk3399-sdram-lpddr4-100.dtsi"
|
||||
|
||||
/ {
|
||||
config {
|
||||
sysreset-gpio = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
smbios {
|
||||
compatible = "u-boot,sysinfo-smbios";
|
||||
smbios {
|
||||
@@ -32,6 +36,10 @@
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&gpio1 {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&sdhci {
|
||||
cap-mmc-highspeed;
|
||||
mmc-ddr-1_8v;
|
||||
|
||||
@@ -39,11 +39,21 @@
|
||||
|
||||
mkimage {
|
||||
args = "-n rk3399 -T rkspi";
|
||||
multiple-data-files;
|
||||
#ifdef CONFIG_ROCKCHIP_EXTERNAL_TPL
|
||||
rockchip-tpl {
|
||||
};
|
||||
#elif defined(CONFIG_TPL)
|
||||
u-boot-tpl {
|
||||
};
|
||||
#endif
|
||||
u-boot-spl {
|
||||
};
|
||||
};
|
||||
u-boot-img {
|
||||
offset = <0x40000>;
|
||||
fit {
|
||||
type = "blob";
|
||||
filename = "u-boot.itb";
|
||||
offset = <CONFIG_SYS_SPI_U_BOOT_OFFS>;
|
||||
};
|
||||
u-boot {
|
||||
offset = <0x300000>;
|
||||
|
||||
8
arch/arm/dts/rk3566-nanopi-r3s-u-boot.dtsi
Normal file
8
arch/arm/dts/rk3566-nanopi-r3s-u-boot.dtsi
Normal file
@@ -0,0 +1,8 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
#include "rk356x-u-boot.dtsi"
|
||||
|
||||
&vcc5v0_usb {
|
||||
/delete-property/ regulator-always-on;
|
||||
/delete-property/ regulator-boot-on;
|
||||
};
|
||||
@@ -87,6 +87,10 @@
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&otp {
|
||||
bootph-some-ram;
|
||||
};
|
||||
|
||||
&pcfg_pull_none {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
3
arch/arm/dts/rk3588-nanopc-t6-lts-u-boot.dtsi
Normal file
3
arch/arm/dts/rk3588-nanopc-t6-lts-u-boot.dtsi
Normal file
@@ -0,0 +1,3 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
|
||||
#include "rk3588-nanopc-t6-u-boot.dtsi"
|
||||
11
arch/arm/dts/rk3588s-rock-5c-u-boot.dtsi
Normal file
11
arch/arm/dts/rk3588s-rock-5c-u-boot.dtsi
Normal file
@@ -0,0 +1,11 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2024-2025 Radxa Computer (Shenzhen) Co., Ltd.
|
||||
*/
|
||||
|
||||
#include "rk3588s-u-boot.dtsi"
|
||||
|
||||
&sdhci {
|
||||
cap-mmc-highspeed;
|
||||
mmc-hs200-1_8v;
|
||||
};
|
||||
@@ -69,6 +69,10 @@
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&otp {
|
||||
bootph-some-ram;
|
||||
};
|
||||
|
||||
&pcfg_pull_down {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
@@ -1,488 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2013 MundoReader S.L.
|
||||
* Author: Heiko Stuebner <heiko@sntech.de>
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/soc/rockchip,boot-mode.h>
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &emac;
|
||||
i2c0 = &i2c0;
|
||||
i2c1 = &i2c1;
|
||||
i2c2 = &i2c2;
|
||||
i2c3 = &i2c3;
|
||||
i2c4 = &i2c4;
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
serial2 = &uart2;
|
||||
serial3 = &uart3;
|
||||
spi0 = &spi0;
|
||||
spi1 = &spi1;
|
||||
};
|
||||
|
||||
xin24m: oscillator {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <24000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "xin24m";
|
||||
};
|
||||
|
||||
gpu: gpu@10090000 {
|
||||
compatible = "arm,mali-400";
|
||||
reg = <0x10090000 0x10000>;
|
||||
clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
|
||||
clock-names = "bus", "core";
|
||||
assigned-clocks = <&cru ACLK_GPU>;
|
||||
assigned-clock-rates = <100000000>;
|
||||
resets = <&cru SRST_GPU>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
vpu: video-codec@10104000 {
|
||||
compatible = "rockchip,rk3066-vpu";
|
||||
reg = <0x10104000 0x800>;
|
||||
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "vepu", "vdpu";
|
||||
clocks = <&cru ACLK_VDPU>, <&cru HCLK_VDPU>,
|
||||
<&cru ACLK_VEPU>, <&cru HCLK_VEPU>;
|
||||
clock-names = "aclk_vdpu", "hclk_vdpu",
|
||||
"aclk_vepu", "hclk_vepu";
|
||||
};
|
||||
|
||||
L2: cache-controller@10138000 {
|
||||
compatible = "arm,pl310-cache";
|
||||
reg = <0x10138000 0x1000>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
||||
scu@1013c000 {
|
||||
compatible = "arm,cortex-a9-scu";
|
||||
reg = <0x1013c000 0x100>;
|
||||
};
|
||||
|
||||
global_timer: global-timer@1013c200 {
|
||||
compatible = "arm,cortex-a9-global-timer";
|
||||
reg = <0x1013c200 0x20>;
|
||||
interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
|
||||
clocks = <&cru CORE_PERI>;
|
||||
status = "disabled";
|
||||
/* The clock source and the sched_clock provided by the arm_global_timer
|
||||
* on Rockchip rk3066a/rk3188 are quite unstable because their rates
|
||||
* depend on the CPU frequency.
|
||||
* Keep the arm_global_timer disabled in order to have the
|
||||
* DW_APB_TIMER (rk3066a) or ROCKCHIP_TIMER (rk3188) selected by default.
|
||||
*/
|
||||
};
|
||||
|
||||
local_timer: local-timer@1013c600 {
|
||||
compatible = "arm,cortex-a9-twd-timer";
|
||||
reg = <0x1013c600 0x20>;
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
|
||||
clocks = <&cru CORE_PERI>;
|
||||
};
|
||||
|
||||
gic: interrupt-controller@1013d000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
reg = <0x1013d000 0x1000>,
|
||||
<0x1013c100 0x0100>;
|
||||
};
|
||||
|
||||
uart0: serial@10124000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x10124000 0x400>;
|
||||
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <1>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@10126000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x10126000 0x400>;
|
||||
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <1>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qos_gpu: qos@1012d000 {
|
||||
compatible = "rockchip,rk3066-qos", "syscon";
|
||||
reg = <0x1012d000 0x20>;
|
||||
};
|
||||
|
||||
qos_vpu: qos@1012e000 {
|
||||
compatible = "rockchip,rk3066-qos", "syscon";
|
||||
reg = <0x1012e000 0x20>;
|
||||
};
|
||||
|
||||
qos_lcdc0: qos@1012f000 {
|
||||
compatible = "rockchip,rk3066-qos", "syscon";
|
||||
reg = <0x1012f000 0x20>;
|
||||
};
|
||||
|
||||
qos_cif0: qos@1012f080 {
|
||||
compatible = "rockchip,rk3066-qos", "syscon";
|
||||
reg = <0x1012f080 0x20>;
|
||||
};
|
||||
|
||||
qos_ipp: qos@1012f100 {
|
||||
compatible = "rockchip,rk3066-qos", "syscon";
|
||||
reg = <0x1012f100 0x20>;
|
||||
};
|
||||
|
||||
qos_lcdc1: qos@1012f180 {
|
||||
compatible = "rockchip,rk3066-qos", "syscon";
|
||||
reg = <0x1012f180 0x20>;
|
||||
};
|
||||
|
||||
qos_cif1: qos@1012f200 {
|
||||
compatible = "rockchip,rk3066-qos", "syscon";
|
||||
reg = <0x1012f200 0x20>;
|
||||
};
|
||||
|
||||
qos_rga: qos@1012f280 {
|
||||
compatible = "rockchip,rk3066-qos", "syscon";
|
||||
reg = <0x1012f280 0x20>;
|
||||
};
|
||||
|
||||
usb_otg: usb@10180000 {
|
||||
compatible = "rockchip,rk3066-usb", "snps,dwc2";
|
||||
reg = <0x10180000 0x40000>;
|
||||
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru HCLK_OTG0>;
|
||||
clock-names = "otg";
|
||||
dr_mode = "otg";
|
||||
g-np-tx-fifo-size = <16>;
|
||||
g-rx-fifo-size = <275>;
|
||||
g-tx-fifo-size = <256 128 128 64 64 32>;
|
||||
phys = <&usbphy0>;
|
||||
phy-names = "usb2-phy";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb_host: usb@101c0000 {
|
||||
compatible = "snps,dwc2";
|
||||
reg = <0x101c0000 0x40000>;
|
||||
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru HCLK_OTG1>;
|
||||
clock-names = "otg";
|
||||
dr_mode = "host";
|
||||
phys = <&usbphy1>;
|
||||
phy-names = "usb2-phy";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
emac: ethernet@10204000 {
|
||||
compatible = "snps,arc-emac";
|
||||
reg = <0x10204000 0x3c>;
|
||||
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
rockchip,grf = <&grf>;
|
||||
|
||||
clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>;
|
||||
clock-names = "hclk", "macref";
|
||||
max-speed = <100>;
|
||||
phy-mode = "rmii";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mmc0: mmc@10214000 {
|
||||
compatible = "rockchip,rk2928-dw-mshc";
|
||||
reg = <0x10214000 0x1000>;
|
||||
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
|
||||
clock-names = "biu", "ciu";
|
||||
dmas = <&dmac2 1>;
|
||||
dma-names = "rx-tx";
|
||||
fifo-depth = <256>;
|
||||
resets = <&cru SRST_SDMMC>;
|
||||
reset-names = "reset";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mmc1: mmc@10218000 {
|
||||
compatible = "rockchip,rk2928-dw-mshc";
|
||||
reg = <0x10218000 0x1000>;
|
||||
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>;
|
||||
clock-names = "biu", "ciu";
|
||||
dmas = <&dmac2 3>;
|
||||
dma-names = "rx-tx";
|
||||
fifo-depth = <256>;
|
||||
resets = <&cru SRST_SDIO>;
|
||||
reset-names = "reset";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
emmc: mmc@1021c000 {
|
||||
compatible = "rockchip,rk2928-dw-mshc";
|
||||
reg = <0x1021c000 0x1000>;
|
||||
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
|
||||
clock-names = "biu", "ciu";
|
||||
dmas = <&dmac2 4>;
|
||||
dma-names = "rx-tx";
|
||||
fifo-depth = <256>;
|
||||
resets = <&cru SRST_EMMC>;
|
||||
reset-names = "reset";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
nfc: nand-controller@10500000 {
|
||||
compatible = "rockchip,rk2928-nfc";
|
||||
reg = <0x10500000 0x4000>;
|
||||
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru HCLK_NANDC0>;
|
||||
clock-names = "ahb";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pmu: pmu@20004000 {
|
||||
compatible = "rockchip,rk3066-pmu", "syscon", "simple-mfd";
|
||||
reg = <0x20004000 0x100>;
|
||||
|
||||
reboot-mode {
|
||||
compatible = "syscon-reboot-mode";
|
||||
offset = <0x40>;
|
||||
mode-normal = <BOOT_NORMAL>;
|
||||
mode-recovery = <BOOT_RECOVERY>;
|
||||
mode-bootloader = <BOOT_FASTBOOT>;
|
||||
mode-loader = <BOOT_BL_DOWNLOAD>;
|
||||
};
|
||||
};
|
||||
|
||||
grf: grf@20008000 {
|
||||
compatible = "syscon", "simple-mfd";
|
||||
reg = <0x20008000 0x200>;
|
||||
};
|
||||
|
||||
dmac1_s: dma-controller@20018000 {
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x20018000 0x4000>;
|
||||
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#dma-cells = <1>;
|
||||
arm,pl330-broken-no-flushp;
|
||||
arm,pl330-periph-burst;
|
||||
clocks = <&cru ACLK_DMA1>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
dmac1_ns: dma-controller@2001c000 {
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x2001c000 0x4000>;
|
||||
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#dma-cells = <1>;
|
||||
arm,pl330-broken-no-flushp;
|
||||
arm,pl330-periph-burst;
|
||||
clocks = <&cru ACLK_DMA1>;
|
||||
clock-names = "apb_pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@2002d000 {
|
||||
compatible = "rockchip,rk3066-i2c";
|
||||
reg = <0x2002d000 0x1000>;
|
||||
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
rockchip,grf = <&grf>;
|
||||
|
||||
clock-names = "i2c";
|
||||
clocks = <&cru PCLK_I2C0>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@2002f000 {
|
||||
compatible = "rockchip,rk3066-i2c";
|
||||
reg = <0x2002f000 0x1000>;
|
||||
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
rockchip,grf = <&grf>;
|
||||
|
||||
clocks = <&cru PCLK_I2C1>;
|
||||
clock-names = "i2c";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm0: pwm@20030000 {
|
||||
compatible = "rockchip,rk2928-pwm";
|
||||
reg = <0x20030000 0x10>;
|
||||
#pwm-cells = <2>;
|
||||
clocks = <&cru PCLK_PWM01>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm1: pwm@20030010 {
|
||||
compatible = "rockchip,rk2928-pwm";
|
||||
reg = <0x20030010 0x10>;
|
||||
#pwm-cells = <2>;
|
||||
clocks = <&cru PCLK_PWM01>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wdt: watchdog@2004c000 {
|
||||
compatible = "snps,dw-wdt";
|
||||
reg = <0x2004c000 0x100>;
|
||||
clocks = <&cru PCLK_WDT>;
|
||||
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm2: pwm@20050020 {
|
||||
compatible = "rockchip,rk2928-pwm";
|
||||
reg = <0x20050020 0x10>;
|
||||
#pwm-cells = <2>;
|
||||
clocks = <&cru PCLK_PWM23>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm3: pwm@20050030 {
|
||||
compatible = "rockchip,rk2928-pwm";
|
||||
reg = <0x20050030 0x10>;
|
||||
#pwm-cells = <2>;
|
||||
clocks = <&cru PCLK_PWM23>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@20056000 {
|
||||
compatible = "rockchip,rk3066-i2c";
|
||||
reg = <0x20056000 0x1000>;
|
||||
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
rockchip,grf = <&grf>;
|
||||
|
||||
clocks = <&cru PCLK_I2C2>;
|
||||
clock-names = "i2c";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c3: i2c@2005a000 {
|
||||
compatible = "rockchip,rk3066-i2c";
|
||||
reg = <0x2005a000 0x1000>;
|
||||
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
rockchip,grf = <&grf>;
|
||||
|
||||
clocks = <&cru PCLK_I2C3>;
|
||||
clock-names = "i2c";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c4: i2c@2005e000 {
|
||||
compatible = "rockchip,rk3066-i2c";
|
||||
reg = <0x2005e000 0x1000>;
|
||||
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
rockchip,grf = <&grf>;
|
||||
|
||||
clocks = <&cru PCLK_I2C4>;
|
||||
clock-names = "i2c";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@20064000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x20064000 0x400>;
|
||||
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <1>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@20068000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x20068000 0x400>;
|
||||
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <1>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
saradc: saradc@2006c000 {
|
||||
compatible = "rockchip,saradc";
|
||||
reg = <0x2006c000 0x100>;
|
||||
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#io-channel-cells = <1>;
|
||||
clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
|
||||
clock-names = "saradc", "apb_pclk";
|
||||
resets = <&cru SRST_SARADC>;
|
||||
reset-names = "saradc-apb";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi0: spi@20070000 {
|
||||
compatible = "rockchip,rk3066-spi";
|
||||
clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
|
||||
clock-names = "spiclk", "apb_pclk";
|
||||
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0x20070000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
dmas = <&dmac2 10>, <&dmac2 11>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi1: spi@20074000 {
|
||||
compatible = "rockchip,rk3066-spi";
|
||||
clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
|
||||
clock-names = "spiclk", "apb_pclk";
|
||||
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0x20074000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
dmas = <&dmac2 12>, <&dmac2 13>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dmac2: dma-controller@20078000 {
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x20078000 0x4000>;
|
||||
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#dma-cells = <1>;
|
||||
arm,pl330-broken-no-flushp;
|
||||
arm,pl330-periph-burst;
|
||||
clocks = <&cru ACLK_DMA2>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
};
|
||||
@@ -346,7 +346,7 @@ enum {
|
||||
ACLK_VOP_LOW_ROOT_SEL_100M,
|
||||
ACLK_VOP_LOW_ROOT_SEL_24M,
|
||||
ACLK_VOP_ROOT_SEL_SHIFT = 5,
|
||||
ACLK_VOP_ROOT_SEL_MASK = 3 << ACLK_VOP_ROOT_SEL_SHIFT,
|
||||
ACLK_VOP_ROOT_SEL_MASK = 7 << ACLK_VOP_ROOT_SEL_SHIFT,
|
||||
ACLK_VOP_ROOT_SEL_GPLL = 0,
|
||||
ACLK_VOP_ROOT_SEL_CPLL,
|
||||
ACLK_VOP_ROOT_SEL_AUPLL,
|
||||
|
||||
@@ -48,6 +48,7 @@ config ROCKCHIP_RK3066
|
||||
select TPL
|
||||
select TPL_ROCKCHIP_BACK_TO_BROM
|
||||
select TPL_ROCKCHIP_EARLYRETURN_TO_BROM
|
||||
imply OF_UPSTREAM
|
||||
imply ROCKCHIP_COMMON_BOARD
|
||||
imply SPL_ROCKCHIP_COMMON_BOARD
|
||||
imply SPL_SERIAL
|
||||
@@ -84,6 +85,7 @@ config ROCKCHIP_RK3188
|
||||
select SPL_ROCKCHIP_EARLYRETURN_TO_BROM
|
||||
select SPL_ROCKCHIP_BACK_TO_BROM
|
||||
select BOARD_LATE_INIT
|
||||
imply OF_UPSTREAM
|
||||
imply ROCKCHIP_COMMON_BOARD
|
||||
imply SPL_ROCKCHIP_COMMON_BOARD
|
||||
help
|
||||
|
||||
@@ -75,7 +75,7 @@ config TARGET_FENNEC_RK3288
|
||||
config TARGET_FIREFLY_RK3288
|
||||
bool "Firefly-RK3288"
|
||||
select BOARD_LATE_INIT
|
||||
select SPL_BOARD_INIT if SPL
|
||||
select ROCKCHIP_COMMON_STACK_ADDR
|
||||
select TPL
|
||||
help
|
||||
Firefly is a RK3288-based development board with 2 USB ports,
|
||||
@@ -86,6 +86,8 @@ config TARGET_FIREFLY_RK3288
|
||||
config TARGET_MIQI_RK3288
|
||||
bool "MiQi-RK3288"
|
||||
select BOARD_LATE_INIT
|
||||
select ROCKCHIP_COMMON_STACK_ADDR
|
||||
select TPL
|
||||
help
|
||||
MiQi-RK3288 is a RK3288-based development board with 4 USB 2.0
|
||||
ports, HDMI, micro-SD card, 16 GB eMMC and Gigabit Ethernet. It
|
||||
@@ -132,6 +134,7 @@ config TARGET_ROCK2
|
||||
config TARGET_TINKER_RK3288
|
||||
bool "Tinker-RK3288"
|
||||
select BOARD_LATE_INIT
|
||||
select ROCKCHIP_COMMON_STACK_ADDR
|
||||
select TPL
|
||||
help
|
||||
Tinker is a RK3288-based development board with 2 USB ports, HDMI,
|
||||
@@ -160,7 +163,7 @@ config SYS_SOC
|
||||
default "rk3288"
|
||||
|
||||
config SYS_MALLOC_F_LEN
|
||||
default 0x2000
|
||||
default 0x2000 if !SPL_SHARES_INIT_SP_ADDR
|
||||
|
||||
config SPL_DRIVERS_MISC
|
||||
default y
|
||||
@@ -177,6 +180,9 @@ config SPL_SERIAL
|
||||
config TPL_STACK
|
||||
default 0xff718000
|
||||
|
||||
config TPL_SYS_MALLOC_F_LEN
|
||||
default 0x2000
|
||||
|
||||
config TPL_TEXT_BASE
|
||||
default 0xff704000
|
||||
|
||||
|
||||
@@ -216,3 +216,19 @@ int arch_cpu_init(void)
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#define RK3308_GRF_CHIP_ID 0xFF000800
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
u32 chip_id = readl(RK3308_GRF_CHIP_ID);
|
||||
|
||||
if (chip_id == 0x3308)
|
||||
printf("SoC: RK3308B\n");
|
||||
else if (chip_id == 0x3308c)
|
||||
printf("SoC: RK3308B-S\n");
|
||||
else
|
||||
printf("SoC: RK3308\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -146,15 +146,6 @@ config SYS_SOC
|
||||
config ROCKCHIP_COMMON_STACK_ADDR
|
||||
default y
|
||||
|
||||
config SYS_MALLOC_F_LEN
|
||||
default 0x4000 if !SPL_SHARES_INIT_SP_ADDR
|
||||
|
||||
config SPL_LIBCOMMON_SUPPORT
|
||||
default y
|
||||
|
||||
config SPL_LIBGENERIC_SUPPORT
|
||||
default y
|
||||
|
||||
config TPL_LDSCRIPT
|
||||
default "arch/arm/mach-rockchip/u-boot-tpl-v8.lds"
|
||||
|
||||
@@ -164,9 +155,6 @@ config TPL_STACK
|
||||
config TPL_TEXT_BASE
|
||||
default 0xff8c2000
|
||||
|
||||
config SPL_STACK_R_ADDR
|
||||
default 0x04000000 if !SPL_SHARES_INIT_SP_ADDR
|
||||
|
||||
if BOOTCOUNT_LIMIT
|
||||
|
||||
config BOOTCOUNT_BOOTLIMIT
|
||||
|
||||
@@ -7,7 +7,6 @@
|
||||
#include <init.h>
|
||||
#include <log.h>
|
||||
#include <spl.h>
|
||||
#include <spl_gpio.h>
|
||||
#include <syscon.h>
|
||||
#include <asm/armv8/mmu.h>
|
||||
#include <asm/arch-rockchip/bootrom.h>
|
||||
@@ -16,6 +15,7 @@
|
||||
#include <asm/arch-rockchip/gpio.h>
|
||||
#include <asm/arch-rockchip/grf_rk3399.h>
|
||||
#include <asm/arch-rockchip/hardware.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/printk.h>
|
||||
#include <power/regulator.h>
|
||||
@@ -133,27 +133,6 @@ void board_debug_uart_init(void)
|
||||
GRF_GPIO3B7_SEL_MASK,
|
||||
GRF_UART3_SOUT << GRF_GPIO3B7_SEL_SHIFT);
|
||||
#else
|
||||
struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE;
|
||||
struct rockchip_gpio_regs * const gpio = (void *)GPIO0_BASE;
|
||||
|
||||
if (IS_ENABLED(CONFIG_XPL_BUILD) &&
|
||||
(IS_ENABLED(CONFIG_TARGET_CHROMEBOOK_BOB) ||
|
||||
IS_ENABLED(CONFIG_TARGET_CHROMEBOOK_KEVIN))) {
|
||||
rk_setreg(&grf->io_vsel, 1 << 0);
|
||||
|
||||
/*
|
||||
* Let's enable these power rails here, we are already running
|
||||
* the SPI-Flash-based code.
|
||||
*/
|
||||
spl_gpio_output(gpio, GPIO(BANK_B, 2), 1); /* PP1500_EN */
|
||||
spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 2),
|
||||
GPIO_PULL_NORMAL);
|
||||
|
||||
spl_gpio_output(gpio, GPIO(BANK_B, 4), 1); /* PP3000_EN */
|
||||
spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 4),
|
||||
GPIO_PULL_NORMAL);
|
||||
}
|
||||
|
||||
/* Enable early UART2 channel C on the RK3399 */
|
||||
rk_clrsetreg(&grf->gpio4c_iomux,
|
||||
GRF_GPIO4C3_SEL_MASK,
|
||||
|
||||
@@ -3,7 +3,10 @@
|
||||
* (C) Copyright 2021 Rockchip Electronics Co., Ltd
|
||||
*/
|
||||
|
||||
#define LOG_CATEGORY LOGC_ARCH
|
||||
|
||||
#include <dm.h>
|
||||
#include <misc.h>
|
||||
#include <asm/armv8/mmu.h>
|
||||
#include <asm/arch-rockchip/bootrom.h>
|
||||
#include <asm/arch-rockchip/grf_rk3568.h>
|
||||
@@ -139,3 +142,61 @@ int arch_cpu_init(void)
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
#define RK3568_OTP_CPU_CODE_OFFSET 0x02
|
||||
#define RK3568_OTP_SPECIFICATION_OFFSET 0x07
|
||||
#define RK3568_OTP_PERFORMANCE_OFFSET 0x22
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
u8 cpu_code[2], specification, package, performance;
|
||||
struct udevice *dev;
|
||||
char suffix[3];
|
||||
int ret;
|
||||
|
||||
if (!IS_ENABLED(CONFIG_ROCKCHIP_OTP) || !CONFIG_IS_ENABLED(MISC))
|
||||
return 0;
|
||||
|
||||
ret = uclass_get_device_by_driver(UCLASS_MISC,
|
||||
DM_DRIVER_GET(rockchip_otp), &dev);
|
||||
if (ret) {
|
||||
log_debug("Could not find otp device, ret=%d\n", ret);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* cpu-code: SoC model, e.g. 0x35 0x66 or 0x35 0x68 */
|
||||
ret = misc_read(dev, RK3568_OTP_CPU_CODE_OFFSET, cpu_code, 2);
|
||||
if (ret < 0) {
|
||||
log_debug("Could not read cpu-code, ret=%d\n", ret);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* specification: SoC variant, e.g. 0x2 for RK3568B2 and 0xA for RK3568J */
|
||||
ret = misc_read(dev, RK3568_OTP_SPECIFICATION_OFFSET, &specification, 1);
|
||||
if (ret < 0) {
|
||||
log_debug("Could not read specification, ret=%d\n", ret);
|
||||
return 0;
|
||||
}
|
||||
/* package: likely SoC variant revision, 0x2 for RK3568B2 */
|
||||
package = specification >> 5;
|
||||
specification &= 0x1f;
|
||||
|
||||
/* performance: used to identify RK3566T SoC variant */
|
||||
ret = misc_read(dev, RK3568_OTP_PERFORMANCE_OFFSET, &performance, 1);
|
||||
if (ret < 0) {
|
||||
log_debug("Could not read performance, ret=%d\n", ret);
|
||||
return 0;
|
||||
}
|
||||
if (performance & 0x0f)
|
||||
specification = 0x14; /* T-variant */
|
||||
|
||||
/* for RK3568J i.e. '@' + 0xA = 'J' */
|
||||
suffix[0] = specification > 1 ? '@' + specification : '\0';
|
||||
/* for RK3568B2 i.e. '0' + 0x2 = '2' */
|
||||
suffix[1] = package > 1 ? '0' + package : '\0';
|
||||
suffix[2] = '\0';
|
||||
|
||||
printf("SoC: RK%02x%02x%s\n", cpu_code[0], cpu_code[1], suffix);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -74,6 +74,28 @@ config TARGET_JAGUAR_RK3588
|
||||
- fan controller (AMC6821 emulation)
|
||||
* 80-pin Mezzanine connector
|
||||
|
||||
config TARGET_KHADAS_EDGE2_RK3588
|
||||
bool "Khadas Edge2 RK3588 board"
|
||||
select BOARD_LATE_INIT
|
||||
help
|
||||
Khadas Edge2 is a Rockchip RK3588S based SBC (Single Board Computer)
|
||||
by Khadas.
|
||||
|
||||
There are tree variants depending on the DRAM size : 8G and 16G.
|
||||
|
||||
Specification:
|
||||
|
||||
Rockchip RK3588S SoC
|
||||
4x ARM Cortex-A76, 4x ARM Cortex-A55
|
||||
8/16GB memory LPDDR4x
|
||||
Mali G610MP4 GPU
|
||||
3x MIPI CSI 4x lanes
|
||||
2x MIPI-DSI DPHY 4x lanes
|
||||
32/64GB eMMC
|
||||
1x USB 2.0, 1x USB 3.0, 2x USB-Type-C
|
||||
1x HDMI 2.1 output, 1x DP 1.4 output
|
||||
USB PD over USB Type-C
|
||||
|
||||
config TARGET_NANOPCT6_RK3588
|
||||
bool "FriendlyElec NanoPC-T6 RK3588 board"
|
||||
select BOARD_LATE_INIT
|
||||
@@ -260,6 +282,26 @@ config TARGET_ROCK_5_ITX_RK3588
|
||||
Front-panel connectors for audio and case-power, -leds
|
||||
Powered by either 12V, ATX power-supply or PoE
|
||||
|
||||
config TARGET_ROCK_5C_RK3588S
|
||||
bool "Radxa ROCK 5C RK3588S2 board"
|
||||
select BOARD_LATE_INIT
|
||||
help
|
||||
Radxa ROCK 5C is a Rockchip RK3588S2 based single board computer.
|
||||
|
||||
Specification:
|
||||
|
||||
Quad A76 and Quad A55 CPU
|
||||
6 TOPS NPU
|
||||
up to 32GB LPDDR4x RAM
|
||||
eMMC / SPI flash connector
|
||||
Micro SD Card slot
|
||||
Gigabit ethernet port (supports PoE with add-on PoE HAT)
|
||||
WiFi6 / BT5.4
|
||||
1x USB 3.0 Type-A HOST port
|
||||
1x USB 3.0 Type-A OTG port
|
||||
2x USB 2.0 Type-A HOST port
|
||||
1x USB Type-C 5V power port
|
||||
|
||||
config TARGET_SIGE7_RK3588
|
||||
bool "ArmSoM Sige7 RK3588 board"
|
||||
select BOARD_LATE_INIT
|
||||
@@ -393,11 +435,13 @@ source "board/friendlyelec/nanopi-r6c-rk3588s/Kconfig"
|
||||
source "board/friendlyelec/nanopi-r6s-rk3588s/Kconfig"
|
||||
source "board/hardkernel/odroid_m2/Kconfig"
|
||||
source "board/indiedroid/nova/Kconfig"
|
||||
source "board/khadas/khadas-edge2-rk3588s/Kconfig"
|
||||
source "board/pine64/quartzpro64-rk3588/Kconfig"
|
||||
source "board/turing/turing-rk1-rk3588/Kconfig"
|
||||
source "board/radxa/rock5a-rk3588s/Kconfig"
|
||||
source "board/radxa/rock5b-rk3588/Kconfig"
|
||||
source "board/radxa/rock-5-itx-rk3588/Kconfig"
|
||||
source "board/radxa/rock-5c-rk3588s/Kconfig"
|
||||
source "board/rockchip/evb_rk3588/Kconfig"
|
||||
source "board/rockchip/toybrick_rk3588/Kconfig"
|
||||
source "board/theobroma-systems/jaguar_rk3588/Kconfig"
|
||||
|
||||
@@ -4,6 +4,10 @@
|
||||
* Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
|
||||
*/
|
||||
|
||||
#define LOG_CATEGORY LOGC_ARCH
|
||||
|
||||
#include <dm.h>
|
||||
#include <misc.h>
|
||||
#include <spl.h>
|
||||
#include <asm/armv8/mmu.h>
|
||||
#include <asm/arch-rockchip/bootrom.h>
|
||||
@@ -178,3 +182,51 @@ int arch_cpu_init(void)
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#define RK3588_OTP_CPU_CODE_OFFSET 0x02
|
||||
#define RK3588_OTP_SPECIFICATION_OFFSET 0x06
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
u8 cpu_code[2], specification, package;
|
||||
struct udevice *dev;
|
||||
char suffix[3];
|
||||
int ret;
|
||||
|
||||
if (!IS_ENABLED(CONFIG_ROCKCHIP_OTP) || !CONFIG_IS_ENABLED(MISC))
|
||||
return 0;
|
||||
|
||||
ret = uclass_get_device_by_driver(UCLASS_MISC,
|
||||
DM_DRIVER_GET(rockchip_otp), &dev);
|
||||
if (ret) {
|
||||
log_debug("Could not find otp device, ret=%d\n", ret);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* cpu-code: SoC model, e.g. 0x35 0x82 or 0x35 0x88 */
|
||||
ret = misc_read(dev, RK3588_OTP_CPU_CODE_OFFSET, cpu_code, 2);
|
||||
if (ret < 0) {
|
||||
log_debug("Could not read cpu-code, ret=%d\n", ret);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* specification: SoC variant, e.g. 0xA for RK3588J and 0x13 for RK3588S */
|
||||
ret = misc_read(dev, RK3588_OTP_SPECIFICATION_OFFSET, &specification, 1);
|
||||
if (ret < 0) {
|
||||
log_debug("Could not read specification, ret=%d\n", ret);
|
||||
return 0;
|
||||
}
|
||||
/* package: likely SoC variant revision, 0x2 for RK3588S2 */
|
||||
package = specification >> 5;
|
||||
specification &= 0x1f;
|
||||
|
||||
/* for RK3588J i.e. '@' + 0xA = 'J' */
|
||||
suffix[0] = specification > 1 ? '@' + specification : '\0';
|
||||
/* for RK3588S2 i.e. '0' + 0x2 = '2' */
|
||||
suffix[1] = package > 1 ? '0' + package : '\0';
|
||||
suffix[2] = '\0';
|
||||
|
||||
printf("SoC: RK%02x%02x%s\n", cpu_code[0], cpu_code[1], suffix);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -1,6 +1,7 @@
|
||||
FIREFLY
|
||||
M: Simon Glass <sjg@chromium.org>
|
||||
S: Maintained
|
||||
F: arch/arm/dts/rk3288-firefly-u-boot.dtsi
|
||||
F: board/firefly/firefly-rk3288
|
||||
F: include/configs/firefly-rk3288.h
|
||||
F: configs/firefly-rk3288_defconfig
|
||||
|
||||
@@ -1,7 +0,0 @@
|
||||
#
|
||||
# (C) Copyright 2015 Google, Inc
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y += firefly-rk3288.o
|
||||
@@ -1,46 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* (C) Copyright 2015 Google, Inc
|
||||
*/
|
||||
|
||||
#include <hang.h>
|
||||
#include <led.h>
|
||||
#include <log.h>
|
||||
#include <asm/global_data.h>
|
||||
#include <dm/ofnode.h>
|
||||
|
||||
#ifdef CONFIG_XPL_BUILD
|
||||
static int setup_led(void)
|
||||
{
|
||||
#ifdef CONFIG_SPL_LED
|
||||
struct udevice *dev;
|
||||
char *led_name;
|
||||
int ret;
|
||||
|
||||
led_name = ofnode_conf_read_str("u-boot,boot-led");
|
||||
if (!led_name)
|
||||
return 0;
|
||||
ret = led_get_by_label(led_name, &dev);
|
||||
if (ret) {
|
||||
debug("%s: get=%d\n", __func__, ret);
|
||||
return ret;
|
||||
}
|
||||
ret = led_set_state(dev, LEDST_ON);
|
||||
if (ret)
|
||||
return ret;
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void spl_board_init(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = setup_led();
|
||||
if (ret) {
|
||||
debug("LED ret=%d\n", ret);
|
||||
hang();
|
||||
}
|
||||
}
|
||||
#endif
|
||||
@@ -5,5 +5,4 @@ S: Maintained
|
||||
F: board/friendlyelec/nanopc-t6-rk3588
|
||||
F: include/configs/nanopc-t6-rk3588.h
|
||||
F: configs/nanopc-t6-rk3588_defconfig
|
||||
F: arch/arm/dts/rk3588-nanopc-t6.dts
|
||||
F: arch/arm/dts/rk3588-nanopc-t6-u-boot.dtsi
|
||||
F: arch/arm/dts/rk3588-nanopc-t6*
|
||||
|
||||
12
board/khadas/khadas-edge2-rk3588s/Kconfig
Normal file
12
board/khadas/khadas-edge2-rk3588s/Kconfig
Normal file
@@ -0,0 +1,12 @@
|
||||
if TARGET_KHADAS_EDGE2_RK3588
|
||||
|
||||
config SYS_BOARD
|
||||
default "khadas-edge2-rk3588s"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "khadas"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "khadas-edge2-rk3588s"
|
||||
|
||||
endif
|
||||
6
board/khadas/khadas-edge2-rk3588s/MAINTAINERS
Normal file
6
board/khadas/khadas-edge2-rk3588s/MAINTAINERS
Normal file
@@ -0,0 +1,6 @@
|
||||
KHADAS-EDGE2-RK3588S
|
||||
M: Jacobe Zang <jacobe.zang@wesion.com>
|
||||
S: Maintained
|
||||
F: configs/khadas-edge2-rk3588s_defconfig
|
||||
F: include/configs/khadas-edge2-rk3588s.h
|
||||
F: dts/upstream/src/arm64/rockchip/rk3588s-khadas-edge2.dts
|
||||
@@ -1,7 +1,6 @@
|
||||
MIQI
|
||||
M: Jernej Skrabec <jernej.skrabec@siol.net>
|
||||
S: Maintained
|
||||
F: arch/arm/dts/rk3288-miqi.dts
|
||||
F: arch/arm/dts/rk3288-miqi-u-boot.dtsi
|
||||
F: board/mqmaker/miqi_rk3288
|
||||
F: include/configs/miqi_rk3288.h
|
||||
|
||||
12
board/radxa/rock-5c-rk3588s/Kconfig
Normal file
12
board/radxa/rock-5c-rk3588s/Kconfig
Normal file
@@ -0,0 +1,12 @@
|
||||
if TARGET_ROCK_5C_RK3588S
|
||||
|
||||
config SYS_BOARD
|
||||
default "rock-5c-rk3588s"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "radxa"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "rock-5c-rk3588s"
|
||||
|
||||
endif
|
||||
7
board/radxa/rock-5c-rk3588s/MAINTAINERS
Normal file
7
board/radxa/rock-5c-rk3588s/MAINTAINERS
Normal file
@@ -0,0 +1,7 @@
|
||||
ROCK-5C-RK3588S
|
||||
M: FUKAUMI Naoki <naoki@radxa.com>
|
||||
S: Maintained
|
||||
F: arch/arm/dts/rk3588s-rock-5c-u-boot.dtsi
|
||||
F: board/radxa/rock-5c-rk3588s/
|
||||
F: configs/rock-5c-rk3588s_defconfig
|
||||
F: include/configs/rock-5c-rk3588s.h
|
||||
@@ -52,6 +52,8 @@ void rockchip_capsule_update_board_setup(void)
|
||||
|
||||
fw_images[0].fw_name = u"ROCKPI4C-IDBLOADER";
|
||||
fw_images[1].fw_name = u"ROCKPI4C-UBOOT";
|
||||
} else {
|
||||
update_info.num_images = 0;
|
||||
}
|
||||
}
|
||||
#endif /* CONFIG_EFI_HAVE_CAPSULE_SUPPORT && CONFIG_EFI_PARTITION */
|
||||
|
||||
@@ -28,6 +28,13 @@ F: configs/lubancat-2-rk3568_defconfig
|
||||
F: arch/arm/dts/rk3568-lubancat-2.dts
|
||||
F: arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi
|
||||
|
||||
NANOPI-R3S
|
||||
M: Tianling Shen <cnsztl@gmail.com>
|
||||
R: Jonas Karlman <jonas@kwiboo.se>
|
||||
S: Maintained
|
||||
F: configs/nanopi-r3s-rk3566_defconfig
|
||||
F: arch/arm/dts/rk3566-nanopi-r3s-u-boot.dtsi
|
||||
|
||||
NANOPI-R5C
|
||||
M: Tianling Shen <cnsztl@gmail.com>
|
||||
R: Jonas Karlman <jonas@kwiboo.se>
|
||||
|
||||
@@ -1,10 +1,7 @@
|
||||
TINKER-RK3288
|
||||
M: Lin Huang <hl@rock-chips.com>
|
||||
R: Jonas Karlman <jonas@kwiboo.se>
|
||||
S: Maintained
|
||||
F: arch/arm/dts/rk3288-tinker.dts
|
||||
F: arch/arm/dts/rk3288-tinker.dtsi
|
||||
F: arch/arm/dts/rk3288-tinker-s.dts
|
||||
F: arch/arm/dts/rk3288-tinker-s-u-boot.dtsi
|
||||
F: arch/arm/dts/rk3288-tinker-u-boot.dtsi
|
||||
F: board/rockchip/tinker_rk3288
|
||||
F: include/configs/tinker_rk3288.h
|
||||
@@ -12,7 +9,9 @@ F: configs/tinker-rk3288_defconfig
|
||||
|
||||
TINKER-S-RK3288
|
||||
M: Michael Trimarchi <michael@amarulasolutions.com>
|
||||
R: Jonas Karlman <jonas@kwiboo.se>
|
||||
S: Maintained
|
||||
F: arch/arm/dts/rk3288-tinker-s-u-boot.dtsi
|
||||
F: board/rockchip/tinker_rk3288
|
||||
F: include/configs/tinker_rk3288.h
|
||||
F: configs/tinker-s-rk3288_defconfig
|
||||
|
||||
@@ -22,7 +22,7 @@ static int get_ethaddr_from_eeprom(u8 *addr)
|
||||
return i2c_eeprom_read(dev, 0, addr, 6);
|
||||
}
|
||||
|
||||
int rk3288_board_late_init(void)
|
||||
int rockchip_early_misc_init_r(void)
|
||||
{
|
||||
u8 ethaddr[6];
|
||||
|
||||
|
||||
@@ -1,28 +1,16 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
CONFIG_SPL_SYS_DCACHE_OFF=y
|
||||
CONFIG_COUNTER_FREQUENCY=24000000
|
||||
CONFIG_ARCH_ROCKCHIP=y
|
||||
CONFIG_TEXT_BASE=0x00200000
|
||||
CONFIG_SPL_GPIO=y
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
|
||||
CONFIG_SF_DEFAULT_SPEED=20000000
|
||||
CONFIG_ENV_OFFSET=0x3F8000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-gru-bob"
|
||||
CONFIG_DM_RESET=y
|
||||
CONFIG_ROCKCHIP_RK3399=y
|
||||
CONFIG_ROCKCHIP_BOOT_MODE_REG=0
|
||||
CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000
|
||||
# CONFIG_SPL_MMC is not set
|
||||
CONFIG_SPL_STACK=0xff8effff
|
||||
CONFIG_SPL_TEXT_BASE=0xff8c2000
|
||||
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
CONFIG_SPL_BSS_START_ADDR=0xff8e0000
|
||||
CONFIG_SPL_BSS_MAX_SIZE=0x10000
|
||||
CONFIG_SPL_STACK_R=y
|
||||
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
|
||||
CONFIG_SYS_LOAD_ADDR=0x800800
|
||||
CONFIG_SF_DEFAULT_BUS=1
|
||||
CONFIG_DEBUG_UART_BASE=0xff1a0000
|
||||
@@ -30,22 +18,22 @@ CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
CONFIG_SPL_SPI_FLASH_SUPPORT=y
|
||||
CONFIG_SPL_SPI=y
|
||||
CONFIG_DEBUG_UART=y
|
||||
# CONFIG_SPL_FIT_SIGNATURE is not set
|
||||
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-bob.dtb"
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
CONFIG_BOARD_EARLY_INIT_R=y
|
||||
CONFIG_BLOBLIST=y
|
||||
# CONFIG_TPL_BLOBLIST is not set
|
||||
CONFIG_BLOBLIST_ADDR=0x100000
|
||||
CONFIG_BLOBLIST_SIZE=0x1000
|
||||
CONFIG_SPL_MAX_SIZE=0x1e000
|
||||
CONFIG_SPL_MAX_SIZE=0x40000
|
||||
CONFIG_SPL_PAD_TO=0x7f8000
|
||||
CONFIG_HANDOFF=y
|
||||
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
||||
CONFIG_SPL_SPI_LOAD=y
|
||||
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
|
||||
CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000
|
||||
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
|
||||
CONFIG_TPL=y
|
||||
CONFIG_CMD_BOOTZ=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_GPT=y
|
||||
@@ -60,7 +48,7 @@ CONFIG_CMD_PMIC=y
|
||||
CONFIG_CMD_REGULATOR=y
|
||||
CONFIG_CMD_LOG=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_ROCKCHIP_GPIO=y
|
||||
@@ -76,6 +64,7 @@ CONFIG_MMC_PWRSEQ=y
|
||||
CONFIG_MMC_DW=y
|
||||
CONFIG_MMC_DW_ROCKCHIP=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_SDMA=y
|
||||
CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
@@ -85,6 +74,7 @@ CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
||||
CONFIG_PHY_ROCKCHIP_TYPEC=y
|
||||
CONFIG_PMIC_RK8XX=y
|
||||
CONFIG_REGULATOR_PWM=y
|
||||
CONFIG_SPL_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DM_REGULATOR_GPIO=y
|
||||
CONFIG_REGULATOR_RK8XX=y
|
||||
CONFIG_PWM_CROS_EC=y
|
||||
|
||||
@@ -1,29 +1,17 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
CONFIG_SPL_SYS_DCACHE_OFF=y
|
||||
CONFIG_COUNTER_FREQUENCY=24000000
|
||||
CONFIG_ARCH_ROCKCHIP=y
|
||||
CONFIG_TEXT_BASE=0x00200000
|
||||
CONFIG_SPL_GPIO=y
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
|
||||
CONFIG_SF_DEFAULT_SPEED=20000000
|
||||
CONFIG_ENV_OFFSET=0x3F8000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-gru-kevin"
|
||||
CONFIG_DM_RESET=y
|
||||
CONFIG_ROCKCHIP_RK3399=y
|
||||
CONFIG_ROCKCHIP_BOOT_MODE_REG=0
|
||||
CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000
|
||||
# CONFIG_SPL_MMC is not set
|
||||
CONFIG_TARGET_CHROMEBOOK_KEVIN=y
|
||||
CONFIG_SPL_STACK=0xff8effff
|
||||
CONFIG_SPL_TEXT_BASE=0xff8c2000
|
||||
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
CONFIG_SPL_BSS_START_ADDR=0xff8e0000
|
||||
CONFIG_SPL_BSS_MAX_SIZE=0x10000
|
||||
CONFIG_SPL_STACK_R=y
|
||||
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
|
||||
CONFIG_SYS_LOAD_ADDR=0x800800
|
||||
CONFIG_SF_DEFAULT_BUS=1
|
||||
CONFIG_DEBUG_UART_BASE=0xff1a0000
|
||||
@@ -31,22 +19,22 @@ CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
CONFIG_SPL_SPI_FLASH_SUPPORT=y
|
||||
CONFIG_SPL_SPI=y
|
||||
CONFIG_DEBUG_UART=y
|
||||
# CONFIG_SPL_FIT_SIGNATURE is not set
|
||||
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-kevin.dtb"
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
CONFIG_BOARD_EARLY_INIT_R=y
|
||||
CONFIG_BLOBLIST=y
|
||||
# CONFIG_TPL_BLOBLIST is not set
|
||||
CONFIG_BLOBLIST_ADDR=0x100000
|
||||
CONFIG_BLOBLIST_SIZE=0x1000
|
||||
CONFIG_SPL_MAX_SIZE=0x1e000
|
||||
CONFIG_SPL_MAX_SIZE=0x40000
|
||||
CONFIG_SPL_PAD_TO=0x7f8000
|
||||
CONFIG_HANDOFF=y
|
||||
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
||||
CONFIG_SPL_SPI_LOAD=y
|
||||
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
|
||||
CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000
|
||||
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
|
||||
CONFIG_TPL=y
|
||||
CONFIG_CMD_BOOTZ=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_GPT=y
|
||||
@@ -61,7 +49,7 @@ CONFIG_CMD_PMIC=y
|
||||
CONFIG_CMD_REGULATOR=y
|
||||
CONFIG_CMD_LOG=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_ROCKCHIP_GPIO=y
|
||||
@@ -77,6 +65,7 @@ CONFIG_MMC_PWRSEQ=y
|
||||
CONFIG_MMC_DW=y
|
||||
CONFIG_MMC_DW_ROCKCHIP=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_SDMA=y
|
||||
CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
@@ -86,6 +75,7 @@ CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
||||
CONFIG_PHY_ROCKCHIP_TYPEC=y
|
||||
CONFIG_PMIC_RK8XX=y
|
||||
CONFIG_REGULATOR_PWM=y
|
||||
CONFIG_SPL_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DM_REGULATOR_GPIO=y
|
||||
CONFIG_REGULATOR_RK8XX=y
|
||||
CONFIG_PWM_CROS_EC=y
|
||||
|
||||
@@ -4,20 +4,13 @@ CONFIG_TPL_SKIP_LOWLEVEL_INIT_ONLY=y
|
||||
CONFIG_SYS_ARCH_TIMER=y
|
||||
CONFIG_ARCH_ROCKCHIP=y
|
||||
CONFIG_TEXT_BASE=0x01000000
|
||||
CONFIG_SPL_GPIO=y
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000
|
||||
CONFIG_SF_DEFAULT_SPEED=20000000
|
||||
CONFIG_ENV_OFFSET=0x3F8000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rk3288-firefly"
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3288-firefly"
|
||||
CONFIG_DM_RESET=y
|
||||
CONFIG_SYS_MONITOR_LEN=614400
|
||||
CONFIG_ROCKCHIP_RK3288=y
|
||||
CONFIG_TARGET_FIREFLY_RK3288=y
|
||||
CONFIG_SPL_STACK_R_ADDR=0x80000
|
||||
CONFIG_SPL_STACK=0xff718000
|
||||
CONFIG_SPL_STACK_R=y
|
||||
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
|
||||
CONFIG_SYS_BOOTM_LEN=0x4000000
|
||||
CONFIG_SYS_LOAD_ADDR=0x800800
|
||||
CONFIG_SPL_SIZE_LIMIT=0x40000
|
||||
@@ -25,13 +18,15 @@ CONFIG_DEBUG_UART_BASE=0xff690000
|
||||
CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
CONFIG_DEBUG_UART=y
|
||||
# CONFIG_ANDROID_BOOT_IMAGE is not set
|
||||
CONFIG_USE_PREBOOT=y
|
||||
CONFIG_DEFAULT_FDT_FILE="rk3288-firefly.dtb"
|
||||
CONFIG_SILENT_CONSOLE=y
|
||||
CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_SPL_FIT_SIGNATURE=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
CONFIG_LEGACY_IMAGE_FORMAT=y
|
||||
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3288-firefly.dtb"
|
||||
CONFIG_MISC_INIT_R=y
|
||||
CONFIG_SPL_PAD_TO=0x7f8000
|
||||
CONFIG_SPL_NO_BSS_LIMIT=y
|
||||
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
||||
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_GPT=y
|
||||
CONFIG_CMD_I2C=y
|
||||
@@ -47,10 +42,12 @@ CONFIG_CMD_REGULATOR=y
|
||||
# CONFIG_SPL_DOS_PARTITION is not set
|
||||
# CONFIG_SPL_EFI_PARTITION is not set
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
CONFIG_OF_LIVE=y
|
||||
CONFIG_OF_UPSTREAM=y
|
||||
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_SPL_DM_SEQ_ALIAS=y
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_SPL_REGMAP=y
|
||||
CONFIG_SYSCON=y
|
||||
@@ -63,17 +60,22 @@ CONFIG_ROCKCHIP_GPIO=y
|
||||
CONFIG_SYS_I2C_ROCKCHIP=y
|
||||
CONFIG_LED=y
|
||||
CONFIG_LED_GPIO=y
|
||||
CONFIG_MISC=y
|
||||
CONFIG_ROCKCHIP_EFUSE=y
|
||||
CONFIG_MMC_DW=y
|
||||
CONFIG_MMC_DW_ROCKCHIP=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_DM_ETH_PHY=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_ETH_DESIGNWARE=y
|
||||
CONFIG_GMAC_ROCKCHIP=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_SPL_PINCTRL=y
|
||||
CONFIG_DM_PMIC=y
|
||||
# CONFIG_SPL_PMIC_CHILDREN is not set
|
||||
CONFIG_PMIC_ACT8846=y
|
||||
CONFIG_REGULATOR_ACT8846=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_SPL_DM_REGULATOR_FIXED=y
|
||||
CONFIG_PWM_ROCKCHIP=y
|
||||
CONFIG_RAM=y
|
||||
CONFIG_SPL_RAM=y
|
||||
@@ -96,4 +98,5 @@ CONFIG_VIDEO_ROCKCHIP=y
|
||||
CONFIG_DISPLAY_ROCKCHIP_HDMI=y
|
||||
CONFIG_CONSOLE_SCROLL_LINES=10
|
||||
CONFIG_CMD_DHRYSTONE=y
|
||||
CONFIG_SPL_CRC32=y
|
||||
CONFIG_ERRNO_STR=y
|
||||
|
||||
215
configs/khadas-edge2-rk3588s_defconfig
Normal file
215
configs/khadas-edge2-rk3588s_defconfig
Normal file
@@ -0,0 +1,215 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
CONFIG_COUNTER_FREQUENCY=24000000
|
||||
CONFIG_ARCH_ROCKCHIP=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588s-khadas-edge2"
|
||||
CONFIG_SPL_GPIO_SUPPORT=y
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x80000
|
||||
CONFIG_ROCKCHIP_RK3588=y
|
||||
CONFIG_ROCKCHIP_FIT_IMAGE=y
|
||||
CONFIG_SPL_SERIAL=y
|
||||
CONFIG_TARGET_KHADAS_EDGE2_RK3588=y
|
||||
CONFIG_DEBUG_UART_BASE=0xFEB50000
|
||||
CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
CONFIG_SYS_LOAD_ADDR=0xc00800
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_SPL_FIT_SIGNATURE=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
CONFIG_LEGACY_IMAGE_FORMAT=y
|
||||
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-khadas-edge2.dtb"
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
CONFIG_SPL_MAX_SIZE=0x40000
|
||||
CONFIG_SPL_PAD_TO=0x7f8000
|
||||
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
CONFIG_SPL_SEPARATE_BSS=y
|
||||
CONFIG_SPL_MMC_WRITE=y
|
||||
CONFIG_SPL_MTD_SUPPORT=y
|
||||
CONFIG_SPL_ATF=y
|
||||
CONFIG_SPL_AB=y
|
||||
CONFIG_SYS_PROMPT="kedge2# "
|
||||
CONFIG_AUTOBOOT_KEYED=y
|
||||
CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot\n"
|
||||
CONFIG_AUTOBOOT_STOP_STR=" "
|
||||
CONFIG_CMD_BOOTZ=y
|
||||
CONFIG_CMD_DTIMG=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_GPT=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_SPL_SPI_SUPPORT=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_DM_MMC=y
|
||||
# CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_MMC=y
|
||||
# CONFIG_MMC_SPI=y
|
||||
CONFIG_CMD_SF=y
|
||||
CONFIG_CMD_SPI=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_USB_MASS_STORAGE=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_REGULATOR=y
|
||||
CONFIG_CMD_TFTPPUT=y
|
||||
CONFIG_CMD_TFTP_BOOTM=y
|
||||
CONFIG_CMD_TFTP_FLASH=y
|
||||
CONFIG_CMD_MTD_BLK=y
|
||||
# CONFIG_SPL_DOS_PARTITION is not set
|
||||
CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_SPL_DTB_MINIMUM=y
|
||||
CONFIG_OF_LIVE=y
|
||||
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
CONFIG_SPL_DM_SEQ_ALIAS=y
|
||||
CONFIG_OF_U_BOOT_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_SPL_REGMAP=y
|
||||
CONFIG_SYSCON=y
|
||||
CONFIG_SPL_SYSCON=y
|
||||
CONFIG_SARADC_ROCKCHIP_V2=y
|
||||
CONFIG_CLK=y
|
||||
CONFIG_SPL_CLK=y
|
||||
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
|
||||
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x1
|
||||
CONFIG_FASTBOOT_BUF_ADDR=0xc00800
|
||||
CONFIG_FASTBOOT_BUF_SIZE=0x07000000
|
||||
CONFIG_FASTBOOT_FLASH=y
|
||||
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
|
||||
CONFIG_ROCKCHIP_GPIO=y
|
||||
CONFIG_ROCKCHIP_GPIO_V2=y
|
||||
CONFIG_SYS_I2C_ROCKCHIP=y
|
||||
CONFIG_I2C_MUX=y
|
||||
CONFIG_DM_KEY=y
|
||||
CONFIG_RK8XX_PWRKEY=y
|
||||
CONFIG_ADC_KEY=y
|
||||
CONFIG_MISC=y
|
||||
CONFIG_SUPPORT_EMMC_RPMB=y
|
||||
CONFIG_SPL_MISC=y
|
||||
CONFIG_MISC_DECOMPRESS=y
|
||||
CONFIG_SPL_MISC_DECOMPRESS=y
|
||||
CONFIG_ROCKCHIP_OTP=y
|
||||
CONFIG_ROCKCHIP_HW_DECOMPRESS=y
|
||||
CONFIG_SPL_ROCKCHIP_HW_DECOMPRESS=y
|
||||
CONFIG_SPL_ROCKCHIP_SECURE_OTP=y
|
||||
CONFIG_MMC_DW=y
|
||||
CONFIG_MMC_DW_ROCKCHIP=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_HS200_SUPPORT=y
|
||||
CONFIG_MMC_HS400_SUPPORT=y
|
||||
CONFIG_MMC_SDHCI_SDMA=y
|
||||
CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_BLK=y
|
||||
CONFIG_MTD_DEVICE=y
|
||||
# CONFIG_NAND=y
|
||||
# CONFIG_MTD_SPI_NAND=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_SPEED=80000000
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SST=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_SPI_FLASH_XMC=y
|
||||
CONFIG_SPI_FLASH_XTX=y
|
||||
CONFIG_SPI_FLASH_MTD=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_DM_ETH_PHY=y
|
||||
CONFIG_DWC_ETH_QOS=y
|
||||
CONFIG_DWC_ETH_QOS_ROCKCHIP=y
|
||||
CONFIG_GMAC_ROCKCHIP=y
|
||||
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
||||
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
|
||||
CONFIG_PHY_ROCKCHIP_USBDP=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_SPL_PINCTRL=y
|
||||
CONFIG_DM_FUEL_GAUGE=y
|
||||
CONFIG_POWER_FG_CW201X=y
|
||||
CONFIG_POWER_FG_CW221X=y
|
||||
CONFIG_DM_PMIC=y
|
||||
CONFIG_PMIC_SPI_RK8XX=y
|
||||
CONFIG_DM_POWER_DELIVERY=y
|
||||
CONFIG_TYPEC_TCPM=y
|
||||
CONFIG_TYPEC_TCPCI=y
|
||||
CONFIG_TYPEC_HUSB311=y
|
||||
CONFIG_TYPEC_FUSB302=y
|
||||
CONFIG_REGULATOR_PWM=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DM_REGULATOR_GPIO=y
|
||||
CONFIG_REGULATOR_RK860X=y
|
||||
CONFIG_REGULATOR_RK806=y
|
||||
CONFIG_CHARGER_BQ25700=y
|
||||
CONFIG_CHARGER_BQ25890=y
|
||||
CONFIG_CHARGER_SC8551=y
|
||||
CONFIG_CHARGER_SGM41542=y
|
||||
CONFIG_DM_CHARGE_DISPLAY=y
|
||||
CONFIG_CHARGE_ANIMATION=y
|
||||
CONFIG_PWM_ROCKCHIP=y
|
||||
CONFIG_RAM=y
|
||||
CONFIG_SPL_RAM=y
|
||||
CONFIG_TPL_RAM=y
|
||||
CONFIG_DM_RAMDISK=y
|
||||
CONFIG_RAMDISK_RO=y
|
||||
CONFIG_DM_RESET=y
|
||||
CONFIG_SPL_DM_RESET=y
|
||||
CONFIG_SPL_RESET_ROCKCHIP=y
|
||||
CONFIG_BAUDRATE=1500000
|
||||
CONFIG_DEBUG_UART_SHIFT=2
|
||||
CONFIG_SYS_NS16550_MEM32=y
|
||||
CONFIG_ROCKCHIP_SPI=y
|
||||
CONFIG_ROCKCHIP_SFC=y
|
||||
CONFIG_SYSRESET=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_GENERIC=y
|
||||
CONFIG_USB_OHCI_HCD=y
|
||||
CONFIG_USB_OHCI_GENERIC=y
|
||||
CONFIG_USB_DWC3=y
|
||||
CONFIG_USB_DWC3_GENERIC=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
|
||||
CONFIG_USB_GADGET_VENDOR_NUM=0x2207
|
||||
CONFIG_USB_GADGET_PRODUCT_NUM=0x350a
|
||||
CONFIG_USB_GADGET_DOWNLOAD=y
|
||||
CONFIG_DM_VIDEO=y
|
||||
CONFIG_DISPLAY=y
|
||||
CONFIG_DRM_ROCKCHIP=y
|
||||
CONFIG_DRM_MAXIM_MAX96745=y
|
||||
CONFIG_DRM_MAXIM_MAX96755F=y
|
||||
CONFIG_DRM_PANEL_ROHM_BU18RL82=y
|
||||
CONFIG_DRM_PANEL_MAXIM_MAX96752F=y
|
||||
CONFIG_DRM_ROHM_BU18XL82=y
|
||||
CONFIG_DRM_ROCKCHIP_DW_HDMI_QP=y
|
||||
CONFIG_DRM_ROCKCHIP_DW_MIPI_DSI2=y
|
||||
CONFIG_DRM_ROCKCHIP_DW_DP=y
|
||||
CONFIG_DRM_ROCKCHIP_ANALOGIX_DP=y
|
||||
CONFIG_DRM_ROCKCHIP_SAMSUNG_MIPI_DCPHY=y
|
||||
CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX_HDMI=y
|
||||
CONFIG_USE_TINY_PRINTF=y
|
||||
CONFIG_LIB_RAND=y
|
||||
CONFIG_SPL_TINY_MEMSET=y
|
||||
CONFIG_RSA=y
|
||||
CONFIG_SPL_RSA=y
|
||||
CONFIG_RSA_N_SIZE=0x200
|
||||
CONFIG_RSA_E_SIZE=0x10
|
||||
CONFIG_RSA_C_SIZE=0x20
|
||||
CONFIG_XBC=y
|
||||
CONFIG_LZ4=y
|
||||
CONFIG_LZMA=y
|
||||
CONFIG_ERRNO_STR=y
|
||||
CONFIG_AVB_LIBAVB=y
|
||||
CONFIG_AVB_LIBAVB_AB=y
|
||||
CONFIG_AVB_LIBAVB_ATX=y
|
||||
CONFIG_AVB_LIBAVB_USER=y
|
||||
CONFIG_RK_AVB_LIBAVB_USER=y
|
||||
CONFIG_OPTEE_CLIENT=y
|
||||
CONFIG_OPTEE_V2=y
|
||||
CONFIG_OPTEE_ALWAYS_USE_SECURITY_PARTITION=y
|
||||
@@ -1,37 +1,31 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y
|
||||
CONFIG_TPL_SKIP_LOWLEVEL_INIT_ONLY=y
|
||||
CONFIG_SYS_ARCH_TIMER=y
|
||||
CONFIG_ARCH_ROCKCHIP=y
|
||||
CONFIG_TEXT_BASE=0x00000000
|
||||
CONFIG_TEXT_BASE=0x01000000
|
||||
CONFIG_SPL_GPIO=y
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000
|
||||
CONFIG_SF_DEFAULT_SPEED=20000000
|
||||
CONFIG_ENV_OFFSET=0x3F8000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rk3288-miqi"
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3288-miqi"
|
||||
CONFIG_DM_RESET=y
|
||||
CONFIG_SYS_MONITOR_LEN=614400
|
||||
CONFIG_ROCKCHIP_RK3288=y
|
||||
CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
|
||||
CONFIG_TARGET_MIQI_RK3288=y
|
||||
CONFIG_SPL_STACK_R_ADDR=0x80000
|
||||
CONFIG_SPL_STACK=0xff718000
|
||||
CONFIG_SPL_TEXT_BASE=0xff704000
|
||||
CONFIG_SPL_STACK_R=y
|
||||
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
|
||||
CONFIG_SYS_BOOTM_LEN=0x4000000
|
||||
CONFIG_SYS_LOAD_ADDR=0x800800
|
||||
CONFIG_DEBUG_UART_BASE=0xff690000
|
||||
CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
CONFIG_DEBUG_UART=y
|
||||
# CONFIG_ANDROID_BOOT_IMAGE is not set
|
||||
CONFIG_USE_PREBOOT=y
|
||||
CONFIG_DEFAULT_FDT_FILE="rk3288-miqi.dtb"
|
||||
CONFIG_SILENT_CONSOLE=y
|
||||
CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_SPL_FIT_SIGNATURE=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
CONFIG_LEGACY_IMAGE_FORMAT=y
|
||||
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3288-miqi.dtb"
|
||||
CONFIG_MISC_INIT_R=y
|
||||
CONFIG_SPL_PAD_TO=0x7f8000
|
||||
CONFIG_SPL_NO_BSS_LIMIT=y
|
||||
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
||||
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_GPT=y
|
||||
CONFIG_CMD_I2C=y
|
||||
@@ -47,10 +41,12 @@ CONFIG_CMD_REGULATOR=y
|
||||
# CONFIG_SPL_DOS_PARTITION is not set
|
||||
# CONFIG_SPL_EFI_PARTITION is not set
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
CONFIG_OF_LIVE=y
|
||||
CONFIG_OF_UPSTREAM=y
|
||||
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_SPL_DM_SEQ_ALIAS=y
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_SPL_REGMAP=y
|
||||
CONFIG_SYSCON=y
|
||||
@@ -61,8 +57,13 @@ CONFIG_SPL_CLK=y
|
||||
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
|
||||
CONFIG_ROCKCHIP_GPIO=y
|
||||
CONFIG_SYS_I2C_ROCKCHIP=y
|
||||
CONFIG_MISC=y
|
||||
CONFIG_ROCKCHIP_EFUSE=y
|
||||
CONFIG_MMC_DW=y
|
||||
CONFIG_MMC_DW_ROCKCHIP=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_DM_ETH_PHY=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_ETH_DESIGNWARE=y
|
||||
CONFIG_GMAC_ROCKCHIP=y
|
||||
CONFIG_PINCTRL=y
|
||||
@@ -71,6 +72,7 @@ CONFIG_DM_PMIC=y
|
||||
CONFIG_PMIC_ACT8846=y
|
||||
CONFIG_REGULATOR_ACT8846=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_SPL_DM_REGULATOR_FIXED=y
|
||||
CONFIG_PWM_ROCKCHIP=y
|
||||
CONFIG_RAM=y
|
||||
CONFIG_SPL_RAM=y
|
||||
@@ -93,4 +95,5 @@ CONFIG_VIDEO_ROCKCHIP=y
|
||||
CONFIG_DISPLAY_ROCKCHIP_HDMI=y
|
||||
CONFIG_CONSOLE_SCROLL_LINES=10
|
||||
CONFIG_CMD_DHRYSTONE=y
|
||||
CONFIG_SPL_CRC32=y
|
||||
CONFIG_ERRNO_STR=y
|
||||
|
||||
@@ -14,7 +14,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x78000000
|
||||
CONFIG_SF_DEFAULT_SPEED=20000000
|
||||
CONFIG_ENV_SIZE=0x8000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rk3066a-mk808"
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3066a-mk808"
|
||||
CONFIG_DM_RESET=y
|
||||
CONFIG_ROCKCHIP_RK3066=y
|
||||
# CONFIG_ROCKCHIP_STIMER is not set
|
||||
@@ -35,7 +35,7 @@ CONFIG_SPL_PAYLOAD="u-boot.bin"
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_SD_BOOT=y
|
||||
CONFIG_USE_PREBOOT=y
|
||||
CONFIG_DEFAULT_FDT_FILE="rk3066a-mk808.dtb"
|
||||
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3066a-mk808.dtb"
|
||||
CONFIG_SYS_CBSIZE=256
|
||||
CONFIG_SYS_PBSIZE=276
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
|
||||
75
configs/nanopi-r3s-rk3566_defconfig
Normal file
75
configs/nanopi-r3s-rk3566_defconfig
Normal file
@@ -0,0 +1,75 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
CONFIG_SYS_HAS_NONCACHED_MEMORY=y
|
||||
CONFIG_COUNTER_FREQUENCY=24000000
|
||||
CONFIG_ARCH_ROCKCHIP=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3566-nanopi-r3s"
|
||||
CONFIG_ROCKCHIP_RK3568=y
|
||||
CONFIG_SPL_SERIAL=y
|
||||
CONFIG_SYS_LOAD_ADDR=0xc00800
|
||||
CONFIG_DEBUG_UART_BASE=0xFE660000
|
||||
CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_SPL_FIT_SIGNATURE=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
CONFIG_LEGACY_IMAGE_FORMAT=y
|
||||
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-nanopi-r3s.dtb"
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
CONFIG_SPL_MAX_SIZE=0x40000
|
||||
CONFIG_SPL_PAD_TO=0x7f8000
|
||||
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
CONFIG_SPL_ATF=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_GPT=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_PCI=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_PMIC=y
|
||||
CONFIG_CMD_REGULATOR=y
|
||||
# CONFIG_SPL_DOS_PARTITION is not set
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_OF_LIVE=y
|
||||
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
CONFIG_SPL_DM_SEQ_ALIAS=y
|
||||
CONFIG_SPL_REGMAP=y
|
||||
CONFIG_SPL_SYSCON=y
|
||||
CONFIG_SPL_CLK=y
|
||||
CONFIG_ROCKCHIP_GPIO=y
|
||||
CONFIG_SYS_I2C_ROCKCHIP=y
|
||||
CONFIG_LED=y
|
||||
CONFIG_LED_GPIO=y
|
||||
CONFIG_MISC=y
|
||||
CONFIG_SUPPORT_EMMC_RPMB=y
|
||||
CONFIG_MMC_DW=y
|
||||
CONFIG_MMC_DW_ROCKCHIP=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_SDMA=y
|
||||
CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_DWC_ETH_QOS=y
|
||||
CONFIG_DWC_ETH_QOS_ROCKCHIP=y
|
||||
CONFIG_RTL8169=y
|
||||
CONFIG_NVME_PCI=y
|
||||
CONFIG_PCIE_DW_ROCKCHIP=y
|
||||
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
||||
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
|
||||
CONFIG_SPL_PINCTRL=y
|
||||
CONFIG_DM_PMIC=y
|
||||
CONFIG_PMIC_RK8XX=y
|
||||
CONFIG_REGULATOR_RK8XX=y
|
||||
CONFIG_PWM_ROCKCHIP=y
|
||||
CONFIG_SPL_RAM=y
|
||||
CONFIG_BAUDRATE=1500000
|
||||
CONFIG_DEBUG_UART_SHIFT=2
|
||||
CONFIG_SYS_NS16550_MEM32=y
|
||||
CONFIG_SYSRESET=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_DWC3=y
|
||||
CONFIG_USB_DWC3_GENERIC=y
|
||||
CONFIG_ERRNO_STR=y
|
||||
84
configs/rock-5c-rk3588s_defconfig
Normal file
84
configs/rock-5c-rk3588s_defconfig
Normal file
@@ -0,0 +1,84 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
CONFIG_SYS_HAS_NONCACHED_MEMORY=y
|
||||
CONFIG_COUNTER_FREQUENCY=24000000
|
||||
CONFIG_ARCH_ROCKCHIP=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588s-rock-5c"
|
||||
CONFIG_ROCKCHIP_RK3588=y
|
||||
CONFIG_SPL_SERIAL=y
|
||||
CONFIG_TARGET_ROCK_5C_RK3588S=y
|
||||
CONFIG_SYS_LOAD_ADDR=0xc00800
|
||||
CONFIG_DEBUG_UART_BASE=0xFEB50000
|
||||
CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_SPL_FIT_SIGNATURE=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
CONFIG_LEGACY_IMAGE_FORMAT=y
|
||||
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-rock-5c.dtb"
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_SPL_MAX_SIZE=0x40000
|
||||
CONFIG_SPL_PAD_TO=0x7f8000
|
||||
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
CONFIG_SPL_ATF=y
|
||||
CONFIG_CMD_ADC=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_GPT=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_PCI=y
|
||||
CONFIG_CMD_USB=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_REGULATOR=y
|
||||
# CONFIG_SPL_DOS_PARTITION is not set
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_OF_LIVE=y
|
||||
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
CONFIG_SPL_DM_SEQ_ALIAS=y
|
||||
CONFIG_SPL_REGMAP=y
|
||||
CONFIG_SPL_SYSCON=y
|
||||
CONFIG_SCSI_AHCI=y
|
||||
CONFIG_AHCI_PCI=y
|
||||
CONFIG_SPL_CLK=y
|
||||
CONFIG_ROCKCHIP_GPIO=y
|
||||
CONFIG_LED=y
|
||||
CONFIG_LED_GPIO=y
|
||||
CONFIG_MISC=y
|
||||
CONFIG_SUPPORT_EMMC_RPMB=y
|
||||
CONFIG_MMC_DW=y
|
||||
CONFIG_MMC_DW_ROCKCHIP=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_SDMA=y
|
||||
CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_DWC_ETH_QOS=y
|
||||
CONFIG_DWC_ETH_QOS_ROCKCHIP=y
|
||||
CONFIG_RTL8169=y
|
||||
CONFIG_NVME_PCI=y
|
||||
CONFIG_PCIE_DW_ROCKCHIP=y
|
||||
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
||||
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
|
||||
CONFIG_PHY_ROCKCHIP_USBDP=y
|
||||
CONFIG_SPL_PINCTRL=y
|
||||
CONFIG_DM_PMIC=y
|
||||
CONFIG_PMIC_RK8XX=y
|
||||
CONFIG_REGULATOR_RK8XX=y
|
||||
CONFIG_SPL_RAM=y
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_BAUDRATE=1500000
|
||||
CONFIG_DEBUG_UART_SHIFT=2
|
||||
CONFIG_SYS_NS16550_MEM32=y
|
||||
CONFIG_ROCKCHIP_SPI=y
|
||||
CONFIG_SYSRESET=y
|
||||
CONFIG_SYSRESET_PSCI=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_GENERIC=y
|
||||
CONFIG_USB_OHCI_HCD=y
|
||||
CONFIG_USB_OHCI_GENERIC=y
|
||||
CONFIG_USB_DWC3=y
|
||||
CONFIG_USB_DWC3_GENERIC=y
|
||||
CONFIG_ERRNO_STR=y
|
||||
@@ -11,7 +11,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x60100000
|
||||
CONFIG_SF_DEFAULT_SPEED=20000000
|
||||
CONFIG_ENV_OFFSET=0x3F8000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rk3188-radxarock"
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3188-radxarock"
|
||||
CONFIG_ROCKCHIP_RK3188=y
|
||||
# CONFIG_ROCKCHIP_STIMER is not set
|
||||
CONFIG_TARGET_ROCK=y
|
||||
@@ -25,7 +25,7 @@ CONFIG_DEBUG_UART_BASE=0x20064000
|
||||
CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_USE_PREBOOT=y
|
||||
CONFIG_DEFAULT_FDT_FILE="rk3188-radxarock.dtb"
|
||||
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3188-radxarock.dtb"
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
CONFIG_SPL_MAX_SIZE=0x7800
|
||||
|
||||
@@ -20,8 +20,6 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y
|
||||
CONFIG_SPL_SPI=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_BOOTSTAGE=y
|
||||
CONFIG_BOOTSTAGE_REPORT=y
|
||||
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rockpro64.dtb"
|
||||
CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
CONFIG_SPL_MAX_SIZE=0x40000
|
||||
@@ -39,7 +37,6 @@ CONFIG_CMD_POWEROFF=y
|
||||
CONFIG_CMD_USB=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_TIME=y
|
||||
CONFIG_CMD_BOOTSTAGE=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
|
||||
@@ -4,21 +4,12 @@ CONFIG_TPL_SKIP_LOWLEVEL_INIT_ONLY=y
|
||||
CONFIG_SYS_ARCH_TIMER=y
|
||||
CONFIG_ARCH_ROCKCHIP=y
|
||||
CONFIG_TEXT_BASE=0x01000000
|
||||
CONFIG_SPL_GPIO=y
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000
|
||||
CONFIG_SF_DEFAULT_SPEED=20000000
|
||||
CONFIG_ENV_OFFSET=0x3F8000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rk3288-tinker"
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3288-tinker"
|
||||
CONFIG_DM_RESET=y
|
||||
CONFIG_SYS_MONITOR_LEN=614400
|
||||
CONFIG_ROCKCHIP_RK3288=y
|
||||
CONFIG_TARGET_TINKER_RK3288=y
|
||||
CONFIG_SPL_STACK_R_ADDR=0x80000
|
||||
CONFIG_SPL_STACK=0xff718000
|
||||
CONFIG_SPL_STACK_R=y
|
||||
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
|
||||
CONFIG_SYS_BOOTM_LEN=0x4000000
|
||||
CONFIG_SYS_LOAD_ADDR=0x800800
|
||||
CONFIG_SPL_SIZE_LIMIT=0x4b000
|
||||
@@ -26,15 +17,15 @@ CONFIG_DEBUG_UART_BASE=0xff690000
|
||||
CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
CONFIG_DEBUG_UART=y
|
||||
# CONFIG_ANDROID_BOOT_IMAGE is not set
|
||||
CONFIG_USE_PREBOOT=y
|
||||
CONFIG_DEFAULT_FDT_FILE="rk3288-tinker.dtb"
|
||||
CONFIG_SILENT_CONSOLE=y
|
||||
CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_SPL_FIT_SIGNATURE=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
CONFIG_LEGACY_IMAGE_FORMAT=y
|
||||
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3288-tinker.dtb"
|
||||
CONFIG_MISC_INIT_R=y
|
||||
CONFIG_SPL_PAD_TO=0x7f8000
|
||||
CONFIG_SPL_NO_BSS_LIMIT=y
|
||||
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
||||
CONFIG_SPL_I2C=y
|
||||
CONFIG_SPL_POWER=y
|
||||
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_GPT=y
|
||||
CONFIG_CMD_I2C=y
|
||||
@@ -43,6 +34,7 @@ CONFIG_CMD_SPI=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_USB_MASS_STORAGE=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_BMP=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_TIME=y
|
||||
CONFIG_CMD_PMIC=y
|
||||
@@ -50,10 +42,13 @@ CONFIG_CMD_REGULATOR=y
|
||||
# CONFIG_SPL_DOS_PARTITION is not set
|
||||
# CONFIG_SPL_EFI_PARTITION is not set
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_OF_LIVE=y
|
||||
CONFIG_OF_UPSTREAM=y
|
||||
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_SYS_MMC_ENV_DEV=1
|
||||
CONFIG_SPL_DM_SEQ_ALIAS=y
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_SPL_REGMAP=y
|
||||
CONFIG_SYSCON=y
|
||||
@@ -65,19 +60,20 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
|
||||
CONFIG_ROCKCHIP_GPIO=y
|
||||
CONFIG_SYS_I2C_ROCKCHIP=y
|
||||
CONFIG_MISC=y
|
||||
CONFIG_ROCKCHIP_EFUSE=y
|
||||
CONFIG_I2C_EEPROM=y
|
||||
CONFIG_MMC_DW=y
|
||||
CONFIG_MMC_DW_ROCKCHIP=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_DM_ETH_PHY=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_ETH_DESIGNWARE=y
|
||||
CONFIG_GMAC_ROCKCHIP=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_SPL_PINCTRL=y
|
||||
CONFIG_DM_PMIC=y
|
||||
CONFIG_PMIC_RK8XX=y
|
||||
CONFIG_SPL_PMIC_RK8XX=y
|
||||
CONFIG_SPL_DM_REGULATOR=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_SPL_DM_REGULATOR_FIXED=y
|
||||
CONFIG_REGULATOR_RK8XX=y
|
||||
CONFIG_PWM_ROCKCHIP=y
|
||||
CONFIG_RAM=y
|
||||
@@ -95,8 +91,11 @@ CONFIG_USB_ETHER_SMSC95XX=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_GADGET_DWC2_OTG=y
|
||||
CONFIG_VIDEO=y
|
||||
# CONFIG_VIDEO_BPP8 is not set
|
||||
CONFIG_DISPLAY=y
|
||||
CONFIG_VIDEO_ROCKCHIP=y
|
||||
CONFIG_DISPLAY_ROCKCHIP_HDMI=y
|
||||
CONFIG_CONSOLE_SCROLL_LINES=10
|
||||
CONFIG_CMD_DHRYSTONE=y
|
||||
CONFIG_SPL_CRC32=y
|
||||
CONFIG_ERRNO_STR=y
|
||||
|
||||
@@ -4,21 +4,12 @@ CONFIG_TPL_SKIP_LOWLEVEL_INIT_ONLY=y
|
||||
CONFIG_SYS_ARCH_TIMER=y
|
||||
CONFIG_ARCH_ROCKCHIP=y
|
||||
CONFIG_TEXT_BASE=0x01000000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x4000
|
||||
CONFIG_SPL_GPIO=y
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000
|
||||
CONFIG_SF_DEFAULT_SPEED=20000000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rk3288-tinker-s"
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3288-tinker-s"
|
||||
CONFIG_DM_RESET=y
|
||||
CONFIG_SYS_MONITOR_LEN=614400
|
||||
CONFIG_ROCKCHIP_RK3288=y
|
||||
CONFIG_TARGET_TINKER_RK3288=y
|
||||
CONFIG_SPL_STACK_R_ADDR=0x800000
|
||||
CONFIG_SPL_STACK=0xff718000
|
||||
CONFIG_SPL_STACK_R=y
|
||||
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x300000
|
||||
CONFIG_SYS_BOOTM_LEN=0x4000000
|
||||
CONFIG_SYS_LOAD_ADDR=0x800800
|
||||
CONFIG_SPL_SIZE_LIMIT=0x4b000
|
||||
@@ -26,15 +17,15 @@ CONFIG_DEBUG_UART_BASE=0xff690000
|
||||
CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
CONFIG_DEBUG_UART=y
|
||||
# CONFIG_ANDROID_BOOT_IMAGE is not set
|
||||
CONFIG_USE_PREBOOT=y
|
||||
CONFIG_DEFAULT_FDT_FILE="rk3288-tinker-s.dtb"
|
||||
CONFIG_SILENT_CONSOLE=y
|
||||
CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_SPL_FIT_SIGNATURE=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
CONFIG_LEGACY_IMAGE_FORMAT=y
|
||||
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3288-tinker-s.dtb"
|
||||
CONFIG_MISC_INIT_R=y
|
||||
CONFIG_SPL_PAD_TO=0x7f8000
|
||||
CONFIG_SPL_NO_BSS_LIMIT=y
|
||||
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
||||
CONFIG_SPL_I2C=y
|
||||
CONFIG_SPL_POWER=y
|
||||
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_GPT=y
|
||||
CONFIG_CMD_I2C=y
|
||||
@@ -51,10 +42,13 @@ CONFIG_CMD_REGULATOR=y
|
||||
# CONFIG_SPL_DOS_PARTITION is not set
|
||||
# CONFIG_SPL_EFI_PARTITION is not set
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_OF_LIVE=y
|
||||
CONFIG_OF_UPSTREAM=y
|
||||
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_SYS_MMC_ENV_DEV=1
|
||||
CONFIG_SPL_DM_SEQ_ALIAS=y
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_SPL_REGMAP=y
|
||||
CONFIG_SYSCON=y
|
||||
@@ -66,19 +60,20 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
|
||||
CONFIG_ROCKCHIP_GPIO=y
|
||||
CONFIG_SYS_I2C_ROCKCHIP=y
|
||||
CONFIG_MISC=y
|
||||
CONFIG_ROCKCHIP_EFUSE=y
|
||||
CONFIG_I2C_EEPROM=y
|
||||
CONFIG_MMC_DW=y
|
||||
CONFIG_MMC_DW_ROCKCHIP=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_DM_ETH_PHY=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_ETH_DESIGNWARE=y
|
||||
CONFIG_GMAC_ROCKCHIP=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_SPL_PINCTRL=y
|
||||
CONFIG_DM_PMIC=y
|
||||
CONFIG_PMIC_RK8XX=y
|
||||
CONFIG_SPL_PMIC_RK8XX=y
|
||||
CONFIG_SPL_DM_REGULATOR=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_SPL_DM_REGULATOR_FIXED=y
|
||||
CONFIG_REGULATOR_RK8XX=y
|
||||
CONFIG_PWM_ROCKCHIP=y
|
||||
CONFIG_RAM=y
|
||||
@@ -102,4 +97,5 @@ CONFIG_VIDEO_ROCKCHIP=y
|
||||
CONFIG_DISPLAY_ROCKCHIP_HDMI=y
|
||||
CONFIG_CONSOLE_SCROLL_LINES=10
|
||||
CONFIG_CMD_DHRYSTONE=y
|
||||
CONFIG_SPL_CRC32=y
|
||||
CONFIG_ERRNO_STR=y
|
||||
|
||||
@@ -99,6 +99,7 @@ List of mainline supported Rockchip boards:
|
||||
|
||||
* rk3566
|
||||
- Anbernic RGxx3 (anbernic-rgxx3-rk3566)
|
||||
- FriendlyElec NanoPi R3S (nanopi-r3s-rk3566)
|
||||
- Hardkernel ODROID-M1S (odroid-m1s-rk3566)
|
||||
- Pine64 PineTab2 (pinetab2-rk3566)
|
||||
- Pine64 Quartz64-A Board (quartz64-a-rk3566)
|
||||
@@ -137,10 +138,12 @@ List of mainline supported Rockchip boards:
|
||||
- Generic RK3588S/RK3588 (generic-rk3588)
|
||||
- Hardkernel ODROID-M2 (odroid-m2-rk3588s)
|
||||
- Indiedroid Nova (nova-rk3588s)
|
||||
- Khadas Edge2 (khadas-edge2-rk3588s)
|
||||
- Pine64 QuartzPro64 (quartzpro64-rk3588)
|
||||
- Radxa ROCK 5 ITX (rock-5-itx-rk3588)
|
||||
- Radxa ROCK 5A (rock5a-rk3588s)
|
||||
- Radxa ROCK 5B (rock5b-rk3588)
|
||||
- Radxa ROCK 5C (rock-5c-rk3588s)
|
||||
- Rockchip Toybrick TB-RK3588X (toybrick-rk3588)
|
||||
- Theobroma Systems RK3588-SBC Jaguar (jaguar-rk3588)
|
||||
- Theobroma Systems SOM-RK3588-Q7 - Tiger (tiger-rk3588)
|
||||
|
||||
@@ -40,10 +40,10 @@ Get the TF-A and DDR init (TPL) binaries
|
||||
git clone https://github.com/rockchip-linux/rkbin
|
||||
cd rkbin
|
||||
export RKBIN=$(pwd)
|
||||
export BL31=$RKBIN/bin/rk35/rk3588_bl31_v1.38.elf
|
||||
export ROCKCHIP_TPL=$RKBIN/bin/rk35/rk3588_ddr_lp4_2112MHz_lp5_2736MHz_v1.11.bin
|
||||
export BL31=$RKBIN/bin/rk35/rk3588_bl31_v1.47.elf
|
||||
export ROCKCHIP_TPL=$RKBIN/bin/rk35/rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v1.18.bin
|
||||
sed -i 's/^uart baudrate=.*$/uart baudrate=115200/' tools/ddrbin_param.txt
|
||||
./tools/ddrbin_tool tools/ddrbin_param.txt "$ROCKCHIP_TPL"
|
||||
./tools/ddrbin_tool rk3588 tools/ddrbin_param.txt "$ROCKCHIP_TPL"
|
||||
./tools/boot_merger RKBOOT/RK3588MINIALL.ini
|
||||
export RKDB=$RKBIN/rk3588_spl_loader_v1.11.112.bin
|
||||
|
||||
|
||||
@@ -47,11 +47,11 @@ Get the TF-A and DDR init (TPL) binaries
|
||||
git clone https://github.com/rockchip-linux/rkbin
|
||||
cd rkbin
|
||||
export RKBIN=$(pwd)
|
||||
export BL31=$RKBIN/bin/rk35/rk3588_bl31_v1.38.elf
|
||||
export ROCKCHIP_TPL=$RKBIN/bin/rk35/rk3588_ddr_lp4_2112MHz_lp5_2736MHz_v1.11.bin
|
||||
export BL31=$RKBIN/bin/rk35/rk3588_bl31_v1.47.elf
|
||||
export ROCKCHIP_TPL=$RKBIN/bin/rk35/rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v1.18.bin
|
||||
sed -i 's/^uart baudrate=.*$/uart baudrate=115200/' tools/ddrbin_param.txt
|
||||
sed -i 's/^uart iomux=.*$/uart iomux=2/' tools/ddrbin_param.txt
|
||||
./tools/ddrbin_tool tools/ddrbin_param.txt "$ROCKCHIP_TPL"
|
||||
./tools/ddrbin_tool rk3588 tools/ddrbin_param.txt "$ROCKCHIP_TPL"
|
||||
./tools/boot_merger RKBOOT/RK3588MINIALL.ini
|
||||
export RKDB=$RKBIN/rk3588_spl_loader_v1.11.112.bin
|
||||
|
||||
|
||||
@@ -903,11 +903,11 @@ static int __maybe_unused rk3288_gmac_set_parent(struct clk *clk, struct clk *pa
|
||||
int ret;
|
||||
|
||||
/*
|
||||
* If the requested parent is in the same clock-controller and
|
||||
* the id is SCLK_MAC_PLL ("mac_pll_src"), switch to the internal
|
||||
* clock.
|
||||
* If the requested parent is in the same clock-controller the
|
||||
* likely parent is the unexported SCLK_MAC_PLL ("mac_pll_src"),
|
||||
* switch to the internal clock.
|
||||
*/
|
||||
if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC_PLL)) {
|
||||
if (parent->dev == clk->dev) {
|
||||
debug("%s: switching GAMC to SCLK_MAC_PLL\n", __func__);
|
||||
rk_clrsetreg(&cru->cru_clksel_con[21], RMII_EXTCLK_MASK, 0);
|
||||
return 0;
|
||||
|
||||
554
dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts
Normal file
554
dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts
Normal file
@@ -0,0 +1,554 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
/*
|
||||
* Copyright (c) 2020 Rockchip Electronics Co., Ltd.
|
||||
*
|
||||
* Copyright (c) 2024 FriendlyElec Computer Tech. Co., Ltd.
|
||||
* (http://www.friendlyelec.com)
|
||||
*
|
||||
* Copyright (c) 2024 Tianling Shen <cnsztl@gmail.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/pinctrl/rockchip.h>
|
||||
#include <dt-bindings/soc/rockchip,vop2.h>
|
||||
#include "rk3566.dtsi"
|
||||
|
||||
/ {
|
||||
model = "FriendlyElec NanoPi R3S";
|
||||
compatible = "friendlyarm,nanopi-r3s", "rockchip,rk3566";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &gmac1;
|
||||
mmc0 = &sdhci;
|
||||
mmc1 = &sdmmc0;
|
||||
};
|
||||
|
||||
chosen: chosen {
|
||||
stdout-path = "serial2:1500000n8";
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&reset_button_pin>;
|
||||
|
||||
button-reset {
|
||||
label = "reset";
|
||||
gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_RESTART>;
|
||||
debounce-interval = <50>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&power_led_pin>, <&lan_led_pin>, <&wan_led_pin>;
|
||||
|
||||
power_led: led-0 {
|
||||
color = <LED_COLOR_ID_RED>;
|
||||
function = LED_FUNCTION_POWER;
|
||||
gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "on";
|
||||
};
|
||||
|
||||
lan_led: led-1 {
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
function = LED_FUNCTION_LAN;
|
||||
gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
wan_led: led-2 {
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
function = LED_FUNCTION_WAN;
|
||||
gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_sys: regulator-vcc3v3-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
|
||||
vcc5v0_sys: regulator-vcc5v0-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vdd_usbc>;
|
||||
};
|
||||
|
||||
vcc5v0_usb: regulator-vcc5v0_usb {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_usb_host_en>;
|
||||
regulator-name = "vcc5v0_usb";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
|
||||
vdd_usbc: regulator-vdd-usbc {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vdd_usbc";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&combphy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu1 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu2 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu3 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&gmac1 {
|
||||
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
|
||||
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
|
||||
assigned-clock-rates = <0>, <125000000>;
|
||||
clock_in_out = "output";
|
||||
phy-mode = "rgmii-id";
|
||||
phy-handle = <&rgmii_phy1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac1m0_miim
|
||||
&gmac1m0_tx_bus2_level3
|
||||
&gmac1m0_rx_bus2
|
||||
&gmac1m0_rgmii_clk_level2
|
||||
&gmac1m0_rgmii_bus_level3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpu {
|
||||
mali-supply = <&vdd_gpu>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
|
||||
vdd_cpu: regulator@1c {
|
||||
compatible = "tcs,tcs4525";
|
||||
reg = <0x1c>;
|
||||
fcs,suspend-voltage-selector = <1>;
|
||||
regulator-name = "vdd_cpu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1150000>;
|
||||
regulator-ramp-delay = <2300>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
rk809: pmic@20 {
|
||||
compatible = "rockchip,rk809";
|
||||
reg = <0x20>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
|
||||
#clock-cells = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_int>;
|
||||
system-power-controller;
|
||||
vcc1-supply = <&vcc3v3_sys>;
|
||||
vcc2-supply = <&vcc3v3_sys>;
|
||||
vcc3-supply = <&vcc3v3_sys>;
|
||||
vcc4-supply = <&vcc3v3_sys>;
|
||||
vcc5-supply = <&vcc3v3_sys>;
|
||||
vcc6-supply = <&vcc3v3_sys>;
|
||||
vcc7-supply = <&vcc3v3_sys>;
|
||||
vcc8-supply = <&vcc3v3_sys>;
|
||||
vcc9-supply = <&vcc3v3_sys>;
|
||||
wakeup-source;
|
||||
|
||||
regulators {
|
||||
vdd_logic: DCDC_REG1 {
|
||||
regulator-name = "vdd_logic";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_gpu: DCDC_REG2 {
|
||||
regulator-name = "vdd_gpu";
|
||||
regulator-always-on;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_ddr: DCDC_REG3 {
|
||||
regulator-name = "vcc_ddr";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-initial-mode = <0x2>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_npu: DCDC_REG4 {
|
||||
regulator-name = "vdd_npu";
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v8: DCDC_REG5 {
|
||||
regulator-name = "vcc_1v8";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda0v9_image: LDO_REG1 {
|
||||
regulator-name = "vdda0v9_image";
|
||||
regulator-min-microvolt = <950000>;
|
||||
regulator-max-microvolt = <950000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda_0v9: LDO_REG2 {
|
||||
regulator-name = "vdda_0v9";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda0v9_pmu: LDO_REG3 {
|
||||
regulator-name = "vdda0v9_pmu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <900000>;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_acodec: LDO_REG4 {
|
||||
regulator-name = "vccio_acodec";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_sd: LDO_REG5 {
|
||||
regulator-name = "vccio_sd";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_pmu: LDO_REG6 {
|
||||
regulator-name = "vcc3v3_pmu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca_1v8: LDO_REG7 {
|
||||
regulator-name = "vcca_1v8";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_pmu: LDO_REG8 {
|
||||
regulator-name = "vcca1v8_pmu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_image: LDO_REG9 {
|
||||
regulator-name = "vcca1v8_image";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_3v3: SWITCH_REG1 {
|
||||
regulator-name = "vcc_3v3";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_sd: SWITCH_REG2 {
|
||||
regulator-name = "vcc3v3_sd";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
|
||||
hym8563: rtc@51 {
|
||||
compatible = "haoyu,hym8563";
|
||||
reg = <0x51>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "hym8563";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hym8563_int>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
|
||||
&mdio1 {
|
||||
rgmii_phy1: ethernet-phy@1 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <1>;
|
||||
interrupt-parent = <&gpio4>;
|
||||
interrupts = <RK_PC3 IRQ_TYPE_LEVEL_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <ð_phy_reset_pin>;
|
||||
reset-assert-us = <20000>;
|
||||
reset-deassert-us = <100000>;
|
||||
reset-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
&pcie2x1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie_reset_h>;
|
||||
reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
gpio-leds {
|
||||
lan_led_pin: lan-led-pin {
|
||||
rockchip,pins = <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
power_led_pin: power-led-pin {
|
||||
rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
wan_led_pin: wan-led-pin {
|
||||
rockchip,pins = <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
gmac {
|
||||
eth_phy_reset_pin: eth-phy-reset-pin {
|
||||
rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie {
|
||||
pcie_reset_h: pcie-reset-h {
|
||||
rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
};
|
||||
};
|
||||
|
||||
pmic {
|
||||
pmic_int: pmic-int {
|
||||
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
rockchip-key {
|
||||
reset_button_pin: reset-button-pin {
|
||||
rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
rtc {
|
||||
hym8563_int: hym8563-int {
|
||||
rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
usb {
|
||||
vcc5v0_usb_host_en: vcc5v0-usb-host-en {
|
||||
rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pmu_io_domains {
|
||||
pmuio1-supply = <&vcc3v3_pmu>;
|
||||
pmuio2-supply = <&vcc3v3_pmu>;
|
||||
vccio1-supply = <&vccio_acodec>;
|
||||
vccio2-supply = <&vcc_1v8>;
|
||||
vccio3-supply = <&vccio_sd>;
|
||||
vccio4-supply = <&vcc_3v3>;
|
||||
vccio5-supply = <&vcc_1v8>;
|
||||
vccio6-supply = <&vcc_3v3>;
|
||||
vccio7-supply = <&vcc_3v3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci {
|
||||
bus-width = <8>;
|
||||
max-frequency = <200000000>;
|
||||
mmc-hs200-1_8v;
|
||||
non-removable;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc0 {
|
||||
bus-width = <4>;
|
||||
cap-mmc-highspeed;
|
||||
cap-sd-highspeed;
|
||||
disable-wp;
|
||||
no-sdio;
|
||||
no-mmc;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
|
||||
sd-uhs-sdr50;
|
||||
vmmc-supply = <&vcc3v3_sd>;
|
||||
vqmmc-supply = <&vccio_sd>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tsadc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0_host {
|
||||
phy-supply = <&vcc5v0_usb>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0_otg {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_xhci {
|
||||
extcon = <&usb2phy0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_xhci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vop {
|
||||
assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
|
||||
assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vop_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -1612,23 +1612,43 @@
|
||||
|
||||
pcie20x1 {
|
||||
/omit-if-no-ref/
|
||||
pcie20x1m0_pins: pcie20x1m0-pins {
|
||||
pcie20x1m0_clkreqn: pcie20x1m0-clkreqn {
|
||||
rockchip,pins =
|
||||
/* pcie20x1_2_clkreqn_m0 */
|
||||
<3 RK_PC7 4 &pcfg_pull_none>,
|
||||
<3 RK_PC7 4 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcie20x1m0_perstn: pcie20x1m0-perstn {
|
||||
rockchip,pins =
|
||||
/* pcie20x1_2_perstn_m0 */
|
||||
<3 RK_PD1 4 &pcfg_pull_none>,
|
||||
<3 RK_PD1 4 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcie20x1m0_waken: pcie20x1m0-waken {
|
||||
rockchip,pins =
|
||||
/* pcie20x1_2_waken_m0 */
|
||||
<3 RK_PD0 4 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcie20x1m1_pins: pcie20x1m1-pins {
|
||||
pcie20x1m1_clkreqn: pcie20x1m1-clkreqn {
|
||||
rockchip,pins =
|
||||
/* pcie20x1_2_clkreqn_m1 */
|
||||
<4 RK_PB7 4 &pcfg_pull_none>,
|
||||
<4 RK_PB7 4 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcie20x1m1_perstn: pcie20x1m1-perstn {
|
||||
rockchip,pins =
|
||||
/* pcie20x1_2_perstn_m1 */
|
||||
<4 RK_PC1 4 &pcfg_pull_none>,
|
||||
<4 RK_PC1 4 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcie20x1m1_waken: pcie20x1m1-waken {
|
||||
rockchip,pins =
|
||||
/* pcie20x1_2_waken_m1 */
|
||||
<4 RK_PC0 4 &pcfg_pull_none>;
|
||||
};
|
||||
@@ -1654,52 +1674,127 @@
|
||||
|
||||
pcie30x1 {
|
||||
/omit-if-no-ref/
|
||||
pcie30x1m0_pins: pcie30x1m0-pins {
|
||||
pcie30x1m0_0_clkreqn: pcie30x1m0-0-clkreqn {
|
||||
rockchip,pins =
|
||||
/* pcie30x1_0_clkreqn_m0 */
|
||||
<0 RK_PC0 12 &pcfg_pull_none>,
|
||||
<0 RK_PC0 12 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcie30x1m0_0_perstn: pcie30x1m0-0-perstn {
|
||||
rockchip,pins =
|
||||
/* pcie30x1_0_perstn_m0 */
|
||||
<0 RK_PC5 12 &pcfg_pull_none>,
|
||||
<0 RK_PC5 12 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcie30x1m0_0_waken: pcie30x1m0-0-waken {
|
||||
rockchip,pins =
|
||||
/* pcie30x1_0_waken_m0 */
|
||||
<0 RK_PC4 12 &pcfg_pull_none>,
|
||||
<0 RK_PC4 12 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcie30x1m0_1_clkreqn: pcie30x1m0-1-clkreqn {
|
||||
rockchip,pins =
|
||||
/* pcie30x1_1_clkreqn_m0 */
|
||||
<0 RK_PB5 12 &pcfg_pull_none>,
|
||||
<0 RK_PB5 12 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcie30x1m0_1_perstn: pcie30x1m0-1-perstn {
|
||||
rockchip,pins =
|
||||
/* pcie30x1_1_perstn_m0 */
|
||||
<0 RK_PB7 12 &pcfg_pull_none>,
|
||||
<0 RK_PB7 12 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcie30x1m0_1_waken: pcie30x1m0-1-waken {
|
||||
rockchip,pins =
|
||||
/* pcie30x1_1_waken_m0 */
|
||||
<0 RK_PB6 12 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcie30x1m1_pins: pcie30x1m1-pins {
|
||||
pcie30x1m1_0_clkreqn: pcie30x1m1-0-clkreqn {
|
||||
rockchip,pins =
|
||||
/* pcie30x1_0_clkreqn_m1 */
|
||||
<4 RK_PA3 4 &pcfg_pull_none>,
|
||||
<4 RK_PA3 4 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcie30x1m1_0_perstn: pcie30x1m1-0-perstn {
|
||||
rockchip,pins =
|
||||
/* pcie30x1_0_perstn_m1 */
|
||||
<4 RK_PA5 4 &pcfg_pull_none>,
|
||||
<4 RK_PA5 4 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcie30x1m1_0_waken: pcie30x1m1-0-waken {
|
||||
rockchip,pins =
|
||||
/* pcie30x1_0_waken_m1 */
|
||||
<4 RK_PA4 4 &pcfg_pull_none>,
|
||||
<4 RK_PA4 4 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcie30x1m1_1_clkreqn: pcie30x1m1-1-clkreqn {
|
||||
rockchip,pins =
|
||||
/* pcie30x1_1_clkreqn_m1 */
|
||||
<4 RK_PA0 4 &pcfg_pull_none>,
|
||||
<4 RK_PA0 4 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcie30x1m1_1_perstn: pcie30x1m1-1-perstn {
|
||||
rockchip,pins =
|
||||
/* pcie30x1_1_perstn_m1 */
|
||||
<4 RK_PA2 4 &pcfg_pull_none>,
|
||||
<4 RK_PA2 4 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcie30x1m1_1_waken: pcie30x1m1-1-waken {
|
||||
rockchip,pins =
|
||||
/* pcie30x1_1_waken_m1 */
|
||||
<4 RK_PA1 4 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcie30x1m2_pins: pcie30x1m2-pins {
|
||||
pcie30x1m2_0_clkreqn: pcie30x1m2-0-clkreqn {
|
||||
rockchip,pins =
|
||||
/* pcie30x1_0_clkreqn_m2 */
|
||||
<1 RK_PB5 4 &pcfg_pull_none>,
|
||||
<1 RK_PB5 4 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcie30x1m2_0_perstn: pcie30x1m2-0-perstn {
|
||||
rockchip,pins =
|
||||
/* pcie30x1_0_perstn_m2 */
|
||||
<1 RK_PB4 4 &pcfg_pull_none>,
|
||||
<1 RK_PB4 4 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcie30x1m2_0_waken: pcie30x1m2-0-waken {
|
||||
rockchip,pins =
|
||||
/* pcie30x1_0_waken_m2 */
|
||||
<1 RK_PB3 4 &pcfg_pull_none>,
|
||||
<1 RK_PB3 4 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcie30x1m2_1_clkreqn: pcie30x1m2-1-clkreqn {
|
||||
rockchip,pins =
|
||||
/* pcie30x1_1_clkreqn_m2 */
|
||||
<1 RK_PA0 4 &pcfg_pull_none>,
|
||||
<1 RK_PA0 4 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcie30x1m2_1_perstn: pcie30x1m2-1-perstn {
|
||||
rockchip,pins =
|
||||
/* pcie30x1_1_perstn_m2 */
|
||||
<1 RK_PA7 4 &pcfg_pull_none>,
|
||||
<1 RK_PA7 4 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcie30x1m2_1_waken: pcie30x1m2-1-waken {
|
||||
rockchip,pins =
|
||||
/* pcie30x1_1_waken_m2 */
|
||||
<1 RK_PA1 4 &pcfg_pull_none>;
|
||||
};
|
||||
@@ -1721,45 +1816,85 @@
|
||||
|
||||
pcie30x2 {
|
||||
/omit-if-no-ref/
|
||||
pcie30x2m0_pins: pcie30x2m0-pins {
|
||||
pcie30x2m0_clkreqn: pcie30x2m0-clkreqn {
|
||||
rockchip,pins =
|
||||
/* pcie30x2_clkreqn_m0 */
|
||||
<0 RK_PD1 12 &pcfg_pull_none>,
|
||||
<0 RK_PD1 12 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcie30x2m0_perstn: pcie30x2m0-perstn {
|
||||
rockchip,pins =
|
||||
/* pcie30x2_perstn_m0 */
|
||||
<0 RK_PD4 12 &pcfg_pull_none>,
|
||||
<0 RK_PD4 12 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcie30x2m0_waken: pcie30x2m0-waken {
|
||||
rockchip,pins =
|
||||
/* pcie30x2_waken_m0 */
|
||||
<0 RK_PD2 12 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcie30x2m1_pins: pcie30x2m1-pins {
|
||||
pcie30x2m1_clkreqn: pcie30x2m1-clkreqn {
|
||||
rockchip,pins =
|
||||
/* pcie30x2_clkreqn_m1 */
|
||||
<4 RK_PA6 4 &pcfg_pull_none>,
|
||||
<4 RK_PA6 4 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcie30x2m1_perstn: pcie30x2m1-perstn {
|
||||
rockchip,pins =
|
||||
/* pcie30x2_perstn_m1 */
|
||||
<4 RK_PB0 4 &pcfg_pull_none>,
|
||||
<4 RK_PB0 4 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcie30x2m1_waken: pcie30x2m1-waken {
|
||||
rockchip,pins =
|
||||
/* pcie30x2_waken_m1 */
|
||||
<4 RK_PA7 4 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcie30x2m2_pins: pcie30x2m2-pins {
|
||||
pcie30x2m2_clkreqn: pcie30x2m2-clkreqn {
|
||||
rockchip,pins =
|
||||
/* pcie30x2_clkreqn_m2 */
|
||||
<3 RK_PD2 4 &pcfg_pull_none>,
|
||||
<3 RK_PD2 4 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcie30x2m2_perstn: pcie30x2m2-perstn {
|
||||
rockchip,pins =
|
||||
/* pcie30x2_perstn_m2 */
|
||||
<3 RK_PD4 4 &pcfg_pull_none>,
|
||||
<3 RK_PD4 4 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcie30x2m2_waken: pcie30x2m2-waken {
|
||||
rockchip,pins =
|
||||
/* pcie30x2_waken_m2 */
|
||||
<3 RK_PD3 4 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcie30x2m3_pins: pcie30x2m3-pins {
|
||||
pcie30x2m3_clkreqn: pcie30x2m3-clkreqn {
|
||||
rockchip,pins =
|
||||
/* pcie30x2_clkreqn_m3 */
|
||||
<1 RK_PD7 4 &pcfg_pull_none>,
|
||||
<1 RK_PD7 4 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcie30x2m3_perstn: pcie30x2m3-perstn {
|
||||
rockchip,pins =
|
||||
/* pcie30x2_perstn_m3 */
|
||||
<1 RK_PB7 4 &pcfg_pull_none>,
|
||||
<1 RK_PB7 4 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcie30x2m3_waken: pcie30x2m3-waken {
|
||||
rockchip,pins =
|
||||
/* pcie30x2_waken_m3 */
|
||||
<1 RK_PB6 4 &pcfg_pull_none>;
|
||||
};
|
||||
@@ -1774,45 +1909,85 @@
|
||||
|
||||
pcie30x4 {
|
||||
/omit-if-no-ref/
|
||||
pcie30x4m0_pins: pcie30x4m0-pins {
|
||||
pcie30x4m0_clkreqn: pcie30x4m0-clkreqn {
|
||||
rockchip,pins =
|
||||
/* pcie30x4_clkreqn_m0 */
|
||||
<0 RK_PC6 12 &pcfg_pull_none>,
|
||||
<0 RK_PC6 12 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcie30x4m0_perstn: pcie30x4m0-perstn {
|
||||
rockchip,pins =
|
||||
/* pcie30x4_perstn_m0 */
|
||||
<0 RK_PD0 12 &pcfg_pull_none>,
|
||||
<0 RK_PD0 12 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcie30x4m0_waken: pcie30x4m0-waken {
|
||||
rockchip,pins =
|
||||
/* pcie30x4_waken_m0 */
|
||||
<0 RK_PC7 12 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcie30x4m1_pins: pcie30x4m1-pins {
|
||||
pcie30x4m1_clkreqn: pcie30x4m1-clkreqn {
|
||||
rockchip,pins =
|
||||
/* pcie30x4_clkreqn_m1 */
|
||||
<4 RK_PB4 4 &pcfg_pull_none>,
|
||||
<4 RK_PB4 4 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcie30x4m1_perstn: pcie30x4m1-perstn {
|
||||
rockchip,pins =
|
||||
/* pcie30x4_perstn_m1 */
|
||||
<4 RK_PB6 4 &pcfg_pull_none>,
|
||||
<4 RK_PB6 4 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcie30x4m1_waken: pcie30x4m1-waken {
|
||||
rockchip,pins =
|
||||
/* pcie30x4_waken_m1 */
|
||||
<4 RK_PB5 4 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcie30x4m2_pins: pcie30x4m2-pins {
|
||||
pcie30x4m2_clkreqn: pcie30x4m2-clkreqn {
|
||||
rockchip,pins =
|
||||
/* pcie30x4_clkreqn_m2 */
|
||||
<3 RK_PC4 4 &pcfg_pull_none>,
|
||||
<3 RK_PC4 4 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcie30x4m2_perstn: pcie30x4m2-perstn {
|
||||
rockchip,pins =
|
||||
/* pcie30x4_perstn_m2 */
|
||||
<3 RK_PC6 4 &pcfg_pull_none>,
|
||||
<3 RK_PC6 4 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcie30x4m2_waken: pcie30x4m2-waken {
|
||||
rockchip,pins =
|
||||
/* pcie30x4_waken_m2 */
|
||||
<3 RK_PC5 4 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcie30x4m3_pins: pcie30x4m3-pins {
|
||||
pcie30x4m3_clkreqn: pcie30x4m3-clkreqn {
|
||||
rockchip,pins =
|
||||
/* pcie30x4_clkreqn_m3 */
|
||||
<1 RK_PB0 4 &pcfg_pull_none>,
|
||||
<1 RK_PB0 4 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcie30x4m3_perstn: pcie30x4m3-perstn {
|
||||
rockchip,pins =
|
||||
/* pcie30x4_perstn_m3 */
|
||||
<1 RK_PB2 4 &pcfg_pull_none>,
|
||||
<1 RK_PB2 4 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcie30x4m3_waken: pcie30x4m3-waken {
|
||||
rockchip,pins =
|
||||
/* pcie30x4_waken_m3 */
|
||||
<1 RK_PB1 4 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
@@ -1370,6 +1370,47 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
hdmi0: hdmi@fde80000 {
|
||||
compatible = "rockchip,rk3588-dw-hdmi-qp";
|
||||
reg = <0x0 0xfde80000 0x0 0x20000>;
|
||||
clocks = <&cru PCLK_HDMITX0>,
|
||||
<&cru CLK_HDMITX0_EARC>,
|
||||
<&cru CLK_HDMITX0_REF>,
|
||||
<&cru MCLK_I2S5_8CH_TX>,
|
||||
<&cru CLK_HDMIHDP0>,
|
||||
<&cru HCLK_VO1>;
|
||||
clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1";
|
||||
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
interrupt-names = "avp", "cec", "earc", "main", "hpd";
|
||||
phys = <&hdptxphy_hdmi0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd
|
||||
&hdmim0_tx0_scl &hdmim0_tx0_sda>;
|
||||
power-domains = <&power RK3588_PD_VO1>;
|
||||
resets = <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMIHDP0>;
|
||||
reset-names = "ref", "hdp";
|
||||
rockchip,grf = <&sys_grf>;
|
||||
rockchip,vo-grf = <&vo1_grf>;
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
hdmi0_in: port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
hdmi0_out: port@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
qos_gpu_m0: qos@fdf35000 {
|
||||
compatible = "rockchip,rk3588-qos", "syscon";
|
||||
reg = <0x0 0xfdf35000 0x0 0x20>;
|
||||
|
||||
@@ -310,7 +310,7 @@
|
||||
};
|
||||
|
||||
&pcie2x1l2 {
|
||||
pinctrl-0 = <&pcie20x1m0_pins>;
|
||||
pinctrl-0 = <&pcie2_reset>, <&pcie20x1m0_clkreqn>, <&pcie20x1m0_waken>;
|
||||
pinctrl-names = "default";
|
||||
reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_wf>;
|
||||
@@ -328,6 +328,10 @@
|
||||
pow_en: pow-en {
|
||||
rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
pcie2_reset: pcie2-reset {
|
||||
rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
power {
|
||||
|
||||
920
dts/upstream/src/arm64/rockchip/rk3588s-rock-5c.dts
Normal file
920
dts/upstream/src/arm64/rockchip/rk3588s-rock-5c.dts
Normal file
@@ -0,0 +1,920 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2024 Radxa Computer (Shenzhen) Co., Ltd.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/pinctrl/rockchip.h>
|
||||
#include <dt-bindings/soc/rockchip,vop2.h>
|
||||
#include "rk3588s.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Radxa ROCK 5C";
|
||||
compatible = "radxa,rock-5c", "rockchip,rk3588s";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &gmac1;
|
||||
mmc0 = &sdhci;
|
||||
mmc1 = &sdmmc;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial2:1500000n8";
|
||||
};
|
||||
|
||||
analog-sound {
|
||||
compatible = "audio-graph-card";
|
||||
label = "rk3588-es8316";
|
||||
dais = <&i2s0_8ch_p0>;
|
||||
routing = "MIC2", "Mic Jack",
|
||||
"Headphones", "HPOL",
|
||||
"Headphones", "HPOR";
|
||||
widgets = "Microphone", "Mic Jack",
|
||||
"Headphone", "Headphones";
|
||||
};
|
||||
|
||||
hdmi0-con {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi0_con_in: endpoint {
|
||||
remote-endpoint = <&hdmi0_out_con>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&led_pins>;
|
||||
|
||||
led-0 {
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
default-state = "on";
|
||||
function = LED_FUNCTION_POWER;
|
||||
gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
led-1 {
|
||||
color = <LED_COLOR_ID_BLUE>;
|
||||
default-state = "on";
|
||||
function = LED_FUNCTION_HEARTBEAT;
|
||||
gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
};
|
||||
|
||||
fan {
|
||||
compatible = "pwm-fan";
|
||||
#cooling-cells = <2>;
|
||||
cooling-levels = <0 64 128 192 255>;
|
||||
fan-supply = <&vcc_5v0>;
|
||||
pwms = <&pwm3 0 10000 0>;
|
||||
};
|
||||
|
||||
pcie2x1l2_3v3: regulator-pcie2x1l2-3v3 {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pow_en>;
|
||||
regulator-name = "pcie2x1l2_3v3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vcc_sysin>;
|
||||
};
|
||||
|
||||
vcc5v_dcin: regulator-vcc5v-dcin {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v_dcin";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
};
|
||||
|
||||
vcc5v0_usb_host: regulator-vcc5v0-usb-host {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usb_host_pwren_h>;
|
||||
regulator-name = "vcc5v0_usb_host";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc_sysin>;
|
||||
};
|
||||
|
||||
vcc5v0_usb_otg0: regulator-vcc5v0-usb-otg0 {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usb_otg_pwren_h>;
|
||||
regulator-name = "vcc5v0_usb_otg0";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc_sysin>;
|
||||
};
|
||||
|
||||
vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_1v1_nldo_s3";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1100000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
vin-supply = <&vcc_sysin>;
|
||||
};
|
||||
|
||||
vcc_3v3_pmu: regulator-vcc-3v3-pmu {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_3v3_pmu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vcc_3v3_s3>;
|
||||
};
|
||||
|
||||
vcc_3v3_s0: regulator-vcc-3v3-s0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_3v3_s0";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vcc_1v8_s0>;
|
||||
};
|
||||
|
||||
vcc_5v0: regulator-vcc-5v0 {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc_5v0_pwren_h>;
|
||||
regulator-name = "vcc_5v0";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc_sysin>;
|
||||
};
|
||||
|
||||
vcc_sysin: regulator-vcc-sysin {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_sysin";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc5v_dcin>;
|
||||
};
|
||||
|
||||
vcca: regulator-vcca {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcca";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <4000000>;
|
||||
regulator-max-microvolt = <4000000>;
|
||||
vin-supply = <&vcc_sysin>;
|
||||
};
|
||||
|
||||
vdd_3v3: regulator-vdd-3v3 {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usb_wifi_pwr>;
|
||||
regulator-name = "vdd_3v3";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vcc_3v3_s3>;
|
||||
};
|
||||
};
|
||||
|
||||
&combphy0_ps {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy2_psu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpu_b0 {
|
||||
cpu-supply = <&vdd_cpu_big0_s0>;
|
||||
};
|
||||
|
||||
&cpu_b1 {
|
||||
cpu-supply = <&vdd_cpu_big0_s0>;
|
||||
};
|
||||
|
||||
&cpu_b2 {
|
||||
cpu-supply = <&vdd_cpu_big1_s0>;
|
||||
};
|
||||
|
||||
&cpu_b3 {
|
||||
cpu-supply = <&vdd_cpu_big1_s0>;
|
||||
};
|
||||
|
||||
&cpu_l0 {
|
||||
cpu-supply = <&vdd_cpu_lit_s0>;
|
||||
};
|
||||
|
||||
&cpu_l1 {
|
||||
cpu-supply = <&vdd_cpu_lit_s0>;
|
||||
};
|
||||
|
||||
&cpu_l2 {
|
||||
cpu-supply = <&vdd_cpu_lit_s0>;
|
||||
};
|
||||
|
||||
&cpu_l3 {
|
||||
cpu-supply = <&vdd_cpu_lit_s0>;
|
||||
};
|
||||
|
||||
&gmac1 {
|
||||
phy-handle = <&rgmii_phy1>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy-supply = <&vcc_3v3_s0>;
|
||||
pinctrl-0 = <&gmac1_miim
|
||||
&gmac1_tx_bus2
|
||||
&gmac1_rx_bus2
|
||||
&gmac1_rgmii_clk
|
||||
&gmac1_rgmii_bus
|
||||
&gmac1_clkinout>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpu {
|
||||
mali-supply = <&vdd_gpu_s0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hdmim0_tx0_cec
|
||||
&hdmim1_tx0_hpd
|
||||
&hdmim0_tx0_scl
|
||||
&hdmim0_tx0_sda>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi0_in {
|
||||
hdmi0_in_vp0: endpoint {
|
||||
remote-endpoint = <&vp0_out_hdmi0>;
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi0_out {
|
||||
hdmi0_out_con: endpoint {
|
||||
remote-endpoint = <&hdmi0_con_in>;
|
||||
};
|
||||
};
|
||||
|
||||
&hdptxphy_hdmi0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c0m2_xfer>;
|
||||
status = "okay";
|
||||
|
||||
vdd_cpu_big0_s0: regulator@42 {
|
||||
compatible = "rockchip,rk8602";
|
||||
reg = <0x42>;
|
||||
fcs,suspend-voltage-selector = <1>;
|
||||
regulator-name = "vdd_cpu_big0_s0";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <550000>;
|
||||
regulator-max-microvolt = <1050000>;
|
||||
regulator-ramp-delay = <2300>;
|
||||
vin-supply = <&vcc_sysin>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_cpu_big1_s0: regulator@43 {
|
||||
compatible = "rockchip,rk8603", "rockchip,rk8602";
|
||||
reg = <0x43>;
|
||||
fcs,suspend-voltage-selector = <1>;
|
||||
regulator-name = "vdd_cpu_big1_s0";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <550000>;
|
||||
regulator-max-microvolt = <1050000>;
|
||||
regulator-ramp-delay = <2300>;
|
||||
vin-supply = <&vcc_sysin>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
eeprom@50 {
|
||||
compatible = "belling,bl24c16a", "atmel,24c16";
|
||||
reg = <0x50>;
|
||||
pagesize = <16>;
|
||||
vcc-supply = <&vcc_3v3_pmu>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
status = "okay";
|
||||
|
||||
vdd_npu_s0: regulator@42 {
|
||||
compatible = "rockchip,rk8602";
|
||||
reg = <0x42>;
|
||||
fcs,suspend-voltage-selector = <1>;
|
||||
regulator-name = "vdd_npu_s0";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <550000>;
|
||||
regulator-max-microvolt = <950000>;
|
||||
regulator-ramp-delay = <2300>;
|
||||
vin-supply = <&vcc_sysin>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c5 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c5m2_xfer>;
|
||||
status = "okay";
|
||||
|
||||
rtc@51 {
|
||||
compatible = "haoyu,hym8563";
|
||||
reg = <0x51>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "rtcic_32kout";
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&rtc_int_l>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c7 {
|
||||
status = "okay";
|
||||
|
||||
audio-codec@11 {
|
||||
compatible = "everest,es8316";
|
||||
reg = <0x11>;
|
||||
assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
|
||||
assigned-clock-rates = <12288000>;
|
||||
clocks = <&cru I2S0_8CH_MCLKOUT>;
|
||||
clock-names = "mclk";
|
||||
#sound-dai-cells = <0>;
|
||||
|
||||
port {
|
||||
es8316_p0_0: endpoint {
|
||||
remote-endpoint = <&i2s0_8ch_p0_0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2s0_8ch {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2s0_lrck
|
||||
&i2s0_mclk
|
||||
&i2s0_sclk
|
||||
&i2s0_sdi0
|
||||
&i2s0_sdo0>;
|
||||
status = "okay";
|
||||
|
||||
i2s0_8ch_p0: port {
|
||||
i2s0_8ch_p0_0: endpoint {
|
||||
dai-format = "i2s";
|
||||
mclk-fs = <256>;
|
||||
remote-endpoint = <&es8316_p0_0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mdio1 {
|
||||
rgmii_phy1: ethernet-phy@1 {
|
||||
compatible = "ethernet-phy-id001c.c916";
|
||||
reg = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac1_rstn>;
|
||||
reset-assert-us = <20000>;
|
||||
reset-deassert-us = <100000>;
|
||||
reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
&pcie2x1l2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie20x1_2_perstn_m0>;
|
||||
reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&pcie2x1l2_3v3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
leds {
|
||||
led_pins: led-pins {
|
||||
rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>,
|
||||
<3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
mdio {
|
||||
gmac1_rstn: gmac1-rstn {
|
||||
rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie {
|
||||
pcie20x1_2_perstn_m0: pcie20x1-2-perstn-m0 {
|
||||
rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
pow_en: pow-en {
|
||||
rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
rtc {
|
||||
rtc_int_l: rtc-int-l {
|
||||
rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
usb {
|
||||
usb_host_pwren_h: usb-host-pwren-h {
|
||||
rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
usb_otg_pwren_h: usb-otg-pwren-h {
|
||||
rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
usb_wifi_pwr: usb-wifi-pwr {
|
||||
rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
vcc_5v0_pwren_h: vcc-5v0-pwren-h {
|
||||
rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pwm3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm3m1_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&saradc {
|
||||
vref-supply = <&vcca_1v8_s0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci {
|
||||
bus-width = <8>;
|
||||
mmc-hs400-1_8v;
|
||||
mmc-hs400-enhanced-strobe;
|
||||
no-sdio;
|
||||
no-sd;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc {
|
||||
bus-width = <4>;
|
||||
cap-mmc-highspeed;
|
||||
cap-sd-highspeed;
|
||||
disable-wp;
|
||||
no-sdio;
|
||||
no-mmc;
|
||||
sd-uhs-sdr104;
|
||||
vmmc-supply = <&vcc_3v3_s3>;
|
||||
vqmmc-supply = <&vccio_sd_s0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sfc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&fspim0_pins>;
|
||||
|
||||
flash@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <104000000>;
|
||||
spi-rx-bus-width = <4>;
|
||||
spi-tx-bus-width = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&spi2 {
|
||||
status = "okay";
|
||||
assigned-clocks = <&cru CLK_SPI2>;
|
||||
assigned-clock-rates = <200000000>;
|
||||
num-cs = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
|
||||
|
||||
pmic@0 {
|
||||
compatible = "rockchip,rk806";
|
||||
reg = <0>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
|
||||
<&rk806_dvs2_null>, <&rk806_dvs3_null>;
|
||||
spi-max-frequency = <1000000>;
|
||||
system-power-controller;
|
||||
|
||||
vcc1-supply = <&vcc_sysin>;
|
||||
vcc2-supply = <&vcc_sysin>;
|
||||
vcc3-supply = <&vcc_sysin>;
|
||||
vcc4-supply = <&vcc_sysin>;
|
||||
vcc5-supply = <&vcc_sysin>;
|
||||
vcc6-supply = <&vcc_sysin>;
|
||||
vcc7-supply = <&vcc_sysin>;
|
||||
vcc8-supply = <&vcc_sysin>;
|
||||
vcc9-supply = <&vcc_sysin>;
|
||||
vcc10-supply = <&vcc_sysin>;
|
||||
vcc11-supply = <&vcc_2v0_pldo_s3>;
|
||||
vcc12-supply = <&vcc_sysin>;
|
||||
vcc13-supply = <&vcc_1v1_nldo_s3>;
|
||||
vcc14-supply = <&vcc_1v1_nldo_s3>;
|
||||
vcca-supply = <&vcca>;
|
||||
|
||||
rk806_dvs1_null: dvs1-null-pins {
|
||||
pins = "gpio_pwrctrl1";
|
||||
function = "pin_fun0";
|
||||
};
|
||||
|
||||
rk806_dvs2_null: dvs2-null-pins {
|
||||
pins = "gpio_pwrctrl2";
|
||||
function = "pin_fun0";
|
||||
};
|
||||
|
||||
rk806_dvs3_null: dvs3-null-pins {
|
||||
pins = "gpio_pwrctrl3";
|
||||
function = "pin_fun0";
|
||||
};
|
||||
|
||||
regulators {
|
||||
vdd_gpu_s0: dcdc-reg1 {
|
||||
regulator-name = "vdd_gpu_s0";
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <550000>;
|
||||
regulator-max-microvolt = <950000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
regulator-enable-ramp-delay = <400>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_cpu_lit_s0: dcdc-reg2 {
|
||||
regulator-name = "vdd_cpu_lit_s0";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <550000>;
|
||||
regulator-max-microvolt = <950000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_logic_s0: dcdc-reg3 {
|
||||
regulator-name = "vdd_logic_s0";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <675000>;
|
||||
regulator-max-microvolt = <750000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <750000>;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_vdenc_s0: dcdc-reg4 {
|
||||
regulator-name = "vdd_vdenc_s0";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <550000>;
|
||||
regulator-max-microvolt = <950000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_ddr_s0: dcdc-reg5 {
|
||||
regulator-name = "vdd_ddr_s0";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <675000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <850000>;
|
||||
};
|
||||
};
|
||||
|
||||
vdd2_ddr_s3: dcdc-reg6 {
|
||||
regulator-name = "vdd2_ddr_s3";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_2v0_pldo_s3: dcdc-reg7 {
|
||||
regulator-name = "vdd_2v0_pldo_s3";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <2000000>;
|
||||
regulator-max-microvolt = <2000000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <2000000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_3v3_s3: dcdc-reg8 {
|
||||
regulator-name = "vcc_3v3_s3";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vddq_ddr_s0: dcdc-reg9 {
|
||||
regulator-name = "vddq_ddr_s0";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc1v8_pmu_ddr_s3: dcdc-reg10 {
|
||||
regulator-name = "vcc1v8_pmu_ddr_s3";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v8_s0: pldo-reg1 {
|
||||
regulator-name = "vcc_1v8_s0";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca_1v8_s0: pldo-reg2 {
|
||||
regulator-name = "vcca_1v8_s0";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vdda_1v2_s0: pldo-reg3 {
|
||||
regulator-name = "vdda_1v2_s0";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcca_3v3_s0: pldo-reg4 {
|
||||
regulator-name = "vcca_3v3_s0";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_sd_s0: pldo-reg5 {
|
||||
regulator-name = "vccio_sd_s0";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
pldo6_s3: pldo-reg6 {
|
||||
regulator-name = "pldo6_s3";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_0v75_s3: nldo-reg1 {
|
||||
regulator-name = "vdd_0v75_s3";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <750000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <750000>;
|
||||
};
|
||||
};
|
||||
|
||||
vdda_ddr_pll_s0: nldo-reg2 {
|
||||
regulator-name = "vdda_ddr_pll_s0";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <850000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <850000>;
|
||||
};
|
||||
};
|
||||
|
||||
vdda_0v75_s0: nldo-reg3 {
|
||||
regulator-name = "vdda_0v75_s0";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <750000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda_0v85_s0: nldo-reg4 {
|
||||
regulator-name = "vdda_0v85_s0";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <850000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_0v75_s0: nldo-reg5 {
|
||||
regulator-name = "vdd_0v75_s0";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <750000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&tsadc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy0_otg {
|
||||
phy-supply = <&vcc5v0_usb_otg0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy2_host {
|
||||
/* connected to USB hub, which is powered by vcc_5v0 */
|
||||
phy-supply = <&vcc_5v0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy3_host {
|
||||
phy-supply = <&vcc5v0_usb_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
pinctrl-0 = <&uart2m0_xfer>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbdp_phy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_xhci {
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host2_xhci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vop_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vop {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vp0 {
|
||||
vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
|
||||
reg = <ROCKCHIP_VOP2_EP_HDMI0>;
|
||||
remote-endpoint = <&hdmi0_in_vp0>;
|
||||
};
|
||||
};
|
||||
15
include/configs/khadas-edge2-rk3588s.h
Normal file
15
include/configs/khadas-edge2-rk3588s.h
Normal file
@@ -0,0 +1,15 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (c) 2024 Khadas Technology Co., Ltd.
|
||||
*/
|
||||
|
||||
#ifndef __KHADAS_EDGE2_RK3588_H
|
||||
#define __KHADAS_EDGE2_RK3588_H
|
||||
|
||||
#include <configs/rk3588_common.h>
|
||||
|
||||
#define ROCKCHIP_DEVICE_SETTINGS \
|
||||
"stdout=serial,vidconsole\0" \
|
||||
"stderr=serial,vidconsole\0"
|
||||
|
||||
#endif /* __KHADAS_EDGE2_RK3588_H */
|
||||
@@ -20,16 +20,16 @@
|
||||
#endif
|
||||
|
||||
#define ENV_MEM_LAYOUT_SETTINGS \
|
||||
"scriptaddr=0x00500000\0" \
|
||||
"scriptaddr=0x00c00000\0" \
|
||||
"script_offset_f=0xffe000\0" \
|
||||
"script_size_f=0x2000\0" \
|
||||
"pxefile_addr_r=0x00600000\0" \
|
||||
"fdt_addr_r=0x01e00000\0" \
|
||||
"fdtoverlay_addr_r=0x01f00000\0" \
|
||||
"kernel_addr_r=0x02080000\0" \
|
||||
"ramdisk_addr_r=0x06000000\0" \
|
||||
"kernel_comp_addr_r=0x08000000\0" \
|
||||
"kernel_comp_size=0x2000000\0"
|
||||
"pxefile_addr_r=0x00e00000\0" \
|
||||
"kernel_addr_r=0x02000000\0" \
|
||||
"kernel_comp_addr_r=0x0a000000\0" \
|
||||
"fdt_addr_r=0x12000000\0" \
|
||||
"fdtoverlay_addr_r=0x12100000\0" \
|
||||
"ramdisk_addr_r=0x12180000\0" \
|
||||
"kernel_comp_size=0x8000000\0"
|
||||
|
||||
#define CFG_EXTRA_ENV_SETTINGS \
|
||||
"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
|
||||
|
||||
15
include/configs/rock-5c-rk3588s.h
Normal file
15
include/configs/rock-5c-rk3588s.h
Normal file
@@ -0,0 +1,15 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (c) 2024-2025 Radxa Computer (Shenzhen) Co., Ltd.
|
||||
*/
|
||||
|
||||
#ifndef __ROCK_5C_RK3588S_H
|
||||
#define __ROCK_5C_RK3588S_H
|
||||
|
||||
#define ROCKCHIP_DEVICE_SETTINGS \
|
||||
"stdout=serial,vidconsole\0" \
|
||||
"stderr=serial,vidconsole\0"
|
||||
|
||||
#include <configs/rk3588_common.h>
|
||||
|
||||
#endif /* __ROCK_5C_RK3588S_H */
|
||||
@@ -1,31 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (c) 2014 MundoReader S.L.
|
||||
* Author: Heiko Stuebner <heiko@sntech.de>
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3066A_H
|
||||
#define _DT_BINDINGS_CLK_ROCKCHIP_RK3066A_H
|
||||
|
||||
#include <dt-bindings/clock/rk3188-cru-common.h>
|
||||
|
||||
/* soft-reset indices */
|
||||
#define SRST_SRST1 0
|
||||
#define SRST_SRST2 1
|
||||
|
||||
#define SRST_L2MEM 18
|
||||
#define SRST_I2S0 23
|
||||
#define SRST_I2S1 24
|
||||
#define SRST_I2S2 25
|
||||
#define SRST_TIMER2 29
|
||||
|
||||
#define SRST_GPIO4 36
|
||||
#define SRST_GPIO6 38
|
||||
|
||||
#define SRST_TSADC 92
|
||||
|
||||
#define SRST_HDMI 96
|
||||
#define SRST_HDMI_APB 97
|
||||
#define SRST_CIF1 111
|
||||
|
||||
#endif
|
||||
@@ -1,261 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
/*
|
||||
* Copyright (c) 2014 MundoReader S.L.
|
||||
* Author: Heiko Stuebner <heiko@sntech.de>
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3188_COMMON_H
|
||||
#define _DT_BINDINGS_CLK_ROCKCHIP_RK3188_COMMON_H
|
||||
|
||||
/* core clocks from */
|
||||
#define PLL_APLL 1
|
||||
#define PLL_DPLL 2
|
||||
#define PLL_CPLL 3
|
||||
#define PLL_GPLL 4
|
||||
#define CORE_PERI 5
|
||||
#define CORE_L2C 6
|
||||
#define ARMCLK 7
|
||||
|
||||
/* sclk gates (special clocks) */
|
||||
#define SCLK_UART0 64
|
||||
#define SCLK_UART1 65
|
||||
#define SCLK_UART2 66
|
||||
#define SCLK_UART3 67
|
||||
#define SCLK_MAC 68
|
||||
#define SCLK_SPI0 69
|
||||
#define SCLK_SPI1 70
|
||||
#define SCLK_SARADC 71
|
||||
#define SCLK_SDMMC 72
|
||||
#define SCLK_SDIO 73
|
||||
#define SCLK_EMMC 74
|
||||
#define SCLK_I2S0 75
|
||||
#define SCLK_I2S1 76
|
||||
#define SCLK_I2S2 77
|
||||
#define SCLK_SPDIF 78
|
||||
#define SCLK_CIF0 79
|
||||
#define SCLK_CIF1 80
|
||||
#define SCLK_OTGPHY0 81
|
||||
#define SCLK_OTGPHY1 82
|
||||
#define SCLK_HSADC 83
|
||||
#define SCLK_TIMER0 84
|
||||
#define SCLK_TIMER1 85
|
||||
#define SCLK_TIMER2 86
|
||||
#define SCLK_TIMER3 87
|
||||
#define SCLK_TIMER4 88
|
||||
#define SCLK_TIMER5 89
|
||||
#define SCLK_TIMER6 90
|
||||
#define SCLK_JTAG 91
|
||||
#define SCLK_SMC 92
|
||||
#define SCLK_TSADC 93
|
||||
|
||||
#define DCLK_LCDC0 190
|
||||
#define DCLK_LCDC1 191
|
||||
|
||||
/* aclk gates */
|
||||
#define ACLK_DMA1 192
|
||||
#define ACLK_DMA2 193
|
||||
#define ACLK_GPS 194
|
||||
#define ACLK_LCDC0 195
|
||||
#define ACLK_LCDC1 196
|
||||
#define ACLK_GPU 197
|
||||
#define ACLK_SMC 198
|
||||
#define ACLK_CIF1 199
|
||||
#define ACLK_IPP 200
|
||||
#define ACLK_RGA 201
|
||||
#define ACLK_CIF0 202
|
||||
#define ACLK_CPU 203
|
||||
#define ACLK_PERI 204
|
||||
#define ACLK_VEPU 205
|
||||
#define ACLK_VDPU 206
|
||||
|
||||
/* pclk gates */
|
||||
#define PCLK_GRF 320
|
||||
#define PCLK_PMU 321
|
||||
#define PCLK_TIMER0 322
|
||||
#define PCLK_TIMER1 323
|
||||
#define PCLK_TIMER2 324
|
||||
#define PCLK_TIMER3 325
|
||||
#define PCLK_PWM01 326
|
||||
#define PCLK_PWM23 327
|
||||
#define PCLK_SPI0 328
|
||||
#define PCLK_SPI1 329
|
||||
#define PCLK_SARADC 330
|
||||
#define PCLK_WDT 331
|
||||
#define PCLK_UART0 332
|
||||
#define PCLK_UART1 333
|
||||
#define PCLK_UART2 334
|
||||
#define PCLK_UART3 335
|
||||
#define PCLK_I2C0 336
|
||||
#define PCLK_I2C1 337
|
||||
#define PCLK_I2C2 338
|
||||
#define PCLK_I2C3 339
|
||||
#define PCLK_I2C4 340
|
||||
#define PCLK_GPIO0 341
|
||||
#define PCLK_GPIO1 342
|
||||
#define PCLK_GPIO2 343
|
||||
#define PCLK_GPIO3 344
|
||||
#define PCLK_GPIO4 345
|
||||
#define PCLK_GPIO6 346
|
||||
#define PCLK_EFUSE 347
|
||||
#define PCLK_TZPC 348
|
||||
#define PCLK_TSADC 349
|
||||
#define PCLK_CPU 350
|
||||
#define PCLK_PERI 351
|
||||
#define PCLK_DDRUPCTL 352
|
||||
#define PCLK_PUBL 353
|
||||
|
||||
/* hclk gates */
|
||||
#define HCLK_SDMMC 448
|
||||
#define HCLK_SDIO 449
|
||||
#define HCLK_EMMC 450
|
||||
#define HCLK_OTG0 451
|
||||
#define HCLK_EMAC 452
|
||||
#define HCLK_SPDIF 453
|
||||
#define HCLK_I2S0 454
|
||||
#define HCLK_I2S1 455
|
||||
#define HCLK_I2S2 456
|
||||
#define HCLK_OTG1 457
|
||||
#define HCLK_HSIC 458
|
||||
#define HCLK_HSADC 459
|
||||
#define HCLK_PIDF 460
|
||||
#define HCLK_LCDC0 461
|
||||
#define HCLK_LCDC1 462
|
||||
#define HCLK_ROM 463
|
||||
#define HCLK_CIF0 464
|
||||
#define HCLK_IPP 465
|
||||
#define HCLK_RGA 466
|
||||
#define HCLK_NANDC0 467
|
||||
#define HCLK_CPU 468
|
||||
#define HCLK_PERI 469
|
||||
#define HCLK_CIF1 470
|
||||
#define HCLK_VEPU 471
|
||||
#define HCLK_VDPU 472
|
||||
#define HCLK_HDMI 473
|
||||
|
||||
#define CLK_NR_CLKS (HCLK_HDMI + 1)
|
||||
|
||||
/* soft-reset indices */
|
||||
#define SRST_MCORE 2
|
||||
#define SRST_CORE0 3
|
||||
#define SRST_CORE1 4
|
||||
#define SRST_MCORE_DBG 7
|
||||
#define SRST_CORE0_DBG 8
|
||||
#define SRST_CORE1_DBG 9
|
||||
#define SRST_CORE0_WDT 12
|
||||
#define SRST_CORE1_WDT 13
|
||||
#define SRST_STRC_SYS 14
|
||||
#define SRST_L2C 15
|
||||
|
||||
#define SRST_CPU_AHB 17
|
||||
#define SRST_AHB2APB 19
|
||||
#define SRST_DMA1 20
|
||||
#define SRST_INTMEM 21
|
||||
#define SRST_ROM 22
|
||||
#define SRST_SPDIF 26
|
||||
#define SRST_TIMER0 27
|
||||
#define SRST_TIMER1 28
|
||||
#define SRST_EFUSE 30
|
||||
|
||||
#define SRST_GPIO0 32
|
||||
#define SRST_GPIO1 33
|
||||
#define SRST_GPIO2 34
|
||||
#define SRST_GPIO3 35
|
||||
|
||||
#define SRST_UART0 39
|
||||
#define SRST_UART1 40
|
||||
#define SRST_UART2 41
|
||||
#define SRST_UART3 42
|
||||
#define SRST_I2C0 43
|
||||
#define SRST_I2C1 44
|
||||
#define SRST_I2C2 45
|
||||
#define SRST_I2C3 46
|
||||
#define SRST_I2C4 47
|
||||
|
||||
#define SRST_PWM0 48
|
||||
#define SRST_PWM1 49
|
||||
#define SRST_DAP_PO 50
|
||||
#define SRST_DAP 51
|
||||
#define SRST_DAP_SYS 52
|
||||
#define SRST_TPIU_ATB 53
|
||||
#define SRST_PMU_APB 54
|
||||
#define SRST_GRF 55
|
||||
#define SRST_PMU 56
|
||||
#define SRST_PERI_AXI 57
|
||||
#define SRST_PERI_AHB 58
|
||||
#define SRST_PERI_APB 59
|
||||
#define SRST_PERI_NIU 60
|
||||
#define SRST_CPU_PERI 61
|
||||
#define SRST_EMEM_PERI 62
|
||||
#define SRST_USB_PERI 63
|
||||
|
||||
#define SRST_DMA2 64
|
||||
#define SRST_SMC 65
|
||||
#define SRST_MAC 66
|
||||
#define SRST_NANC0 68
|
||||
#define SRST_USBOTG0 69
|
||||
#define SRST_USBPHY0 70
|
||||
#define SRST_OTGC0 71
|
||||
#define SRST_USBOTG1 72
|
||||
#define SRST_USBPHY1 73
|
||||
#define SRST_OTGC1 74
|
||||
#define SRST_HSADC 76
|
||||
#define SRST_PIDFILTER 77
|
||||
#define SRST_DDR_MSCH 79
|
||||
|
||||
#define SRST_TZPC 80
|
||||
#define SRST_SDMMC 81
|
||||
#define SRST_SDIO 82
|
||||
#define SRST_EMMC 83
|
||||
#define SRST_SPI0 84
|
||||
#define SRST_SPI1 85
|
||||
#define SRST_WDT 86
|
||||
#define SRST_SARADC 87
|
||||
#define SRST_DDRPHY 88
|
||||
#define SRST_DDRPHY_APB 89
|
||||
#define SRST_DDRCTL 90
|
||||
#define SRST_DDRCTL_APB 91
|
||||
#define SRST_DDRPUB 93
|
||||
|
||||
#define SRST_VIO0_AXI 98
|
||||
#define SRST_VIO0_AHB 99
|
||||
#define SRST_LCDC0_AXI 100
|
||||
#define SRST_LCDC0_AHB 101
|
||||
#define SRST_LCDC0_DCLK 102
|
||||
#define SRST_LCDC1_AXI 103
|
||||
#define SRST_LCDC1_AHB 104
|
||||
#define SRST_LCDC1_DCLK 105
|
||||
#define SRST_IPP_AXI 106
|
||||
#define SRST_IPP_AHB 107
|
||||
#define SRST_RGA_AXI 108
|
||||
#define SRST_RGA_AHB 109
|
||||
#define SRST_CIF0 110
|
||||
|
||||
#define SRST_VCODEC_AXI 112
|
||||
#define SRST_VCODEC_AHB 113
|
||||
#define SRST_VIO1_AXI 114
|
||||
#define SRST_VCODEC_CPU 115
|
||||
#define SRST_VCODEC_NIU 116
|
||||
#define SRST_GPU 120
|
||||
#define SRST_GPU_NIU 122
|
||||
#define SRST_TFUN_ATB 125
|
||||
#define SRST_TFUN_APB 126
|
||||
#define SRST_CTI4_APB 127
|
||||
|
||||
#define SRST_TPIU_APB 128
|
||||
#define SRST_TRACE 129
|
||||
#define SRST_CORE_DBG 130
|
||||
#define SRST_DBG_APB 131
|
||||
#define SRST_CTI0 132
|
||||
#define SRST_CTI0_APB 133
|
||||
#define SRST_CTI1 134
|
||||
#define SRST_CTI1_APB 135
|
||||
#define SRST_PTM_CORE0 136
|
||||
#define SRST_PTM_CORE1 137
|
||||
#define SRST_PTM0 138
|
||||
#define SRST_PTM0_ATB 139
|
||||
#define SRST_PTM1 140
|
||||
#define SRST_PTM1_ATB 141
|
||||
#define SRST_CTM 142
|
||||
#define SRST_TS 143
|
||||
|
||||
#endif
|
||||
@@ -1,47 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (c) 2014 MundoReader S.L.
|
||||
* Author: Heiko Stuebner <heiko@sntech.de>
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3188_H
|
||||
#define _DT_BINDINGS_CLK_ROCKCHIP_RK3188_H
|
||||
|
||||
#include <dt-bindings/clock/rk3188-cru-common.h>
|
||||
|
||||
/* soft-reset indices */
|
||||
#define SRST_PTM_CORE2 0
|
||||
#define SRST_PTM_CORE3 1
|
||||
#define SRST_CORE2 5
|
||||
#define SRST_CORE3 6
|
||||
#define SRST_CORE2_DBG 10
|
||||
#define SRST_CORE3_DBG 11
|
||||
|
||||
#define SRST_TIMER2 16
|
||||
#define SRST_TIMER4 23
|
||||
#define SRST_I2S0 24
|
||||
#define SRST_TIMER5 25
|
||||
#define SRST_TIMER3 29
|
||||
#define SRST_TIMER6 31
|
||||
|
||||
#define SRST_PTM3 36
|
||||
#define SRST_PTM3_ATB 37
|
||||
|
||||
#define SRST_GPS 67
|
||||
#define SRST_HSICPHY 75
|
||||
#define SRST_TIMER 78
|
||||
|
||||
#define SRST_PTM2 92
|
||||
#define SRST_CORE2_WDT 94
|
||||
#define SRST_CORE3_WDT 95
|
||||
|
||||
#define SRST_PTM2_ATB 111
|
||||
|
||||
#define SRST_HSIC 117
|
||||
#define SRST_CTI2 118
|
||||
#define SRST_CTI2_APB 119
|
||||
#define SRST_GPU_BRIDGE 121
|
||||
#define SRST_CTI3 123
|
||||
#define SRST_CTI3_APB 124
|
||||
|
||||
#endif
|
||||
@@ -1,22 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __DT_BINDINGS_POWER_RK3066_POWER_H__
|
||||
#define __DT_BINDINGS_POWER_RK3066_POWER_H__
|
||||
|
||||
/* VD_CORE */
|
||||
#define RK3066_PD_A9_0 0
|
||||
#define RK3066_PD_A9_1 1
|
||||
#define RK3066_PD_DBG 4
|
||||
#define RK3066_PD_SCU 5
|
||||
|
||||
/* VD_LOGIC */
|
||||
#define RK3066_PD_VIDEO 6
|
||||
#define RK3066_PD_VIO 7
|
||||
#define RK3066_PD_GPU 8
|
||||
#define RK3066_PD_PERI 9
|
||||
#define RK3066_PD_CPU 10
|
||||
#define RK3066_PD_ALIVE 11
|
||||
|
||||
/* VD_PMU */
|
||||
#define RK3066_PD_RTC 12
|
||||
|
||||
#endif
|
||||
@@ -1,24 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __DT_BINDINGS_POWER_RK3188_POWER_H__
|
||||
#define __DT_BINDINGS_POWER_RK3188_POWER_H__
|
||||
|
||||
/* VD_CORE */
|
||||
#define RK3188_PD_A9_0 0
|
||||
#define RK3188_PD_A9_1 1
|
||||
#define RK3188_PD_A9_2 2
|
||||
#define RK3188_PD_A9_3 3
|
||||
#define RK3188_PD_DBG 4
|
||||
#define RK3188_PD_SCU 5
|
||||
|
||||
/* VD_LOGIC */
|
||||
#define RK3188_PD_VIDEO 6
|
||||
#define RK3188_PD_VIO 7
|
||||
#define RK3188_PD_GPU 8
|
||||
#define RK3188_PD_PERI 9
|
||||
#define RK3188_PD_CPU 10
|
||||
#define RK3188_PD_ALIVE 11
|
||||
|
||||
/* VD_PMU */
|
||||
#define RK3188_PD_RTC 12
|
||||
|
||||
#endif
|
||||
@@ -1,32 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __DT_BINDINGS_POWER_RK3288_POWER_H__
|
||||
#define __DT_BINDINGS_POWER_RK3288_POWER_H__
|
||||
|
||||
/**
|
||||
* RK3288 Power Domain and Voltage Domain Summary.
|
||||
*/
|
||||
|
||||
/* VD_CORE */
|
||||
#define RK3288_PD_A17_0 0
|
||||
#define RK3288_PD_A17_1 1
|
||||
#define RK3288_PD_A17_2 2
|
||||
#define RK3288_PD_A17_3 3
|
||||
#define RK3288_PD_SCU 4
|
||||
#define RK3288_PD_DEBUG 5
|
||||
#define RK3288_PD_MEM 6
|
||||
|
||||
/* VD_LOGIC */
|
||||
#define RK3288_PD_BUS 7
|
||||
#define RK3288_PD_PERI 8
|
||||
#define RK3288_PD_VIO 9
|
||||
#define RK3288_PD_ALIVE 10
|
||||
#define RK3288_PD_HEVC 11
|
||||
#define RK3288_PD_VIDEO 12
|
||||
|
||||
/* VD_GPU */
|
||||
#define RK3288_PD_GPU 13
|
||||
|
||||
/* VD_PMU */
|
||||
#define RK3288_PD_PMU 14
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user