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Merge tag 'u-boot-rockchip-20230629' of https://source.denx.de/u-boot/custodians/u-boot-rockchip

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- rockchip inno phy fix;
- pinctrl driver in SPL arort in specific case;
- fix IO port voltage for rock5b-rk3588 board;
This commit is contained in:
Tom Rini
2023-06-29 09:52:48 -04:00
parent 580eb31199 d77d5301d7
commit bd8de8f4fc
4 changed files with 16 additions and 30 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
arch/arm/mach-rockchip/rk3588/Kconfig
View File

@@ -34,15 +34,15 @@ config TARGET_ROCK5B_RK3588
4x ARM Cortex-A76, 4x ARM Cortex-A55
4/8/16GB memory LPDDR4x
Mali G610MC4 GPU
MIPI CSI 2 multiple lanes connector
2x MIPI CSI 2 multiple lanes connector
eMMC module connector
uSD slot (up to 128GB)
2x USB 2.0, 2x USB 3.0
2x HDMI output, 1x HDMI input
Ethernet port
2x USB 2.0 Type-A, 2x USB 3.0 Type-A, 1x USB 3.0 Type-C
2x HDMI 2.1 output, 1x micro HDMI input
2.5 Gbps Ethernet port
40-pin IO header including UART, SPI, I2C and 5V DC power in
USB PD over USB Type-C
Size: 85mm x 54mm
Size: 100mm x 72mm (Pico-ITX form factor)
config ROCKCHIP_BOOT_MODE_REG
default 0xfd588080

6
board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c
View File

@@ -15,7 +15,8 @@
#include <asm/arch-rockchip/misc.h>
#include <power/regulator.h>
#define GRF_IO_VSEL_BT565_SHIFT 0
#define GRF_IO_VSEL_BT565_GPIO2AB 1
#define GRF_IO_VSEL_AUDIO_GPIO3D4A 2
#define PMUGRF_CON0_VSEL_SHIFT 8
#ifndef CONFIG_SPL_BUILD
@@ -48,7 +49,8 @@ static void setup_iodomain(void)
syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
/* BT565 is in 1.8v domain */
rk_setreg(&grf->io_vsel, 1 << GRF_IO_VSEL_BT565_SHIFT);
rk_setreg(&grf->io_vsel,
GRF_IO_VSEL_BT565_GPIO2AB | GRF_IO_VSEL_AUDIO_GPIO3D4A);
/* Set GPIO1 1.8v/3.0v source select to PMU1830_VOL */
rk_setreg(&pmugrf->soc_con0, 1 << PMUGRF_CON0_VSEL_SHIFT);

2
drivers/phy/rockchip/phy-rockchip-inno-usb2.c
View File

@@ -259,7 +259,7 @@ static int rockchip_usb2phy_probe(struct udevice *dev)
}
/* support address_cells=2 */
if (reg == 0) {
if (dev_read_addr_cells(dev) == 2 && reg == 0) {
if (ofnode_read_u32_index(dev_ofnode(dev), "reg", 1, &reg)) {
dev_err(dev, "%s must have reg[1]\n",
ofnode_get_name(dev_ofnode(dev)));

28
drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
View File

@@ -12,7 +12,6 @@
#include <fdtdec.h>
#include <linux/bitops.h>
#include <linux/libfdt.h>
#include <asm/global_data.h>
#include "pinctrl-rockchip.h"
@@ -433,13 +432,7 @@ static int rockchip_pinctrl_set_state(struct udevice *dev,
int prop_len, param;
const u32 *data;
ofnode node;
#ifdef CONFIG_OF_LIVE
const struct device_node *np;
struct property *pp;
#else
int property_offset, pcfg_node;
const void *blob = gd->fdt_blob;
#endif
struct ofprop prop;
data = dev_read_prop(config, "rockchip,pins", &count);
if (count < 0) {
debug("%s: bad array size %d\n", __func__, count);
@@ -473,24 +466,15 @@ static int rockchip_pinctrl_set_state(struct udevice *dev,
node = ofnode_get_by_phandle(conf);
if (!ofnode_valid(node))
return -ENODEV;
#ifdef CONFIG_OF_LIVE
np = ofnode_to_np(node);
for (pp = np->properties; pp; pp = pp->next) {
prop_name = pp->name;
prop_len = pp->length;
value = pp->value;
#else
pcfg_node = ofnode_to_offset(node);
fdt_for_each_property_offset(property_offset, blob, pcfg_node) {
value = fdt_getprop_by_offset(blob, property_offset,
&prop_name, &prop_len);
ofnode_for_each_prop(prop, node) {
value = ofprop_get_property(&prop, &prop_name, &prop_len);
if (!value)
return -ENOENT;
#endif
continue;
param = rockchip_pinconf_prop_name_to_param(prop_name,
&default_val);
if (param < 0)
break;
continue;
if (prop_len >= sizeof(fdt32_t))
arg = fdt32_to_cpu(*(fdt32_t *)value);