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mmc: socfpga_dw_mmc: Retrieve clock manager address via DT

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Update the MMC driver to retrieve the clock manager base address via
probing the clock manager node in the device tree.

Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
Alif Zakuan Yuslaimi
2025-06-19 23:28:40 -07:00
committed by Peng Fan
parent 49666c41e9
commit be7fc8f331
1 changed files with 18 additions and 4 deletions
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22
drivers/mmc/socfpga_dw_mmc.c
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@@ -54,16 +54,30 @@ static int socfpga_dwmci_clksel(struct dwmci_host *host)
u32 sdmmc_mask = ((priv->smplsel & 0x7) << SYSMGR_SDMMC_SMPLSEL_SHIFT) |
((priv->drvsel & 0x7) << SYSMGR_SDMMC_DRVSEL_SHIFT);
/* Get clock manager base address */
struct udevice *clkmgr_dev;
int ret = uclass_get_device_by_name(UCLASS_CLK, "clock-controller@ffd10000", &clkmgr_dev);
if (ret) {
printf("Failed to get clkmgr device: %d\n", ret);
return ret;
}
fdt_addr_t clkmgr_base = dev_read_addr(clkmgr_dev);
if (clkmgr_base == FDT_ADDR_T_NONE) {
printf("Failed to read base address from clkmgr DT node\n");
return -EINVAL;
}
/* Disable SDMMC clock. */
clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN,
clrbits_le32(clkmgr_base + CLKMGR_PERPLL_EN,
CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
debug("%s: drvsel %d smplsel %d\n", __func__,
priv->drvsel, priv->smplsel);
#if !defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_ATF)
int ret;
ret = socfpga_secure_reg_write32(SOCFPGA_SECURE_REG_SYSMGR_SOC64_SDMMC,
sdmmc_mask);
if (ret) {
@@ -78,7 +92,7 @@ static int socfpga_dwmci_clksel(struct dwmci_host *host)
#endif
/* Enable SDMMC clock */
setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN,
setbits_le32(clkmgr_base + CLKMGR_PERPLL_EN,
CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
return 0;