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clk: rockchip: rk3328: Handle usb480m phy clock

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Handle USB480M clock ID in set_rate() and set_parent()
to allow the dt assigned-clocks and assigned-clock-parents
work on rk3328.dtsi

Cc: Lukasz Majewski <lukma@denx.de>
Cc: Sean Anderson <seanga2@gmail.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Jagan Teki
2023-06-06 22:39:17 +05:30
committed by Kever Yang
parent 9aa93d8403
commit c016525858
1 changed files with 2 additions and 0 deletions
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2
drivers/clk/rockchip/clk_rk3328.c
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@@ -681,6 +681,7 @@ static ulong rk3328_clk_set_rate(struct clk *clk, ulong rate)
case ACLK_GMAC:
case PCLK_GMAC:
case SCLK_USB3OTG_SUSPEND:
case USB480M:
return 0;
default:
return -ENOENT;
@@ -771,6 +772,7 @@ static int rk3328_clk_set_parent(struct clk *clk, struct clk *parent)
case SCLK_MAC2IO_EXT:
return rk3328_gmac2io_ext_set_parent(clk, parent);
case DCLK_LCDC:
case USB480M:
case SCLK_PDM:
case SCLK_RTC32K:
case SCLK_UART0: