Mirrors/u-boot
1
0
Fork 0
mirror of https://source.denx.de/u-boot/u-boot.git synced 2026-06-13 15:03:58 +03:00
Code Issues Packages Projects Releases Wiki Activity

Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi

Browse Source 
Not many and nothing really exciting this time: there are more patches
in fly, but they are not ready yet.  I will also send some DT updates
and new board defconfig files later, once they have seen the list. I am
aware of the USB rebasing repo efforts, but would like to see how this
plays out, also we have one compatibility issue that I painstakingly
work around in the U-Boot tree for the last three years or so. So for
now I stick to the previous approach.

So now just some easy changes: support for USB peripheral mode on the
Allwinner F1C100s, T113-s3 SPI boot support, and some SPL cleanup
patches.

The branch passed the gitlab CI run, and brief boot testing on some
boards didn't turn up any issues.
This commit is contained in:
Tom Rini
2024-04-22 10:24:34 -06:00
parent 0eb249748e 192c5c9e51
commit c18ead4ba7
14 changed files with 163 additions and 124 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
arch/arm/include/asm/arch-sunxi/clock_sun9i.h
View File

@@ -220,10 +220,7 @@ struct sunxi_ccm_reg {
#ifndef __ASSEMBLY__
void clock_set_pll1(unsigned int clk);
void clock_set_pll2(unsigned int clk);
void clock_set_pll4(unsigned int clk);
void clock_set_pll6(unsigned int clk);
void clock_set_pll12(unsigned int clk);
unsigned int clock_get_pll4_periph0(void);
#endif

6
arch/arm/include/asm/arch-sunxi/tzpc.h
View File

@@ -28,6 +28,12 @@ struct sunxi_tzpc {
#define SUN8I_H3_TZPC_DECPORT1_ALL 0xff
#define SUN8I_H3_TZPC_DECPORT2_ALL 0x7f
#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_H3
void tzpc_init(void);
#else
static inline void tzpc_init(void)
{
}
#endif
#endif /* _SUNXI_TZPC_H */

2
arch/arm/mach-sunxi/Kconfig
View File

@@ -1078,7 +1078,7 @@ config SPL_STACK_R_ADDR
config SPL_SPI_SUNXI
bool "Support for SPI Flash on Allwinner SoCs in SPL"
depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || SUN50I_GEN_H6 || MACH_SUNIV
depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || SUN50I_GEN_H6 || MACH_SUNIV || SUNXI_GEN_NCAT2
help
Enable support for SPI Flash. This option allows SPL to read from
sunxi SPI Flash. It uses the same method as the boot ROM, so does

2
arch/arm/mach-sunxi/Makefile
View File

@@ -7,7 +7,6 @@
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
obj-y += board.o
obj-y += clock.o
obj-y += cpu_info.o
obj-y += dram_helpers.o
obj-$(CONFIG_SUN6I_PRCM) += prcm.o
@@ -31,6 +30,7 @@ obj-y += timer.o
endif
ifdef CONFIG_SPL_BUILD
obj-y += clock.o
obj-$(CONFIG_MACH_SUNIV) += dram_suniv.o
obj-$(CONFIG_DRAM_SUN4I) += dram_sun4i.o
obj-$(CONFIG_DRAM_SUN6I) += dram_sun6i.o

2
arch/arm/mach-sunxi/board.c
View File

@@ -458,10 +458,8 @@ void board_init_f(ulong dummy)
{
sunxi_sram_init();
#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_H3
/* Enable non-secure access to some peripherals */
tzpc_init();
#endif
clock_init();
timer_init();

2
arch/arm/mach-sunxi/clock.c
View File

@@ -23,10 +23,8 @@ __weak void gtbus_init(void)
int clock_init(void)
{
#ifdef CONFIG_SPL_BUILD
clock_init_safe();
gtbus_init();
#endif
clock_init_uart();
clock_init_sec();

5
arch/arm/mach-sunxi/clock_sun4i.c
View File

@@ -43,7 +43,6 @@ void clock_init_safe(void)
setbits_le32(&ccm->pll6_cfg, 0x1 << CCM_PLL6_CTRL_SATA_EN_SHIFT);
#endif
}
#endif
void clock_init_uart(void)
{
@@ -77,7 +76,6 @@ int clock_twi_onoff(int port, int state)
return 0;
}
#ifdef CONFIG_SPL_BUILD
#define PLL1_CFG(N, K, M, P) ( 1 << CCM_PLL1_CFG_ENABLE_SHIFT | \
0 << CCM_PLL1_CFG_VCO_RST_SHIFT | \
8 << CCM_PLL1_CFG_VCO_BIAS_SHIFT | \
@@ -177,8 +175,9 @@ void clock_set_pll1(unsigned int hz)
&ccm->cpu_ahb_apb0_cfg);
sdelay(20);
}
#endif
#endif /* CONFIG_SPL_BUILD */
/* video, DRAM, PLL_PERIPH clocks */
void clock_set_pll3(unsigned int clk)
{
struct sunxi_ccm_reg * const ccm =

57
arch/arm/mach-sunxi/clock_sun50i_h6.c
View File

@@ -51,7 +51,6 @@ void clock_init_safe(void)
*/
writel(MBUS_CLK_SRC_PLL6X2 | MBUS_CLK_M(3), &ccm->mbus_cfg);
}
#endif
void clock_init_uart(void)
{
@@ -73,7 +72,6 @@ void clock_init_uart(void)
1 << (RESET_SHIFT + CONFIG_CONS_INDEX - 1));
}
#ifdef CONFIG_SPL_BUILD
void clock_set_pll1(unsigned int clk)
{
struct sunxi_ccm_reg * const ccm =
@@ -105,33 +103,6 @@ void clock_set_pll1(unsigned int clk)
val |= CCM_CPU_AXI_MUX_PLL_CPUX;
writel(val, &ccm->cpu_axi_cfg);
}
#endif
unsigned int clock_get_pll6(void)
{
struct sunxi_ccm_reg *const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
uint32_t rval = readl(&ccm->pll6_cfg);
int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1;
int div2 = ((rval & CCM_PLL6_CTRL_DIV2_MASK) >>
CCM_PLL6_CTRL_DIV2_SHIFT) + 1;
int div1, m;
if (IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) {
div1 = ((rval & CCM_PLL6_CTRL_P0_MASK) >>
CCM_PLL6_CTRL_P0_SHIFT) + 1;
m = 1;
} else {
div1 = ((rval & CCM_PLL6_CTRL_DIV1_MASK) >>
CCM_PLL6_CTRL_DIV1_SHIFT) + 1;
if (IS_ENABLED(CONFIG_MACH_SUN50I_H6))
m = 4;
else
m = 2;
}
return 24000000U * n / m / div1 / div2;
}
int clock_twi_onoff(int port, int state)
{
@@ -160,3 +131,31 @@ int clock_twi_onoff(int port, int state)
return 0;
}
#endif /* CONFIG_SPL_BUILD */
/* PLL_PERIPH0 clock, used by the MMC driver */
unsigned int clock_get_pll6(void)
{
struct sunxi_ccm_reg *const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
uint32_t rval = readl(&ccm->pll6_cfg);
int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1;
int div2 = ((rval & CCM_PLL6_CTRL_DIV2_MASK) >>
CCM_PLL6_CTRL_DIV2_SHIFT) + 1;
int div1, m;
if (IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) {
div1 = ((rval & CCM_PLL6_CTRL_P0_MASK) >>
CCM_PLL6_CTRL_P0_SHIFT) + 1;
m = 1;
} else {
div1 = ((rval & CCM_PLL6_CTRL_DIV1_MASK) >>
CCM_PLL6_CTRL_DIV1_SHIFT) + 1;
if (IS_ENABLED(CONFIG_MACH_SUN50I_H6))
m = 4;
else
m = 2;
}
return 24000000U * n / m / div1 / div2;
}

3
arch/arm/mach-sunxi/clock_sun6i.c
View File

@@ -62,7 +62,6 @@ void clock_init_safe(void)
setbits_le32(&ccm->sata_clk_cfg, CCM_SATA_CTRL_ENABLE);
#endif
}
#endif /* CONFIG_SPL_BUILD */
void clock_init_sec(void)
{
@@ -124,7 +123,6 @@ void clock_init_uart(void)
#endif
}
#ifdef CONFIG_SPL_BUILD
void clock_set_pll1(unsigned int clk)
{
struct sunxi_ccm_reg * const ccm =
@@ -173,6 +171,7 @@ void clock_set_pll1(unsigned int clk)
}
#endif /* CONFIG_SPL_BUILD */
/* video, DRAM, PLL_PERIPH clocks */
void clock_set_pll3(unsigned int clk)
{
struct sunxi_ccm_reg * const ccm =

5
arch/arm/mach-sunxi/clock_sun8i_a83t.c
View File

@@ -46,7 +46,6 @@ void clock_init_safe(void)
/* timestamp */
writel(1, 0x01720000);
}
#endif
void clock_init_uart(void)
{
@@ -70,7 +69,6 @@ void clock_init_uart(void)
CONFIG_CONS_INDEX - 1));
}
#ifdef CONFIG_SPL_BUILD
void clock_set_pll1(unsigned int clk)
{
struct sunxi_ccm_reg * const ccm =
@@ -102,8 +100,9 @@ void clock_set_pll1(unsigned int clk)
CPU_CLK_SRC_PLL1 << C1_CPUX_CLK_SRC_SHIFT,
&ccm->cpu_axi_cfg);
}
#endif
#endif /* CONFIG_SPL_BUILD */
/* DRAM and PLL_PERIPH0 clock (used by the MMC driver) */
void clock_set_pll5(unsigned int clk)
{
struct sunxi_ccm_reg * const ccm =

97
arch/arm/mach-sunxi/clock_sun9i.c
View File

@@ -17,6 +17,52 @@
#ifdef CONFIG_SPL_BUILD
static void clock_set_pll2(unsigned int clk)
{
struct sunxi_ccm_reg * const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
const int p = 0;
/* Switch cluster 1 to 24MHz clock while changing PLL2 */
clrsetbits_le32(&ccm->cpu_clk_source, C1_CPUX_CLK_SRC_MASK,
C1_CPUX_CLK_SRC_OSC24M);
writel(CCM_PLL2_CTRL_EN | CCM_PLL2_CTRL_P(p) |
CCM_PLL2_CLOCK_TIME_2 | CCM_PLL2_CTRL_N(clk / 24000000),
&ccm->pll2_c1_cfg);
sdelay(2000);
/* Switch cluster 1 back to PLL2 */
clrsetbits_le32(&ccm->cpu_clk_source, C1_CPUX_CLK_SRC_MASK,
C1_CPUX_CLK_SRC_PLL2);
}
static void clock_set_pll4(unsigned int clk)
{
struct sunxi_ccm_reg * const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
writel(CCM_PLL4_CTRL_EN | CCM_PLL4_CTRL_N(clk / 24000000),
&ccm->pll4_periph0_cfg);
sdelay(2000);
}
static void clock_set_pll12(unsigned int clk)
{
struct sunxi_ccm_reg * const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
if (readl(&ccm->pll12_periph1_cfg) & CCM_PLL12_CTRL_EN)
return;
writel(CCM_PLL12_CTRL_EN | CCM_PLL12_CTRL_N(clk / 24000000),
&ccm->pll12_periph1_cfg);
sdelay(2000);
}
void clock_init_safe(void)
{
struct sunxi_ccm_reg * const ccm =
@@ -63,7 +109,6 @@ void clock_init_safe(void)
/* set enable-bit in TSTAMP_CTRL_REG */
writel(1, 0x01720000);
}
#endif
void clock_init_uart(void)
{
@@ -80,7 +125,6 @@ void clock_init_uart(void)
CONFIG_CONS_INDEX - 1));
}
#ifdef CONFIG_SPL_BUILD
void clock_set_pll1(unsigned int clk)
{
struct sunxi_ccm_reg * const ccm =
@@ -108,27 +152,6 @@ void clock_set_pll1(unsigned int clk)
C0_CPUX_CLK_SRC_PLL1);
}
void clock_set_pll2(unsigned int clk)
{
struct sunxi_ccm_reg * const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
const int p = 0;
/* Switch cluster 1 to 24MHz clock while changing PLL2 */
clrsetbits_le32(&ccm->cpu_clk_source, C1_CPUX_CLK_SRC_MASK,
C1_CPUX_CLK_SRC_OSC24M);
writel(CCM_PLL2_CTRL_EN | CCM_PLL2_CTRL_P(p) |
CCM_PLL2_CLOCK_TIME_2 | CCM_PLL2_CTRL_N(clk / 24000000),
&ccm->pll2_c1_cfg);
sdelay(2000);
/* Switch cluster 1 back to PLL2 */
clrsetbits_le32(&ccm->cpu_clk_source, C1_CPUX_CLK_SRC_MASK,
C1_CPUX_CLK_SRC_PLL2);
}
void clock_set_pll6(unsigned int clk)
{
struct sunxi_ccm_reg * const ccm =
@@ -143,32 +166,6 @@ void clock_set_pll6(unsigned int clk)
sdelay(2000);
}
void clock_set_pll12(unsigned int clk)
{
struct sunxi_ccm_reg * const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
if (readl(&ccm->pll12_periph1_cfg) & CCM_PLL12_CTRL_EN)
return;
writel(CCM_PLL12_CTRL_EN | CCM_PLL12_CTRL_N(clk / 24000000),
&ccm->pll12_periph1_cfg);
sdelay(2000);
}
void clock_set_pll4(unsigned int clk)
{
struct sunxi_ccm_reg * const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
writel(CCM_PLL4_CTRL_EN | CCM_PLL4_CTRL_N(clk / 24000000),
&ccm->pll4_periph0_cfg);
sdelay(2000);
}
#endif
int clock_twi_onoff(int port, int state)
{
@@ -193,7 +190,9 @@ int clock_twi_onoff(int port, int state)
return 0;
}
#endif /* CONFIG_SPL_BUILD */
/* PLL_PERIPH0 clock (used by the MMC driver) */
unsigned int clock_get_pll4_periph0(void)
{
struct sunxi_ccm_reg *const ccm =

78
arch/arm/mach-sunxi/spl_spi_sunxi.c
View File

@@ -72,18 +72,27 @@
#define SUN6I_CTL_ENABLE BIT(0)
#define SUN6I_CTL_MASTER BIT(1)
#define SUN6I_CTL_SRST BIT(31)
#define SUN6I_TCR_SDM BIT(13)
#define SUN6I_TCR_XCH BIT(31)
/*****************************************************************************/
#define CCM_AHB_GATING0 (0x01C20000 + 0x60)
#define CCM_H6_SPI_BGR_REG (0x03001000 + 0x96c)
#ifdef CONFIG_SUN50I_GEN_H6
#define CCM_SPI0_CLK (0x03001000 + 0x940)
#if IS_ENABLED(CONFIG_SUN50I_GEN_H6)
#define CCM_BASE 0x03001000
#elif IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)
#define CCM_BASE 0x02001000
#else
#define CCM_SPI0_CLK (0x01C20000 + 0xA0)
#define CCM_BASE 0x01C20000
#endif
#define SUN6I_BUS_SOFT_RST_REG0 (0x01C20000 + 0x2C0)
#define CCM_AHB_GATING0 (CCM_BASE + 0x60)
#define CCM_H6_SPI_BGR_REG (CCM_BASE + 0x96c)
#if IS_ENABLED(CONFIG_SUN50I_GEN_H6) || IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)
#define CCM_SPI0_CLK (CCM_BASE + 0x940)
#else
#define CCM_SPI0_CLK (CCM_BASE + 0xA0)
#endif
#define SUN6I_BUS_SOFT_RST_REG0 (CCM_BASE + 0x2C0)
#define AHB_RESET_SPI0_SHIFT 20
#define AHB_GATE_OFFSET_SPI0 20
@@ -101,17 +110,22 @@
*/
static void spi0_pinmux_setup(unsigned int pin_function)
{
/* All chips use PC0 and PC2. */
sunxi_gpio_set_cfgpin(SUNXI_GPC(0), pin_function);
/* All chips use PC2. And all chips use PC0, except R528/T113 */
if (!IS_ENABLED(CONFIG_MACH_SUN8I_R528))
sunxi_gpio_set_cfgpin(SUNXI_GPC(0), pin_function);
sunxi_gpio_set_cfgpin(SUNXI_GPC(2), pin_function);
/* All chips except H6 and H616 use PC1. */
if (!IS_ENABLED(CONFIG_SUN50I_GEN_H6))
/* All chips except H6/H616/R528/T113 use PC1. */
if (!IS_ENABLED(CONFIG_SUN50I_GEN_H6) &&
!IS_ENABLED(CONFIG_MACH_SUN8I_R528))
sunxi_gpio_set_cfgpin(SUNXI_GPC(1), pin_function);
if (IS_ENABLED(CONFIG_MACH_SUN50I_H6))
if (IS_ENABLED(CONFIG_MACH_SUN50I_H6) ||
IS_ENABLED(CONFIG_MACH_SUN8I_R528))
sunxi_gpio_set_cfgpin(SUNXI_GPC(5), pin_function);
if (IS_ENABLED(CONFIG_MACH_SUN50I_H616))
if (IS_ENABLED(CONFIG_MACH_SUN50I_H616) ||
IS_ENABLED(CONFIG_MACH_SUN8I_R528))
sunxi_gpio_set_cfgpin(SUNXI_GPC(4), pin_function);
/* Older generations use PC23 for CS, newer ones use PC3. */
@@ -125,7 +139,8 @@ static void spi0_pinmux_setup(unsigned int pin_function)
static bool is_sun6i_gen_spi(void)
{
return IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I) ||
IS_ENABLED(CONFIG_SUN50I_GEN_H6);
IS_ENABLED(CONFIG_SUN50I_GEN_H6) ||
IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2);
}
static uintptr_t spi0_base_address(void)
@@ -136,6 +151,9 @@ static uintptr_t spi0_base_address(void)
if (IS_ENABLED(CONFIG_SUN50I_GEN_H6))
return 0x05010000;
if (IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2))
return 0x04025000;
if (!is_sun6i_gen_spi() ||
IS_ENABLED(CONFIG_MACH_SUNIV))
return 0x01C05000;
@@ -151,23 +169,30 @@ static void spi0_enable_clock(void)
uintptr_t base = spi0_base_address();
/* Deassert SPI0 reset on SUN6I */
if (IS_ENABLED(CONFIG_SUN50I_GEN_H6))
if (IS_ENABLED(CONFIG_SUN50I_GEN_H6) ||
IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2))
setbits_le32(CCM_H6_SPI_BGR_REG, (1U << 16) | 0x1);
else if (is_sun6i_gen_spi())
setbits_le32(SUN6I_BUS_SOFT_RST_REG0,
(1 << AHB_RESET_SPI0_SHIFT));
/* Open the SPI0 gate */
if (!IS_ENABLED(CONFIG_SUN50I_GEN_H6))
if (!IS_ENABLED(CONFIG_SUN50I_GEN_H6) &&
!IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2))
setbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0));
if (IS_ENABLED(CONFIG_MACH_SUNIV)) {
/* Divide by 32, clock source is AHB clock 200MHz */
writel(SPI0_CLK_DIV_BY_32, base + SUN6I_SPI0_CCTL);
} else {
/* Divide by 4 */
writel(SPI0_CLK_DIV_BY_4, base + (is_sun6i_gen_spi() ?
SUN6I_SPI0_CCTL : SUN4I_SPI0_CCTL));
/* New SoCs do not have a clock divider inside */
if (!IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) {
/* Divide by 4 */
writel(SPI0_CLK_DIV_BY_4,
base + (is_sun6i_gen_spi() ? SUN6I_SPI0_CCTL :
SUN4I_SPI0_CCTL));
}
/* 24MHz from OSC24M */
writel((1 << 31), CCM_SPI0_CLK);
}
@@ -179,6 +204,14 @@ static void spi0_enable_clock(void)
/* Wait for completion */
while (readl(base + SUN6I_SPI0_GCR) & SUN6I_CTL_SRST)
;
/*
* For new SoCs we should configure sample mode depending on
* input clock. As 24MHz from OSC24M is used, we could use
* normal sample mode by setting SDM bit in the TCR register
*/
if (IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2))
setbits_le32(base + SUN6I_SPI0_TCR, SUN6I_TCR_SDM);
} else {
/* Enable SPI in the master mode and reset FIFO */
setbits_le32(base + SUN4I_SPI0_CTL, SUN4I_CTL_MASTER |
@@ -205,11 +238,13 @@ static void spi0_disable_clock(void)
writel(0, CCM_SPI0_CLK);
/* Close the SPI0 gate */
if (!IS_ENABLED(CONFIG_SUN50I_GEN_H6))
if (!IS_ENABLED(CONFIG_SUN50I_GEN_H6) &&
!IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2))
clrbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0));
/* Assert SPI0 reset on SUN6I */
if (IS_ENABLED(CONFIG_SUN50I_GEN_H6))
if (IS_ENABLED(CONFIG_SUN50I_GEN_H6) ||
IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2))
clrbits_le32(CCM_H6_SPI_BGR_REG, (1U << 16) | 0x1);
else if (is_sun6i_gen_spi())
clrbits_le32(SUN6I_BUS_SOFT_RST_REG0,
@@ -223,7 +258,8 @@ static void spi0_init(void)
if (IS_ENABLED(CONFIG_MACH_SUN50I) ||
IS_ENABLED(CONFIG_SUN50I_GEN_H6))
pin_function = SUN50I_GPC_SPI0;
else if (IS_ENABLED(CONFIG_MACH_SUNIV))
else if (IS_ENABLED(CONFIG_MACH_SUNIV) ||
IS_ENABLED(CONFIG_MACH_SUN8I_R528))
pin_function = SUNIV_GPC_SPI0;
spi0_pinmux_setup(pin_function);

9
board/sunxi/board.c
View File

@@ -186,7 +186,7 @@ enum env_location env_get_location(enum env_operation op, int prio)
return ENVL_UNKNOWN;
}
/* add board specific code here */
/* called only from U-Boot proper */
int board_init(void)
{
__maybe_unused int id_pfr1, ret;
@@ -226,13 +226,6 @@ int board_init(void)
if (ret)
return ret;
#if CONFIG_IS_ENABLED(DM_I2C)
/*
* Temporary workaround for enabling I2C clocks until proper sunxi DM
* clk, reset and pinctrl drivers land.
*/
i2c_init_board();
#endif
eth_init_board();
return 0;

16
drivers/usb/musb-new/sunxi.c
View File

@@ -506,6 +506,16 @@ static int musb_usb_remove(struct udevice *dev)
return 0;
}
/*
* The Linux driver has a config struct, its fields mapping to this driver
* like this:
* .hdrc_config:
* sunxi_musb_hdrc_config_5eps => musb_config
* sunxi_musb_hdrc_config_4eps => musb_config_h3
* .has_sram: always enabled, ideally no-op on SoCs not using it
* .has_reset: automatically detected from DT
* .no_configdata: handled via Kconfig's CONFIG_USB_MUSB_FIXED_CONFIGDATA
*/
static const struct sunxi_musb_config sun4i_a10_cfg = {
.config = &musb_config,
};
@@ -518,6 +528,10 @@ static const struct sunxi_musb_config sun8i_h3_cfg = {
.config = &musb_config_h3,
};
static const struct sunxi_musb_config suniv_f1c100s_cfg = {
.config = &musb_config,
};
static const struct udevice_id sunxi_musb_ids[] = {
{ .compatible = "allwinner,sun4i-a10-musb",
.data = (ulong)&sun4i_a10_cfg },
@@ -527,6 +541,8 @@ static const struct udevice_id sunxi_musb_ids[] = {
.data = (ulong)&sun6i_a31_cfg },
{ .compatible = "allwinner,sun8i-h3-musb",
.data = (ulong)&sun8i_h3_cfg },
{ .compatible = "allwinner,suniv-f1c100s-musb",
.data = (ulong)&suniv_f1c100s_cfg },
{ }
};