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doc: thead: lpi4a: Update for S-Mode proper U-Boot support
Proper U-Boot for Lichee Pi 4A now runs in S mode instead of M mode, which means the extra firmware, OpenSBI, must be built and integrated in the image, and the vendor U-Boot cannot chainload the result image anymore as it runs in M mode. Remove redundant information about chainloading and update build steps to mention OpenSBI firmware. Signed-off-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
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Yao Zi
@@ -55,123 +55,70 @@ DDR driver requires a firmware to function, to build it:
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cd th1520-firmware
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lua5.4 ddr-generate.lua src/<CONFIGURATION_NAME>.lua th1520-ddr-firmware.bin
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4. Build U-Boot images
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4. Build OpenSBI Firmware
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The U-Boot is capable of running in M-Mode, so we can directly build it without
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OpenSBI. The DDR firmware should be copied to U-Boot source directory before
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TH1520 port of proper U-Boot runs in S mode, thus OpenSBI is required as
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SBI firmware to setup S-mode environment and provide SBI calls. It could
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be cloned and built for TH1520 as below,
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.. code-block:: bash
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git clone https://github.com/riscv-software-src/opensbi.git
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cd opensbi
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make PLATFORM=generic
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TH1520 support in OpenSBI requires v1.2 or a more recent version.
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More detailed description of steps required to build fw_dynamic firmware
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is beyond the scope of this document. Please refer to OpenSBI
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documenation.
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5. Build U-Boot images
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The DDR firmware should be copied to U-Boot source directory before
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building.
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.. code-block:: console
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.. code-block:: bash
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cd <U-Boot-dir>
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cp <path-to-ddr-firmware> th1520-ddr-firmware.bin
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make th1520_lpi4a_defconfig
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make
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make OPENSBI=<opensbi_dir>/build/platform/generic/firmware/fw_dynamic.bin
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This will generate u-boot-dtb.bin and u-boot-with-spl.bin. The former contains
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only proper U-Boot and is for chainloading; the later contains also SPL and
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DDR firmware and is ready for booting by BROM directly.
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This will generate u-boot-with-spl.bin, which contains SPL, DDR firmware,
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OpenSBI firmware and proper U-Boot.
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Booting
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~~~~~~~
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Currently, we rely on vendor u-boot to initialize the clock, pinctrl subsystem,
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and chain load the mainline u-boot image either via tftp or emmc storage,
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then bootup from it.
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u-boot-with-spl.bin should be loaded to SRAM through fastboot. Connect
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the board to computer with Type-C cable and run
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Sample boot log from Lichee PI 4A board via tftp
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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.. code-block:: bash
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fastboot flash ram u-boot-with-spl.bin
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fastboot reboot
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Sample boot log from Lichee PI 4A board via fastboot
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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.. code-block:: none
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brom_ver 8
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[APP][E] protocol_connect failed, exit.
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Starting download of 940681 bytes
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U-Boot SPL 2020.01-00016-g8c870a6be8 (May 20 2023 - 01:04:49 +0000)
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FM[1] lpddr4x dualrank freq=3733 64bit dbi_off=n sdram init
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ddr initialized, jump to uboot
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image has no header
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downloading of 940681 bytes finished
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U-Boot 2020.01-00016-g8c870a6be8 (May 20 2023 - 01:04:49 +0000)
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CPU: rv64imafdcvsu
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Model: T-HEAD c910 light
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DRAM: 8 GiB
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C910 CPU FREQ: 750MHz
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AHB2_CPUSYS_HCLK FREQ: 250MHz
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AHB3_CPUSYS_PCLK FREQ: 125MHz
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PERISYS_AHB_HCLK FREQ: 250MHz
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PERISYS_APB_PCLK FREQ: 62MHz
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GMAC PLL POSTDIV FREQ: 1000MHZ
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DPU0 PLL POSTDIV FREQ: 1188MHZ
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DPU1 PLL POSTDIV FREQ: 1188MHZ
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MMC: sdhci@ffe7080000: 0, sd@ffe7090000: 1
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Loading Environment from MMC... OK
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Error reading output register
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Warning: cannot get lcd-en GPIO
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LCD panel cannot be found : -121
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splash screen startup cost 16 ms
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In: serial
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Out: serial
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Err: serial
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Net:
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Warning: ethernet@ffe7070000 using MAC address from ROM
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eth0: ethernet@ffe7070000ethernet@ffe7070000:0 is connected to ethernet@ffe7070000. Reconnecting to ethernet@ffe7060000
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Warning: ethernet@ffe7060000 (eth1) using random MAC address - 42:25:d4:16:5f:fc
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, eth1: ethernet@ffe7060000
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Hit any key to stop autoboot: 2
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ethernet@ffe7060000 Waiting for PHY auto negotiation to complete.. done
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Speed: 1000, full duplex
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Using ethernet@ffe7070000 device
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TFTP from server 192.168.8.50; our IP address is 192.168.8.45
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Filename 'u-boot-dtb.bin'.
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Load address: 0x1c00000
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Loading: * #########################
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8 MiB/s
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done
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Bytes transferred = 376686 (5bf6e hex)
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## Starting application at 0x01C00000 ...
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U-Boot 2023.07-rc2-00004-g1befbe31c1 (May 23 2023 - 18:40:01 +0800)
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CPU: rv64imafdc
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Model: Sipeed Lichee Pi 4A
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DRAM: 8 GiB
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Core: 13 devices, 6 uclasses, devicetree: separate
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Loading Environment from <NULL>... OK
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In: serial@ffe7014000
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Out: serial@ffe7014000
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Err: serial@ffe7014000
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Model: Sipeed Lichee Pi 4A
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LPI4A=>
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SPL support is still in an early stage and not all of the functionalities are
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available when booting from mainline SPL. When using mainline SPL,
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u-boot-with-spl.bin should be loaded to SRAM through fastboot.
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Sample boot log from Lichee PI 4A board via fastboot and mainline SPL
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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.. code-block:: none
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brom_ver 8
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[APP][E] protocol_connect failed, exit.
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Starting download of 636588 bytes
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downloading of 636588 bytes finished
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U-Boot SPL 2025.04-rc2-00049-geaa9fc99d4cd-dirty (Apr 26 2025 - 13:31:41 +0000)
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U-Boot SPL 2025.07-rc3-00005-g3a0ef515b8bb (May 29 2025 - 10:42:46 +0000)
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Trying to boot from RAM
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U-Boot 2025.04-rc2-00049-geaa9fc99d4cd-dirty (Apr 26 2025 - 13:31:41 +0000)
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U-Boot 2025.07-rc3-00005-g3a0ef515b8bb (May 29 2025 - 10:42:46 +0000)
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CPU: thead,c910
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Model: Sipeed Lichee Pi 4A
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DRAM: 8 GiB
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Core: 30 devices, 9 uclasses, devicetree: separate
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Core: 110 devices, 9 uclasses, devicetree: separate
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MMC: mmc@ffe7080000: 0, mmc@ffe7090000: 1
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Loading Environment from <NULL>... OK
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In: serial@ffe7014000
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