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Tegra: T20: Remove unused 'SLOW' SoC ID and PLLX table entry

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Signed-off-by: Tom Warren <twarren@nvidia.com>
This commit is contained in:
Tom Warren
2013-01-18 13:36:26 -07:00
parent 36068ae75e
commit d83152d8e4
2 changed files with 0 additions and 8 deletions
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7
arch/arm/cpu/arm720t/tegra-common/cpu.c
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@@ -75,13 +75,6 @@ struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
{ 700, 6, 0, 8},
{ 700, 13, 0, 8},
},
/* TEGRA_SOC2_SLOW: 312 MHz */
{{ 312, 13, 0, 12}, /* OSC 13M */
{ 260, 16, 0, 8}, /* OSC 19.2M */
{ 312, 12, 0, 12}, /* OSC 12M */
{ 312, 26, 0, 12}, /* OSC 26M */
},
};
void adjust_pllp_out_freqs(void)

1
arch/arm/include/asm/arch-tegra/tegra.h
View File

@@ -85,7 +85,6 @@ enum {
TEGRA_SOC_T20,
TEGRA_SOC_T25,
TEGRA_SOC_T30,
TEGRA_SOC2_SLOW, /* T2x needs to run at slow clock initially */
TEGRA_SOC_CNT,
TEGRA_SOC_UNKNOWN = -1,