mirror of
https://source.denx.de/u-boot/u-boot.git
synced 2026-06-02 09:46:37 +03:00
Merge tag 'u-boot-rockchip-20260309' of https://source.denx.de/u-boot/custodians/u-boot-rockchip into next
CI: https://source.denx.de/u-boot/custodians/u-boot-rockchip/-/pipelines/29452 - New SoC support: RK3506, RK3582; - New Board support: RK3528 FriendlyElec NanoPi Zero2; - Other fixes
This commit is contained in:
Tom Rini
@@ -58,17 +58,6 @@ dtb-$(CONFIG_ROCKCHIP_RK3128) += \
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dtb-$(CONFIG_ROCKCHIP_RK322X) += \
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rk3229-evb.dtb
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dtb-$(CONFIG_ROCKCHIP_RK3288) += \
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rk3288-evb.dtb \
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rk3288-popmetal.dtb \
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rk3288-rock2-square.dtb \
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rk3288-rock-pi-n8.dtb \
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rk3288-veyron-jerry.dtb \
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rk3288-veyron-mickey.dtb \
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rk3288-veyron-minnie.dtb \
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rk3288-veyron-speedy.dtb \
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rk3288-vyasa.dtb
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dtb-$(CONFIG_ROCKCHIP_RK3368) += \
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rk3368-sheep.dtb \
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rk3368-geekbox.dtb \
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@@ -1,52 +0,0 @@
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/*
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* Smart battery dts fragment for devices that use cros-ec-sbs
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*
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* Copyright (c) 2015 Google, Inc
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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||||
* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
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*
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||||
* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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||||
* GNU General Public License for more details.
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||||
*
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||||
* Or, alternatively,
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||||
*
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* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
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*
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||||
* The above copyright notice and this permission notice shall be
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||||
* included in all copies or substantial portions of the Software.
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*
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||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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||||
* OTHER DEALINGS IN THE SOFTWARE.
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*/
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&i2c_tunnel {
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battery: sbs-battery@b {
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compatible = "sbs,sbs-battery";
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reg = <0xb>;
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sbs,i2c-retry-count = <2>;
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sbs,poll-retry-count = <1>;
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};
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};
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@@ -1,20 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* (C) Copyright 2016 Rockchip Electronics Co., Ltd
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*/
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/dts-v1/;
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#include "rk3288-evb.dtsi"
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/ {
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model = "Evb-RK3288";
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compatible = "evb-rk3288,evb-rk3288", "rockchip,rk3288";
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chosen {
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stdout-path = &uart2;
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};
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};
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&pwm1 {
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status = "okay";
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};
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@@ -1,476 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* (C) Copyright 2016 Rockchip Electronics Co., Ltd
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*/
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#include "rk3288.dtsi"
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/ {
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memory {
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reg = <0x0 0x0 0x0 0x80000000>;
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};
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ext_gmac: external-gmac-clock {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <125000000>;
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clock-output-names = "ext_gmac";
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};
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keys: gpio-keys {
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compatible = "gpio-keys";
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button@0 {
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gpio-key,wakeup = <1>;
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gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
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label = "GPIO Power";
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linux,code = <116>;
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pinctrl-names = "default";
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pinctrl-0 = <&pwr_key>;
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};
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};
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vcc_sys: vsys-regulator {
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compatible = "regulator-fixed";
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regulator-name = "vcc_sys";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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regulator-always-on;
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regulator-boot-on;
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};
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vcc_flash: flash-regulator {
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compatible = "regulator-fixed";
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regulator-name = "vcc_flash";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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vin-supply = <&vcc_io>;
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};
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vcc_5v: usb-regulator {
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compatible = "regulator-fixed";
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regulator-name = "vcc_5v";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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regulator-always-on;
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regulator-boot-on;
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vin-supply = <&vcc_sys>;
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};
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vcc_host_5v: usb-host-regulator {
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compatible = "regulator-fixed";
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enable-active-high;
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gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&host_vbus_drv>;
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regulator-name = "vcc_host_5v";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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regulator-always-on;
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vin-supply = <&vcc_5v>;
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};
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vcc_otg_5v: usb-otg-regulator {
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compatible = "regulator-fixed";
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enable-active-high;
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gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&otg_vbus_drv>;
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regulator-name = "vcc_otg_5v";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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regulator-always-on;
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vin-supply = <&vcc_5v>;
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};
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backlight: backlight {
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compatible = "pwm-backlight";
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power-supply = <&vcc_sys>;
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enable-gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>;
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brightness-levels = <
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0 1 2 3 4 5 6 7
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8 9 10 11 12 13 14 15
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16 17 18 19 20 21 22 23
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24 25 26 27 28 29 30 31
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32 33 34 35 36 37 38 39
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40 41 42 43 44 45 46 47
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48 49 50 51 52 53 54 55
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56 57 58 59 60 61 62 63
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64 65 66 67 68 69 70 71
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72 73 74 75 76 77 78 79
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80 81 82 83 84 85 86 87
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88 89 90 91 92 93 94 95
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96 97 98 99 100 101 102 103
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104 105 106 107 108 109 110 111
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112 113 114 115 116 117 118 119
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120 121 122 123 124 125 126 127
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128 129 130 131 132 133 134 135
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136 137 138 139 140 141 142 143
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144 145 146 147 148 149 150 151
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152 153 154 155 156 157 158 159
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160 161 162 163 164 165 166 167
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168 169 170 171 172 173 174 175
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176 177 178 179 180 181 182 183
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184 185 186 187 188 189 190 191
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192 193 194 195 196 197 198 199
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200 201 202 203 204 205 206 207
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208 209 210 211 212 213 214 215
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216 217 218 219 220 221 222 223
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224 225 226 227 228 229 230 231
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232 233 234 235 236 237 238 239
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240 241 242 243 244 245 246 247
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248 249 250 251 252 253 254 255>;
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default-brightness-level = <50>;
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pwms = <&pwm0 0 25000 0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pwm0_pin>;
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pwm-delay-us = <10000>;
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status = "disabled";
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};
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panel: panel {
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compatible = "simple-panel";
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power-supply = <&vcc_io>;
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backlight = <&backlight>;
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enable-gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>;
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status = "disabled";
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};
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};
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&cpu0 {
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cpu0-supply = <&vdd_cpu>;
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};
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&emmc {
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broken-cd;
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bus-width = <8>;
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cap-mmc-highspeed;
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disable-wp;
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non-removable;
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num-slots = <1>;
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pinctrl-names = "default";
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pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_pwr>, <&emmc_bus8>;
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status = "okay";
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};
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&gmac {
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phy-mode = "rgmii";
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clock_in_out = "input";
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snps,reset-gpio = <&gpio4 7 0>;
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snps,reset-active-low;
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snps,reset-delays-us = <0 10000 1000000>;
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assigned-clocks = <&cru SCLK_MAC>;
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assigned-clock-parents = <&ext_gmac>;
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pinctrl-names = "default";
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pinctrl-0 = <&rgmii_pins>;
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tx_delay = <0x30>;
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rx_delay = <0x10>;
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status = "okay";
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};
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&hdmi {
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ddc-i2c-bus = <&i2c5>;
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status = "okay";
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};
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&i2c0 {
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clock-frequency = <400000>;
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status = "okay";
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vdd_cpu: syr827@40 {
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compatible = "silergy,syr827";
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fcs,suspend-voltage-selector = <1>;
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reg = <0x40>;
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regulator-name = "vdd_cpu";
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regulator-min-microvolt = <850000>;
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regulator-max-microvolt = <1350000>;
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regulator-always-on;
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regulator-boot-on;
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vin-supply = <&vcc_sys>;
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};
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vdd_gpu: syr828@41 {
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compatible = "silergy,syr828";
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fcs,suspend-voltage-selector = <1>;
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reg = <0x41>;
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regulator-name = "vdd_gpu";
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regulator-min-microvolt = <850000>;
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regulator-max-microvolt = <1350000>;
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regulator-always-on;
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vin-supply = <&vcc_sys>;
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};
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hym8563: hym8563@51 {
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compatible = "haoyu,hym8563";
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reg = <0x51>;
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#clock-cells = <0>;
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clock-frequency = <32768>;
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clock-output-names = "xin32k";
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interrupt-parent = <&gpio7>;
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interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
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pinctrl-names = "default";
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pinctrl-0 = <&rtc_int>;
|
||||
};
|
||||
|
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act8846: act8846@5a {
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compatible = "active-semi,act8846";
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reg = <0x5a>;
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pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwr_hold>;
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||||
system-power-controller;
|
||||
|
||||
regulators {
|
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vcc_ddr: REG1 {
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regulator-name = "vcc_ddr";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vcc_io: REG2 {
|
||||
regulator-name = "vcc_io";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdd_log: REG3 {
|
||||
regulator-name = "vdd_log";
|
||||
regulator-min-microvolt = <1100000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vcc_20: REG4 {
|
||||
regulator-name = "vcc_20";
|
||||
regulator-min-microvolt = <2000000>;
|
||||
regulator-max-microvolt = <2000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vccio_sd: REG5 {
|
||||
regulator-name = "vccio_sd";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdd10_lcd: REG6 {
|
||||
regulator-name = "vdd10_lcd";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vcca_codec: REG7 {
|
||||
regulator-name = "vcca_codec";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
vcc_tp: REG8 {
|
||||
regulator-name = "vcca_33";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
vccio_pmu: REG9 {
|
||||
regulator-name = "vccio_pmu";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
vdd_10: REG10 {
|
||||
regulator-name = "vdd_10";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vcc_18: REG11 {
|
||||
regulator-name = "vcc_18";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vcc18_lcd: REG12 {
|
||||
regulator-name = "vcc18_lcd";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c5 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
pcfg_output_high: pcfg-output-high {
|
||||
output-high;
|
||||
};
|
||||
|
||||
pcfg_output_low: pcfg-output-low {
|
||||
output-low;
|
||||
};
|
||||
|
||||
act8846 {
|
||||
pwr_hold: pwr-hold {
|
||||
rockchip,pins = <0 9 RK_FUNC_GPIO &pcfg_output_high>;
|
||||
};
|
||||
};
|
||||
|
||||
hym8563 {
|
||||
rtc_int: rtc-int {
|
||||
rockchip,pins = <0 4 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
keys {
|
||||
pwr_key: pwr-key {
|
||||
rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
sdmmc {
|
||||
sdmmc_pwr: sdmmc-pwr {
|
||||
rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
usb_host {
|
||||
host_vbus_drv: host-vbus-drv {
|
||||
rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
usb_otg {
|
||||
otg_vbus_drv: otg-vbus-drv {
|
||||
rockchip,pins = <0 12 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pwm0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&saradc {
|
||||
vref-supply = <&vcc_18>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdio0 {
|
||||
broken-cd;
|
||||
bus-width = <4>;
|
||||
disable-wp;
|
||||
non-removable;
|
||||
num-slots = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdio0_bus4>, <&sdio0_cmd>, <&sdio0_clk>;
|
||||
vmmc-supply = <&vcc_18>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&sdmmc {
|
||||
bus-width = <4>;
|
||||
cap-mmc-highspeed;
|
||||
cap-sd-highspeed;
|
||||
card-detect-delay = <200>;
|
||||
disable-wp;
|
||||
num-slots = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>;
|
||||
vmmc-supply = <&vccio_sd>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi0_clk>, <&spi0_cs0>, <&spi0_tx>, <&spi0_rx>, <&spi0_cs1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0_xfer>, <&uart0_cts>, <&uart0_rts>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_otg {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopb {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopb_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopl {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopl_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mipi_dsi {
|
||||
status = "disabled";
|
||||
rockchip,panel = <&panel>;
|
||||
display-timings {
|
||||
timing0 {
|
||||
bits-per-pixel = <24>;
|
||||
clock-frequency = <160000000>;
|
||||
hfront-porch = <120>;
|
||||
hsync-len = <20>;
|
||||
hback-porch = <21>;
|
||||
hactive = <1200>;
|
||||
vfront-porch = <21>;
|
||||
vsync-len = <3>;
|
||||
vback-porch = <18>;
|
||||
vactive = <1920>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&wdt {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -1,20 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
||||
/*
|
||||
* (C) Copyright 2016 Rockchip Electronics Co., Ltd
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "rk3288-popmetal.dtsi"
|
||||
|
||||
/ {
|
||||
model = "PopMetal-RK3288";
|
||||
compatible = "chipspark,popmetal-rk3288", "rockchip,rk3288";
|
||||
|
||||
chosen {
|
||||
stdout-path = &uart2;
|
||||
};
|
||||
};
|
||||
|
||||
&pwm1 {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -1,547 +0,0 @@
|
||||
/*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include "rk3288.dtsi"
|
||||
|
||||
/ {
|
||||
memory{
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0 0x0 0x80000000>;
|
||||
};
|
||||
|
||||
ext_gmac: external-gmac-clock {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <125000000>;
|
||||
clock-output-names = "ext_gmac";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
autorepeat;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwrbtn>;
|
||||
|
||||
power {
|
||||
gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
|
||||
label = "GPIO Key Power";
|
||||
linux,code = <KEY_POWER>;
|
||||
linux,input-type = <1>;
|
||||
wakeup-source;
|
||||
debounce-interval = <100>;
|
||||
};
|
||||
};
|
||||
|
||||
ir: ir-receiver {
|
||||
compatible = "gpio-ir-receiver";
|
||||
gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ir_int>;
|
||||
};
|
||||
|
||||
vcc_flash: flash-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_flash";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
vin-supply = <&vcc_io>;
|
||||
};
|
||||
|
||||
vcc_sd: sdmmc-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
gpio = <&gpio7 11 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc_pwr>;
|
||||
regulator-name = "vcc_sd";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
startup-delay-us = <100000>;
|
||||
vin-supply = <&vcc_io>;
|
||||
};
|
||||
|
||||
vcc_sys: vsys-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_sys";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
/*
|
||||
* A PT5128 creates both dovdd_1v8 and vcc28_dvp, controlled
|
||||
* by the dvp_pwr pin.
|
||||
*/
|
||||
vcc18_dvp: vcc18-dvp-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc18-dvp";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
vin-supply = <&vcc28_dvp>;
|
||||
};
|
||||
|
||||
vcc28_dvp: vcc28-dvp-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 17 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&dvp_pwr>;
|
||||
regulator-name = "vcc28_dvp";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
regulator-always-on;
|
||||
vin-supply = <&vcc_io>;
|
||||
};
|
||||
|
||||
vcc5v0_host: usb-host-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&host_vbus_drv>;
|
||||
regulator-name = "vcc5v0_host";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu0-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&emmc {
|
||||
bus-width = <8>;
|
||||
cap-mmc-highspeed;
|
||||
disable-wp;
|
||||
non-removable;
|
||||
num-slots = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>;
|
||||
vmmc-supply = <&vcc_io>;
|
||||
vqmmc-supply = <&vcc_flash>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc {
|
||||
bus-width = <4>;
|
||||
cap-mmc-highspeed;
|
||||
cap-sd-highspeed;
|
||||
card-detect-delay = <200>;
|
||||
disable-wp;
|
||||
num-slots = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
|
||||
vmmc-supply = <&vcc_sd>;
|
||||
vqmmc-supply = <&vccio_sd>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gmac {
|
||||
phy-supply = <&vcc_lan>;
|
||||
phy-mode = "rgmii";
|
||||
clock_in_out = "input";
|
||||
snps,reset-gpio = <&gpio4 7 0>;
|
||||
snps,reset-active-low;
|
||||
snps,reset-delays-us = <0 10000 1000000>;
|
||||
assigned-clocks = <&cru SCLK_MAC>;
|
||||
assigned-clock-parents = <&ext_gmac>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&rgmii_pins>;
|
||||
tx_delay = <0x30>;
|
||||
rx_delay = <0x10>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
ddc-i2c-bus = <&i2c5>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
rk808: pmic@1b {
|
||||
compatible = "rockchip,rk808";
|
||||
reg = <0x1b>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_int &global_pwroff>;
|
||||
rockchip,system-power-controller;
|
||||
wakeup-source;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "xin32k", "rk808-clkout2";
|
||||
|
||||
vcc1-supply = <&vcc_sys>;
|
||||
vcc2-supply = <&vcc_sys>;
|
||||
vcc3-supply = <&vcc_sys>;
|
||||
vcc4-supply = <&vcc_sys>;
|
||||
vcc6-supply = <&vcc_sys>;
|
||||
vcc7-supply = <&vcc_sys>;
|
||||
vcc8-supply = <&vcc_18>;
|
||||
vcc9-supply = <&vcc_io>;
|
||||
vcc10-supply = <&vcc_io>;
|
||||
vcc11-supply = <&vcc_sys>;
|
||||
vcc12-supply = <&vcc_io>;
|
||||
vddio-supply = <&vcc_io>;
|
||||
|
||||
regulators {
|
||||
vdd_cpu: DCDC_REG1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-name = "vdd_arm";
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_gpu: DCDC_REG2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <1250000>;
|
||||
regulator-name = "vdd_gpu";
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1000000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_ddr: DCDC_REG3 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vcc_ddr";
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_io: DCDC_REG4 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcc_io";
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_lan: LDO_REG1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcc_lan";
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_sd: LDO_REG2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vccio_sd";
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_10: LDO_REG3 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-name = "vdd_10";
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1000000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc18_lcd: LDO_REG4 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcc18_lcd";
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
ldo5: LDO_REG5 {
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "ldo5";
|
||||
};
|
||||
|
||||
vdd10_lcd: LDO_REG6 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-name = "vdd10_lcd";
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1000000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_18: LDO_REG7 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcc_18";
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca_33: LDO_REG8 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcca_33";
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_wl: SWITCH_REG1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vccio_wl";
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_lcd: SWITCH_REG2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vcc_lcd";
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
ak8963: ak8963@0d {
|
||||
compatible = "asahi-kasei,ak8975";
|
||||
reg = <0x0d>;
|
||||
interrupt-parent = <&gpio8>;
|
||||
interrupts = <1 IRQ_TYPE_EDGE_RISING>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&comp_int>;
|
||||
};
|
||||
|
||||
l3g4200d: l3g4200d@68 {
|
||||
compatible = "st,l3g4200d-gyro";
|
||||
st,drdy-int-pin = <2>;
|
||||
reg = <0x6b>;
|
||||
};
|
||||
|
||||
mma8452: mma8452@1d {
|
||||
compatible = "fsl,mma8452";
|
||||
reg = <0x1d>;
|
||||
interrupt-parent = <&gpio8>;
|
||||
interrupts = <0 IRQ_TYPE_EDGE_RISING>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gsensor_int>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c5 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&io_domains {
|
||||
audio-supply = <&vcca_33>;
|
||||
bb-supply = <&vcc_io>;
|
||||
dvp-supply = <&vcc18_dvp>;
|
||||
flash0-supply = <&vcc_flash>;
|
||||
flash1-supply = <&vcc_lan>;
|
||||
gpio30-supply = <&vcc_io>;
|
||||
gpio1830-supply = <&vcc_io>;
|
||||
lcdc-supply = <&vcc_io>;
|
||||
sdcard-supply = <&vccio_sd>;
|
||||
wifi-supply = <&vccio_wl>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
ak8963 {
|
||||
comp_int: comp-int {
|
||||
rockchip,pins = <8 1 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
buttons {
|
||||
pwrbtn: pwrbtn {
|
||||
rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
dvp {
|
||||
dvp_pwr: dvp-pwr {
|
||||
rockchip,pins = <0 17 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
ir {
|
||||
ir_int: ir-int {
|
||||
rockchip,pins = <0 6 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
mma8452 {
|
||||
gsensor_int: gsensor-int {
|
||||
rockchip,pins = <8 0 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
pmic {
|
||||
pmic_int: pmic-int {
|
||||
rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
sdmmc {
|
||||
sdmmc_pwr: sdmmc-pwr {
|
||||
rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
usb_host {
|
||||
host_vbus_drv: host-vbus-drv {
|
||||
rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&saradc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tsadc {
|
||||
rockchip,hw-tshut-mode = <0>;
|
||||
rockchip,hw-tshut-polarity = <0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopb {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopb_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopl {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopl_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1 {
|
||||
vbus-supply = <&vcc5v0_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbphy {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -1,17 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
|
||||
* Copyright (c) 2019 Vamrs Limited
|
||||
* Copyright (c) 2019 Amarula Solutions(India)
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "rk3288.dtsi"
|
||||
#include <rockchip-radxa-dalang-carrier.dtsi>
|
||||
#include "rk3288-vmarc-som.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Radxa ROCK Pi N8";
|
||||
compatible = "radxa,rockpi-n8", "vamrs,rk3288-vmarc-som",
|
||||
"rockchip,rk3288";
|
||||
};
|
||||
@@ -1,278 +0,0 @@
|
||||
/*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/pwm/pwm.h>
|
||||
#include "rk3288.dtsi"
|
||||
|
||||
/ {
|
||||
memory {
|
||||
reg = <0x0 0x0 0x0 0x80000000>;
|
||||
device_type = "memory";
|
||||
};
|
||||
|
||||
emmc_pwrseq: emmc-pwrseq {
|
||||
compatible = "mmc-pwrseq-emmc";
|
||||
pinctrl-0 = <&emmc_reset>;
|
||||
pinctrl-names = "default";
|
||||
reset-gpios = <&gpio3 9 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
ext_gmac: external-gmac-clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <125000000>;
|
||||
clock-output-names = "ext_gmac";
|
||||
};
|
||||
|
||||
vcc_sys: vsys-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_sys";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu0-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&emmc {
|
||||
bus-width = <8>;
|
||||
cap-mmc-highspeed;
|
||||
disable-wp;
|
||||
non-removable;
|
||||
num-slots = <1>;
|
||||
mmc-pwrseq = <&emmc_pwrseq>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
|
||||
vmmc-supply = <&vcc_io>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gmac {
|
||||
assigned-clocks = <&cru SCLK_MAC>;
|
||||
assigned-clock-parents = <&ext_gmac>;
|
||||
clock_in_out = "input";
|
||||
phy-mode = "rgmii";
|
||||
phy-supply = <&vccio_pmu>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&rgmii_pins &phy_rst>;
|
||||
snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
snps,reset-delays-us = <0 10000 30000>;
|
||||
rx_delay = <0x10>;
|
||||
tx_delay = <0x30>;
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
|
||||
act8846: act8846@5a {
|
||||
compatible = "active-semi,act8846";
|
||||
reg = <0x5a>;
|
||||
system-power-controller;
|
||||
inl1-supply = <&vcc_io>;
|
||||
inl2-supply = <&vcc_sys>;
|
||||
inl3-supply = <&vcc_20>;
|
||||
vp1-supply = <&vcc_sys>;
|
||||
vp2-supply = <&vcc_sys>;
|
||||
vp3-supply = <&vcc_sys>;
|
||||
vp4-supply = <&vcc_sys>;
|
||||
|
||||
regulators {
|
||||
vcc_ddr: REG1 {
|
||||
regulator-name = "VCC_DDR";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vcc_io: REG2 {
|
||||
regulator-name = "VCC_IO";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdd_log: REG3 {
|
||||
regulator-name = "VDD_LOG";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vcc_20: REG4 {
|
||||
regulator-name = "VCC_20";
|
||||
regulator-min-microvolt = <2000000>;
|
||||
regulator-max-microvolt = <2000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vccio_sd: REG5 {
|
||||
regulator-name = "VCCIO_SD";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdd10_lcd: REG6 {
|
||||
regulator-name = "VDD10_LCD";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vcca_codec: REG7 {
|
||||
regulator-name = "VCCA_CODEC";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vcca_tp: REG8 {
|
||||
regulator-name = "VCCA_TP";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vccio_pmu: REG9 {
|
||||
regulator-name = "VCCIO_PMU";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdd_10: REG10 {
|
||||
regulator-name = "VDD_10";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vcc_18: REG11 {
|
||||
regulator-name = "VCC_18";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vcc18_lcd: REG12 {
|
||||
regulator-name = "VCC18_LCD";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
vdd_cpu: syr827@40 {
|
||||
compatible = "silergy,syr827";
|
||||
reg = <0x40>;
|
||||
fcs,suspend-voltage-selector = <1>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-enable-ramp-delay = <300>;
|
||||
regulator-name = "vdd_cpu";
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <8000>;
|
||||
vin-supply = <&vcc_sys>;
|
||||
};
|
||||
|
||||
vdd_gpu: syr828@41 {
|
||||
compatible = "silergy,syr828";
|
||||
reg = <0x41>;
|
||||
fcs,suspend-voltage-selector = <1>;
|
||||
regulator-always-on;
|
||||
regulator-enable-ramp-delay = <300>;
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-name = "vdd_gpu";
|
||||
regulator-ramp-delay = <8000>;
|
||||
vin-supply = <&vcc_sys>;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
pcfg_output_high: pcfg-output-high {
|
||||
output-high;
|
||||
};
|
||||
|
||||
emmc {
|
||||
emmc_reset: emmc-reset {
|
||||
rockchip,pins = <3 9 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
gmac {
|
||||
phy_rst: phy-rst {
|
||||
rockchip,pins = <4 8 RK_FUNC_GPIO &pcfg_output_high>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&tsadc {
|
||||
rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
|
||||
rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopb {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopb_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopl {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopl_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wdt {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -1,181 +0,0 @@
|
||||
/*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "rk3288-rock2-som.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Radxa Rock 2 Square";
|
||||
compatible = "radxa,rock2-square", "rockchip,rk3288";
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial2:115200n8";
|
||||
};
|
||||
|
||||
ir: ir-receiver {
|
||||
compatible = "gpio-ir-receiver";
|
||||
gpios = <&gpio8 1 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ir_int>;
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,name = "SPDIF";
|
||||
simple-audio-card,dai-link@1 { /* S/PDIF - S/PDIF */
|
||||
cpu { sound-dai = <&spdif>; };
|
||||
codec { sound-dai = <&spdif_out>; };
|
||||
};
|
||||
};
|
||||
|
||||
spdif_out: spdif-out {
|
||||
compatible = "linux,spdif-dit";
|
||||
#sound-dai-cells = <0>;
|
||||
};
|
||||
|
||||
vcc_usb_host: vcc-host-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&host_vbus_drv>;
|
||||
/* Always on as the rockchip usb phy doesn't have a vbus-supply
|
||||
* property
|
||||
*/
|
||||
regulator-always-on;
|
||||
regulator-name = "vcc_host";
|
||||
};
|
||||
|
||||
vcc_sd: sdmmc-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
gpio = <&gpio7 11 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc_pwr>;
|
||||
regulator-name = "vcc_sd";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vcc_io>;
|
||||
};
|
||||
};
|
||||
|
||||
&sdmmc {
|
||||
bus-width = <4>;
|
||||
cap-mmc-highspeed;
|
||||
cap-sd-highspeed;
|
||||
card-detect-delay = <200>;
|
||||
disable-wp; /* wp not hooked up */
|
||||
num-slots = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
|
||||
vmmc-supply = <&vcc_sd>;
|
||||
vqmmc-supply = <&vccio_sd>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gmac {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
ddc-i2c-bus = <&i2c5>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
hym8563@51 {
|
||||
compatible = "haoyu,hym8563";
|
||||
reg = <0x51>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
clock-output-names = "xin32k";
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_int>;
|
||||
|
||||
};
|
||||
};
|
||||
|
||||
&i2c5 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
ir {
|
||||
ir_int: ir-int {
|
||||
rockchip,pins = <8 1 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
pmic {
|
||||
pmic_int: pmic-int {
|
||||
rockchip,pins = <0 4 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
usb {
|
||||
host_vbus_drv: host-vbus-drv {
|
||||
rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
sdmmc {
|
||||
sdmmc_pwr: sdmmc-pwr {
|
||||
rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&spdif {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
reg-shift = <2>;
|
||||
};
|
||||
|
||||
&usbphy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -1,205 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Google Veyron (and derivatives) board device tree source
|
||||
*
|
||||
* Copyright 2014 Google, Inc
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/rockchip,rk808.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include "rk3288-veyron.dtsi"
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
i2c20 = &i2c_tunnel;
|
||||
video0 = &vopl;
|
||||
video1 = &vopb;
|
||||
};
|
||||
|
||||
gpio_keys: gpio-keys {
|
||||
pinctrl-0 = <&pwr_key_h &ap_lid_int_l>;
|
||||
lid {
|
||||
label = "Lid";
|
||||
gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <0>; /* SW_LID */
|
||||
linux,input-type = <5>; /* EV_SW */
|
||||
debounce-interval = <1>;
|
||||
gpio-key,wakeup;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-charger {
|
||||
compatible = "gpio-charger";
|
||||
gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ac_present_ap>;
|
||||
charger-type = "mains";
|
||||
};
|
||||
|
||||
/* A non-regulated voltage from power supply or battery */
|
||||
vccsys: vccsys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vccsys";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vcc33_sys: vcc33-sys {
|
||||
vin-supply = <&vccsys>;
|
||||
};
|
||||
|
||||
vcc_5v: vcc-5v {
|
||||
vin-supply = <&vccsys>;
|
||||
};
|
||||
|
||||
/* This turns on vbus for host1 (dwc2) */
|
||||
vcc5_host1: vcc5-host1-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 11 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&host1_pwr_en>;
|
||||
regulator-name = "vcc5_host1";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
/* This turns on vbus for otg for host mode (dwc2) */
|
||||
vcc5v_otg: vcc5v-otg-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usbotg_pwren_h>;
|
||||
regulator-name = "vcc5_host2";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
};
|
||||
|
||||
&rk808 {
|
||||
regulators {
|
||||
vcc33_ccd: LDO_REG8 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcc33_ccd";
|
||||
regulator-suspend-mem-disabled;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
status = "okay";
|
||||
spi-activate-delay = <100>;
|
||||
spi-max-frequency = <3000000>;
|
||||
spi-deactivate-delay = <200>;
|
||||
|
||||
cros_ec: ec@0 {
|
||||
compatible = "google,cros-ec-spi";
|
||||
spi-max-frequency = <3000000>;
|
||||
interrupt-parent = <&gpio7>;
|
||||
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
|
||||
ec-interrupt = <&gpio7 7 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ec_int>;
|
||||
reg = <0>;
|
||||
google,cros-ec-spi-pre-delay = <30>;
|
||||
|
||||
i2c_tunnel: i2c-tunnel {
|
||||
compatible = "google,cros-ec-i2c-tunnel";
|
||||
google,remote-bus = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
trackpad@15 {
|
||||
compatible = "elan,i2c_touchpad";
|
||||
interrupt-parent = <&gpio7>;
|
||||
interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&trackpad_int>;
|
||||
reg = <0x15>;
|
||||
vcc-supply = <&vcc33_io>;
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
pinctrl-0 = <
|
||||
/* Common for sleep and wake, but no owners */
|
||||
&ddr0_retention
|
||||
&ddrio_pwroff
|
||||
&global_pwroff
|
||||
|
||||
/* Wake only */
|
||||
&suspend_l_wake
|
||||
&bt_dev_wake_awake
|
||||
>;
|
||||
pinctrl-1 = <
|
||||
/* Common for sleep and wake, but no owners */
|
||||
&ddr0_retention
|
||||
&ddrio_pwroff
|
||||
&global_pwroff
|
||||
|
||||
/* Sleep only */
|
||||
&suspend_l_sleep
|
||||
&bt_dev_wake_sleep
|
||||
>;
|
||||
|
||||
buttons {
|
||||
ap_lid_int_l: ap-lid-int-l {
|
||||
rockchip,pins = <0 6 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
charger {
|
||||
ac_present_ap: ac-present-ap {
|
||||
rockchip,pins = <0 8 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
cros-ec {
|
||||
ec_int: ec-int {
|
||||
rockchip,pins = <7 7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
sdmmc {
|
||||
sdmmc_wp_gpio: sdmmc-wp-gpio {
|
||||
rockchip,pins = <7 10 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
suspend {
|
||||
suspend_l_wake: suspend-l-wake {
|
||||
rockchip,pins = <0 17 RK_FUNC_GPIO &pcfg_output_low>;
|
||||
};
|
||||
|
||||
suspend_l_sleep: suspend-l-sleep {
|
||||
rockchip,pins = <0 17 RK_FUNC_GPIO &pcfg_output_high>;
|
||||
};
|
||||
};
|
||||
|
||||
trackpad {
|
||||
trackpad_int: trackpad-int {
|
||||
rockchip,pins = <7 3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
usb-host {
|
||||
host1_pwr_en: host1-pwr-en {
|
||||
rockchip,pins = <0 11 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
usbotg_pwren_h: usbotg-pwren-h {
|
||||
rockchip,pins = <0 12 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
#include "cros-ec-keyboard.dtsi"
|
||||
@@ -1,208 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Google Veyron Jerry Rev 3+ board device tree source
|
||||
*
|
||||
* Copyright 2014 Google, Inc
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "rk3288-veyron-chromebook.dtsi"
|
||||
#include "cros-ec-sbs.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Google Jerry";
|
||||
compatible = "google,veyron-jerry-rev7", "google,veyron-jerry-rev6",
|
||||
"google,veyron-jerry-rev5", "google,veyron-jerry-rev4",
|
||||
"google,veyron-jerry-rev3", "google,veyron-jerry",
|
||||
"google,veyron", "rockchip,rk3288";
|
||||
|
||||
chosen {
|
||||
stdout-path = &uart2;
|
||||
};
|
||||
|
||||
panel_regulator: panel-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio7 14 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&lcd_enable_h>;
|
||||
regulator-name = "panel_regulator";
|
||||
vin-supply = <&vcc33_sys>;
|
||||
};
|
||||
|
||||
vcc18_lcd: vcc18-lcd {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&avdd_1v8_disp_en>;
|
||||
regulator-name = "vcc18_lcd";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
vin-supply = <&vcc18_wl>;
|
||||
};
|
||||
|
||||
backlight_regulator: backlight-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&bl_pwr_en>;
|
||||
regulator-name = "backlight_regulator";
|
||||
vin-supply = <&vcc33_sys>;
|
||||
startup-delay-us = <15000>;
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "rockchip,audio-max98090-jerry";
|
||||
|
||||
cpu {
|
||||
sound-dai = <&i2s 0>;
|
||||
};
|
||||
|
||||
codec {
|
||||
sound-dai = <&max98090 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gpio_keys {
|
||||
power {
|
||||
gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
&backlight {
|
||||
power-supply = <&backlight_regulator>;
|
||||
};
|
||||
|
||||
&panel {
|
||||
power-supply= <&panel_regulator>;
|
||||
};
|
||||
|
||||
&rk808 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>;
|
||||
dvs-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>,
|
||||
<&gpio7 15 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
regulators {
|
||||
mic_vcc: LDO_REG2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "mic_vcc";
|
||||
regulator-suspend-mem-disabled;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&sdmmc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio
|
||||
&sdmmc_bus4>;
|
||||
disable-wp;
|
||||
};
|
||||
|
||||
&vcc_5v {
|
||||
enable-active-high;
|
||||
gpio = <&gpio7 21 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&drv_5v>;
|
||||
};
|
||||
|
||||
&vcc50_hdmi {
|
||||
enable-active-high;
|
||||
gpio = <&gpio5 19 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc50_hdmi_en>;
|
||||
};
|
||||
|
||||
&edp {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&edp_hpd>;
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
backlight {
|
||||
bl_pwr_en: bl_pwr_en {
|
||||
rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
buck-5v {
|
||||
drv_5v: drv-5v {
|
||||
rockchip,pins = <7 21 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
emmc {
|
||||
/* Make sure eMMC is not in reset */
|
||||
emmc_deassert_reset: emmc-deassert-reset {
|
||||
rockchip,pins = <2 9 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
hdmi {
|
||||
vcc50_hdmi_en: vcc50-hdmi-en {
|
||||
rockchip,pins = <5 19 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
lcd {
|
||||
lcd_enable_h: lcd-en {
|
||||
rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
avdd_1v8_disp_en: avdd-1v8-disp-en {
|
||||
rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pmic {
|
||||
dvs_1: dvs-1 {
|
||||
rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
};
|
||||
|
||||
dvs_2: dvs-2 {
|
||||
rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
status = "okay";
|
||||
|
||||
/*
|
||||
* Trackpad pin control is shared between Elan and Synaptics devices
|
||||
* so we have to pull it up to the bus level.
|
||||
*/
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c4_xfer &trackpad_int>;
|
||||
|
||||
trackpad@15 {
|
||||
compatible = "elan,i2c_touchpad";
|
||||
interrupt-parent = <&gpio7>;
|
||||
interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
|
||||
/*
|
||||
* Remove the inherited pinctrl settings to avoid clashing
|
||||
* with bus-wide ones.
|
||||
*/
|
||||
/delete-property/pinctrl-names;
|
||||
/delete-property/pinctrl-0;
|
||||
reg = <0x15>;
|
||||
vcc-supply = <&vcc33_io>;
|
||||
wakeup-source;
|
||||
};
|
||||
|
||||
trackpad@2c {
|
||||
compatible = "hid-over-i2c";
|
||||
interrupt-parent = <&gpio7>;
|
||||
interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
|
||||
reg = <0x2c>;
|
||||
hid-descr-addr = <0x0020>;
|
||||
vcc-supply = <&vcc33_io>;
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
@@ -1,266 +0,0 @@
|
||||
/*
|
||||
* Google Veyron Mickey Rev 0 board device tree source
|
||||
*
|
||||
* Copyright 2015 Google, Inc
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "rk3288-veyron-chromebook.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Google Mickey";
|
||||
compatible = "google,veyron-mickey-rev8", "google,veyron-mickey-rev7",
|
||||
"google,veyron-mickey-rev6", "google,veyron-mickey-rev5",
|
||||
"google,veyron-mickey-rev4", "google,veyron-mickey-rev3",
|
||||
"google,veyron-mickey-rev2", "google,veyron-mickey-rev1",
|
||||
"google,veyron-mickey-rev0", "google,veyron-mickey",
|
||||
"google,veyron", "rockchip,rk3288";
|
||||
|
||||
vcc_5v: vcc-5v {
|
||||
vin-supply = <&vcc33_sys>;
|
||||
};
|
||||
|
||||
vcc33_io: vcc33_io {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc33_io";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
vin-supply = <&vcc33_sys>;
|
||||
};
|
||||
};
|
||||
|
||||
&cpu_thermal {
|
||||
/delete-node/ trips;
|
||||
/delete-node/ cooling-maps;
|
||||
|
||||
trips {
|
||||
cpu_alert_almost_warm: cpu_alert_almost_warm {
|
||||
temperature = <63000>; /* millicelsius */
|
||||
hysteresis = <2000>; /* millicelsius */
|
||||
type = "passive";
|
||||
};
|
||||
cpu_alert_warm: cpu_alert_warm {
|
||||
temperature = <65000>; /* millicelsius */
|
||||
hysteresis = <2000>; /* millicelsius */
|
||||
type = "passive";
|
||||
};
|
||||
cpu_alert_almost_hot: cpu_alert_almost_hot {
|
||||
temperature = <80000>; /* millicelsius */
|
||||
hysteresis = <2000>; /* millicelsius */
|
||||
type = "passive";
|
||||
};
|
||||
cpu_alert_hot: cpu_alert_hot {
|
||||
temperature = <82000>; /* millicelsius */
|
||||
hysteresis = <2000>; /* millicelsius */
|
||||
type = "passive";
|
||||
};
|
||||
cpu_alert_hotter: cpu_alert_hotter {
|
||||
temperature = <84000>; /* millicelsius */
|
||||
hysteresis = <2000>; /* millicelsius */
|
||||
type = "passive";
|
||||
};
|
||||
cpu_alert_very_hot: cpu_alert_very_hot {
|
||||
temperature = <85000>; /* millicelsius */
|
||||
hysteresis = <2000>; /* millicelsius */
|
||||
type = "passive";
|
||||
};
|
||||
cpu_crit: cpu_crit {
|
||||
temperature = <90000>; /* millicelsius */
|
||||
hysteresis = <2000>; /* millicelsius */
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
/*
|
||||
* After 1st level, throttle the CPU down to as low as 1.4 GHz
|
||||
* and don't let the GPU go faster than 400 MHz. Note that we
|
||||
* won't throttle the GPU lower than 400 MHz due to CPU
|
||||
* heat--we'll let the GPU do the rest itself.
|
||||
*/
|
||||
cpu_warm_limit_cpu {
|
||||
trip = <&cpu_alert_warm>;
|
||||
cooling-device =
|
||||
<&cpu0 THERMAL_NO_LIMIT 4>;
|
||||
};
|
||||
|
||||
/*
|
||||
* Add some discrete steps to help throttling system deal
|
||||
* with the fact that there are two passive cooling devices:
|
||||
* the CPU and the GPU.
|
||||
*
|
||||
* - 1.2 GHz - 1.0 GHz (almost hot)
|
||||
* - 800 MHz (hot)
|
||||
* - 800 MHz - 696 MHz (hotter)
|
||||
* - 696 MHz - min (very hot)
|
||||
*
|
||||
* Note:
|
||||
* - 800 MHz appears to be a "sweet spot" for me. I can run
|
||||
* some pretty serious workload here and be happy.
|
||||
* - After 696 MHz we stop lowering voltage, so throttling
|
||||
* past there is less effective.
|
||||
*/
|
||||
cpu_almost_hot_limit_cpu {
|
||||
trip = <&cpu_alert_almost_hot>;
|
||||
cooling-device =
|
||||
<&cpu0 5 6>;
|
||||
};
|
||||
cpu_hot_limit_cpu {
|
||||
trip = <&cpu_alert_hot>;
|
||||
cooling-device =
|
||||
<&cpu0 7 7>;
|
||||
};
|
||||
cpu_hotter_limit_cpu {
|
||||
trip = <&cpu_alert_hotter>;
|
||||
cooling-device =
|
||||
<&cpu0 7 8>;
|
||||
};
|
||||
cpu_very_hot_limit_cpu {
|
||||
trip = <&cpu_alert_very_hot>;
|
||||
cooling-device =
|
||||
<&cpu0 8 THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&emmc {
|
||||
/delete-property/mmc-hs200-1_8v;
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&i2s {
|
||||
status = "okay";
|
||||
clock-names = "i2s_hclk", "i2s_clk", "i2s_clk_out";
|
||||
clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>, <&cru SCLK_I2S0_OUT>;
|
||||
};
|
||||
|
||||
&rk808 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>;
|
||||
dvs-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>,
|
||||
<&gpio7 15 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
/delete-property/ vcc6-supply;
|
||||
/delete-property/ vcc12-supply;
|
||||
|
||||
vcc11-supply = <&vcc33_sys>;
|
||||
|
||||
regulators {
|
||||
/* vcc33_io is sourced directly from vcc33_sys */
|
||||
/delete-node/ LDO_REG1;
|
||||
/delete-node/ LDO_REG7;
|
||||
|
||||
/* This is not a pwren anymore, but the real power supply */
|
||||
vdd10_lcd: LDO_REG7 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-name = "vdd10_lcd";
|
||||
regulator-suspend-mem-disabled;
|
||||
};
|
||||
|
||||
vcc18_lcd: LDO_REG8 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcc18_lcd";
|
||||
regulator-suspend-mem-disabled;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
hdmi {
|
||||
power_hdmi_on: power-hdmi-on {
|
||||
rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pmic {
|
||||
dvs_1: dvs-1 {
|
||||
rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
};
|
||||
|
||||
dvs_2: dvs-2 {
|
||||
rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&sdmmc {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&sdio0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&sdmmc {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&usb_host0_ehci {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&usb_host1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&vcc50_hdmi {
|
||||
enable-active-high;
|
||||
gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&power_hdmi_on>;
|
||||
};
|
||||
@@ -1,302 +0,0 @@
|
||||
/*
|
||||
* Google Veyron Minnie Rev 0+ board device tree source
|
||||
*
|
||||
* Copyright 2015 Google, Inc
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "rk3288-veyron-chromebook.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Google Minnie";
|
||||
compatible = "google,veyron-minnie-rev4", "google,veyron-minnie-rev3",
|
||||
"google,veyron-minnie-rev2", "google,veyron-minnie-rev1",
|
||||
"google,veyron-minnie-rev0", "google,veyron-minnie",
|
||||
"google,veyron", "rockchip,rk3288";
|
||||
|
||||
backlight_regulator: backlight-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&bl_pwr_en>;
|
||||
regulator-name = "backlight_regulator";
|
||||
vin-supply = <&vcc33_sys>;
|
||||
startup-delay-us = <15000>;
|
||||
};
|
||||
|
||||
panel_regulator: panel-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio7 14 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&lcd_enable_h>;
|
||||
regulator-name = "panel_regulator";
|
||||
startup-delay-us = <100000>;
|
||||
vin-supply = <&vcc33_sys>;
|
||||
};
|
||||
|
||||
vcc18_lcd: vcc18-lcd {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&avdd_1v8_disp_en>;
|
||||
regulator-name = "vcc18_lcd";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
vin-supply = <&vcc18_wl>;
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "rockchip,audio-max98090-jerry";
|
||||
|
||||
cpu {
|
||||
sound-dai = <&i2s 0>;
|
||||
};
|
||||
|
||||
codec {
|
||||
sound-dai = <&max98090 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&backlight {
|
||||
/* Minnie panel PWM must be >= 1%, so start non-zero brightness at 3 */
|
||||
brightness-levels = <
|
||||
0 3 4 5 6 7
|
||||
8 9 10 11 12 13 14 15
|
||||
16 17 18 19 20 21 22 23
|
||||
24 25 26 27 28 29 30 31
|
||||
32 33 34 35 36 37 38 39
|
||||
40 41 42 43 44 45 46 47
|
||||
48 49 50 51 52 53 54 55
|
||||
56 57 58 59 60 61 62 63
|
||||
64 65 66 67 68 69 70 71
|
||||
72 73 74 75 76 77 78 79
|
||||
80 81 82 83 84 85 86 87
|
||||
88 89 90 91 92 93 94 95
|
||||
96 97 98 99 100 101 102 103
|
||||
104 105 106 107 108 109 110 111
|
||||
112 113 114 115 116 117 118 119
|
||||
120 121 122 123 124 125 126 127
|
||||
128 129 130 131 132 133 134 135
|
||||
136 137 138 139 140 141 142 143
|
||||
144 145 146 147 148 149 150 151
|
||||
152 153 154 155 156 157 158 159
|
||||
160 161 162 163 164 165 166 167
|
||||
168 169 170 171 172 173 174 175
|
||||
176 177 178 179 180 181 182 183
|
||||
184 185 186 187 188 189 190 191
|
||||
192 193 194 195 196 197 198 199
|
||||
200 201 202 203 204 205 206 207
|
||||
208 209 210 211 212 213 214 215
|
||||
216 217 218 219 220 221 222 223
|
||||
224 225 226 227 228 229 230 231
|
||||
232 233 234 235 236 237 238 239
|
||||
240 241 242 243 244 245 246 247
|
||||
248 249 250 251 252 253 254 255>;
|
||||
power-supply = <&backlight_regulator>;
|
||||
};
|
||||
|
||||
&emmc {
|
||||
/delete-property/mmc-hs200-1_8v;
|
||||
};
|
||||
|
||||
&gpio_keys {
|
||||
pinctrl-0 = <&pwr_key_h &ap_lid_int_l &volum_down_l &volum_up_l>;
|
||||
|
||||
volum_down {
|
||||
label = "Volum_down";
|
||||
gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_VOLUMEDOWN>;
|
||||
debounce-interval = <100>;
|
||||
};
|
||||
|
||||
volum_up {
|
||||
label = "Volum_up";
|
||||
gpios = <&gpio5 10 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_VOLUMEUP>;
|
||||
debounce-interval = <100>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c_tunnel {
|
||||
battery: bq27500@55 {
|
||||
compatible = "ti,bq27500";
|
||||
reg = <0x55>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
status = "okay";
|
||||
|
||||
clock-frequency = <400000>;
|
||||
i2c-scl-falling-time-ns = <50>;
|
||||
i2c-scl-rising-time-ns = <300>;
|
||||
|
||||
touchscreen@10 {
|
||||
compatible = "elan,ekth3500";
|
||||
reg = <0x10>;
|
||||
interrupt-parent = <&gpio2>;
|
||||
interrupts = <14 IRQ_TYPE_EDGE_FALLING>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&touch_int &touch_rst>;
|
||||
reset-gpios = <&gpio2 15 GPIO_ACTIVE_LOW>;
|
||||
vcc33-supply = <&vcc33_touch>;
|
||||
vccio-supply = <&vcc33_touch>;
|
||||
};
|
||||
};
|
||||
|
||||
&panel {
|
||||
compatible = "auo,b101ean01", "simple-panel";
|
||||
power-supply= <&panel_regulator>;
|
||||
};
|
||||
|
||||
&rk808 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>;
|
||||
|
||||
regulators {
|
||||
vcc33_touch: LDO_REG2 {
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcc33_touch";
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc5v_touch: SWITCH_REG2 {
|
||||
regulator-name = "vcc5v_touch";
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&sdmmc {
|
||||
disable-wp;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio
|
||||
&sdmmc_bus4>;
|
||||
};
|
||||
|
||||
&vcc_5v {
|
||||
enable-active-high;
|
||||
gpio = <&gpio7 21 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&drv_5v>;
|
||||
};
|
||||
|
||||
&vcc50_hdmi {
|
||||
enable-active-high;
|
||||
gpio = <&gpio5 19 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc50_hdmi_en>;
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
backlight {
|
||||
bl_pwr_en: bl_pwr_en {
|
||||
rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
buck-5v {
|
||||
drv_5v: drv-5v {
|
||||
rockchip,pins = <7 21 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
buttons {
|
||||
volum_down_l: volum-down-l {
|
||||
rockchip,pins = <5 11 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
volum_up_l: volum-up-l {
|
||||
rockchip,pins = <5 10 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
hdmi {
|
||||
vcc50_hdmi_en: vcc50-hdmi-en {
|
||||
rockchip,pins = <5 19 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
lcd {
|
||||
lcd_enable_h: lcd-en {
|
||||
rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
avdd_1v8_disp_en: avdd-1v8-disp-en {
|
||||
rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pmic {
|
||||
dvs_1: dvs-1 {
|
||||
rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
};
|
||||
|
||||
dvs_2: dvs-2 {
|
||||
rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
};
|
||||
};
|
||||
|
||||
prochot {
|
||||
gpio_prochot: gpio-prochot {
|
||||
rockchip,pins = <2 8 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
touchscreen {
|
||||
touch_int: touch-int {
|
||||
rockchip,pins = <2 14 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
touch_rst: touch-rst {
|
||||
rockchip,pins = <2 15 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -1,143 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Google Veyron Speedy Rev 1+ board device tree source
|
||||
*
|
||||
* Copyright 2015 Google, Inc
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "rk3288-veyron-chromebook.dtsi"
|
||||
#include "cros-ec-sbs.dtsi"
|
||||
#include "rk3288-veyron-speedy-u-boot.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Google Speedy";
|
||||
compatible = "google,veyron-speedy-rev9", "google,veyron-speedy-rev8",
|
||||
"google,veyron-speedy-rev7", "google,veyron-speedy-rev6",
|
||||
"google,veyron-speedy-rev5", "google,veyron-speedy-rev4",
|
||||
"google,veyron-speedy-rev3", "google,veyron-speedy-rev2",
|
||||
"google,veyron-speedy", "google,veyron", "rockchip,rk3288";
|
||||
|
||||
panel_regulator: panel-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio7 RK_PB6 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&lcd_enable_h>;
|
||||
regulator-name = "panel_regulator";
|
||||
startup-delay-us = <100000>;
|
||||
vin-supply = <&vcc33_sys>;
|
||||
};
|
||||
|
||||
vcc18_lcd: vcc18-lcd {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&avdd_1v8_disp_en>;
|
||||
regulator-name = "vcc18_lcd";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
vin-supply = <&vcc18_wl>;
|
||||
};
|
||||
|
||||
backlight_regulator: backlight-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&bl_pwr_en>;
|
||||
regulator-name = "backlight_regulator";
|
||||
vin-supply = <&vcc33_sys>;
|
||||
startup-delay-us = <15000>;
|
||||
};
|
||||
};
|
||||
|
||||
&backlight {
|
||||
power-supply = <&backlight_regulator>;
|
||||
};
|
||||
|
||||
&cpu_alert0 {
|
||||
temperature = <65000>;
|
||||
};
|
||||
|
||||
&cpu_alert1 {
|
||||
temperature = <70000>;
|
||||
};
|
||||
|
||||
&edp {
|
||||
/delete-property/pinctrl-names;
|
||||
/delete-property/pinctrl-0;
|
||||
|
||||
force-hpd;
|
||||
};
|
||||
|
||||
&panel {
|
||||
power-supply = <&panel_regulator>;
|
||||
};
|
||||
|
||||
&rk808 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_int_l>;
|
||||
};
|
||||
|
||||
&sdmmc {
|
||||
disable-wp;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio
|
||||
&sdmmc_bus4>;
|
||||
};
|
||||
|
||||
&vcc_5v {
|
||||
enable-active-high;
|
||||
gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&drv_5v>;
|
||||
};
|
||||
|
||||
&vcc50_hdmi {
|
||||
enable-active-high;
|
||||
gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc50_hdmi_en>;
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
backlight {
|
||||
bl_pwr_en: bl_pwr_en {
|
||||
rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
buck-5v {
|
||||
drv_5v: drv-5v {
|
||||
rockchip,pins = <7 21 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
hdmi {
|
||||
vcc50_hdmi_en: vcc50-hdmi-en {
|
||||
rockchip,pins = <5 19 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
lcd {
|
||||
lcd_enable_h: lcd-en {
|
||||
rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
avdd_1v8_disp_en: avdd-1v8-disp-en {
|
||||
rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pmic {
|
||||
dvs_1: dvs-1 {
|
||||
rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
};
|
||||
|
||||
dvs_2: dvs-2 {
|
||||
rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -1,795 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Google Veyron (and derivatives) board device tree source
|
||||
*
|
||||
* Copyright 2014 Google, Inc
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/rockchip,rk808.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include "rk3288.dtsi"
|
||||
|
||||
/ {
|
||||
memory {
|
||||
reg = <0x0 0x0 0x0 0x80000000>;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = &uart2;
|
||||
};
|
||||
|
||||
firmware {
|
||||
chromeos {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&fw_wp_ap>;
|
||||
write-protect-gpio = <&gpio7 6 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
backlight: backlight {
|
||||
compatible = "pwm-backlight";
|
||||
brightness-levels = <
|
||||
0 1 2 3 4 5 6 7
|
||||
8 9 10 11 12 13 14 15
|
||||
16 17 18 19 20 21 22 23
|
||||
24 25 26 27 28 29 30 31
|
||||
32 33 34 35 36 37 38 39
|
||||
40 41 42 43 44 45 46 47
|
||||
48 49 50 51 52 53 54 55
|
||||
56 57 58 59 60 61 62 63
|
||||
64 65 66 67 68 69 70 71
|
||||
72 73 74 75 76 77 78 79
|
||||
80 81 82 83 84 85 86 87
|
||||
88 89 90 91 92 93 94 95
|
||||
96 97 98 99 100 101 102 103
|
||||
104 105 106 107 108 109 110 111
|
||||
112 113 114 115 116 117 118 119
|
||||
120 121 122 123 124 125 126 127
|
||||
128 129 130 131 132 133 134 135
|
||||
136 137 138 139 140 141 142 143
|
||||
144 145 146 147 148 149 150 151
|
||||
152 153 154 155 156 157 158 159
|
||||
160 161 162 163 164 165 166 167
|
||||
168 169 170 171 172 173 174 175
|
||||
176 177 178 179 180 181 182 183
|
||||
184 185 186 187 188 189 190 191
|
||||
192 193 194 195 196 197 198 199
|
||||
200 201 202 203 204 205 206 207
|
||||
208 209 210 211 212 213 214 215
|
||||
216 217 218 219 220 221 222 223
|
||||
224 225 226 227 228 229 230 231
|
||||
232 233 234 235 236 237 238 239
|
||||
240 241 242 243 244 245 246 247
|
||||
248 249 250 251 252 253 254 255>;
|
||||
default-brightness-level = <128>;
|
||||
enable-gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>;
|
||||
backlight-boot-off;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&bl_en>;
|
||||
pwms = <&pwm0 0 1000000 0>;
|
||||
};
|
||||
|
||||
panel: panel {
|
||||
compatible ="cnm,n116bgeea2","simple-panel";
|
||||
status = "okay";
|
||||
power-supply = <&vcc33_lcd>;
|
||||
backlight = <&backlight>;
|
||||
};
|
||||
|
||||
gpio_keys: gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwr_key_h>;
|
||||
power {
|
||||
label = "Power";
|
||||
gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>;
|
||||
linux,code = <KEY_POWER>;
|
||||
debounce-interval = <100>;
|
||||
gpio-key,wakeup;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-restart {
|
||||
compatible = "gpio-restart";
|
||||
gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ap_warm_reset_h>;
|
||||
priority = /bits/ 8 <200>;
|
||||
};
|
||||
|
||||
emmc_pwrseq: emmc-pwrseq {
|
||||
compatible = "mmc-pwrseq-emmc";
|
||||
pinctrl-0 = <&emmc_reset>;
|
||||
pinctrl-names = "default";
|
||||
reset-gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "rockchip,rockchip-audio-max98090";
|
||||
rockchip,model = "ROCKCHIP-I2S";
|
||||
rockchip,i2s-controller = <&i2s>;
|
||||
rockchip,audio-codec = <&max98090>;
|
||||
rockchip,hp-det-gpios = <&gpio6 5 GPIO_ACTIVE_HIGH>;
|
||||
rockchip,mic-det-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
|
||||
rockchip,headset-codec = <&headsetcodec>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mic_det>, <&hp_det>;
|
||||
};
|
||||
|
||||
vdd_logic: pwm-regulator {
|
||||
compatible = "pwm-regulator";
|
||||
pwms = <&pwm1 0 2000 0>;
|
||||
|
||||
voltage-table = <1350000 0>,
|
||||
<1300000 10>,
|
||||
<1250000 20>,
|
||||
<1200000 31>,
|
||||
<1150000 41>,
|
||||
<1100000 52>,
|
||||
<1050000 62>,
|
||||
<1000000 72>,
|
||||
< 950000 83>;
|
||||
|
||||
regulator-min-microvolt = <950000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-name = "vdd_logic";
|
||||
regulator-ramp-delay = <4000>;
|
||||
};
|
||||
|
||||
vcc33_sys: vcc33-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc33_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vccsys>;
|
||||
};
|
||||
|
||||
vcc_5v: vcc-5v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_5v";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
};
|
||||
|
||||
vcc50_hdmi: vcc50-hdmi {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc50_hdmi";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
vin-supply = <&vcc_5v>;
|
||||
};
|
||||
|
||||
bt_regulator: bt-regulator {
|
||||
/*
|
||||
* On the module itself this is one of these (depending
|
||||
* on the actual card pouplated):
|
||||
* - BT_I2S_WS_BT_RFDISABLE_L
|
||||
* - No connect
|
||||
*/
|
||||
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&bt_enable_l>;
|
||||
regulator-name = "bt_regulator";
|
||||
};
|
||||
|
||||
wifi_regulator: wifi-regulator {
|
||||
/*
|
||||
* On the module itself this is one of these (depending
|
||||
* on the actual card populated):
|
||||
* - SDIO_RESET_L_WL_REG_ON
|
||||
* - PDN (power down when low)
|
||||
*/
|
||||
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wifi_enable_h>;
|
||||
regulator-name = "wifi_regulator";
|
||||
|
||||
/* Faux input supply. See bt_regulator description. */
|
||||
vin-supply = <&bt_regulator>;
|
||||
};
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu0-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&efuse {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&emmc {
|
||||
broken-cd;
|
||||
bus-width = <8>;
|
||||
cap-mmc-highspeed;
|
||||
mmc-hs200-1_8v;
|
||||
mmc-pwrseq = <&emmc_pwrseq>;
|
||||
disable-wp;
|
||||
non-removable;
|
||||
num-slots = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8 &emmc_pwr>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdio0 {
|
||||
broken-cd;
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
sd-uhs-sdr12;
|
||||
sd-uhs-sdr25;
|
||||
sd-uhs-sdr50;
|
||||
sd-uhs-sdr104;
|
||||
cap-sdio-irq;
|
||||
card-external-vcc-supply = <&wifi_regulator>;
|
||||
clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, <&cru SCLK_SDIO0_DRV>,
|
||||
<&cru SCLK_SDIO0_SAMPLE>, <&rk808 RK808_CLKOUT1>;
|
||||
clock-names = "biu", "ciu", "ciu_drv", "ciu_sample", "card_ext_clock";
|
||||
keep-power-in-suspend;
|
||||
non-removable;
|
||||
num-slots = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_bus4>;
|
||||
status = "okay";
|
||||
vmmc-supply = <&vcc33_sys>;
|
||||
vqmmc-supply = <&vcc18_wl>;
|
||||
};
|
||||
|
||||
&sdmmc {
|
||||
bus-width = <4>;
|
||||
cap-mmc-highspeed;
|
||||
cap-sd-highspeed;
|
||||
sd-uhs-sdr12;
|
||||
sd-uhs-sdr25;
|
||||
sd-uhs-sdr50;
|
||||
sd-uhs-sdr104;
|
||||
card-detect-delay = <200>;
|
||||
cd-gpios = <&gpio7 5 GPIO_ACTIVE_LOW>;
|
||||
num-slots = <1>;
|
||||
status = "okay";
|
||||
vmmc-supply = <&vcc33_sd>;
|
||||
vqmmc-supply = <&vccio_sd>;
|
||||
};
|
||||
|
||||
&spi2 {
|
||||
status = "okay";
|
||||
|
||||
spi_flash: spiflash@0 {
|
||||
compatible = "spidev", "jedec,spi-nor";
|
||||
spi-max-frequency = <20000000>; /* Reduce for Dediprog em100 pro */
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
|
||||
clock-frequency = <400000>;
|
||||
i2c-scl-falling-time-ns = <50>; /* 2.5ns measured */
|
||||
i2c-scl-rising-time-ns = <100>; /* 45ns measured */
|
||||
|
||||
rk808: pmic@1b {
|
||||
compatible = "rockchip,rk808";
|
||||
clock-output-names = "xin32k", "wifibt_32kin";
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_int_l>;
|
||||
reg = <0x1b>;
|
||||
rockchip,system-power-controller;
|
||||
wakeup-source;
|
||||
#clock-cells = <1>;
|
||||
|
||||
vcc1-supply = <&vcc33_sys>;
|
||||
vcc2-supply = <&vcc33_sys>;
|
||||
vcc3-supply = <&vcc33_sys>;
|
||||
vcc4-supply = <&vcc33_sys>;
|
||||
vcc6-supply = <&vcc_5v>;
|
||||
vcc7-supply = <&vcc33_sys>;
|
||||
vcc8-supply = <&vcc33_sys>;
|
||||
vcc9-supply = <&vcc_5v>;
|
||||
vcc10-supply = <&vcc33_sys>;
|
||||
vcc11-supply = <&vcc_5v>;
|
||||
vcc12-supply = <&vcc_18>;
|
||||
|
||||
vddio-supply = <&vcc33_io>;
|
||||
|
||||
regulators {
|
||||
vdd_cpu: DCDC_REG1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <1450000>;
|
||||
regulator-name = "vdd_arm";
|
||||
regulator-ramp-delay = <6001>;
|
||||
regulator-suspend-mem-disabled;
|
||||
};
|
||||
|
||||
vdd_gpu: DCDC_REG2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1250000>;
|
||||
regulator-name = "vdd_gpu";
|
||||
regulator-ramp-delay = <6001>;
|
||||
regulator-suspend-mem-disabled;
|
||||
};
|
||||
|
||||
vcc135_ddr: DCDC_REG3 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vcc135_ddr";
|
||||
regulator-suspend-mem-enabled;
|
||||
};
|
||||
|
||||
/*
|
||||
* vcc_18 has several aliases. (vcc18_flashio and
|
||||
* vcc18_wl). We'll add those aliases here just to
|
||||
* make it easier to follow the schematic. The signals
|
||||
* are actually hooked together and only separated for
|
||||
* power measurement purposes).
|
||||
*/
|
||||
vcc18_wl: vcc18_flashio: vcc_18: DCDC_REG4 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcc_18";
|
||||
regulator-suspend-mem-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
/*
|
||||
* Note that both vcc33_io and vcc33_pmuio are always
|
||||
* powered together. To simplify the logic in the dts
|
||||
* we just refer to vcc33_io every time something is
|
||||
* powered from vcc33_pmuio. In fact, on later boards
|
||||
* (such as danger) they're the same net.
|
||||
*/
|
||||
vcc33_io: LDO_REG1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcc33_io";
|
||||
regulator-suspend-mem-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
vdd_10: LDO_REG3 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-name = "vdd_10";
|
||||
regulator-suspend-mem-microvolt = <1000000>;
|
||||
};
|
||||
|
||||
vccio_sd: LDO_REG4 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vccio_sd";
|
||||
regulator-suspend-mem-disabled;
|
||||
};
|
||||
|
||||
vcc33_sd: LDO_REG5 {
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcc33_sd";
|
||||
regulator-suspend-mem-disabled;
|
||||
};
|
||||
|
||||
vcc18_codec: LDO_REG6 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcc18_codec";
|
||||
regulator-suspend-mem-disabled;
|
||||
};
|
||||
|
||||
vdd10_lcd_pwren_h: LDO_REG7 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <2500000>;
|
||||
regulator-max-microvolt = <2500000>;
|
||||
regulator-name = "vdd10_lcd_pwren_h";
|
||||
regulator-suspend-mem-disabled;
|
||||
};
|
||||
|
||||
vcc33_lcd: SWITCH_REG1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vcc33_lcd";
|
||||
regulator-suspend-mem-disabled;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
|
||||
clock-frequency = <400000>;
|
||||
i2c-scl-falling-time-ns = <50>; /* 2.5ns measured */
|
||||
i2c-scl-rising-time-ns = <100>; /* 40ns measured */
|
||||
|
||||
tpm: tpm@20 {
|
||||
compatible = "infineon,slb9645tt";
|
||||
reg = <0x20>;
|
||||
powered-while-suspended;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
status = "okay";
|
||||
|
||||
/* 100kHz since 4.7k resistors don't rise fast enough */
|
||||
clock-frequency = <100000>;
|
||||
i2c-scl-falling-time-ns = <50>; /* 10ns measured */
|
||||
i2c-scl-rising-time-ns = <800>; /* 600ns measured */
|
||||
|
||||
max98090: max98090@10 {
|
||||
compatible = "maxim,max98090";
|
||||
reg = <0x10>;
|
||||
#sound-dai-cells = <0>;
|
||||
interrupt-parent = <&gpio6>;
|
||||
interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&int_codec>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
status = "okay";
|
||||
|
||||
clock-frequency = <400000>;
|
||||
i2c-scl-falling-time-ns = <50>;
|
||||
i2c-scl-rising-time-ns = <300>;
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
status = "okay";
|
||||
|
||||
clock-frequency = <400000>;
|
||||
i2c-scl-falling-time-ns = <50>; /* 11ns measured */
|
||||
i2c-scl-rising-time-ns = <300>; /* 225ns measured */
|
||||
|
||||
headsetcodec: ts3a227e@3b {
|
||||
compatible = "ti,ts3a227e";
|
||||
reg = <0x3b>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ts3a227e_int_l>;
|
||||
ti,micbias = <7>; /* MICBIAS = 2.8V */
|
||||
};
|
||||
};
|
||||
|
||||
&i2c5 {
|
||||
status = "okay";
|
||||
|
||||
clock-frequency = <100000>;
|
||||
i2c-scl-falling-time-ns = <300>;
|
||||
i2c-scl-rising-time-ns = <1000>;
|
||||
};
|
||||
|
||||
&i2s {
|
||||
status = "okay";
|
||||
clock-names = "i2s_hclk", "i2s_clk", "i2s_clk_out";
|
||||
clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>, <&cru SCLK_I2S0_OUT>;
|
||||
};
|
||||
|
||||
&io_domains {
|
||||
audio-supply = <&vcc18_codec>;
|
||||
bb-supply = <&vcc33_io>;
|
||||
dvp-supply = <&vcc_18>;
|
||||
flash0-supply = <&vcc18_flashio>;
|
||||
gpio1830-supply = <&vcc33_io>;
|
||||
gpio30-supply = <&vcc33_io>;
|
||||
lcdc-supply = <&vcc33_lcd>;
|
||||
sdcard-supply = <&vccio_sd>;
|
||||
wifi-supply = <&vcc18_wl>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wdt {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
|
||||
/* Pins don't include flow control by default; add that in */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
|
||||
/* We need to go faster than 24MHz, so adjust clock parents / rates */
|
||||
assigned-clocks = <&cru SCLK_UART0>;
|
||||
assigned-clock-rates = <48000000>;
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
reg-shift = <2>;
|
||||
};
|
||||
|
||||
&vopb {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopb_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopl {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopl_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&edp {
|
||||
status = "okay";
|
||||
rockchip,panel = <&panel>;
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tsadc {
|
||||
tsadc-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
|
||||
tsadc-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <
|
||||
/* Common for sleep and wake, but no owners */
|
||||
&ddr0_retention
|
||||
&ddrio_pwroff
|
||||
&global_pwroff
|
||||
|
||||
/* Wake only */
|
||||
&bt_dev_wake_awake
|
||||
>;
|
||||
pinctrl-1 = <
|
||||
/* Common for sleep and wake, but no owners */
|
||||
&ddr0_retention
|
||||
&ddrio_pwroff
|
||||
&global_pwroff
|
||||
|
||||
/* Sleep only */
|
||||
&bt_dev_wake_sleep
|
||||
>;
|
||||
|
||||
/* Add this for sdmmc pins to SD card */
|
||||
pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
|
||||
drive-strength = <8>;
|
||||
};
|
||||
|
||||
pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
|
||||
bias-pull-up;
|
||||
drive-strength = <8>;
|
||||
};
|
||||
|
||||
pcfg_output_high: pcfg-output-high {
|
||||
output-high;
|
||||
};
|
||||
|
||||
pcfg_output_low: pcfg-output-low {
|
||||
output-low;
|
||||
};
|
||||
|
||||
backlight {
|
||||
bl_en: bl-en {
|
||||
rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
buttons {
|
||||
pwr_key_h: pwr-key-h {
|
||||
rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
codec {
|
||||
hp_det: hp-det {
|
||||
rockchip,pins = <6 5 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
int_codec: int-codec {
|
||||
rockchip,pins = <6 7 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
mic_det: mic-det {
|
||||
rockchip,pins = <6 11 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
emmc {
|
||||
emmc_reset: emmc-reset {
|
||||
rockchip,pins = <2 9 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/*
|
||||
* We run eMMC at max speed; bump up drive strength.
|
||||
* We also have external pulls, so disable the internal ones.
|
||||
*/
|
||||
emmc_clk: emmc-clk {
|
||||
rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
|
||||
};
|
||||
|
||||
emmc_cmd: emmc-cmd {
|
||||
rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
|
||||
};
|
||||
|
||||
emmc_bus8: emmc-bus8 {
|
||||
rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
|
||||
<3 1 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
|
||||
<3 2 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
|
||||
<3 3 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
|
||||
<3 4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
|
||||
<3 5 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
|
||||
<3 6 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
|
||||
<3 7 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
|
||||
};
|
||||
};
|
||||
|
||||
headset {
|
||||
ts3a227e_int_l: ts3a227e-int-l {
|
||||
rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
pmic {
|
||||
pmic_int_l: pmic-int-l {
|
||||
/*
|
||||
* Causes jerry to hang when probing bus 0
|
||||
* rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
*/
|
||||
};
|
||||
};
|
||||
|
||||
reboot {
|
||||
ap_warm_reset_h: ap-warm-reset-h {
|
||||
rockchip,pins = <RK_GPIO0 13 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
sdio0 {
|
||||
wifi_enable_h: wifienable-h {
|
||||
rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/* NOTE: mislabelled on schematic; should be bt_enable_h */
|
||||
bt_enable_l: bt-enable-l {
|
||||
rockchip,pins = <4 29 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/*
|
||||
* We run sdio0 at max speed; bump up drive strength.
|
||||
* We also have external pulls, so disable the internal ones.
|
||||
*/
|
||||
sdio0_bus4: sdio0-bus4 {
|
||||
rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
|
||||
<4 21 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
|
||||
<4 22 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
|
||||
<4 23 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
|
||||
};
|
||||
|
||||
sdio0_cmd: sdio0-cmd {
|
||||
rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
|
||||
};
|
||||
|
||||
sdio0_clk: sdio0-clk {
|
||||
rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
|
||||
};
|
||||
|
||||
/*
|
||||
* These pins are only present on very new veyron boards; on
|
||||
* older boards bt_dev_wake is simply always high. Note that
|
||||
* gpio4_26 is a NC on old veyron boards, so it doesn't hurt
|
||||
* to map this pin everywhere
|
||||
*/
|
||||
bt_dev_wake_sleep: bt-dev-wake-sleep {
|
||||
rockchip,pins = <4 26 RK_FUNC_GPIO &pcfg_output_low>;
|
||||
};
|
||||
|
||||
bt_dev_wake_awake: bt-dev-wake-awake {
|
||||
rockchip,pins = <4 26 RK_FUNC_GPIO &pcfg_output_high>;
|
||||
};
|
||||
};
|
||||
|
||||
sdmmc {
|
||||
/*
|
||||
* We run sdmmc at max speed; bump up drive strength.
|
||||
* We also have external pulls, so disable the internal ones.
|
||||
*/
|
||||
sdmmc_bus4: sdmmc-bus4 {
|
||||
rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
|
||||
<6 17 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
|
||||
<6 18 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
|
||||
<6 19 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
|
||||
};
|
||||
|
||||
sdmmc_clk: sdmmc-clk {
|
||||
rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
|
||||
};
|
||||
|
||||
sdmmc_cmd: sdmmc-cmd {
|
||||
rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
|
||||
};
|
||||
|
||||
/*
|
||||
* Builtin CD line is hooked to ground to prevent JTAG at boot
|
||||
* (and also to get the voltage rail correct). Make we
|
||||
* configure gpio6_C6 as GPIO so dw_mmc builtin CD doesn't
|
||||
* think there's a card inserted
|
||||
*/
|
||||
sdmmc_cd_disabled: sdmmc-cd-disabled {
|
||||
rockchip,pins = <6 22 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/* This is where we actually hook up CD */
|
||||
sdmmc_cd_gpio: sdmmc-cd-gpio {
|
||||
rockchip,pins = <7 5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
tpm {
|
||||
tpm_int_h: tpm-int-h {
|
||||
rockchip,pins = <7 4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
write-protect {
|
||||
fw_wp_ap: fw-wp-ap {
|
||||
rockchip,pins = <7 6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&usbphy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ehci {
|
||||
status = "okay";
|
||||
needs-reset-on-resume;
|
||||
};
|
||||
|
||||
&usb_host1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_otg {
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
assigned-clocks = <&cru SCLK_USBPHY480M_SRC>;
|
||||
assigned-clock-parents = <&cru SCLK_OTGPHY0>;
|
||||
};
|
||||
@@ -1,361 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
|
||||
* Copyright (c) 2019 Vamrs Limited
|
||||
* Copyright (c) 2019 Amarula Solutions(India)
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/pinctrl/rockchip.h>
|
||||
|
||||
/ {
|
||||
compatible = "vamrs,rk3288-vmarc-som", "rockchip,rk3288";
|
||||
|
||||
vccio_flash: vccio-flash-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vccio_flash";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
vin-supply = <&vcc_io>;
|
||||
};
|
||||
};
|
||||
|
||||
&emmc {
|
||||
bus-width = <8>;
|
||||
cap-mmc-highspeed;
|
||||
disable-wp;
|
||||
non-removable;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>;
|
||||
vmmc-supply = <&vcc_io>;
|
||||
vqmmc-supply = <&vccio_flash>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gmac {
|
||||
assigned-clocks = <&cru SCLK_MAC>;
|
||||
phy-supply = <&vcc_io>;
|
||||
snps,reset-gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
ddc-i2c-bus = <&i2c5>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hdmi_cec_c0>;
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
|
||||
rk808: pmic@1b {
|
||||
compatible = "rockchip,rk808";
|
||||
reg = <0x1b>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <RK_PA4 IRQ_TYPE_LEVEL_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_int &global_pwroff>;
|
||||
rockchip,system-power-controller;
|
||||
wakeup-source;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "rk808-clkout1", "rk808-clkout2";
|
||||
|
||||
vcc1-supply = <&vcc5v0_sys>;
|
||||
vcc2-supply = <&vcc5v0_sys>;
|
||||
vcc3-supply = <&vcc5v0_sys>;
|
||||
vcc4-supply = <&vcc5v0_sys>;
|
||||
vcc6-supply = <&vcc5v0_sys>;
|
||||
vcc7-supply = <&vcc5v0_sys>;
|
||||
vcc8-supply = <&vcc_io>;
|
||||
vcc9-supply = <&vcc_io>;
|
||||
vcc10-supply = <&vcc5v0_sys>;
|
||||
vcc11-supply = <&vcc5v0_sys>;
|
||||
vcc12-supply = <&vcc_io>;
|
||||
vddio-supply = <&vcc_io>;
|
||||
|
||||
regulators {
|
||||
vdd_cpu: DCDC_REG1 {
|
||||
regulator-name = "vdd_arm";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <1400000>;
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_gpu: DCDC_REG2 {
|
||||
regulator-name = "vdd_gpu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <1250000>;
|
||||
regulator-ramp-delay = <6000>;
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_ddr: DCDC_REG3 {
|
||||
regulator-name = "vcc_ddr";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_io: DCDC_REG4 {
|
||||
regulator-name = "vcc_io";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_tp: LDO_REG1 {
|
||||
regulator-name = "vcc_tp";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcca_codec: LDO_REG2 {
|
||||
regulator-name = "vcca_codec";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_10: LDO_REG3 {
|
||||
regulator-name = "vdd_10";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1000000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_wl: LDO_REG4 {
|
||||
regulator-name = "vcc_wl";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_sd: LDO_REG5 {
|
||||
regulator-name = "vccio_sd";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vdd10_lcd: LDO_REG6 {
|
||||
regulator-name = "vdd10_lcd";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_18: LDO_REG7 {
|
||||
regulator-name = "vcc_18";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc18_lcd: LDO_REG8 {
|
||||
regulator-name = "vcc18_lcd";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_sd: SWITCH_REG1 {
|
||||
regulator-name = "vcc_sd";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_lcd: SWITCH_REG2 {
|
||||
regulator-name = "vcc_lcd";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
|
||||
hym8563: rtc@51 {
|
||||
compatible = "haoyu,hym8563";
|
||||
reg = <0x51>;
|
||||
interrupt-parent = <&gpio5>;
|
||||
interrupts = <RK_PC3 IRQ_TYPE_LEVEL_LOW>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "hym8563";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hym8563_int>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c5 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&io_domains {
|
||||
bb-supply = <&vcc_io>;
|
||||
flash0-supply = <&vccio_flash>;
|
||||
gpio1830-supply = <&vcc_18>;
|
||||
gpio30-supply = <&vcc_io>;
|
||||
sdcard-supply = <&vccio_sd>;
|
||||
wifi-supply = <&vcc_wl>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
hym8563 {
|
||||
hym8563_int: hym8563-int {
|
||||
rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
|
||||
drive-strength = <8>;
|
||||
};
|
||||
|
||||
pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
|
||||
bias-pull-up;
|
||||
drive-strength = <8>;
|
||||
};
|
||||
|
||||
pmic {
|
||||
pmic_int: pmic-int {
|
||||
rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
sdio-pwrseq {
|
||||
wifi_enable_h: wifi-enable-h {
|
||||
rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
sdmmc {
|
||||
sdmmc_bus4: sdmmc-bus4 {
|
||||
rockchip,pins =
|
||||
<6 RK_PC0 1 &pcfg_pull_up_drv_8ma>,
|
||||
<6 RK_PC1 1 &pcfg_pull_up_drv_8ma>,
|
||||
<6 RK_PC2 1 &pcfg_pull_up_drv_8ma>,
|
||||
<6 RK_PC3 1 &pcfg_pull_up_drv_8ma>;
|
||||
};
|
||||
|
||||
sdmmc_clk: sdmmc-clk {
|
||||
rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_drv_8ma>;
|
||||
};
|
||||
|
||||
sdmmc_cmd: sdmmc-cmd {
|
||||
rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up_drv_8ma>;
|
||||
};
|
||||
};
|
||||
|
||||
vbus_host {
|
||||
usb1_en_oc: usb1-en-oc {
|
||||
rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
vbus_typec {
|
||||
usb0_en_oc: usb0-en-oc {
|
||||
rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&sdio_pwrseq {
|
||||
/*
|
||||
* On the module itself this is one of these (depending
|
||||
* on the actual card populated):
|
||||
* - SDIO_RESET_L_WL_REG_ON
|
||||
* - PDN (power down when low)
|
||||
*/
|
||||
reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>; /* WIFI_REG_ON */
|
||||
};
|
||||
|
||||
&usbphy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_otg {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vbus_host {
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; /* USB1_EN_OC# */
|
||||
};
|
||||
|
||||
&vbus_typec {
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; /* USB0_EN_OC# */
|
||||
};
|
||||
@@ -1,473 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (C) 2017 Jagan Teki <jagan@amarulasolutions.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "rk3288.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Amarula Vyasa-RK3288";
|
||||
compatible = "amarula,vyasa-rk3288", "rockchip,rk3288";
|
||||
|
||||
chosen {
|
||||
stdout-path = &uart2;
|
||||
};
|
||||
|
||||
memory {
|
||||
reg = <0x0 0x0 0x0 0x80000000>;
|
||||
device_type = "memory";
|
||||
};
|
||||
|
||||
dc12_vbat: dc12-vbat {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "dc12_vbat";
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vboot_3v3: vboot-3v3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vboot_3v3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
vin-supply = <&dc12_vbat>;
|
||||
};
|
||||
|
||||
vcc_sys: vsys-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_sys";
|
||||
regulator-min-microvolt = <3700000>;
|
||||
regulator-max-microvolt = <3700000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
vin-supply = <&dc12_vbat>;
|
||||
};
|
||||
|
||||
vboot_5v: vboot-5v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vboot_sv";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
vin-supply = <&dc12_vbat>;
|
||||
};
|
||||
|
||||
v3g_3v3: v3g-3v3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "v3g_3v3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
vin-supply = <&dc12_vbat>;
|
||||
};
|
||||
|
||||
vsus_5v: vsus-5v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vsus_5v";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
vin-supply = <&vcc_io>;
|
||||
};
|
||||
|
||||
vcc50_hdmi: vcc50-hdmi {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc50_hdmi";
|
||||
enable-active-high;
|
||||
gpio = <&gpio7 RK_PB4 GPIO_ACTIVE_HIGH>; /* HDMI_EN */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc50_hdmi_en>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
vin-supply = <&vsus_5v>;
|
||||
};
|
||||
vusb1_5v: vusb1-5v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vusb1_5v";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; /* OTG_VBUS_DRV */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&otg_vbus_drv>;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
vin-supply = <&vsus_5v>;
|
||||
};
|
||||
|
||||
vusb2_5v: vusb2-5v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vusb2_5v";
|
||||
enable-active-high;
|
||||
gpio = <&gpio8 RK_PB1 GPIO_ACTIVE_HIGH>; /* USB2_PWR_EN */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usb2_pwr_en>;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
vin-supply = <&vsus_5v>;
|
||||
};
|
||||
|
||||
ext_gmac: external-gmac-clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <125000000>;
|
||||
clock-output-names = "ext_gmac";
|
||||
};
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu0-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&emmc {
|
||||
bus-width = <8>;
|
||||
cap-mmc-highspeed;
|
||||
non-removable;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>;
|
||||
vmmc-supply = <&vcc_io>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gmac {
|
||||
assigned-clocks = <&cru SCLK_MAC>;
|
||||
assigned-clock-parents = <&ext_gmac>;
|
||||
clock_in_out = "input";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>;
|
||||
phy-supply = <&vcc_lan>;
|
||||
phy-mode = "rgmii";
|
||||
snps,reset-active-low;
|
||||
snps,reset-delays-us = <0 10000 1000000>;
|
||||
snps,reset-gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_LOW>;
|
||||
tx_delay = <0x30>;
|
||||
rx_delay = <0x10>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpu {
|
||||
mali-supply = <&vdd_gpu>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
ddc-i2c-bus = <&i2c5>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
|
||||
rk808: pmic@1b {
|
||||
compatible = "rockchip,rk808";
|
||||
reg = <0x1b>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <RK_PA4 IRQ_TYPE_LEVEL_LOW>;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "xin32k", "rk808-clkout2";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_int &global_pwroff>;
|
||||
rockchip,system-power-controller;
|
||||
wakeup-source;
|
||||
|
||||
vcc1-supply = <&vcc_sys>;
|
||||
vcc2-supply = <&vcc_sys>;
|
||||
vcc3-supply = <&vcc_sys>;
|
||||
vcc4-supply = <&vcc_sys>;
|
||||
vcc6-supply = <&vcc_sys>;
|
||||
vcc7-supply = <&vcc_sys>;
|
||||
vcc8-supply = <&vcc_io>;
|
||||
vcc9-supply = <&vcc_sys>;
|
||||
vcc10-supply = <&vcc_sys>;
|
||||
vcc11-supply = <&vcc_sys>;
|
||||
vcc12-supply = <&vcc_io>;
|
||||
|
||||
regulators {
|
||||
vdd_cpu: DCDC_REG1 {
|
||||
regulator-name = "vdd_arm";
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_gpu: DCDC_REG2 {
|
||||
regulator-name = "vdd_gpu";
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <1250000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1000000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_ddr: DCDC_REG3 {
|
||||
regulator-name = "vcc_ddr";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_io: DCDC_REG4 {
|
||||
regulator-name = "vcc_io";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca_tp: LDO_REG1 {
|
||||
regulator-name = "vcc_tp";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_codec: LDO_REG2 {
|
||||
regulator-name = "vcc_codec";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_10: LDO_REG3 {
|
||||
regulator-name = "vdd_10";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1000000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_gps: LDO_REG4 {
|
||||
regulator-name = "vcc_gps";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_sd: LDO_REG5 {
|
||||
regulator-name = "vccio_sd";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vdd10_lcd: LDO_REG6 {
|
||||
regulator-name = "vdd10_lcd";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1000000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_18: LDO_REG7 {
|
||||
regulator-name = "vcc_18";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc18_lcd: LDO_REG8 {
|
||||
regulator-name = "vcc18_lcd";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_sd: SWITCH_REG1 {
|
||||
regulator-name = "vcc_sd";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_lan: SWITCH_REG2 {
|
||||
regulator-name = "vcc_lan";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c5 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc {
|
||||
bus-width = <4>;
|
||||
cap-mmc-highspeed;
|
||||
cap-sd-highspeed;
|
||||
card-detect-delay = <200>;
|
||||
disable-wp;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>;
|
||||
vmmc-supply = <&vcc_sd>;
|
||||
vqmmc-supply = <&vccio_sd>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tsadc {
|
||||
rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
|
||||
rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbphy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&phy_pwr_en>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_otg {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopb {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopb_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopl {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopl_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wdt {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
pcfg_output_high: pcfg-output-high {
|
||||
output-high;
|
||||
};
|
||||
|
||||
gmac {
|
||||
phy_int: phy-int {
|
||||
rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
phy_pmeb: phy-pmeb {
|
||||
rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
phy_rst: phy-rst {
|
||||
rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>;
|
||||
};
|
||||
};
|
||||
|
||||
hdmi {
|
||||
vcc50_hdmi_en: vcc50-hdmi-en {
|
||||
rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pmic {
|
||||
pmic_int: pmic-int {
|
||||
rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
usb_host {
|
||||
phy_pwr_en: phy-pwr-en {
|
||||
rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_output_high>;
|
||||
};
|
||||
|
||||
usb2_pwr_en: usb2-pwr-en {
|
||||
rockchip,pins = <8 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
usb_otg {
|
||||
otg_vbus_drv: otg-vbus-drv {
|
||||
rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
|
||||
};
|
||||
};
|
||||
};
|
||||
11
arch/arm/dts/rk3528-nanopi-zero2-u-boot.dtsi
Normal file
11
arch/arm/dts/rk3528-nanopi-zero2-u-boot.dtsi
Normal file
@@ -0,0 +1,11 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
|
||||
#include "rk3528-u-boot.dtsi"
|
||||
|
||||
&vdd_arm {
|
||||
regulator-init-microvolt = <953000>;
|
||||
};
|
||||
|
||||
&vdd_logic {
|
||||
regulator-init-microvolt = <900000>;
|
||||
};
|
||||
@@ -118,13 +118,11 @@
|
||||
&sdhci {
|
||||
bootph-pre-ram;
|
||||
bootph-some-ram;
|
||||
u-boot,spl-fifo-mode;
|
||||
};
|
||||
|
||||
&sdmmc {
|
||||
bootph-pre-ram;
|
||||
bootph-some-ram;
|
||||
u-boot,spl-fifo-mode;
|
||||
};
|
||||
|
||||
&sdmmc0_bus4 {
|
||||
@@ -154,12 +152,10 @@
|
||||
|
||||
&sfc0 {
|
||||
bootph-some-ram;
|
||||
u-boot,spl-sfc-no-dma;
|
||||
};
|
||||
|
||||
&sfc1 {
|
||||
bootph-some-ram;
|
||||
u-boot,spl-sfc-no-dma;
|
||||
};
|
||||
|
||||
&sys_grf {
|
||||
|
||||
@@ -1,13 +1,13 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Minimal generic DT for RK3588S/RK3588 with eMMC, SD-card and USB OTG enabled
|
||||
* Minimal generic DT for RK3582/RK3588S/RK3588 with eMMC, SD-card and USB OTG enabled
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "rk3588s.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Generic RK3588S/RK3588";
|
||||
model = "Generic RK3582/RK3588S/RK3588";
|
||||
compatible = "rockchip,rk3588";
|
||||
|
||||
aliases {
|
||||
|
||||
@@ -1,137 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
|
||||
* Copyright (c) 2019 Radxa Limited
|
||||
* Copyright (c) 2019 Amarula Solutions(India)
|
||||
*/
|
||||
|
||||
#include <dt-bindings/pwm/pwm.h>
|
||||
|
||||
/ {
|
||||
clkin_gmac: external-gmac-clock {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <125000000>;
|
||||
clock-output-names = "clkin_gmac";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
sdio_pwrseq: sdio-pwrseq {
|
||||
compatible = "mmc-pwrseq-simple";
|
||||
clocks = <&hym8563>;
|
||||
clock-names = "ext_clock";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wifi_enable_h>;
|
||||
};
|
||||
|
||||
vcc12v_dcin: vcc12v-dcin-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc12v_dcin";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
};
|
||||
|
||||
vcc5v0_sys: vcc5v0-sys-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
};
|
||||
|
||||
vbus_host: vbus-host {
|
||||
compatible = "regulator-fixed";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usb1_en_oc>;
|
||||
regulator-name = "vbus_host"; /* HOST-5V */
|
||||
regulator-always-on;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
|
||||
vbus_typec: vbus-typec {
|
||||
compatible = "regulator-fixed";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usb0_en_oc>;
|
||||
regulator-name = "vbus_typec";
|
||||
regulator-always-on;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
};
|
||||
|
||||
&gmac {
|
||||
assigned-clock-parents = <&clkin_gmac>;
|
||||
clock_in_out = "input";
|
||||
phy-mode = "rgmii";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&rgmii_pins>;
|
||||
snps,reset-active-low;
|
||||
snps,reset-delays-us = <0 10000 50000>;
|
||||
tx_delay = <0x28>;
|
||||
rx_delay = <0x11>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdio0 {
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
cap-sdio-irq;
|
||||
keep-power-in-suspend;
|
||||
mmc-pwrseq = <&sdio_pwrseq>;
|
||||
non-removable;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
|
||||
sd-uhs-sdr104;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc {
|
||||
bus-width = <4>;
|
||||
cap-mmc-highspeed;
|
||||
cap-sd-highspeed;
|
||||
disable-wp;
|
||||
vqmmc-supply = <&vccio_sd>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0_xfer &uart0_cts>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopb {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopb_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopl {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopl_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -246,16 +246,18 @@
|
||||
pad-byte = <0x00>;
|
||||
|
||||
u-boot-spl {
|
||||
no-write-symbols;
|
||||
};
|
||||
|
||||
payload {
|
||||
type = "section";
|
||||
align = <CONFIG_SYS_CACHELINE_SIZE>;
|
||||
#ifdef HAS_FIT
|
||||
fit {
|
||||
insert-template = <&fit_template>;
|
||||
#else
|
||||
u-boot-img {
|
||||
#endif
|
||||
offset = <(CONFIG_SPL_LOAD_FIT_ADDRESS - CFG_SYS_SDRAM_BASE)>;
|
||||
};
|
||||
};
|
||||
};
|
||||
#endif /* CONFIG_ROCKCHIP_MASKROM_IMAGE */
|
||||
|
||||
9
arch/arm/include/asm/arch-rk3506/boot0.h
Normal file
9
arch/arm/include/asm/arch-rk3506/boot0.h
Normal file
@@ -0,0 +1,9 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
/* Copyright Contributors to the U-Boot project. */
|
||||
|
||||
#ifndef __ASM_ARCH_BOOT0_H__
|
||||
#define __ASM_ARCH_BOOT0_H__
|
||||
|
||||
#include <asm/arch-rockchip/boot0.h>
|
||||
|
||||
#endif
|
||||
9
arch/arm/include/asm/arch-rk3506/gpio.h
Normal file
9
arch/arm/include/asm/arch-rk3506/gpio.h
Normal file
@@ -0,0 +1,9 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
/* Copyright Contributors to the U-Boot project. */
|
||||
|
||||
#ifndef __ASM_ARCH_GPIO_H__
|
||||
#define __ASM_ARCH_GPIO_H__
|
||||
|
||||
#include <asm/arch-rockchip/gpio.h>
|
||||
|
||||
#endif
|
||||
@@ -214,6 +214,16 @@ int rockchip_reset_bind(struct udevice *pdev, u32 reg_offset, u32 reg_number);
|
||||
*/
|
||||
int rockchip_reset_bind_lut(struct udevice *pdev, const int *lookup_table,
|
||||
u32 reg_offset, u32 reg_number);
|
||||
/*
|
||||
* rk3506_reset_bind_lut() - Bind soft reset device as child of clock device
|
||||
* using dedicated RK3506 lookup table
|
||||
*
|
||||
* @pdev: clock udevice
|
||||
* @reg_offset: the first offset in cru for softreset registers
|
||||
* @reg_number: the reg numbers of softreset registers
|
||||
* Return: 0 success, or error value
|
||||
*/
|
||||
int rk3506_reset_bind_lut(struct udevice *pdev, u32 reg_offset, u32 reg_number);
|
||||
/*
|
||||
* rk3528_reset_bind_lut() - Bind soft reset device as child of clock device
|
||||
* using dedicated RK3528 lookup table
|
||||
|
||||
181
arch/arm/include/asm/arch-rockchip/cru_rk3506.h
Normal file
181
arch/arm/include/asm/arch-rockchip/cru_rk3506.h
Normal file
@@ -0,0 +1,181 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
|
||||
* Author: Finley Xiao <finley.xiao@rock-chips.com>
|
||||
*/
|
||||
|
||||
#ifndef _ASM_ARCH_CRU_RK3506_H
|
||||
#define _ASM_ARCH_CRU_RK3506_H
|
||||
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/bitfield.h>
|
||||
|
||||
#define MHz 1000000
|
||||
#define KHz 1000
|
||||
#define OSC_HZ (24 * MHz)
|
||||
|
||||
/* RK3506 pll id */
|
||||
enum rk3506_pll_id {
|
||||
GPLL,
|
||||
V0PLL,
|
||||
V1PLL,
|
||||
PLL_COUNT,
|
||||
};
|
||||
|
||||
struct rk3506_clk_priv {
|
||||
unsigned long gpll_hz;
|
||||
unsigned long gpll_div_hz;
|
||||
unsigned long gpll_div_100mhz;
|
||||
unsigned long v0pll_hz;
|
||||
unsigned long v0pll_div_hz;
|
||||
unsigned long v1pll_hz;
|
||||
unsigned long v1pll_div_hz;
|
||||
};
|
||||
|
||||
struct pll_rate_table {
|
||||
unsigned long rate;
|
||||
unsigned int fbdiv;
|
||||
unsigned int postdiv1;
|
||||
unsigned int refdiv;
|
||||
unsigned int postdiv2;
|
||||
unsigned int dsmpd;
|
||||
unsigned int frac;
|
||||
};
|
||||
|
||||
#define RK3506_CRU_BASE 0xff9a0000
|
||||
#define RK3506_MODE_CON 0x0280
|
||||
#define RK3506_CLKSEL_CON(x) (RK3506_CRU_BASE + 0x0300 + (x) * 0x4)
|
||||
#define RK3506_SOFTRST_CON0 0x0a00
|
||||
#define RK3506_GLB_SRST_FST 0x0c08
|
||||
#define RK3506_GLB_SRST_SND 0x0c0c
|
||||
#define RK3506_PLL_CON(x) (0x10000 + (x) * 0x4)
|
||||
#define RK3506_SCRU_BASE 0xff9a8000
|
||||
#define RK3506_PMU_CRU_BASE 0xff9b0000
|
||||
#define RK3506_PMU_CLKSEL_CON(x) (RK3506_PMU_CRU_BASE + 0x0300 + (x) * 0x4)
|
||||
|
||||
enum {
|
||||
/* CRU_CLKSEL_CON00 */
|
||||
CLK_GPLL_DIV_MASK = GENMASK(9, 6),
|
||||
CLK_GPLL_DIV_100M_MASK = GENMASK(13, 10),
|
||||
|
||||
/* CRU_CLKSEL_CON01 */
|
||||
CLK_V0PLL_DIV_MASK = GENMASK(3, 0),
|
||||
CLK_V1PLL_DIV_MASK = GENMASK(7, 4),
|
||||
|
||||
/* CRU_CLKSEL_CON15 */
|
||||
CLK_CORE_SRC_DIV_MASK = GENMASK(4, 0),
|
||||
CLK_CORE_SRC_SEL_MASK = GENMASK(6, 5),
|
||||
CLK_CORE_SEL_GPLL = 0,
|
||||
CLK_CORE_SEL_V0PLL,
|
||||
CLK_CORE_SEL_V1PLL,
|
||||
|
||||
ACLK_CORE_DIV_MASK = GENMASK(12, 9),
|
||||
|
||||
/* CRU_CLKSEL_CON16 */
|
||||
PCLK_CORE_DIV_MASK = GENMASK(3, 0),
|
||||
|
||||
/* CRU_CLKSEL_CON21 */
|
||||
ACLK_BUS_DIV_MASK = GENMASK(4, 0),
|
||||
ACLK_BUS_SEL_MASK = GENMASK(6, 5),
|
||||
ACLK_BUS_SEL_GPLL_DIV = 0,
|
||||
ACLK_BUS_SEL_V0PLL_DIV,
|
||||
ACLK_BUS_SEL_V1PLL_DIV,
|
||||
|
||||
HCLK_BUS_DIV_MASK = GENMASK(11, 7),
|
||||
HCLK_BUS_SEL_MASK = GENMASK(13, 12),
|
||||
|
||||
/* CRU_CLKSEL_CON22 */
|
||||
PCLK_BUS_DIV_MASK = GENMASK(4, 0),
|
||||
PCLK_BUS_SEL_MASK = GENMASK(6, 5),
|
||||
|
||||
/* CRU_CLKSEL_CON29 */
|
||||
HCLK_LSPERI_DIV_MASK = GENMASK(4, 0),
|
||||
HCLK_LSPERI_SEL_MASK = GENMASK(6, 5),
|
||||
|
||||
/* CRU_CLKSEL_CON32 */
|
||||
CLK_I2C0_DIV_MASK = GENMASK(3, 0),
|
||||
CLK_I2C0_SEL_MASK = GENMASK(5, 4),
|
||||
CLK_I2C_SEL_GPLL = 0,
|
||||
CLK_I2C_SEL_V0PLL,
|
||||
CLK_I2C_SEL_V1PLL,
|
||||
CLK_I2C1_DIV_MASK = GENMASK(9, 6),
|
||||
CLK_I2C1_SEL_MASK = GENMASK(11, 10),
|
||||
|
||||
/* CRU_CLKSEL_CON33 */
|
||||
CLK_I2C2_DIV_MASK = GENMASK(3, 0),
|
||||
CLK_I2C2_SEL_MASK = GENMASK(5, 4),
|
||||
CLK_PWM1_DIV_MASK = GENMASK(9, 6),
|
||||
CLK_PWM1_SEL_MASK = GENMASK(11, 10),
|
||||
CLK_PWM1_SEL_GPLL_DIV = 0,
|
||||
CLK_PWM1_SEL_V0PLL_DIV,
|
||||
CLK_PWM1_SEL_V1PLL_DIV,
|
||||
|
||||
/* CRU_CLKSEL_CON34 */
|
||||
CLK_SPI0_DIV_MASK = GENMASK(7, 4),
|
||||
CLK_SPI0_SEL_MASK = GENMASK(9, 8),
|
||||
CLK_SPI_SEL_24M = 0,
|
||||
CLK_SPI_SEL_GPLL_DIV,
|
||||
CLK_SPI_SEL_V0PLL_DIV,
|
||||
CLK_SPI_SEL_V1PLL_DIV,
|
||||
CLK_SPI1_DIV_MASK = GENMASK(13, 10),
|
||||
CLK_SPI1_SEL_MASK = GENMASK(15, 14),
|
||||
|
||||
/* CRU_CLKSEL_CON49 */
|
||||
ACLK_HSPERI_DIV_MASK = GENMASK(4, 0),
|
||||
ACLK_HSPERI_SEL_MASK = GENMASK(6, 5),
|
||||
ACLK_HSPERI_SEL_GPLL_DIV = 0,
|
||||
ACLK_HSPERI_SEL_V0PLL_DIV,
|
||||
ACLK_HSPERI_SEL_V1PLL_DIV,
|
||||
|
||||
CCLK_SDMMC_DIV_MASK = GENMASK(12, 7),
|
||||
CCLK_SDMMC_SEL_MASK = GENMASK(14, 13),
|
||||
CCLK_SDMMC_SEL_24M = 0,
|
||||
CCLK_SDMMC_SEL_GPLL,
|
||||
CCLK_SDMMC_SEL_V0PLL,
|
||||
CCLK_SDMMC_SEL_V1PLL,
|
||||
|
||||
/* CRU_CLKSEL_CON50 */
|
||||
SCLK_FSPI_DIV_MASK = GENMASK(4, 0),
|
||||
SCLK_FSPI_SEL_MASK = GENMASK(6, 5),
|
||||
SCLK_FSPI_SEL_24M = 0,
|
||||
SCLK_FSPI_SEL_GPLL,
|
||||
SCLK_FSPI_SEL_V0PLL,
|
||||
SCLK_FSPI_SEL_V1PLL,
|
||||
CLK_MAC_DIV_MASK = GENMASK(11, 7),
|
||||
|
||||
/* CRU_CLKSEL_CON54 */
|
||||
CLK_SARADC_DIV_MASK = GENMASK(3, 0),
|
||||
CLK_SARADC_SEL_MASK = GENMASK(5, 4),
|
||||
CLK_SARADC_SEL_24M = 0,
|
||||
CLK_SARADC_SEL_400K,
|
||||
CLK_SARADC_SEL_32K,
|
||||
|
||||
/* CRU_CLKSEL_CON60 */
|
||||
DCLK_VOP_DIV_MASK = GENMASK(7, 0),
|
||||
DCLK_VOP_SEL_MASK = GENMASK(10, 8),
|
||||
DCLK_VOP_SEL_24M = 0,
|
||||
DCLK_VOP_SEL_GPLL,
|
||||
DCLK_VOP_SEL_V0PLL,
|
||||
DCLK_VOP_SEL_V1PLL,
|
||||
DCLK_VOP_SEL_FRAC_VOIC1,
|
||||
DCLK_VOP_SEL_FRAC_COMMON0,
|
||||
DCLK_VOP_SEL_FRAC_COMMON1,
|
||||
DCLK_VOP_SEL_FRAC_COMMON2,
|
||||
|
||||
/* CRU_CLKSEL_CON61 */
|
||||
CLK_TSADC_DIV_MASK = GENMASK(7, 0),
|
||||
CLK_TSADC_TSEN_DIV_MASK = GENMASK(10, 8),
|
||||
|
||||
/* PMUCRU_CLKSEL_CON00 */
|
||||
CLK_PWM0_DIV_MASK = GENMASK(9, 6),
|
||||
CLK_MAC_OUT_DIV_MASK = GENMASK(15, 10),
|
||||
|
||||
/* SCRU_CLKSEL_CON104 */
|
||||
CLK_PKA_CRYPTO_DIV_MASK = GENMASK(11, 7),
|
||||
CLK_PKA_CRYPTO_SEL_MASK = GENMASK(13, 12),
|
||||
CLK_PKA_CRYPTO_SEL_GPLL = 0,
|
||||
CLK_PKA_CRYPTO_SEL_V0PLL,
|
||||
CLK_PKA_CRYPTO_SEL_V1PLL,
|
||||
};
|
||||
|
||||
#endif /* _ASM_ARCH_CRU_RK3506_H */
|
||||
@@ -8,7 +8,6 @@ config ROCKCHIP_PX30
|
||||
select SUPPORT_TPL
|
||||
select SPL
|
||||
select TPL
|
||||
select TPL_TINY_FRAMEWORK if TPL
|
||||
select TPL_HAVE_INIT_STACK if TPL
|
||||
imply SPL_SEPARATE_BSS
|
||||
imply SPL_SERIAL
|
||||
@@ -132,6 +131,7 @@ config ROCKCHIP_RK3288
|
||||
select SPL
|
||||
select SUPPORT_TPL
|
||||
select FDT_64BIT
|
||||
imply OF_UPSTREAM
|
||||
imply PRE_CONSOLE_BUFFER
|
||||
imply ROCKCHIP_COMMON_BOARD
|
||||
imply SPL_ROCKCHIP_COMMON_BOARD
|
||||
@@ -317,6 +317,49 @@ config ROCKCHIP_RK3399
|
||||
and video codec support. Peripherals include Gigabit Ethernet,
|
||||
USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
|
||||
|
||||
config ROCKCHIP_RK3506
|
||||
bool "Support Rockchip RK3506"
|
||||
select CPU_V7A
|
||||
select SUPPORT_SPL
|
||||
select SPL
|
||||
select CLK
|
||||
select PINCTRL
|
||||
select RAM
|
||||
select REGMAP
|
||||
select SYSCON
|
||||
select BOARD_LATE_INIT
|
||||
select DM_REGULATOR_FIXED
|
||||
select DM_RESET
|
||||
imply BOOTSTD_FULL
|
||||
imply DM_RNG
|
||||
imply ENV_RELOC_GD_ENV_ADDR
|
||||
imply FIT
|
||||
imply LEGACY_IMAGE_FORMAT
|
||||
imply MISC
|
||||
imply MISC_INIT_R
|
||||
imply OF_LIBFDT_OVERLAY
|
||||
imply OF_LIVE
|
||||
imply RNG_ROCKCHIP
|
||||
imply ROCKCHIP_COMMON_BOARD
|
||||
imply ROCKCHIP_COMMON_STACK_ADDR
|
||||
imply ROCKCHIP_EXTERNAL_TPL
|
||||
imply ROCKCHIP_OTP
|
||||
imply SPL_ARMV7_SET_CORTEX_SMPEN
|
||||
imply SPL_CLK
|
||||
imply SPL_DM_SEQ_ALIAS
|
||||
imply SPL_FIT_SIGNATURE
|
||||
imply SPL_LOAD_FIT
|
||||
imply SPL_OF_CONTROL
|
||||
imply SPL_PINCTRL
|
||||
imply SPL_RAM
|
||||
imply SPL_REGMAP
|
||||
imply SPL_SERIAL
|
||||
imply SPL_SYSCON
|
||||
imply SYS_ARCH_TIMER
|
||||
imply SYSRESET
|
||||
help
|
||||
The Rockchip RK3506 is a ARM-based SoC with a tri-core Cortex-A7.
|
||||
|
||||
config ROCKCHIP_RK3528
|
||||
bool "Support Rockchip RK3528"
|
||||
select ARM64
|
||||
@@ -745,6 +788,7 @@ source "arch/arm/mach-rockchip/rk3308/Kconfig"
|
||||
source "arch/arm/mach-rockchip/rk3328/Kconfig"
|
||||
source "arch/arm/mach-rockchip/rk3368/Kconfig"
|
||||
source "arch/arm/mach-rockchip/rk3399/Kconfig"
|
||||
source "arch/arm/mach-rockchip/rk3506/Kconfig"
|
||||
source "arch/arm/mach-rockchip/rk3528/Kconfig"
|
||||
source "arch/arm/mach-rockchip/rk3568/Kconfig"
|
||||
source "arch/arm/mach-rockchip/rk3576/Kconfig"
|
||||
|
||||
@@ -42,6 +42,7 @@ obj-$(CONFIG_ROCKCHIP_RK3308) += rk3308/
|
||||
obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328/
|
||||
obj-$(CONFIG_ROCKCHIP_RK3368) += rk3368/
|
||||
obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399/
|
||||
obj-$(CONFIG_ROCKCHIP_RK3506) += rk3506/
|
||||
obj-$(CONFIG_ROCKCHIP_RK3528) += rk3528/
|
||||
obj-$(CONFIG_ROCKCHIP_RK3568) += rk3568/
|
||||
obj-$(CONFIG_ROCKCHIP_RK3576) += rk3576/
|
||||
|
||||
15
arch/arm/mach-rockchip/rk3506/Kconfig
Normal file
15
arch/arm/mach-rockchip/rk3506/Kconfig
Normal file
@@ -0,0 +1,15 @@
|
||||
if ROCKCHIP_RK3506
|
||||
|
||||
config ROCKCHIP_BOOT_MODE_REG
|
||||
default 0xff910200
|
||||
|
||||
config ROCKCHIP_STIMER_BASE
|
||||
default 0xff980000
|
||||
|
||||
config SYS_SOC
|
||||
default "rk3506"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "rk3506_common"
|
||||
|
||||
endif
|
||||
5
arch/arm/mach-rockchip/rk3506/Makefile
Normal file
5
arch/arm/mach-rockchip/rk3506/Makefile
Normal file
@@ -0,0 +1,5 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
obj-y += rk3506.o
|
||||
obj-y += clk_rk3506.o
|
||||
obj-y += syscon_rk3506.o
|
||||
16
arch/arm/mach-rockchip/rk3506/clk_rk3506.c
Normal file
16
arch/arm/mach-rockchip/rk3506/clk_rk3506.c
Normal file
@@ -0,0 +1,16 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
// Copyright Contributors to the U-Boot project.
|
||||
|
||||
#include <dm.h>
|
||||
#include <asm/arch-rockchip/cru_rk3506.h>
|
||||
|
||||
int rockchip_get_clk(struct udevice **devp)
|
||||
{
|
||||
return uclass_get_device_by_driver(UCLASS_CLK,
|
||||
DM_DRIVER_GET(rockchip_rk3506_cru), devp);
|
||||
}
|
||||
|
||||
void *rockchip_get_cru(void)
|
||||
{
|
||||
return (void *)RK3506_CRU_BASE;
|
||||
}
|
||||
125
arch/arm/mach-rockchip/rk3506/rk3506.c
Normal file
125
arch/arm/mach-rockchip/rk3506/rk3506.c
Normal file
@@ -0,0 +1,125 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
// Copyright Contributors to the U-Boot project.
|
||||
|
||||
#define LOG_CATEGORY LOGC_ARCH
|
||||
|
||||
#include <dm.h>
|
||||
#include <misc.h>
|
||||
#include <asm/arch-rockchip/bootrom.h>
|
||||
#include <asm/arch-rockchip/hardware.h>
|
||||
|
||||
#define SGRF_BASE 0xff210000
|
||||
|
||||
#define FIREWALL_DDR_BASE 0xff5f0000
|
||||
#define FW_DDR_MST1_REG 0x24
|
||||
#define FW_DDR_MST2_REG 0x28
|
||||
#define FW_DDR_MST3_REG 0x2c
|
||||
|
||||
const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
|
||||
[BROM_BOOTSOURCE_EMMC] = "/soc/mmc@ff480000",
|
||||
[BROM_BOOTSOURCE_SD] = "/soc/mmc@ff480000",
|
||||
};
|
||||
|
||||
void board_debug_uart_init(void)
|
||||
{
|
||||
}
|
||||
|
||||
int arch_cpu_init(void)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
if (!IS_ENABLED(CONFIG_SPL_BUILD))
|
||||
return 0;
|
||||
|
||||
/* Select non-secure OTPC */
|
||||
rk_clrreg(SGRF_BASE + 0x100, BIT(1));
|
||||
|
||||
/* Set the sdmmc/emmc to access ddr memory */
|
||||
val = readl(FIREWALL_DDR_BASE + FW_DDR_MST1_REG);
|
||||
writel(val & 0xffff00ff, FIREWALL_DDR_BASE + FW_DDR_MST1_REG);
|
||||
|
||||
/* Set the fspi to access ddr memory */
|
||||
val = readl(FIREWALL_DDR_BASE + FW_DDR_MST1_REG);
|
||||
writel(val & 0xff00ffff, FIREWALL_DDR_BASE + FW_DDR_MST1_REG);
|
||||
|
||||
/* Set the mac0 to access ddr memory */
|
||||
val = readl(FIREWALL_DDR_BASE + FW_DDR_MST1_REG);
|
||||
writel(val & 0xf0ffffff, FIREWALL_DDR_BASE + FW_DDR_MST1_REG);
|
||||
|
||||
/* Set the mac1 to access ddr memory */
|
||||
val = readl(FIREWALL_DDR_BASE + FW_DDR_MST2_REG);
|
||||
writel(val & 0xfffffff0, FIREWALL_DDR_BASE + FW_DDR_MST2_REG);
|
||||
|
||||
/* Set the otg1 to access ddr memory */
|
||||
val = readl(FIREWALL_DDR_BASE + FW_DDR_MST3_REG);
|
||||
writel(val & 0xfff0ffff, FIREWALL_DDR_BASE + FW_DDR_MST3_REG);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#define HP_TIMER_BASE CONFIG_ROCKCHIP_STIMER_BASE
|
||||
#define HP_CTRL_REG 0x04
|
||||
#define TIMER_EN BIT(0)
|
||||
#define HP_LOAD_COUNT0_REG 0x14
|
||||
#define HP_LOAD_COUNT1_REG 0x18
|
||||
|
||||
void rockchip_stimer_init(void)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
if (!IS_ENABLED(CONFIG_XPL_BUILD))
|
||||
return;
|
||||
|
||||
reg = readl(HP_TIMER_BASE + HP_CTRL_REG);
|
||||
if (reg & TIMER_EN)
|
||||
return;
|
||||
|
||||
asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (CONFIG_COUNTER_FREQUENCY));
|
||||
writel(0xffffffff, HP_TIMER_BASE + HP_LOAD_COUNT0_REG);
|
||||
writel(0xffffffff, HP_TIMER_BASE + HP_LOAD_COUNT1_REG);
|
||||
writel((TIMER_EN << 16) | TIMER_EN, HP_TIMER_BASE + HP_CTRL_REG);
|
||||
}
|
||||
|
||||
#define RK3506_OTP_CPU_CODE_OFFSET 0x02
|
||||
#define RK3506_OTP_SPECIFICATION_OFFSET 0x08
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
u8 cpu_code[2], specification;
|
||||
struct udevice *dev;
|
||||
char suffix[2];
|
||||
int ret;
|
||||
|
||||
if (!IS_ENABLED(CONFIG_ROCKCHIP_OTP) || !CONFIG_IS_ENABLED(MISC))
|
||||
return 0;
|
||||
|
||||
ret = uclass_get_device_by_driver(UCLASS_MISC,
|
||||
DM_DRIVER_GET(rockchip_otp), &dev);
|
||||
if (ret) {
|
||||
log_debug("Could not find otp device, ret=%d\n", ret);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* cpu-code: SoC model, e.g. 0x35 0x06 */
|
||||
ret = misc_read(dev, RK3506_OTP_CPU_CODE_OFFSET, cpu_code, 2);
|
||||
if (ret < 0) {
|
||||
log_debug("Could not read cpu-code, ret=%d\n", ret);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* specification: SoC variant, e.g. 0xA for RK3506J */
|
||||
ret = misc_read(dev, RK3506_OTP_SPECIFICATION_OFFSET, &specification, 1);
|
||||
if (ret < 0) {
|
||||
log_debug("Could not read specification, ret=%d\n", ret);
|
||||
return 0;
|
||||
}
|
||||
specification &= 0x1f;
|
||||
|
||||
/* for RK3506J i.e. '@' + 0xA = 'J' */
|
||||
suffix[0] = specification > 1 ? '@' + specification : '\0';
|
||||
suffix[1] = '\0';
|
||||
|
||||
printf("SoC: RK%02x%02x%s\n", cpu_code[0], cpu_code[1], suffix);
|
||||
|
||||
return 0;
|
||||
}
|
||||
19
arch/arm/mach-rockchip/rk3506/syscon_rk3506.c
Normal file
19
arch/arm/mach-rockchip/rk3506/syscon_rk3506.c
Normal file
@@ -0,0 +1,19 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
// Copyright Contributors to the U-Boot project.
|
||||
|
||||
#include <dm.h>
|
||||
#include <asm/arch-rockchip/clock.h>
|
||||
|
||||
static const struct udevice_id rk3506_syscon_ids[] = {
|
||||
{ .compatible = "rockchip,rk3506-grf", .data = ROCKCHIP_SYSCON_GRF },
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(rockchip_rk3506_syscon) = {
|
||||
.name = "rockchip_rk3506_syscon",
|
||||
.id = UCLASS_SYSCON,
|
||||
.of_match = rk3506_syscon_ids,
|
||||
#if CONFIG_IS_ENABLED(OF_REAL)
|
||||
.bind = dm_scan_fdt_dev,
|
||||
#endif
|
||||
};
|
||||
@@ -4,6 +4,12 @@ S: Maintained
|
||||
F: arch/arm/dts/rk3528-generic*
|
||||
F: configs/generic-rk3528_defconfig
|
||||
|
||||
NANOPI-ZERO2-RK3528
|
||||
M: Jonas Karlman <jonas@kwiboo.se>
|
||||
S: Maintained
|
||||
F: arch/arm/dts/rk3528-nanopi-zero2*
|
||||
F: configs/nanopi-zero2-rk3528_defconfig
|
||||
|
||||
RADXA-E20C
|
||||
M: Jonas Karlman <jonas@kwiboo.se>
|
||||
S: Maintained
|
||||
|
||||
@@ -49,21 +49,6 @@ void board_debug_uart_init(void)
|
||||
{
|
||||
}
|
||||
|
||||
u32 read_brom_bootsource_id(void)
|
||||
{
|
||||
u32 bootsource_id = readl(BROM_BOOTSOURCE_ID_ADDR);
|
||||
|
||||
/* Re-map the raw value read from reg to an existing BROM_BOOTSOURCE
|
||||
* enum value to avoid having to create a larger boot_devices table.
|
||||
*/
|
||||
if (bootsource_id == 0x81)
|
||||
return BROM_BOOTSOURCE_USB;
|
||||
else if (bootsource_id > BROM_LAST_BOOTSOURCE)
|
||||
log_debug("Unknown bootsource %x\n", bootsource_id);
|
||||
|
||||
return bootsource_id;
|
||||
}
|
||||
|
||||
int arch_cpu_init(void)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
@@ -26,6 +26,9 @@
|
||||
#define SYS_SGRF_SOC_CON15 0x005C
|
||||
#define SYS_SGRF_SOC_CON20 0x0070
|
||||
|
||||
#define FW_PMU1SGRF_BASE 0x26003000
|
||||
#define PMU1SGRF_SLV_LOOKUP0 0x80
|
||||
|
||||
#define FW_SYS_SGRF_BASE 0x26005000
|
||||
#define SGRF_DOMAIN_CON1 0x4
|
||||
#define SGRF_DOMAIN_CON2 0x8
|
||||
@@ -140,6 +143,9 @@ int arch_cpu_init(void)
|
||||
if (!IS_ENABLED(CONFIG_SPL_BUILD))
|
||||
return 0;
|
||||
|
||||
/* Allow pmu sram access for non-secure masters */
|
||||
writel(0xffff3fff, FW_PMU1SGRF_BASE + PMU1SGRF_SLV_LOOKUP0);
|
||||
|
||||
/* Set the emmc to access ddr memory */
|
||||
val = readl(FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON2);
|
||||
writel(val | 0x7, FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON2);
|
||||
|
||||
@@ -286,14 +286,15 @@ config TARGET_ROCK_5_ITX_RK3588
|
||||
Powered by either 12V, ATX power-supply or PoE
|
||||
|
||||
config TARGET_ROCK_5C_RK3588S
|
||||
bool "Radxa ROCK 5C RK3588S2 board"
|
||||
bool "Radxa ROCK 5C/5C Lite"
|
||||
help
|
||||
Radxa ROCK 5C is a Rockchip RK3588S2 based single board computer.
|
||||
Radxa ROCK 5C/5C Lite is a Rockchip RK3588S2/RK3582 based SBC (Single
|
||||
Board Computer) by Radxa.
|
||||
|
||||
Specification:
|
||||
|
||||
Quad A76 and Quad A55 CPU
|
||||
6 TOPS NPU
|
||||
Quad/Dual A76 and Quad A55 CPU
|
||||
6/5 TOPS NPU
|
||||
up to 32GB LPDDR4x RAM
|
||||
eMMC / SPI flash connector
|
||||
Micro SD Card slot
|
||||
|
||||
@@ -7,6 +7,7 @@
|
||||
#define LOG_CATEGORY LOGC_ARCH
|
||||
|
||||
#include <dm.h>
|
||||
#include <fdt_support.h>
|
||||
#include <misc.h>
|
||||
#include <spl.h>
|
||||
#include <asm/armv8/mmu.h>
|
||||
@@ -87,6 +88,24 @@ static struct mm_region rk3588_mem_map[] = {
|
||||
PTE_BLOCK_NON_SHARE |
|
||||
PTE_BLOCK_PXN | PTE_BLOCK_UXN
|
||||
}, {
|
||||
.virt = 0x100000000UL,
|
||||
.phys = 0x100000000UL,
|
||||
.size = 0x2fc000000UL,
|
||||
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
|
||||
PTE_BLOCK_INNER_SHARE
|
||||
}, {
|
||||
.virt = 0x3fc500000UL,
|
||||
.phys = 0x3fc500000UL,
|
||||
.size = 0x3a00000UL,
|
||||
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
|
||||
PTE_BLOCK_INNER_SHARE
|
||||
}, {
|
||||
.virt = 0x400000000UL,
|
||||
.phys = 0x400000000UL,
|
||||
.size = 0x400000000UL,
|
||||
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
|
||||
PTE_BLOCK_INNER_SHARE
|
||||
}, {
|
||||
.virt = 0x900000000,
|
||||
.phys = 0x900000000,
|
||||
.size = 0x150000000,
|
||||
@@ -211,8 +230,45 @@ int arch_cpu_init(void)
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* RK3588 has two known memory gaps when using 16+ GiB DRAM,
|
||||
* [0x3fc000000, 0x3fc500000) and [0x3fff00000, 0x400000000).
|
||||
*
|
||||
* Remove the [0x3fc000000, 0x400000000) range to ensure OS does not
|
||||
* use memory from these gaps when a DDR_MEM tag cannot be found.
|
||||
*/
|
||||
|
||||
#define DRAM_GAP_START 0x3FC000000
|
||||
#define DRAM_GAP_END 0x400000000
|
||||
|
||||
int rockchip_dram_init_banksize_fixup(struct bd_info *bd)
|
||||
{
|
||||
size_t ram_top = bd->bi_dram[1].start + bd->bi_dram[1].size;
|
||||
|
||||
if (ram_top > DRAM_GAP_START) {
|
||||
bd->bi_dram[1].size = DRAM_GAP_START - bd->bi_dram[1].start;
|
||||
|
||||
if (ram_top > DRAM_GAP_END && CONFIG_NR_DRAM_BANKS > 2) {
|
||||
bd->bi_dram[2].start = DRAM_GAP_END;
|
||||
bd->bi_dram[2].size = ram_top - bd->bi_dram[2].start;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#define RK3588_OTP_CPU_CODE_OFFSET 0x02
|
||||
#define RK3588_OTP_SPECIFICATION_OFFSET 0x06
|
||||
#define RK3588_OTP_IP_STATE_OFFSET 0x1d
|
||||
|
||||
#define FAIL_CPU_CLUSTER0 GENMASK(3, 0)
|
||||
#define FAIL_CPU_CLUSTER1 GENMASK(5, 4)
|
||||
#define FAIL_CPU_CLUSTER2 GENMASK(7, 6)
|
||||
#define FAIL_GPU GENMASK(4, 1)
|
||||
#define FAIL_RKVDEC0 BIT(6)
|
||||
#define FAIL_RKVDEC1 BIT(7)
|
||||
#define FAIL_RKVENC0 BIT(0)
|
||||
#define FAIL_RKVENC1 BIT(2)
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
@@ -258,3 +314,207 @@ int checkboard(void)
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int fdt_path_del_node(void *fdt, const char *path)
|
||||
{
|
||||
int nodeoffset;
|
||||
|
||||
nodeoffset = fdt_path_offset(fdt, path);
|
||||
if (nodeoffset < 0)
|
||||
return nodeoffset;
|
||||
|
||||
return fdt_del_node(fdt, nodeoffset);
|
||||
}
|
||||
|
||||
static int fdt_path_set_name(void *fdt, const char *path, const char *name)
|
||||
{
|
||||
int nodeoffset;
|
||||
|
||||
nodeoffset = fdt_path_offset(fdt, path);
|
||||
if (nodeoffset < 0)
|
||||
return nodeoffset;
|
||||
|
||||
return fdt_set_name(fdt, nodeoffset, name);
|
||||
}
|
||||
|
||||
/*
|
||||
* RK3582 is a variant of the RK3588S with some IP blocks disabled. What blocks
|
||||
* are disabled/non-working is indicated by ip-state in OTP. ft_system_setup()
|
||||
* is used to mark any cpu, gpu and/or vdec/venc node with status=fail as
|
||||
* indicated by ip-state. Apply same policy as vendor U-Boot for RK3582, i.e.
|
||||
* two big cpu cores, the gpu and one vdec/venc core is always failed. Enable
|
||||
* OF_SYSTEM_SETUP to use the required DT fixups for RK3582 board variants.
|
||||
*/
|
||||
int ft_system_setup(void *blob, struct bd_info *bd)
|
||||
{
|
||||
static const char * const cpu_node_names[] = {
|
||||
"cpu@0", "cpu@100", "cpu@200", "cpu@300",
|
||||
"cpu@400", "cpu@500", "cpu@600", "cpu@700",
|
||||
};
|
||||
int parent, node, i, comp_len, len, ret;
|
||||
bool cluster1_removed = false;
|
||||
u8 cpu_code[2], ip_state[3];
|
||||
struct udevice *dev;
|
||||
char soc_comp[16];
|
||||
const char *comp;
|
||||
void *data;
|
||||
|
||||
if (!IS_ENABLED(CONFIG_OF_SYSTEM_SETUP))
|
||||
return 0;
|
||||
|
||||
if (!IS_ENABLED(CONFIG_ROCKCHIP_OTP) || !CONFIG_IS_ENABLED(MISC))
|
||||
return -ENOSYS;
|
||||
|
||||
ret = uclass_get_device_by_driver(UCLASS_MISC,
|
||||
DM_DRIVER_GET(rockchip_otp), &dev);
|
||||
if (ret) {
|
||||
log_debug("Could not find otp device, ret=%d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* cpu-code: SoC model, e.g. 0x35 0x82 or 0x35 0x88 */
|
||||
ret = misc_read(dev, RK3588_OTP_CPU_CODE_OFFSET, cpu_code, 2);
|
||||
if (ret < 0) {
|
||||
log_debug("Could not read cpu-code, ret=%d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
log_debug("cpu-code: %02x %02x\n", cpu_code[0], cpu_code[1]);
|
||||
|
||||
/* only fail cores on rk3582 */
|
||||
if (!(cpu_code[0] == 0x35 && cpu_code[1] == 0x82))
|
||||
return 0;
|
||||
|
||||
ret = misc_read(dev, RK3588_OTP_IP_STATE_OFFSET, &ip_state, 3);
|
||||
if (ret < 0) {
|
||||
log_err("Could not read ip-state, ret=%d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
log_debug("ip-state: %02x %02x %02x (otp)\n",
|
||||
ip_state[0], ip_state[1], ip_state[2]);
|
||||
|
||||
/* policy: fail entire big core cluster when one or more core is bad */
|
||||
if (ip_state[0] & FAIL_CPU_CLUSTER1)
|
||||
ip_state[0] |= FAIL_CPU_CLUSTER1;
|
||||
if (ip_state[0] & FAIL_CPU_CLUSTER2)
|
||||
ip_state[0] |= FAIL_CPU_CLUSTER2;
|
||||
|
||||
/* policy: always fail one big core cluster on rk3582 */
|
||||
if (!(ip_state[0] & (FAIL_CPU_CLUSTER1 | FAIL_CPU_CLUSTER2)))
|
||||
ip_state[0] |= FAIL_CPU_CLUSTER2;
|
||||
|
||||
/* policy: always fail gpu on rk3582 */
|
||||
ip_state[1] |= FAIL_GPU;
|
||||
|
||||
/* policy: always fail one rkvdec core on rk3582 */
|
||||
if (!(ip_state[1] & (FAIL_RKVDEC0 | FAIL_RKVDEC1)))
|
||||
ip_state[1] |= FAIL_RKVDEC1;
|
||||
|
||||
/* policy: always fail one rkvenc core on rk3582 */
|
||||
if (!(ip_state[2] & (FAIL_RKVENC0 | FAIL_RKVENC1)))
|
||||
ip_state[2] |= FAIL_RKVENC1;
|
||||
|
||||
log_debug("ip-state: %02x %02x %02x (policy)\n",
|
||||
ip_state[0], ip_state[1], ip_state[2]);
|
||||
|
||||
/* cpu cluster1: ip_state[0]: bit4~5 */
|
||||
if ((ip_state[0] & FAIL_CPU_CLUSTER1) == FAIL_CPU_CLUSTER1) {
|
||||
log_debug("remove cpu-map cluster1\n");
|
||||
fdt_path_del_node(blob, "/cpus/cpu-map/cluster1");
|
||||
cluster1_removed = true;
|
||||
}
|
||||
|
||||
/* cpu cluster2: ip_state[0]: bit6~7 */
|
||||
if ((ip_state[0] & FAIL_CPU_CLUSTER2) == FAIL_CPU_CLUSTER2) {
|
||||
log_debug("remove cpu-map cluster2\n");
|
||||
fdt_path_del_node(blob, "/cpus/cpu-map/cluster2");
|
||||
} else if (cluster1_removed) {
|
||||
/* cluster nodes must be named in a continuous series */
|
||||
log_debug("rename cpu-map cluster2\n");
|
||||
fdt_path_set_name(blob, "/cpus/cpu-map/cluster2", "cluster1");
|
||||
}
|
||||
|
||||
/* gpu: ip_state[1]: bit1~4 */
|
||||
if (ip_state[1] & FAIL_GPU) {
|
||||
log_debug("fail gpu\n");
|
||||
fdt_status_fail_by_pathf(blob, "/gpu@fb000000");
|
||||
}
|
||||
|
||||
/* rkvdec: ip_state[1]: bit6,7 */
|
||||
if (ip_state[1] & FAIL_RKVDEC0) {
|
||||
log_debug("fail rkvdec0\n");
|
||||
fdt_status_fail_by_pathf(blob, "/video-codec@fdc38000");
|
||||
fdt_status_fail_by_pathf(blob, "/iommu@fdc38700");
|
||||
}
|
||||
if (ip_state[1] & FAIL_RKVDEC1) {
|
||||
log_debug("fail rkvdec1\n");
|
||||
fdt_status_fail_by_pathf(blob, "/video-codec@fdc40000");
|
||||
fdt_status_fail_by_pathf(blob, "/iommu@fdc40700");
|
||||
}
|
||||
|
||||
/* rkvenc: ip_state[2]: bit0,2 */
|
||||
if (ip_state[2] & FAIL_RKVENC0) {
|
||||
log_debug("fail rkvenc0\n");
|
||||
fdt_status_fail_by_pathf(blob, "/video-codec@fdbd0000");
|
||||
fdt_status_fail_by_pathf(blob, "/iommu@fdbdf000");
|
||||
}
|
||||
if (ip_state[2] & FAIL_RKVENC1) {
|
||||
log_debug("fail rkvenc1\n");
|
||||
fdt_status_fail_by_pathf(blob, "/video-codec@fdbe0000");
|
||||
fdt_status_fail_by_pathf(blob, "/iommu@fdbef000");
|
||||
}
|
||||
|
||||
parent = fdt_path_offset(blob, "/cpus");
|
||||
if (parent < 0) {
|
||||
log_err("Could not find /cpus, parent=%d\n", parent);
|
||||
return parent;
|
||||
}
|
||||
|
||||
/* cpu: ip_state[0]: bit0~7 */
|
||||
for (i = 0; i < 8; i++) {
|
||||
/* fail any bad cpu core */
|
||||
if (!(ip_state[0] & BIT(i)))
|
||||
continue;
|
||||
|
||||
node = fdt_subnode_offset(blob, parent, cpu_node_names[i]);
|
||||
if (node >= 0) {
|
||||
log_debug("fail cpu %s\n", cpu_node_names[i]);
|
||||
fdt_status_fail(blob, node);
|
||||
} else {
|
||||
log_err("Could not find %s, node=%d\n",
|
||||
cpu_node_names[i], node);
|
||||
return node;
|
||||
}
|
||||
}
|
||||
|
||||
node = fdt_path_offset(blob, "/");
|
||||
if (node < 0) {
|
||||
log_err("Could not find /, node=%d\n", node);
|
||||
return node;
|
||||
}
|
||||
|
||||
snprintf(soc_comp, sizeof(soc_comp), "rockchip,rk35%x", cpu_code[1]);
|
||||
|
||||
for (i = 0, comp_len = 0;
|
||||
(comp = fdt_stringlist_get(blob, node, "compatible", i, &len));
|
||||
i++) {
|
||||
/* stop at soc compatible */
|
||||
if (!strcmp(comp, soc_comp) ||
|
||||
!strcmp(comp, "rockchip,rk3588s") ||
|
||||
!strcmp(comp, "rockchip,rk3588"))
|
||||
break;
|
||||
|
||||
log_debug("compatible[%d]: %s\n", i, comp);
|
||||
comp_len += len + 1;
|
||||
}
|
||||
|
||||
/* truncate to only include board compatible */
|
||||
fdt_setprop_placeholder(blob, node, "compatible", comp_len, &data);
|
||||
|
||||
/* append soc compatible */
|
||||
fdt_appendprop_string(blob, node, "compatible", soc_comp);
|
||||
fdt_appendprop_string(blob, node, "compatible", "rockchip,rk3588s");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -289,6 +289,11 @@ static int rockchip_dram_init_banksize(void)
|
||||
}
|
||||
#endif
|
||||
|
||||
__weak int rockchip_dram_init_banksize_fixup(struct bd_info *bd)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int dram_init_banksize(void)
|
||||
{
|
||||
size_t ram_top = (unsigned long)(gd->ram_size + CFG_SYS_SDRAM_BASE);
|
||||
@@ -342,7 +347,7 @@ int dram_init_banksize(void)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
return rockchip_dram_init_banksize_fixup(gd->bd);
|
||||
}
|
||||
|
||||
u8 rockchip_sdram_type(phys_addr_t reg)
|
||||
|
||||
@@ -3,6 +3,7 @@
|
||||
* (C) Copyright 2019 Rockchip Electronics Co., Ltd
|
||||
*/
|
||||
|
||||
#include <binman_sym.h>
|
||||
#include <cpu_func.h>
|
||||
#include <debug_uart.h>
|
||||
#include <dm.h>
|
||||
@@ -10,6 +11,7 @@
|
||||
#include <image.h>
|
||||
#include <init.h>
|
||||
#include <log.h>
|
||||
#include <mapmem.h>
|
||||
#include <ram.h>
|
||||
#include <spl.h>
|
||||
#include <asm/arch-rockchip/bootrom.h>
|
||||
@@ -33,7 +35,17 @@ __weak const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
|
||||
|
||||
__weak u32 read_brom_bootsource_id(void)
|
||||
{
|
||||
return readl(BROM_BOOTSOURCE_ID_ADDR);
|
||||
u32 bootsource_id = readl(BROM_BOOTSOURCE_ID_ADDR);
|
||||
|
||||
/* Re-map the raw value read from reg to an existing BROM_BOOTSOURCE
|
||||
* enum value to avoid having to create a larger boot_devices table.
|
||||
*/
|
||||
if (bootsource_id == 0x81)
|
||||
return BROM_BOOTSOURCE_USB;
|
||||
else if (bootsource_id > BROM_LAST_BOOTSOURCE)
|
||||
log_debug("Unknown bootsource %x\n", bootsource_id);
|
||||
|
||||
return bootsource_id;
|
||||
}
|
||||
|
||||
const char *board_spl_was_booted_from(void)
|
||||
@@ -140,3 +152,52 @@ void spl_board_prepare_for_boot(void)
|
||||
|
||||
cleanup_before_linux();
|
||||
}
|
||||
|
||||
#if CONFIG_IS_ENABLED(RAM_DEVICE) && IS_ENABLED(CONFIG_SPL_LOAD_FIT)
|
||||
binman_sym_declare_optional(ulong, payload, image_pos);
|
||||
binman_sym_declare_optional(ulong, payload, size);
|
||||
|
||||
static ulong ramboot_load_read(struct spl_load_info *load, ulong sector,
|
||||
ulong count, void *buf)
|
||||
{
|
||||
ulong addr = IF_ENABLED_INT(CONFIG_SPL_LOAD_FIT,
|
||||
CONFIG_SPL_LOAD_FIT_ADDRESS);
|
||||
|
||||
memcpy(buf, map_sysmem(addr + sector, 0), count);
|
||||
return count;
|
||||
}
|
||||
|
||||
static int ramboot_load_image(struct spl_image_info *spl_image,
|
||||
struct spl_boot_device *bootdev)
|
||||
{
|
||||
struct legacy_img_hdr *header;
|
||||
ulong addr = IF_ENABLED_INT(CONFIG_SPL_LOAD_FIT,
|
||||
CONFIG_SPL_LOAD_FIT_ADDRESS);
|
||||
ulong image_pos = binman_sym(ulong, payload, image_pos);
|
||||
ulong size = binman_sym(ulong, payload, size);
|
||||
|
||||
if (addr == CFG_SYS_SDRAM_BASE || addr == CONFIG_SPL_TEXT_BASE)
|
||||
return -ENODEV;
|
||||
|
||||
if (image_pos != BINMAN_SYM_MISSING && size != BINMAN_SYM_MISSING) {
|
||||
header = map_sysmem(image_pos, 0);
|
||||
if (image_get_magic(header) == FDT_MAGIC) {
|
||||
memmove(map_sysmem(addr, 0), header, size);
|
||||
memset(header, 0, sizeof(*header));
|
||||
}
|
||||
}
|
||||
|
||||
header = map_sysmem(addr, 0);
|
||||
if (image_get_magic(header) == FDT_MAGIC) {
|
||||
struct spl_load_info load;
|
||||
|
||||
spl_load_init(&load, ramboot_load_read, NULL, 1);
|
||||
return spl_load_simple_fit(spl_image, &load, 0, header);
|
||||
}
|
||||
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
/* Use priority and method name that sort before default spl_ram_load_image */
|
||||
SPL_LOAD_IMAGE_METHOD("RAM", 0, BOOT_DEVICE_RAM, ramboot_load_image);
|
||||
#endif
|
||||
|
||||
@@ -4,5 +4,4 @@ S: Maintained
|
||||
F: board/amarula/vyasa-rk3288
|
||||
F: include/configs/vyasa-rk3288.h
|
||||
F: configs/vyasa-rk3288_defconfig
|
||||
F: arch/arm/dts/rk3288-vyasa.dts
|
||||
F: arch/arm/dts/rk3288-vyasa-u-boot.dtsi
|
||||
|
||||
@@ -1,7 +1,6 @@
|
||||
POPMETAL-RK3288
|
||||
M: Lin Huang <hl@rock-chips.com>
|
||||
S: Maintained
|
||||
F: arch/arm/dts/rk3288-popmetal.dts
|
||||
F: arch/arm/dts/rk3288-popmetal-u-boot.dtsi
|
||||
F: board/chipspark/popmetal_rk3288
|
||||
F: include/configs/popmetal_rk3288.h
|
||||
|
||||
@@ -1,7 +1,6 @@
|
||||
CHROMEBOOK JERRY BOARD
|
||||
M: Simon Glass <sjg@chromium.org>
|
||||
S: Maintained
|
||||
F: arch/arm/dts/rk3288-veyron-jerry.dts
|
||||
F: arch/arm/dts/rk3288-veyron-jerry-u-boot.dtsi
|
||||
F: board/google/veyron/
|
||||
F: include/configs/veyron.h
|
||||
@@ -10,7 +9,6 @@ F: configs/chromebook_jerry_defconfig
|
||||
CHROMEBIT MICKEY BOARD
|
||||
M: Simon Glass <sjg@chromium.org>
|
||||
S: Maintained
|
||||
F: arch/arm/dts/rk3288-veyron-mickey.dts
|
||||
F: arch/arm/dts/rk3288-veyron-mickey-u-boot.dtsi
|
||||
F: board/google/veyron/
|
||||
F: include/configs/veyron.h
|
||||
@@ -19,7 +17,6 @@ F: configs/chromebit_mickey_defconfig
|
||||
CHROMEBOOK MINNIE BOARD
|
||||
M: Simon Glass <sjg@chromium.org>
|
||||
S: Maintained
|
||||
F: arch/arm/dts/rk3288-veyron-minnie.dts
|
||||
F: arch/arm/dts/rk3288-veyron-minnie-u-boot.dtsi
|
||||
F: board/google/veyron/
|
||||
F: include/configs/veyron.h
|
||||
@@ -28,7 +25,6 @@ F: configs/chromebook_minnie_defconfig
|
||||
CHROMEBOOK SPEEDY BOARD
|
||||
M: Simon Glass <sjg@chromium.org>
|
||||
S: Maintained
|
||||
F: arch/arm/dts/rk3288-veyron-speedy.dts
|
||||
F: arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi
|
||||
F: board/google/veyron/
|
||||
F: include/configs/veyron.h
|
||||
@@ -37,8 +33,4 @@ F: configs/chromebook_speedy_defconfig
|
||||
CHROMEBOOK VEYRON COMMON FILES
|
||||
M: Simon Glass <sjg@chromium.org>
|
||||
S: Maintained
|
||||
F: arch/arm/dts/rk3288-veyron.dtsi
|
||||
F: arch/arm/dts/rk3288-veyron-analog-audio.dtsi
|
||||
F: arch/arm/dts/rk3288-veyron-broadcom-bluetooth.dtsi
|
||||
F: arch/arm/dts/rk3288-veyron-chromebook.dtsi
|
||||
F: arch/arm/dts/rk3288-veyron-edp.dtsi
|
||||
F: arch/arm/dts/rk3288-veyron-u-boot.dtsi
|
||||
|
||||
@@ -1,12 +1,10 @@
|
||||
EVB-RK3288
|
||||
M: Lin Huang <hl@rock-chips.com>
|
||||
S: Maintained
|
||||
F: arch/arm/dts/rk3288-evb.dts
|
||||
F: arch/arm/dts/rk3288-evb.dtsi
|
||||
F: arch/arm/dts/rk3288-evb-u-boot.dtsi
|
||||
F: arch/arm/dts/rk3288-evb-rk808-u-boot.dtsi
|
||||
F: board/rockchip/evb_rk3288
|
||||
F: include/configs/evb_rk3288.h
|
||||
F: configs/evb-rk3288_defconfig
|
||||
F: configs/evb-rk3288-rk808_defconfig
|
||||
|
||||
ROCK-PI-N8
|
||||
M: Jagan Teki <jagan@amarulasolutions.com>
|
||||
|
||||
@@ -8,7 +8,7 @@ CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000
|
||||
CONFIG_SF_DEFAULT_SPEED=20000000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-mickey"
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3288-veyron-mickey"
|
||||
CONFIG_DM_RESET=y
|
||||
CONFIG_SYS_MONITOR_LEN=614400
|
||||
CONFIG_ROCKCHIP_RK3288=y
|
||||
@@ -29,7 +29,7 @@ CONFIG_SPL_SPI=y
|
||||
CONFIG_SPL_PAYLOAD="u-boot.img"
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_USE_PREBOOT=y
|
||||
CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-mickey.dtb"
|
||||
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3288-veyron-mickey.dtb"
|
||||
CONFIG_SILENT_CONSOLE=y
|
||||
CONFIG_LOG=y
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
|
||||
@@ -8,7 +8,7 @@ CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000
|
||||
CONFIG_SF_DEFAULT_SPEED=20000000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-jerry"
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3288-veyron-jerry"
|
||||
CONFIG_DM_RESET=y
|
||||
CONFIG_SYS_MONITOR_LEN=614400
|
||||
CONFIG_ROCKCHIP_RK3288=y
|
||||
@@ -28,7 +28,7 @@ CONFIG_SPL_SPI=y
|
||||
CONFIG_SPL_PAYLOAD="u-boot.img"
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_USE_PREBOOT=y
|
||||
CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-jerry.dtb"
|
||||
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3288-veyron-jerry.dtb"
|
||||
CONFIG_SILENT_CONSOLE=y
|
||||
CONFIG_LOG=y
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
|
||||
@@ -8,7 +8,7 @@ CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000
|
||||
CONFIG_SF_DEFAULT_SPEED=20000000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-minnie"
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3288-veyron-minnie"
|
||||
CONFIG_DM_RESET=y
|
||||
CONFIG_SYS_MONITOR_LEN=614400
|
||||
CONFIG_ROCKCHIP_RK3288=y
|
||||
@@ -29,7 +29,7 @@ CONFIG_SPL_SPI=y
|
||||
CONFIG_SPL_PAYLOAD="u-boot.img"
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_USE_PREBOOT=y
|
||||
CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-minnie.dtb"
|
||||
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3288-veyron-minnie.dtb"
|
||||
CONFIG_SILENT_CONSOLE=y
|
||||
CONFIG_LOG=y
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
|
||||
@@ -8,7 +8,7 @@ CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000
|
||||
CONFIG_SF_DEFAULT_SPEED=20000000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-speedy"
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3288-veyron-speedy"
|
||||
CONFIG_DM_RESET=y
|
||||
CONFIG_SYS_MONITOR_LEN=614400
|
||||
CONFIG_ROCKCHIP_RK3288=y
|
||||
@@ -29,7 +29,7 @@ CONFIG_SPL_SPI=y
|
||||
CONFIG_SPL_PAYLOAD="u-boot.img"
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_USE_PREBOOT=y
|
||||
CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-speedy.dtb"
|
||||
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3288-veyron-speedy.dtb"
|
||||
CONFIG_SILENT_CONSOLE=y
|
||||
CONFIG_LOG=y
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
|
||||
@@ -9,7 +9,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000
|
||||
CONFIG_SF_DEFAULT_SPEED=20000000
|
||||
CONFIG_ENV_OFFSET=0x3F8000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rk3288-evb"
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3288-evb-rk808"
|
||||
CONFIG_DM_RESET=y
|
||||
CONFIG_SYS_MONITOR_LEN=614400
|
||||
CONFIG_ROCKCHIP_RK3288=y
|
||||
@@ -29,7 +29,7 @@ CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
CONFIG_USE_PREBOOT=y
|
||||
CONFIG_DEFAULT_FDT_FILE="rk3288-evb-rk808.dtb"
|
||||
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3288-evb-rk808.dtb"
|
||||
CONFIG_SILENT_CONSOLE=y
|
||||
CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
CONFIG_SPL_NO_BSS_LIMIT=y
|
||||
@@ -42,7 +42,6 @@ CONFIG_CMD_REGULATOR=y
|
||||
# CONFIG_SPL_EFI_PARTITION is not set
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_OF_LIVE=y
|
||||
CONFIG_OF_UPSTREAM=y
|
||||
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_ENV_RELOC_GD_ENV_ADDR=y
|
||||
|
||||
@@ -16,6 +16,7 @@ CONFIG_SPL_FIT_SIGNATURE=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
# CONFIG_BOOTMETH_VBE is not set
|
||||
CONFIG_LEGACY_IMAGE_FORMAT=y
|
||||
CONFIG_OF_SYSTEM_SETUP=y
|
||||
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-generic.dtb"
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_SPL_MAX_SIZE=0x40000
|
||||
|
||||
@@ -41,7 +41,6 @@ CONFIG_CMD_REGULATOR=y
|
||||
# CONFIG_SPL_EFI_PARTITION is not set
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_OF_LIVE=y
|
||||
CONFIG_OF_UPSTREAM=y
|
||||
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_ENV_RELOC_GD_ENV_ADDR=y
|
||||
|
||||
64
configs/nanopi-zero2-rk3528_defconfig
Normal file
64
configs/nanopi-zero2-rk3528_defconfig
Normal file
@@ -0,0 +1,64 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
CONFIG_COUNTER_FREQUENCY=24000000
|
||||
CONFIG_ARCH_ROCKCHIP=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3528-nanopi-zero2"
|
||||
CONFIG_ROCKCHIP_RK3528=y
|
||||
CONFIG_SYS_LOAD_ADDR=0xc00800
|
||||
CONFIG_DEBUG_UART_BASE=0xFF9F0000
|
||||
CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3528-nanopi-zero2.dtb"
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_BOARD_RNG_SEED=y
|
||||
CONFIG_SPL_MAX_SIZE=0x40000
|
||||
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
CONFIG_CMD_MEMINFO=y
|
||||
CONFIG_CMD_MEMINFO_MAP=y
|
||||
CONFIG_CMD_ADC=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_GPT=y
|
||||
CONFIG_CMD_MISC=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_ROCKUSB=y
|
||||
CONFIG_CMD_USB_MASS_STORAGE=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_RNG=y
|
||||
CONFIG_CMD_REGULATOR=y
|
||||
# CONFIG_SPL_DOS_PARTITION is not set
|
||||
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
CONFIG_BUTTON=y
|
||||
CONFIG_BUTTON_ADC=y
|
||||
# CONFIG_USB_FUNCTION_FASTBOOT is not set
|
||||
CONFIG_ROCKCHIP_GPIO=y
|
||||
CONFIG_LED=y
|
||||
CONFIG_LED_GPIO=y
|
||||
CONFIG_SUPPORT_EMMC_RPMB=y
|
||||
CONFIG_MMC_DW=y
|
||||
CONFIG_MMC_DW_ROCKCHIP=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_SDMA=y
|
||||
CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_DM_MDIO=y
|
||||
CONFIG_DWC_ETH_QOS=y
|
||||
CONFIG_DWC_ETH_QOS_ROCKCHIP=y
|
||||
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
||||
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
|
||||
CONFIG_REGULATOR_PWM=y
|
||||
CONFIG_DM_REGULATOR_GPIO=y
|
||||
CONFIG_PWM_ROCKCHIP=y
|
||||
CONFIG_BAUDRATE=1500000
|
||||
CONFIG_DEBUG_UART_SHIFT=2
|
||||
CONFIG_SYS_NS16550_MEM32=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_GENERIC=y
|
||||
CONFIG_USB_DWC3=y
|
||||
CONFIG_USB_DWC3_GENERIC=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_GADGET_DOWNLOAD=y
|
||||
CONFIG_USB_FUNCTION_ROCKUSB=y
|
||||
CONFIG_ERRNO_STR=y
|
||||
@@ -26,7 +26,7 @@ CONFIG_DEBUG_UART=y
|
||||
CONFIG_LTO=y
|
||||
# CONFIG_ANDROID_BOOT_IMAGE is not set
|
||||
CONFIG_USE_PREBOOT=y
|
||||
CONFIG_DEFAULT_FDT_FILE="rk3288-phycore-rdk.dtb"
|
||||
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3288-phycore-rdk.dtb"
|
||||
CONFIG_SILENT_CONSOLE=y
|
||||
CONFIG_CONSOLE_MUX=y
|
||||
CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
@@ -48,7 +48,6 @@ CONFIG_CMD_REGULATOR=y
|
||||
# CONFIG_SPL_DOS_PARTITION is not set
|
||||
# CONFIG_SPL_EFI_PARTITION is not set
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_OF_UPSTREAM=y
|
||||
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_ENV_RELOC_GD_ENV_ADDR=y
|
||||
|
||||
@@ -8,7 +8,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000
|
||||
CONFIG_SF_DEFAULT_SPEED=20000000
|
||||
CONFIG_ENV_OFFSET=0x3F8000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rk3288-popmetal"
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3288-popmetal"
|
||||
CONFIG_SYS_MONITOR_LEN=614400
|
||||
CONFIG_ROCKCHIP_RK3288=y
|
||||
CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
|
||||
@@ -25,7 +25,7 @@ CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
CONFIG_DEBUG_UART=y
|
||||
# CONFIG_ANDROID_BOOT_IMAGE is not set
|
||||
CONFIG_USE_PREBOOT=y
|
||||
CONFIG_DEFAULT_FDT_FILE="rk3288-popmetal.dtb"
|
||||
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3288-popmetal.dtb"
|
||||
CONFIG_SILENT_CONSOLE=y
|
||||
CONFIG_CONSOLE_MUX=y
|
||||
CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
|
||||
@@ -18,6 +18,7 @@ CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_SPL_FIT_SIGNATURE=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
CONFIG_LEGACY_IMAGE_FORMAT=y
|
||||
CONFIG_OF_SYSTEM_SETUP=y
|
||||
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-rock-5c.dtb"
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_SPL_MAX_SIZE=0x40000
|
||||
|
||||
@@ -10,7 +10,7 @@ CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000
|
||||
CONFIG_ENV_OFFSET=0x3F8000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rk3288-rock-pi-n8"
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3288-rock-pi-n8"
|
||||
CONFIG_DM_RESET=y
|
||||
CONFIG_SYS_MONITOR_LEN=614400
|
||||
CONFIG_ROCKCHIP_RK3288=y
|
||||
|
||||
@@ -8,7 +8,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000
|
||||
CONFIG_SF_DEFAULT_SPEED=20000000
|
||||
CONFIG_ENV_OFFSET=0x3F8000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rk3288-rock2-square"
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3288-rock2-square"
|
||||
CONFIG_SYS_MONITOR_LEN=614400
|
||||
CONFIG_ROCKCHIP_RK3288=y
|
||||
CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
|
||||
@@ -25,7 +25,7 @@ CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
CONFIG_DEBUG_UART=y
|
||||
# CONFIG_ANDROID_BOOT_IMAGE is not set
|
||||
CONFIG_USE_PREBOOT=y
|
||||
CONFIG_DEFAULT_FDT_FILE="rk3288-rock2-square.dtb"
|
||||
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3288-rock2-square.dtb"
|
||||
CONFIG_SILENT_CONSOLE=y
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
|
||||
@@ -75,10 +75,6 @@ CONFIG_MMC_IO_VOLTAGE=y
|
||||
CONFIG_SPL_MMC_IO_VOLTAGE=y
|
||||
CONFIG_MMC_UHS_SUPPORT=y
|
||||
CONFIG_SPL_MMC_UHS_SUPPORT=y
|
||||
CONFIG_MMC_HS400_ES_SUPPORT=y
|
||||
CONFIG_SPL_MMC_HS400_ES_SUPPORT=y
|
||||
CONFIG_MMC_HS400_SUPPORT=y
|
||||
CONFIG_SPL_MMC_HS400_SUPPORT=y
|
||||
CONFIG_MMC_DW=y
|
||||
CONFIG_MMC_DW_ROCKCHIP=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
|
||||
@@ -42,7 +42,6 @@ CONFIG_CMD_REGULATOR=y
|
||||
# CONFIG_SPL_EFI_PARTITION is not set
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_OF_LIVE=y
|
||||
CONFIG_OF_UPSTREAM=y
|
||||
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_ENV_RELOC_GD_ENV_ADDR=y
|
||||
|
||||
@@ -42,7 +42,6 @@ CONFIG_CMD_REGULATOR=y
|
||||
# CONFIG_SPL_EFI_PARTITION is not set
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_OF_LIVE=y
|
||||
CONFIG_OF_UPSTREAM=y
|
||||
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_ENV_RELOC_GD_ENV_ADDR=y
|
||||
|
||||
@@ -11,7 +11,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000
|
||||
CONFIG_SF_DEFAULT_SPEED=20000000
|
||||
CONFIG_ENV_OFFSET=0x3F8000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rk3288-vyasa"
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3288-vyasa"
|
||||
CONFIG_DM_RESET=y
|
||||
CONFIG_SYS_MONITOR_LEN=614400
|
||||
CONFIG_ROCKCHIP_RK3288=y
|
||||
@@ -26,7 +26,7 @@ CONFIG_DEBUG_UART_BASE=0xff690000
|
||||
CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_USE_PREBOOT=y
|
||||
CONFIG_DEFAULT_FDT_FILE="rk3288-vyasa.dtb"
|
||||
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3288-vyasa.dtb"
|
||||
CONFIG_SILENT_CONSOLE=y
|
||||
CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
CONFIG_SPL_NO_BSS_LIMIT=y
|
||||
|
||||
@@ -40,15 +40,17 @@ List of mainline supported Rockchip boards:
|
||||
* rk3229
|
||||
- Rockchip Evb-RK3229 (evb-rk3229)
|
||||
* rk3288
|
||||
- Rockchip Evb-RK3288 (evb-rk3288)
|
||||
- Rockchip Evb-RK3288-rk808 (evb-rk3288-rk808)
|
||||
- Firefly-RK3288 (firefly-rk3288)
|
||||
- MQmaker MiQi (miqi-rk3288)
|
||||
- Phytec RK3288 PCM-947 (phycore-rk3288)
|
||||
- PopMetal-RK3288 (popmetal-rk3288)
|
||||
- Radxa Rock 2 Square (rock2)
|
||||
- Radxa Rock Pi N8 (rock-pi-n8-rk3288)
|
||||
- Tinker-RK3288 (tinker-rk3288)
|
||||
- Tinker-S-RK3288 (tinker-s-rk3288)
|
||||
- Google Jerry (chromebook_jerry)
|
||||
- Google Mickey (chromebook_mickey)
|
||||
- Google Mickey (chromebit_mickey)
|
||||
- Google Minnie (chromebook_minnie)
|
||||
- Google Speedy (chromebook_speedy)
|
||||
- Amarula Vyasa-RK3288 (vyasa-rk3288)
|
||||
@@ -101,6 +103,7 @@ List of mainline supported Rockchip boards:
|
||||
|
||||
* rk3528
|
||||
- ArmSoM Sige1 (sige1-rk3528)
|
||||
- FriendlyElec NanoPi Zero2 (nanopi-zero2-rk3528)
|
||||
- Generic RK3528 (generic-rk3528)
|
||||
- Radxa E20C (radxa-e20c-rk3528)
|
||||
- Radxa ROCK 2A/2F (rock-2-rk3528)
|
||||
@@ -154,7 +157,7 @@ List of mainline supported Rockchip boards:
|
||||
- FriendlyElec NanoPi R6C (nanopi-r6c-rk3588s)
|
||||
- FriendlyElec NanoPi R6S (nanopi-r6s-rk3588s)
|
||||
- GameForce Ace (gameforce-ace-rk3588s)
|
||||
- Generic RK3588S/RK3588 (generic-rk3588)
|
||||
- Generic RK3582/RK3588S/RK3588 (generic-rk3588)
|
||||
- Hardkernel ODROID-M2 (odroid-m2-rk3588s)
|
||||
- Indiedroid Nova (nova-rk3588s)
|
||||
- Khadas Edge2 (khadas-edge2-rk3588s)
|
||||
@@ -163,7 +166,7 @@ List of mainline supported Rockchip boards:
|
||||
- Radxa ROCK 5 ITX (rock-5-itx-rk3588)
|
||||
- Radxa ROCK 5A (rock5a-rk3588s)
|
||||
- Radxa ROCK 5B/5B+/5T (rock5b-rk3588)
|
||||
- Radxa ROCK 5C (rock-5c-rk3588s)
|
||||
- Radxa ROCK 5C/5C Lite (rock-5c-rk3588s)
|
||||
- Rockchip Toybrick TB-RK3588X (toybrick-rk3588)
|
||||
- Theobroma Systems RK3588-SBC Jaguar (jaguar-rk3588)
|
||||
- Theobroma Systems SOM-RK3588-Q7 - Tiger (tiger-rk3588)
|
||||
@@ -244,7 +247,7 @@ To build rk3288 boards:
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
make evb-rk3288_defconfig
|
||||
make evb-rk3288-mk808_defconfig
|
||||
make CROSS_COMPILE=arm-linux-gnueabihf-
|
||||
|
||||
To build rk3308 boards:
|
||||
|
||||
@@ -15,6 +15,7 @@ obj-$(CONFIG_ROCKCHIP_RK3308) += clk_rk3308.o
|
||||
obj-$(CONFIG_ROCKCHIP_RK3328) += clk_rk3328.o
|
||||
obj-$(CONFIG_ROCKCHIP_RK3368) += clk_rk3368.o
|
||||
obj-$(CONFIG_ROCKCHIP_RK3399) += clk_rk3399.o
|
||||
obj-$(CONFIG_ROCKCHIP_RK3506) += clk_rk3506.o
|
||||
obj-$(CONFIG_ROCKCHIP_RK3528) += clk_rk3528.o
|
||||
obj-$(CONFIG_ROCKCHIP_RK3568) += clk_rk3568.o
|
||||
obj-$(CONFIG_ROCKCHIP_RK3576) += clk_rk3576.o
|
||||
|
||||
1166
drivers/clk/rockchip/clk_rk3506.c
Normal file
1166
drivers/clk/rockchip/clk_rk3506.c
Normal file
File diff suppressed because it is too large
Load Diff
@@ -390,6 +390,10 @@ static const struct udevice_id rockchip_otp_ids[] = {
|
||||
.compatible = "rockchip,rk3308-otp",
|
||||
.data = (ulong)&px30_data,
|
||||
},
|
||||
{
|
||||
.compatible = "rockchip,rk3506-otp",
|
||||
.data = (ulong)&rk3568_data,
|
||||
},
|
||||
{
|
||||
.compatible = "rockchip,rk3528-otp",
|
||||
.data = (ulong)&rk3568_data,
|
||||
|
||||
@@ -1620,6 +1620,10 @@ static const struct udevice_id eqos_ids[] = {
|
||||
},
|
||||
#endif
|
||||
#if IS_ENABLED(CONFIG_DWC_ETH_QOS_ROCKCHIP)
|
||||
{
|
||||
.compatible = "rockchip,rk3506-gmac",
|
||||
.data = (ulong)&eqos_rockchip_config
|
||||
},
|
||||
{
|
||||
.compatible = "rockchip,rk3528-gmac",
|
||||
.data = (ulong)&eqos_rockchip_config
|
||||
|
||||
@@ -50,6 +50,80 @@ struct rockchip_platform_data {
|
||||
(((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \
|
||||
((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE))
|
||||
|
||||
#define RK3506_GRF_SOC_CON8 0x0020
|
||||
#define RK3506_GRF_SOC_CON11 0x002c
|
||||
|
||||
#define RK3506_GMAC_RMII_MODE GRF_BIT(1)
|
||||
|
||||
#define RK3506_GMAC_CLK_RMII_DIV2 GRF_BIT(3)
|
||||
#define RK3506_GMAC_CLK_RMII_DIV20 GRF_CLR_BIT(3)
|
||||
|
||||
#define RK3506_GMAC_CLK_SELECT_CRU GRF_CLR_BIT(5)
|
||||
#define RK3506_GMAC_CLK_SELECT_IO GRF_BIT(5)
|
||||
|
||||
#define RK3506_GMAC_CLK_RMII_GATE GRF_BIT(2)
|
||||
#define RK3506_GMAC_CLK_RMII_NOGATE GRF_CLR_BIT(2)
|
||||
|
||||
static int rk3506_set_to_rgmii(struct udevice *dev,
|
||||
int tx_delay, int rx_delay)
|
||||
{
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static int rk3506_set_to_rmii(struct udevice *dev)
|
||||
{
|
||||
struct eth_pdata *pdata = dev_get_plat(dev);
|
||||
struct rockchip_platform_data *data = pdata->priv_pdata;
|
||||
u32 reg;
|
||||
|
||||
reg = data->id == 1 ? RK3506_GRF_SOC_CON11 :
|
||||
RK3506_GRF_SOC_CON8;
|
||||
regmap_write(data->grf, reg, RK3506_GMAC_RMII_MODE);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rk3506_set_gmac_speed(struct udevice *dev)
|
||||
{
|
||||
struct eqos_priv *eqos = dev_get_priv(dev);
|
||||
struct eth_pdata *pdata = dev_get_plat(dev);
|
||||
struct rockchip_platform_data *data = pdata->priv_pdata;
|
||||
u32 val, reg;
|
||||
|
||||
switch (eqos->phy->speed) {
|
||||
case SPEED_10:
|
||||
val = RK3506_GMAC_CLK_RMII_DIV20;
|
||||
break;
|
||||
case SPEED_100:
|
||||
val = RK3506_GMAC_CLK_RMII_DIV2;
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
reg = data->id == 1 ? RK3506_GRF_SOC_CON11 :
|
||||
RK3506_GRF_SOC_CON8;
|
||||
regmap_write(data->grf, reg, val);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void rk3506_set_clock_selection(struct udevice *dev, bool enable)
|
||||
{
|
||||
struct eth_pdata *pdata = dev_get_plat(dev);
|
||||
struct rockchip_platform_data *data = pdata->priv_pdata;
|
||||
u32 val, reg;
|
||||
|
||||
val = data->clock_input ? RK3506_GMAC_CLK_SELECT_IO :
|
||||
RK3506_GMAC_CLK_SELECT_CRU;
|
||||
val |= enable ? RK3506_GMAC_CLK_RMII_NOGATE :
|
||||
RK3506_GMAC_CLK_RMII_GATE;
|
||||
|
||||
reg = data->id == 1 ? RK3506_GRF_SOC_CON11 :
|
||||
RK3506_GRF_SOC_CON8;
|
||||
regmap_write(data->grf, reg, val);
|
||||
}
|
||||
|
||||
#define RK3528_VO_GRF_GMAC_CON 0x0018
|
||||
#define RK3528_VPU_GRF_GMAC_CON5 0x0018
|
||||
#define RK3528_VPU_GRF_GMAC_CON6 0x001c
|
||||
@@ -534,6 +608,18 @@ static void rk3588_set_clock_selection(struct udevice *dev, bool enable)
|
||||
}
|
||||
|
||||
static const struct rk_gmac_ops rk_gmac_ops[] = {
|
||||
{
|
||||
.compatible = "rockchip,rk3506-gmac",
|
||||
.set_to_rgmii = rk3506_set_to_rgmii,
|
||||
.set_to_rmii = rk3506_set_to_rmii,
|
||||
.set_gmac_speed = rk3506_set_gmac_speed,
|
||||
.set_clock_selection = rk3506_set_clock_selection,
|
||||
.regs = {
|
||||
0xff4c8000, /* gmac0 */
|
||||
0xff4d0000, /* gmac1 */
|
||||
0x0, /* sentinel */
|
||||
},
|
||||
},
|
||||
{
|
||||
.compatible = "rockchip,rk3528-gmac",
|
||||
.set_to_rgmii = rk3528_set_to_rgmii,
|
||||
|
||||
@@ -421,6 +421,22 @@ static const struct rockchip_usb2phy_cfg rk3399_usb2phy_cfgs[] = {
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static const struct rockchip_usb2phy_cfg rk3506_phy_cfgs[] = {
|
||||
{
|
||||
.reg = 0xff2b0000,
|
||||
.clkout_ctl_phy = { 0x041c, 7, 2, 0, 0x27 },
|
||||
.port_cfgs = {
|
||||
[USB2PHY_PORT_OTG] = {
|
||||
.phy_sus = { 0x0060, 1, 0, 2, 1 },
|
||||
},
|
||||
[USB2PHY_PORT_HOST] = {
|
||||
.phy_sus = { 0x0070, 1, 0, 2, 1 },
|
||||
}
|
||||
},
|
||||
},
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static const struct rockchip_usb2phy_cfg rk3528_phy_cfgs[] = {
|
||||
{
|
||||
.reg = 0xffdf0000,
|
||||
@@ -540,6 +556,10 @@ static const struct udevice_id rockchip_usb2phy_ids[] = {
|
||||
.compatible = "rockchip,rk3399-usb2phy",
|
||||
.data = (ulong)&rk3399_usb2phy_cfgs,
|
||||
},
|
||||
{
|
||||
.compatible = "rockchip,rk3506-usb2phy",
|
||||
.data = (ulong)&rk3506_phy_cfgs,
|
||||
},
|
||||
{
|
||||
.compatible = "rockchip,rk3528-usb2phy",
|
||||
.data = (ulong)&rk3528_phy_cfgs,
|
||||
|
||||
@@ -399,6 +399,14 @@ static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
|
||||
param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
|
||||
param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
|
||||
param_write(priv->phy_grf, &cfg->usb_mode_set, true);
|
||||
switch (priv->id) {
|
||||
case 0:
|
||||
param_write(priv->pipe_grf, &cfg->u3otg0_port_en, true);
|
||||
break;
|
||||
case 1:
|
||||
param_write(priv->pipe_grf, &cfg->u3otg1_port_en, true);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case PHY_TYPE_SATA:
|
||||
writel(0x41, priv->mmio + 0x38);
|
||||
|
||||
@@ -14,6 +14,7 @@ obj-$(CONFIG_ROCKCHIP_RK3308) += pinctrl-rk3308.o
|
||||
obj-$(CONFIG_ROCKCHIP_RK3328) += pinctrl-rk3328.o
|
||||
obj-$(CONFIG_ROCKCHIP_RK3368) += pinctrl-rk3368.o
|
||||
obj-$(CONFIG_ROCKCHIP_RK3399) += pinctrl-rk3399.o
|
||||
obj-$(CONFIG_ROCKCHIP_RK3506) += pinctrl-rk3506.o
|
||||
obj-$(CONFIG_ROCKCHIP_RK3528) += pinctrl-rk3528.o
|
||||
obj-$(CONFIG_ROCKCHIP_RK3568) += pinctrl-rk3568.o
|
||||
obj-$(CONFIG_ROCKCHIP_RK3576) += pinctrl-rk3576.o
|
||||
|
||||
462
drivers/pinctrl/rockchip/pinctrl-rk3506.c
Normal file
462
drivers/pinctrl/rockchip/pinctrl-rk3506.c
Normal file
@@ -0,0 +1,462 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
/*
|
||||
* Copyright (c) 2024 Rockchip Electronics Co., Ltd.
|
||||
*/
|
||||
|
||||
#include <dm.h>
|
||||
#include <dm/pinctrl.h>
|
||||
#include <regmap.h>
|
||||
#include <syscon.h>
|
||||
|
||||
#include "pinctrl-rockchip.h"
|
||||
#include <dt-bindings/pinctrl/rockchip.h>
|
||||
|
||||
static int rk3506_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
|
||||
{
|
||||
struct rockchip_pinctrl_priv *priv = bank->priv;
|
||||
int iomux_num = (pin / 8);
|
||||
struct regmap *regmap;
|
||||
int reg, mask;
|
||||
u8 bit;
|
||||
u32 data, rmask;
|
||||
|
||||
if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
|
||||
regmap = priv->regmap_pmu;
|
||||
else
|
||||
regmap = priv->regmap_base;
|
||||
|
||||
if (bank->bank_num == 1)
|
||||
regmap = priv->regmap_ioc1;
|
||||
else if (bank->bank_num == 4)
|
||||
return 0;
|
||||
|
||||
reg = bank->iomux[iomux_num].offset;
|
||||
if ((pin % 8) >= 4)
|
||||
reg += 0x4;
|
||||
bit = (pin % 4) * 4;
|
||||
mask = 0xf;
|
||||
|
||||
if (bank->recalced_mask & BIT(pin))
|
||||
rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
|
||||
|
||||
data = (mask << (bit + 16));
|
||||
rmask = data | (data >> 16);
|
||||
data |= (mux & mask) << bit;
|
||||
|
||||
return regmap_update_bits(regmap, reg, rmask, data);
|
||||
}
|
||||
|
||||
#define RK3506_DRV_BITS_PER_PIN 8
|
||||
#define RK3506_DRV_PINS_PER_REG 2
|
||||
#define RK3506_DRV_GPIO0_A_OFFSET 0x100
|
||||
#define RK3506_DRV_GPIO0_D_OFFSET 0x830
|
||||
#define RK3506_DRV_GPIO1_OFFSET 0x140
|
||||
#define RK3506_DRV_GPIO2_OFFSET 0x180
|
||||
#define RK3506_DRV_GPIO3_OFFSET 0x1c0
|
||||
#define RK3506_DRV_GPIO4_OFFSET 0x840
|
||||
|
||||
static int rk3506_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
|
||||
int pin_num, struct regmap **regmap,
|
||||
int *reg, u8 *bit)
|
||||
{
|
||||
struct rockchip_pinctrl_priv *priv = bank->priv;
|
||||
int ret = 0;
|
||||
|
||||
switch (bank->bank_num) {
|
||||
case 0:
|
||||
*regmap = priv->regmap_pmu;
|
||||
if (pin_num > 24) {
|
||||
ret = -EINVAL;
|
||||
} else if (pin_num < 24) {
|
||||
*reg = RK3506_DRV_GPIO0_A_OFFSET;
|
||||
} else {
|
||||
*reg = RK3506_DRV_GPIO0_D_OFFSET;
|
||||
*bit = 3;
|
||||
|
||||
return 0;
|
||||
}
|
||||
break;
|
||||
|
||||
case 1:
|
||||
*regmap = priv->regmap_ioc1;
|
||||
if (pin_num < 28)
|
||||
*reg = RK3506_DRV_GPIO1_OFFSET;
|
||||
else
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
|
||||
case 2:
|
||||
*regmap = priv->regmap_base;
|
||||
if (pin_num < 17)
|
||||
*reg = RK3506_DRV_GPIO2_OFFSET;
|
||||
else
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
|
||||
case 3:
|
||||
*regmap = priv->regmap_base;
|
||||
if (pin_num < 15)
|
||||
*reg = RK3506_DRV_GPIO3_OFFSET;
|
||||
else
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
|
||||
case 4:
|
||||
*regmap = priv->regmap_base;
|
||||
if (pin_num < 8 || pin_num > 11) {
|
||||
ret = -EINVAL;
|
||||
} else {
|
||||
*reg = RK3506_DRV_GPIO4_OFFSET;
|
||||
*bit = 10;
|
||||
|
||||
return 0;
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
}
|
||||
|
||||
if (ret) {
|
||||
debug("unsupported bank_num %d pin_num %d\n", bank->bank_num, pin_num);
|
||||
return ret;
|
||||
}
|
||||
|
||||
*reg += ((pin_num / RK3506_DRV_PINS_PER_REG) * 4);
|
||||
*bit = pin_num % RK3506_DRV_PINS_PER_REG;
|
||||
*bit *= RK3506_DRV_BITS_PER_PIN;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rk3506_set_drive(struct rockchip_pin_bank *bank,
|
||||
int pin_num, int strength)
|
||||
{
|
||||
struct regmap *regmap;
|
||||
int reg, ret, i;
|
||||
u32 data, rmask;
|
||||
u8 bit;
|
||||
int rmask_bits = RK3506_DRV_BITS_PER_PIN;
|
||||
|
||||
ret = rk3506_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
for (i = 0, ret = 1; i < strength; i++)
|
||||
ret = (ret << 1) | 1;
|
||||
|
||||
if ((bank->bank_num == 0 && pin_num == 24) || bank->bank_num == 4) {
|
||||
rmask_bits = 2;
|
||||
ret = strength;
|
||||
}
|
||||
|
||||
/* enable the write to the equivalent lower bits */
|
||||
data = ((1 << rmask_bits) - 1) << (bit + 16);
|
||||
rmask = data | (data >> 16);
|
||||
data |= (ret << bit);
|
||||
|
||||
return regmap_update_bits(regmap, reg, rmask, data);
|
||||
}
|
||||
|
||||
#define RK3506_PULL_BITS_PER_PIN 2
|
||||
#define RK3506_PULL_PINS_PER_REG 8
|
||||
#define RK3506_PULL_GPIO0_A_OFFSET 0x200
|
||||
#define RK3506_PULL_GPIO0_D_OFFSET 0x830
|
||||
#define RK3506_PULL_GPIO1_OFFSET 0x210
|
||||
#define RK3506_PULL_GPIO2_OFFSET 0x220
|
||||
#define RK3506_PULL_GPIO3_OFFSET 0x230
|
||||
#define RK3506_PULL_GPIO4_OFFSET 0x840
|
||||
|
||||
static int rk3506_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
|
||||
int pin_num, struct regmap **regmap,
|
||||
int *reg, u8 *bit)
|
||||
{
|
||||
struct rockchip_pinctrl_priv *priv = bank->priv;
|
||||
int ret = 0;
|
||||
|
||||
switch (bank->bank_num) {
|
||||
case 0:
|
||||
*regmap = priv->regmap_pmu;
|
||||
if (pin_num > 24) {
|
||||
ret = -EINVAL;
|
||||
} else if (pin_num < 24) {
|
||||
*reg = RK3506_PULL_GPIO0_A_OFFSET;
|
||||
} else {
|
||||
*reg = RK3506_PULL_GPIO0_D_OFFSET;
|
||||
*bit = 5;
|
||||
|
||||
return 0;
|
||||
}
|
||||
break;
|
||||
|
||||
case 1:
|
||||
*regmap = priv->regmap_ioc1;
|
||||
if (pin_num < 28)
|
||||
*reg = RK3506_PULL_GPIO1_OFFSET;
|
||||
else
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
|
||||
case 2:
|
||||
*regmap = priv->regmap_base;
|
||||
if (pin_num < 17)
|
||||
*reg = RK3506_PULL_GPIO2_OFFSET;
|
||||
else
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
|
||||
case 3:
|
||||
*regmap = priv->regmap_base;
|
||||
if (pin_num < 15)
|
||||
*reg = RK3506_PULL_GPIO3_OFFSET;
|
||||
else
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
|
||||
case 4:
|
||||
*regmap = priv->regmap_base;
|
||||
if (pin_num < 8 || pin_num > 11) {
|
||||
ret = -EINVAL;
|
||||
} else {
|
||||
*reg = RK3506_PULL_GPIO4_OFFSET;
|
||||
*bit = 13;
|
||||
|
||||
return 0;
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
}
|
||||
|
||||
if (ret) {
|
||||
debug("unsupported bank_num %d pin_num %d\n", bank->bank_num, pin_num);
|
||||
return ret;
|
||||
}
|
||||
|
||||
*reg += ((pin_num / RK3506_PULL_PINS_PER_REG) * 4);
|
||||
*bit = pin_num % RK3506_PULL_PINS_PER_REG;
|
||||
*bit *= RK3506_PULL_BITS_PER_PIN;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rk3506_set_pull(struct rockchip_pin_bank *bank,
|
||||
int pin_num, int pull)
|
||||
{
|
||||
struct regmap *regmap;
|
||||
int reg, ret;
|
||||
u8 bit, type;
|
||||
u32 data, rmask;
|
||||
|
||||
if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
|
||||
return -EOPNOTSUPP;
|
||||
|
||||
ret = rk3506_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit);
|
||||
if (ret)
|
||||
return ret;
|
||||
type = bank->pull_type[pin_num / 8];
|
||||
|
||||
if ((bank->bank_num == 0 && pin_num == 24) || bank->bank_num == 4)
|
||||
type = 1;
|
||||
|
||||
ret = rockchip_translate_pull_value(type, pull);
|
||||
if (ret < 0) {
|
||||
debug("unsupported pull setting %d\n", pull);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* enable the write to the equivalent lower bits */
|
||||
data = ((1 << RK3506_PULL_BITS_PER_PIN) - 1) << (bit + 16);
|
||||
rmask = data | (data >> 16);
|
||||
data |= (ret << bit);
|
||||
|
||||
return regmap_update_bits(regmap, reg, rmask, data);
|
||||
}
|
||||
|
||||
#define RK3506_SMT_BITS_PER_PIN 1
|
||||
#define RK3506_SMT_PINS_PER_REG 8
|
||||
#define RK3506_SMT_GPIO0_A_OFFSET 0x400
|
||||
#define RK3506_SMT_GPIO0_D_OFFSET 0x830
|
||||
#define RK3506_SMT_GPIO1_OFFSET 0x410
|
||||
#define RK3506_SMT_GPIO2_OFFSET 0x420
|
||||
#define RK3506_SMT_GPIO3_OFFSET 0x430
|
||||
#define RK3506_SMT_GPIO4_OFFSET 0x840
|
||||
|
||||
static int rk3506_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
|
||||
int pin_num,
|
||||
struct regmap **regmap,
|
||||
int *reg, u8 *bit)
|
||||
{
|
||||
struct rockchip_pinctrl_priv *priv = bank->priv;
|
||||
int ret = 0;
|
||||
|
||||
switch (bank->bank_num) {
|
||||
case 0:
|
||||
*regmap = priv->regmap_pmu;
|
||||
if (pin_num > 24) {
|
||||
ret = -EINVAL;
|
||||
} else if (pin_num < 24) {
|
||||
*reg = RK3506_SMT_GPIO0_A_OFFSET;
|
||||
} else {
|
||||
*reg = RK3506_SMT_GPIO0_D_OFFSET;
|
||||
*bit = 9;
|
||||
|
||||
return 0;
|
||||
}
|
||||
break;
|
||||
|
||||
case 1:
|
||||
*regmap = priv->regmap_ioc1;
|
||||
if (pin_num < 28)
|
||||
*reg = RK3506_SMT_GPIO1_OFFSET;
|
||||
else
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
|
||||
case 2:
|
||||
*regmap = priv->regmap_base;
|
||||
if (pin_num < 17)
|
||||
*reg = RK3506_SMT_GPIO2_OFFSET;
|
||||
else
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
|
||||
case 3:
|
||||
*regmap = priv->regmap_base;
|
||||
if (pin_num < 15)
|
||||
*reg = RK3506_SMT_GPIO3_OFFSET;
|
||||
else
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
|
||||
case 4:
|
||||
*regmap = priv->regmap_base;
|
||||
if (pin_num < 8 || pin_num > 11) {
|
||||
ret = -EINVAL;
|
||||
} else {
|
||||
*reg = RK3506_SMT_GPIO4_OFFSET;
|
||||
*bit = 8;
|
||||
|
||||
return 0;
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
}
|
||||
|
||||
if (ret) {
|
||||
debug("unsupported bank_num %d pin_num %d\n", bank->bank_num, pin_num);
|
||||
return ret;
|
||||
}
|
||||
|
||||
*reg += ((pin_num / RK3506_SMT_PINS_PER_REG) * 4);
|
||||
*bit = pin_num % RK3506_SMT_PINS_PER_REG;
|
||||
*bit *= RK3506_SMT_BITS_PER_PIN;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rk3506_set_schmitt(struct rockchip_pin_bank *bank,
|
||||
int pin_num, int enable)
|
||||
{
|
||||
struct regmap *regmap;
|
||||
int reg, ret;
|
||||
u32 data, rmask;
|
||||
u8 bit;
|
||||
|
||||
ret = rk3506_calc_schmitt_reg_and_bit(bank, pin_num, ®map, ®, &bit);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* enable the write to the equivalent lower bits */
|
||||
data = ((1 << RK3506_SMT_BITS_PER_PIN) - 1) << (bit + 16);
|
||||
rmask = data | (data >> 16);
|
||||
data |= (enable << bit);
|
||||
|
||||
if ((bank->bank_num == 0 && pin_num == 24) || bank->bank_num == 4) {
|
||||
data = 0x3 << (bit + 16);
|
||||
rmask = data | (data >> 16);
|
||||
data |= ((enable ? 0x3 : 0) << bit);
|
||||
}
|
||||
|
||||
return regmap_update_bits(regmap, reg, rmask, data);
|
||||
}
|
||||
|
||||
static struct rockchip_mux_recalced_data rk3506_mux_recalced_data[] = {
|
||||
{
|
||||
.num = 0,
|
||||
.pin = 24,
|
||||
.reg = 0x830,
|
||||
.bit = 0,
|
||||
.mask = 0x3
|
||||
},
|
||||
};
|
||||
|
||||
static struct rockchip_pin_bank rk3506_pin_banks[] = {
|
||||
PIN_BANK_IOMUX_FLAGS_OFFSET(0, 32, "gpio0",
|
||||
IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU,
|
||||
IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU,
|
||||
IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU,
|
||||
IOMUX_8WIDTH_2BIT | IOMUX_SOURCE_PMU,
|
||||
0x0, 0x8, 0x10, 0x830),
|
||||
PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1",
|
||||
IOMUX_WIDTH_4BIT,
|
||||
IOMUX_WIDTH_4BIT,
|
||||
IOMUX_WIDTH_4BIT,
|
||||
IOMUX_WIDTH_4BIT,
|
||||
0x20, 0x28, 0x30, 0x38),
|
||||
PIN_BANK_IOMUX_FLAGS_OFFSET(2, 32, "gpio2",
|
||||
IOMUX_WIDTH_4BIT,
|
||||
IOMUX_WIDTH_4BIT,
|
||||
IOMUX_WIDTH_4BIT,
|
||||
IOMUX_WIDTH_4BIT,
|
||||
0x40, 0x48, 0x50, 0x58),
|
||||
PIN_BANK_IOMUX_FLAGS_OFFSET(3, 32, "gpio3",
|
||||
IOMUX_WIDTH_4BIT,
|
||||
IOMUX_WIDTH_4BIT,
|
||||
IOMUX_WIDTH_4BIT,
|
||||
IOMUX_WIDTH_4BIT,
|
||||
0x60, 0x68, 0x70, 0x78),
|
||||
PIN_BANK_IOMUX_FLAGS_OFFSET(4, 32, "gpio4",
|
||||
IOMUX_WIDTH_4BIT,
|
||||
IOMUX_WIDTH_4BIT,
|
||||
IOMUX_WIDTH_4BIT,
|
||||
IOMUX_WIDTH_4BIT,
|
||||
0x80, 0x88, 0x90, 0x98),
|
||||
};
|
||||
|
||||
static const struct rockchip_pin_ctrl rk3506_pin_ctrl = {
|
||||
.pin_banks = rk3506_pin_banks,
|
||||
.nr_banks = ARRAY_SIZE(rk3506_pin_banks),
|
||||
.iomux_recalced = rk3506_mux_recalced_data,
|
||||
.niomux_recalced = ARRAY_SIZE(rk3506_mux_recalced_data),
|
||||
.set_mux = rk3506_set_mux,
|
||||
.set_pull = rk3506_set_pull,
|
||||
.set_drive = rk3506_set_drive,
|
||||
.set_schmitt = rk3506_set_schmitt,
|
||||
};
|
||||
|
||||
static const struct udevice_id rk3506_pinctrl_ids[] = {
|
||||
{
|
||||
.compatible = "rockchip,rk3506-pinctrl",
|
||||
.data = (ulong)&rk3506_pin_ctrl
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(rockchip_rk3506_pinctrl) = {
|
||||
.name = "rockchip_rk3506_pinctrl",
|
||||
.id = UCLASS_PINCTRL,
|
||||
.of_match = rk3506_pinctrl_ids,
|
||||
.priv_auto = sizeof(struct rockchip_pinctrl_priv),
|
||||
.ops = &rockchip_pinctrl_ops,
|
||||
#if CONFIG_IS_ENABLED(OF_REAL)
|
||||
.bind = dm_scan_fdt_dev,
|
||||
#endif
|
||||
.probe = rockchip_pinctrl_probe,
|
||||
};
|
||||
@@ -10,6 +10,7 @@
|
||||
#include <syscon.h>
|
||||
#include <fdtdec.h>
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/libfdt.h>
|
||||
|
||||
#include "pinctrl-rockchip.h"
|
||||
@@ -641,37 +642,30 @@ int rockchip_pinctrl_probe(struct udevice *dev)
|
||||
{
|
||||
struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
|
||||
struct rockchip_pin_ctrl *ctrl;
|
||||
struct udevice *syscon;
|
||||
struct regmap *regmap;
|
||||
int ret = 0;
|
||||
|
||||
/* get rockchip grf syscon phandle */
|
||||
ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,grf",
|
||||
&syscon);
|
||||
if (ret) {
|
||||
debug("unable to find rockchip,grf syscon device (%d)\n", ret);
|
||||
return ret;
|
||||
priv->regmap_base =
|
||||
syscon_regmap_lookup_by_phandle(dev, "rockchip,grf");
|
||||
if (IS_ERR(priv->regmap_base)) {
|
||||
debug("unable to find rockchip,grf regmap\n");
|
||||
return PTR_ERR(priv->regmap_base);
|
||||
}
|
||||
|
||||
/* get grf-reg base address */
|
||||
regmap = syscon_get_regmap(syscon);
|
||||
if (!regmap) {
|
||||
debug("unable to find rockchip grf regmap\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
priv->regmap_base = regmap;
|
||||
|
||||
/* option: get pmu-reg base address */
|
||||
ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pmu",
|
||||
&syscon);
|
||||
if (!ret) {
|
||||
/* get pmugrf-reg base address */
|
||||
regmap = syscon_get_regmap(syscon);
|
||||
if (!regmap) {
|
||||
debug("unable to find rockchip pmu regmap\n");
|
||||
return -ENODEV;
|
||||
if (dev_read_bool(dev, "rockchip,pmu")) {
|
||||
priv->regmap_pmu =
|
||||
syscon_regmap_lookup_by_phandle(dev, "rockchip,pmu");
|
||||
if (IS_ERR(priv->regmap_pmu)) {
|
||||
debug("unable to find rockchip,pmu regmap\n");
|
||||
return PTR_ERR(priv->regmap_pmu);
|
||||
}
|
||||
}
|
||||
|
||||
if (dev_read_bool(dev, "rockchip,ioc1")) {
|
||||
priv->regmap_ioc1 =
|
||||
syscon_regmap_lookup_by_phandle(dev, "rockchip,ioc1");
|
||||
if (IS_ERR(priv->regmap_ioc1)) {
|
||||
debug("unable to find rockchip,ioc1 regmap\n");
|
||||
return PTR_ERR(priv->regmap_ioc1);
|
||||
}
|
||||
priv->regmap_pmu = regmap;
|
||||
}
|
||||
|
||||
ctrl = rockchip_pinctrl_get_soc_data(dev);
|
||||
|
||||
@@ -528,6 +528,7 @@ struct rockchip_pinctrl_priv {
|
||||
struct rockchip_pin_ctrl *ctrl;
|
||||
struct regmap *regmap_base;
|
||||
struct regmap *regmap_pmu;
|
||||
struct regmap *regmap_ioc1;
|
||||
};
|
||||
|
||||
extern const struct pinctrl_ops rockchip_pinctrl_ops;
|
||||
|
||||
@@ -13,6 +13,7 @@ obj-$(CONFIG_ROCKCHIP_RK3288) = sdram_rk3288.o
|
||||
obj-$(CONFIG_ROCKCHIP_RK3308) = sdram_rk3308.o
|
||||
obj-$(CONFIG_ROCKCHIP_RK3328) = sdram_rk3328.o sdram_pctl_px30.o sdram_phy_px30.o
|
||||
obj-$(CONFIG_ROCKCHIP_RK3399) += sdram_rk3399.o
|
||||
obj-$(CONFIG_ROCKCHIP_RK3506) += sdram_rk3506.o
|
||||
obj-$(CONFIG_ROCKCHIP_RK3528) += sdram_rk3528.o
|
||||
obj-$(CONFIG_ROCKCHIP_RK3568) += sdram_rk3568.o
|
||||
obj-$(CONFIG_ROCKCHIP_RK3576) += sdram_rk3576.o
|
||||
|
||||
33
drivers/ram/rockchip/sdram_rk3506.c
Normal file
33
drivers/ram/rockchip/sdram_rk3506.c
Normal file
@@ -0,0 +1,33 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
// Copyright Contributors to the U-Boot project.
|
||||
|
||||
#include <dm.h>
|
||||
#include <ram.h>
|
||||
#include <asm/arch-rockchip/sdram.h>
|
||||
|
||||
#define PMUGRF_BASE 0xff910000
|
||||
#define OS_REG2_REG 0x208
|
||||
|
||||
static int rk3506_dmc_get_info(struct udevice *dev, struct ram_info *info)
|
||||
{
|
||||
info->base = CFG_SYS_SDRAM_BASE;
|
||||
info->size = rockchip_sdram_size(PMUGRF_BASE + OS_REG2_REG);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct ram_ops rk3506_dmc_ops = {
|
||||
.get_info = rk3506_dmc_get_info,
|
||||
};
|
||||
|
||||
static const struct udevice_id rk3506_dmc_ids[] = {
|
||||
{ .compatible = "rockchip,rk3506-dmc" },
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(rockchip_rk3506_dmc) = {
|
||||
.name = "rockchip_rk3506_dmc",
|
||||
.id = UCLASS_RAM,
|
||||
.of_match = rk3506_dmc_ids,
|
||||
.ops = &rk3506_dmc_ops,
|
||||
};
|
||||
@@ -16,7 +16,7 @@ obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o
|
||||
obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
|
||||
obj-$(CONFIG_RESET_AST2500) += reset-ast2500.o
|
||||
obj-$(CONFIG_RESET_AST2600) += reset-ast2600.o
|
||||
obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o rst-rk3528.o rst-rk3576.o rst-rk3588.o
|
||||
obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o rst-rk3506.o rst-rk3528.o rst-rk3576.o rst-rk3588.o
|
||||
obj-$(CONFIG_RESET_MESON) += reset-meson.o
|
||||
obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
|
||||
obj-$(CONFIG_RESET_MEDIATEK) += reset-mediatek.o
|
||||
|
||||
222
drivers/reset/rst-rk3506.c
Normal file
222
drivers/reset/rst-rk3506.c
Normal file
@@ -0,0 +1,222 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
/*
|
||||
* Copyright (c) 2025 Rockchip Electronics Co., Ltd.
|
||||
* Author: Finley Xiao <finley.xiao@rock-chips.com>
|
||||
*/
|
||||
|
||||
#include <dm.h>
|
||||
#include <asm/arch-rockchip/clock.h>
|
||||
#include <dt-bindings/reset/rockchip,rk3506-cru.h>
|
||||
|
||||
/* 0xFF9A0000 + 0x0A00 */
|
||||
#define RK3506_CRU_RESET_OFFSET(id, reg, bit) [id] = (0 + reg * 16 + bit)
|
||||
|
||||
/* mapping table for reset ID to register offset */
|
||||
static const int rk3506_register_offset[] = {
|
||||
/* CRU-->SOFTRST_CON00 */
|
||||
RK3506_CRU_RESET_OFFSET(SRST_NCOREPORESET0_AC, 0, 0),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_NCOREPORESET1_AC, 0, 1),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_NCOREPORESET2_AC, 0, 2),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_NCORESET0_AC, 0, 4),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_NCORESET1_AC, 0, 5),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_NCORESET2_AC, 0, 6),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_NL2RESET_AC, 0, 8),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_A_CORE_BIU_AC, 0, 9),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_H_M0_AC, 0, 10),
|
||||
|
||||
/* CRU-->SOFTRST_CON02 */
|
||||
RK3506_CRU_RESET_OFFSET(SRST_NDBGRESET, 2, 10),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_P_CORE_BIU, 2, 14),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_PMU, 2, 15),
|
||||
|
||||
/* CRU-->SOFTRST_CON03 */
|
||||
RK3506_CRU_RESET_OFFSET(SRST_P_DBG, 3, 1),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_POT_DBG, 3, 2),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_P_CORE_GRF, 3, 4),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_CORE_EMA_DETECT, 3, 6),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_REF_PVTPLL_CORE, 3, 7),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_P_GPIO1, 3, 8),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_DB_GPIO1, 3, 9),
|
||||
|
||||
/* CRU-->SOFTRST_CON04 */
|
||||
RK3506_CRU_RESET_OFFSET(SRST_A_CORE_PERI_BIU, 4, 3),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_A_DSMC, 4, 5),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_P_DSMC, 4, 6),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_FLEXBUS, 4, 7),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_A_FLEXBUS, 4, 9),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_H_FLEXBUS, 4, 10),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_A_DSMC_SLV, 4, 11),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_H_DSMC_SLV, 4, 12),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_DSMC_SLV, 4, 13),
|
||||
|
||||
/* CRU-->SOFTRST_CON05 */
|
||||
RK3506_CRU_RESET_OFFSET(SRST_A_BUS_BIU, 5, 3),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_H_BUS_BIU, 5, 4),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_P_BUS_BIU, 5, 5),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_A_SYSRAM, 5, 6),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_H_SYSRAM, 5, 7),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_A_DMAC0, 5, 8),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_A_DMAC1, 5, 9),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_H_M0, 5, 10),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_M0_JTAG, 5, 11),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_H_CRYPTO, 5, 15),
|
||||
|
||||
/* CRU-->SOFTRST_CON06 */
|
||||
RK3506_CRU_RESET_OFFSET(SRST_H_RNG, 6, 0),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_P_BUS_GRF, 6, 1),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_P_TIMER0, 6, 2),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_TIMER0_CH0, 6, 3),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_TIMER0_CH1, 6, 4),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_TIMER0_CH2, 6, 5),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_TIMER0_CH3, 6, 6),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_TIMER0_CH4, 6, 7),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_TIMER0_CH5, 6, 8),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_P_WDT0, 6, 9),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_T_WDT0, 6, 10),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_P_WDT1, 6, 11),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_T_WDT1, 6, 12),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_P_MAILBOX, 6, 13),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_P_INTMUX, 6, 14),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_P_SPINLOCK, 6, 15),
|
||||
|
||||
/* CRU-->SOFTRST_CON07 */
|
||||
RK3506_CRU_RESET_OFFSET(SRST_P_DDRC, 7, 0),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_H_DDRPHY, 7, 1),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_P_DDRMON, 7, 2),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_DDRMON_OSC, 7, 3),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_P_DDR_LPC, 7, 4),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_H_USBOTG0, 7, 5),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_USBOTG0_ADP, 7, 7),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_H_USBOTG1, 7, 8),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_USBOTG1_ADP, 7, 10),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_P_USBPHY, 7, 11),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_USBPHY_POR, 7, 12),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_USBPHY_OTG0, 7, 13),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_USBPHY_OTG1, 7, 14),
|
||||
|
||||
/* CRU-->SOFTRST_CON08 */
|
||||
RK3506_CRU_RESET_OFFSET(SRST_A_DMA2DDR, 8, 0),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_P_DMA2DDR, 8, 1),
|
||||
|
||||
/* CRU-->SOFTRST_CON09 */
|
||||
RK3506_CRU_RESET_OFFSET(SRST_USBOTG0_UTMI, 9, 0),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_USBOTG1_UTMI, 9, 1),
|
||||
|
||||
/* CRU-->SOFTRST_CON10 */
|
||||
RK3506_CRU_RESET_OFFSET(SRST_A_DDRC_0, 10, 0),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_A_DDRC_1, 10, 1),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_A_DDR_BIU, 10, 2),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_DDRC, 10, 3),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_DDRMON, 10, 4),
|
||||
|
||||
/* CRU-->SOFTRST_CON11 */
|
||||
RK3506_CRU_RESET_OFFSET(SRST_H_LSPERI_BIU, 11, 2),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_P_UART0, 11, 4),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_P_UART1, 11, 5),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_P_UART2, 11, 6),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_P_UART3, 11, 7),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_P_UART4, 11, 8),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_UART0, 11, 9),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_UART1, 11, 10),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_UART2, 11, 11),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_UART3, 11, 12),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_UART4, 11, 13),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_P_I2C0, 11, 14),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_I2C0, 11, 15),
|
||||
|
||||
/* CRU-->SOFTRST_CON12 */
|
||||
RK3506_CRU_RESET_OFFSET(SRST_P_I2C1, 12, 0),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_I2C1, 12, 1),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_P_I2C2, 12, 2),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_I2C2, 12, 3),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_P_PWM1, 12, 4),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_PWM1, 12, 5),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_P_SPI0, 12, 10),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_SPI0, 12, 11),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_P_SPI1, 12, 12),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_SPI1, 12, 13),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_P_GPIO2, 12, 14),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_DB_GPIO2, 12, 15),
|
||||
|
||||
/* CRU-->SOFTRST_CON13 */
|
||||
RK3506_CRU_RESET_OFFSET(SRST_P_GPIO3, 13, 0),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_DB_GPIO3, 13, 1),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_P_GPIO4, 13, 2),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_DB_GPIO4, 13, 3),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_H_CAN0, 13, 4),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_CAN0, 13, 5),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_H_CAN1, 13, 6),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_CAN1, 13, 7),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_H_PDM, 13, 8),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_M_PDM, 13, 9),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_PDM, 13, 10),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_SPDIFTX, 13, 11),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_H_SPDIFTX, 13, 12),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_H_SPDIFRX, 13, 13),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_SPDIFRX, 13, 14),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_M_SAI0, 13, 15),
|
||||
|
||||
/* CRU-->SOFTRST_CON14 */
|
||||
RK3506_CRU_RESET_OFFSET(SRST_H_SAI0, 14, 0),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_M_SAI1, 14, 2),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_H_SAI1, 14, 3),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_H_ASRC0, 14, 5),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_ASRC0, 14, 6),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_H_ASRC1, 14, 7),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_ASRC1, 14, 8),
|
||||
|
||||
/* CRU-->SOFTRST_CON17 */
|
||||
RK3506_CRU_RESET_OFFSET(SRST_H_HSPERI_BIU, 17, 4),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_H_SDMMC, 17, 7),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_H_FSPI, 17, 8),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_S_FSPI, 17, 9),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_P_SPI2, 17, 10),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_A_MAC0, 17, 11),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_A_MAC1, 17, 12),
|
||||
|
||||
/* CRU-->SOFTRST_CON18 */
|
||||
RK3506_CRU_RESET_OFFSET(SRST_M_SAI2, 18, 2),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_H_SAI2, 18, 3),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_H_SAI3, 18, 6),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_M_SAI3, 18, 7),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_H_SAI4, 18, 10),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_M_SAI4, 18, 11),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_H_DSM, 18, 12),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_M_DSM, 18, 13),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_P_AUDIO_ADC, 18, 14),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_M_AUDIO_ADC, 18, 15),
|
||||
|
||||
/* CRU-->SOFTRST_CON19 */
|
||||
RK3506_CRU_RESET_OFFSET(SRST_P_SARADC, 19, 0),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_SARADC, 19, 1),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_SARADC_PHY, 19, 2),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_P_OTPC_NS, 19, 3),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_SBPI_OTPC_NS, 19, 4),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_USER_OTPC_NS, 19, 5),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_P_UART5, 19, 6),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_UART5, 19, 7),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_P_GPIO234_IOC, 19, 8),
|
||||
|
||||
/* CRU-->SOFTRST_CON21 */
|
||||
RK3506_CRU_RESET_OFFSET(SRST_A_VIO_BIU, 21, 3),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_H_VIO_BIU, 21, 4),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_H_RGA, 21, 6),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_A_RGA, 21, 7),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_CORE_RGA, 21, 8),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_A_VOP, 21, 9),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_H_VOP, 21, 10),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_VOP, 21, 11),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_P_DPHY, 21, 12),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_P_DSI_HOST, 21, 13),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_P_TSADC, 21, 14),
|
||||
RK3506_CRU_RESET_OFFSET(SRST_TSADC, 21, 15),
|
||||
|
||||
/* CRU-->SOFTRST_CON22 */
|
||||
RK3506_CRU_RESET_OFFSET(SRST_P_GPIO1_IOC, 22, 1),
|
||||
};
|
||||
|
||||
int rk3506_reset_bind_lut(struct udevice *pdev, u32 reg_offset, u32 reg_number)
|
||||
{
|
||||
return rockchip_reset_bind_lut(pdev, rk3506_register_offset,
|
||||
reg_offset, reg_number);
|
||||
}
|
||||
@@ -89,6 +89,7 @@ config USB_GADGET_PRODUCT_NUM
|
||||
default 0x350b if ROCKCHIP_RK3588
|
||||
default 0x350c if ROCKCHIP_RK3528
|
||||
default 0x350e if ROCKCHIP_RK3576
|
||||
default 0x350f if ROCKCHIP_RK3506
|
||||
default 0x4ee0 if ARCH_SNAPDRAGON
|
||||
default 0x0
|
||||
help
|
||||
|
||||
38
include/configs/rk3506_common.h
Normal file
38
include/configs/rk3506_common.h
Normal file
@@ -0,0 +1,38 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
/* Copyright Contributors to the U-Boot project. */
|
||||
|
||||
#ifndef __CONFIG_RK3506_COMMON_H
|
||||
#define __CONFIG_RK3506_COMMON_H
|
||||
|
||||
#define CFG_CPUID_OFFSET 0xa
|
||||
|
||||
#include "rockchip-common.h"
|
||||
|
||||
#define CFG_IRAM_BASE 0xfff80000
|
||||
|
||||
#define CFG_SYS_SDRAM_BASE 0
|
||||
#define SDRAM_MAX_SIZE 0xc0000000
|
||||
|
||||
#ifndef ROCKCHIP_DEVICE_SETTINGS
|
||||
#define ROCKCHIP_DEVICE_SETTINGS
|
||||
#endif
|
||||
|
||||
#define ENV_MEM_LAYOUT_SETTINGS \
|
||||
"scriptaddr=0x00500000\0" \
|
||||
"script_offset_f=0xffe000\0" \
|
||||
"script_size_f=0x2000\0" \
|
||||
"pxefile_addr_r=0x00600000\0" \
|
||||
"kernel_addr_r=0x02080000\0" \
|
||||
"kernel_comp_addr_r=0x08000000\0" \
|
||||
"fdt_addr_r=0x01e00000\0" \
|
||||
"fdtoverlay_addr_r=0x01f00000\0" \
|
||||
"ramdisk_addr_r=0x06000000\0" \
|
||||
"kernel_comp_size=0x2000000\0"
|
||||
|
||||
#define CFG_EXTRA_ENV_SETTINGS \
|
||||
"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
|
||||
ENV_MEM_LAYOUT_SETTINGS \
|
||||
ROCKCHIP_DEVICE_SETTINGS \
|
||||
"boot_targets=" BOOT_TARGETS "\0"
|
||||
|
||||
#endif /* __CONFIG_RK3506_COMMON_H */
|
||||
@@ -148,12 +148,13 @@ static struct spl_info spl_infos[] = {
|
||||
{ "rk3328", "RK32", 0x8000 - 0x800, false, RK_HEADER_V1 },
|
||||
{ "rk3368", "RK33", 0x8000 - 0x1000, false, RK_HEADER_V1 },
|
||||
{ "rk3399", "RK33", 0x30000 - 0x2000, false, RK_HEADER_V1 },
|
||||
{ "rv1108", "RK11", 0x1800, false, RK_HEADER_V1 },
|
||||
{ "rv1126", "110B", 0x10000 - 0x1000, false, RK_HEADER_V1 },
|
||||
{ "rk3506", "RK35", 0xC000 - 0x1000, false, RK_HEADER_V2 },
|
||||
{ "rk3528", "RK35", 0x10000 - 0x1000, false, RK_HEADER_V2 },
|
||||
{ "rk3568", "RK35", 0x10000 - 0x1000, false, RK_HEADER_V2 },
|
||||
{ "rk3576", "RK35", 0x80000 - 0x1000, false, RK_HEADER_V2 },
|
||||
{ "rk3588", "RK35", 0x100000 - 0x1000, false, RK_HEADER_V2 },
|
||||
{ "rv1108", "RK11", 0x1800, false, RK_HEADER_V1 },
|
||||
{ "rv1126", "110B", 0x10000 - 0x1000, false, RK_HEADER_V1 },
|
||||
};
|
||||
|
||||
/**
|
||||
|
||||
Reference in New Issue
Block a user