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Merge tag 'u-boot-imx-next-20260515' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx into next

Browse Source 
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/30134

- Several conversions to OF_UPSTREAM.
- Added i.MX9 Quickboot support.
- Added support for i.MX952 in the fsl_enetc driver.
- Update i.MX91 part number detection.
This commit is contained in:
Tom Rini
2026-05-15 17:32:13 -06:00
parent a6f6947e43 9e46861a01
commit dc4dd58926
58 changed files with 1018 additions and 6582 deletions
Download Patch File Download Diff File Expand all files Collapse all files

21
MAINTAINERS
View File

@@ -310,26 +310,13 @@ M: Fabio Estevam <festevam@gmail.com>
R: NXP i.MX U-Boot Team <uboot-imx@nxp.com>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-imx.git
F: arch/Kconfig.nxp
N: imx
N: mxc
N: nxp
N: vf610
F: arch/arm/cpu/arm1136/mx*/
F: arch/arm/cpu/arm926ejs/mx*/
F: arch/arm/cpu/armv7/vf610/
F: arch/arm/dts/*imx*
F: arch/arm/mach-imx/
F: arch/arm/include/asm/arch-imx*/
F: arch/arm/include/asm/arch-mx*/
F: arch/arm/include/asm/arch-vf610/
F: arch/arm/include/asm/mach-imx/
F: board/nxp/*mx*/
F: board/nxp/common/
F: common/spl/spl_imx_container.c
F: doc/board/nxp/
F: doc/imx/
F: drivers/mailbox/imx-mailbox.c
F: drivers/remoteproc/imx*
F: drivers/serial/serial_mxc.c
F: drivers/spi/nxp_xspi.c
F: include/imx_container.h
ARM HISILICON
M: Peter Griffin <peter.griffin@linaro.org>

7
arch/arm/dts/Makefile
View File

@@ -879,8 +879,6 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mm-mx8menlo.dtb \
imx8mm-phg.dtb \
imx8mq-cm.dtb \
imx8mq-mnt-reform2.dtb \
imx8mq-phanbell.dtb \
imx8mp-data-modul-edm-sbc.dtb \
imx8mp-dhcom-som-overlay-rev100.dtbo \
imx8mp-dhcom-som-overlay-eth1xfast.dtbo \
@@ -890,10 +888,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mp-dhcom-pdk3-overlay-rev100.dtbo \
imx8mp-dhcom-picoitx.dtb \
imx8mp-icore-mx8mp-edimm2.2.dtb \
imx8mp-msc-sm2s.dtb \
imx8mq-pico-pi.dtb \
imx8mq-kontron-pitx-imx8m.dtb \
imx8mq-librem5-r4.dtb
imx8mp-msc-sm2s.dtb
dtb-$(CONFIG_ARCH_IMX9) += \
imx93-11x11-frdm.dtb \

437
arch/arm/dts/imx8mm-beacon-baseboard.dtsi
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@@ -1,437 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2020 Compass Electronics Group, LLC
*/
#include <dt-bindings/phy/phy-imx8-pcie.h>
/ {
leds {
compatible = "gpio-leds";
led0 {
label = "gen_led0";
gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led1 {
label = "gen_led1";
gpios = <&pca6416_1 5 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led2 {
label = "gen_led2";
gpios = <&pca6416_1 6 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_led3>;
label = "heartbeat";
gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
pcie0_refclk: pcie0-refclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
pcie0_refclk_gated: pcie0-refclk-gated {
compatible = "gpio-gate-clock";
clocks = <&pcie0_refclk>;
#clock-cells = <0>;
enable-gpios = <&pca6416_1 2 GPIO_ACTIVE_LOW>;
};
reg_audio: regulator-audio {
compatible = "regulator-fixed";
regulator-name = "3v3_aud";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&pca6416_1 11 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usbotg1: regulator-usbotg1 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usb_otg1>;
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_camera: regulator-camera {
compatible = "regulator-fixed";
regulator-name = "mipi_pwr";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
gpio = <&pca6416_1 0 GPIO_ACTIVE_HIGH>;
enable-active-high;
startup-delay-us = <100000>;
};
reg_pcie0: regulator-pcie {
compatible = "regulator-fixed";
regulator-name = "pci_pwr_en";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
enable-active-high;
gpio = <&pca6416_1 1 GPIO_ACTIVE_HIGH>;
startup-delay-us = <100000>;
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
regulator-name = "VSD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
sound {
compatible = "fsl,imx-audio-wm8962";
model = "wm8962-audio";
audio-cpu = <&sai3>;
audio-codec = <&wm8962>;
audio-routing =
"Headphone Jack", "HPOUTL",
"Headphone Jack", "HPOUTR",
"Ext Spk", "SPKOUTL",
"Ext Spk", "SPKOUTR",
"AMIC", "MICBIAS",
"IN3R", "AMIC";
};
};
&csi {
status = "okay";
};
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_espi2>;
cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
status = "okay";
eeprom@0 {
compatible = "microchip,at25160bn", "atmel,at25";
reg = <0>;
spi-max-frequency = <5000000>;
spi-cpha;
spi-cpol;
pagesize = <32>;
size = <2048>;
address-width = <16>;
};
};
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
camera@3c {
compatible = "ovti,ov5640";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ov5640>;
reg = <0x3c>;
clocks = <&clk IMX8MM_CLK_CLKO1>;
clock-names = "xclk";
assigned-clocks = <&clk IMX8MM_CLK_CLKO1>;
assigned-clock-parents = <&clk IMX8MM_CLK_24M>;
assigned-clock-rates = <24000000>;
AVDD-supply = <&reg_camera>; /* 2.8v */
powerdown-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
port {
/* MIPI CSI-2 bus endpoint */
ov5640_to_mipi_csi2: endpoint {
remote-endpoint = <&imx8mm_mipi_csi_in>;
clock-lanes = <0>;
data-lanes = <1 2>;
};
};
};
};
&i2c4 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
status = "okay";
wm8962: audio-codec@1a {
compatible = "wlf,wm8962";
reg = <0x1a>;
clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
DCVDD-supply = <&reg_audio>;
DBVDD-supply = <&reg_audio>;
AVDD-supply = <&reg_audio>;
CPVDD-supply = <&reg_audio>;
MICVDD-supply = <&reg_audio>;
PLLVDD-supply = <&reg_audio>;
SPKVDD1-supply = <&reg_audio>;
SPKVDD2-supply = <&reg_audio>;
gpio-cfg = <
0x0000 /* 0:Default */
0x0000 /* 1:Default */
0x0000 /* 2:FN_DMICCLK */
0x0000 /* 3:Default */
0x0000 /* 4:FN_DMICCDAT */
0x0000 /* 5:Default */
>;
};
pca6416_0: gpio@20 {
compatible = "nxp,pcal6416";
reg = <0x20>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcal6414>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&gpio4>;
interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
};
pca6416_1: gpio@21 {
compatible = "nxp,pcal6416";
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&gpio4>;
interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
};
};
&mipi_csi {
status = "okay";
ports {
port@0 {
imx8mm_mipi_csi_in: endpoint {
remote-endpoint = <&ov5640_to_mipi_csi2>;
data-lanes = <1 2>;
};
};
};
};
&pcie_phy {
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
fsl,tx-deemph-gen1 = <0x2d>;
fsl,tx-deemph-gen2 = <0xf>;
fsl,clkreq-unsupported;
clocks = <&pcie0_refclk_gated>;
clock-names = "ref";
status = "okay";
};
&pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0>;
reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
<&pcie0_refclk_gated>;
clock-names = "pcie", "pcie_aux", "pcie_bus";
assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
<&clk IMX8MM_CLK_PCIE1_CTRL>;
assigned-clock-rates = <10000000>, <250000000>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
<&clk IMX8MM_SYS_PLL2_250M>;
vpcie-supply = <&reg_pcie0>;
status = "okay";
};
&sai3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
assigned-clock-rates = <24576000>;
fsl,sai-mclk-direction-output;
status = "okay";
};
&snvs_pwrkey {
status = "okay";
};
&uart2 { /* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
assigned-clocks = <&clk IMX8MM_CLK_UART3>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
uart-has-rtscts;
status = "okay";
};
&usbotg1 {
vbus-supply = <&reg_usbotg1>;
disable-over-current;
dr_mode = "otg";
status = "okay";
};
&usbotg2 {
pinctrl-names = "default";
disable-over-current;
dr_mode = "host";
status = "okay";
};
&usbphynop2 {
reset-gpios = <&pca6416_1 7 GPIO_ACTIVE_HIGH>;
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
bus-width = <4>;
vmmc-supply = <&reg_usdhc2_vmmc>;
status = "okay";
};
&iomuxc {
pinctrl_espi2: espi2grp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82
MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82
MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82
MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x41
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
>;
};
pinctrl_led3: led3grp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x41
>;
};
pinctrl_ov5640: ov5640grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19
MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19
MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x59
>;
};
pinctrl_pcal6414: pcal6414-gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x19
>;
};
pinctrl_reg_usb_otg1: usbotg1grp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19
>;
};
pinctrl_pcie0: pcie0grp {
fsl,pins = <
MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x41
>;
};
pinctrl_sai3: sai3grp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x40
MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x40
MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x40
MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x40
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x41
MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
};

309
arch/arm/dts/imx8mn-beacon-baseboard.dtsi
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@@ -1,309 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2020 Compass Electronics Group, LLC
*/
/ {
leds {
compatible = "gpio-leds";
led-0 {
label = "gen_led0";
gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led-1 {
label = "gen_led1";
gpios = <&pca6416_1 5 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led-2 {
label = "gen_led2";
gpios = <&pca6416_1 6 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led-3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_led3>;
label = "heartbeat";
gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
reg_audio: regulator-audio {
compatible = "regulator-fixed";
regulator-name = "3v3_aud";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&pca6416_1 11 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
regulator-name = "vsd_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usb_otg_vbus: regulator-usb {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usb_otg>;
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
sound {
compatible = "fsl,imx-audio-wm8962";
model = "wm8962-audio";
audio-cpu = <&sai3>;
audio-codec = <&wm8962>;
audio-routing =
"Headphone Jack", "HPOUTL",
"Headphone Jack", "HPOUTR",
"Ext Spk", "SPKOUTL",
"Ext Spk", "SPKOUTR",
"AMIC", "MICBIAS",
"IN3R", "AMIC";
};
};
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_espi2>;
cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
status = "okay";
eeprom@0 {
compatible = "microchip,at25160bn", "atmel,at25";
reg = <0>;
spi-max-frequency = <5000000>;
spi-cpha;
spi-cpol;
pagesize = <32>;
size = <2048>;
address-width = <16>;
};
};
&i2c4 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
status = "okay";
pca6416_0: gpio@20 {
compatible = "nxp,pcal6416";
reg = <0x20>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcal6414>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&gpio4>;
interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
};
pca6416_1: gpio@21 {
compatible = "nxp,pcal6416";
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&gpio4>;
interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
};
wm8962: audio-codec@1a {
compatible = "wlf,wm8962";
reg = <0x1a>;
clocks = <&clk IMX8MN_CLK_SAI3_ROOT>;
DCVDD-supply = <&reg_audio>;
DBVDD-supply = <&reg_audio>;
AVDD-supply = <&reg_audio>;
CPVDD-supply = <&reg_audio>;
MICVDD-supply = <&reg_audio>;
PLLVDD-supply = <&reg_audio>;
SPKVDD1-supply = <&reg_audio>;
SPKVDD2-supply = <&reg_audio>;
gpio-cfg = <
0x0000 /* 0:Default */
0x0000 /* 1:Default */
0x0000 /* 2:FN_DMICCLK */
0x0000 /* 3:Default */
0x0000 /* 4:FN_DMICCDAT */
0x0000 /* 5:Default */
>;
};
};
&easrc {
fsl,asrc-rate = <48000>;
status = "okay";
};
&sai3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
assigned-clocks = <&clk IMX8MN_CLK_SAI3>;
assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
assigned-clock-rates = <24576000>;
fsl,sai-mclk-direction-output;
status = "okay";
};
&snvs_pwrkey {
status = "okay";
};
&uart2 { /* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
assigned-clocks = <&clk IMX8MN_CLK_UART3>;
assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
uart-has-rtscts;
status = "okay";
};
&usbotg1 {
vbus-supply = <&reg_usb_otg_vbus>;
disable-over-current;
dr_mode = "otg";
status = "okay";
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
bus-width = <4>;
vmmc-supply = <&reg_usdhc2_vmmc>;
status = "okay";
};
&iomuxc {
pinctrl_espi2: espi2grp {
fsl,pins = <
MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82
MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82
MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82
MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x41
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
>;
};
pinctrl_led3: led3grp {
fsl,pins = <
MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x41
>;
};
pinctrl_pcal6414: pcal6414-gpiogrp {
fsl,pins = <
MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x19
>;
};
pinctrl_reg_usb_otg: reg-otggrp {
fsl,pins = <
MX8MN_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19
>;
};
pinctrl_sai3: sai3grp {
fsl,pins = <
MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
MX8MN_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x40
MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x40
MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x40
MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x40
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX8MN_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x41
MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
};

533
arch/arm/dts/imx8mn-evk.dtsi
View File

@@ -1,533 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2019 NXP
*/
#include <dt-bindings/usb/pd.h>
#include "imx8mn.dtsi"
/ {
chosen {
stdout-path = &uart2;
};
gpio-leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_led>;
status {
label = "yellow:status";
gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
};
memory@40000000 {
device_type = "memory";
reg = <0x0 0x40000000 0 0x80000000>;
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
regulator-name = "VSD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
ir-receiver {
compatible = "gpio-ir-receiver";
gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ir>;
linux,autosuspend-period = <125>;
};
audio_codec_bt_sco: audio-codec-bt-sco {
compatible = "linux,bt-sco";
#sound-dai-cells = <1>;
};
wm8524: audio-codec {
#sound-dai-cells = <0>;
compatible = "wlf,wm8524";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_wlf>;
wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>;
clocks = <&clk IMX8MN_CLK_SAI3_ROOT>;
clock-names = "mclk";
};
sound-bt-sco {
compatible = "simple-audio-card";
simple-audio-card,name = "bt-sco-audio";
simple-audio-card,format = "dsp_a";
simple-audio-card,bitclock-inversion;
simple-audio-card,frame-master = <&btcpu>;
simple-audio-card,bitclock-master = <&btcpu>;
btcpu: simple-audio-card,cpu {
sound-dai = <&sai2>;
dai-tdm-slot-num = <2>;
dai-tdm-slot-width = <16>;
};
simple-audio-card,codec {
sound-dai = <&audio_codec_bt_sco 1>;
};
};
sound-wm8524 {
compatible = "fsl,imx-audio-wm8524";
model = "wm8524-audio";
audio-cpu = <&sai3>;
audio-codec = <&wm8524>;
audio-asrc = <&easrc>;
audio-routing =
"Line Out Jack", "LINEVOUTL",
"Line Out Jack", "LINEVOUTR";
};
sound-spdif {
compatible = "fsl,imx-audio-spdif";
model = "imx-spdif";
spdif-controller = <&spdif1>;
spdif-out;
spdif-in;
};
};
&easrc {
fsl,asrc-rate = <48000>;
status = "okay";
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy0>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
qca,disable-smarteee;
vddio-supply = <&vddio>;
vddio: vddio-regulator {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
};
};
};
&flexspi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexspi>;
status = "okay";
flash0: flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <166000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
};
};
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
};
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
ptn5110: tcpc@50 {
compatible = "nxp,ptn5110";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_typec1>;
reg = <0x50>;
interrupt-parent = <&gpio2>;
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
status = "okay";
port {
typec1_dr_sw: endpoint {
remote-endpoint = <&usb1_drd_sw>;
};
};
typec1_con: connector {
compatible = "usb-c-connector";
label = "USB-C";
power-role = "dual";
data-role = "dual";
try-power-role = "sink";
source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
PDO_VAR(5000, 20000, 3000)>;
op-sink-microwatt = <15000000>;
self-powered;
};
};
};
&i2c3 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
pca6416: gpio@20 {
compatible = "ti,tca6416";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
};
};
&sai2 {
#sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai2>;
assigned-clocks = <&clk IMX8MN_CLK_SAI2>;
assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
assigned-clock-rates = <24576000>;
status = "okay";
};
&sai3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
assigned-clocks = <&clk IMX8MN_CLK_SAI3>;
assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
assigned-clock-rates = <24576000>;
fsl,sai-mclk-direction-output;
status = "okay";
};
&snvs_pwrkey {
status = "okay";
};
&spdif1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spdif1>;
assigned-clocks = <&clk IMX8MN_CLK_SPDIF1>;
assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
assigned-clock-rates = <24576000>;
status = "okay";
};
&uart2 { /* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
assigned-clocks = <&clk IMX8MN_CLK_UART3>;
assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
uart-has-rtscts;
status = "okay";
};
&usbotg1 {
dr_mode = "otg";
hnp-disable;
srp-disable;
adp-disable;
usb-role-switch;
disable-over-current;
samsung,picophy-pre-emp-curr-control = <3>;
samsung,picophy-dc-vol-level-adjust = <7>;
status = "okay";
port {
usb1_drd_sw: endpoint {
remote-endpoint = <&typec1_dr_sw>;
};
};
};
&usdhc2 {
assigned-clocks = <&clk IMX8MN_CLK_USDHC2>;
assigned-clock-rates = <200000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
bus-width = <4>;
vmmc-supply = <&reg_usdhc2_vmmc>;
status = "okay";
};
&usdhc3 {
assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>;
assigned-clock-rates = <400000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
>;
};
pinctrl_flexspi: flexspigrp {
fsl,pins = <
MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2
MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
>;
};
pinctrl_gpio_led: gpioledgrp {
fsl,pins = <
MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
>;
};
pinctrl_gpio_wlf: gpiowlfgrp {
fsl,pins = <
MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21 0xd6
>;
};
pinctrl_ir: irgrp {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x4f
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
>;
};
pinctrl_pmic: pmicirqgrp {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141
>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
>;
};
pinctrl_sai2: sai2grp {
fsl,pins = <
MX8MN_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
MX8MN_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
MX8MN_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
MX8MN_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6
>;
};
pinctrl_sai3: sai3grp {
fsl,pins = <
MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
>;
};
pinctrl_spdif1: spdif1grp {
fsl,pins = <
MX8MN_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6
MX8MN_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6
>;
};
pinctrl_typec1: typec1grp {
fsl,pins = <
MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x140
MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x140
MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x140
MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x140
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190
MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
>;
};
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins = <
MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194
MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
>;
};
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = <
MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196
MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166
>;
};
};

613
arch/arm/dts/imx8mq-kontron-pitx-imx8m.dts
View File

@@ -1,613 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree File for the Kontron pitx-imx8m board.
*
* Copyright (C) 2021 Heiko Thiery <heiko.thiery@gmail.com>
*/
/dts-v1/;
#include "imx8mq.dtsi"
#include <dt-bindings/net/ti-dp83867.h>
/ {
model = "Kontron pITX-imx8m";
compatible = "kontron,pitx-imx8m", "fsl,imx8mq";
aliases {
i2c0 = &i2c1;
i2c1 = &i2c2;
i2c2 = &i2c3;
mmc0 = &usdhc1;
mmc1 = &usdhc2;
serial0 = &uart1;
serial1 = &uart2;
serial2 = &uart3;
spi0 = &qspi0;
spi1 = &ecspi2;
};
chosen {
stdout-path = "serial2:115200n8";
};
pcie0_refclk: pcie0-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
pcie1_refclk: pcie1-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2>;
regulator-name = "V_3V3_SD";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
off-on-delay-us = <20000>;
enable-active-high;
};
};
&ecspi2 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
status = "okay";
tpm@0 {
compatible = "infineon,slb9670";
reg = <0>;
spi-max-frequency = <43000000>;
};
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy0>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
reset-assert-us = <10>;
reset-deassert-us = <280>;
};
};
};
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
pmic@8 {
compatible = "fsl,pfuze100";
fsl,pfuze-support-disable-sw;
reg = <0x8>;
regulators {
sw1a_reg: sw1ab {
regulator-name = "V_0V9_GPU";
regulator-min-microvolt = <825000>;
regulator-max-microvolt = <1100000>;
};
sw1c_reg: sw1c {
regulator-name = "V_0V9_VPU";
regulator-min-microvolt = <825000>;
regulator-max-microvolt = <1100000>;
};
sw2_reg: sw2 {
regulator-name = "V_1V1_NVCC_DRAM";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-always-on;
};
sw3a_reg: sw3ab {
regulator-name = "V_1V0_DRAM";
regulator-min-microvolt = <825000>;
regulator-max-microvolt = <1100000>;
regulator-always-on;
};
sw4_reg: sw4 {
regulator-name = "V_1V8_S0";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
swbst_reg: swbst {
regulator-name = "NC";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5150000>;
};
snvs_reg: vsnvs {
regulator-name = "V_0V9_SNVS";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <3000000>;
regulator-always-on;
};
vref_reg: vrefddr {
regulator-name = "V_0V55_VREF_DDR";
regulator-always-on;
};
vgen1_reg: vgen1 {
regulator-name = "V_1V5_CSI";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
};
vgen2_reg: vgen2 {
regulator-name = "V_0V9_PHY";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <975000>;
regulator-always-on;
};
vgen3_reg: vgen3 {
regulator-name = "V_1V8_PHY";
regulator-min-microvolt = <1675000>;
regulator-max-microvolt = <1975000>;
regulator-always-on;
};
vgen4_reg: vgen4 {
regulator-name = "V_1V8_VDDA";
regulator-min-microvolt = <1625000>;
regulator-max-microvolt = <1875000>;
regulator-always-on;
};
vgen5_reg: vgen5 {
regulator-name = "V_3V3_PHY";
regulator-min-microvolt = <3075000>;
regulator-max-microvolt = <3625000>;
regulator-always-on;
};
vgen6_reg: vgen6 {
regulator-name = "V_2V8_CAM";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
};
fan-controller@1b {
compatible = "maxim,max6650";
reg = <0x1b>;
maxim,fan-microvolt = <5000000>;
};
rtc@32 {
compatible = "microcrystal,rv8803";
reg = <0x32>;
};
sensor@4b {
compatible = "national,lm75b";
reg = <0x4b>;
};
eeprom@51 {
compatible = "atmel,24c32";
reg = <0x51>;
pagesize = <32>;
};
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
};
/* M.2 B-key slot */
&pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0>;
reset-gpio = <&gpio1 9 GPIO_ACTIVE_LOW>;
clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
<&clk IMX8MQ_CLK_PCIE1_AUX>,
<&clk IMX8MQ_CLK_PCIE1_PHY>,
<&pcie0_refclk>;
clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
status = "okay";
};
/* Intel Ethernet Controller I210/I211 */
&pcie1 {
clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
<&clk IMX8MQ_CLK_PCIE2_AUX>,
<&clk IMX8MQ_CLK_PCIE2_PHY>,
<&pcie1_refclk>;
clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
fsl,max-link-speed = <1>;
status = "okay";
};
&pgc_gpu {
power-supply = <&sw1a_reg>;
};
&pgc_vpu {
power-supply = <&sw1c_reg>;
};
&qspi0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qspi>;
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
m25p,fast-read;
spi-max-frequency = <50000000>;
};
};
&snvs_pwrkey {
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
assigned-clocks = <&clk IMX8MQ_CLK_UART1>;
assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
assigned-clocks = <&clk IMX8MQ_CLK_UART2>;
assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
uart-has-rtscts;
assigned-clocks = <&clk IMX8MQ_CLK_UART3>;
assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
status = "okay";
};
&usb3_phy0 {
status = "okay";
};
&usb3_phy1 {
status = "okay";
};
&usb_dwc3_0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0>;
dr_mode = "otg";
hnp-disable;
srp-disable;
adp-disable;
maximum-speed = "high-speed";
status = "okay";
};
&usb_dwc3_1 {
dr_mode = "host";
status = "okay";
};
&usdhc1 {
assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
assigned-clock-rates = <400000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
vqmmc-supply = <&sw4_reg>;
bus-width = <8>;
non-removable;
no-sd;
no-sdio;
status = "okay";
};
&usdhc2 {
assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
assigned-clock-rates = <200000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
bus-width = <4>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
vmmc-supply = <&reg_usdhc2_vmmc>;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
pinctrl_hog: hoggrp {
fsl,pins = <
MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x19 /* TPM Reset */
MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x19 /* USB2 Hub Reset */
>;
};
pinctrl_gpio: gpiogrp {
fsl,pins = <
MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x19 /* GPIO0 */
MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x19 /* GPIO1 */
MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x19 /* GPIO2 */
MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x19 /* GPIO3 */
MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 /* GPIO4 */
MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x19 /* GPIO5 */
MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x19 /* GPIO6 */
MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x19 /* GPIO7 */
>;
};
pinctrl_pcie0: pcie0grp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x16 /* PCIE_PERST */
MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x16 /* W_DISABLE */
>;
};
pinctrl_reg_usdhc2: regusdhc2gpiogrp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x16
MX8MQ_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x16
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f
MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f
MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f
>;
};
pinctrl_qspi: qspigrp {
fsl,pins = <
MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82
MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
>;
};
pinctrl_ecspi2: ecspi2grp {
fsl,pins = <
MX8MQ_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x19
MX8MQ_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x19
MX8MQ_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x19
>;
};
pinctrl_ecspi2_cs: ecspi2csgrp {
fsl,pins = <
MX8MQ_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x19
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49
MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49
MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49
MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x49
MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x49
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>;
};
pinctrl_usdhc1_100mhz: usdhc1-100grp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>;
};
pinctrl_usdhc1_200mhz: usdhc1-200grp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x19
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100grp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200grp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xdf
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xdf
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xdf
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xdf
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xdf
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>;
};
pinctrl_usb0: usb0grp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x19
MX8MQ_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x19
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
>;
};
};

45
arch/arm/dts/imx8mq-librem5-r3.dtsi
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@@ -1,45 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
// Copyright (C) 2021 Purism SPC <kernel@puri.sm>
/dts-v1/;
/*
* This file describes hardware that is shared among r3 ("Dogwood") and
* later revisions of the Librem 5 so it has to be included in dts there.
*/
#include "imx8mq-librem5.dtsi"
/ {
model = "Purism Librem 5r3";
compatible = "purism,librem5r3", "purism,librem5", "fsl,imx8mq";
};
&accel_gyro {
mount-matrix = "1", "0", "0",
"0", "1", "0",
"0", "0", "-1";
};
&bq25895 {
ti,battery-regulation-voltage = <4200000>; /* uV */
ti,charge-current = <1500000>; /* uA */
ti,termination-current = <144000>; /* uA */
};
&camera_front {
pinctrl-0 = <&pinctrl_csi1>, <&pinctrl_r3_camera_pwr>;
shutdown-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>;
};
&iomuxc {
pinctrl_r3_camera_pwr: r3camerapwrgrp {
fsl,pins = <
MX8MQ_IOMUXC_SPDIF_RX_GPIO5_IO4 0x83
>;
};
};
&proximity {
proximity-near-level = <25>;
};

27
arch/arm/dts/imx8mq-librem5-r4.dts
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@@ -1,27 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
// Copyright (C) 2021 Purism SPC <kernel@puri.sm>
/dts-v1/;
#include "imx8mq-librem5-r3.dtsi"
/ {
model = "Purism Librem 5r4";
compatible = "purism,librem5r4", "purism,librem5", "fsl,imx8mq";
};
&bat {
maxim,rsns-microohm = <1667>;
};
&led_backlight {
led-max-microamp = <25000>;
};
&lcd_panel {
compatible = "ys,ys57pss36bh5gq";
};
&proximity {
proximity-near-level = <10>;
};

1382
arch/arm/dts/imx8mq-librem5.dtsi
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4
arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi
View File

@@ -9,3 +9,7 @@
&uart1 { /* console */
bootph-pre-ram;
};
&{/panel} {
compatible = "innolux,n125hce-gn1", "simple-panel";
};

354
arch/arm/dts/imx8mq-mnt-reform2.dts
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@@ -1,354 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2019-2021 MNT Research GmbH
* Copyright 2021 Lucas Stach <dev@lynxeye.de>
*/
/dts-v1/;
#include "imx8mq-nitrogen-som.dtsi"
/ {
model = "MNT Reform 2";
compatible = "mntre,reform2", "boundary,imx8mq-nitrogen8m-som", "fsl,imx8mq";
chassis-type = "laptop";
backlight: backlight {
compatible = "pwm-backlight";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_backlight>;
pwms = <&pwm2 0 10000 0>;
power-supply = <&reg_main_usb>;
enable-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
brightness-levels = <0 32 64 128 160 200 255>;
default-brightness-level = <6>;
};
panel {
compatible = "innolux,n125hce-gn1", "simple-panel";
power-supply = <&reg_main_3v3>;
backlight = <&backlight>;
no-hpd;
port {
panel_in: endpoint {
remote-endpoint = <&edp_bridge_out>;
};
};
};
pcie1_refclk: clock-pcie1-refclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
reg_main_5v: regulator-main-5v {
compatible = "regulator-fixed";
regulator-name = "5V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
reg_main_3v3: regulator-main-3v3 {
compatible = "regulator-fixed";
regulator-name = "3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
reg_main_usb: regulator-main-usb {
compatible = "regulator-fixed";
regulator-name = "USB_PWR";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&reg_main_5v>;
};
reg_main_1v8: regulator-main-1v8 {
compatible = "regulator-fixed";
regulator-name = "1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&reg_main_3v3>;
};
reg_main_1v2: regulator-main-1v2 {
compatible = "regulator-fixed";
regulator-name = "1V2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
vin-supply = <&reg_main_5v>;
};
sound {
compatible = "fsl,imx-audio-wm8960";
audio-cpu = <&sai2>;
audio-codec = <&wm8960>;
audio-routing =
"Headphone Jack", "HP_L",
"Headphone Jack", "HP_R",
"Ext Spk", "SPK_LP",
"Ext Spk", "SPK_LN",
"Ext Spk", "SPK_RP",
"Ext Spk", "SPK_RN",
"LINPUT1", "Mic Jack",
"Mic Jack", "MICB",
"LINPUT2", "Line In Jack",
"RINPUT2", "Line In Jack";
model = "wm8960-audio";
};
};
&dphy {
assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>;
assigned-clock-rates = <25000000>;
status = "okay";
};
&fec1 {
status = "okay";
};
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
wm8960: codec@1a {
compatible = "wlf,wm8960";
reg = <0x1a>;
clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>;
clock-names = "mclk";
#sound-dai-cells = <0>;
};
rtc@68 {
compatible = "nxp,pcf8523";
reg = <0x68>;
};
};
&i2c4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
clock-frequency = <400000>;
status = "okay";
edp_bridge: bridge@2c {
compatible = "ti,sn65dsi86";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_edp_bridge>;
reg = <0x2c>;
enable-gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
vccio-supply = <&reg_main_1v8>;
vpll-supply = <&reg_main_1v8>;
vcca-supply = <&reg_main_1v2>;
vcc-supply = <&reg_main_1v2>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
edp_bridge_in: endpoint {
remote-endpoint = <&mipi_dsi_out>;
};
};
port@1 {
reg = <1>;
edp_bridge_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
};
};
};
&lcdif {
assigned-clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>;
assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>;
/delete-property/assigned-clock-rates;
status = "okay";
};
&mipi_dsi {
status = "okay";
ports {
port@1 {
reg = <1>;
mipi_dsi_out: endpoint {
remote-endpoint = <&edp_bridge_in>;
};
};
};
};
&pcie1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie1>;
reset-gpio = <&gpio3 23 GPIO_ACTIVE_LOW>;
clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
<&clk IMX8MQ_CLK_PCIE2_AUX>,
<&clk IMX8MQ_CLK_PCIE2_PHY>,
<&pcie1_refclk>;
clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
status = "okay";
};
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>;
status = "okay";
};
&reg_1p8v {
vin-supply = <&reg_main_5v>;
};
&reg_snvs {
vin-supply = <&reg_main_5v>;
};
&reg_arm_dram {
vin-supply = <&reg_main_5v>;
};
&reg_dram_1p1v {
vin-supply = <&reg_main_5v>;
};
&reg_soc_gpu_vpu {
vin-supply = <&reg_main_5v>;
};
&sai2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai2>;
assigned-clocks = <&clk IMX8MQ_CLK_SAI2>;
assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
assigned-clock-rates = <25000000>;
fsl,sai-mclk-direction-output;
fsl,sai-asynchronous;
status = "okay";
};
&snvs_rtc {
status = "disabled";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&usb3_phy0 {
vbus-supply = <&reg_main_usb>;
status = "okay";
};
&usb3_phy1 {
vbus-supply = <&reg_main_usb>;
status = "okay";
};
&usb_dwc3_0 {
dr_mode = "host";
status = "okay";
};
&usb_dwc3_1 {
dr_mode = "host";
status = "okay";
};
&usdhc2 {
assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
assigned-clock-rates = <200000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
vqmmc-supply = <&reg_main_3v3>;
vmmc-supply = <&reg_main_3v3>;
bus-width = <4>;
status = "okay";
};
&iomuxc {
pinctrl_backlight: backlightgrp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x3
>;
};
pinctrl_edp_bridge: edpbridgegrp {
fsl,pins = <
MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x1
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000022
MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000022
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000022
MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000022
>;
};
pinctrl_pcie1: pcie1grp {
fsl,pins = <
MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x16
>;
};
pinctrl_pwm2: pwm2grp {
fsl,pins = <
MX8MQ_IOMUXC_SPDIF_RX_PWM2_OUT 0x3
>;
};
pinctrl_sai2: sai2grp {
fsl,pins = <
MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6
MX8MQ_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0xd6
MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
MX8MQ_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0xd6
MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6
MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x45
MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x45
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
>;
};
};

278
arch/arm/dts/imx8mq-nitrogen-som.dtsi
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@@ -1,278 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2018 Boundary Devices
* Copyright 2021 Lucas Stach <dev@lynxeye.de>
*/
#include "imx8mq.dtsi"
/ {
model = "Boundary Devices i.MX8MQ Nitrogen8M";
compatible = "boundary,imx8mq-nitrogen8m-som", "fsl,imx8mq";
chosen {
stdout-path = &uart1;
};
reg_1p8v: regulator-fixed-1v8 {
compatible = "regulator-fixed";
regulator-name = "1P8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
reg_snvs: regulator-fixed-snvs {
compatible = "regulator-fixed";
regulator-name = "VDD_SNVS";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
&{/opp-table/opp-800000000} {
opp-microvolt = <1000000>;
};
&{/opp-table/opp-1000000000} {
opp-microvolt = <1000000>;
};
&A53_0 {
cpu-supply = <&reg_arm_dram>;
};
&A53_1 {
cpu-supply = <&reg_arm_dram>;
};
&A53_2 {
cpu-supply = <&reg_arm_dram>;
};
&A53_3 {
cpu-supply = <&reg_arm_dram>;
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy0>;
fsl,magic-packet;
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <4>;
interrupt-parent = <&gpio1>;
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <300>;
};
};
};
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
i2c-mux@70 {
compatible = "nxp,pca9546";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1_pca9546>;
reg = <0x70>;
reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
#address-cells = <1>;
#size-cells = <0>;
i2c1a: i2c@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
reg_arm_dram: regulator@60 {
compatible = "fcs,fan53555";
reg = <0x60>;
regulator-name = "VDD_ARM_DRAM_1V";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
};
};
i2c1b: i2c@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
reg_dram_1p1v: regulator@60 {
compatible = "fcs,fan53555";
reg = <0x60>;
regulator-name = "NVCC_DRAM_1P1V";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-always-on;
};
};
i2c1c: i2c@2 {
reg = <2>;
#address-cells = <1>;
#size-cells = <0>;
reg_soc_gpu_vpu: regulator@60 {
compatible = "fcs,fan53555";
reg = <0x60>;
regulator-name = "VDD_SOC_GPU_VPU";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-always-on;
};
};
i2c1d: i2c@3 {
reg = <3>;
#address-cells = <1>;
#size-cells = <0>;
};
};
};
&pgc_gpu {
power-supply = <&reg_soc_gpu_vpu>;
};
&pgc_vpu {
power-supply = <&reg_soc_gpu_vpu>;
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&usdhc1 {
assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
assigned-clock-rates = <400000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
vqmmc-supply = <&reg_1p8v>;
vmmc-supply = <&reg_snvs>;
bus-width = <8>;
non-removable;
no-mmc-hs400;
no-sdio;
no-sd;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0xd1
MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0xd1
MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x1
MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x41
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000022
MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000022
>;
};
pinctrl_i2c1_pca9546: i2c1-pca9546grp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x49
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x45
MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x45
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>;
};
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
>;
};
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
>;
};
};

481
arch/arm/dts/imx8mq-phanbell.dts
View File

@@ -1,481 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2017-2019 NXP
*/
/dts-v1/;
#include "imx8mq.dtsi"
#include <dt-bindings/interrupt-controller/irq.h>
/ {
model = "Google i.MX8MQ Phanbell";
compatible = "google,imx8mq-phanbell", "fsl,imx8mq";
chosen {
stdout-path = &uart1;
};
memory@40000000 {
device_type = "memory";
reg = <0x00000000 0x40000000 0 0x40000000>;
};
pmic_osc: clock-pmic {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "pmic_osc";
};
reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
compatible = "regulator-fixed";
regulator-name = "VSD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
fan: gpio-fan {
compatible = "gpio-fan";
gpio-fan,speed-map = <0 0 8600 1>;
gpios = <&gpio3 5 GPIO_ACTIVE_HIGH>;
#cooling-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_fan>;
status = "okay";
};
};
&A53_0 {
cpu-supply = <&buck2>;
};
&A53_1 {
cpu-supply = <&buck2>;
};
&A53_2 {
cpu-supply = <&buck2>;
};
&A53_3 {
cpu-supply = <&buck2>;
};
&cpu_thermal {
trips {
cpu_alert0: trip0 {
temperature = <75000>;
hysteresis = <2000>;
type = "passive";
};
cpu_alert1: trip1 {
temperature = <80000>;
hysteresis = <2000>;
type = "passive";
};
cpu_crit0: trip3 {
temperature = <90000>;
hysteresis = <2000>;
type = "critical";
};
fan_toggle0: trip4 {
temperature = <65000>;
hysteresis = <10000>;
type = "active";
};
};
cooling-maps {
map0 {
trip = <&cpu_alert0>;
cooling-device =
<&A53_0 0 1>; /* Exclude highest OPP */
};
map1 {
trip = <&cpu_alert1>;
cooling-device =
<&A53_0 0 2>; /* Exclude two highest OPPs */
};
map4 {
trip = <&fan_toggle0>;
cooling-device = <&fan 0 1>;
};
};
};
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
pmic: pmic@4b {
compatible = "rohm,bd71837";
reg = <0x4b>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
#clock-cells = <0>;
clocks = <&pmic_osc>;
clock-output-names = "pmic_clk";
interrupt-parent = <&gpio1>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
regulators {
buck1: BUCK1 {
regulator-name = "buck1";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <1250>;
rohm,dvs-run-voltage = <900000>;
rohm,dvs-idle-voltage = <900000>;
rohm,dvs-suspend-voltage = <800000>;
};
buck2: BUCK2 {
regulator-name = "buck2";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1000000>;
regulator-boot-on;
regulator-always-on;
rohm,dvs-run-voltage = <1000000>;
rohm,dvs-idle-voltage = <900000>;
};
buck3: BUCK3 {
regulator-name = "buck3";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
regulator-boot-on;
rohm,dvs-run-voltage = <900000>;
};
buck4: BUCK4 {
regulator-name = "buck4";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
regulator-boot-on;
regulator-always-on;
rohm,dvs-run-voltage = <900000>;
};
buck5: BUCK5 {
regulator-name = "buck5";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1350000>;
regulator-boot-on;
regulator-always-on;
};
buck6: BUCK6 {
regulator-name = "buck6";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
buck7: BUCK7 {
regulator-name = "buck7";
regulator-min-microvolt = <1605000>;
regulator-max-microvolt = <1995000>;
regulator-boot-on;
regulator-always-on;
};
buck8: BUCK8 {
regulator-name = "buck8";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1400000>;
regulator-boot-on;
regulator-always-on;
};
ldo1: LDO1 {
regulator-name = "ldo1";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo2: LDO2 {
regulator-name = "ldo2";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-boot-on;
regulator-always-on;
};
ldo3: LDO3 {
regulator-name = "ldo3";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo4: LDO4 {
regulator-name = "ldo4";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
ldo5: LDO5 {
regulator-name = "ldo5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo6: LDO6 {
regulator-name = "ldo6";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
ldo7: LDO7 {
regulator-name = "ldo7";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
};
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy0>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <50000>;
};
};
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
bus-width = <4>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_usdhc2_vmmc>;
status = "okay";
};
&usb3_phy0 {
status = "okay";
};
&usb_dwc3_0 {
dr_mode = "otg";
status = "okay";
};
&usb3_phy1 {
status = "okay";
};
&usb_dwc3_1 {
dr_mode = "host";
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
>;
};
pinctrl_gpio_fan: gpiofangrp {
fsl,pins = <
MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x16
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
>;
};
pinctrl_pmic: pmicirqgrp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>;
};
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>;
};
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
>;
};
};

418
arch/arm/dts/imx8mq-pico-pi.dts
View File

@@ -1,418 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018 Wandboard, Org.
* Copyright 2017 NXP
*
* Author: Richard Hu <hakahu@gmail.com>
*/
/dts-v1/;
#include "imx8mq.dtsi"
#include <dt-bindings/interrupt-controller/irq.h>
/ {
model = "TechNexion PICO-PI-8M";
compatible = "technexion,pico-pi-imx8m", "fsl,imx8mq";
chosen {
stdout-path = &uart1;
};
pmic_osc: clock-pmic {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "pmic_osc";
};
reg_usb_otg_vbus: regulator-usb-otg-vbus {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_otg_vbus>;
compatible = "regulator-fixed";
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio3 14 GPIO_ACTIVE_LOW>;
};
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1 &pinctrl_enet_3v3>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy0>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
pmic: pmic@4b {
reg = <0x4b>;
compatible = "rohm,bd71837";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
clocks = <&pmic_osc>;
clock-names = "osc";
clock-output-names = "pmic_clk";
interrupt-parent = <&gpio1>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "irq";
regulators {
buck1: BUCK1 {
regulator-name = "buck1";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
regulator-boot-on;
regulator-ramp-delay = <1250>;
rohm,dvs-run-voltage = <900000>;
rohm,dvs-idle-voltage = <850000>;
rohm,dvs-suspend-voltage = <800000>;
};
buck2: BUCK2 {
regulator-name = "buck2";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
regulator-boot-on;
regulator-ramp-delay = <1250>;
rohm,dvs-run-voltage = <1000000>;
rohm,dvs-idle-voltage = <900000>;
};
buck3: BUCK3 {
regulator-name = "buck3";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
regulator-boot-on;
rohm,dvs-run-voltage = <1000000>;
};
buck4: BUCK4 {
regulator-name = "buck4";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
regulator-boot-on;
rohm,dvs-run-voltage = <1000000>;
};
buck5: BUCK5 {
regulator-name = "buck5";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1350000>;
regulator-boot-on;
};
buck6: BUCK6 {
regulator-name = "buck6";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
};
buck7: BUCK7 {
regulator-name = "buck7";
regulator-min-microvolt = <1605000>;
regulator-max-microvolt = <1995000>;
regulator-boot-on;
};
buck8: BUCK8 {
regulator-name = "buck8";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1400000>;
regulator-boot-on;
};
ldo1: LDO1 {
regulator-name = "ldo1";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo2: LDO2 {
regulator-name = "ldo2";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-boot-on;
regulator-always-on;
};
ldo3: LDO3 {
regulator-name = "ldo3";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
};
ldo4: LDO4 {
regulator-name = "ldo4";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
};
ldo5: LDO5 {
regulator-name = "ldo5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
};
ldo6: LDO6 {
regulator-name = "ldo6";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
};
ldo7: LDO7 {
regulator-name = "ldo7";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
};
};
};
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
};
&uart1 { /* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&usdhc1 {
assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
assigned-clock-rates = <400000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";
};
&usdhc2 {
assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
assigned-clock-rates = <200000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
bus-width = <4>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
status = "okay";
};
&usb3_phy0 {
status = "okay";
};
&usb3_phy1 {
status = "okay";
};
&usb_dwc3_1 {
dr_mode = "host";
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl_enet_3v3: enet3v3grp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x19
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f
MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f
>;
};
pinctrl_otg_vbus: otgvbusgrp {
fsl,pins = <
MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x19 /* USB OTG VBUS Enable */
>;
};
pinctrl_pmic: pmicirqgrp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49
MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49
MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x49
MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x49
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
>;
};
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85
>;
};
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
>;
};
};

1615
arch/arm/dts/imx8mq.dtsi
View File

File diff suppressed because it is too large Load Diff

1
arch/arm/dts/imx95-toradex-smarc-dev-u-boot.dtsi
View File

@@ -10,7 +10,6 @@
};
&gpio1 {
reg = <0 0x47400000 0 0x1000>, <0 0x47400040 0 0x40>;
bootph-pre-ram;
};

1
arch/arm/dts/imx95-verdin-wifi-dev-u-boot.dtsi
View File

@@ -26,7 +26,6 @@
};
&gpio1 {
reg = <0 0x47400000 0 0x1000>, <0 0x47400000 0 0x40>;
bootph-pre-ram;
ctrl-sleep-moci-hog {

48
arch/arm/include/asm/arch-imx9/ddr.h
View File

@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2022 NXP
* Copyright 2022-2026 NXP
*/
#ifndef __ASM_ARCH_IMX8M_DDR_H
@@ -100,6 +100,52 @@ struct dram_timing_info {
extern struct dram_timing_info dram_timing;
/* Quick Boot related */
#define DDRPHY_QB_CSR_SIZE 5168
#define DDRPHY_QB_ACSM_SIZE (4 * 1024)
#define DDRPHY_QB_MSB_SIZE 0x200
#define DDRPHY_QB_PSTATES 0
#define DDRPHY_QB_PST_SIZE (DDRPHY_QB_PSTATES * 4 * 1024)
/**
* This structure needs to be aligned with the one in OEI.
*/
struct ddrphy_qb_state {
u32 crc; /* Used for ensuring integrity in DRAM */
#define MAC_LENGTH 8 /* 256 bits, 32-bit aligned */
u32 mac[MAC_LENGTH]; /* For 95A0/1 use mac[0] to keep CRC32 value */
u8 trained_vrefca_a0;
u8 trained_vrefca_a1;
u8 trained_vrefca_b0;
u8 trained_vrefca_b1;
u8 trained_vrefdq_a0;
u8 trained_vrefdq_a1;
u8 trained_vrefdq_b0;
u8 trained_vrefdq_b1;
u8 trained_vrefdqu_a0;
u8 trained_vrefdqu_a1;
u8 trained_vrefdqu_b0;
u8 trained_vrefdqu_b1;
u8 trained_dramdfe_a0;
u8 trained_dramdfe_a1;
u8 trained_dramdfe_b0;
u8 trained_dramdfe_b1;
u8 trained_dramdca_a0;
u8 trained_dramdca_a1;
u8 trained_dramdca_b0;
u8 trained_dramdca_b1;
u16 qb_pll_upll_prog0;
u16 qb_pll_upll_prog1;
u16 qb_pll_upll_prog2;
u16 qb_pll_upll_prog3;
u16 qb_pll_ctrl1;
u16 qb_pll_ctrl4;
u16 qb_pll_ctrl5;
u16 csr[DDRPHY_QB_CSR_SIZE];
u16 acsm[DDRPHY_QB_ACSM_SIZE];
u16 pst[DDRPHY_QB_PST_SIZE];
};
void ddr_load_train_firmware(enum fw_type type);
int ddr_init(struct dram_timing_info *timing_info);
int ddr_cfg_phy(struct dram_timing_info *timing_info);

4
arch/arm/include/asm/arch-imx9/sys_proto.h
View File

@@ -23,6 +23,10 @@ int low_drive_freq_update(void *blob);
enum imx9_soc_voltage_mode soc_target_voltage_mode(void);
int get_reset_reason(bool sys, bool lm);
int scmi_get_boot_device_offset(unsigned long *img_off);
int scmi_get_boot_stage(u8 *stage);
u8 scmi_get_imgset_sel(void);
#define is_voltage_mode(mode) (soc_target_voltage_mode() == (mode))
#endif

2
arch/arm/include/asm/mach-imx/ahab.h
View File

@@ -8,7 +8,7 @@
#include <imx_container.h>
int ahab_auth_cntr_hdr(struct container_hdr *container, u16 length);
void *ahab_auth_cntr_hdr(struct container_hdr *container, u16 length);
int ahab_auth_release(void);
int ahab_verify_cntr_image(struct boot_img_t *img, int image_index);

15
arch/arm/include/asm/mach-imx/qb.h Normal file
View File

@@ -0,0 +1,15 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2026 NXP
*/
#ifndef __IMX_QB_H__
#define __IMX_QB_H__
#include <stdbool.h>
bool imx_qb_check(void);
int imx_qb(const char *ifname, const char *dev, bool save);
void spl_imx_qb_save(void);
#endif

30
arch/arm/mach-imx/Kconfig
View File

@@ -71,10 +71,38 @@ config CSF_SIZE
Define the maximum size for Command Sequence File (CSF) binary
this information is used to define the image boot data.
config IMX_QB
bool "Support Quickboot flow for Synopsis DDR PHY on iMX platforms"
default y
depends on IMX94 || IMX95 || IMX952
help
Enable the logic for saving DDR training data from volatile
memory to non-volatile storage. OEI uses the saved data to
run Quickboot flow and skip re-training the DDR PHY.
config SPL_IMX_QB
bool "Run qb save during SPL"
depends on SPL && IMX_QB
help
Automatically save DDR training data (Quickboot data)
to current boot device when needed (when OEI runs Training
flow and saves qb data to volatile memory).
config CMD_IMX_QB
bool "Support the 'qb' command"
default y
depends on IMX_QB
help
Enable qb command to write/erase DDR quick boot training
data to/from a chosen boot device. Using 'qb save/erase'
without arguments implies using the current boot device's
first bootable partition (e.g. boot0 for eMMC). For use in
uuu scripts, the boot device must be specified explicitly.
config CMD_BMODE
bool "Support the 'bmode' command"
default y
depends on ARCH_IMX8M || ARCH_MX7 || ARCH_MX6 || ARCH_MX5
depends on IMX95 || ARCH_IMX8M || ARCH_MX7 || ARCH_MX6 || ARCH_MX5
help
This enables the 'bmode' (bootmode) command for forcing
a boot from specific media.

1
arch/arm/mach-imx/Makefile
View File

@@ -80,6 +80,7 @@ endif
ifneq ($(CONFIG_XPL_BUILD),y)
obj-$(CONFIG_CMD_BMODE) += cmd_bmode.o
obj-$(CONFIG_CMD_HDMIDETECT) += cmd_hdmidet.o
obj-$(CONFIG_CMD_IMX_QB) += cmd_qb.o
obj-$(CONFIG_CMD_DEKBLOB) += cmd_dek.o
obj-$(CONFIG_CMD_NANDBCB) += cmd_nandbcb.o
endif

102
arch/arm/mach-imx/cmd_qb.c Normal file
View File

@@ -0,0 +1,102 @@
// SPDX-License-Identifier: GPL-2.0+
/**
* Copyright 2024-2026 NXP
*/
#include <command.h>
#include <spl.h>
#include <stdlib.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/sys_proto.h>
#include <asm/mach-imx/qb.h>
static void parse_qb_args(int argc, char * const argv[],
const char **ifname, const char **dev)
{
/* qb save/erase -> use boot device */
if (argc < 2) {
*ifname = "auto";
return;
}
*ifname = argv[1];
if (argc == 3)
*dev = argv[2];
}
static int do_qb(struct cmd_tbl *cmdtp, int flag, int argc,
char * const argv[], bool save)
{
const char *ifname, *dev;
parse_qb_args(argc, argv, &ifname, &dev);
if (imx_qb(ifname, dev, save))
return CMD_RET_FAILURE;
return CMD_RET_SUCCESS;
}
static int do_qb_check(struct cmd_tbl *cmdtp, int flag,
int argc, char * const argv[])
{
return imx_qb_check() ? CMD_RET_SUCCESS : CMD_RET_FAILURE;
}
static int do_qb_save(struct cmd_tbl *cmdtp, int flag,
int argc, char * const argv[])
{
return do_qb(cmdtp, flag, argc, argv, true);
}
static int do_qb_erase(struct cmd_tbl *cmdtp, int flag,
int argc, char * const argv[])
{
return do_qb(cmdtp, flag, argc, argv, false);
}
static struct cmd_tbl cmd_qb[] = {
U_BOOT_CMD_MKENT(check, 1, 1, do_qb_check, "", ""),
U_BOOT_CMD_MKENT(save, 3, 1, do_qb_save, "", ""),
U_BOOT_CMD_MKENT(erase, 3, 1, do_qb_erase, "", ""),
};
static int do_qbops(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
struct cmd_tbl *cp;
cp = find_cmd_tbl(argv[1], cmd_qb, ARRAY_SIZE(cmd_qb));
/* Drop the qb command */
argc--;
argv++;
if (!cp) {
printf("qb: %s: command not found\n", argv[0] ? argv[0] : " ");
return CMD_RET_USAGE;
}
if (argc > cp->maxargs) {
printf("qb %s: too many arguments: %d > %d\n", cp->name,
argc - 1, cp->maxargs - 1);
return CMD_RET_USAGE;
}
if (flag == CMD_FLAG_REPEAT && !cmd_is_repeatable(cp)) {
printf("qb %s: repeat flag set but command is not repeatable\n",
cp->name);
return CMD_RET_SUCCESS;
}
return cp->cmd(cmdtp, flag, argc, argv);
}
U_BOOT_CMD(
qb, 4, 1, do_qbops,
"DDR Quick Boot sub system",
"check - check if quick boot data is stored in mem by training flow\n"
"qb save [interface] [dev] - save quick boot data in NVM => trigger quick boot flow\n"
"qb erase [interface] [dev] - erase quick boot data from NVM => trigger training flow\n"
);

12
arch/arm/mach-imx/ele_ahab.c
View File

@@ -255,7 +255,7 @@ static void display_ahab_auth_ind(u32 event)
printf("%s\n", ele_ind_str[get_idx(ele_ind, resp_ind, ARRAY_SIZE(ele_ind))]);
}
int ahab_auth_cntr_hdr(struct container_hdr *container, u16 length)
void *ahab_auth_cntr_hdr(struct container_hdr *container, u16 length)
{
int err;
u32 resp;
@@ -271,9 +271,10 @@ int ahab_auth_cntr_hdr(struct container_hdr *container, u16 length)
printf("Authenticate container hdr failed, return %d, resp 0x%x\n",
err, resp);
display_ahab_auth_ind(resp);
return NULL;
}
return err;
return (void *)IMG_CONTAINER_BASE; /* Return authenticated container header */
}
int ahab_auth_release(void)
@@ -327,7 +328,6 @@ int authenticate_os_container(ulong addr)
{
struct container_hdr *phdr;
int i, ret = 0;
int err;
u16 length;
struct boot_img_t *img;
unsigned long s, e;
@@ -357,8 +357,8 @@ int authenticate_os_container(ulong addr)
debug("container length %u\n", length);
err = ahab_auth_cntr_hdr(phdr, length);
if (err) {
phdr = ahab_auth_cntr_hdr(phdr, length);
if (!phdr) {
ret = -EIO;
goto exit;
}
@@ -367,7 +367,7 @@ int authenticate_os_container(ulong addr)
/* Copy images to dest address */
for (i = 0; i < phdr->num_images; i++) {
img = (struct boot_img_t *)(addr +
img = (struct boot_img_t *)((ulong)phdr +
sizeof(struct container_hdr) +
i * sizeof(struct boot_img_t));

19
arch/arm/mach-imx/image-container.c
View File

@@ -240,6 +240,14 @@ static unsigned long get_boot_device_offset(void *dev, int dev_type)
return offset;
}
#if IS_ENABLED(CONFIG_ARCH_IMX9) && IS_ENABLED(CONFIG_SCMI_FIRMWARE)
int ret;
ret = scmi_get_boot_device_offset(&offset);
if (!ret)
return offset;
/* fall back to boot from primary set if get rom passover failed */
#endif
sec_boot = check_secondary_cnt_set(&sec_set_off);
if (sec_boot)
printf("Secondary set selected\n");
@@ -366,10 +374,17 @@ int spl_mmc_emmc_boot_partition(struct mmc *mmc)
part = EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config);
if (part == EMMC_BOOT_PART_BOOT1 || part == EMMC_BOOT_PART_BOOT2) {
unsigned long sec_set_off = 0;
bool sec_boot = false;
#if IS_ENABLED(CONFIG_ARCH_IMX9) && IS_ENABLED(CONFIG_SCMI_FIRMWARE)
u8 stage;
int ret;
ret = scmi_get_boot_stage(&stage);
if (!ret)
sec_boot = (stage == 0x9);
#else
unsigned long sec_set_off = 0;
sec_boot = check_secondary_cnt_set(&sec_set_off);
#endif
if (sec_boot)
part = (part == EMMC_BOOT_PART_BOOT1) ? EMMC_HWPART_BOOT2 : EMMC_HWPART_BOOT1;
} else if (part == EMMC_BOOT_PART_USER) {

16
arch/arm/mach-imx/imx8/ahab.c
View File

@@ -28,7 +28,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define AHAB_HASH_TYPE_MASK 0x00000700
#define AHAB_HASH_TYPE_SHA256 0
int ahab_auth_cntr_hdr(struct container_hdr *container, u16 length)
void *ahab_auth_cntr_hdr(struct container_hdr *container, u16 length)
{
int err;
@@ -37,10 +37,12 @@ int ahab_auth_cntr_hdr(struct container_hdr *container, u16 length)
err = sc_seco_authenticate(-1, SC_SECO_AUTH_CONTAINER,
SECO_LOCAL_SEC_SEC_SECURE_RAM_BASE);
if (err)
if (err) {
printf("Authenticate container hdr failed, return %d\n", err);
return NULL;
}
return err;
return (void *)SEC_SECURE_RAM_BASE; /* Return authenticated container header */
}
int ahab_auth_release(void)
@@ -126,7 +128,7 @@ int authenticate_os_container(ulong addr)
{
struct container_hdr *phdr;
int i, ret = 0;
int err;
__maybe_unused int err;
u16 length;
struct boot_img_t *img;
unsigned long s, e;
@@ -159,15 +161,15 @@ int authenticate_os_container(ulong addr)
debug("container length %u\n", length);
err = ahab_auth_cntr_hdr(phdr, length);
if (err) {
phdr = ahab_auth_cntr_hdr(phdr, length);
if (!phdr) {
ret = -EIO;
goto exit;
}
/* Copy images to dest address */
for (i = 0; i < phdr->num_images; i++) {
img = (struct boot_img_t *)(addr +
img = (struct boot_img_t *)((ulong)phdr +
sizeof(struct container_hdr) +
i * sizeof(struct boot_img_t));

5
arch/arm/mach-imx/imx8m/Kconfig
View File

@@ -79,11 +79,13 @@ config TARGET_IMX8MQ_PHANBELL
bool "imx8mq_phanbell"
select IMX8MQ
select IMX8M_LPDDR4
imply OF_UPSTREAM
config TARGET_IMX8MQ_REFORM2
bool "imx8mq_reform2"
select IMX8MQ
select IMX8M_LPDDR4
imply OF_UPSTREAM
config TARGET_IMX8MM_DATA_MODUL_EDM_SBC
bool "Data Modul eDM SBC i.MX8M Mini"
@@ -308,6 +310,7 @@ config TARGET_PICO_IMX8MQ
bool "Support Technexion Pico iMX8MQ"
select IMX8MQ
select IMX8M_LPDDR4
imply OF_UPSTREAM
config TARGET_IMX8MN_VAR_SOM
bool "Variscite imx8mn_var_som"
@@ -324,6 +327,7 @@ config TARGET_KONTRON_PITX_IMX8M
bool "Support Kontron pITX-imx8m"
select IMX8MQ
select IMX8M_LPDDR4
imply OF_UPSTREAM
config TARGET_TORADEX_SMARC_IMX8MP
bool "Support Toradex SMARC iMX8M Plus module"
@@ -426,6 +430,7 @@ config TARGET_LIBREM5
select IMX8MQ
select SUPPORT_SPL
select IMX8M_LPDDR4
imply OF_UPSTREAM
endchoice

6
arch/arm/mach-imx/imx9/Makefile
View File

@@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright 2022 NXP
# Copyright 2022,2026 NXP
obj-y += lowlevel_init.o
@@ -12,4 +12,6 @@ endif
ifneq ($(CONFIG_SPL_BUILD),y)
obj-y += imx_bootaux.o
endif
endif
obj-$(CONFIG_$(PHASE_)IMX_QB) += qb.o

1
arch/arm/mach-imx/imx9/clock.c
View File

@@ -478,6 +478,7 @@ u32 get_clk_src_rate(enum ccm_clk_src source)
switch (source) {
case ARM_PLL_CLK:
ctrl = readl(&ana_regs->arm_pll.ctrl.reg);
break;
case AUDIO_PLL_CLK:
ctrl = readl(&ana_regs->audio_pll.ctrl.reg);
break;

403
arch/arm/mach-imx/imx9/qb.c Normal file
View File

@@ -0,0 +1,403 @@
// SPDX-License-Identifier: GPL-2.0+
/**
* Copyright 2024-2026 NXP
*/
#include <dm/device-internal.h>
#include <dm/uclass.h>
#include <errno.h>
#include <imx_container.h>
#include <linux/bitfield.h>
#include <mmc.h>
#include <spi_flash.h>
#include <spl.h>
#include <stdlib.h>
#include <u-boot/crc.h>
#include <asm/arch/ddr.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/sys_proto.h>
#define QB_STATE_LOAD_SIZE SZ_64K
#define BLK_DEV 0
#define SPI_DEV 1
#define IMG_FLAGS_IMG_TYPE_MASK 0xF
#define IMG_FLAGS_IMG_TYPE(x) FIELD_GET(IMG_FLAGS_IMG_TYPE_MASK, (x))
#define IMG_TYPE_DDR_TDATA_DUMMY 0xD /* dummy DDR training data image */
static const struct {
const char *ifname;
const char *dev;
} imx_boot_devs[] = {
[BOOT_DEVICE_MMC1] = { "mmc", "0" },
[BOOT_DEVICE_MMC2] = { "mmc", "1" },
[BOOT_DEVICE_SPI] = { "spi", "" },
};
static int imx_qb_get_board_boot_device(void)
{
switch (get_boot_device()) {
case SD1_BOOT:
case MMC1_BOOT:
return BOOT_DEVICE_MMC1;
case SD2_BOOT:
case MMC2_BOOT:
return BOOT_DEVICE_MMC2;
case USB_BOOT:
return BOOT_DEVICE_BOARD;
case QSPI_BOOT:
return BOOT_DEVICE_SPI;
default:
return BOOT_DEVICE_NONE;
}
}
static int imx_qb_get_boot_dev_str(const char **ifname, const char **dev)
{
int boot_dev;
if (IS_ENABLED(CONFIG_XPL_BUILD))
boot_dev = spl_boot_device();
else
boot_dev = imx_qb_get_board_boot_device();
if (boot_dev == BOOT_DEVICE_NONE || boot_dev == BOOT_DEVICE_BOARD)
return -EINVAL;
*ifname = imx_boot_devs[boot_dev].ifname;
*dev = imx_boot_devs[boot_dev].dev;
return 0;
}
bool imx_qb_check(void)
{
struct ddrphy_qb_state *qb_state;
u32 size, crc;
/**
* Ensure CRC is not empty, the reason is that
* the data is invalidated after first save run
* or after it is overwritten.
*/
qb_state = (struct ddrphy_qb_state *)CONFIG_QB_SAVED_STATE_BASE;
size = sizeof(struct ddrphy_qb_state) - sizeof(qb_state->crc);
crc = crc32(0, (u8 *)qb_state->mac, size);
if (!qb_state->crc || crc != qb_state->crc)
return false;
return true;
}
static int imx_qb_get_blk_boot_part(const char * const ifname,
const char * const dev,
struct blk_desc **bdesc)
{
struct udevice *udev;
struct disk_partition info;
struct mmc *mmc;
int part;
int ret;
if (!IS_ENABLED(CONFIG_XPL_BUILD))
return blk_get_device_part_str(ifname, dev, bdesc, &info, 1);
/**
* SPL does not have access to part_get_info,
* so get the partition manually. Currently only
* supporting MMC devices.
*/
ret = blk_get_device_by_str(ifname, dev, bdesc);
if (ret < 0)
return -ENODEV;
if ((*bdesc)->uclass_id != UCLASS_MMC)
return -EOPNOTSUPP;
udev = dev_get_parent((*bdesc)->bdev);
mmc = mmc_get_mmc_dev(udev);
if (IS_SD(mmc) || mmc->part_config == MMCPART_NOAVAILABLE)
return 0;
part = EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config);
if (part == EMMC_BOOT_PART_BOOT1 || part == EMMC_BOOT_PART_BOOT2)
return part;
return 0;
}
static ulong imx_qb_get_boot_device_offset(void *dev, int dev_type)
{
struct blk_desc *bdesc;
switch (dev_type) {
case BLK_DEV:
bdesc = dev;
/* eMMC boot partition */
if (bdesc->hwpart)
return CONTAINER_HDR_EMMC_OFFSET;
return CONTAINER_HDR_MMCSD_OFFSET;
case SPI_DEV:
return CONTAINER_HDR_QSPI_OFFSET;
default:
return -EOPNOTSUPP;
}
}
static int imx_qb_parse_container(void *addr, u64 *qb_data_off)
{
struct container_hdr *phdr;
struct boot_img_t *img_entry;
u32 img_type, img_end;
int i;
phdr = addr;
if (phdr->tag != 0x87 || (phdr->version != 0x0 && phdr->version != 0x2))
return -EINVAL;
img_entry = addr + sizeof(struct container_hdr);
for (i = 0; i < phdr->num_images; i++) {
img_type = IMG_FLAGS_IMG_TYPE(img_entry->hab_flags);
if (img_type == IMG_TYPE_DDR_TDATA_DUMMY && img_entry->size == 0) {
/* Image entry pointing to DDR Training Data */
*qb_data_off = img_entry->offset;
return 0;
}
img_end = img_entry->offset + img_entry->size;
if (i + 1 < phdr->num_images) {
img_entry++;
if (img_end + QB_STATE_LOAD_SIZE == img_entry->offset) {
/* hole detected */
*qb_data_off = img_end;
return 0;
}
}
}
return -EINVAL;
}
static int imx_qb_get_dev_qbdata_offset(void *dev, int dev_type, ulong offset,
u64 *qbdata_offset)
{
struct blk_desc *bdesc;
u8 *buf;
ulong count;
int ret;
buf = malloc(CONTAINER_HDR_ALIGNMENT);
if (!buf)
return -ENOMEM;
switch (dev_type) {
case BLK_DEV:
bdesc = dev;
count = blk_dread(bdesc,
offset / bdesc->blksz,
CONTAINER_HDR_ALIGNMENT / bdesc->blksz,
buf);
if (count == 0) {
printf("Read container image from MMC/SD failed\n");
ret = -EIO;
goto imx_qb_get_dev_qbdata_offset_exit;
}
break;
case SPI_DEV:
if (!CONFIG_IS_ENABLED(SPI)) {
ret = -EOPNOTSUPP;
goto imx_qb_get_dev_qbdata_offset_exit;
}
ret = spi_flash_read_dm(dev, offset,
CONTAINER_HDR_ALIGNMENT, buf);
if (ret) {
printf("Read container header from SPI failed\n");
ret = -EIO;
goto imx_qb_get_dev_qbdata_offset_exit;
}
break;
default:
printf("Support for device %d not enabled\n", dev_type);
ret = -EOPNOTSUPP;
goto imx_qb_get_dev_qbdata_offset_exit;
}
ret = imx_qb_parse_container(buf, qbdata_offset);
imx_qb_get_dev_qbdata_offset_exit:
free(buf);
return ret;
}
static int imx_qb_get_qbdata_offset(void *dev, int dev_type,
u64 *qbdata_offset)
{
u64 cont_offset;
int ret, i;
cont_offset = imx_qb_get_boot_device_offset(dev, dev_type);
for (i = 0; i < 3; i++) {
ret = imx_qb_get_dev_qbdata_offset(dev, dev_type, cont_offset,
qbdata_offset);
if (ret == 0) {
(*qbdata_offset) += cont_offset;
break;
}
cont_offset += CONTAINER_HDR_ALIGNMENT;
}
return ret;
}
static int imx_qb_blk(const char * const ifname,
const char * const dev, bool save)
{
struct blk_desc *bdesc;
u64 offset;
u64 load_size;
int part, orig_part;
int ret;
part = imx_qb_get_blk_boot_part(ifname, dev, &bdesc);
if (part < 0) {
printf("Failed to find %s %s\n", ifname, dev);
return -ENODEV;
}
orig_part = bdesc->hwpart;
ret = blk_dselect_hwpart(bdesc, part);
if (ret && ret != -EMEDIUMTYPE) {
printf("Failed to select hwpart, ret %d\n", ret);
return ret;
}
ret = imx_qb_get_qbdata_offset(bdesc, BLK_DEV, &offset);
if (ret) {
printf("get_qbdata_offset failed, ret = %d\n", ret);
return ret;
}
offset /= bdesc->blksz;
load_size = QB_STATE_LOAD_SIZE / bdesc->blksz;
if (save) {
/* QB data is stored in DDR -> can use it as buf */
ret = blk_dwrite(bdesc, offset, load_size,
(const void *)CONFIG_QB_SAVED_STATE_BASE);
} else {
/* erase */
ret = blk_derase(bdesc, offset, load_size);
}
if (!ret) {
printf("Failed to write to block device\n");
return -EIO;
}
/* Return to original partition */
ret = blk_dselect_hwpart(bdesc, orig_part);
if (ret && ret != -EMEDIUMTYPE) {
printf("Failed to select hwpart, ret %d\n", ret);
return ret;
}
return 0;
}
static int imx_qb_spi(bool save)
{
struct udevice *flash;
u64 offset;
int ret;
if (!CONFIG_IS_ENABLED(SPI)) {
printf("SPI not enabled\n");
return -EOPNOTSUPP;
}
ret = uclass_first_device_err(UCLASS_SPI_FLASH, &flash);
if (ret) {
printf("SPI flash not found.\n");
return -ENODEV;
}
ret = imx_qb_get_qbdata_offset(flash, SPI_DEV, &offset);
if (ret) {
printf("get_qbdata_offset failed, ret = %d\n", ret);
return ret;
}
ret = spi_flash_erase_dm(flash, offset, QB_STATE_LOAD_SIZE);
if (ret)
return ret;
if (!save)
return 0;
/* QB data is stored in DDR -> can use it as buf */
ret = spi_flash_write_dm(flash, offset,
QB_STATE_LOAD_SIZE,
(const void *)CONFIG_QB_SAVED_STATE_BASE);
return ret;
}
int imx_qb(const char *ifname, const char *dev, bool save)
{
int ret;
ret = 0;
/* Try to use boot device */
if (!strcmp(ifname, "auto"))
ret = imx_qb_get_boot_dev_str(&ifname, &dev);
if (ret)
return ret;
if (save && !imx_qb_check())
return -EINVAL;
if (!strcmp(ifname, "spi"))
ret = imx_qb_spi(save);
else
ret = imx_qb_blk(ifname, dev, save);
if (ret)
return ret;
if (!save)
return 0;
/**
* invalidate qb_state mem so that at next boot
* the check function will fail and save won't happen
*/
memset((void *)CONFIG_QB_SAVED_STATE_BASE, 0,
sizeof(struct ddrphy_qb_state));
return 0;
}
void spl_imx_qb_save(void)
{
/* Save QB data on current boot device */
if (imx_qb("auto", "", true))
printf("QB save failed\n");
}

47
arch/arm/mach-imx/imx9/scmi/soc.c
View File

@@ -310,6 +310,13 @@ static struct mm_region imx9_mem_map[] = {
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* QB data */
.virt = CONFIG_QB_SAVED_STATE_BASE,
.phys = CONFIG_QB_SAVED_STATE_BASE,
.size = 0x200000UL, /* 2M */
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE
}, {
/* empty entry to split table entry 5 if needed when TEEs are used */
0,
@@ -745,6 +752,46 @@ void build_info(void)
puts("\n");
}
int scmi_get_boot_device_offset(unsigned long *img_off)
{
int ret;
rom_passover_t rom_data = {0};
ret = scmi_get_rom_data(&rom_data);
if (!ret)
*img_off = rom_data.img_ofs;
return 0;
}
int scmi_get_boot_stage(u8 *stage)
{
int ret;
rom_passover_t rom_data = {0};
ret = scmi_get_rom_data(&rom_data);
if (!ret)
*stage = rom_data.boot_stage;
return ret;
}
u8 scmi_get_imgset_sel(void)
{
rom_passover_t rdata = { 0 };
int ret = scmi_get_rom_data(&rdata);
if (!ret)
return rdata.img_set_sel;
return 0;
}
int boot_mode_getprisec(void)
{
return !!scmi_get_imgset_sel();
}
int arch_misc_init(void)
{
build_info();

21
arch/arm/mach-imx/imx9/soc.c
View File

@@ -198,26 +198,15 @@ static u32 get_cpu_variant_type(u32 type)
bool npu_disable = !!(val & BIT(13));
bool core1_disable = !!(val & BIT(15));
u32 pack_9x9_fused = BIT(4) | BIT(5) | BIT(17) | BIT(19) | BIT(24);
u32 nxp_recog = (val & GENMASK(23, 16)) >> 16;
u32 speed = (val & GENMASK(11, 6)) >> 6;
/* For iMX91 */
if (type == MXC_CPU_IMX91) {
switch (nxp_recog) {
case 0x9:
case 0xA:
if ((val2 & pack_9x9_fused) == pack_9x9_fused)
type = MXC_CPU_IMX9111;
break;
case 0xD:
case 0xE:
type = MXC_CPU_IMX9121;
break;
case 0xF:
case 0x10:
type = MXC_CPU_IMX9101;
break;
default:
break; /* 9131 as default */
}
if (speed == 0xf) /* 800Mhz arm */
type += 1;
return type;
}

97
arch/arm/mach-imx/mx6/module_fuse.c
View File

@@ -12,6 +12,54 @@
static struct fuse_entry_desc mx6_fuse_descs[] = {
#if defined(CONFIG_MX6ULL)
{MODULE_TSC, "/soc/bus@2000000/touchscreen@2040000", 0x430, 22},
{MODULE_TSC, "/soc/bus@2000000/tsc@2040000", 0x430, 22},
{MODULE_ADC2, "/soc/bus@2100000/adc@219c000", 0x430, 23},
{MODULE_EPDC, "/soc/bus@2200000/epdc@228c000", 0x430, 24},
{MODULE_ESAI, "/soc/bus@2000000/spba-bus@2000000/esai@2024000", 0x430, 25},
{MODULE_FLEXCAN1, "/soc/bus@2000000/can@2090000", 0x430, 26},
{MODULE_FLEXCAN2, "/soc/bus@2000000/can@2094000", 0x430, 27},
{MODULE_SPDIF, "/soc/bus@2000000/spba-bus@2000000/spdif@2004000", 0x440, 2},
{MODULE_EIM, "/soc/bus@2100000/memory-controller@21b8000", 0x440, 3},
{MODULE_EIM, "/soc/bus@2100000/weim@21b8000", 0x440, 3},
{MODULE_SD1, "/soc/bus@2100000/mmc@2190000", 0x440, 4},
{MODULE_SD1, "/soc/bus@2100000/usdhc@2190000", 0x440, 4},
{MODULE_SD2, "/soc/bus@2100000/mmc@2194000", 0x440, 5},
{MODULE_SD2, "/soc/bus@2100000/usdhc@2194000", 0x440, 5},
{MODULE_QSPI1, "/soc/bus@2100000/spi@21e0000", 0x440, 6},
{MODULE_QSPI1, "/soc/bus@2100000/qspi@21e0000", 0x440, 6},
{MODULE_GPMI, "/soc/nand-controller@1806000", 0x440, 7},
{MODULE_APBHDMA, "/soc/dma-controller@1804000", 0x440, 7},
{MODULE_APBHDMA, "/soc/dma-apbh@1804000", 0x440, 7},
{MODULE_LCDIF, "/soc/bus@2100000/lcdif@21c8000", 0x440, 8},
{MODULE_PXP, "/soc/bus@2100000/pxp@21cc000", 0x440, 9},
{MODULE_CSI, "/soc/bus@2100000/csi@21c4000", 0x440, 10},
{MODULE_ADC1, "/soc/bus@2100000/adc@2198000", 0x440, 11},
{MODULE_ENET1, "/soc/bus@2100000/ethernet@2188000", 0x440, 12},
{MODULE_ENET2, "/soc/bus@2000000/ethernet@20b4000", 0x440, 13},
{MODULE_DCP, "/soc/bus@2200000/dcp@2280000", 0x440, 14},
{MODULE_USB_OTG2, "/soc/bus@2100000/usb@2184200", 0x440, 15},
{MODULE_SAI2, "/soc/bus@2000000/spba-bus@2000000/sai@202c000", 0x440, 24},
{MODULE_SAI3, "/soc/bus@2000000/spba-bus@2000000/sai@2030000", 0x440, 24},
{MODULE_DCP_CRYPTO, "/soc/bus@2200000/dcp@2280000", 0x440, 25},
{MODULE_UART5, "/soc/bus@2100000/serial@21f4000", 0x440, 26},
{MODULE_UART6, "/soc/bus@2100000/serial@21fc000", 0x440, 26},
{MODULE_UART7, "/soc/bus@2000000/spba-bus@2000000/serial@2018000", 0x440, 26},
{MODULE_UART8, "/soc/bus@2200000/serial@2288000", 0x440, 26},
{MODULE_PWM5, "/soc/bus@2000000/pwm@20f0000", 0x440, 27},
{MODULE_PWM6, "/soc/bus@2000000/pwm@20f4000", 0x440, 27},
{MODULE_PWM7, "/soc/bus@2000000/pwm@20f8000", 0x440, 27},
{MODULE_PWM8, "/soc/bus@2000000/pwm@20fc000", 0x440, 27},
{MODULE_ECSPI3, "/soc/bus@2000000/spba-bus@2000000/spi@2010000", 0x440, 28},
{MODULE_ECSPI3, "/soc/bus@2000000/spba-bus@2000000/ecspi@2010000", 0x440, 28},
{MODULE_ECSPI4, "/soc/bus@2000000/spba-bus@2000000/spi@2014000", 0x440, 28},
{MODULE_ECSPI4, "/soc/bus@2000000/spba-bus@2000000/ecspi@2014000", 0x440, 28},
{MODULE_I2C3, "/soc/bus@2100000/i2c@21a8000", 0x440, 29},
{MODULE_I2C4, "/soc/bus@2100000/i2c@21f8000", 0x440, 29},
{MODULE_GPT2, "/soc/bus@2000000/timer@20e8000", 0x440, 30},
{MODULE_GPT2, "/soc/bus@2000000/gpt@20e8000", 0x440, 30},
{MODULE_EPIT2, "/soc/bus@2000000/epit@20d4000", 0x440, 31},
{MODULE_TSC, "/soc/aips-bus@2000000/tsc@2040000", 0x430, 22},
{MODULE_ADC2, "/soc/aips-bus@2100000/adc@219c000", 0x430, 23},
{MODULE_EPDC, "/soc/aips-bus@2200000/epdc@228c000", 0x430, 24},
@@ -90,6 +138,55 @@ static struct fuse_entry_desc mx6_fuse_descs[] = {
{MODULE_GPT2, "/soc/aips-bus@02000000/gpt@020e8000", 0x440, 30},
{MODULE_EPIT2, "/soc/aips-bus@02000000/epit@020d4000", 0x440, 31},
#elif defined(CONFIG_MX6UL)
{MODULE_TSC, "/soc/bus@2000000/touchscreen@2040000", 0x430, 22},
{MODULE_TSC, "/soc/bus@2000000/tsc@2040000", 0x430, 22},
{MODULE_ADC2, "/soc/bus@2100000/adc@219c000", 0x430, 23},
{MODULE_SIM1, "/soc/bus@2100000/sim@218c000", 0x430, 24},
{MODULE_SIM2, "/soc/bus@2100000/sim@21b4000", 0x430, 25},
{MODULE_FLEXCAN1, "/soc/bus@2000000/can@2090000", 0x430, 26},
{MODULE_FLEXCAN2, "/soc/bus@2000000/can@2094000", 0x430, 27},
{MODULE_SPDIF, "/soc/bus@2000000/spba-bus@2000000/spdif@2004000", 0x440, 2},
{MODULE_EIM, "/soc/bus@2100000/memory-controller@21b8000", 0x440, 3},
{MODULE_EIM, "/soc/bus@2100000/weim@21b8000", 0x440, 3},
{MODULE_SD1, "/soc/bus@2100000/mmc@2190000", 0x440, 4},
{MODULE_SD1, "/soc/bus@2100000/usdhc@2190000", 0x440, 4},
{MODULE_SD2, "/soc/bus@2100000/mmc@2194000", 0x440, 5},
{MODULE_SD2, "/soc/bus@2100000/usdhc@2194000", 0x440, 5},
{MODULE_QSPI1, "/soc/bus@2100000/spi@21e0000", 0x440, 6},
{MODULE_QSPI1, "/soc/bus@2100000/qspi@21e0000", 0x440, 6},
{MODULE_GPMI, "/soc/nand-controller@1806000", 0x440, 7},
{MODULE_APBHDMA, "/soc/dma-controller@1804000", 0x440, 7},
{MODULE_APBHDMA, "/soc/dma-apbh@1804000", 0x440, 7},
{MODULE_LCDIF, "/soc/bus@2100000/lcdif@21c8000", 0x440, 8},
{MODULE_PXP, "/soc/bus@2100000/pxp@21cc000", 0x440, 9},
{MODULE_CSI, "/soc/bus@2100000/csi@21c4000", 0x440, 10},
{MODULE_ADC1, "/soc/bus@2100000/adc@2198000", 0x440, 11},
{MODULE_ENET1, "/soc/bus@2100000/ethernet@2188000", 0x440, 12},
{MODULE_ENET2, "/soc/bus@2000000/ethernet@20b4000", 0x440, 13},
{MODULE_CAAM, "/soc/bus@2100000/crypto@2140000", 0x440, 14},
{MODULE_CAAM, "/soc/bus@2100000/caam@2140000", 0x440, 14},
{MODULE_USB_OTG2, "/soc/bus@2100000/usb@2184200", 0x440, 15},
{MODULE_SAI2, "/soc/bus@2000000/spba-bus@2000000/sai@202c000", 0x440, 24},
{MODULE_SAI3, "/soc/bus@2000000/spba-bus@2000000/sai@2030000", 0x440, 24},
{MODULE_BEE, "/soc/bus@2000000/bee@2044000", 0x440, 25},
{MODULE_UART5, "/soc/bus@2100000/serial@21f4000", 0x440, 26},
{MODULE_UART6, "/soc/bus@2100000/serial@21fc000", 0x440, 26},
{MODULE_UART7, "/soc/bus@2000000/spba-bus@2000000/serial@2018000", 0x440, 26},
{MODULE_UART8, "/soc/bus@2000000/spba-bus@2000000/serial@2024000", 0x440, 26},
{MODULE_PWM5, "/soc/bus@2000000/pwm@20f0000", 0x440, 27},
{MODULE_PWM6, "/soc/bus@2000000/pwm@20f4000", 0x440, 27},
{MODULE_PWM7, "/soc/bus@2000000/pwm@20f8000", 0x440, 27},
{MODULE_PWM8, "/soc/bus@2000000/pwm@20fc000", 0x440, 27},
{MODULE_ECSPI3, "/soc/bus@2000000/spba-bus@2000000/spi@2010000", 0x440, 28},
{MODULE_ECSPI3, "/soc/bus@2000000/spba-bus@2000000/ecspi@2010000", 0x440, 28},
{MODULE_ECSPI4, "/soc/bus@2000000/spba-bus@2000000/spi@2014000", 0x440, 28},
{MODULE_ECSPI4, "/soc/bus@2000000/spba-bus@2000000/ecspi@2014000", 0x440, 28},
{MODULE_I2C3, "/soc/bus@2100000/i2c@21a8000", 0x440, 29},
{MODULE_I2C4, "/soc/bus@2100000/i2c@21f8000", 0x440, 29},
{MODULE_GPT2, "/soc/bus@2000000/timer@20e8000", 0x440, 30},
{MODULE_GPT2, "/soc/bus@2000000/gpt@20e8000", 0x440, 30},
{MODULE_EPIT2, "/soc/bus@2000000/epit@20d4000", 0x440, 31},
{MODULE_TSC, "/soc/aips-bus@2000000/tsc@2040000", 0x430, 22},
{MODULE_ADC2, "/soc/aips-bus@2100000/adc@219c000", 0x430, 23},
{MODULE_SIM1, "/soc/aips-bus@2100000/sim@218c000", 0x430, 24},

1
arch/arm/mach-imx/priblob.c
View File

@@ -10,6 +10,7 @@
* to decrypt an encrypted boot image.
*/
#include <config.h>
#include <asm/io.h>
#include <command.h>
#include <fsl_sec.h>

2
board/boundary/nitrogen6x/nitrogen6x.c
View File

@@ -909,8 +909,10 @@ static const struct boot_mode board_boot_modes[] = {
int misc_init_r(void)
{
#if defined(CONFIG_VIDEO_IPUV3)
gpio_request(RGB_BACKLIGHT_GP, "lvds backlight");
gpio_request(LVDS_BACKLIGHT_GP, "lvds backlight");
#endif
gpio_request(GP_USB_OTG_PWR, "usbotg power");
gpio_request(IMX_GPIO_NR(7, 12), "usbh1 hub reset");
gpio_request(IMX_GPIO_NR(2, 2), "back");

2
board/compulab/cm_fx6/cm_fx6.c
View File

@@ -778,7 +778,7 @@ static int sata_imx_remove(struct udevice *dev)
return 0;
}
struct ahci_ops sata_imx_ops = {
static const struct ahci_ops sata_imx_ops = {
.port_status = dwc_ahsata_port_status,
.reset = dwc_ahsata_bus_reset,
.scan = dwc_ahsata_scan,

1
board/kontron/pitx_imx8m/MAINTAINERS
View File

@@ -1,7 +1,6 @@
Kontron pITX-imx8m Board
M: Heiko Thiery <heiko.thiery@gmail.com>
S: Maintained
F: arch/arm/dts/imx8mq-kontron-pitx-imx8m*
F: board/kontron/pitx_imx8m/*
F: include/configs/kontron_pitx_imx8m.h
F: configs/kontron_pitx_imx8m_defconfig

2
board/nxp/imx8mp_evk/spl.c
View File

@@ -65,7 +65,7 @@ int power_init_board(void)
* Enable DVS control through PMIC_STBY_REQ and
* set B1_ENMODE=1 (ON by PMIC_ON_REQ=H)
*/
if (CONFIG_IS_ENABLED(IMX8M_VDD_SOC_850MV))
if (IS_ENABLED(CONFIG_IMX8M_VDD_SOC_850MV))
pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14);
else
pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1C);

6
board/nxp/imx94_evk/spl.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2025 NXP
* Copyright 2025-2026 NXP
*/
#include <hang.h>
@@ -14,6 +14,7 @@
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/ele_api.h>
#include <asm/mach-imx/qb.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -44,6 +45,9 @@ void spl_board_init(void)
ret = ele_start_rng();
if (ret)
printf("Fail to start RNG: %d\n", ret);
if (IS_ENABLED(CONFIG_SPL_IMX_QB))
spl_imx_qb_save();
}
static void xspi_nor_reset(void)

4
board/nxp/imx952_evk/spl.c
View File

@@ -8,6 +8,7 @@
#include <asm/gpio.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/ele_api.h>
#include <asm/mach-imx/qb.h>
#include <asm/sections.h>
#include <hang.h>
#include <init.h>
@@ -44,6 +45,9 @@ void spl_board_init(void)
ret = ele_start_rng();
if (ret)
printf("Fail to start RNG: %d\n", ret);
if (IS_ENABLED(CONFIG_SPL_IMX_QB))
spl_imx_qb_save();
}
static void xspi_nor_reset(void)

6
board/nxp/imx95_evk/spl.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2025 NXP
* Copyright 2025-2026 NXP
*/
#include <hang.h>
@@ -13,6 +13,7 @@
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/ele_api.h>
#include <asm/mach-imx/qb.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -41,6 +42,9 @@ void spl_board_init(void)
ret = ele_start_rng();
if (ret)
printf("Fail to start RNG: %d\n", ret);
if (IS_ENABLED(CONFIG_SPL_IMX_QB))
spl_imx_qb_save();
}
void board_init_f(ulong dummy)

1
board/purism/librem5/MAINTAINERS
View File

@@ -2,7 +2,6 @@ PURISM LIBREM5 PHONE
M: Angus Ainslie <angus@akkea.ca>
R: kernel@puri.sm
S: Supported
F: arch/arm/dts/imx8mq-librem5*
F: board/purism/librem5/
F: configs/librem5_defconfig
F: include/configs/librem5.h

13
common/spl/spl_imx_container.c
View File

@@ -88,6 +88,7 @@ static int read_auth_container(struct spl_image_info *spl_image,
struct spl_load_info *info, ulong offset)
{
struct container_hdr *container = NULL;
struct container_hdr *authhdr;
u16 length;
int i, size, ret = 0;
@@ -140,15 +141,19 @@ static int read_auth_container(struct spl_image_info *spl_image,
}
}
authhdr = container;
#ifdef CONFIG_AHAB_BOOT
ret = ahab_auth_cntr_hdr(container, length);
if (ret)
authhdr = ahab_auth_cntr_hdr(authhdr, length);
if (!authhdr) {
ret = -EINVAL;
goto end_auth;
}
#endif
for (i = 0; i < container->num_images; i++) {
for (i = 0; i < authhdr->num_images; i++) {
struct boot_img_t *image = read_auth_image(spl_image, info,
container, i,
authhdr, i,
offset);
if (!image) {

2
configs/imx8mq_phanbell_defconfig
View File

@@ -7,7 +7,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x400000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx8mq-phanbell"
CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mq-phanbell"
CONFIG_TARGET_IMX8MQ_PHANBELL=y
CONFIG_DM_RESET=y
CONFIG_SYS_MONITOR_LEN=524288

2
configs/imx8mq_reform2_defconfig
View File

@@ -10,7 +10,7 @@ CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx8mq-mnt-reform2"
CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mq-mnt-reform2"
CONFIG_TARGET_IMX8MQ_REFORM2=y
CONFIG_DM_RESET=y
CONFIG_SYS_MONITOR_LEN=524288

2
configs/kontron_pitx_imx8m_defconfig
View File

@@ -7,7 +7,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x300000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx8mq-kontron-pitx-imx8m"
CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mq-kontron-pitx-imx8m"
CONFIG_TARGET_KONTRON_PITX_IMX8M=y
CONFIG_DM_RESET=y
CONFIG_SYS_MONITOR_LEN=524288

2
configs/librem5_defconfig
View File

@@ -10,7 +10,7 @@ CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_SYS_I2C_MXC_I2C4=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx8mq-librem5-r4"
CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mq-librem5-r4"
CONFIG_TARGET_LIBREM5=y
CONFIG_DM_RESET=y
CONFIG_SYS_MONITOR_LEN=524288

2
configs/pico-imx8mq_defconfig
View File

@@ -10,7 +10,7 @@ CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx8mq-pico-pi"
CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mq-pico-pi"
CONFIG_TARGET_PICO_IMX8MQ=y
CONFIG_DM_RESET=y
CONFIG_SYS_MONITOR_LEN=524288

1
doc/board/nxp/index.rst
View File

@@ -30,3 +30,4 @@ NXP Semiconductors
mx6ullevk
rproc
psb
quickboot

59
doc/board/nxp/quickboot.rst Normal file
View File

@@ -0,0 +1,59 @@
.. SPDX-License-Identifier: GPL-2.0+
Copyright 2026 NXP
DDR QuickBoot flow
------------------
Some NXP SoCs (which use OEI - iMX943, iMX95, iMX952 etc.) support saving
DDR training data (collected by OEI during Training flow) from volatile
to non-volatile memory, which is then available to OEI at next cold reboot.
OEI uses the saved data to run Quickboot flow and avoid training the DDR again.
This significantly reduces the boot time.
The location of the quickboot data in NVM is a space left in the bootloader by
mkimage, with the size of 64K. The qb command searches for this space to
save the data. Thus, the NVM should also be a boot device and contain
the bootloader at the time of the saving.
U-Boot provides no authentication for quickboot data, only its integrity
is verified via the CRC32. The authentication is done in OEI. With
the exception of iMX95 A0/A1, which use CRC32 as well for verifying
the data, the rest of the SoCs use ELE to verify the MAC stored
in the ddrphy_qb_state structure.
If the quickboot data in memory is not valid (CRC32 check fails),
U-Boot does not save it to NVM. So, if OEI runs Quickboot flow -> no
data is written to volatile memory -> invalid data -> no saving happens
(qb save fails during qb check).
After successful saving, U-Boot clears the data in volatile memory so
that qb check fails at next reboot and the NVM isn't accessed again.
There are 2 ways to save this data, both can be enabled:
1. automatically, in SPL (by enabling CONFIG_SPL_IMX_QB)
- this will save the data on the current boot device (e.g. SD)
- other configs specific to the boot device need to be enabled (CONFIG_SPL_MMC_WRITE for saving to eMMC/SD)
- use for: automating qb save / saving quickboot data if using Falcon mode (skipping U-Boot proper)
2. using qb command in U-Boot console (by enabling CONFIG_CMD_IMX_QB)
- supports saving on the current boot device, or on another, specified device.
- supports specifying the hwpartition for eMMC (for booting from boot0/boot1)
- if flashing via uuu, the command can be added in an uuu script (boot device needs to be specified)
- use 'qb erase' to force DDR re-training
- use for: saving quickboot data during flashing / controlling the NVM to save to / forcing re-training
::
# To save/erase on current boot device
# For eMMC boot1, mmc 0:2 has to be specified explicitly
=> qb save/erase
# To save/erase on other boot device
=> qb save/erase mmc 0 # eMMC boot0
=> qb save/erase mmc 0:1 # eMMC boot0
=> qb save/erase mmc 0:2 # eMMC boot1
=> qb save/erase mmc 1 # SD
=> qb save/erase spi # NOR SPI

7
drivers/ddr/imx/imx9/Kconfig
View File

@@ -29,4 +29,11 @@ config SAVED_DRAM_TIMING_BASE
after DRAM is trained, need to save the dram related timming
info into memory for low power use.
config QB_SAVED_STATE_BASE
hex "Define the base address for saved QuickBoot state"
default 0x8fe00000
help
Once DRAM is trained, the resulted training info is
saved into memory in order to be reachable from U-Boot.
endmenu

4
drivers/i2c/imx_lpi2c.c
View File

@@ -239,7 +239,6 @@ static int bus_i2c_stop(struct udevice *bus)
start_time = get_timer(0);
while (1) {
status = readl(&regs->msr);
result = imx_lpci2c_check_clear_error(regs);
/* stop detect flag */
if (status & LPI2C_MSR_SDF_MASK) {
/* clear stop flag */
@@ -250,10 +249,13 @@ static int bus_i2c_stop(struct udevice *bus)
if (get_timer(start_time) > LPI2C_NACK_TOUT_MS) {
debug("stop timeout\n");
result = imx_lpci2c_check_clear_error(regs);
return -ETIMEDOUT;
}
}
result = imx_lpci2c_check_clear_error(regs);
return result;
}

4
drivers/net/Kconfig
View File

@@ -1018,8 +1018,8 @@ config FSL_ENETC
config FSL_ENETC_NETC_BLK_CTRL
bool "NXP ENETC NETC blocks control driver"
depends on FSL_ENETC
depends on IMX95 || IMX94
default y if IMX95 || IMX94
depends on IMX95 || IMX94 || IMX952
default y if IMX95 || IMX94 || IMX952
help
This driver configures Integrated Endpoint Register Block (IERB) and
Privileged Register Block (PRB) of NETC. For i.MX platforms, it also

46
drivers/net/fsl_enetc.c
View File

@@ -18,6 +18,7 @@
#include <asm/io.h>
#include <pci.h>
#include <miiphy.h>
#include <linux/bitfield.h>
#include <linux/bug.h>
#include <linux/delay.h>
#include <linux/build_bug.h>
@@ -74,10 +75,36 @@ static int enetc_is_ls1028a(struct udevice *dev)
pplat->vendor == PCI_VENDOR_ID_FREESCALE;
}
static int enetc_dev_id_imx(struct udevice *dev)
{
if (IS_ENABLED(CONFIG_IMX952)) {
int bus_devfn;
u32 reg[5];
int error;
error = dev_read_u32_array(dev, "reg", reg, ARRAY_SIZE(reg));
if (error)
return error;
bus_devfn = (reg[0] >> 8) & 0xffff;
switch (bus_devfn) {
case 0:
return 0;
case 0x100:
return 1;
default:
return -EINVAL;
}
}
return PCI_DEV(pci_get_devfn(dev)) >> 3;
}
static int enetc_dev_id(struct udevice *dev)
{
if (enetc_is_imx95(dev))
return PCI_DEV(pci_get_devfn(dev)) >> 3;
return enetc_dev_id_imx(dev);
if (enetc_is_ls1028a(dev))
return PCI_FUNC(pci_get_devfn(dev));
@@ -396,7 +423,7 @@ static int enetc_init_sgmii(struct udevice *dev)
/* set up MAC for RGMII */
static void enetc_init_rgmii(struct udevice *dev, struct phy_device *phydev)
{
u32 old_val, val, dpx = 0;
u32 old_val, val = 0;
old_val = val = enetc_read_mac_port(dev, ENETC_PM_IF_MODE);
@@ -416,15 +443,14 @@ static void enetc_init_rgmii(struct udevice *dev, struct phy_device *phydev)
val |= ENETC_PM_IFM_SSP_10;
}
if (enetc_is_imx95(dev))
dpx = ENETC_PM_IFM_FULL_DPX_IMX;
if (enetc_is_imx95(dev))
val = u32_replace_bits(val,
phydev->duplex == DUPLEX_FULL ? 0 : 1,
ENETC_PM_IFM_FULL_DPX_IMX);
else if (enetc_is_ls1028a(dev))
dpx = ENETC_PM_IFM_FULL_DPX_LS;
if (phydev->duplex == DUPLEX_FULL)
val |= dpx;
else
val &= ~dpx;
val = u32_replace_bits(val,
phydev->duplex == DUPLEX_FULL ? 1 : 0,
ENETC_PM_IFM_FULL_DPX_LS);
if (val == old_val)
return;

72
drivers/net/fsl_enetc_netc_blk_ctrl.c
View File

@@ -35,6 +35,7 @@
#define MII_PROT_RGMII 0x2
#define MII_PROT_SERIAL 0x3
#define MII_PROT(port, prot) (((prot) & 0xf) << ((port) << 2))
#define MII_PROT_GET(reg, port) (((reg) >> ((port) << 2)) & 0xf)
#define IMX95_CFG_LINK_PCS_PROT(a) (0x8 + (a) * 4)
#define PCS_PROT_1G_SGMII BIT(0)
@@ -97,6 +98,9 @@
#define IMX94_TIMER1_ID 1
#define IMX94_TIMER2_ID 2
#define IMX952_ENETC0_BUS_DEVFN 0x0
#define IMX952_ENETC1_BUS_DEVFN 0x100
/* Flags for different platforms */
#define NETC_HAS_NETCMIX BIT(0)
@@ -567,6 +571,69 @@ static int netc_prb_check_error(struct netc_blk_ctrl *priv)
return 0;
}
static int imx952_netcmix_init(struct udevice *dev)
{
struct netc_blk_ctrl *priv = dev_get_priv(dev);
ofnode child, gchild;
phy_interface_t interface;
int bus_devfn, mii_proto;
u32 val;
/* Default setting */
val = MII_PROT(0, MII_PROT_RGMII) | MII_PROT(1, MII_PROT_RGMII);
/* Update the link MII protocol through parsing phy-mode */
dev_for_each_subnode(child, dev) {
if (!ofnode_is_enabled(child))
continue;
ofnode_for_each_subnode(gchild, child) {
if (!ofnode_is_enabled(gchild))
continue;
if (!ofnode_device_is_compatible(gchild, "pci1131,e101"))
continue;
bus_devfn = netc_of_pci_get_bus_devfn(gchild);
if (bus_devfn < 0)
return -EINVAL;
interface = ofnode_read_phy_mode(gchild);
if (interface == -1)
continue;
mii_proto = netc_get_link_mii_protocol(interface);
if (mii_proto < 0)
return -EINVAL;
switch (bus_devfn) {
case IMX952_ENETC0_BUS_DEVFN:
val &= ~CFG_LINK_MII_PORT_0;
val |= FIELD_PREP(CFG_LINK_MII_PORT_0, mii_proto);
break;
case IMX952_ENETC1_BUS_DEVFN:
val &= ~CFG_LINK_MII_PORT_1;
val |= FIELD_PREP(CFG_LINK_MII_PORT_1, mii_proto);
break;
default:
return -EINVAL;
}
}
}
if (MII_PROT_GET(val, 1) == MII_PROT_SERIAL) {
/* Configure Link I/O variant */
netc_reg_write(priv->netcmix, IMX95_CFG_LINK_IO_VAR,
IO_VAR(1, IO_VAR_16FF_16G_SERDES));
/* Configure Link 2 PCS protocol */
netc_reg_write(priv->netcmix, IMX95_CFG_LINK_PCS_PROT(1),
PCS_PROT_2500M_SGMII);
}
netc_reg_write(priv->netcmix, IMX95_CFG_LINK_MII_PROT, val);
return 0;
}
static const struct netc_devinfo imx95_devinfo = {
.netcmix_init = imx95_netcmix_init,
.ierb_init = imx95_ierb_init,
@@ -578,9 +645,14 @@ static const struct netc_devinfo imx94_devinfo = {
.xpcs_port_init = imx94_netc_xpcs_port_init,
};
static const struct netc_devinfo imx952_devinfo = {
.netcmix_init = imx952_netcmix_init,
};
static const struct udevice_id netc_blk_ctrl_match[] = {
{ .compatible = "nxp,imx95-netc-blk-ctrl", .data = (ulong)&imx95_devinfo },
{ .compatible = "nxp,imx94-netc-blk-ctrl", .data = (ulong)&imx94_devinfo },
{ .compatible = "nxp,imx952-netc-blk-ctrl", .data = (ulong)&imx952_devinfo },
{},
};

2
drivers/net/phy/nxp-c45-tja11xx.c
View File

@@ -343,7 +343,7 @@ static int nxp_c45_probe(struct phy_device *phydev)
{
struct nxp_c45_phy *priv;
priv = devm_kzalloc(phydev->priv, sizeof(*priv), GFP_KERNEL);
priv = kzalloc(sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;

2
drivers/power/regulator/pfuze100.c
View File

@@ -550,6 +550,8 @@ static int pfuze100_regulator_val(struct udevice *dev, int op, int *uV)
return -EINVAL;
}
val = pmic_reg_read(dev->parent, desc->vsel_reg);
if (val < 0)
return val;
if (desc->high_volt_mask && (val & desc->high_volt_mask)) {
min_uV = desc->high_volt_desc->min_uV;
uV_step = desc->high_volt_desc->uV_step;