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serial: lpuart: Fix RX FIFO Enable bitmask

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The Receive FIFO Enable (RXFE) field in the LPUART FIFO register is
bit 3 on all supported architectures. The define has been wrong since
it was introduced: for non-i.MX8/i.MXRT it set bit 6, which on LS102xA
is read-only-as-zero, so the bug went unnoticed.

NXP confirmed bit 3 is correct everywhere, so drop the ARCH-based
selection.

Link: 9498bcc514
Link: https://lore.kernel.org/u-boot/dc163ea7-9063-4dfb-a39a-e643c0bcccf1@oss.nxp.com/
Fixes: 6209e14cb0 ("serial: lpuart: add 32-bit registers lpuart support")
Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Reviewed-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
This commit is contained in:
Emanuele Ghidoli
2026-05-28 15:49:06 +02:00
committed by Tom Rini
parent 6c636eabbd
commit e65a87e959
1 changed files with 0 additions and 4 deletions
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4
drivers/serial/serial_lpuart.c
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@@ -53,11 +53,7 @@
#define FIFO_RXSIZE_MASK 0x7
#define FIFO_RXSIZE_OFF 0
#define FIFO_TXFE 0x80
#if defined(CONFIG_ARCH_IMX8) || defined(CONFIG_ARCH_IMXRT)
#define FIFO_RXFE 0x08
#else
#define FIFO_RXFE 0x40
#endif
#define WATER_TXWATER_OFF 0
#define WATER_RXWATER_OFF 16