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riscv: dts: th1520: Describe GMACs and enable them on Lichee Pi 4A

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TH1520 SoC ships two MAC controllers based on Designware Ethernet IP
that are capable of Gigabit operation. Describe them in SoC devicetree
and enable them for Lichee Pi 4A.

Signed-off-by: Yao Zi <ziyao@disroot.org>
Acked-by: Leo Yu-Chi Liang <ycliang@andestech.com>
This commit is contained in:
Yao Zi
2025-07-10 03:42:00 +00:00
committed by Leo Yu-Chi Liang
parent 8a3c3a8a11
commit e875813600
2 changed files with 161 additions and 0 deletions
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119
arch/riscv/dts/th1520-lichee-module-4a.dtsi
View File

@@ -11,6 +11,11 @@
model = "Sipeed Lichee Module 4A";
compatible = "sipeed,lichee-module-4a", "thead,th1520";
aliases {
ethernet0 = &gmac0;
ethernet1 = &gmac1;
};
memory@0 {
device_type = "memory";
reg = <0x0 0x00000000 0x2 0x00000000>;
@@ -38,6 +43,120 @@
status = "okay";
};
&gmac0 {
pinctrl-names = "default";
pinctrl-0 = <&gmac0_pins>, <&mdio0_pins>;
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
status = "okay";
};
&gmac1 {
pinctrl-names = "default";
pinctrl-0 = <&gmac1_pins>;
phy-handle = <&phy1>;
phy-mode = "rgmii-id";
status = "okay";
};
&mdio0 {
phy0: ethernet-phy@1 {
reg = <1>;
};
phy1: ethernet-phy@2 {
reg = <2>;
};
};
&padctrl0_apsys {
gmac0_pins: gmac0-0 {
tx-pins {
pins = "GMAC0_TX_CLK",
"GMAC0_TXEN",
"GMAC0_TXD0",
"GMAC0_TXD1",
"GMAC0_TXD2",
"GMAC0_TXD3";
function = "gmac0";
bias-disable;
drive-strength = <25>;
input-disable;
input-schmitt-disable;
slew-rate = <0>;
};
rx-pins {
pins = "GMAC0_RX_CLK",
"GMAC0_RXDV",
"GMAC0_RXD0",
"GMAC0_RXD1",
"GMAC0_RXD2",
"GMAC0_RXD3";
function = "gmac0";
bias-disable;
drive-strength = <1>;
input-enable;
input-schmitt-disable;
slew-rate = <0>;
};
};
gmac1_pins: gmac1-0 {
tx-pins {
pins = "GPIO2_18", /* GMAC1_TX_CLK */
"GPIO2_20", /* GMAC1_TXEN */
"GPIO2_21", /* GMAC1_TXD0 */
"GPIO2_22", /* GMAC1_TXD1 */
"GPIO2_23", /* GMAC1_TXD2 */
"GPIO2_24"; /* GMAC1_TXD3 */
function = "gmac1";
bias-disable;
drive-strength = <25>;
input-disable;
input-schmitt-disable;
slew-rate = <0>;
};
rx-pins {
pins = "GPIO2_19", /* GMAC1_RX_CLK */
"GPIO2_25", /* GMAC1_RXDV */
"GPIO2_30", /* GMAC1_RXD0 */
"GPIO2_31", /* GMAC1_RXD1 */
"GPIO3_0", /* GMAC1_RXD2 */
"GPIO3_1"; /* GMAC1_RXD3 */
function = "gmac1";
bias-disable;
drive-strength = <1>;
input-enable;
input-schmitt-disable;
slew-rate = <0>;
};
};
mdio0_pins: mdio0-0 {
mdc-pins {
pins = "GMAC0_MDC";
function = "gmac0";
bias-disable;
drive-strength = <13>;
input-disable;
input-schmitt-disable;
slew-rate = <0>;
};
mdio-pins {
pins = "GMAC0_MDIO";
function = "gmac0";
bias-disable;
drive-strength = <13>;
input-enable;
input-schmitt-enable;
slew-rate = <0>;
};
};
};
&sdio0 {
bus-width = <4>;
max-frequency = <198000000>;

42
arch/riscv/dts/th1520.dtsi
View File

@@ -177,6 +177,48 @@
status = "disabled";
};
gmac1: ethernet@ffe7060000 {
compatible = "thead,th1520-gmac", "snps,dwmac-3.70a";
reg = <0xff 0xe7060000 0x0 0x2000>, <0xff 0xec004000 0x0 0x1000>;
reg-names = "dwmac", "apb";
interrupts = <67 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
clocks = <&clk CLK_GMAC_AXI>, <&clk CLK_GMAC1>;
clock-names = "stmmaceth", "pclk";
snps,pbl = <32>;
snps,fixed-burst;
snps,multicast-filter-bins = <64>;
snps,perfect-filter-entries = <32>;
status = "disabled";
mdio1: mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
};
};
gmac0: ethernet@ffe7070000 {
compatible = "thead,th1520-gmac", "snps,dwmac-3.70a";
reg = <0xff 0xe7070000 0x0 0x2000>, <0xff 0xec003000 0x0 0x1000>;
reg-names = "dwmac", "apb";
interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
clocks = <&clk CLK_GMAC_AXI>, <&clk CLK_GMAC0>;
clock-names = "stmmaceth", "pclk";
snps,pbl = <32>;
snps,fixed-burst;
snps,multicast-filter-bins = <64>;
snps,perfect-filter-entries = <32>;
status = "disabled";
mdio0: mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
};
};
emmc: mmc@ffe7080000 {
compatible = "thead,th1520-dwcmshc";
reg = <0xff 0xe7080000 0x0 0x10000>;