Merge patch series "Implement all missing SMBIOS types required by distro tooling"

Raymond Mao <raymondmaoca@gmail.com> says:

From: Raymond Mao <raymond.mao@riscstar.com>

This series finish the last missing puzzle of required SMBIOS types by:
1) Fixing duplicated handles when multiple instances exist in one type;
2) Implementing the rest of required types 9/16/17/19;
3) Adding version control when printing properties for all types.

Type 9/16/17/19 are generally DT-based, the idea is to write these tables
using a hybrid approach:
Explicit DT definitions under existing '/smbios/smbios' take precedence,
with fallback to scan and interpret values from the entire DT.

Moreover, all below APIs:
smbios_get_val_si()
smbios_get_u64_si()
smbios_add_prop_si()
are on top of sysinfo, thus allow vendors to get values from other
subsystems by implementing their own sysinfo driver if needed.

Link: https://lore.kernel.org/r/20260213225254.2544596-1-raymondmaoca@gmail.com
This commit is contained in:
Tom Rini
2026-02-18 08:27:58 -06:00
7 changed files with 1905 additions and 33 deletions

View File

@@ -77,6 +77,18 @@
SMBIOS_CACHE_OP_WB)>;
};
};
system-slot {
};
memory-array {
};
memory-device {
};
memory-array-mapped-address {
};
};
};
};

View File

@@ -119,6 +119,149 @@ static const struct str_lookup_table associativity_strings[] = {
};
static const struct str_lookup_table slot_type_strings[] = {
{ SMBIOS_SYSSLOT_TYPE_OTHER, "Other" },
{ SMBIOS_SYSSLOT_TYPE_UNKNOWN, "Unknown" },
{ SMBIOS_SYSSLOT_TYPE_ISA, "ISA" },
{ SMBIOS_SYSSLOT_TYPE_PCI, "PCI" },
{ SMBIOS_SYSSLOT_TYPE_PCMCIA, "PC Card (PCMCIA)" },
{ SMBIOS_SYSSLOT_TYPE_PCIE, "PCI Express" },
{ SMBIOS_SYSSLOT_TYPE_PCIEGEN2, "PCI Express Gen 2" },
{ SMBIOS_SYSSLOT_TYPE_PCIEGEN3, "PCI Express Gen 3" },
{ SMBIOS_SYSSLOT_TYPE_PCIEGEN3X16, "PCI Express Gen 3 x16" },
{ SMBIOS_SYSSLOT_TYPE_PCIEGEN4, "PCI Express Gen 4" },
{ SMBIOS_SYSSLOT_TYPE_PCIEGEN4X8, "PCI Express Gen 4 x8" },
{ SMBIOS_SYSSLOT_TYPE_PCIEGEN4X16, "PCI Express Gen 4 x16" },
};
static const struct str_lookup_table slot_bus_width_strings[] = {
{ SMBIOS_SYSSLOT_WIDTH_OTHER, "Other" },
{ SMBIOS_SYSSLOT_WIDTH_UNKNOWN, "Unknown" },
{ SMBIOS_SYSSLOT_WIDTH_8BIT, "8 bit" },
{ SMBIOS_SYSSLOT_WIDTH_16BIT, "16 bit" },
{ SMBIOS_SYSSLOT_WIDTH_32BIT, "32 bit" },
{ SMBIOS_SYSSLOT_WIDTH_64BIT, "64 bit" },
{ SMBIOS_SYSSLOT_WIDTH_128BIT, "128 bit " },
{ SMBIOS_SYSSLOT_WIDTH_1X, "1x or x1" },
{ SMBIOS_SYSSLOT_WIDTH_2X, "2x or x2" },
{ SMBIOS_SYSSLOT_WIDTH_4X, "4x or x4" },
{ SMBIOS_SYSSLOT_WIDTH_8X, "8x or x8" },
{ SMBIOS_SYSSLOT_WIDTH_12X, "12x or x12" },
{ SMBIOS_SYSSLOT_WIDTH_16X, "16x or x16" },
{ SMBIOS_SYSSLOT_WIDTH_32X, "32x or x32" },
};
static const struct str_lookup_table slot_usage_strings[] = {
{ SMBIOS_SYSSLOT_USAGE_OTHER, "Other" },
{ SMBIOS_SYSSLOT_USAGE_UNKNOWN, "Unknown" },
{ SMBIOS_SYSSLOT_USAGE_AVAILABLE, "Available" },
{ SMBIOS_SYSSLOT_USAGE_INUSE, "In use" },
{ SMBIOS_SYSSLOT_USAGE_NA, "Unavailable" },
};
static const struct str_lookup_table slot_length_strings[] = {
{ SMBIOS_SYSSLOT_LENG_OTHER, "Other" },
{ SMBIOS_SYSSLOT_LENG_UNKNOWN, "Unknown" },
{ SMBIOS_SYSSLOT_LENG_SHORT, "Short Length" },
{ SMBIOS_SYSSLOT_LENG_LONG, "Long Length" },
{ SMBIOS_SYSSLOT_LENG_2_5INDRV, "2.5 inch drive form factor" },
{ SMBIOS_SYSSLOT_LENG_3_5INDRV, "3.5 inch drive form factor" },
};
static const struct str_lookup_table ma_location_strings[] = {
{ SMBIOS_MA_LOCATION_OTHER, "Other" },
{ SMBIOS_MA_LOCATION_UNKNOWN, "Unknown" },
{ SMBIOS_MA_LOCATION_MOTHERBOARD, "System board or motherboard" },
};
static const struct str_lookup_table ma_use_strings[] = {
{ SMBIOS_MA_USE_OTHER, "Other" },
{ SMBIOS_MA_USE_UNKNOWN, "Unknown" },
{ SMBIOS_MA_USE_SYSTEM, "System memory" },
{ SMBIOS_MA_USE_VIDEO, "Video memory" },
{ SMBIOS_MA_USE_FLASH, "Flash memory" },
{ SMBIOS_MA_USE_NVRAM, "Non-volatile RAM" },
{ SMBIOS_MA_USE_CACHE, "Cache memory" },
};
static const struct str_lookup_table ma_err_corr_strings[] = {
{ SMBIOS_MA_ERRCORR_OTHER, "Other" },
{ SMBIOS_MA_ERRCORR_UNKNOWN, "Unknown" },
{ SMBIOS_MA_ERRCORR_NONE, "None" },
{ SMBIOS_MA_ERRCORR_PARITY, "Parity" },
{ SMBIOS_MA_ERRCORR_SBITECC, "Single-bit ECC" },
{ SMBIOS_MA_ERRCORR_MBITECC, "Multi-bit ECC" },
{ SMBIOS_MA_ERRCORR_CRC, "CRC" },
};
static const struct str_lookup_table md_form_factor_strings[] = {
{ SMBIOS_MD_FF_OTHER, "Other" },
{ SMBIOS_MD_FF_UNKNOWN, "Unknown" },
{ SMBIOS_MD_FF_SIMM, "SIMM" },
{ SMBIOS_MD_FF_SIP, "SIP" },
{ SMBIOS_MD_FF_CHIP, "Chip" },
{ SMBIOS_MD_FF_DIP, "DIP" },
{ SMBIOS_MD_FF_ZIP, "ZIP" },
{ SMBIOS_MD_FF_PROPCARD, "Proprietary Card" },
{ SMBIOS_MD_FF_DIMM, "DIMM" },
{ SMBIOS_MD_FF_TSOP, "TSOP" },
{ SMBIOS_MD_FF_ROC, "Row of chips" },
{ SMBIOS_MD_FF_RIMM, "RIMM" },
{ SMBIOS_MD_FF_SODIMM, "SODIMM" },
{ SMBIOS_MD_FF_SRIMM, "SRIMM" },
{ SMBIOS_MD_FF_FBDIMM, "FB-DIMM" },
{ SMBIOS_MD_FF_DIE, "Die" },
};
static const struct str_lookup_table md_type_strings[] = {
{ SMBIOS_MD_TYPE_OTHER, "Other" },
{ SMBIOS_MD_TYPE_UNKNOWN, "Unknown" },
{ SMBIOS_MD_TYPE_DRAM, "DRAM" },
{ SMBIOS_MD_TYPE_EDRAM, "EDRAM" },
{ SMBIOS_MD_TYPE_VRAM, "VRAM" },
{ SMBIOS_MD_TYPE_SRAM, "SRAM" },
{ SMBIOS_MD_TYPE_RAM, "RAM" },
{ SMBIOS_MD_TYPE_ROM, "ROM" },
{ SMBIOS_MD_TYPE_FLASH, "FLASH" },
{ SMBIOS_MD_TYPE_EEPROM, "EEPROM" },
{ SMBIOS_MD_TYPE_FEPROM, "FEPROM" },
{ SMBIOS_MD_TYPE_EPROM, "EPROM" },
{ SMBIOS_MD_TYPE_CDRAM, "CDRAM" },
{ SMBIOS_MD_TYPE_3DRAM, "3DRAM" },
{ SMBIOS_MD_TYPE_SDRAM, "SDRAM" },
{ SMBIOS_MD_TYPE_SGRAM, "SGRAM" },
{ SMBIOS_MD_TYPE_RDRAM, "RDRAM" },
{ SMBIOS_MD_TYPE_DDR, "DDR" },
{ SMBIOS_MD_TYPE_DDR2, "DDR2" },
{ SMBIOS_MD_TYPE_DDR2FBD, "DDR2 FB-DIMM" },
{ SMBIOS_MD_TYPE_RSVD1, "Reserved" },
{ SMBIOS_MD_TYPE_RSVD2, "Reserved" },
{ SMBIOS_MD_TYPE_DSVD3, "Reserved" },
{ SMBIOS_MD_TYPE_DDR3, "DDR3" },
{ SMBIOS_MD_TYPE_FBD2, "FBD2" },
{ SMBIOS_MD_TYPE_DDR4, "DDR4" },
{ SMBIOS_MD_TYPE_LPDDR, "LPDDR" },
{ SMBIOS_MD_TYPE_LPDDR2, "LPDDR2" },
{ SMBIOS_MD_TYPE_LPDDR3, "LPDDR3" },
{ SMBIOS_MD_TYPE_LPDDR4, "LPDDR4" },
{ SMBIOS_MD_TYPE_LNVD, "Logical non-volatile device" },
{ SMBIOS_MD_TYPE_HBM, "HBM" },
{ SMBIOS_MD_TYPE_HBM2, "HBM2" },
{ SMBIOS_MD_TYPE_DDR5, "DDR5" },
{ SMBIOS_MD_TYPE_LPDDR5, "LPDDR5" },
{ SMBIOS_MD_TYPE_HBM3, "HBM3" },
};
static const struct str_lookup_table md_tech_strings[] = {
{ SMBIOS_MD_TECH_OTHER, "Other" },
{ SMBIOS_MD_TECH_UNKNOWN, "Unknown" },
{ SMBIOS_MD_TECH_DRAM, "DRAM" },
{ SMBIOS_MD_TECH_NVDIMMN, "NVDIMM-N" },
{ SMBIOS_MD_TECH_NVDIMMF, "NVDIMM-F" },
{ SMBIOS_MD_TECH_NVDIMMP, "NVDIMM-P" },
{ SMBIOS_MD_TECH_OPTANE, "Intel Optane persistent memory" },
};
/**
* smbios_get_string() - get SMBIOS string from table
*
@@ -205,6 +348,8 @@ static void smbios_print_type0(struct smbios_type0 *table)
printf("\tBIOS ROM Size: 0x%02x\n", table->bios_rom_size);
printf("\tBIOS Characteristics: 0x%016llx\n",
table->bios_characteristics);
if (table->hdr.length < SMBIOS_TYPE0_LENGTH_V24)
return;
printf("\tBIOS Characteristics Extension Byte 1: 0x%02x\n",
table->bios_characteristics_ext1);
printf("\tBIOS Characteristics Extension Byte 2: 0x%02x\n",
@@ -217,6 +362,8 @@ static void smbios_print_type0(struct smbios_type0 *table)
table->ec_major_release);
printf("\tEmbedded Controller Firmware Minor Release: 0x%02x\n",
table->ec_minor_release);
if (table->hdr.length < SMBIOS_TYPE0_LENGTH_V31)
return;
printf("\tExtended BIOS ROM Size: 0x%04x\n",
table->extended_bios_rom_size);
}
@@ -228,17 +375,16 @@ static void smbios_print_type1(struct smbios_type1 *table)
smbios_print_str("Product Name", table, table->product_name);
smbios_print_str("Version", table, table->version);
smbios_print_str("Serial Number", table, table->serial_number);
if (table->hdr.length >= SMBIOS_TYPE1_LENGTH_V21) {
printf("\tUUID: %pUl\n", table->uuid);
smbios_print_lookup_str(wakeup_type_strings,
table->wakeup_type,
ARRAY_SIZE(wakeup_type_strings),
"Wake-up Type");
}
if (table->hdr.length >= SMBIOS_TYPE1_LENGTH_V24) {
smbios_print_str("SKU Number", table, table->sku_number);
smbios_print_str("Family", table, table->family);
}
if (table->hdr.length < SMBIOS_TYPE1_LENGTH_V21)
return;
printf("\tUUID: %pUl\n", table->uuid);
smbios_print_lookup_str(wakeup_type_strings, table->wakeup_type,
ARRAY_SIZE(wakeup_type_strings),
"Wake-up Type");
if (table->hdr.length < SMBIOS_TYPE1_LENGTH_V24)
return;
smbios_print_str("SKU Number", table, table->sku_number);
smbios_print_str("Family", table, table->family);
}
static void smbios_print_type2(struct smbios_type2 *table)
@@ -358,21 +504,31 @@ static void smbios_print_type4(struct smbios_type4 *table)
printf("\tL1 Cache Handle: 0x%04x\n", table->l1_cache_handle);
printf("\tL2 Cache Handle: 0x%04x\n", table->l2_cache_handle);
printf("\tL3 Cache Handle: 0x%04x\n", table->l3_cache_handle);
if (table->hdr.length < SMBIOS_TYPE4_LENGTH_V23)
return;
smbios_print_str("Serial Number", table, table->serial_number);
smbios_print_str("Asset Tag", table, table->asset_tag);
smbios_print_str("Part Number", table, table->part_number);
if (table->hdr.length < SMBIOS_TYPE4_LENGTH_V25)
return;
printf("\tCore Count: 0x%02x\n", table->core_count);
printf("\tCore Enabled: 0x%02x\n", table->core_enabled);
printf("\tThread Count: 0x%02x\n", table->thread_count);
printf("\tProcessor Characteristics: 0x%04x\n",
table->processor_characteristics);
if (table->hdr.length < SMBIOS_TYPE4_LENGTH_V26)
return;
smbios_print_lookup_str(processor_family_strings,
table->processor_family2,
ARRAY_SIZE(processor_family_strings),
"Processor Family 2");
if (table->hdr.length < SMBIOS_TYPE4_LENGTH_V30)
return;
printf("\tCore Count 2: 0x%04x\n", table->core_count2);
printf("\tCore Enabled 2: 0x%04x\n", table->core_enabled2);
printf("\tThread Count 2: 0x%04x\n", table->thread_count2);
if (table->hdr.length < SMBIOS_TYPE4_LENGTH_V36)
return;
printf("\tThread Enabled: 0x%04x\n", table->thread_enabled);
}
@@ -386,6 +542,8 @@ static void smbios_print_type7(struct smbios_type7 *table)
printf("\tInstalled Size: 0x%04x\n", table->inst_size.data);
printf("\tSupported SRAM Type: 0x%04x\n", table->supp_sram_type.data);
printf("\tCurrent SRAM Type: 0x%04x\n", table->curr_sram_type.data);
if (table->hdr.length < SMBIOS_TYPE7_LENGTH_V21)
return;
printf("\tCache Speed: 0x%02x\n", table->speed);
smbios_print_lookup_str(err_corr_type_strings,
table->err_corr_type,
@@ -399,10 +557,183 @@ static void smbios_print_type7(struct smbios_type7 *table)
table->associativity,
ARRAY_SIZE(associativity_strings),
"Associativity");
if (table->hdr.length < SMBIOS_TYPE7_LENGTH_V31)
return;
printf("\tMaximum Cache Size 2: 0x%08x\n", table->max_size2.data);
printf("\tInstalled Cache Size 2: 0x%08x\n", table->inst_size2.data);
}
static void smbios_print_type9(struct smbios_type9 *table)
{
int i;
u8 *addr = (u8 *)table +
offsetof(struct smbios_type9, slot_information);
printf("System Slots:\n");
smbios_print_str("Socket Designation", table,
table->socket_design);
smbios_print_lookup_str(slot_type_strings,
table->slot_type,
ARRAY_SIZE(slot_type_strings),
"Slot Type");
smbios_print_lookup_str(slot_bus_width_strings,
table->slot_data_bus_width,
ARRAY_SIZE(slot_bus_width_strings),
"Slot Data Bus Width");
smbios_print_lookup_str(slot_usage_strings,
table->current_usage,
ARRAY_SIZE(slot_usage_strings),
"Current Usage");
smbios_print_lookup_str(slot_length_strings,
table->slot_length,
ARRAY_SIZE(slot_length_strings),
"Slot Length");
printf("\tSlot ID: 0x%04x\n", table->slot_id);
printf("\tSlot Characteristics 1: 0x%04x\n",
table->slot_characteristics_1);
if (table->hdr.length < SMBIOS_TYPE9_LENGTH_V21)
return;
printf("\tSlot Characteristics 2: 0x%04x\n",
table->slot_characteristics_2);
if (table->hdr.length < SMBIOS_TYPE9_LENGTH_V26)
return;
printf("\tSegment Group Number (Base): 0x%04x\n",
table->segment_group_number);
printf("\tBus Number (Base): 0x%04x\n", table->bus_number);
printf("\tDevice/Function Number (Base): 0x%04x\n",
table->device_function_number.data);
printf("\tData Bus Width (Base): 0x%04x\n",
table->electrical_bus_width);
printf("\tPeer (S/B/D/F/Width) grouping count: 0x%04x\n",
table->peer_grouping_count);
printf("\tPeer (S/B/D/F/Width) groups:\n");
for (i = 0; i < table->peer_grouping_count; i++) {
printf("\t\tPeer group[%03d]:\n", i);
if (CONFIG_IS_ENABLED(HEXDUMP))
print_hex_dump("\t\t", DUMP_PREFIX_OFFSET, 16, 1, addr,
SMBIOS_TYPE9_PGROUP_SIZE, false);
addr += SMBIOS_TYPE9_PGROUP_SIZE;
}
printf("\n");
/* table->slot_information */
printf("\tSlot Information: 0x%04x\n", *addr);
/* table->slot_physical_width */
addr += sizeof(table->slot_information);
printf("\tSlot Physical Width: 0x%04x\n", *addr);
/* table->slot_pitch */
addr += sizeof(table->slot_physical_width);
printf("\tSlot Pitch: 0x%04x\n", *(u16 *)addr);
/* table->slot_height */
addr += sizeof(table->slot_pitch);
printf("\tSlot Height: 0x%04x\n", *addr);
}
static void smbios_print_type16(struct smbios_type16 *table)
{
printf("Physical Memory Array:\n");
if (table->hdr.length < SMBIOS_TYPE16_LENGTH_V21)
return;
smbios_print_lookup_str(ma_location_strings, table->location,
ARRAY_SIZE(ma_location_strings), "Location");
smbios_print_lookup_str(ma_use_strings, table->use,
ARRAY_SIZE(ma_use_strings), "Use");
smbios_print_lookup_str(ma_err_corr_strings, table->mem_err_corr,
ARRAY_SIZE(ma_err_corr_strings),
"Memory Error Correction");
printf("\tMaximum Capacity: 0x%08x\n", table->max_cap);
printf("\tMemory Error Information Handle: 0x%04x\n",
table->mem_err_info_hdl);
printf("\tNumber of Memory Devices: 0x%04x\n", table->num_of_mem_dev);
if (table->hdr.length < SMBIOS_TYPE16_LENGTH_V27)
return;
printf("\tExtended Maximum Capacity: 0x%016llx\n", table->ext_max_cap);
}
static void smbios_print_type17(struct smbios_type17 *table)
{
printf("Memory Device:\n");
if (table->hdr.length < SMBIOS_TYPE17_LENGTH_V21)
return;
printf("\tPhysical Memory Array Handle: 0x%04x\n",
table->phy_mem_array_hdl);
printf("\tMemory Error Information Handle: 0x%04x\n",
table->mem_err_info_hdl);
printf("\tTotal Width: 0x%04x\n", table->total_width);
printf("\tData Width: 0x%04x\n", table->data_width);
printf("\tSize: 0x%04x\n", table->size);
smbios_print_lookup_str(md_form_factor_strings, table->form_factor,
ARRAY_SIZE(md_form_factor_strings),
"Form Factor");
printf("\tDevice Set: 0x%04x\n", table->dev_set);
smbios_print_str("Device Locator", table, table->dev_locator);
smbios_print_str("Bank Locator", table, table->bank_locator);
smbios_print_lookup_str(md_type_strings, table->mem_type,
ARRAY_SIZE(md_type_strings), "Memory Type");
printf("\tType Detail: 0x%04x\n", table->type_detail);
if (table->hdr.length < SMBIOS_TYPE17_LENGTH_V23)
return;
printf("\tSpeed: 0x%04x\n", table->speed);
smbios_print_str("Manufacturer", table, table->manufacturer);
smbios_print_str("Serial Number", table, table->serial_number);
smbios_print_str("Asset Tag", table, table->asset_tag);
smbios_print_str("Part Number", table, table->part_number);
if (table->hdr.length < SMBIOS_TYPE17_LENGTH_V26)
return;
printf("\tAttributes: 0x%04x\n", table->attributes);
if (table->hdr.length < SMBIOS_TYPE17_LENGTH_V27)
return;
printf("\tExtended Size: 0x%08x\n", table->ext_size);
printf("\tConfigured Memory Speed: 0x%04x\n", table->config_mem_speed);
if (table->hdr.length < SMBIOS_TYPE17_LENGTH_V28)
return;
printf("\tMinimum voltage: 0x%04x\n", table->min_voltage);
printf("\tMaximum voltage: 0x%04x\n", table->max_voltage);
printf("\tConfigured voltage: 0x%04x\n", table->config_voltage);
if (table->hdr.length < SMBIOS_TYPE17_LENGTH_V32)
return;
smbios_print_lookup_str(md_tech_strings, table->mem_tech,
ARRAY_SIZE(md_tech_strings),
"Memory Technology");
printf("\tMemory Operating Mode Capability: 0x%04x\n",
table->mem_op_mode_cap);
smbios_print_str("Firmware Version", table, table->fw_ver);
printf("\tModule Manufacturer ID: 0x%04x\n", table->module_man_id);
printf("\tModule Product ID: 0x%04x\n", table->module_prod_id);
printf("\tMemory Subsystem Controller Manufacturer ID: 0x%04x\n",
table->mem_subsys_con_man_id);
printf("\tMemory Subsystem Controller Product ID: 0x%04x\n",
table->mem_subsys_con_prod_id);
printf("\tNon-volatile Size: 0x%016llx\n", table->nonvolatile_size);
printf("\tVolatile Size: 0x%016llx\n", table->volatile_size);
printf("\tCache Size: 0x%016llx\n", table->cache_size);
printf("\tLogical Size: 0x%016llx\n", table->logical_size);
if (table->hdr.length < SMBIOS_TYPE17_LENGTH_V33)
return;
printf("\tExtended Speed: 0x%04x\n", table->ext_speed);
printf("\tExtended Configured Memory Speed: 0x%04x\n",
table->ext_config_mem_speed);
printf("\tPMIC0 Manufacturer ID: 0x%04x\n", table->pmic0_man_id);
printf("\tPMIC0 Revision Number: 0x%04x\n", table->pmic0_rev_num);
printf("\tRCD Manufacturer ID: 0x%04x\n", table->rcd_man_id);
printf("\tRCD Revision Number: 0x%04x\n", table->rcd_rev_num);
}
static void smbios_print_type19(struct smbios_type19 *table)
{
printf("Memory Array Mapped Address:\n");
if (table->hdr.length < SMBIOS_TYPE19_LENGTH_V21)
return;
printf("\tStarting Address: 0x%08x\n", table->start_addr);
printf("\tEnding Address: 0x%08x\n", table->end_addr);
printf("\tMemory Array Handle: 0x%04x\n", table->mem_array_hdl);
printf("\tPartition Width: 0x%04x\n", table->partition_wid);
if (table->hdr.length < SMBIOS_TYPE19_LENGTH_V27)
return;
printf("\tExtended Starting Address: 0x%016llx\n", table->ext_start_addr);
printf("\tExtended Ending Address: 0x%016llx\n", table->ext_end_addr);
}
static void smbios_print_type127(struct smbios_type127 *table)
{
printf("End Of Table\n");
@@ -482,6 +813,18 @@ static int do_smbios(struct cmd_tbl *cmdtp, int flag, int argc,
case SMBIOS_CACHE_INFORMATION:
smbios_print_type7((struct smbios_type7 *)pos);
break;
case SMBIOS_SYSTEM_SLOTS:
smbios_print_type9((struct smbios_type9 *)pos);
break;
case SMBIOS_PHYS_MEMORY_ARRAY:
smbios_print_type16((struct smbios_type16 *)pos);
break;
case SMBIOS_MEMORY_DEVICE:
smbios_print_type17((struct smbios_type17 *)pos);
break;
case SMBIOS_MEMORY_ARRAY_MAPPED_ADDRESS:
smbios_print_type19((struct smbios_type19 *)pos);
break;
case SMBIOS_END_OF_TABLE:
smbios_print_type127((struct smbios_type127 *)pos);
break;

View File

@@ -24,6 +24,7 @@ struct sysinfo_plat_priv {
struct smbios_type7 t7[SYSINFO_CACHE_LVL_MAX];
u16 cache_handles[SYSINFO_CACHE_LVL_MAX];
u8 cache_level;
u16 marray_handles[SYSINFO_MEM_HANDLE_MAX];
};
static void smbios_cache_info_dump(struct smbios_type7 *cache_info)
@@ -165,6 +166,10 @@ static int sysinfo_plat_get_data(struct udevice *dev, int id, void **buf,
*buf = &priv->cache_handles[0];
*size = sizeof(priv->cache_handles);
break;
case SYSID_SM_MEMARRAY_HANDLE:
*buf = &priv->marray_handles[0];
*size = sizeof(priv->marray_handles);
break;
default:
return -EOPNOTSUPP;
}

View File

@@ -110,10 +110,42 @@ struct __packed smbios_type0 {
char eos[SMBIOS_STRUCT_EOS_BYTES];
};
#define SMBIOS_TYPE0_LENGTH_V24 0x18
#define SMBIOS_TYPE0_LENGTH_V31 0x1a
#define SMBIOS_TYPE1_LENGTH_V20 0x08
#define SMBIOS_TYPE1_LENGTH_V21 0x19
#define SMBIOS_TYPE1_LENGTH_V24 0x1b
#define SMBIOS_TYPE4_LENGTH_V20 0x1a
#define SMBIOS_TYPE4_LENGTH_V23 0x23
#define SMBIOS_TYPE4_LENGTH_V25 0x28
#define SMBIOS_TYPE4_LENGTH_V26 0x2a
#define SMBIOS_TYPE4_LENGTH_V30 0x30
#define SMBIOS_TYPE4_LENGTH_V36 0x32
#define SMBIOS_TYPE7_LENGTH_V20 0x0f
#define SMBIOS_TYPE7_LENGTH_V21 0x13
#define SMBIOS_TYPE7_LENGTH_V31 0x1b
#define SMBIOS_TYPE9_LENGTH_V20 0x0c
#define SMBIOS_TYPE9_LENGTH_V21 0x0d
#define SMBIOS_TYPE9_LENGTH_V26 0x11
#define SMBIOS_TYPE16_LENGTH_V21 0x0f
#define SMBIOS_TYPE16_LENGTH_V27 0x17
#define SMBIOS_TYPE17_LENGTH_V21 0x15
#define SMBIOS_TYPE17_LENGTH_V23 0x1b
#define SMBIOS_TYPE17_LENGTH_V26 0x1c
#define SMBIOS_TYPE17_LENGTH_V27 0x22
#define SMBIOS_TYPE17_LENGTH_V28 0x28
#define SMBIOS_TYPE17_LENGTH_V32 0x54
#define SMBIOS_TYPE17_LENGTH_V33 0x5c
#define SMBIOS_TYPE19_LENGTH_V21 0x0f
#define SMBIOS_TYPE19_LENGTH_V27 0x1f
struct __packed smbios_type1 {
struct smbios_header hdr;
u8 manufacturer;
@@ -264,6 +296,125 @@ struct __packed smbios_type7 {
char eos[SMBIOS_STRUCT_EOS_BYTES];
};
#define SMBIOS_TYPE9_PGROUP_SIZE 5
struct pci_attr_lookup_table {
const char *str;
u8 slot_type;
u8 data_bus_width;
u8 slot_length;
u8 chara1;
u8 chara2;
};
union dev_func_num {
struct {
u8 dev_num:5;
u8 func_num:3;
} fields;
u8 data;
};
struct __packed smbios_type9 {
struct smbios_header hdr;
u8 socket_design;
u8 slot_type;
u8 slot_data_bus_width;
u8 current_usage;
u8 slot_length;
u16 slot_id;
u8 slot_characteristics_1;
u8 slot_characteristics_2;
u16 segment_group_number;
u8 bus_number;
union dev_func_num device_function_number;
u8 electrical_bus_width;
u8 peer_grouping_count;
/*
* Dynamic bytes will be inserted here to store peer_groups.
* length is equal to 'peer_grouping_count' * 5
*/
u8 slot_information;
u8 slot_physical_width;
u16 slot_pitch;
u8 slot_height;
char eos[SMBIOS_STRUCT_EOS_BYTES];
};
enum {
SMBIOS_MEM_NONE = 0,
SMBIOS_MEM_CUSTOM = 1,
SMBIOS_MEM_FDT_MEM_NODE = 2,
SMBIOS_MEM_FDT_MEMCON_NODE = 3
};
struct __packed smbios_type16 {
struct smbios_header hdr;
u8 location;
u8 use;
u8 mem_err_corr;
u32 max_cap;
u16 mem_err_info_hdl;
u16 num_of_mem_dev;
u64 ext_max_cap;
char eos[SMBIOS_STRUCT_EOS_BYTES];
};
struct __packed smbios_type17 {
struct smbios_header hdr;
u16 phy_mem_array_hdl;
u16 mem_err_info_hdl;
u16 total_width;
u16 data_width;
u16 size;
u8 form_factor;
u8 dev_set;
u8 dev_locator;
u8 bank_locator;
u8 mem_type;
u16 type_detail;
u16 speed;
u8 manufacturer;
u8 serial_number;
u8 asset_tag;
u8 part_number;
u8 attributes;
u32 ext_size;
u16 config_mem_speed;
u16 min_voltage;
u16 max_voltage;
u16 config_voltage;
u8 mem_tech;
u16 mem_op_mode_cap;
u8 fw_ver;
u16 module_man_id;
u16 module_prod_id;
u16 mem_subsys_con_man_id;
u16 mem_subsys_con_prod_id;
u64 nonvolatile_size;
u64 volatile_size;
u64 cache_size;
u64 logical_size;
u32 ext_speed;
u32 ext_config_mem_speed;
u16 pmic0_man_id;
u16 pmic0_rev_num;
u16 rcd_man_id;
u16 rcd_rev_num;
char eos[SMBIOS_STRUCT_EOS_BYTES];
};
struct __packed smbios_type19 {
struct smbios_header hdr;
u32 start_addr;
u32 end_addr;
u16 mem_array_hdl;
u8 partition_wid;
u64 ext_start_addr;
u64 ext_end_addr;
char eos[SMBIOS_STRUCT_EOS_BYTES];
};
struct __packed smbios_type32 {
u8 type;
u8 length;

View File

@@ -191,4 +191,254 @@
#define SMBIOS_CACHE_ASSOC_64WAY 13
#define SMBIOS_CACHE_ASSOC_20WAY 14
/*
* System Slot
*/
/* Slot Type */
#define SMBIOS_SYSSLOT_TYPE_OTHER 1
#define SMBIOS_SYSSLOT_TYPE_UNKNOWN 2
#define SMBIOS_SYSSLOT_TYPE_ISA 3 /* ISA */
#define SMBIOS_SYSSLOT_TYPE_PCI 6 /* PCI */
#define SMBIOS_SYSSLOT_TYPE_PCMCIA 7 /* PCMCIA */
#define SMBIOS_SYSSLOT_TYPE_PCIE 0xa5 /* PCI Express */
#define SMBIOS_SYSSLOT_TYPE_PCIEX1 0xa6 /* PCI Express x1 */
#define SMBIOS_SYSSLOT_TYPE_PCIEX2 0xa7 /* PCI Express x2 */
#define SMBIOS_SYSSLOT_TYPE_PCIEX4 0xa8 /* PCI Express x4 */
#define SMBIOS_SYSSLOT_TYPE_PCIEX8 0xa9 /* PCI Express x8 */
#define SMBIOS_SYSSLOT_TYPE_PCIEX16 0xaa /* PCI Express x16 */
#define SMBIOS_SYSSLOT_TYPE_PCIEGEN2 0xab /* PCI Express Gen 2 */
#define SMBIOS_SYSSLOT_TYPE_PCIEGEN2X1 0xac /* PCI Express Gen 2 x1 */
#define SMBIOS_SYSSLOT_TYPE_PCIEGEN2X2 0xad /* PCI Express Gen 2 x2 */
#define SMBIOS_SYSSLOT_TYPE_PCIEGEN2X4 0xae /* PCI Express Gen 2 x4 */
#define SMBIOS_SYSSLOT_TYPE_PCIEGEN2X8 0xaf /* PCI Express Gen 2 x8 */
#define SMBIOS_SYSSLOT_TYPE_PCIEGEN2X16 0xb0 /* PCI Express Gen 2 x16 */
#define SMBIOS_SYSSLOT_TYPE_PCIEGEN3 0xb1 /* PCI Express Gen 3 */
#define SMBIOS_SYSSLOT_TYPE_PCIEGEN3X1 0xb2 /* PCI Express Gen 3 x1 */
#define SMBIOS_SYSSLOT_TYPE_PCIEGEN3X2 0xb3 /* PCI Express Gen 3 x2 */
#define SMBIOS_SYSSLOT_TYPE_PCIEGEN3X4 0xb4 /* PCI Express Gen 3 x4 */
#define SMBIOS_SYSSLOT_TYPE_PCIEGEN3X8 0xb5 /* PCI Express Gen 3 x8 */
#define SMBIOS_SYSSLOT_TYPE_PCIEGEN3X16 0xb6 /* PCI Express Gen 3 x16 */
#define SMBIOS_SYSSLOT_TYPE_PCIEGEN4 0xb8 /* PCI Express Gen 4 */
#define SMBIOS_SYSSLOT_TYPE_PCIEGEN4X1 0xb9 /* PCI Express Gen 4 x1 */
#define SMBIOS_SYSSLOT_TYPE_PCIEGEN4X2 0xba /* PCI Express Gen 4 x2 */
#define SMBIOS_SYSSLOT_TYPE_PCIEGEN4X4 0xbb /* PCI Express Gen 4 x4 */
#define SMBIOS_SYSSLOT_TYPE_PCIEGEN4X8 0xbc /* PCI Express Gen 4 x8 */
#define SMBIOS_SYSSLOT_TYPE_PCIEGEN4X16 0xbd /* PCI Express Gen 4 x16 */
/* Slot Data Bus Width */
#define SMBIOS_SYSSLOT_WIDTH_OTHER 1
#define SMBIOS_SYSSLOT_WIDTH_UNKNOWN 2
#define SMBIOS_SYSSLOT_WIDTH_8BIT 3
#define SMBIOS_SYSSLOT_WIDTH_16BIT 4
#define SMBIOS_SYSSLOT_WIDTH_32BIT 5
#define SMBIOS_SYSSLOT_WIDTH_64BIT 6
#define SMBIOS_SYSSLOT_WIDTH_128BIT 7
#define SMBIOS_SYSSLOT_WIDTH_1X 8
#define SMBIOS_SYSSLOT_WIDTH_2X 9
#define SMBIOS_SYSSLOT_WIDTH_4X 10
#define SMBIOS_SYSSLOT_WIDTH_8X 11
#define SMBIOS_SYSSLOT_WIDTH_12X 12
#define SMBIOS_SYSSLOT_WIDTH_16X 13
#define SMBIOS_SYSSLOT_WIDTH_32X 14
/* Current Usage */
#define SMBIOS_SYSSLOT_USAGE_OTHER 1
#define SMBIOS_SYSSLOT_USAGE_UNKNOWN 2
#define SMBIOS_SYSSLOT_USAGE_AVAILABLE 3
#define SMBIOS_SYSSLOT_USAGE_INUSE 4
#define SMBIOS_SYSSLOT_USAGE_NA 5
/* Slot Length */
#define SMBIOS_SYSSLOT_LENG_OTHER 1
#define SMBIOS_SYSSLOT_LENG_UNKNOWN 2
#define SMBIOS_SYSSLOT_LENG_SHORT 3
#define SMBIOS_SYSSLOT_LENG_LONG 4
#define SMBIOS_SYSSLOT_LENG_2_5INDRV 5
#define SMBIOS_SYSSLOT_LENG_3_5INDRV 6
/* Slot Characteristics 1 */
#define SMBIOS_SYSSLOT_CHAR_UND 1 /* BIT(0) */
#define SMBIOS_SYSSLOT_CHAR_5V 2 /* BIT(1) */
#define SMBIOS_SYSSLOT_CHAR_3_3V 4 /* BIT(2) */
#define SMBIOS_SYSSLOT_CHAR_SHARED 8 /* BIT(3) */
#define SMBIOS_SYSSLOT_CHAR_PCCARD16 16 /* BIT(4) */
#define SMBIOS_SYSSLOT_CHAR_PCCARDBUS 32 /* BIT(5) */
#define SMBIOS_SYSSLOT_CHAR_PCCARDZV 64 /* BIT(6) */
#define SMBIOS_SYSSLOT_CHAR_PCCARDMRR 0x80 /* BIT(7) */
/* Slot Characteristics 2 */
#define SMBIOS_SYSSLOT_CHAR_PCIPME 1 /* BIT(0) */
#define SMBIOS_SYSSLOT_CHAR_HOTPLUG 2 /* BIT(1) */
#define SMBIOS_SYSSLOT_CHAR_PCISMB 4 /* BIT(2) */
#define SMBIOS_SYSSLOT_CHAR_PCIBIF 8 /* BIT(3) */
#define SMBIOS_SYSSLOT_CHAR_ASYNCRM 16 /* BIT(4) */
#define SMBIOS_SYSSLOT_CHAR_FBCXL1 32 /* BIT(5) */
#define SMBIOS_SYSSLOT_CHAR_FBCXL2 64 /* BIT(6) */
#define SMBIOS_SYSSLOT_CHAR_FBCXL3 0x80 /* BIT(7) */
/* Slot segment group number */
#define SMBIOS_SYSSLOT_SGGNUM_UND 0
/* Physical Memory Array */
/* Location */
#define SMBIOS_MA_LOCATION_OTHER 1
#define SMBIOS_MA_LOCATION_UNKNOWN 2
#define SMBIOS_MA_LOCATION_MOTHERBOARD 3
/* Use */
#define SMBIOS_MA_USE_OTHER 1
#define SMBIOS_MA_USE_UNKNOWN 2
#define SMBIOS_MA_USE_SYSTEM 3
#define SMBIOS_MA_USE_VIDEO 4
#define SMBIOS_MA_USE_FLASH 5
#define SMBIOS_MA_USE_NVRAM 6
#define SMBIOS_MA_USE_CACHE 7
/* Error Correction Type */
#define SMBIOS_MA_ERRCORR_OTHER 1
#define SMBIOS_MA_ERRCORR_UNKNOWN 2
#define SMBIOS_MA_ERRCORR_NONE 3
#define SMBIOS_MA_ERRCORR_PARITY 4
#define SMBIOS_MA_ERRCORR_SBITECC 5
#define SMBIOS_MA_ERRCORR_MBITECC 6
#define SMBIOS_MA_ERRCORR_CRC 7
/* Error Information Handle */
#define SMBIOS_MA_ERRINFO_NONE 0xFFFE
#define SMBIOS_MA_ERRINFO_NOERR 0xFFFF
/* Memory Device */
/* Size */
#define SMBIOS_MD_SIZE_UNKNOWN 0xFFFF
#define SMBIOS_MD_SIZE_EXT 0x7FFF
/* Form Factor */
#define SMBIOS_MD_FF_OTHER 1
#define SMBIOS_MD_FF_UNKNOWN 2
#define SMBIOS_MD_FF_SIMM 3
#define SMBIOS_MD_FF_SIP 4
#define SMBIOS_MD_FF_CHIP 5
#define SMBIOS_MD_FF_DIP 6
#define SMBIOS_MD_FF_ZIP 7
#define SMBIOS_MD_FF_PROPCARD 8
#define SMBIOS_MD_FF_DIMM 9
#define SMBIOS_MD_FF_TSOP 10
#define SMBIOS_MD_FF_ROC 11
#define SMBIOS_MD_FF_RIMM 12
#define SMBIOS_MD_FF_SODIMM 13
#define SMBIOS_MD_FF_SRIMM 14
#define SMBIOS_MD_FF_FBDIMM 15
#define SMBIOS_MD_FF_DIE 16
/* Device set */
#define SMBIOS_MD_DEVSET_NONE 0
#define SMBIOS_MD_DEVSET_UNKNOWN 0xFF
/* Speed */
#define SMBIOS_MD_SPEED_UNKNOWN 0
#define SMBIOS_MD_SPEED_EXT 0xFFFF
/* Attributes */
#define SMBIOS_MD_ATTR_RANK_UNKNOWN 0
/* Configured Memory Speed */
#define SMBIOS_MD_CONFSPEED_UNKNOWN 0
#define SMBIOS_MD_CONFSPEED_EXT 0xFFFF
/* Voltage */
#define SMBIOS_MD_VOLTAGE_UNKNOWN 0
/* Type */
#define SMBIOS_MD_TYPE_OTHER 1
#define SMBIOS_MD_TYPE_UNKNOWN 2
#define SMBIOS_MD_TYPE_DRAM 3
#define SMBIOS_MD_TYPE_EDRAM 4
#define SMBIOS_MD_TYPE_VRAM 5
#define SMBIOS_MD_TYPE_SRAM 6
#define SMBIOS_MD_TYPE_RAM 7
#define SMBIOS_MD_TYPE_ROM 8
#define SMBIOS_MD_TYPE_FLASH 9
#define SMBIOS_MD_TYPE_EEPROM 10
#define SMBIOS_MD_TYPE_FEPROM 11
#define SMBIOS_MD_TYPE_EPROM 12
#define SMBIOS_MD_TYPE_CDRAM 13
#define SMBIOS_MD_TYPE_3DRAM 14
#define SMBIOS_MD_TYPE_SDRAM 15
#define SMBIOS_MD_TYPE_SGRAM 16
#define SMBIOS_MD_TYPE_RDRAM 17
#define SMBIOS_MD_TYPE_DDR 18
#define SMBIOS_MD_TYPE_DDR2 19
#define SMBIOS_MD_TYPE_DDR2FBD 20
#define SMBIOS_MD_TYPE_RSVD1 21
#define SMBIOS_MD_TYPE_RSVD2 22
#define SMBIOS_MD_TYPE_DSVD3 23
#define SMBIOS_MD_TYPE_DDR3 24
#define SMBIOS_MD_TYPE_FBD2 25
#define SMBIOS_MD_TYPE_DDR4 26
#define SMBIOS_MD_TYPE_LPDDR 27
#define SMBIOS_MD_TYPE_LPDDR2 28
#define SMBIOS_MD_TYPE_LPDDR3 29
#define SMBIOS_MD_TYPE_LPDDR4 30
#define SMBIOS_MD_TYPE_LNVD 31
#define SMBIOS_MD_TYPE_HBM 32
#define SMBIOS_MD_TYPE_HBM2 33
#define SMBIOS_MD_TYPE_DDR5 34
#define SMBIOS_MD_TYPE_LPDDR5 35
#define SMBIOS_MD_TYPE_HBM3 36
/* Type Detail */
#define SMBIOS_MD_TD_RSVD 1 /* BIT(0), set to 0 */
#define SMBIOS_MD_TD_OTHER 2 /* BIT(1) */
#define SMBIOS_MD_TD_UNKNOWN 4 /* BIT(2) */
#define SMBIOS_MD_TD_FP 8 /* BIT(3) */
#define SMBIOS_MD_TD_SC 0x10 /* BIT(4) */
#define SMBIOS_MD_TD_PS 0x20 /* BIT(5) */
#define SMBIOS_MD_TD_RAMBUS 0x40 /* BIT(6) */
#define SMBIOS_MD_TD_SYNC 0x80 /* BIT(7) */
#define SMBIOS_MD_TD_CMOS 0x100 /* BIT(8) */
#define SMBIOS_MD_TD_EDO 0x200 /* BIT(9) */
#define SMBIOS_MD_TD_WINDRAM 0x400 /* BIT(10) */
#define SMBIOS_MD_TD_CACHEDRAM 0x800 /* BIT(11) */
#define SMBIOS_MD_TD_NV 0x1000 /* BIT(12) */
#define SMBIOS_MD_TD_RGSTD 0x2000 /* BIT(13) */
#define SMBIOS_MD_TD_UNRGSTD 0x4000 /* BIT(14) */
#define SMBIOS_MD_TD_LRDIMM 0x8000 /* BIT(15) */
/* Technology */
#define SMBIOS_MD_TECH_OTHER 1
#define SMBIOS_MD_TECH_UNKNOWN 2
#define SMBIOS_MD_TECH_DRAM 3
#define SMBIOS_MD_TECH_NVDIMMN 4
#define SMBIOS_MD_TECH_NVDIMMF 5
#define SMBIOS_MD_TECH_NVDIMMP 6
#define SMBIOS_MD_TECH_OPTANE 7
/* Operating Mode Capability */
#define SMBIOS_MD_OPMC_RSVD 1 /* BIT(0), set to 0 */
#define SMBIOS_MD_OPMC_OTHER 2 /* BIT(1) */
#define SMBIOS_MD_OPMC_UNKNOWN 4 /* BIT(2) */
#define SMBIOS_MD_OPMC_VM 8 /* BIT(3) */
#define SMBIOS_MD_OPMC_BYTEAPM 0x10 /* BIT(4) */
#define SMBIOS_MD_OPMC_BLKAPM 0x20 /* BIT(5) */
/* Bit 6:15 Reserved, set to 0 */
/* Non-volatile / Volatile / Cache / Logical portion Size */
#define SMBIOS_MD_PORT_SIZE_NONE 0
#define SMBIOS_MD_PORT_SIZE_UNKNOWN_HI 0xFFFFFFFF
#define SMBIOS_MD_PORT_SIZE_UNKNOWN_LO 0xFFFFFFFF
#define SMBIOS_MS_PORT_SIZE_UNKNOWN 0xFFFFFFFFFFFFFFFF
/* Error Information Handle */
#define SMBIOS_MD_ERRINFO_NONE 0xFFFE
#define SMBIOS_MD_ERRINFO_NOERR 0xFFFF
/* Memory Array Mapped Address */
/* Partition Width */
#define SMBIOS_MAMA_PW_DEF 1 /* not partitioned */
#endif /* _SMBIOS_DEF_H_ */

View File

@@ -12,6 +12,7 @@
struct udevice;
#define SYSINFO_CACHE_LVL_MAX 3
#define SYSINFO_MEM_HANDLE_MAX 8
/*
* This uclass encapsulates hardware methods to gather information about a
@@ -149,6 +150,9 @@ enum sysinfo_id {
SYSID_SM_CACHE_INFO_END =
SYSID_SM_CACHE_INST_SIZE2 + SYSINFO_CACHE_LVL_MAX - 1,
/* Memory Array (Type 16) */
SYSID_SM_MEMARRAY_HANDLE,
/* For show_board_info() */
SYSID_BOARD_MODEL,
SYSID_BOARD_MANUFACTURER,

File diff suppressed because it is too large Load Diff