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net: phy: Add driver for Motorcomm yt8531 gigabit ethernet phy
Add a driver for the motorcomm yt8531 gigabit ethernet phy. We have verified the driver on StarFive VisionFive2 board. Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
This commit is contained in:
Yanhong Wang
committed by
Leo Yu-Chi Liang
Leo Yu-Chi Liang
parent
8e21064cb3
commit
e92ed065ba
@@ -220,6 +220,12 @@ config PHY_MICREL_KSZ8XXX
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endif # PHY_MICREL
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config PHY_MOTORCOMM
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tristate "Motorcomm PHYs"
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help
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Enables support for Motorcomm network PHYs.
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Currently supports the YT8531 Gigabit Ethernet PHYs.
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config PHY_MSCC
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bool "Microsemi Corp Ethernet PHYs support"
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@@ -24,6 +24,7 @@ obj-$(CONFIG_PHY_MARVELL_10G) += marvell10g.o
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obj-$(CONFIG_PHY_MICREL_KSZ8XXX) += micrel_ksz8xxx.o
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obj-$(CONFIG_PHY_MICREL_KSZ90X1) += micrel_ksz90x1.o
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obj-$(CONFIG_PHY_MESON_GXL) += meson-gxl.o
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obj-$(CONFIG_PHY_MOTORCOMM) += motorcomm.o
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obj-$(CONFIG_PHY_NATSEMI) += natsemi.o
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obj-$(CONFIG_PHY_NXP_C45_TJA11XX) += nxp-c45-tja11xx.o
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obj-$(CONFIG_PHY_NXP_TJA11XX) += nxp-tja11xx.o
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437
drivers/net/phy/motorcomm.c
Normal file
437
drivers/net/phy/motorcomm.c
Normal file
@@ -0,0 +1,437 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Motorcomm 8531 PHY driver.
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*
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* Copyright (C) 2023 StarFive Technology Co., Ltd.
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*/
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#include <config.h>
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#include <common.h>
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#include <malloc.h>
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#include <phy.h>
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#include <linux/bitfield.h>
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#define PHY_ID_YT8531 0x4f51e91b
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#define PHY_ID_MASK GENMASK(31, 0)
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/* Extended Register's Address Offset Register */
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#define YTPHY_PAGE_SELECT 0x1E
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/* Extended Register's Data Register */
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#define YTPHY_PAGE_DATA 0x1F
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#define YTPHY_SYNCE_CFG_REG 0xA012
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#define YTPHY_DTS_OUTPUT_CLK_DIS 0
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#define YTPHY_DTS_OUTPUT_CLK_25M 25000000
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#define YTPHY_DTS_OUTPUT_CLK_125M 125000000
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#define YT8531_SCR_SYNCE_ENABLE BIT(6)
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/* 1b0 output 25m clock *default*
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* 1b1 output 125m clock
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*/
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#define YT8531_SCR_CLK_FRE_SEL_125M BIT(4)
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#define YT8531_SCR_CLK_SRC_MASK GENMASK(3, 1)
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#define YT8531_SCR_CLK_SRC_PLL_125M 0
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#define YT8531_SCR_CLK_SRC_UTP_RX 1
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#define YT8531_SCR_CLK_SRC_SDS_RX 2
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#define YT8531_SCR_CLK_SRC_CLOCK_FROM_DIGITAL 3
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#define YT8531_SCR_CLK_SRC_REF_25M 4
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#define YT8531_SCR_CLK_SRC_SSC_25M 5
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/* 1b0 use original tx_clk_rgmii *default*
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* 1b1 use inverted tx_clk_rgmii.
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*/
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#define YT8531_RC1R_TX_CLK_SEL_INVERTED BIT(14)
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#define YT8531_RC1R_RX_DELAY_MASK GENMASK(13, 10)
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#define YT8531_RC1R_FE_TX_DELAY_MASK GENMASK(7, 4)
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#define YT8531_RC1R_GE_TX_DELAY_MASK GENMASK(3, 0)
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#define YT8531_RC1R_RGMII_0_000_NS 0
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#define YT8531_RC1R_RGMII_0_150_NS 1
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#define YT8531_RC1R_RGMII_0_300_NS 2
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#define YT8531_RC1R_RGMII_0_450_NS 3
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#define YT8531_RC1R_RGMII_0_600_NS 4
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#define YT8531_RC1R_RGMII_0_750_NS 5
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#define YT8531_RC1R_RGMII_0_900_NS 6
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#define YT8531_RC1R_RGMII_1_050_NS 7
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#define YT8531_RC1R_RGMII_1_200_NS 8
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#define YT8531_RC1R_RGMII_1_350_NS 9
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#define YT8531_RC1R_RGMII_1_500_NS 10
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#define YT8531_RC1R_RGMII_1_650_NS 11
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#define YT8531_RC1R_RGMII_1_800_NS 12
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#define YT8531_RC1R_RGMII_1_950_NS 13
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#define YT8531_RC1R_RGMII_2_100_NS 14
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#define YT8531_RC1R_RGMII_2_250_NS 15
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/* Phy gmii clock gating Register */
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#define YT8531_CLOCK_GATING_REG 0xC
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#define YT8531_CGR_RX_CLK_EN BIT(12)
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/* Specific Status Register */
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#define YTPHY_SPECIFIC_STATUS_REG 0x11
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#define YTPHY_DUPLEX_MASK BIT(13)
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#define YTPHY_DUPLEX_SHIFT 13
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#define YTPHY_SPEED_MODE_MASK GENMASK(15, 14)
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#define YTPHY_SPEED_MODE_SHIFT 14
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#define YT8531_EXTREG_SLEEP_CONTROL1_REG 0x27
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#define YT8531_ESC1R_SLEEP_SW BIT(15)
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#define YT8531_ESC1R_PLLON_SLP BIT(14)
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#define YT8531_RGMII_CONFIG1_REG 0xA003
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#define YT8531_CHIP_CONFIG_REG 0xA001
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#define YT8531_CCR_SW_RST BIT(15)
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/* 1b0 disable 1.9ns rxc clock delay *default*
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* 1b1 enable 1.9ns rxc clock delay
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*/
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#define YT8531_CCR_RXC_DLY_EN BIT(8)
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#define YT8531_CCR_RXC_DLY_1_900_NS 1900
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/* bits in struct ytphy_plat_priv->flag */
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#define TX_CLK_ADJ_ENABLED BIT(0)
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#define AUTO_SLEEP_DISABLED BIT(1)
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#define KEEP_PLL_ENABLED BIT(2)
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#define TX_CLK_10_INVERTED BIT(3)
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#define TX_CLK_100_INVERTED BIT(4)
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#define TX_CLK_1000_INVERTED BIT(5)
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struct ytphy_plat_priv {
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u32 rx_delay_ps;
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u32 tx_delay_ps;
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u32 clk_out_frequency;
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u32 flag;
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};
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/**
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* struct ytphy_cfg_reg_map - map a config value to a register value
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* @cfg: value in device configuration
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* @reg: value in the register
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*/
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struct ytphy_cfg_reg_map {
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u32 cfg;
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u32 reg;
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};
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static const struct ytphy_cfg_reg_map ytphy_rgmii_delays[] = {
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/* for tx delay / rx delay with YT8531_CCR_RXC_DLY_EN is not set. */
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{ 0, YT8531_RC1R_RGMII_0_000_NS },
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{ 150, YT8531_RC1R_RGMII_0_150_NS },
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{ 300, YT8531_RC1R_RGMII_0_300_NS },
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{ 450, YT8531_RC1R_RGMII_0_450_NS },
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{ 600, YT8531_RC1R_RGMII_0_600_NS },
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{ 750, YT8531_RC1R_RGMII_0_750_NS },
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{ 900, YT8531_RC1R_RGMII_0_900_NS },
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{ 1050, YT8531_RC1R_RGMII_1_050_NS },
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{ 1200, YT8531_RC1R_RGMII_1_200_NS },
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{ 1350, YT8531_RC1R_RGMII_1_350_NS },
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{ 1500, YT8531_RC1R_RGMII_1_500_NS },
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{ 1650, YT8531_RC1R_RGMII_1_650_NS },
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{ 1800, YT8531_RC1R_RGMII_1_800_NS },
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{ 1950, YT8531_RC1R_RGMII_1_950_NS }, /* default tx/rx delay */
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{ 2100, YT8531_RC1R_RGMII_2_100_NS },
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{ 2250, YT8531_RC1R_RGMII_2_250_NS },
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/* only for rx delay with YT8531_CCR_RXC_DLY_EN is set. */
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{ 0 + YT8531_CCR_RXC_DLY_1_900_NS, YT8531_RC1R_RGMII_0_000_NS },
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{ 150 + YT8531_CCR_RXC_DLY_1_900_NS, YT8531_RC1R_RGMII_0_150_NS },
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{ 300 + YT8531_CCR_RXC_DLY_1_900_NS, YT8531_RC1R_RGMII_0_300_NS },
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{ 450 + YT8531_CCR_RXC_DLY_1_900_NS, YT8531_RC1R_RGMII_0_450_NS },
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{ 600 + YT8531_CCR_RXC_DLY_1_900_NS, YT8531_RC1R_RGMII_0_600_NS },
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{ 750 + YT8531_CCR_RXC_DLY_1_900_NS, YT8531_RC1R_RGMII_0_750_NS },
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{ 900 + YT8531_CCR_RXC_DLY_1_900_NS, YT8531_RC1R_RGMII_0_900_NS },
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{ 1050 + YT8531_CCR_RXC_DLY_1_900_NS, YT8531_RC1R_RGMII_1_050_NS },
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{ 1200 + YT8531_CCR_RXC_DLY_1_900_NS, YT8531_RC1R_RGMII_1_200_NS },
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{ 1350 + YT8531_CCR_RXC_DLY_1_900_NS, YT8531_RC1R_RGMII_1_350_NS },
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{ 1500 + YT8531_CCR_RXC_DLY_1_900_NS, YT8531_RC1R_RGMII_1_500_NS },
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{ 1650 + YT8531_CCR_RXC_DLY_1_900_NS, YT8531_RC1R_RGMII_1_650_NS },
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{ 1800 + YT8531_CCR_RXC_DLY_1_900_NS, YT8531_RC1R_RGMII_1_800_NS },
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{ 1950 + YT8531_CCR_RXC_DLY_1_900_NS, YT8531_RC1R_RGMII_1_950_NS },
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{ 2100 + YT8531_CCR_RXC_DLY_1_900_NS, YT8531_RC1R_RGMII_2_100_NS },
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{ 2250 + YT8531_CCR_RXC_DLY_1_900_NS, YT8531_RC1R_RGMII_2_250_NS }
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};
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static u32 ytphy_get_delay_reg_value(struct phy_device *phydev,
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u32 val,
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u16 *rxc_dly_en)
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{
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int tb_size = ARRAY_SIZE(ytphy_rgmii_delays);
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int tb_size_half = tb_size / 2;
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int i;
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/* when rxc_dly_en is NULL, it is get the delay for tx, only half of
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* tb_size is valid.
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*/
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if (!rxc_dly_en)
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tb_size = tb_size_half;
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for (i = 0; i < tb_size; i++) {
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if (ytphy_rgmii_delays[i].cfg == val) {
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if (rxc_dly_en && i < tb_size_half)
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*rxc_dly_en = 0;
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return ytphy_rgmii_delays[i].reg;
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}
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}
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pr_warn("Unsupported value %d, using default (%u)\n",
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val, YT8531_RC1R_RGMII_1_950_NS);
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/* when rxc_dly_en is not NULL, it is get the delay for rx.
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* The rx default in dts and ytphy_rgmii_clk_delay_config is 1950 ps,
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* so YT8531_CCR_RXC_DLY_EN should not be set.
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*/
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if (rxc_dly_en)
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*rxc_dly_en = 0;
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return YT8531_RC1R_RGMII_1_950_NS;
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}
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static int ytphy_modify_ext(struct phy_device *phydev, u16 regnum, u16 mask,
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u16 set)
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{
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int ret;
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ret = phy_write(phydev, MDIO_DEVAD_NONE, YTPHY_PAGE_SELECT, regnum);
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if (ret < 0)
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return ret;
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return phy_modify(phydev, MDIO_DEVAD_NONE, YTPHY_PAGE_DATA, mask, set);
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}
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static int ytphy_rgmii_clk_delay_config(struct phy_device *phydev)
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{
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struct ytphy_plat_priv *priv = phydev->priv;
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u16 rxc_dly_en = YT8531_CCR_RXC_DLY_EN;
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u32 rx_reg, tx_reg;
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u16 mask, val = 0;
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int ret;
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rx_reg = ytphy_get_delay_reg_value(phydev, priv->rx_delay_ps,
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&rxc_dly_en);
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tx_reg = ytphy_get_delay_reg_value(phydev, priv->tx_delay_ps,
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NULL);
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switch (phydev->interface) {
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case PHY_INTERFACE_MODE_RGMII:
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rxc_dly_en = 0;
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break;
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case PHY_INTERFACE_MODE_RGMII_RXID:
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val |= FIELD_PREP(YT8531_RC1R_RX_DELAY_MASK, rx_reg);
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break;
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case PHY_INTERFACE_MODE_RGMII_TXID:
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rxc_dly_en = 0;
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val |= FIELD_PREP(YT8531_RC1R_GE_TX_DELAY_MASK, tx_reg);
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break;
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case PHY_INTERFACE_MODE_RGMII_ID:
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val |= FIELD_PREP(YT8531_RC1R_RX_DELAY_MASK, rx_reg) |
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FIELD_PREP(YT8531_RC1R_GE_TX_DELAY_MASK, tx_reg);
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break;
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default: /* do not support other modes */
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return -EOPNOTSUPP;
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}
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ret = ytphy_modify_ext(phydev, YT8531_CHIP_CONFIG_REG,
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YT8531_CCR_RXC_DLY_EN, rxc_dly_en);
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if (ret < 0)
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return ret;
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/* Generally, it is not necessary to adjust YT8531_RC1R_FE_TX_DELAY */
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mask = YT8531_RC1R_RX_DELAY_MASK | YT8531_RC1R_GE_TX_DELAY_MASK;
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return ytphy_modify_ext(phydev, YT8531_RGMII_CONFIG1_REG, mask, val);
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}
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static int yt8531_parse_status(struct phy_device *phydev)
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{
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int val;
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int speed, speed_mode;
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val = phy_read(phydev, MDIO_DEVAD_NONE, YTPHY_SPECIFIC_STATUS_REG);
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if (val < 0)
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return val;
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speed_mode = (val & YTPHY_SPEED_MODE_MASK) >> YTPHY_SPEED_MODE_SHIFT;
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switch (speed_mode) {
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case 2:
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speed = SPEED_1000;
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break;
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case 1:
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speed = SPEED_100;
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break;
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default:
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speed = SPEED_10;
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break;
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}
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phydev->speed = speed;
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phydev->duplex = (val & YTPHY_DUPLEX_MASK) >> YTPHY_DUPLEX_SHIFT;
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return 0;
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}
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static int yt8531_startup(struct phy_device *phydev)
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{
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struct ytphy_plat_priv *priv = phydev->priv;
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u16 val = 0;
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int ret;
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ret = genphy_update_link(phydev);
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if (ret)
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return ret;
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ret = yt8531_parse_status(phydev);
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if (ret)
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return ret;
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if (phydev->speed < 0)
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return -EINVAL;
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if (!(priv->flag & TX_CLK_ADJ_ENABLED))
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return 0;
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switch (phydev->speed) {
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case SPEED_1000:
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if (priv->flag & TX_CLK_1000_INVERTED)
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val = YT8531_RC1R_TX_CLK_SEL_INVERTED;
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break;
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case SPEED_100:
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if (priv->flag & TX_CLK_100_INVERTED)
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val = YT8531_RC1R_TX_CLK_SEL_INVERTED;
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break;
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case SPEED_10:
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if (priv->flag & TX_CLK_10_INVERTED)
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val = YT8531_RC1R_TX_CLK_SEL_INVERTED;
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break;
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default:
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printf("UNKNOWN SPEED\n");
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return -EINVAL;
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}
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ret = ytphy_modify_ext(phydev, YT8531_RGMII_CONFIG1_REG,
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YT8531_RC1R_TX_CLK_SEL_INVERTED, val);
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if (ret < 0)
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pr_warn("Modify TX_CLK_SEL err:%d\n", ret);
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return 0;
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}
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static void ytphy_dt_parse(struct phy_device *phydev)
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{
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struct ytphy_plat_priv *priv = phydev->priv;
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priv->clk_out_frequency = ofnode_read_u32_default(phydev->node,
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"motorcomm,clk-out-frequency-hz",
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YTPHY_DTS_OUTPUT_CLK_DIS);
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priv->rx_delay_ps = ofnode_read_u32_default(phydev->node,
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"rx-internal-delay-ps",
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YT8531_RC1R_RGMII_1_950_NS);
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priv->tx_delay_ps = ofnode_read_u32_default(phydev->node,
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"tx-internal-delay-ps",
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YT8531_RC1R_RGMII_1_950_NS);
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if (ofnode_read_bool(phydev->node, "motorcomm,auto-sleep-disabled"))
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priv->flag |= AUTO_SLEEP_DISABLED;
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if (ofnode_read_bool(phydev->node, "motorcomm,keep-pll-enabled"))
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priv->flag |= KEEP_PLL_ENABLED;
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if (ofnode_read_bool(phydev->node, "motorcomm,tx-clk-adj-enabled"))
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priv->flag |= TX_CLK_ADJ_ENABLED;
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if (ofnode_read_bool(phydev->node, "motorcomm,tx-clk-10-inverted"))
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priv->flag |= TX_CLK_10_INVERTED;
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if (ofnode_read_bool(phydev->node, "motorcomm,tx-clk-100-inverted"))
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priv->flag |= TX_CLK_100_INVERTED;
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|
||||
if (ofnode_read_bool(phydev->node, "motorcomm,tx-clk-1000-inverted"))
|
||||
priv->flag |= TX_CLK_1000_INVERTED;
|
||||
}
|
||||
|
||||
static int yt8531_config(struct phy_device *phydev)
|
||||
{
|
||||
struct ytphy_plat_priv *priv = phydev->priv;
|
||||
u16 mask, val;
|
||||
int ret;
|
||||
|
||||
ret = genphy_config_aneg(phydev);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
ytphy_dt_parse(phydev);
|
||||
switch (priv->clk_out_frequency) {
|
||||
case YTPHY_DTS_OUTPUT_CLK_DIS:
|
||||
mask = YT8531_SCR_SYNCE_ENABLE;
|
||||
val = 0;
|
||||
break;
|
||||
case YTPHY_DTS_OUTPUT_CLK_25M:
|
||||
mask = YT8531_SCR_SYNCE_ENABLE | YT8531_SCR_CLK_SRC_MASK |
|
||||
YT8531_SCR_CLK_FRE_SEL_125M;
|
||||
val = YT8531_SCR_SYNCE_ENABLE |
|
||||
FIELD_PREP(YT8531_SCR_CLK_SRC_MASK,
|
||||
YT8531_SCR_CLK_SRC_REF_25M);
|
||||
break;
|
||||
case YTPHY_DTS_OUTPUT_CLK_125M:
|
||||
mask = YT8531_SCR_SYNCE_ENABLE | YT8531_SCR_CLK_SRC_MASK |
|
||||
YT8531_SCR_CLK_FRE_SEL_125M;
|
||||
val = YT8531_SCR_SYNCE_ENABLE | YT8531_SCR_CLK_FRE_SEL_125M |
|
||||
FIELD_PREP(YT8531_SCR_CLK_SRC_MASK,
|
||||
YT8531_SCR_CLK_SRC_PLL_125M);
|
||||
break;
|
||||
default:
|
||||
pr_warn("Freq err:%u\n", priv->clk_out_frequency);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ret = ytphy_modify_ext(phydev, YTPHY_SYNCE_CFG_REG, mask,
|
||||
val);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
ret = ytphy_rgmii_clk_delay_config(phydev);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
if (priv->flag & AUTO_SLEEP_DISABLED) {
|
||||
/* disable auto sleep */
|
||||
ret = ytphy_modify_ext(phydev,
|
||||
YT8531_EXTREG_SLEEP_CONTROL1_REG,
|
||||
YT8531_ESC1R_SLEEP_SW, 0);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (priv->flag & KEEP_PLL_ENABLED) {
|
||||
/* enable RXC clock when no wire plug */
|
||||
ret = ytphy_modify_ext(phydev,
|
||||
YT8531_CLOCK_GATING_REG,
|
||||
YT8531_CGR_RX_CLK_EN, 0);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int yt8531_probe(struct phy_device *phydev)
|
||||
{
|
||||
struct ytphy_plat_priv *priv;
|
||||
|
||||
priv = calloc(1, sizeof(struct ytphy_plat_priv));
|
||||
if (!priv)
|
||||
return -ENOMEM;
|
||||
|
||||
phydev->priv = priv;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
U_BOOT_PHY_DRIVER(motorcomm8531) = {
|
||||
.name = "YT8531 Gigabit Ethernet",
|
||||
.uid = PHY_ID_YT8531,
|
||||
.mask = PHY_ID_MASK,
|
||||
.features = PHY_GBIT_FEATURES,
|
||||
.probe = &yt8531_probe,
|
||||
.config = &yt8531_config,
|
||||
.startup = &yt8531_startup,
|
||||
.shutdown = &genphy_shutdown,
|
||||
};
|
||||
Reference in New Issue
Block a user