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drivers: phy: phy-mtk-ufs: disable clk in power_off

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Disable clocks in power_off(). Also define ufs_mtk_phy_set_inactive()
helper function to keep consistency with power_on() and
ufs_mtk_phy_set_active().

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260318-mt8195-add-ufs-support-v2-4-f18eeeeb0e72@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
This commit is contained in:
Julien Stephan
2026-03-18 17:50:56 +01:00
committed by David Lechner
parent ad2422cc05
commit ebb222e8c5
1 changed files with 32 additions and 22 deletions
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54
drivers/phy/phy-mtk-ufs.c
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@@ -88,34 +88,44 @@ static int mtk_phy_power_on(struct phy *phy)
return 0;
}
static void ufs_mtk_phy_set_inactive(struct mtk_ufs_phy *phy)
{
/* Set PHY to Deep Hibernate mode */
setbits_le32(phy->mmio + MP_LN_DIG_RX_9C, FSM_DIFZ_FRC);
/* force DA_MP_RX0_SQ_EN */
setbits_le32(phy->mmio + MP_LN_DIG_RX_AC, FRC_RX_SQ_EN);
clrbits_le32(phy->mmio + MP_LN_DIG_RX_AC, RX_SQ_EN);
/* force DA_MP_CDR_ISO_EN */
setbits_le32(phy->mmio + MP_LN_RX_44, FRC_CDR_ISO_EN);
setbits_le32(phy->mmio + MP_LN_RX_44, CDR_ISO_EN);
/* force DA_MP_CDR_PWR_ON */
setbits_le32(phy->mmio + MP_LN_RX_44, FRC_CDR_PWR_ON);
clrbits_le32(phy->mmio + MP_LN_RX_44, CDR_PWR_ON);
/* force DA_MP_PLL_ISO_EN */
setbits_le32(phy->mmio + MP_GLB_DIG_8C, FRC_PLL_ISO_EN);
setbits_le32(phy->mmio + MP_GLB_DIG_8C, PLL_ISO_EN);
/* force DA_MP_PLL_PWR_ON */
setbits_le32(phy->mmio + MP_GLB_DIG_8C, FRC_FRC_PWR_ON);
clrbits_le32(phy->mmio + MP_GLB_DIG_8C, PLL_PWR_ON);
}
static int mtk_phy_power_off(struct phy *phy)
{
struct mtk_ufs_phy *ufs_phy = dev_get_priv(phy->dev);
int ret;
/* Set PHY to Deep Hibernate mode */
setbits_le32(ufs_phy->mmio + MP_LN_DIG_RX_9C, FSM_DIFZ_FRC);
ufs_mtk_phy_set_inactive(ufs_phy);
/* force DA_MP_RX0_SQ_EN */
setbits_le32(ufs_phy->mmio + MP_LN_DIG_RX_AC, FRC_RX_SQ_EN);
clrbits_le32(ufs_phy->mmio + MP_LN_DIG_RX_AC, RX_SQ_EN);
ret = clk_disable_bulk(&ufs_phy->clk_bulk);
if (ret)
dev_err(phy->dev, "failed to disable clocks (ret=%d)\n", ret);
/* force DA_MP_CDR_ISO_EN */
setbits_le32(ufs_phy->mmio + MP_LN_RX_44, FRC_CDR_ISO_EN);
setbits_le32(ufs_phy->mmio + MP_LN_RX_44, CDR_ISO_EN);
/* force DA_MP_CDR_PWR_ON */
setbits_le32(ufs_phy->mmio + MP_LN_RX_44, FRC_CDR_PWR_ON);
clrbits_le32(ufs_phy->mmio + MP_LN_RX_44, CDR_PWR_ON);
/* force DA_MP_PLL_ISO_EN */
setbits_le32(ufs_phy->mmio + MP_GLB_DIG_8C, FRC_PLL_ISO_EN);
setbits_le32(ufs_phy->mmio + MP_GLB_DIG_8C, PLL_ISO_EN);
/* force DA_MP_PLL_PWR_ON */
setbits_le32(ufs_phy->mmio + MP_GLB_DIG_8C, FRC_FRC_PWR_ON);
clrbits_le32(ufs_phy->mmio + MP_GLB_DIG_8C, PLL_PWR_ON);
return 0;
return ret;
}
static const struct phy_ops mtk_ufs_phy_ops = {