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rockchip: Use common bss and stack addresses on RK3328

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With the stack and text base used by U-Boot SPL and proper on RK3328
there is a high likelihood of overlapping when U-Boot proper + FDT nears
or exceeded 1 MiB in size.

Currently the following memory layout is typically used on RK3328:
[    0, 256K) - SPL binary
[ 256K,   2M) - TF-A / reserved
[   2M,   +X) - U-Boot proper binary (TEXT_BASE)
[   -X,   3M) - U-Boot proper pre-reloc stack (CUSTOM_SYS_INIT_SP_ADDR)
[  -8K,   3M)   - pre-reloc malloc heap (SYS_MALLOC_F_LEN)
[   -X,   4M) - SPL pre-reloc stack (SPL_STACK)
[  -8K,   4M)   - pre-reloc malloc heap (SPL_SYS_MALLOC_F_LEN)
[   -X,   6M) - SPL reloc stack (SPL_STACK_R_ADDR)
[   5M,   6M)   - reloc malloc heap (SPL_STACK_R_MALLOC_SIMPLE_LEN)
[  32M,  +8K) - SPL bss (SPL_BSS_START_ADDR, SPL_BSS_MAX_SIZE)

SPL can safely load U-Boot proper + FDT to [2M, 4M-8K) with this layout.
However, the stack at [-X, 3M) used during U-Boot proper pre-reloc is
restricting the safe size of U-Boot proper + FDT to be less than 1 MiB.

Migrate to use common bss, stack and malloc heap size and addresses to
fix this restriction and allow for a larger U-Boot proper image size.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Jonas Karlman
2024-03-02 19:16:13 +00:00
committed by Kever Yang
parent 41098d2e3e
commit f01a399203
10 changed files with 4 additions and 146 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
arch/arm/mach-rockchip/rk3328/Kconfig
View File

@@ -21,13 +21,7 @@ config ROCKCHIP_STIMER_BASE
config SYS_SOC
default "rk3328"
config SYS_MALLOC_F_LEN
default 0x2000
config SPL_LIBCOMMON_SUPPORT
default y
config SPL_LIBGENERIC_SUPPORT
config ROCKCHIP_COMMON_STACK_ADDR
default y
config TPL_LDSCRIPT
@@ -39,6 +33,9 @@ config TPL_TEXT_BASE
config TPL_STACK
default 0xff098000
config TPL_SYS_MALLOC_F_LEN
default 0x800
source "board/rockchip/evb_rk3328/Kconfig"
endif

17
configs/evb-rk3328_defconfig
View File

@@ -2,22 +2,12 @@ CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_TEXT_BASE=0x00200000
CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3328-evb"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3328=y
CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
CONFIG_TPL_LIBCOMMON_SUPPORT=y
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_STACK_R_ADDR=0x4000000
CONFIG_SPL_STACK=0x400000
CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
CONFIG_SPL_SYS_MALLOC_F_LEN=0x4000
CONFIG_DEBUG_UART_BASE=0xFF130000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
@@ -33,16 +23,9 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-evb.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x2000000
CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
CONFIG_SPL_ATF=y
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL_SYS_MALLOC_SIMPLE=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y

15
configs/nanopi-r2c-plus-rk3328_defconfig
View File

@@ -2,22 +2,13 @@ CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_TEXT_BASE=0x00200000
CONFIG_SPL_GPIO=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3328-nanopi-r2c-plus"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3328=y
CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
CONFIG_TPL_LIBCOMMON_SUPPORT=y
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_SPL_STACK=0x400000
CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
CONFIG_DEBUG_UART_BASE=0xFF130000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
@@ -33,16 +24,10 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2c-plus.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x2000000
CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_POWER=y
CONFIG_SPL_ATF=y
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL_SYS_MALLOC_SIMPLE=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y

15
configs/nanopi-r2c-rk3328_defconfig
View File

@@ -2,22 +2,13 @@ CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_TEXT_BASE=0x00200000
CONFIG_SPL_GPIO=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3328-nanopi-r2c"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3328=y
CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
CONFIG_TPL_LIBCOMMON_SUPPORT=y
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_SPL_STACK=0x400000
CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
CONFIG_DEBUG_UART_BASE=0xFF130000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
@@ -33,16 +24,10 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2c.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x2000000
CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_POWER=y
CONFIG_SPL_ATF=y
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL_SYS_MALLOC_SIMPLE=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y

15
configs/nanopi-r2s-rk3328_defconfig
View File

@@ -2,22 +2,13 @@ CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_TEXT_BASE=0x00200000
CONFIG_SPL_GPIO=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3328-nanopi-r2s"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3328=y
CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
CONFIG_TPL_LIBCOMMON_SUPPORT=y
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_SPL_STACK=0x400000
CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
CONFIG_DEBUG_UART_BASE=0xFF130000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
@@ -33,16 +24,10 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2s.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x2000000
CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_POWER=y
CONFIG_SPL_ATF=y
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL_SYS_MALLOC_SIMPLE=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y

15
configs/orangepi-r1-plus-lts-rk3328_defconfig
View File

@@ -2,23 +2,14 @@ CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_TEXT_BASE=0x00200000
CONFIG_SPL_GPIO=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus-lts"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3328=y
CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
CONFIG_ROCKCHIP_SPI_IMAGE=y
CONFIG_TPL_LIBCOMMON_SUPPORT=y
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_SPL_STACK=0x400000
CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
CONFIG_DEBUG_UART_BASE=0xFF130000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
@@ -36,18 +27,12 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-orangepi-r1-plus-lts.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x2000000
CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_POWER=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
CONFIG_SPL_ATF=y
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL_SYS_MALLOC_SIMPLE=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y

15
configs/orangepi-r1-plus-rk3328_defconfig
View File

@@ -2,23 +2,14 @@ CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_TEXT_BASE=0x00200000
CONFIG_SPL_GPIO=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3328=y
CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
CONFIG_ROCKCHIP_SPI_IMAGE=y
CONFIG_TPL_LIBCOMMON_SUPPORT=y
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_SPL_STACK=0x400000
CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
CONFIG_DEBUG_UART_BASE=0xFF130000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
@@ -36,18 +27,12 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-orangepi-r1-plus.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x2000000
CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_POWER=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
CONFIG_SPL_ATF=y
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL_SYS_MALLOC_SIMPLE=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y

15
configs/roc-cc-rk3328_defconfig
View File

@@ -2,22 +2,13 @@ CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_TEXT_BASE=0x00200000
CONFIG_SPL_GPIO=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3328-roc-cc"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3328=y
CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
CONFIG_TPL_LIBCOMMON_SUPPORT=y
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_SPL_STACK=0x400000
CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
CONFIG_DEBUG_UART_BASE=0xFF130000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
@@ -33,16 +24,10 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-roc-cc.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x2000000
CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_POWER=y
CONFIG_SPL_ATF=y
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL_SYS_MALLOC_SIMPLE=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y

17
configs/rock-pi-e-rk3328_defconfig
View File

@@ -2,23 +2,13 @@ CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_TEXT_BASE=0x00200000
CONFIG_SPL_GPIO=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3328-rock-pi-e"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3328=y
CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
CONFIG_TPL_LIBCOMMON_SUPPORT=y
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_STACK_R_ADDR=0x4000000
CONFIG_SPL_STACK=0x400000
CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
CONFIG_SPL_SYS_MALLOC_F_LEN=0x4000
CONFIG_DEBUG_UART_BASE=0xFF130000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
@@ -34,17 +24,10 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-rock-pi-e.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x2000000
CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
CONFIG_SPL_POWER=y
CONFIG_SPL_ATF=y
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL_SYS_MALLOC_SIMPLE=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y

15
configs/rock64-rk3328_defconfig
View File

@@ -2,23 +2,14 @@ CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_TEXT_BASE=0x00200000
CONFIG_SPL_GPIO=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3328-rock64"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3328=y
CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
CONFIG_ROCKCHIP_SPI_IMAGE=y
CONFIG_TPL_LIBCOMMON_SUPPORT=y
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_SPL_STACK=0x400000
CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
CONFIG_DEBUG_UART_BASE=0xFF130000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
@@ -36,18 +27,12 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-rock64.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x2000000
CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_POWER=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
CONFIG_SPL_ATF=y
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL_SYS_MALLOC_SIMPLE=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y