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https://source.denx.de/u-boot/u-boot.git
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Merge tag 'i2c-updates-for-2026.07-rc3' of https://source.denx.de/u-boot/custodians/u-boot-i2c
updates for 2026.07-rc3 - designware_i2c: Staticize driver ops from Marek - i2c: Remove legacy CONFIG_SYS_I2C_SOFT -
This commit is contained in:
Tom Rini
92
README
92
README
@@ -628,98 +628,6 @@ The following options need to be configured:
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If you do not have i2c muxes on your board, omit this define.
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- Legacy I2C Support:
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If you use the software i2c interface (CONFIG_SYS_I2C_SOFT)
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then the following macros need to be defined (examples are
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from include/configs/lwmon.h):
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I2C_INIT
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(Optional). Any commands necessary to enable the I2C
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controller or configure ports.
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eg: #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
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I2C_ACTIVE
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The code necessary to make the I2C data line active
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(driven). If the data line is open collector, this
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define can be null.
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eg: #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
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I2C_TRISTATE
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The code necessary to make the I2C data line tri-stated
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(inactive). If the data line is open collector, this
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define can be null.
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eg: #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
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I2C_READ
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Code that returns true if the I2C data line is high,
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false if it is low.
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eg: #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
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I2C_SDA(bit)
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If <bit> is true, sets the I2C data line high. If it
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is false, it clears it (low).
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eg: #define I2C_SDA(bit) \
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if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
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else immr->im_cpm.cp_pbdat &= ~PB_SDA
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I2C_SCL(bit)
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If <bit> is true, sets the I2C clock line high. If it
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is false, it clears it (low).
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eg: #define I2C_SCL(bit) \
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if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
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else immr->im_cpm.cp_pbdat &= ~PB_SCL
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I2C_DELAY
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This delay is invoked four times per clock cycle so this
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controls the rate of data transfer. The data rate thus
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is 1 / (I2C_DELAY * 4). Often defined to be something
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like:
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#define I2C_DELAY udelay(2)
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CONFIG_SOFT_I2C_GPIO_SCL / CONFIG_SOFT_I2C_GPIO_SDA
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If your arch supports the generic GPIO framework (asm/gpio.h),
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then you may alternatively define the two GPIOs that are to be
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used as SCL / SDA. Any of the previous I2C_xxx macros will
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have GPIO-based defaults assigned to them as appropriate.
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You should define these to the GPIO value as given directly to
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the generic GPIO functions.
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CFG_SYS_I2C_NOPROBES
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This option specifies a list of I2C devices that will be skipped
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when the 'i2c probe' command is issued.
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e.g.
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#define CFG_SYS_I2C_NOPROBES {0x50,0x68}
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will skip addresses 0x50 and 0x68 on a board with one I2C bus
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CONFIG_SOFT_I2C_READ_REPEATED_START
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defining this will force the i2c_read() function in
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the soft_i2c driver to perform an I2C repeated start
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between writing the address pointer and reading the
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data. If this define is omitted the default behaviour
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of doing a stop-start sequence will be used. Most I2C
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devices can use either method, but some require one or
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the other.
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- SPI Support: CONFIG_SPI
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Enables SPI driver (so far only tested with
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@@ -90,10 +90,6 @@ MCFFEC_TOUT_LOOP -- set FEC timeout loop
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CONFIG_MCFTMR -- define to use DMA timer
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CONFIG_SYS_I2C_FSL -- define to use FSL common I2C driver
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CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged
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CONFIG_SYS_I2C_SPEED -- define for I2C speed
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CONFIG_SYS_I2C_SLAVE -- define for I2C slave address
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CONFIG_SYS_I2C_OFFSET -- define for I2C base address offset
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CONFIG_SYS_IMMR -- define for MBAR offset
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CFG_SYS_MBAR -- define MBAR offset
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@@ -89,10 +89,6 @@ MCFFEC_TOUT_LOOP -- set FEC timeout loop
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CONFIG_MCFTMR -- define to use DMA timer
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CONFIG_SYS_I2C_FSL -- define to use FSL common I2C driver
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CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged
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CONFIG_SYS_I2C_SPEED -- define for I2C speed
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CONFIG_SYS_I2C_SLAVE -- define for I2C slave address
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CONFIG_SYS_I2C_OFFSET -- define for I2C base address offset
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CONFIG_SYS_IMMR -- define for MBAR offset
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CFG_SYS_MBAR -- define MBAR offset
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@@ -624,26 +624,6 @@ config SH_I2C_CLOCK
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default 104000000
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endif
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config SYS_I2C_SOFT
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bool "Legacy software I2C interface"
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depends on !COMPILE_TEST
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help
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Enable the legacy software defined I2C interface
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config SYS_I2C_SOFT_SPEED
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int "Software I2C bus speed"
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depends on SYS_I2C_SOFT
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default 100000
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help
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Speed of the software I2C bus
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config SYS_I2C_SOFT_SLAVE
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hex "Software I2C slave address"
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depends on SYS_I2C_SOFT
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default 0xfe
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help
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Slave address of the software I2C bus
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config SYS_I2C_OCTEON
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bool "Octeon II/III/TX/TX2 I2C driver"
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depends on (ARCH_OCTEON || ARCH_OCTEONTX || ARCH_OCTEONTX2) && DM_I2C
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@@ -47,7 +47,6 @@ obj-$(CONFIG_SYS_I2C_RZ_RIIC) += rz_riic.o
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obj-$(CONFIG_SYS_I2C_S3C24X0) += s3c24x0_i2c.o exynos_hs_i2c.o
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obj-$(CONFIG_SYS_I2C_SANDBOX) += sandbox_i2c.o i2c-emul-uclass.o
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obj-$(CONFIG_SYS_I2C_SH) += sh_i2c.o
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obj-$(CONFIG_SYS_I2C_SOFT) += soft_i2c.o
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obj-$(CONFIG_SYS_I2C_STM32F7) += stm32f7_i2c.o
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obj-$(CONFIG_SYS_I2C_SUN6I_P2WI) += sun6i_p2wi.o
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obj-$(CONFIG_SYS_I2C_SUN8I_RSB) += sun8i_rsb.o
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@@ -168,7 +168,7 @@ static int dw_i2c_acpi_fill_ssdt(const struct udevice *dev,
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return 0;
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}
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struct acpi_ops dw_i2c_acpi_ops = {
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static struct acpi_ops dw_i2c_acpi_ops = {
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.fill_ssdt = dw_i2c_acpi_fill_ssdt,
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};
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@@ -1,418 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2009
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* Heiko Schocher, DENX Software Engineering, hs@denx.de.
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* Changes for multibus/multiadapter I2C support.
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*
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* (C) Copyright 2001, 2002
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* This has been changed substantially by Gerald Van Baren, Custom IDEAS,
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* vanbaren@cideas.com. It was heavily influenced by LiMon, written by
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* Neil Russell.
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*
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* NOTE: This driver should be converted to driver model before June 2017.
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* Please see doc/driver-model/i2c-howto.rst for instructions.
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*/
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#include <config.h>
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#if defined(CONFIG_AT91FAMILY)
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#include <asm/io.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/at91_pio.h>
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#ifdef CONFIG_ATMEL_LEGACY
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#include <asm/arch/gpio.h>
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#endif
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#endif
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#include <i2c.h>
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#include <linux/delay.h>
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#if defined(CONFIG_SOFT_I2C_GPIO_SCL)
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# include <asm/gpio.h>
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# ifndef I2C_GPIO_SYNC
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# define I2C_GPIO_SYNC
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# endif
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# ifndef I2C_INIT
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# define I2C_INIT \
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do { \
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gpio_request(CONFIG_SOFT_I2C_GPIO_SCL, "soft_i2c"); \
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gpio_request(CONFIG_SOFT_I2C_GPIO_SDA, "soft_i2c"); \
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} while (0)
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# endif
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# ifndef I2C_ACTIVE
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# define I2C_ACTIVE do { } while (0)
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# endif
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# ifndef I2C_TRISTATE
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# define I2C_TRISTATE do { } while (0)
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# endif
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# ifndef I2C_READ
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# define I2C_READ gpio_get_value(CONFIG_SOFT_I2C_GPIO_SDA)
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# endif
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# ifndef I2C_SDA
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# define I2C_SDA(bit) \
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do { \
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if (bit) \
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gpio_direction_input(CONFIG_SOFT_I2C_GPIO_SDA); \
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else \
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gpio_direction_output(CONFIG_SOFT_I2C_GPIO_SDA, 0); \
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I2C_GPIO_SYNC; \
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} while (0)
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# endif
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# ifndef I2C_SCL
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# define I2C_SCL(bit) \
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do { \
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gpio_direction_output(CONFIG_SOFT_I2C_GPIO_SCL, bit); \
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I2C_GPIO_SYNC; \
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} while (0)
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# endif
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# ifndef I2C_DELAY
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# define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
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# endif
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#endif
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/* #define DEBUG_I2C */
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#ifndef I2C_SOFT_DECLARATIONS
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# define I2C_SOFT_DECLARATIONS
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#endif
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/*-----------------------------------------------------------------------
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* Definitions
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*/
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#define RETRIES 0
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#define I2C_ACK 0 /* PD_SDA level to ack a byte */
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#define I2C_NOACK 1 /* PD_SDA level to noack a byte */
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#ifdef DEBUG_I2C
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#define PRINTD(fmt,args...) do { \
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printf (fmt ,##args); \
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} while (0)
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#else
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#define PRINTD(fmt,args...)
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#endif
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/*-----------------------------------------------------------------------
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* Local functions
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*/
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static void send_reset (void);
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static void send_start (void);
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static void send_stop (void);
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static void send_ack (int);
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static int write_byte (uchar byte);
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static uchar read_byte (int);
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/*-----------------------------------------------------------------------
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* Send a reset sequence consisting of 9 clocks with the data signal high
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* to clock any confused device back into an idle state. Also send a
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* <stop> at the end of the sequence for belts & suspenders.
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*/
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static void send_reset(void)
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{
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I2C_SOFT_DECLARATIONS /* intentional without ';' */
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int j;
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I2C_SCL(1);
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I2C_SDA(1);
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#ifdef I2C_INIT
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I2C_INIT;
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#endif
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I2C_TRISTATE;
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for(j = 0; j < 9; j++) {
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I2C_SCL(0);
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I2C_DELAY;
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I2C_DELAY;
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I2C_SCL(1);
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I2C_DELAY;
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I2C_DELAY;
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}
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send_stop();
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I2C_TRISTATE;
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}
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/*-----------------------------------------------------------------------
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* START: High -> Low on SDA while SCL is High
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*/
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static void send_start(void)
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{
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I2C_SOFT_DECLARATIONS /* intentional without ';' */
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I2C_DELAY;
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I2C_SDA(1);
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I2C_ACTIVE;
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I2C_DELAY;
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I2C_SCL(1);
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I2C_DELAY;
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I2C_SDA(0);
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I2C_DELAY;
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}
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/*-----------------------------------------------------------------------
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* STOP: Low -> High on SDA while SCL is High
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*/
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static void send_stop(void)
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{
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I2C_SOFT_DECLARATIONS /* intentional without ';' */
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I2C_SCL(0);
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I2C_DELAY;
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I2C_SDA(0);
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I2C_ACTIVE;
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I2C_DELAY;
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I2C_SCL(1);
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I2C_DELAY;
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I2C_SDA(1);
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I2C_DELAY;
|
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I2C_TRISTATE;
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}
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/*-----------------------------------------------------------------------
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* ack should be I2C_ACK or I2C_NOACK
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*/
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static void send_ack(int ack)
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{
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I2C_SOFT_DECLARATIONS /* intentional without ';' */
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|
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I2C_SCL(0);
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I2C_DELAY;
|
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I2C_ACTIVE;
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I2C_SDA(ack);
|
||||
I2C_DELAY;
|
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I2C_SCL(1);
|
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I2C_DELAY;
|
||||
I2C_DELAY;
|
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I2C_SCL(0);
|
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I2C_DELAY;
|
||||
}
|
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|
||||
/*-----------------------------------------------------------------------
|
||||
* Send 8 bits and look for an acknowledgement.
|
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*/
|
||||
static int write_byte(uchar data)
|
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{
|
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I2C_SOFT_DECLARATIONS /* intentional without ';' */
|
||||
int j;
|
||||
int nack;
|
||||
|
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I2C_ACTIVE;
|
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for(j = 0; j < 8; j++) {
|
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I2C_SCL(0);
|
||||
I2C_DELAY;
|
||||
I2C_SDA(data & 0x80);
|
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I2C_DELAY;
|
||||
I2C_SCL(1);
|
||||
I2C_DELAY;
|
||||
I2C_DELAY;
|
||||
|
||||
data <<= 1;
|
||||
}
|
||||
|
||||
/*
|
||||
* Look for an <ACK>(negative logic) and return it.
|
||||
*/
|
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I2C_SCL(0);
|
||||
I2C_DELAY;
|
||||
I2C_SDA(1);
|
||||
I2C_TRISTATE;
|
||||
I2C_DELAY;
|
||||
I2C_SCL(1);
|
||||
I2C_DELAY;
|
||||
I2C_DELAY;
|
||||
nack = I2C_READ;
|
||||
I2C_SCL(0);
|
||||
I2C_DELAY;
|
||||
I2C_ACTIVE;
|
||||
|
||||
return(nack); /* not a nack is an ack */
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* if ack == I2C_ACK, ACK the byte so can continue reading, else
|
||||
* send I2C_NOACK to end the read.
|
||||
*/
|
||||
static uchar read_byte(int ack)
|
||||
{
|
||||
I2C_SOFT_DECLARATIONS /* intentional without ';' */
|
||||
int data;
|
||||
int j;
|
||||
|
||||
/*
|
||||
* Read 8 bits, MSB first.
|
||||
*/
|
||||
I2C_TRISTATE;
|
||||
I2C_SDA(1);
|
||||
data = 0;
|
||||
for(j = 0; j < 8; j++) {
|
||||
I2C_SCL(0);
|
||||
I2C_DELAY;
|
||||
I2C_SCL(1);
|
||||
I2C_DELAY;
|
||||
data <<= 1;
|
||||
data |= I2C_READ;
|
||||
I2C_DELAY;
|
||||
}
|
||||
send_ack(ack);
|
||||
|
||||
return(data);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Initialization
|
||||
*/
|
||||
static void soft_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
|
||||
{
|
||||
/*
|
||||
* WARNING: Do NOT save speed in a static variable: if the
|
||||
* I2C routines are called before RAM is initialized (to read
|
||||
* the DIMM SPD, for instance), RAM won't be usable and your
|
||||
* system will crash.
|
||||
*/
|
||||
send_reset ();
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Probe to see if a chip is present. Also good for checking for the
|
||||
* completion of EEPROM writes since the chip stops responding until
|
||||
* the write completes (typically 10mSec).
|
||||
*/
|
||||
static int soft_i2c_probe(struct i2c_adapter *adap, uint8_t addr)
|
||||
{
|
||||
int rc;
|
||||
|
||||
/*
|
||||
* perform 1 byte write transaction with just address byte
|
||||
* (fake write)
|
||||
*/
|
||||
send_start();
|
||||
rc = write_byte ((addr << 1) | 0);
|
||||
send_stop();
|
||||
|
||||
return (rc ? 1 : 0);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Read bytes
|
||||
*/
|
||||
static int soft_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
|
||||
int alen, uchar *buffer, int len)
|
||||
{
|
||||
int shift;
|
||||
PRINTD("i2c_read: chip %02X addr %02X alen %d buffer %p len %d\n",
|
||||
chip, addr, alen, buffer, len);
|
||||
|
||||
#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
|
||||
/*
|
||||
* EEPROM chips that implement "address overflow" are ones
|
||||
* like Catalyst 24WC04/08/16 which has 9/10/11 bits of
|
||||
* address and the extra bits end up in the "chip address"
|
||||
* bit slots. This makes a 24WC08 (1Kbyte) chip look like
|
||||
* four 256 byte chips.
|
||||
*
|
||||
* Note that we consider the length of the address field to
|
||||
* still be one byte because the extra address bits are
|
||||
* hidden in the chip address.
|
||||
*/
|
||||
chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
|
||||
|
||||
PRINTD("i2c_read: fix addr_overflow: chip %02X addr %02X\n",
|
||||
chip, addr);
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Do the addressing portion of a write cycle to set the
|
||||
* chip's address pointer. If the address length is zero,
|
||||
* don't do the normal write cycle to set the address pointer,
|
||||
* there is no address pointer in this chip.
|
||||
*/
|
||||
send_start();
|
||||
if(alen > 0) {
|
||||
if(write_byte(chip << 1)) { /* write cycle */
|
||||
send_stop();
|
||||
PRINTD("i2c_read, no chip responded %02X\n", chip);
|
||||
return(1);
|
||||
}
|
||||
shift = (alen-1) * 8;
|
||||
while(alen-- > 0) {
|
||||
if(write_byte(addr >> shift)) {
|
||||
PRINTD("i2c_read, address not <ACK>ed\n");
|
||||
return(1);
|
||||
}
|
||||
shift -= 8;
|
||||
}
|
||||
|
||||
/* Some I2C chips need a stop/start sequence here,
|
||||
* other chips don't work with a full stop and need
|
||||
* only a start. Default behaviour is to send the
|
||||
* stop/start sequence.
|
||||
*/
|
||||
#ifdef CONFIG_SOFT_I2C_READ_REPEATED_START
|
||||
send_start();
|
||||
#else
|
||||
send_stop();
|
||||
send_start();
|
||||
#endif
|
||||
}
|
||||
/*
|
||||
* Send the chip address again, this time for a read cycle.
|
||||
* Then read the data. On the last byte, we do a NACK instead
|
||||
* of an ACK(len == 0) to terminate the read.
|
||||
*/
|
||||
write_byte((chip << 1) | 1); /* read cycle */
|
||||
while(len-- > 0) {
|
||||
*buffer++ = read_byte(len == 0);
|
||||
}
|
||||
send_stop();
|
||||
return(0);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Write bytes
|
||||
*/
|
||||
static int soft_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
|
||||
int alen, uchar *buffer, int len)
|
||||
{
|
||||
int shift, failures = 0;
|
||||
|
||||
PRINTD("i2c_write: chip %02X addr %02X alen %d buffer %p len %d\n",
|
||||
chip, addr, alen, buffer, len);
|
||||
|
||||
send_start();
|
||||
if(write_byte(chip << 1)) { /* write cycle */
|
||||
send_stop();
|
||||
PRINTD("i2c_write, no chip responded %02X\n", chip);
|
||||
return(1);
|
||||
}
|
||||
shift = (alen-1) * 8;
|
||||
while(alen-- > 0) {
|
||||
if(write_byte(addr >> shift)) {
|
||||
PRINTD("i2c_write, address not <ACK>ed\n");
|
||||
return(1);
|
||||
}
|
||||
shift -= 8;
|
||||
}
|
||||
|
||||
while(len-- > 0) {
|
||||
if(write_byte(*buffer++)) {
|
||||
failures++;
|
||||
}
|
||||
}
|
||||
send_stop();
|
||||
return(failures);
|
||||
}
|
||||
|
||||
/*
|
||||
* Register soft i2c adapters
|
||||
*/
|
||||
U_BOOT_I2C_ADAP_COMPLETE(soft00, soft_i2c_init, soft_i2c_probe,
|
||||
soft_i2c_read, soft_i2c_write, NULL,
|
||||
CONFIG_SYS_I2C_SOFT_SPEED, CONFIG_SYS_I2C_SOFT_SLAVE,
|
||||
0)
|
||||
|
||||
Reference in New Issue
Block a user