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rockchip: rk3288: do not generate u-boot.rom anymore

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This was only used on RK3288 Chromebooks and the EVB.

If it follows the same pattern as for RK3399 Chromebooks where their
maintainer (Simon) agreed[1] to removal of u-boot.rom on the basis that
the generic u-boot-rockchip-spi.bin is now enough, let's do the same for
RK3288 and remove the last Rockchip users of u-boot.rom (and HAS_ROM
symbol).

At the same time, remove HAS_ROM symbol from the RK3288 Chromebooks and
EVB configs since they were used only for that.

SYS_SPI_U_BOOT_OFFS offset in rockchip-u-boot.dtsi for the u-boot-img
node of simple-bin-spi binman image matches the one used in u-boot.rom
except for the EVB.
The EVB doesn't have ROCKCHIP_SPI_IMAGE symbol enabled, so HAS_ROM had
no effect anyway. Even if it had, this would not have been enough
considering that SPL_SPI_LOAD symbol is not set, so U-Boot proper could
not be loaded from SPI even if SPL/TPL does.

Make sure u-boot-rockchip-spi.bin has the same size of u-boot.rom for
Chromebooks as that seems to be important.

[1] https://lore.kernel.org/u-boot/CAFLszTh-SewFod8dEOF3+e-wCE1qFF0CyxxR8CbQwy3BRW3k6w@mail.gmail.com/

Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Simon Glass <sjg@chromium.org>  # chromebook-kevin
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
This commit is contained in:
Quentin Schulz
2025-05-05 16:47:19 +02:00
committed by Kever Yang
parent 1f140fefa6
commit f9b4d051a7
3 changed files with 8 additions and 29 deletions
Download Patch File Download Diff File Expand all files Collapse all files

24
arch/arm/dts/rk3288-u-boot.dtsi
View File

@@ -46,30 +46,6 @@
};
};
#if defined(CONFIG_ROCKCHIP_SPI_IMAGE) && defined(CONFIG_HAS_ROM)
&binman {
rom {
filename = "u-boot.rom";
size = <0x400000>;
pad-byte = <0xff>;
mkimage {
args = "-n rk3288 -T rkspi";
u-boot-spl {
};
};
u-boot-img {
offset = <0x20000>;
};
u-boot {
offset = <0x300000>;
};
fdtmap {
};
};
};
#endif
&bus_intmem {
ddr_sram: ddr-sram@1000 {
compatible = "rockchip,rk3288-ddr-sram";

8
arch/arm/dts/rk3288-veyron-u-boot.dtsi
View File

@@ -11,6 +11,14 @@
};
};
#if defined(CONFIG_ROCKCHIP_SPI_IMAGE)
&binman {
simple-bin-spi {
size = <0x400000>;
};
};
#endif
&dmc {
logic-supply = <&vdd_logic>;
rockchip,odt-disable-freq = <333000000>;

5
arch/arm/mach-rockchip/rk3288/Kconfig
View File

@@ -5,7 +5,6 @@ choice
config TARGET_CHROMEBOOK_JERRY
bool "Google/Rockchip Veyron-Jerry Chromebook"
select HAS_ROM
select BOARD_LATE_INIT
select ROCKCHIP_SPI_IMAGE
help
@@ -16,7 +15,6 @@ config TARGET_CHROMEBOOK_JERRY
config TARGET_CHROMEBIT_MICKEY
bool "Google/Rockchip Veyron-Mickey Chromebit"
select HAS_ROM
select BOARD_LATE_INIT
select ROCKCHIP_SPI_IMAGE
help
@@ -28,7 +26,6 @@ config TARGET_CHROMEBIT_MICKEY
config TARGET_CHROMEBOOK_MINNIE
bool "Google/Rockchip Veyron-Minnie Chromebook"
select HAS_ROM
select BOARD_LATE_INIT
select ROCKCHIP_SPI_IMAGE
help
@@ -41,7 +38,6 @@ config TARGET_CHROMEBOOK_MINNIE
config TARGET_CHROMEBOOK_SPEEDY
bool "Google/Rockchip Veyron-Speedy Chromebook"
select HAS_ROM
select BOARD_LATE_INIT
select ROCKCHIP_SPI_IMAGE
help
@@ -54,7 +50,6 @@ config TARGET_CHROMEBOOK_SPEEDY
config TARGET_EVB_RK3288
bool "Evb-RK3288"
select HAS_ROM
select BOARD_LATE_INIT
select TPL
help