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clk/qcom: move ipq4019 driver from mach-ipq40xx

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This driver is just a stub, but it's necessary to support the upcoming
reset driver changes.

Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
This commit is contained in:
Caleb Connolly
2023-11-07 12:41:00 +00:00
parent a623c14f43
commit fac2121a47
6 changed files with 13 additions and 40 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
arch/arm/Kconfig
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@@ -776,6 +776,7 @@ config ARCH_IPQ40XX
select CLK
select SMEM
select OF_CONTROL
select CLK_QCOM_IPQ4019
imply CMD_DM
config ARCH_KEYSTONE

1
arch/arm/mach-ipq40xx/Makefile
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@@ -4,6 +4,5 @@
#
# Author: Robert Marko <robert.marko@sartura.hr>
obj-y += clock-ipq4019.o
obj-y += pinctrl-snapdragon.o
obj-y += pinctrl-ipq4019.o

8
drivers/clk/qcom/Kconfig
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@@ -23,6 +23,14 @@ config CLK_QCOM_APQ8096
on the Snapdragon APQ8096 SoC. This driver supports the clocks
and resets exposed by the GCC hardware block.
config CLK_QCOM_IPQ4019
bool "Qualcomm IPQ4019 GCC"
select CLK_QCOM
help
Say Y here to enable support for the Global Clock Controller
on the Snapdragon IPQ4019 SoC. This driver supports the clocks
and resets exposed by the GCC hardware block.
config CLK_QCOM_QCS404
bool "Qualcomm QCS404 GCC"
select CLK_QCOM

1
drivers/clk/qcom/Makefile
View File

@@ -6,4 +6,5 @@ obj-y += clock-qcom.o
obj-$(CONFIG_CLK_QCOM_SDM845) += clock-sdm845.o
obj-$(CONFIG_CLK_QCOM_APQ8016) += clock-apq8016.o
obj-$(CONFIG_CLK_QCOM_APQ8096) += clock-apq8096.o
obj-$(CONFIG_CLK_QCOM_IPQ4019) += clock-ipq4019.o
obj-$(CONFIG_CLK_QCOM_QCS404) += clock-qcs404.o

41
arch/arm/mach-ipq40xx/clock-ipq4019.c → drivers/clk/qcom/clock-ipq4019.c
View File

@@ -12,12 +12,9 @@
#include <common.h>
#include <dm.h>
#include <errno.h>
#include <dt-bindings/clock/qcom,ipq4019-gcc.h>
struct msm_clk_priv {
phys_addr_t base;
};
#include "clock-qcom.h"
ulong msm_set_rate(struct clk *clk, ulong rate)
{
@@ -30,23 +27,7 @@ ulong msm_set_rate(struct clk *clk, ulong rate)
}
}
static int msm_clk_probe(struct udevice *dev)
{
struct msm_clk_priv *priv = dev_get_priv(dev);
priv->base = dev_read_addr(dev);
if (priv->base == FDT_ADDR_T_NONE)
return -EINVAL;
return 0;
}
static ulong msm_clk_set_rate(struct clk *clk, ulong rate)
{
return msm_set_rate(clk, rate);
}
static int msm_enable(struct clk *clk)
int msm_enable(struct clk *clk)
{
switch (clk->id) {
case GCC_BLSP1_QUP1_SPI_APPS_CLK: /*SPI1*/
@@ -68,21 +49,3 @@ static int msm_enable(struct clk *clk)
}
}
static struct clk_ops msm_clk_ops = {
.set_rate = msm_clk_set_rate,
.enable = msm_enable,
};
static const struct udevice_id msm_clk_ids[] = {
{ .compatible = "qcom,gcc-ipq4019" },
{ }
};
U_BOOT_DRIVER(clk_msm) = {
.name = "clk_msm",
.id = UCLASS_CLK,
.of_match = msm_clk_ids,
.ops = &msm_clk_ops,
.priv_auto = sizeof(struct msm_clk_priv),
.probe = msm_clk_probe,
};

1
drivers/clk/qcom/clock-qcom.c
View File

@@ -166,6 +166,7 @@ static const struct udevice_id msm_clk_ids[] = {
{ .compatible = "qcom,gcc-apq8016" },
{ .compatible = "qcom,gcc-msm8996" },
{ .compatible = "qcom,gcc-apq8096" },
{ .compatible = "qcom,gcc-ipq4019" },
{ .compatible = "qcom,gcc-sdm845" },
{ .compatible = "qcom,gcc-qcs404" },
{ }