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clk: rockchip: Add support for RK3506

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Add clock driver for RK3506.

Imported from vendor U-Boot linux-6.1-stan-rkr6 tag with minor
adjustments and fixes for mainline.

Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Finley Xiao
2026-01-31 23:38:17 +00:00
committed by Tom Rini
parent a445494f24
commit fbf72dce91
6 changed files with 1581 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
arch/arm/include/asm/arch-rockchip/clock.h
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@@ -214,6 +214,16 @@ int rockchip_reset_bind(struct udevice *pdev, u32 reg_offset, u32 reg_number);
*/
int rockchip_reset_bind_lut(struct udevice *pdev, const int *lookup_table,
u32 reg_offset, u32 reg_number);
/*
* rk3506_reset_bind_lut() - Bind soft reset device as child of clock device
* using dedicated RK3506 lookup table
*
* @pdev: clock udevice
* @reg_offset: the first offset in cru for softreset registers
* @reg_number: the reg numbers of softreset registers
* Return: 0 success, or error value
*/
int rk3506_reset_bind_lut(struct udevice *pdev, u32 reg_offset, u32 reg_number);
/*
* rk3528_reset_bind_lut() - Bind soft reset device as child of clock device
* using dedicated RK3528 lookup table

181
arch/arm/include/asm/arch-rockchip/cru_rk3506.h Normal file
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@@ -0,0 +1,181 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
* Author: Finley Xiao <finley.xiao@rock-chips.com>
*/
#ifndef _ASM_ARCH_CRU_RK3506_H
#define _ASM_ARCH_CRU_RK3506_H
#include <linux/bitops.h>
#include <linux/bitfield.h>
#define MHz 1000000
#define KHz 1000
#define OSC_HZ (24 * MHz)
/* RK3506 pll id */
enum rk3506_pll_id {
GPLL,
V0PLL,
V1PLL,
PLL_COUNT,
};
struct rk3506_clk_priv {
unsigned long gpll_hz;
unsigned long gpll_div_hz;
unsigned long gpll_div_100mhz;
unsigned long v0pll_hz;
unsigned long v0pll_div_hz;
unsigned long v1pll_hz;
unsigned long v1pll_div_hz;
};
struct pll_rate_table {
unsigned long rate;
unsigned int fbdiv;
unsigned int postdiv1;
unsigned int refdiv;
unsigned int postdiv2;
unsigned int dsmpd;
unsigned int frac;
};
#define RK3506_CRU_BASE 0xff9a0000
#define RK3506_MODE_CON 0x0280
#define RK3506_CLKSEL_CON(x) (RK3506_CRU_BASE + 0x0300 + (x) * 0x4)
#define RK3506_SOFTRST_CON0 0x0a00
#define RK3506_GLB_SRST_FST 0x0c08
#define RK3506_GLB_SRST_SND 0x0c0c
#define RK3506_PLL_CON(x) (0x10000 + (x) * 0x4)
#define RK3506_SCRU_BASE 0xff9a8000
#define RK3506_PMU_CRU_BASE 0xff9b0000
#define RK3506_PMU_CLKSEL_CON(x) (RK3506_PMU_CRU_BASE + 0x0300 + (x) * 0x4)
enum {
/* CRU_CLKSEL_CON00 */
CLK_GPLL_DIV_MASK = GENMASK(9, 6),
CLK_GPLL_DIV_100M_MASK = GENMASK(13, 10),
/* CRU_CLKSEL_CON01 */
CLK_V0PLL_DIV_MASK = GENMASK(3, 0),
CLK_V1PLL_DIV_MASK = GENMASK(7, 4),
/* CRU_CLKSEL_CON15 */
CLK_CORE_SRC_DIV_MASK = GENMASK(4, 0),
CLK_CORE_SRC_SEL_MASK = GENMASK(6, 5),
CLK_CORE_SEL_GPLL = 0,
CLK_CORE_SEL_V0PLL,
CLK_CORE_SEL_V1PLL,
ACLK_CORE_DIV_MASK = GENMASK(12, 9),
/* CRU_CLKSEL_CON16 */
PCLK_CORE_DIV_MASK = GENMASK(3, 0),
/* CRU_CLKSEL_CON21 */
ACLK_BUS_DIV_MASK = GENMASK(4, 0),
ACLK_BUS_SEL_MASK = GENMASK(6, 5),
ACLK_BUS_SEL_GPLL_DIV = 0,
ACLK_BUS_SEL_V0PLL_DIV,
ACLK_BUS_SEL_V1PLL_DIV,
HCLK_BUS_DIV_MASK = GENMASK(11, 7),
HCLK_BUS_SEL_MASK = GENMASK(13, 12),
/* CRU_CLKSEL_CON22 */
PCLK_BUS_DIV_MASK = GENMASK(4, 0),
PCLK_BUS_SEL_MASK = GENMASK(6, 5),
/* CRU_CLKSEL_CON29 */
HCLK_LSPERI_DIV_MASK = GENMASK(4, 0),
HCLK_LSPERI_SEL_MASK = GENMASK(6, 5),
/* CRU_CLKSEL_CON32 */
CLK_I2C0_DIV_MASK = GENMASK(3, 0),
CLK_I2C0_SEL_MASK = GENMASK(5, 4),
CLK_I2C_SEL_GPLL = 0,
CLK_I2C_SEL_V0PLL,
CLK_I2C_SEL_V1PLL,
CLK_I2C1_DIV_MASK = GENMASK(9, 6),
CLK_I2C1_SEL_MASK = GENMASK(11, 10),
/* CRU_CLKSEL_CON33 */
CLK_I2C2_DIV_MASK = GENMASK(3, 0),
CLK_I2C2_SEL_MASK = GENMASK(5, 4),
CLK_PWM1_DIV_MASK = GENMASK(9, 6),
CLK_PWM1_SEL_MASK = GENMASK(11, 10),
CLK_PWM1_SEL_GPLL_DIV = 0,
CLK_PWM1_SEL_V0PLL_DIV,
CLK_PWM1_SEL_V1PLL_DIV,
/* CRU_CLKSEL_CON34 */
CLK_SPI0_DIV_MASK = GENMASK(7, 4),
CLK_SPI0_SEL_MASK = GENMASK(9, 8),
CLK_SPI_SEL_24M = 0,
CLK_SPI_SEL_GPLL_DIV,
CLK_SPI_SEL_V0PLL_DIV,
CLK_SPI_SEL_V1PLL_DIV,
CLK_SPI1_DIV_MASK = GENMASK(13, 10),
CLK_SPI1_SEL_MASK = GENMASK(15, 14),
/* CRU_CLKSEL_CON49 */
ACLK_HSPERI_DIV_MASK = GENMASK(4, 0),
ACLK_HSPERI_SEL_MASK = GENMASK(6, 5),
ACLK_HSPERI_SEL_GPLL_DIV = 0,
ACLK_HSPERI_SEL_V0PLL_DIV,
ACLK_HSPERI_SEL_V1PLL_DIV,
CCLK_SDMMC_DIV_MASK = GENMASK(12, 7),
CCLK_SDMMC_SEL_MASK = GENMASK(14, 13),
CCLK_SDMMC_SEL_24M = 0,
CCLK_SDMMC_SEL_GPLL,
CCLK_SDMMC_SEL_V0PLL,
CCLK_SDMMC_SEL_V1PLL,
/* CRU_CLKSEL_CON50 */
SCLK_FSPI_DIV_MASK = GENMASK(4, 0),
SCLK_FSPI_SEL_MASK = GENMASK(6, 5),
SCLK_FSPI_SEL_24M = 0,
SCLK_FSPI_SEL_GPLL,
SCLK_FSPI_SEL_V0PLL,
SCLK_FSPI_SEL_V1PLL,
CLK_MAC_DIV_MASK = GENMASK(11, 7),
/* CRU_CLKSEL_CON54 */
CLK_SARADC_DIV_MASK = GENMASK(3, 0),
CLK_SARADC_SEL_MASK = GENMASK(5, 4),
CLK_SARADC_SEL_24M = 0,
CLK_SARADC_SEL_400K,
CLK_SARADC_SEL_32K,
/* CRU_CLKSEL_CON60 */
DCLK_VOP_DIV_MASK = GENMASK(7, 0),
DCLK_VOP_SEL_MASK = GENMASK(10, 8),
DCLK_VOP_SEL_24M = 0,
DCLK_VOP_SEL_GPLL,
DCLK_VOP_SEL_V0PLL,
DCLK_VOP_SEL_V1PLL,
DCLK_VOP_SEL_FRAC_VOIC1,
DCLK_VOP_SEL_FRAC_COMMON0,
DCLK_VOP_SEL_FRAC_COMMON1,
DCLK_VOP_SEL_FRAC_COMMON2,
/* CRU_CLKSEL_CON61 */
CLK_TSADC_DIV_MASK = GENMASK(7, 0),
CLK_TSADC_TSEN_DIV_MASK = GENMASK(10, 8),
/* PMUCRU_CLKSEL_CON00 */
CLK_PWM0_DIV_MASK = GENMASK(9, 6),
CLK_MAC_OUT_DIV_MASK = GENMASK(15, 10),
/* SCRU_CLKSEL_CON104 */
CLK_PKA_CRYPTO_DIV_MASK = GENMASK(11, 7),
CLK_PKA_CRYPTO_SEL_MASK = GENMASK(13, 12),
CLK_PKA_CRYPTO_SEL_GPLL = 0,
CLK_PKA_CRYPTO_SEL_V0PLL,
CLK_PKA_CRYPTO_SEL_V1PLL,
};
#endif /* _ASM_ARCH_CRU_RK3506_H */

1
drivers/clk/rockchip/Makefile
View File

@@ -15,6 +15,7 @@ obj-$(CONFIG_ROCKCHIP_RK3308) += clk_rk3308.o
obj-$(CONFIG_ROCKCHIP_RK3328) += clk_rk3328.o
obj-$(CONFIG_ROCKCHIP_RK3368) += clk_rk3368.o
obj-$(CONFIG_ROCKCHIP_RK3399) += clk_rk3399.o
obj-$(CONFIG_ROCKCHIP_RK3506) += clk_rk3506.o
obj-$(CONFIG_ROCKCHIP_RK3528) += clk_rk3528.o
obj-$(CONFIG_ROCKCHIP_RK3568) += clk_rk3568.o
obj-$(CONFIG_ROCKCHIP_RK3576) += clk_rk3576.o

1166
drivers/clk/rockchip/clk_rk3506.c Normal file
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File diff suppressed because it is too large Load Diff

2
drivers/reset/Makefile
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@@ -16,7 +16,7 @@ obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o
obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
obj-$(CONFIG_RESET_AST2500) += reset-ast2500.o
obj-$(CONFIG_RESET_AST2600) += reset-ast2600.o
obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o rst-rk3528.o rst-rk3576.o rst-rk3588.o
obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o rst-rk3506.o rst-rk3528.o rst-rk3576.o rst-rk3588.o
obj-$(CONFIG_RESET_MESON) += reset-meson.o
obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
obj-$(CONFIG_RESET_MEDIATEK) += reset-mediatek.o

222
drivers/reset/rst-rk3506.c Normal file
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@@ -0,0 +1,222 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) 2025 Rockchip Electronics Co., Ltd.
* Author: Finley Xiao <finley.xiao@rock-chips.com>
*/
#include <dm.h>
#include <asm/arch-rockchip/clock.h>
#include <dt-bindings/reset/rockchip,rk3506-cru.h>
/* 0xFF9A0000 + 0x0A00 */
#define RK3506_CRU_RESET_OFFSET(id, reg, bit) [id] = (0 + reg * 16 + bit)
/* mapping table for reset ID to register offset */
static const int rk3506_register_offset[] = {
/* CRU-->SOFTRST_CON00 */
RK3506_CRU_RESET_OFFSET(SRST_NCOREPORESET0_AC, 0, 0),
RK3506_CRU_RESET_OFFSET(SRST_NCOREPORESET1_AC, 0, 1),
RK3506_CRU_RESET_OFFSET(SRST_NCOREPORESET2_AC, 0, 2),
RK3506_CRU_RESET_OFFSET(SRST_NCORESET0_AC, 0, 4),
RK3506_CRU_RESET_OFFSET(SRST_NCORESET1_AC, 0, 5),
RK3506_CRU_RESET_OFFSET(SRST_NCORESET2_AC, 0, 6),
RK3506_CRU_RESET_OFFSET(SRST_NL2RESET_AC, 0, 8),
RK3506_CRU_RESET_OFFSET(SRST_A_CORE_BIU_AC, 0, 9),
RK3506_CRU_RESET_OFFSET(SRST_H_M0_AC, 0, 10),
/* CRU-->SOFTRST_CON02 */
RK3506_CRU_RESET_OFFSET(SRST_NDBGRESET, 2, 10),
RK3506_CRU_RESET_OFFSET(SRST_P_CORE_BIU, 2, 14),
RK3506_CRU_RESET_OFFSET(SRST_PMU, 2, 15),
/* CRU-->SOFTRST_CON03 */
RK3506_CRU_RESET_OFFSET(SRST_P_DBG, 3, 1),
RK3506_CRU_RESET_OFFSET(SRST_POT_DBG, 3, 2),
RK3506_CRU_RESET_OFFSET(SRST_P_CORE_GRF, 3, 4),
RK3506_CRU_RESET_OFFSET(SRST_CORE_EMA_DETECT, 3, 6),
RK3506_CRU_RESET_OFFSET(SRST_REF_PVTPLL_CORE, 3, 7),
RK3506_CRU_RESET_OFFSET(SRST_P_GPIO1, 3, 8),
RK3506_CRU_RESET_OFFSET(SRST_DB_GPIO1, 3, 9),
/* CRU-->SOFTRST_CON04 */
RK3506_CRU_RESET_OFFSET(SRST_A_CORE_PERI_BIU, 4, 3),
RK3506_CRU_RESET_OFFSET(SRST_A_DSMC, 4, 5),
RK3506_CRU_RESET_OFFSET(SRST_P_DSMC, 4, 6),
RK3506_CRU_RESET_OFFSET(SRST_FLEXBUS, 4, 7),
RK3506_CRU_RESET_OFFSET(SRST_A_FLEXBUS, 4, 9),
RK3506_CRU_RESET_OFFSET(SRST_H_FLEXBUS, 4, 10),
RK3506_CRU_RESET_OFFSET(SRST_A_DSMC_SLV, 4, 11),
RK3506_CRU_RESET_OFFSET(SRST_H_DSMC_SLV, 4, 12),
RK3506_CRU_RESET_OFFSET(SRST_DSMC_SLV, 4, 13),
/* CRU-->SOFTRST_CON05 */
RK3506_CRU_RESET_OFFSET(SRST_A_BUS_BIU, 5, 3),
RK3506_CRU_RESET_OFFSET(SRST_H_BUS_BIU, 5, 4),
RK3506_CRU_RESET_OFFSET(SRST_P_BUS_BIU, 5, 5),
RK3506_CRU_RESET_OFFSET(SRST_A_SYSRAM, 5, 6),
RK3506_CRU_RESET_OFFSET(SRST_H_SYSRAM, 5, 7),
RK3506_CRU_RESET_OFFSET(SRST_A_DMAC0, 5, 8),
RK3506_CRU_RESET_OFFSET(SRST_A_DMAC1, 5, 9),
RK3506_CRU_RESET_OFFSET(SRST_H_M0, 5, 10),
RK3506_CRU_RESET_OFFSET(SRST_M0_JTAG, 5, 11),
RK3506_CRU_RESET_OFFSET(SRST_H_CRYPTO, 5, 15),
/* CRU-->SOFTRST_CON06 */
RK3506_CRU_RESET_OFFSET(SRST_H_RNG, 6, 0),
RK3506_CRU_RESET_OFFSET(SRST_P_BUS_GRF, 6, 1),
RK3506_CRU_RESET_OFFSET(SRST_P_TIMER0, 6, 2),
RK3506_CRU_RESET_OFFSET(SRST_TIMER0_CH0, 6, 3),
RK3506_CRU_RESET_OFFSET(SRST_TIMER0_CH1, 6, 4),
RK3506_CRU_RESET_OFFSET(SRST_TIMER0_CH2, 6, 5),
RK3506_CRU_RESET_OFFSET(SRST_TIMER0_CH3, 6, 6),
RK3506_CRU_RESET_OFFSET(SRST_TIMER0_CH4, 6, 7),
RK3506_CRU_RESET_OFFSET(SRST_TIMER0_CH5, 6, 8),
RK3506_CRU_RESET_OFFSET(SRST_P_WDT0, 6, 9),
RK3506_CRU_RESET_OFFSET(SRST_T_WDT0, 6, 10),
RK3506_CRU_RESET_OFFSET(SRST_P_WDT1, 6, 11),
RK3506_CRU_RESET_OFFSET(SRST_T_WDT1, 6, 12),
RK3506_CRU_RESET_OFFSET(SRST_P_MAILBOX, 6, 13),
RK3506_CRU_RESET_OFFSET(SRST_P_INTMUX, 6, 14),
RK3506_CRU_RESET_OFFSET(SRST_P_SPINLOCK, 6, 15),
/* CRU-->SOFTRST_CON07 */
RK3506_CRU_RESET_OFFSET(SRST_P_DDRC, 7, 0),
RK3506_CRU_RESET_OFFSET(SRST_H_DDRPHY, 7, 1),
RK3506_CRU_RESET_OFFSET(SRST_P_DDRMON, 7, 2),
RK3506_CRU_RESET_OFFSET(SRST_DDRMON_OSC, 7, 3),
RK3506_CRU_RESET_OFFSET(SRST_P_DDR_LPC, 7, 4),
RK3506_CRU_RESET_OFFSET(SRST_H_USBOTG0, 7, 5),
RK3506_CRU_RESET_OFFSET(SRST_USBOTG0_ADP, 7, 7),
RK3506_CRU_RESET_OFFSET(SRST_H_USBOTG1, 7, 8),
RK3506_CRU_RESET_OFFSET(SRST_USBOTG1_ADP, 7, 10),
RK3506_CRU_RESET_OFFSET(SRST_P_USBPHY, 7, 11),
RK3506_CRU_RESET_OFFSET(SRST_USBPHY_POR, 7, 12),
RK3506_CRU_RESET_OFFSET(SRST_USBPHY_OTG0, 7, 13),
RK3506_CRU_RESET_OFFSET(SRST_USBPHY_OTG1, 7, 14),
/* CRU-->SOFTRST_CON08 */
RK3506_CRU_RESET_OFFSET(SRST_A_DMA2DDR, 8, 0),
RK3506_CRU_RESET_OFFSET(SRST_P_DMA2DDR, 8, 1),
/* CRU-->SOFTRST_CON09 */
RK3506_CRU_RESET_OFFSET(SRST_USBOTG0_UTMI, 9, 0),
RK3506_CRU_RESET_OFFSET(SRST_USBOTG1_UTMI, 9, 1),
/* CRU-->SOFTRST_CON10 */
RK3506_CRU_RESET_OFFSET(SRST_A_DDRC_0, 10, 0),
RK3506_CRU_RESET_OFFSET(SRST_A_DDRC_1, 10, 1),
RK3506_CRU_RESET_OFFSET(SRST_A_DDR_BIU, 10, 2),
RK3506_CRU_RESET_OFFSET(SRST_DDRC, 10, 3),
RK3506_CRU_RESET_OFFSET(SRST_DDRMON, 10, 4),
/* CRU-->SOFTRST_CON11 */
RK3506_CRU_RESET_OFFSET(SRST_H_LSPERI_BIU, 11, 2),
RK3506_CRU_RESET_OFFSET(SRST_P_UART0, 11, 4),
RK3506_CRU_RESET_OFFSET(SRST_P_UART1, 11, 5),
RK3506_CRU_RESET_OFFSET(SRST_P_UART2, 11, 6),
RK3506_CRU_RESET_OFFSET(SRST_P_UART3, 11, 7),
RK3506_CRU_RESET_OFFSET(SRST_P_UART4, 11, 8),
RK3506_CRU_RESET_OFFSET(SRST_UART0, 11, 9),
RK3506_CRU_RESET_OFFSET(SRST_UART1, 11, 10),
RK3506_CRU_RESET_OFFSET(SRST_UART2, 11, 11),
RK3506_CRU_RESET_OFFSET(SRST_UART3, 11, 12),
RK3506_CRU_RESET_OFFSET(SRST_UART4, 11, 13),
RK3506_CRU_RESET_OFFSET(SRST_P_I2C0, 11, 14),
RK3506_CRU_RESET_OFFSET(SRST_I2C0, 11, 15),
/* CRU-->SOFTRST_CON12 */
RK3506_CRU_RESET_OFFSET(SRST_P_I2C1, 12, 0),
RK3506_CRU_RESET_OFFSET(SRST_I2C1, 12, 1),
RK3506_CRU_RESET_OFFSET(SRST_P_I2C2, 12, 2),
RK3506_CRU_RESET_OFFSET(SRST_I2C2, 12, 3),
RK3506_CRU_RESET_OFFSET(SRST_P_PWM1, 12, 4),
RK3506_CRU_RESET_OFFSET(SRST_PWM1, 12, 5),
RK3506_CRU_RESET_OFFSET(SRST_P_SPI0, 12, 10),
RK3506_CRU_RESET_OFFSET(SRST_SPI0, 12, 11),
RK3506_CRU_RESET_OFFSET(SRST_P_SPI1, 12, 12),
RK3506_CRU_RESET_OFFSET(SRST_SPI1, 12, 13),
RK3506_CRU_RESET_OFFSET(SRST_P_GPIO2, 12, 14),
RK3506_CRU_RESET_OFFSET(SRST_DB_GPIO2, 12, 15),
/* CRU-->SOFTRST_CON13 */
RK3506_CRU_RESET_OFFSET(SRST_P_GPIO3, 13, 0),
RK3506_CRU_RESET_OFFSET(SRST_DB_GPIO3, 13, 1),
RK3506_CRU_RESET_OFFSET(SRST_P_GPIO4, 13, 2),
RK3506_CRU_RESET_OFFSET(SRST_DB_GPIO4, 13, 3),
RK3506_CRU_RESET_OFFSET(SRST_H_CAN0, 13, 4),
RK3506_CRU_RESET_OFFSET(SRST_CAN0, 13, 5),
RK3506_CRU_RESET_OFFSET(SRST_H_CAN1, 13, 6),
RK3506_CRU_RESET_OFFSET(SRST_CAN1, 13, 7),
RK3506_CRU_RESET_OFFSET(SRST_H_PDM, 13, 8),
RK3506_CRU_RESET_OFFSET(SRST_M_PDM, 13, 9),
RK3506_CRU_RESET_OFFSET(SRST_PDM, 13, 10),
RK3506_CRU_RESET_OFFSET(SRST_SPDIFTX, 13, 11),
RK3506_CRU_RESET_OFFSET(SRST_H_SPDIFTX, 13, 12),
RK3506_CRU_RESET_OFFSET(SRST_H_SPDIFRX, 13, 13),
RK3506_CRU_RESET_OFFSET(SRST_SPDIFRX, 13, 14),
RK3506_CRU_RESET_OFFSET(SRST_M_SAI0, 13, 15),
/* CRU-->SOFTRST_CON14 */
RK3506_CRU_RESET_OFFSET(SRST_H_SAI0, 14, 0),
RK3506_CRU_RESET_OFFSET(SRST_M_SAI1, 14, 2),
RK3506_CRU_RESET_OFFSET(SRST_H_SAI1, 14, 3),
RK3506_CRU_RESET_OFFSET(SRST_H_ASRC0, 14, 5),
RK3506_CRU_RESET_OFFSET(SRST_ASRC0, 14, 6),
RK3506_CRU_RESET_OFFSET(SRST_H_ASRC1, 14, 7),
RK3506_CRU_RESET_OFFSET(SRST_ASRC1, 14, 8),
/* CRU-->SOFTRST_CON17 */
RK3506_CRU_RESET_OFFSET(SRST_H_HSPERI_BIU, 17, 4),
RK3506_CRU_RESET_OFFSET(SRST_H_SDMMC, 17, 7),
RK3506_CRU_RESET_OFFSET(SRST_H_FSPI, 17, 8),
RK3506_CRU_RESET_OFFSET(SRST_S_FSPI, 17, 9),
RK3506_CRU_RESET_OFFSET(SRST_P_SPI2, 17, 10),
RK3506_CRU_RESET_OFFSET(SRST_A_MAC0, 17, 11),
RK3506_CRU_RESET_OFFSET(SRST_A_MAC1, 17, 12),
/* CRU-->SOFTRST_CON18 */
RK3506_CRU_RESET_OFFSET(SRST_M_SAI2, 18, 2),
RK3506_CRU_RESET_OFFSET(SRST_H_SAI2, 18, 3),
RK3506_CRU_RESET_OFFSET(SRST_H_SAI3, 18, 6),
RK3506_CRU_RESET_OFFSET(SRST_M_SAI3, 18, 7),
RK3506_CRU_RESET_OFFSET(SRST_H_SAI4, 18, 10),
RK3506_CRU_RESET_OFFSET(SRST_M_SAI4, 18, 11),
RK3506_CRU_RESET_OFFSET(SRST_H_DSM, 18, 12),
RK3506_CRU_RESET_OFFSET(SRST_M_DSM, 18, 13),
RK3506_CRU_RESET_OFFSET(SRST_P_AUDIO_ADC, 18, 14),
RK3506_CRU_RESET_OFFSET(SRST_M_AUDIO_ADC, 18, 15),
/* CRU-->SOFTRST_CON19 */
RK3506_CRU_RESET_OFFSET(SRST_P_SARADC, 19, 0),
RK3506_CRU_RESET_OFFSET(SRST_SARADC, 19, 1),
RK3506_CRU_RESET_OFFSET(SRST_SARADC_PHY, 19, 2),
RK3506_CRU_RESET_OFFSET(SRST_P_OTPC_NS, 19, 3),
RK3506_CRU_RESET_OFFSET(SRST_SBPI_OTPC_NS, 19, 4),
RK3506_CRU_RESET_OFFSET(SRST_USER_OTPC_NS, 19, 5),
RK3506_CRU_RESET_OFFSET(SRST_P_UART5, 19, 6),
RK3506_CRU_RESET_OFFSET(SRST_UART5, 19, 7),
RK3506_CRU_RESET_OFFSET(SRST_P_GPIO234_IOC, 19, 8),
/* CRU-->SOFTRST_CON21 */
RK3506_CRU_RESET_OFFSET(SRST_A_VIO_BIU, 21, 3),
RK3506_CRU_RESET_OFFSET(SRST_H_VIO_BIU, 21, 4),
RK3506_CRU_RESET_OFFSET(SRST_H_RGA, 21, 6),
RK3506_CRU_RESET_OFFSET(SRST_A_RGA, 21, 7),
RK3506_CRU_RESET_OFFSET(SRST_CORE_RGA, 21, 8),
RK3506_CRU_RESET_OFFSET(SRST_A_VOP, 21, 9),
RK3506_CRU_RESET_OFFSET(SRST_H_VOP, 21, 10),
RK3506_CRU_RESET_OFFSET(SRST_VOP, 21, 11),
RK3506_CRU_RESET_OFFSET(SRST_P_DPHY, 21, 12),
RK3506_CRU_RESET_OFFSET(SRST_P_DSI_HOST, 21, 13),
RK3506_CRU_RESET_OFFSET(SRST_P_TSADC, 21, 14),
RK3506_CRU_RESET_OFFSET(SRST_TSADC, 21, 15),
/* CRU-->SOFTRST_CON22 */
RK3506_CRU_RESET_OFFSET(SRST_P_GPIO1_IOC, 22, 1),
};
int rk3506_reset_bind_lut(struct udevice *pdev, u32 reg_offset, u32 reg_number)
{
return rockchip_reset_bind_lut(pdev, rk3506_register_offset,
reg_offset, reg_number);
}