sdhci_brcmstb_init_2712() reads host->mmc->host_caps to decide whether
to force card-detect for a non-removable eMMC, or to route the CD signal
for a removable SD card. At the time this function runs from
sdhci_bcmstb_probe(), however, host->mmc->host_caps is still zero, that
field is only populated later by the MMC uclass, after the driver's
probe returns. mmc_of_parse() has already filled plat->cfg.host_caps
from the device tree by this point, so check that field instead.
Without the fix, every BCM2712 SDHCI instance takes the else branch and
writes SDIO_CFG_SD_PIN_SEL = SDIO_CFG_SD_PIN_SEL_CARD (0x02), including
the non-removable eMMC on boards such as CM5 on Home Assistant Yellow.
The SDIO_CFG block lies outside the SDHCI core's reset scope, so this
value persists across SDHCI_RESET_ALL into the next stage. On the
BCM2712, having SD_PIN_SEL set to "SD" when the Linux kernel performs
its first set_power(MMC_POWER_UP) write racily prevents the SDHCI
POWER_ON bit from latching (see [1] for the whole backstory) - the
voltage bits stick but POWER_ON drops - which wedges the first CMD0 the
full 10 s software timeout. On Home Assistant Yellow this manifested as
a ~20 s eMMC probe delay on roughly one in two Linux boots when U-Boot
was the previous stage. Booting directly from the Pi firmware (no U-Boot
in between) left SD_PIN_SEL at its default and did not exhibit the race.
Reading plat->cfg.host_caps lets init_2712 see the "non-removable"
property and take the correct branch, leaving SD_PIN_SEL untouched for
the eMMC.
[1] https://github.com/home-assistant/operating-system/pull/3700#issuecomment-4430229511
Fixes: 10127cdbab ("mmc: bcmstb: Add support for bcm2712 SD controller")
Signed-off-by: Jan Čermák <sairon@sairon.cz>
Reviewed-by: Ivan T. Ivanov <iivanov@suse.de>
The bcm2835 SDHCI driver sets up the MMC host configuration via
sdhci_setup_cfg(), but does not parse generic MMC device tree
properties.
As a result, properties such as bus-width are ignored. On Raspberry Pi
Compute Module 4, the eMMC node describes an 8-bit bus, but U-Boot
initialized the device as 4-bit.
Call mmc_of_parse() before sdhci_setup_cfg() so that generic MMC
properties are folded into the host configuration before the MMC core
selects the bus width.
Before this change, mmc info reported:
Bus Speed: 52000000
Bus Width: 4-bit
After this change, mmc info reports:
Bus Speed: 52000000
Bus Width: 8-bit
Tested on Raspberry Pi Compute Module 4 with onboard eMMC.
Signed-off-by: Liel Harel <liel.harel@gmail.com>
Reviewed-by: Peter Robinson <pbrobinson@gmail.com>
Tested-by: Peter Robinson <pbrobinson@gmail.com> # on the CM4 as well
The Cadence SD6HC (SDHCI spec v4.20+) controller uses a soft PHY whose
DLL delay characteristics vary with PVT (Process, Voltage, Temperature)
and board-level trace routing.
A static delay value programmed via device tree for SD High Speed mode is
insufficient because the optimal sampling point varies per board, SD card,
and operating conditions. Runtime calibration is required.
While the SD Physical Layer Specification does not mandate tuning for
SD HS mode (only for UHS-I SDR50/SDR104), the Cadence SD6HC PHY
requires runtime calibration of its receive data delay line to find a
valid sampling window under constrained clock conditions.
The tuning is triggered from the set_ios_post callback because at that
moment hardware has committed the new bus width, clock frequency, and speed
mode to the controller registers. This ensuring the tuning sequence runs
at the correct SD HS operating conditions.
The tuning is gated by a device tree property "cdns,sd-hs-tuning" so
that only boards requiring runtime calibration opt in. When enabled,
the driver performs a 40-tap DLL sweep using CMD19 to find the largest
consecutive passing window, then programs the midpoint into
PHY_DLL_SLAVE_CTRL_REG.
To enable on a board, add to the MMC node in device tree:
&mmc {
cdns,sd-hs-tuning;
};
Signed-off-by: Tze Yee Ng <tze.yee.ng@altera.com>
msm_sdc_clk_init() uses clock-frequency to get the clock rate for SDC
clocks. However, the DT files seem to use max-frequency for the same.
Since msm_sdc_clk_init() doesn't find clock-frequency in the DT, it sets
201500000 as the clock rate and this results in timeout errors on IPQ
platforms.
Additionally, clock-frequency is not DT bindings compliant. Hence, get
clock rate using DT bindings compliant max-frequency.
Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Allow cpu families as mcf5441x (m68k) to use the fsl_esdhc_imx driver
since the hardware ip module is the same.
Signed-off-by: Angelo Dureghello <angelo@kernel-space.org>
---
Changes in v2:
- moved before menuconfig changes
The U_BOOT_DRIVER macro creates a list of drivers used at link time, and
all entries here must be unique. This in turn means that all entries in
the code should also be unique in order to not lead to build failures
later with unexpected build combinations. Typically, the problem we have
here is when a driver is obviously based on another driver and didn't
update this particular field and so while the name field reflects
something unique the linker entry itself is not. In a few places this
provides a more suitable string name as well, however.
Reviewed-by: Marek Vasut <marek.vasut+usb@mailbox.org>
Reviewed-by: Svyatoslav Ryhel <clamor95@gmail.com> # Tegra
Reviewed-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Heiko Schocher <hs@nabladev.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
As exposed by "make randconfig", we have an issue with the dependencies
for REGMAP (and xPL variants). As this is a library function, it should
always be selected and not depended on by other functionality. This is
largely done correctly today, so just correct the few outliers.
Acked-by: Anshul Dalal <anshuld@ti.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Add support for eMMC specification version 5.1B by defining
MMC_VERSION_5_1B and including it in the version array.
eMMC 5.1B (JESD84-B51B) is a minor revision of the 5.1 specification
that primarily addresses MDT (Manufacturing Date) adjustment for dates
beyond 2025. This aligns with the Linux kernel commit 9996707822f82
("mmc: core: Adjust MDT beyond 2025").
Since the manufacturing date field is not currently used in U-Boot,
this change has no functional impact beyond proper device recognition.
It allows the driver to correctly identify and initialize eMMC devices
that report version 5.1B in their Extended CSD register.
Signed-off-by: Han Xu <han.xu@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
After years of developing the ADI ADSP platform, Timesys was purchased
by another company and is no longer contracted to maintain the platform.
Signed-off-by: Philip Molloy <philip.molloy@analog.com>
Reviewed-by: Greg Malysa <malysagreg@gmail.com>
When using a fixed 1.8V regulator for vqmmc (indicated by vs18_enable),
attempting to change the voltage produces spurious errors since the
regulator cannot be adjusted. The driver currently attempts the voltage
change, receives -ENOSYS from the regulator subsystem, and reports:
Setting to 1.8V error: -38
esdhc_set_voltage error -5
Fix this by checking vs18_enable early in esdhc_set_voltage() and
returning -ENOTSUPP for all voltage switch requests, not just 3.3V.
This prevents unnecessary regulator operations and eliminates the
error messages when the hardware is correctly configured with a fixed
1.8V supply.
Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
Peng Fan (OSS) <peng.fan@oss.nxp.com> says:
This patch set primarily removes unused DECLARE_GLOBAL_DATA_PTR
instances.
Many files declare DECLARE_GLOBAL_DATA_PTR and include
asm/global_data.h even though gd is never used. In these cases,
asm/global_data.h is effectively treated as a proxy header, which is
not a good practice.
Following the Include What You Use principle, files should include
only the headers they actually depend on, rather than relying on
global_data.h indirectly. This approach is also adopted in Linux kernel
[1].
The first few patches are prepartion to avoid building break after
remove the including of global_data.h.
A script is for filtering the files:
list=`find . -name "*.[ch]"`
for source in ${list}
do
result=`sed -n '/DECLARE_GLOBAL_DATA_PTR/p' ${source}`
if [ "${result}" == "DECLARE_GLOBAL_DATA_PTR;" ]; then
echo "Found in ${source}"
result=`sed -n '/\<gd\>/p' ${source}`
result2=`sed -n '/\<gd_/p' ${source}`
result3=`sed -n '/\<gd->/p' ${source}`
if [ "${result}" == "" ] && [ "${result2}" == "" ] && [ "${result3}" == "" ];then
echo "Cleanup ${source}"
sed -i '/DECLARE_GLOBAL_DATA_PTR/{N;/\n[[:space:]]*$/d;s/.*\n//;}' ${source}
sed -i '/DECLARE_GLOBAL_DATA_PTR/d' ${source}
sed -i '/global_data.h/d' ${source}
git add ${source}
fi
fi
done
[1] https://lpc.events/event/17/contributions/1620/attachments/1228/2520/Linux%20Kernel%20Header%20Optimization.pdf
CI: https://github.com/u-boot/u-boot/pull/865
Link: https://lore.kernel.org/r/20260209-cleanup-v2-0-73a3a84ddbdb@nxp.com
Remove DECLARE_GLOBAL_DATA_PTR from files where gd is not used, and
drop the unnecessary inclusion of asm/global_data.h.
Headers should be included directly by the files that need them,
rather than indirectly via global_data.h.
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> #STMicroelectronics boards and STM32MP1 ram test driver
Tested-by: Anshul Dalal <anshuld@ti.com> #TI boards
Acked-by: Yao Zi <me@ziyao.cc> #TH1520
Signed-off-by: Peng Fan <peng.fan@nxp.com>
TARGET namespace is for machines / boards / what-have-you that
building U-Boot for. Simply replace from TARGET to ARCH
make things more clear and proper for ALL SoCFPGA.
Signed-off-by: Brian Sune <briansune@gmail.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
# Conflicts:
# drivers/ddr/altera/Makefile
Fix the following typos in drivers/mmc/mmc.c:
- "neiter" -> "neither" in __mmc_switch() comment
- "witdh" -> "width" in bus_width() warning message
- "enver" -> "never" in mmc_select_mode_and_width() comment
Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@altera.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Implement DMA support in the MediaTek MMC driver to enhance data
transfer speed.
- Define DMA control and configuration registers
- Implement functions for starting, stopping, and completing DMA
transfers
- Modify data transfer logic to utilize DMA when enabled
- Ensure proper cache management during DMA operations
Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com>
Signed-off-by: ht.lin <ht.lin@mediatek.com>
Signed-off-by: Julien Masson <jmasson@baylibre.com>
Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
Signed-off-by: David Lechner <dlechner@baylibre.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Replace separate mask and shift definitions with GENMASK and FIELD_*
macros for better readability and maintainability.
All macros ending in _M have the suffix dropped. The value remains the
same but is now generated with GENMASK. All macros ending in _S are
removed and their uses replaced with FIELD_PREP and FIELD_GET macros.
Signed-off-by: David Lechner <dlechner@baylibre.com>
Reviewed-by: Macpaul Lin <macpaul.lin@mediatek.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
This patch renames the board directory from board/freescale to
board/nxp because NXP now provides Board Support Packages (BSPs) and
tools for the former Freescale i.MX and other i.MX products.
All relevant references have been updated accordingly. This change does
not affect functionality.
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
In sd_get_capabilities an ACMD is sent (SD_CMD_APP_SEND_SCR),
which requires sending APP_CMD (MMC_CMD_APP_CMD) before.
Currently, the ACMD is retried on error, however APP_CMD isn't.
In this case, when the ACMD fails and it is tried again,
the retry attempts will not be handled as ACMD, which is wrong.
The fix performs the retry attempts on the sequence of
APP_CMD and the ACMD together.
Signed-off-by: Yanir Levin <yanir.levin@tandemg.com>
Reviewed-by: Eran Moshe <emoshe@gsitechnology.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Use dev_read_u32_default() instead of dev_read_u32() to read the
"max-frequency" property from device tree. This preserves the driver-set
cfg->f_max value when the optional "max-frequency" property is not
present, ensuring the controller's default frequency is used as fallback
rather than being overwritten.
Suggested-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@altera.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
When 'max-clk' is not specified, the SDHCI core retrieves the base clock
from the SDHCI_CAPABILITIES register (bits [15:8]). However, this field
is unreliable on MSM SDHCI controllers, as noted by the Linux driver
using the SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN flag. In addition, the field
is only 8 bits wide and cannot represent base clocks above 255 MHz.
On platforms like Agatti/QCM2290, the firmware sets the SDHCI clock to
384 MHz, but the capabilities register reports 200 MHz. As a result,
the core calculates a divider of 4, producing a 96 MHz SDCLK instead of
the intended ~52 MHz. This overclocking can cause sporadic CRC errors
with certain eMMC.
To fix this, use the actual clock rate reported by the SDHCI core clock
instead of relying on the capabilities register for divider calculation.
Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Link: https://patch.msgid.link/20251210155454.1561611-1-loic.poulain@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
This reverts commit aebb523a23.
The change to use dev_read_u32_default() with a default value of 0
causes regression for host controller drivers that hardcode f_max
before calling mmc_of_parse().
When the "max-frequency" property is not specified in the device tree,
dev_read_u32_default() returns 0, which overwrites the previously
configured f_max value set by the driver. This effectively resets
the maximum frequency to 0, breaking MMC functionality for those
controllers.
Revert to the original dev_read_u32() behavior which only updates
cfg->f_max when the "max-frequency" property is explicitly present
in the device tree, preserving driver-configured values otherwise.
Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@altera.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Currently CRC16 is not selected when CRC checking is enabled and
if it wasn't enabled in the config otherwise the build will fail
because of references to crc16_ccitt() that doesn't exist.
Signed-off-by: Daniel Palmer <daniel@thingy.jp>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
mmc/sd specification requires a 1 ms delay (stable supply voltage)
after vdd was enabled and before issuing first command.
For most sdcard/soc combinations, the missing delay seems to be not a
problem because the processing time between enabling vdd and the first
command is often hundreds of microseconds or more. However, in our
specific case, some sdcards were not detected by u-boot:
* soc: NXP i.MX 93
* sdcards: SanDisk Ultra, 64GB micro SDXC 1,
MediaRange, 8GB, SDHC
* measured time between vdd and first command: approx. 784us
* symptom: both sdcards did not respond at all to first commands,
u-boot mmc subsystem ran into timeout and stops to
initialize the cards
Signed-off-by: Christoph Stoidner <c.stoidner@phytec.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
This pull request brings together a set of fixes and enhancements across
the SoCFPGA platform family, with a focus on MMC/SPL robustness, EFI
boot enablement, and Agilex5 SD/eMMC support.
CI: https://source.denx.de/u-boot/custodians/u-boot-socfpga/-/pipelines/28776
Highlights:
*
SPL / MMC:
o
Fix Kconfig handling for
SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
o
Correct raw sector calculations and respect explicit sector values
when loading U-Boot from MMC in SPL
o
Adjust raw MMC loading logic for SoCFPGA platforms
*
EFI boot:
o
Permit EFI booting on SoCFPGA platforms
o
Disable mkeficapsule tool build for Arria 10 where unsupported
*
Agilex5:
o
Upgrade SDHCI controller from SD4HC to SD6HC
o
Enable MMC and Cadence SDHCI support in defconfig
o
Add dedicated eMMC device tree and defconfig for Agilex5 SoCDK
o
Revert incorrect GPIO configuration for SDIO_SEL
o
Refine U-Boot DT handling for SD and eMMC boot variants
*
SPI:
o
Allow disabling the DesignWare SPI driver in SPL via Kconfig
*
Board / configuration fixes:
o
Enable random MAC address generation for Cyclone V
o
Fix DE0-Nano-SoC boot configuration
o
Remove obsolete or conflicting options from multiple legacy
SoCFPGA defconfigs
Upgrade the SDHCI Cadence controller from SD4HC to SD6HC for Agilex5
platform to support the newer controller version with enhanced features.
Key changes:
- Remove combophy0 node and associated references as SD6HC doesn't require
separate PHY configuration node
- Upgrade MMC controller compatible from "cdns,sd4hc" to "cdns,sd6hc"
- Add Agilex5-specific compatible string "altr,agilex5-sd6hc" for
platform-specific optimizations
Hardware configuration updates:
- Add voltage regulator support:
* sd_emmc_power: Fixed 3.3V regulator for card power supply
* sd_io_1v8_reg: GPIO-controlled regulator for 1.8V/3.3V I/O switching
- Configure proper reset control with named resets including combophy
reset
- Add GPIO control via portb pin 3 for voltage switching
SD card operation:
- Configure for SD card specific operation (no-mmc, cap-sd-highspeed)
- Set maximum frequency to 200MHz
- Configure timing parameters for SD modes:
* Default Speed (DS) and UHS-I SDR12 mode timing:
* High Speed and UHS-I SDR25 mode timing:
- Add PHY timing delays for optimal signal integrity
Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
- Add support for configuring the PHY DLL master control register for all
SD/eMMC timing modes (DS, HS, SDR, DDR, HS200, HS400) by extending the
PHY configuration arrays and writing the value during PHY adjustment.
- Fix tuning reliability by toggling the DLL reset before and after
updating the PHY_DLL_SLAVE_CTRL_REG_ADDR register.
Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@altera.com>
Reviewed-by: Balsundar Ponnusamy <balsundar.ponnusamy@altera.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
1. Replace underscores with hyphens in device tree property names to
follow the standard DT naming convention. This affects all
"lpbk_ctrl" properties which are now correctly named "lpbk-ctrl".
Changes:
- cdns,phy-gate-lpbk_ctrl-delay-* → cdns,phy-gate-lpbk-ctrl-delay-*
- cdns,ctrl-hrs10-lpbk_ctrl-delay-* → cdns,ctrl-hrs10-lpbk-ctrl-delay-*
2. Fix typo: semmc → emmc in eMMC SDR PHY property name
Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@altera.com>
Reviewed-by: Balsundar Ponnusamy <balsundar.ponnusamy@altera.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Remove interface type restrictions in sdhci_cdns_execute_tuning() to
enable software tuning for both SD and eMMC devices. The previous
assumption that SD timing should be handled by SDHCI core is incorrect
based on the actual function assignment logic.
The execute_tuning function is assigned based on MMC_SUPPORTS_TUNING
config, which is enabled by both MMC_UHS_SUPPORT and MMC_HS200_SUPPORT.
Changes:
Remove IS_MMC() check that restricted tuning to eMMC only
Remove opcode validation limited to MMC_CMD_SEND_TUNING_BLOCK_HS200
Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@altera.com>
Reviewed-by: Balsundar Ponnusamy <balsundar.ponnusamy@altera.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Replace device tree compatible string checks with hardware version field
detection to determine SDHCI controller capabilities. This approach is
more robust and aligns with standard SDHCI specification practices.
Controllers with SDHCI version 4.2 and above will automatically use the
enhanced PHY adjustment, and tuning v6-specific procedures.
Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@altera.com>
Reviewed-by: Balsundar Ponnusamy <balsundar.ponnusamy@altera.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Replace the legacy clock frequency-based timing mode selection with
proper MMC timing mode constants.
Changes to sdhci-cadence.c:
- Add sdhci_cdns_get_hrs06_mode() helper function for mode selection
- Replace clock frequency logic with mmc->selected_mode switch statement
- Use proper MMC timing constants (MMC_HS, UHS_SDR104, etc.)
- Add SD card specific handling with standard SDHCI control register setup
Changes to sdhci-cadence6.c:
- Add SD high speed PHY and control configuration arrays
- Update sdhci_cdns6_phy_adj() to use timing modes instead of HRS06 modes
- Support both SD and eMMC timing modes with appropriate PHY settings
Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@altera.com>
Reviewed-by: Balsundar Ponnusamy <balsundar.ponnusamy@altera.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
When f_max parameter is 0 in sdhci_setup_cfg(), the function defaults
to using the maximum frequency from host controller capabilities register
instead of the max-frequency property parsed from device tree.
The max-frequency property from device tree is parsed by mmc_of_parse()
and stored in plat->cfg.f_max, but sdhci_setup_cfg() was being called
with f_max=0, causing it to ignore the device tree value and use the
host capabilities register value instead.
Fix this by passing plat->cfg.f_max to sdhci_setup_cfg() to ensure
the device tree specified maximum frequency is respected over the
hardware default.
Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@altera.com>
Reviewed-by: Balsundar Ponnusamy <balsundar.ponnusamy@altera.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
When the max-frequency property is not specified in the device tree,
the function now explicitly defaults to 0 instead of leaving cfg->f_max
uninitialized. This allows sdhci_setup_cfg() to properly detect the
absence of a device tree specified frequency and fall back to using
the host controller's maximum base clock frequency from the capabilities
register.
Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@altera.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Add reset control functionality to the SDHCI Cadence driver to properly
handle hardware reset sequences during probe. This ensures the controller
is in a known state before initialization.
Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@altera.com>
Reviewed-by: Balsundar Ponnusamy <balsundar.ponnusamy@altera.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Andrew Goodbody <andrew.goodbody@linaro.org> says:
The function clk_get_rate() returns a ulong with 0 meaning an invalid
clock rate and also negative error codes being returned for other
errors. But being an unsigned return value this cannot simply be tested
for with a < 0 test. Instead use the IS_ERR_VALUE() macro to check for
negative errors appearing as very large positive values. Fix those
places that test for <= 0. Also fix some places checking the return of
clk_register() that incorrectly used ERR_PTR().
Link: https://lore.kernel.org/r/20251021-clk_funcs-v1-0-acf51a40eea7@linaro.org
Testing an unisgned member of a struct to be <= 0 will only detect the
case when it is 0. So correct this error test to a working version that
will behave as expected.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
clk_get_rate() returns a ulong and that return value is assigned to a
member of a struct that is an unsigned int. So testing this value to <=
0 will only detect a return of 0. Also the code in the if block assumes
ret holds the return value when it does not. So update the test to one
that will work as intended and update the if block to actually refer to
the return value.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Restore legacy implementation of retrieving clkmgr base address from
mach-socfpga/misc.c driver for our legacy devices.
Excluding Agilex7/7M from this implementation as these devices' clock
driver is already following clock driver model and is supporting
enable/disable APIs.
The legacy devices' clock driver will have to be refactored to support
driver model which enables us to support enable/disable APIs for these
devices.
Fixes: ab27182cac ("mmc: socfpga_dw_mmc: Enable/disable SDMMC clock via API")
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
