Commit Graph

28349 Commits

Author SHA1 Message Date
Yao Zi
e6646b35f4 Revert "riscv: Add a Zalrsc-only alternative for synchronization in start.S"
This reverts commit a681cfecb4.

It has been reported that the commit causes boot regression for SPL on
StarFive VisionFive 2 or compatible boards. Inspecting the code, I did
spot one logic error for deciding whether Zaamo or Zalrsc is used, and
it's still unclear what exactly causes the regression, let's revert it
for now.

Reported-by: E Shattow <e@freeshell.de>
Link: https://lore.kernel.org/u-boot/1871663e-b918-4351-9e9e-97f9a4c73733@freeshell.de/
Signed-off-by: Yao Zi <ziyao@disroot.org>
Acked-by: E Shattow <e@freeshell.de>
Acked-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-10-16 16:36:37 +08:00
Mikhail Kshevetskiy
ce175fa9f0 arm/airoha: partly revert support of multiple RAM size for an7581
Partly revert commit 726404a66c ("airoha: rework RAM size handling
to support multiple RAM size").

The general idea is good, but the call of

  get_ram_size((void *)gd->ram_base, SZ_8G);

produces the following result on my an7581 board with only 1Gb of
memory:

  "Synchronous Abort" handler, esr 0x96000004
  elr: 0000000081e201c8 lr : 0000000081e20160 (reloc)
  elr: 00000000bff501c8 lr : 00000000bff50160
  x0 : 0000000180000000 x1 : 0000000100000000
  x2 : 000000000000002e x3 : 0000000000000002
  x4 : 000000001fbf0000 x5 : 0060000000000401
  x6 : 0000000000000000 x7 : 00000000bffdb268
  x8 : 0000000000000060 x9 : 00000000bffdb2c8
  x10: 0000000000000000 x11: 0000000000000060
  x12: 00000000bffdb268 x13: 00000000841c56d0
  x14: 00000000841c56d0 x15: 0000000000000000
  x16: 00000000841506e4 x17: dd7fe29aec3b07e8
  x18: 00000000bf710e00 x19: 0000000080000000
  x20: 0000000000000000 x21: 0000000020000000
  x22: 0000000200000000 x23: 0000000000000001
  x24: 0000000040000000 x25: 00000000bf708e78
  x26: 00000000bf7bdca0 x27: 0000000000000000
  x28: 0000000000000000 x29: 00000000bf708e20

  Code: 910943ff d65f03c0 d37df2a1 8b150e60 (f8616a62)
  Resetting CPU ...

So just not call get_ram_size() and use the value from dtb.

Fixes: 726404a66c ("airoha: rework RAM size handling to support multiple RAM size")
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
2025-10-15 15:08:27 -06:00
Mikhail Kshevetskiy
40f57b571c arm/airoha: an7581 ignores CFG_MAX_MEM_MAPPED value
This partly fix commit 726404a66c ("airoha: rework RAM size handling
to support multiple RAM size")

The function get_effective_memsize() do not see non-global defines
of CFG_MAX_MEM_MAPPED, so the effective memory size will not be changed.

Fix the issue by putting definition of CFG_MAX_MEM_MAPPED to the proper
place.

Fixes: 726404a66c ("airoha: rework RAM size handling to support multiple RAM size")
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
2025-10-15 15:08:27 -06:00
Ernest Van Hoecke
77d11d2f7a arm: dts: k3-am62p-verdin: migrate to OF_UPSTREAM
Enable CONFIG_OF_UPSTREAM to receive automatic
device tree updates for the Verdin AM62P.

Remove the now-obsolete device tree files:
- k3-am62p-verdin.dtsi
- k3-am62p-verdin-dev.dtsi
- k3-am62p-verdin-wifi.dtsi
- k3-am62p5-verdin-wifi-dev.dts

Signed-off-by: Ernest Van Hoecke <ernest.vanhoecke@toradex.com>
2025-10-15 14:17:09 -06:00
Tom Rini
b1cc9a53d7 Merge tag 'xilinx-for-v2026.01-rc1-v2' of https://source.denx.de/u-boot/custodians/u-boot-microblaze
AMD/Xilinx/FPGA changes for v2026.01-rc1 v2

zynqmp:
- DT updates
- Enable new commands

mbv:
- Simplify defconfigs

clk:
- Separate legacy handler and use SMC handler

misc:
- Tighten TTC Kconfig dependency

net:
- Add 10GBE support to Gem

pwm:
- cadence-ttc: Fix array sizes

fwu:
- Add platform hook support

spi:
- Remove undocumented cdns,is-dma property

video:
- Fix DPSUB RGB handling
2025-10-14 09:48:02 -06:00
Tom Rini
78406dda99 Merge tag 'u-boot-marvell-20251014' of https://source.denx.de/u-boot/custodians/u-boot-marvell
CI: https://dev.azure.com/sr0718/u-boot/_build/results?buildId=398&view=results

- sata_mv / octeontx_hsmmc: Smatch fixes / patches (Andrew)
- dts: pxa1908: convert to OF_UPSTREAM (Duje)
- phy: marvell: Tighten MVEBU_COMPHY_SUPPORT dependencies (Tom)
- pci: mvebu: Unable to assign mbus windows for 2nd pcie controller (Tony)
2025-10-14 08:24:35 -06:00
Michal Simek
a040578d82 spi: cadence-qspi: Remove cdns,is-dma property handling
Remove cdns,is-dma DT property handling. Property is not the part of DT
binding and it is also hardcoded to value 1 in all DTs that's why remove it
because none is also testing value 0.
If there is any use case when this configuration should be supported this
patch can be reverted.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/6205c6585589b423692b6ed063506b4c51c04c77.1760006086.git.michal.simek@amd.com
2025-10-14 16:00:45 +02:00
Tom Rini
16b0482a74 sandbox: Make SANDBOX_xPL depend on !COMPILE_TEST
Given how these options are used in the code, it doesn't make sense to
enable them for COMPILE_TEST. Make them depend on !COMPILE_TEST.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-10-13 14:54:32 -06:00
Duje Mihanović
80f3568995 ARM: dts: pxa1908: convert to OF_UPSTREAM
Convert the PXA1908 platform and its coreprimevelte board to OF_UPSTREAM
and enable the few drivers found in the upstream DTS.

Signed-off-by: Duje Mihanović <duje@dujemihanovic.xyz>
2025-10-13 16:13:21 +02:00
Tom Rini
16bbc225fe iotrace: Finish migrating this to Kconfig
When I migrated this to Kconfig in commit 68e54040cc ("sandbox: Move
CONFIG_IO_TRACE to Kconfig") I didn't look hard enough for other
details. As explained in the README, this is valid for ARM too. So start
by making this be a prompted question and CMD_IOTRACE depend on IO_TRACE
being enabled.  Next, migrate the information out of README and in to
the appropriate help text for existing options in Kconfig. Finally, make
this option be default y on SANDBOX but not selected as it's valid to
build without it.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-10-10 14:25:24 -06:00
Tom Rini
b30155c08e sandbox: Rework readX/writeX macros to be more like ARM
The way that the current readX/writeX macros are implemented on sandbox
means that when IO_TRACE is not enabled some code will throw up
incorrect warnings due to how sandbox_{read,write} is implemented. We
instead need to do the "uX __v; __v = sandbox..(..v); __v;" trick that
ARM does.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-10-10 13:58:49 -06:00
Tom Rini
9de2fc9878 arm: v7m: Allow SYS_ARCH_TIMER here
We have had an implementation of the generic timer found in many v7m
chips since 2017, but as part of the Kconfig migration forgot to allow
it as it wasn't being used at the time. Allow it to be built.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-10-10 13:29:34 -06:00
Tom Rini
a1fd7a9589 Merge tag 'u-boot-imx-master-20251009' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/27872

- Several improvements for kontron-sl-mx8mm.
- Add rauc to bootmeths to phycore_imx8mp.
- Fix imx93_frdm USB vendor ID.
2025-10-09 13:47:28 -06:00
Ernest Van Hoecke
15bed125d7 arm: dts: imx8mp-toradex-smarc: migrate to OF_UPSTREAM
Enable CONFIG_OF_UPSTREAM to receive automatic device tree updates for
the Toradex SMARC iMX8MP.

Remove the now obsolete device tree files:
- imx8mp-toradex-smarc-dev.dts
- imx8mp-toradex-smarc.dtsi

Signed-off-by: Ernest Van Hoecke <ernest.vanhoecke@toradex.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2025-10-09 14:57:09 -03:00
Michal Simek
145645a9f2 arm64: zynqmp: Fix DTOVL warning about graphs in kv/kr260
DTC is generating warnings about missing port like:
DTOVL   arch/arm/dts/zynqmp-smk-k24-revA-sck-kv-g-revB.dtb
 arch/arm/dts/zynqmp-sck-kv-g-revA.dtbo: Warning (graph_port):
 /fragment@5/__overlay__: graph port node name should be 'port'
...

That's why change description and add it directly to dpsub mode to contain
full description with also port.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/576630cc9696e21bef15bd1f0ca35e396adc4eca.1758529693.git.michal.simek@amd.com
2025-10-09 09:07:04 +02:00
Michal Simek
9b68682d1c arm64: zynqmp: Add pmw_fan label to k26
Some boards/designs with System Controller which are using SOMs need to
change PWM signal polarity that's why create label to be able to reference
them.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/7a392d79685e5b122528e8fe7617475c4f6fabab.1756803198.git.michal.simek@amd.com
2025-10-09 09:07:04 +02:00
Michal Simek
8651f2a50a arm64: zynqmp: Enable DP for kr260, kv260, zcu100, zcu102, zcu104, zcu111
Upstream DP DT binding enforcing dp-connector and port description to
operate properly.

Co-developed-by: Rohit Visavalia <rohit.visavalia@amd.com>
Signed-off-by: Rohit Visavalia <rohit.visavalia@amd.com>
Co-developed-by: Nithish Kumar Naroju <nithishkumar.naroju@amd.com>
Signed-off-by: Nithish Kumar Naroju <nithishkumar.naroju@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/15e863adca11431f68d37d732cd8a453e508ad91.1756803198.git.michal.simek@amd.com
2025-10-09 09:07:04 +02:00
Michal Simek
8e27bd3a7a arm64: zynqmp: Introduce DP port labels
Describe every port by unique label for easier wiring with DT overlays.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/933151f48f236f64ec9e91b9da4f174460a269e6.1756803198.git.michal.simek@amd.com
2025-10-09 09:07:04 +02:00
Michal Simek
b852fece84 arm64: zynqmp: Update compatible string for tps546X24
ti,tps546d24 is already described in DT binding and ti,tps546b24 should be
described in the same way that's why update compatible string to match
them.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/a247b2b57ebe52e9d23525bf4f96c4872288025d.1756803198.git.michal.simek@amd.com
2025-10-09 09:07:04 +02:00
Michal Simek
4bd2183984 arm64: zynqmp: Enable PSCI 1.0
TF-A is using PSCI 1.0 version for quite a long time but it was never
reflected in DT.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/a3372ee9cce7fade7c9f707727e33d1cf569b607.1756803198.git.michal.simek@amd.com
2025-10-09 09:07:04 +02:00
Michal Simek
5fc47ae48e arm64: zynqmp: Fix incomplete comment in zynqmp-sc-vn-p-b2197-00-revA.dtso
Fix comment inside comment by closing the first one properly.

Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202501111756.IcKlG6rs-lkp@intel.com/
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/779be02a8f0cfa1deab86dbfe8e575ab152d43f3.1756803198.git.michal.simek@amd.com
2025-10-09 09:07:04 +02:00
Radhey Shyam Pandey
09311c8a38 arm64: zynqmp: Revert usb node drive strength and slew rate for zcu106
On a few zcu106 boards USB devices (Dell MS116 USB Optical Mouse, Dell USB
Entry Keyboard) are not enumerated on linux boot due to commit
'b8745e7eb488 ("arm64: zynqmp: Fix usb node drive strength and slew
rate")'.

To fix it as a workaround revert to working version and then investigate
at board level why drive strength from 12mA to 4mA and slew from fast to
slow is not working.

Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/14d3408cf547ac188c07c10abb0ddfaac9d915c4.1756803198.git.michal.simek@amd.com
2025-10-09 09:07:04 +02:00
Padmarao Begari
5b13a280b4 arm64: xilinx: Add i2c mux idle disconnect property
Add i2c-mux-idle-disconnect property to an i2c mux node.
It is used to configure an i2c mux to disconnect all
its channels when idle.

Signed-off-by: Padmarao Begari <padmarao.begari@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/d75f31d72cadf6d98c0faa51239bf2b239797d2d.1756803198.git.michal.simek@amd.com
2025-10-09 09:07:04 +02:00
Michal Simek
4640051cdf arm64: zynqmp: Remove "ti,tps53679" property
Linux driver has been updated that only ti,tps53681 dt property is needed
and there is no need to provide second compatible string.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/609ee957931242ab6cde93e75eb3bd8afa769f12.1756803198.git.michal.simek@amd.com
2025-10-09 09:07:04 +02:00
Michal Simek
e2aaac3f6b arm64: zynqmp: Remove RTC calibration from sm-k26
Default calibration is already in zynqmp.dtsi that's why make no sense to
describe it again.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/6331bf84d7afaf8031d9cbb64354fcd8ca343d45.1756803198.git.michal.simek@amd.com
2025-10-09 09:07:04 +02:00
Michal Simek
09c862aca4 arm64: zynqmp: Remove undocumented arasan, has-mdma property
Property was used long ago by internal Xilinx Linux driver but it is not
documented in DT binding that's why remove it.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/546788df1a64c41e332463411ad99b1f3b40bc96.1756803198.git.michal.simek@amd.com
2025-10-09 09:07:04 +02:00
Quanyang Wang
733f2de332 arm64: zynqmp: Disable coresight by default
When secure-boot mode of bootloader is enabled, the registers of
coresight are not permitted to access that's why disable it by default.

Signed-off-by: Quanyang Wang <quanyang.wang@windriver.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/1ea8e5bdb9bfdcc1fc6670bf4b4e13c40fbdc00c.1756803198.git.michal.simek@amd.com
2025-10-09 09:07:04 +02:00
Naman Trivedi
4146a31dce drivers: firmware: update xilinx_pm_request to support max payload
Currently xilinx_pm_request API supports four u32 payloads. However the
legacy SMC format supports five u32 request payloads and extended SMC
format supports six u32 request payloads. Add support for the same in
xilinx_pm_request API. Also add two dummy arguments to all the callers
of xilinx_pm_request.

The TF-A always fills seven u32 return payload so add support
for the same in xilinx_pm_request API.

Signed-off-by: Naman Trivedi <naman.trivedimanojbhai@amd.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Acked-by: Senthil Nathan Thangaraj <senthilnathan.thangaraj@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/5ae6b560741f3ca8b89059c4ebb87acf75b4718e.1756388537.git.michal.simek@amd.com
2025-10-09 09:07:03 +02:00
Tom Rini
e5fea3f3b9 sandbox: Add more dummy cache functions
In order for cmd/cache.c to link we need to add dummy icache functions
to mirror the dummy dcache functions as well as another dcache flush
function.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-10-08 16:12:46 -06:00
Paresh Bhagat
14dfa6b861 Add initial support for AM62D2-EVM
Add initial support for AM62D2-EVM, Kconfig entries for binman, SPL,
base DTS files for u-boot and SPL, HS-SE and HS-FS support and initial
configs with SD-MMC, UART, eMMC and OSPI boot providing a baseline for
further enablement.

Also add labels and targets to AM62A-SK binman to enable AM62D2-EVM
builds to reuse existing binman infrastructure.

Technical Reference Manual - https://www.ti.com/lit/pdf/sprujd4
Schematics Link - https://www.ti.com/lit/zip/sprcal5

Signed-off-by: Paresh Bhagat <p-bhagat@ti.com>
2025-10-08 16:10:11 -06:00
Marek Vasut
0ee639ff5a thermal: Convert .get_temp() return value to millicelsius
Linux kernel .get_temp() callback reports values in millicelsius,
U-Boot currently reports them in celsius. Align the two and report
in millicelsius. Update drivers accordingly. Update callsites that
use thermal_get_temp() as well.

The 'temperature' command now reports temperature in millicelsius
as well, with additional accuracy. This changes command line ABI
slightly.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: David Zang <davidzangcs@gmail.com>
[trini: Update test/cmd/temperature.c]
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-10-08 13:54:59 -06:00
Bryan Brattlof
8a9f2c19d4 arm: dts: k3-am654: add vin-supply regulators for DDR
As of commit f98d812e53 ("power: regulator: Add vin-supply for GPIO
and Fixed regulators") we must ensure the parent nodes of a regulator
are present in DT if they are described in the vin-supply property

For the am65x reference board the DRAM chips are fed by the 3v3 rail
which is fed by the main 12v rail. Add the bootph properties to these DT
nodes to prevent them from being pruned during the SPL build so we can
enable power to the DRAM chips

Signed-off-by: Bryan Brattlof <bb@ti.com>
Tested-by: Nishanth Menon <nm@ti.com>
2025-10-08 13:34:14 -06:00
Christian Marangi
726404a66c airoha: rework RAM size handling to support multiple RAM size
There are multiple version of the same reference board with different
RAM size and it's not enough to base the RAM size entirely from DT. To
better support it use the get_ram_size way to scan for the actual RAM
size of Airoha SoC and increase the size of the memory map.

Also rework the memory map to account for 2 memory map. The first one of
2GB for 32bit DMA and for safe usage of U-Boot. The second one for the
rest of the RAM since up to 8GB are supported.

Reviewed-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2025-10-07 17:11:49 -06:00
Frieder Schrempf
7f9362ef7f imx: kontron-sl-mx8mm: Convert to OF_UPSTREAM
Switch to OF_UPSTREAM to make use of the upstream devicetree.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2025-10-07 08:58:28 -03:00
Frieder Schrempf
de704144ff imx: kontron-sl-mx8mm: Enable USB hub on BL i.MX8MM OSM-S board
Probe the USB hub on the BL i.MX8MM OSM-S board.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2025-10-07 08:58:28 -03:00
Frieder Schrempf
c1cd4f3806 imx: kontron-sl-mx8mm: Enable SDP support for loading via USB
Enable everything that is required to load via USB. The SPL needs
SDP support so it can load the U-Boot proper image via USB after
it has been loaded via serial loader mode of the i.MX.

This way we can use the uuu tool for loading SPL and U-Boot
proper like this:

  uuu -brun flash.bin

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2025-10-07 08:58:28 -03:00
Tom Rini
0eaa4b3373 Merge branch 'next'
Merge the outstanding changes from the 'next' branch to master.
2025-10-06 13:20:24 -06:00
Tom Rini
601cebc29d cmd: spl: Remove ATAG support from this command
While we continue to have some systems which support extremely legacy
OS booting methods, we do not have use cases for supporting this in
Falcon mode anymore. Remove this support and references from the
documentation.

Co-developed-by: Anshul Dalal <anshuld@ti.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-10-03 16:55:44 -06:00
Anshul Dalal
8fd3768ca1 arm: armv8: remove redundant definition of mmu_status
mmu_status is used in io memcpy functions to prevent accesses to non
8-byte aligned addresses when the mmu is disabled. Though there is a
redundant definition enabled when icaches is turned off by setting
SYS_ICACHE_OFF.

This patch removes the redundant definition, allowing mmu_status to
properly report the status regardless of config settings. This shouldn't
be a problem since access to non 8-byte aligned data can be done
irrespective of icache state.

Fixes: 268f6ac1f9 ("arm64: Update memcpy_{from, to}io() helpers")

Signed-off-by: Anshul Dalal <anshuld@ti.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-10-03 15:13:58 -06:00
Tom Rini
aff68c8514 Merge tag 'u-boot-socfpga-next-20250930' of https://source.denx.de/u-boot/custodians/u-boot-socfpga into next
SoCFPGA updates for v2025.10:

CI: https://source.denx.de/u-boot/custodians/u-boot-socfpga/-/pipelines/27762

This pull request brings a set of updates across SoCFPGA platforms
covering Agilex5, Agilex7, N5X, and Stratix10. The changes include:

* Agilex5 enhancements:
  - USB3.1 enablement and DWC3 host driver support
  - System Manager register configuration for USB3
  - Watchdog timeout increase and SDMMC clock API integration
  - dcache handling improvements in SMC mailbox path
  - Enable SPL_SYS_DCACHE_OFF in defconfig

* Clock driver improvements:
  - Introduce dt-bindings header for Agilex clocks
  - Add enable/disable API and EMAC clock selection fixes
  - Replace manual shifts with FIELD_GET usage

* DDR updates:
  - IOSSM mailbox compatibility check
  - Correct DDR calibration status handling

* Device tree changes:
  - Agilex5: disable cache allocation for reads
  - Stratix10: add NAND IP node
  - Enable driver model watchdog
  - Enable USB3.1 node for Agilex5

* Config cleanups:
  - Simplify Agilex7 VAB defconfig
  - Remove obsolete SYS_BOOTM_LEN from N5X VAB config
  - Enable CRC32 support for SoCFPGA
  - Increase USB hub debounce timeout

Overall this set improves reliability of DDR and cache flows,
adds missing USB and MMC features for Agilex5, and refines clock
and configuration handling across platforms.

This patch set has been tested on Agilex 5 devkit, and Agilex devkit.
2025-09-30 16:11:23 -06:00
Patrick Delaunay
8a2e75e6a1 stm32mp2: update register used by BL31 for boot parameter
Use the ARM64 kernel booting register settings, defined in Linux
documentation Documentation/arch/arm64/booting.rst:

 x0 = physical address of device tree blob (dtb) in system RAM.

so kernel can replace U-Boot in FIP without modification of BL31.

Use x0 for future TF-A version and keep x2 as fallback to be compatible
with previous version of TF-A BL31.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2025-09-30 17:37:10 +02:00
Naresh Kumar Ravulapalli
da57acb4c3 arch: arm: socfpga: Configure USB3 System Manager registers
For successful reset staggering pulse operation, reset pulse
override bit is set. Port overcurrent bit 1, which in reality
reflects PIPE power present signal is set to avoid giving
false information of Vbus status to HPS controller.

Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-09-30 14:45:37 +08:00
Naresh Kumar Ravulapalli
e3a11a240a arch: arm: dts: Enable USB3.1 for Agilex5
USB 3.1 node is enabled for Agilex5.

Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-09-30 14:29:56 +08:00
Boon Khai Ng
38d49808d4 cache: Check dcache availability before calling cache functions
When the data cache (dcache) is disabled, calling related
status functions can lead to compilation errors due to
undefined references.

Adding a !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) check before
invoking dcache_status() (used in common/memsize.c:get_ram_size())
and mmu_status() (from arch/arm/include/asm/io.h).

Without this check, builds with dcache disabled will fail to compile.

Signed-off-by: Boon Khai Ng <boon.khai.ng@altera.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2025-09-30 14:29:55 +08:00
Boon Khai Ng
8d28f121d3 arch: arm: mach-socfpga: smc: Add dcache flushing and invalidation in smc_send_mailbox()
Adding the dcache flushing and invalidation in the smc_send_mailbox()
At the same time replace the use of u64 with uintptr_t to ensure
compatibility across different architectures and correct the
pointer arithmetic for buffer end address calculation.

Signed-off-by: Mahesh Rao <mahesh.rao@altera.com>
Signed-off-by: Boon Khai Ng <boon.khai.ng@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-09-30 14:29:54 +08:00
Alif Zakuan Yuslaimi
f4db066455 arm: socfpga: mailbox: Remove CONFIG_CADENCE_QSPI guard from QSPI mailbox API declarations
The QSPI mailbox API function declarations (mbox_qspi_close and
mbox_qspi_open) in mailbox_s10.h were guarded by CONFIG_CADENCE_QSPI
preprocessor conditional. This prevented their prototypes from being
visible to code that may use the stub implementations when
CONFIG_CADENCE_QSPI is disabled.

Remove the CONFIG_CADENCE_QSPI preprocessor conditional so these functions
are always declared, regardless of the configuration. This avoids potential
build or linkage errors when stubs are used.

Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-09-30 14:29:54 +08:00
Alif Zakuan Yuslaimi
fb7aa75561 arm: socfpga: Define Use FPGA switch handoff section size for Agilex5
Agilex5 FPGA switch section in the handoff data is larger by 32 bytes
than the default value as these extra sections contains I3C0 and I3C1
register offsets and values with 4 bytes each.

This requires 4 more times of reading the FPGA switch section of the
handoff data to fully populate the handoff data table in the memory
during runtime.

Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-09-30 14:29:53 +08:00
Naresh Kumar Ravulapalli
26ffc37787 arm: dts: socfpga: Enable driver model for watchdog timer
All SoCFPGA platforms are switching to CONFIG_WDT (driver
model for watchdog timer drivers) from CONFIG_HW_WATCHDOG. Status
of watchdog is enabled to assist with this switching.

Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-09-30 14:29:52 +08:00
Naresh Kumar Ravulapalli
27e13c9c8d arch: arm: socfpga: Remove speed and mode from flash probe
Change is to allow the user to choose speed and mode values
from dts or the default ones.

Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-09-30 14:29:51 +08:00
Naresh Kumar Ravulapalli
f6dbe41638 arch: arm: dts: stratix10: Add NAND IP to base dtsi
Add NAND node to the base stratix10 dtsi file.

Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-09-30 14:06:57 +08:00