Commit Graph

104610 Commits

Author SHA1 Message Date
Simon Glass
a39fdf2aad binman: test: Move CBFS test files to test/cbfs/
Move about a dozen test files for Coreboot File System entries into a
cbfs/ subdirectory. Drop the numeric prefixes and the redundant cbfs_
filename prefix, and update all references.

Signed-off-by: Simon Glass <simon.glass@canonical.com>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
2026-03-18 06:14:16 -06:00
Simon Glass
dd487d0d55 binman: test: Move security test files to test/security/
Move about 20 test files for signing, encryption, hash, pre-load,
x509, and Xilinx bootgen entries into a security/ subdirectory. Drop
the numeric prefixes and update all references.

Signed-off-by: Simon Glass <simon.glass@canonical.com>
2026-03-18 06:14:16 -06:00
Simon Glass
62d2388401 binman: test: Move blob test files to test/blob/
Move about a dozen test files for blob, blob-ext, blob-ext-list,
fake-blob, and blob-symbol entries into a blob/ subdirectory. Drop
the numeric prefixes and the redundant blob_ filename prefix, and
update all references.

Signed-off-by: Simon Glass <simon.glass@canonical.com>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
2026-03-18 06:14:16 -06:00
Simon Glass
4f283a26e2 binman: test: Move FDT/fdtmap test files to test/fdt/
Move about 30 test files for FDT update, fdtmap, DTB compression,
alternates, and bootph into an fdt/ subdirectory. Drop the numeric
prefixes and the redundant fdt_ filename prefix, and update all
references.

Remove the unused no_alt_format.dts which has no references in any
test.

Signed-off-by: Simon Glass <simon.glass@canonical.com>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
2026-03-18 06:14:16 -06:00
Simon Glass
4ed7c188f9 binman: test: Move FIT image test files to test/fit/
Move about 40 test files for FIT images (signing, external data,
split-elf, encryption, alignment, firmware loadables, templates) into
a fit/ subdirectory. Drop the numeric prefixes and the redundant fit_
filename prefix, and update all references.

Rename the three signature.dts variants to have unique names:
signature.dts, signature_multi_key.dts and signature_no_nodes.dts.

Signed-off-by: Simon Glass <simon.glass@canonical.com>
2026-03-18 06:14:16 -06:00
Simon Glass
b6d35dcc5d binman: test: Move x86 and Intel test files to test/x86/
Move about 40 test files for x86 and Intel platform support (ROM,
microcode, ME, IFWI, FSP, descriptor, reset16, start16, FIT) into an
x86/ subdirectory. Drop the numeric prefixes and the redundant x86_
filename prefix, and update all references.

Signed-off-by: Simon Glass <simon.glass@canonical.com>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
2026-03-18 06:14:16 -06:00
Simon Glass
d076ec97f0 binman: test: Move U-Boot variant test files to test/xpl/
Move about a dozen test files for U-Boot image variants (SPL, TPL,
VPL, DTB, nodtb, bss-pad) into an xpl/ subdirectory. Drop the
numeric prefixes and the redundant u_boot_ filename prefix, and
update all references.

Signed-off-by: Simon Glass <simon.glass@canonical.com>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
2026-03-18 06:14:16 -06:00
Simon Glass
03d5ef3063 binman: test: Move pack/layout test files to test/pack/
Move about 50 test files related to basic layout, packing, alignment,
sections, and image structure into a pack/ subdirectory. Drop the
numeric prefixes from the filenames and update all references in
ftest.py, entry_test.py, and binman_tests.rst

Signed-off-by: Simon Glass <simon.glass@canonical.com>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
2026-03-18 06:14:16 -06:00
Simon Glass
b16319c643 binman: test: Capture output from tests with warnings
Tests are supposed to run silently and capture any output produced.

Fix testRemoveTemplate() so that the message about the missing openssl
is captured, along with the invalid-images message.

Fix testNxpImx9Image() as well, since it is expected that container.img
and bl31.bin are missing.

Signed-off-by: Simon Glass <simon.glass@canonical.com>
2026-03-18 06:14:16 -06:00
David Lechner
142c805d47 clk: mediatek: set CLK_PARENT_XTAL on fixed factor clocks
Explicitly set the CLK_PARENT_XTAL flag for fixed factor clocks.

Prior to this, it was assumed that clock ID 0 was CLK_XTAL and other
IDs used a different clock tree when no parent was explicitly set.
Making the parent explicit will allow us to remove this confusing
behavior in the future.

Reviewed-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260306-clk-mtk-remove-clk-bypass-xtal-flag-v2-8-b253b49f17b2@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
2026-03-17 17:28:43 -05:00
David Lechner
7595833599 clk: mediatek: move common PARENT macros to header
Move repeated *_PARENT() macros from chip-specific .c files to the
common mtk-clk.h file.

Reviewed-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260306-clk-mtk-remove-clk-bypass-xtal-flag-v2-4-b253b49f17b2@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
2026-03-17 17:28:43 -05:00
David Lechner
4e184ff5a0 clk: mediatek: add MUX_GATE_MIXED macros
Add new MUX_GATE_MIXED and MUX_GATE_MIXED_FLAGS macros for mixed parent
muxes that have a gate. These will be used in a few drivers where we
already have this type of mux clocks.

Reviewed-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260306-clk-mtk-remove-clk-bypass-xtal-flag-v2-3-b253b49f17b2@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
2026-03-17 17:28:43 -05:00
David Lechner
e40978fff3 clk: mediatek: rename CLK_DOMAIN_SCPSYS
Rename CLK_DOMAIN_SCPSYS to CLK_MUX_DOMAIN_SCPSYS to make it more clear
that this flag only applies to MUX clocks and not other clock types.

Reviewed-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260306-clk-mtk-remove-clk-bypass-xtal-flag-v2-2-b253b49f17b2@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
2026-03-17 17:28:43 -05:00
David Lechner
f922929828 clk: mediatek: rename HAVE_RST_BAR
Rename HAVE_RST_BAR to CLK_PLL_HAVE_RST_BAR. This makes it more clear
that this flag only applies to PLL clocks. Also add a blank line between
CLK_PLL_HAVE_RST_BAR and the CLK_MUX_ macros to keep the grouping of the
flags consistent.

Reviewed-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260306-clk-mtk-remove-clk-bypass-xtal-flag-v2-1-b253b49f17b2@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
2026-03-17 17:28:43 -05:00
Paul Kocialkowski
98429b7be6 sunxi: a133: dram: Align parameters terminology with Allwinner
There is a mistmatch between Allwinner's dram_para BSP definitions and the
parameters names in mainline u-boot for TPR1-3. What we call TPR1 is actually
MR22 while TPR2 is TPR0 and TPR3 is TPR1. MR22 does get written to the
corresponding register. This only concerns LPDDR4 support.

Introduce a new Kconfig entry for MR22 and proceed with the rename.
Update the only config currently using it.

See the list of parameters from the Allwinner BSP at the end of:
https://linux-sunxi.org/A133/DRAMC

Note that the H616/H6 code is coherent with this new TPR0 definition
(and does not use TPR1 and MR22).

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Sponsored-by: MEC Electronics GmbH <https://www.mec.at/>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2026-03-17 23:27:24 +01:00
Paul Kocialkowski
3d76980947 sunxi: a133: dram: Fix PHY dx delays offsets and add dmb
Some of the offsets for the DRAM PHY dx delays are wrong (as compared
to the H616 code and the reference binary) since the
mctl_phy_dx_delay0_inner function does not perform the correct
calculation for some of them.

Introduce a mctl_phy_dx_delay0_inner0 to fix the incorrect offsets and
rename the existing function to mctl_phy_dx_delay0_inner1 for the
offsets it correctly handles.

Also add memory barriers that are also present in the H616 code while
at it.

This fixes detection of 4 GiB DRAM on some boards using LPDDR4.

Signed-off-by: Paul Kocialkowski <paulk@sys-base.io>
Sponsored-by: MEC Electronics GmbH <https://www.mec.at/>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2026-03-17 23:27:24 +01:00
Chris Chen
4cce6acace clk: mediatek: add clock driver for MT8189
Add new clock driver for MedaiTek MT8189 and compatible SoCs.

Signed-off-by: Chris Chen <chris-qj.chen@mediatek.com>
Co-developed-by: David Lechner <dlechner@baylibre.com>
Reviewed-by: Julien Stephan <jstephan@baylibre.com>
Reviewed-by: Macpaul Lin <macpaul.lin@mediatek.com>
Link: https://patch.msgid.link/20260303-mtk-mt8189-clocks-v4-7-ee85f8dd2f0d@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
2026-03-17 16:35:02 -05:00
Irving-CH Lin
290d17490e dt-bindings: clock: Add MediaTek MT8189 clock
Add IDs for the clocks of MediaTek MT8189 SoC.

Signed-off-by: Irving-CH Lin <irving-ch.lin@mediatek.com>
Reviewed-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260303-mtk-mt8189-clocks-v4-6-ee85f8dd2f0d@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
2026-03-17 16:34:55 -05:00
David Lechner
9776543804 clk: mediatek: add MUX_MIXED_CLR_SET_UPD_FLAGS() macro
Add a new MUX_MIXED_CLR_SET_UPD_FLAGS() macro. This is the same as
MUX_CLR_SET_UPD_FLAGS() except that it uses the parent_flags member
of the union instead of parent.

This will be needed by the incoming mt8189 clock driver.

Reviewed-by: Julien Stephan <jstephan@baylibre.com>
Reviewed-by: Macpaul Lin <macpaul.lin@mediatek.com>
Link: https://patch.msgid.link/20260303-mtk-mt8189-clocks-v4-5-ee85f8dd2f0d@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
2026-03-17 16:34:50 -05:00
David Lechner
b6d11f69ac clk: mediatek: add CLK_PARENT_EXT
Add support for external clock parent type in MediaTek clock driver to
allow multiple external clock sources.

This is intended to eventually replace CLK_PARENT_XTAL which only allows
a single external clock source. Replacing CLK_PARENT_XTAL is not trivial
since it would required touching all chip-specific drivers. So that is
saved for another day.

Before this change, the only way to add additional external clocks was
to use a clock ID mapping and add the external clock in the fixed clocks
portion of the CLK_PARENT_TOPCKGEN clocks. After this change, such hacks
are no longer necessary and external clocks can be added in a cleaner
way.

Reviewed-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260303-mtk-mt8189-clocks-v4-4-ee85f8dd2f0d@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
2026-03-17 16:34:47 -05:00
David Lechner
d09876c4f6 clk: mediatek: add mtk_clk_id_is_* helper functions
Add helper functions to check if a clock ID corresponds to a particular
clock type (mux, gate, fdiv). This simplifies the code and makes it more
readable.

Additionally, it removes the restriction that fdivs_offs < muxes_offs <
gates_offs by making the checking more strict in some places. This will
allow future drivers to not have to define a mapping to meet this
requirement.

Reviewed-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260303-mtk-mt8189-clocks-v4-3-ee85f8dd2f0d@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
2026-03-17 16:34:44 -05:00
David Lechner
00d0ff7f81 clk: mediatek: refactor parent rate lookup functions
Refactor duplicate parent rate lookup code into a common function.

Instead of relying on rules like X is always the parent of Y, we use
the driver ops pointer to make sure we are actually getting the correct
parent clock device. This allows the same function to be called from
different clock types and will allow future chip-specific clock drivers
to not have to follow the rules as strictly.

Reviewed-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260303-mtk-mt8189-clocks-v4-2-ee85f8dd2f0d@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
2026-03-17 16:34:35 -05:00
David Lechner
5d24726581 clk: mediatek: use correct struct type for infrasys clocks
Fix the private data type struct type in a couple of infrasys clock
functions.

struct mtk_cg_priv is a superset of struct mtk_clk_priv and has the same
layout at the beginning so there was no compile errors or runtime bugs.
This could only be found by inspecting the code.

Reviewed-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260303-mtk-mt8189-clocks-v4-1-ee85f8dd2f0d@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
2026-03-17 16:34:27 -05:00
David Lechner
4f821825c8 clk: mediatek: mt8188: fix CLK_TOP_CLK{13,26}M rates
Change CLK_TOP_CLK13M rate from 130_000_000 to 13_000_000 and
CLK_TOP_CLK26M rate from 260_000_000 to 26_000_000. As the names
suggest, these clocks are 13/26 MHz, not 130/260 MHz.

Fixes: 5e9bbbdab0 ("clk: mediatek: mt8188: add missing fixed clock")
Fixes: 11f3cc4632 ("clk: mediatek: add MT8188 clock driver")
Reviewed-by: Julien Stephan <jstephan@baylibre.com>
Tested-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260305-clk-mtk-fix-mt8188-rates-v2-1-0ce2b5212775@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
2026-03-17 16:07:09 -05:00
Jamie Gibbons
b51e59c8b3 riscv: Add support for BeagleV-Fire
Bring U-Boot support for the BeagleV-Fire by adding a device tree and
supporting board files etc.

Signed-off-by: Jamie Gibbons <jamie.gibbons@microchip.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2026-03-17 11:39:18 +08:00
Fabio Estevam
e4be6fc6ca doc: imx95_evk: Fix the binary name
U-Boot produces flash.bin as the final boot image when building for
the i.MX95 EVK, but the documentation refers to imx-boot-imx95.bin.

Update the instructions to use flash.bin when copying the image to
the SD card.

Signed-off-by: Fabio Estevam <festevam@nabladev.com>
2026-03-16 18:45:26 -03:00
Fabio Estevam
24f8b19afd doc: imx95_evk: Update Arm GNU toolchain version to 14.2
The imx-oei and imx-sm build systems defaults to:

  TC_VERSION ?= 14.2.rel1

but the documentation still instructs users to download the 13.3 toolchain.
This causes the build to fail because the expected directory name does
not exist.

Update the documentation to reference the 14.2 toolchain to match the build
system default.

Signed-off-by: Fabio Estevam <festevam@nabladev.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
2026-03-16 18:45:26 -03:00
Alice Guo
306c7ce50b imx943_evk: Enable XSPI1
With this patch, XSPI1 are functional on the i.MX943 EVK board.

Signed-off-by: Alice Guo <alice.guo@nxp.com>
2026-03-16 18:44:58 -03:00
Ye Li
e1690715eb imx94_evk: Get ownership of XSPI control registers protected by GMID in SPL
To gain access to certain registers that are protected by GMID, the SPL
must release XSPI ownership to the current core.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2026-03-16 18:44:58 -03:00
Ye Li
1c6e3a7550 misc: ele_api: Add support for XSPI SET GMID command
The XSPI SET GMID command is used to assign GMID ownership to the
requester, allowing access to protected XSPI control registers. This API
must be called in SPL if XSPI GMID-protected settings need to be
modified. Otherwise, XSPI configuration depends on the previous GMID
owner to provide the correct settings.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2026-03-16 18:44:58 -03:00
Alice Guo
2875ae5969 spi: nxp_xspi: Add new driver for NXP XSPI controller
Add new driver to support NXP XSPI controller for NOR and NAND flash.
XSPI controller also uses a programmable sequence engine to provide
flexibility to support existing and future memory devices. It supports
single, dual, quad, octal modes of operation.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
2026-03-16 18:44:58 -03:00
Francois Berder
262258dc75 liebherr: btt: Fix buffer overflow in board_fit_config_name_match
The maximum length of the board name is not 11 characters
but 14: 11 bytes for the prefix + 3 bytes for the u8 + 1 NULL byte.
Hence, this commit increases the size of the name buffer variable
to 15. Also, this commit fixes the format specifier for the rev_id
variable.

Signed-off-by: Francois Berder <fberder@outlook.fr>
2026-03-16 18:44:33 -03:00
Niko Mauno
7d39e29350 misc: imx_ele: Fix compile without CMD_FUSE
If CONFIG_CMD_FUSE is not enabled in imx93_11x11_evk_defconfig, then
compilation fails with various undefined references to 'fuse_read',
such as:

  | .../arch/arm/mach-imx/imx9/soc.c:188:(.text.get_cpu_rev+0x38): undefined reference to `fuse_read'

therefore remove the 'fuse' command dependency in order to compile
fuse.c unconditionally to mitigate the issue.

Signed-off-by: Niko Mauno <niko.mauno@vaisala.com>
2026-03-16 18:44:13 -03:00
Peng Fan
d55cc91ab4 board: nxp: imx952_evk: Add i.MX952 15x15 lpddr4x board support
Add support for i.MX952 15x15 lpddr4x board support.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
2026-03-16 18:44:00 -03:00
Alice Guo
8f51aec3d1 arm: dts: Add U-Boot device tree for i.MX952 EVK
Add U-Boot specific device tree configuration for i.MX952 EVK board.

Signed-off-by: Alice Guo <alice.guo@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2026-03-16 18:44:00 -03:00
Peng Fan
38d8c286c2 arm64: dts: freescale: Add i.MX952 EVK basic device tree
Add i.MX952 EVK basic device tree, with UART1, SDHC[1,2] supported.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

[ upstream commit: a5aa8551d0046ec701e8962f83361165ccf640a4 ]

(cherry picked from commit bf18a0f083bdf73f806a3afb9b606b2cb0fcafb3)
2026-03-16 18:44:00 -03:00
Peng Fan
c3bb7bf1c0 arm64: dts: freescale: Add initial device tree for i.MX952
i.MX952 is designed for AI-powered sensor fusion and vision sensing
applications, it features 4 Corte-A55, 1 Cortex-M33, 1 Cortex-M7 and
NXP eIQ NPU and advanced graphics, video and advanced security with
edgelock. Product info could be found at:
https://www.nxp.com/products/i.MX-952

The basic device tree includes:
- clock, pin, power header files
- device nodes: CPU[0-3], SCMI firmware, Interrupt Controller, Sys counter,
  eDMA, MU, SPI, UART, I2C, USB and etc

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

[ upstream commit: b516a4dd6a1ff7ddbaf3ab30ddec88088a6ec9e6 ]

(cherry picked from commit 3546aa155a84b8af636d44c852c864845e654864)
2026-03-16 18:44:00 -03:00
Alice Guo
56b39ef00a arm: imx9: Keep WDG3/WDG4 untouched for i.MX952
On i.MX952, WDG3 and WDG4 are not used for system reset. PSCI is used
instead. Keep WDG3 and WDG4 in their default state rather than
explicitly disabling them.

Signed-off-by: Alice Guo <alice.guo@nxp.com>
2026-03-16 18:44:00 -03:00
Alice Guo
62a82fa290 cpu: imx952: Add i.MX952 support
This patch is used to add the imx type string of i.MX952 so that the
i.MX952 CPU info can be printed.

Signed-off-by: Alice Guo <alice.guo@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2026-03-16 18:44:00 -03:00
Alice Guo
9b3797dde7 arm: imx9: Add i.MX952 SoC support
Add basic SoC support for i.MX952:
- Add CONFIG_IMX952 Kconfig option
- Include i.MX952 clock and power headers
- Set CPU speed grade to 1.7GHz for i.MX952

Signed-off-by: Alice Guo <alice.guo@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: David Zang <davidzangcs@gmail.com>
2026-03-16 18:44:00 -03:00
Alice Guo
b65ac8c001 imx: container: Add i.MX952 support to get_imageset_end()
Extend get_imageset_end() to handle i.MX952.

Signed-off-by: Alice Guo <alice.guo@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2026-03-16 18:44:00 -03:00
Alice Guo
0faea69eff imx: ele_ahab: Add i.MX952 support to display_life_cycle()
Extend display_life_cycle() to support i.MX952.

Signed-off-by: Alice Guo <alice.guo@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2026-03-16 18:44:00 -03:00
Alice Guo
14adc40001 arm: imx: Add i.MX952 CPU type support
Add CPU type definition and detection macro for i.MX952 SoC.

Signed-off-by: Alice Guo <alice.guo@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2026-03-16 18:44:00 -03:00
Ye Li
abbf4d7f30 pinctrl: nxp: Add i.MX952 support
Multiple pads can drive the same module input pin, and a daisy chain
register is used to select the active input path. This patch defines
DAISY_OFFSET_IMX952 (0x460) and allows binding on i.MX952.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2026-03-16 18:44:00 -03:00
Ye Li
ea8b1afcd5 imx95/imx94: Remove board_phys_sdram_size from each board
Change to use default board_phys_sdram_size implementation in soc.c,
which will call SM API to get DDR size.

If board has special implementation for DDR size, then board_phys_sdram_size
could be implemented in board file to override the default one in soc.c.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2026-03-16 18:44:00 -03:00
Ye Li
e1cc7117b6 imx9: scmi: Get DDR size through SM SCMI API
System Manager(SM) has implemented the MISC protocol to retrieve DDR
information. Using this API, U-Boot can obtain the DDR size dynamically
instead of relying on static configuration macros.

This change addresses the DDR ECC enabled case, where 1/8 of the total
DDR size is reserved for ECC data. The scmi_misc_ddrinfo() returns the
DDR size with EEC overhead already deducted.

Implementation details:
- Query the DDR size via scmi_misc_ddrinfo()
- Replace direct REG_DDR_CS[0,1]_BNDS register reads with SCMI call
- Switch from PHYS_SDRAM[x]_SIZE macros to runtime detection
- For backward compatibility with older SM firmware, fall back to
  static PHYS_SDRAM[x]_SIZE configuration if the SCMI call fails

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2026-03-16 18:44:00 -03:00
Quentin Schulz
256557dd9a sunxi: remove usage of legacy LED API
We are trying to get rid of the legacy LED API and PinePhone is one of
the last ones requiring it.

Unlike all other users of the legacy LED API, PinePhone is controlling
the GPIO LED in SPL. Unfortunately, Sunxi doesn't enable DM support in
SPL because of tight space constraints, so we cannot make use of the
modern LED framework as that is based on DM_GPIO.

Since PinePhone is the last user of this API, I'm moving the logic to
Sunxi SPL code and will let this community decide how to handle this hot
potato.

The logic is extremely simplified as only one GPIO LED is currently
controlled in SPL by PinePhone. No need for handling multiple LEDs or
inverted polarity, let's keep it simple.

This however allows us to use the modern LED framework once in U-Boot
proper since this logic won't collide with the new framework.

Since the only misc drivers that were compiled in SPL were guarded by
CONFIG_LED_STATUS and CONFIG_LED_STATUS_GPIO, we can also disable
CONFIG_SPL_DRIVERS_MISC (which does nothing anymore).

This also saves some space for PinePhone in SPL and proper.

Tested-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Simon Glass <simon.glass@canonical.com>
2026-03-16 21:55:53 +01:00
E Shattow
1edeb52086 doc: board: starfive: jh7110 common update OPENSBI build env reference
Describe build with OpenSBI fw_dynamic.bin path as OPENSBI=<path> on the
same line instead of as an export. Also remedy a typo which had the wrong
directory path before the filename.

Fixes: 8304f32267 ("doc: board: starfive: update jh7110 common description")
Signed-off-by: E Shattow <e@freeshell.de>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2026-03-17 01:36:57 +08:00
E Shattow
24662f698f doc: board: starfive: jh7110 common give build output dir by env not arg
Describe build with output directory as O=<dir> environment variable
and not unrelated -O <output sync> command line argument.

Fixes: 8304f32267 ("doc: board: starfive: update jh7110 common description")
Signed-off-by: E Shattow <e@freeshell.de>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2026-03-17 01:36:57 +08:00
E Shattow
3ff56c603a doc: board: starfive: Add Xunlong OrangePi RV
OrangePi RV is a board that uses the same EEPROM product serial identifier
as the StarFive VisionFive 2 1.3b.

In fact it is not completely compatible with the StarFive VisionFive 2
1.3b for use with Linux Kernel however it is good enough for use with
U-Boot SPL and U-Boot Main. Describe how to set the devicetree search path
and, for advanced users, suggest that it is possible to update the EEPROM
data with an invented "XOPIRV" identifier for automatic board detection.

Signed-off-by: E Shattow <e@freeshell.de>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2026-03-17 01:36:57 +08:00