I have a hunch VPL_DM_SERIAL should not be selectable if VPL isn't set
as implied by the prefix. Additionally, still based on the prefix, I'm
assuming VPL_DM should be a dependency. Since VPL_DM can only be
selectable when VPL is enabled, only depend on VPL_DM.
This mirrors SPL_DM_SERIAL and TPL_DM_SERIAL so seems right to me.
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add initial pin control tables for the Renesas R-Car X5H R8A78000 SoC.
This SoC is the first one which includes custom DRV register handling,
different from previous generations due to change in DRV register bit
layout.
Signed-off-by: Huy Bui <huy.bui.wm@renesas.com>
Signed-off-by: Khanh Le <khanh.le.xr@renesas.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
The upcoming Renesas R-Car Gen5 uses different mapping of bits in DRV
control register, which is incompatible with existing DRV register bit
mapping. Add .set_drive_strength callback into sh_pfc_soc_operations
and call it from sh_pfc_pinconf_set(), to allow each SoC specific PFC
driver to implement replacement .set_drive_strength. Make the current
sh_pfc_pinconf_set_drive_strength() non-static, rename it with rcar_
prefix, and pass it as .set_drive_strength for existing PFC drivers.
This is a preparatory patch for R-Car Gen5, no functional change.
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Consistently use .set_drive_strength() and pass exisiting
sh_pfc_pinconf_set_drive_strength() as its parameter for
all PFC drivers. Rewrite commit message.]
Show bit position in config write debug log, which is helpful for cases
where the p port setting is applied at the exact p bit position.
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> # Unsplit the string
Fix Kconfig entry indent to be always consistently indented with
leading tabs, never with leading spaces. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Add support for the GPIO controller block in the R-Car Gen5 SoC family.
The GPIO controller has a General Input Enable Register (INEN), whose
reset state is to have all input disabled. The GPIO controller also has
updated offsets for its control registers. U-Boot uses three registers,
INDT, POSNEG, INEN, which have updated offsets, those are handled by the
driver.
Signed-off-by: Huy Bui <huy.bui.wm@renesas.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: - Access Gen5 specific registers via driver data offsets,
- Update commit message]
The Renesas R-Car Gen5 GPIO controller has INDT, POSNEG, INEN registers
at different offsets compared to previous generations. Introduce three
new entries in struct rcar_gpio_data {} match data to describe these
register offsets for each GPIO controller. Update the driver to access
these three registers through the match data offsets. No functional
change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Wrap the RCAR_GPIO_HAS_INEN quirk in more flexible struct rcar_gpio_data {}
in preparation for addition of Renesas R-Car Gen5 GPIO controller support.
The Renesas R-Car Gen5 GPIO controller requires more than a single quirk
to properly describe it, therefore increase the flexibility and introduce
full match data structure, and use it throughout the driver. No functional
change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Remove register macros for registers which are not used by this driver.
This makes it easier to get an overview of which registers are really
used by the driver. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
The PFC offset is no longer used directly in the driver since commit
fbf26bea39 ("gpio: renesas: Migrate to pinctrl GPIO accessors")
Drop the pfc_offset parsing.
Fixes: fbf26bea39 ("gpio: renesas: Migrate to pinctrl GPIO accessors")
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Add PHY driver for Multi-Protocol PHY present on Renesas R-Car X5H
R8A78000 SoC. Currently, the PHY driver only supports configuring
the MPPHY for ethernet operation.
Signed-off-by: Thanh Quan <thanh.quan.xn@renesas.com>
Signed-off-by: Phong Hoang <phong.hoang.wz@renesas.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> #Fix License-Identifier
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Clean up macros, indent, clock and reset handling in probe,
rename the driver and add r8a78000- into compatible string,
update commit message.]
Add support for the Ethernet Physical Coding Sublayer (PCS) controller
on R-Car Gen5 SoCs, specifically the Renesas R-Car X5H R8A78000.
The controller is based on the SERDES infrastructure used in previous
R-Car generations, with updates for Gen5 register layout and features.
Because majority of this driver is SoC-specific register programming,
the majority of this driver is different enough from R8A779F0 SerDes
driver to justify its own driver. Deduplication of the remaining bits
of code does not yield any improvement.
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Phong Hoang <phong.hoang.wz@renesas.com>
Signed-off-by: Tam Nguyen <tam.nguyen.xa@renesas.com>
Signed-off-by: Thanh Quan <thanh.quan.xn@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Add missing clk_bulk_disable() in fail path.
Drop always-true aneg_on setting.
Reduce poll delay from 100s to 100ms.
Use bulk reset operations to finalize reset handling.]
Add support for the Renesas Ethernet Switch3 (RSW3) controller,
present in R-Car Gen5 SoCs such as R-Car X5H (R8A78000). The
hardware offset differences are handled via driver match data.
The driver newly detects whether the switch prot is connected
to xPCS or not, and if so, turns on MIOC bit 3. This is new on
R-Car X5H. GWCKSC register is also programmed only on X5H. The
rest of the operation is identical to RSwitch2.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Tam Nguyen <tam.nguyen.xa@renesas.com>
Signed-off-by: Phong Hoang <phong.hoang.wz@renesas.com>
Signed-off-by: Thanh Quan <thanh.quan.xn@renesas.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
The MPIC_MDC_CLK clock setting value differs between R-Car S4
and R-Car X5H. Parametrize the value in preparation for R-Car
X5H addition into this driver. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
The GWDCBAC0, GWDCBAC1, FWPBFCSDC, CABPIRM register offsets changed
between R-Car S4 and R-Car X5H. Parametrize their offsets in preparation
for R-Car X5H addition into this driver. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Inline FWRO, CARO, GWRO, TARO, RMRO macros directly into the
follow up register macros. FWRO, CARO, GWRO, TARO are already
zero, drop them. RMRO is 0x1000, increment all registers which
add RMRO by 0x1000 directly. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
The forwarding engine CSD register offset changed between the
R-Car S4 and R-Car X5H. Parametrize this offset in preparation
for R-Car X5H addition into this driver. Clean up the macro
parameter names and make them more obvious. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
The total port counts differ across variants of this IP in
R-Car S4 and R-Car X5H. Parametrize port count in preparation
for R-Car X5H addition into this driver. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
The COMA, ETHA, GWCA offsets differ across variants of this IP in
R-Car S4 and R-Car X5H. Parametrize these offsets in preparation
for R-Car X5H addition into this driver. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
This IP does support operating MII and SerDes via different ports.
Currently, the driver assumes that MII and SerDes are always bound
together on the same port, but this may not be the case. Implement
support for controlling MII and SerDes separately.
While the change is extensive, the gist of the change is to pass
pointer to the selected port registers to MII or SerDes functions,
depending on which port and operations should be done on that port.
Each combined ETHA instance contains both MII and SerDes register
pointers, which may not point to the same port, and passes those
registers to MII and SerDes functions respectively to control the
MII or SerDes of each port.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
The new version of RSwitch3 in Renesas R-Car Gen5 uses multiple
clock to supply the IP. Convert the driver to bulk clock API to
cater for both single clock of R-Car S4 and multiple clock of
R-Car Gen5. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Empty RX DMA descriptor must contain .die_dt field set to DT_FEMPTY,
because hardware DMA overwrites this field to non-DT_FEMPTY when data
are received, and the .recv callback tests the content of RX descriptor
.die_dt field to determine whether hardware did receive any data and
updated the .die_dt field, and based on that information, receives a
packet or not. Fix the incorrect RX DMA descriptor initialization to
assure the .recv callback always works correctly.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Fix indent from multiple spaces to tabs, to be consistent with
coding style and the rest of the driver. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Rockchip boards may depend on a working MMC regulator in SPL to
successfully load FIT payload from MMC. Typically, these boards only
include the vmmc-supply regulator and not its vin-supply in SPL control
FDT.
The commit f98d812e53 ("power: regulator: Add vin-supply for GPIO and
Fixed regulators") breaks loading FIT from MMC in SPL on some of these
boards due to now requiring the vin-supply to be included in the SPL
control FDT.
The commit also strangely enables any found vin-supply in
regulator_common_of_to_plat() and not when a regulator is enabled or as
part of regulator_autoset().
Revert the commit to fix FIT loading in SPL on broken boards.
If a board needs to have its vin-supply enabled, two options come to
mind:
- Add regulator-always-on prop to the regulator in the -u-boot.dtsi for
any board.
- Implement full support for reference counting of regulators and then
update the regulator-uclass to enable any found vin-supply when a
regulator is enabled.
This reverts commit f98d812e53.
Reported-by: Dang Huynh <danct12@riseup.net>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Dragan Simic <dsimic@manjaro.org>
If CONFIG_GPIO_HOG is not set, then gpio_hog_lookup_name() is empty,
and thus does not initialize any of its parameters. It does still
return 0 though, and so any calling function might assume that the
parameters have been initialized successfully.
Change the return value to -ENODEV in this case, as the function
would in the case when CONFIG_GPIO_HOG is set but the gpio hog
could not be found.
Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Heiko Schocher <hs@nabladev.com>
Introduce remote processor configuration for the i.MX93 Cortex-M33 core.
This patch adds:
- Address translation table (ATT) for i.MX93, including TCM
(secure and non-secure) and DDR regions.
- A new device configuration structure `imx_rproc_cfg_imx93` using SMC
method and ARM SMC ops.
- Device tree match entry for "fsl,imx93-cm33"
This enables remoteproc framework to properly initialize and manage the
Cortex-M33 core on i.MX93 platforms.
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
i.MX8MQ/M use MMIO based method to directly configure SRC registers
to start/stop M4.
Add mmio ops to start/stop/is_running.
Add i.MX8MQ cfg data, i.MX8MN reuses i.MX8MQ data.
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Support i.MX8MP/N with start/stop/device_to_virt/is_running/load
implemented. The device static configuration is mostly reused from
Linux Kernel with adapation to U-Boot dm_rproc_ops.
The booting method:
- load mmc 2:2 0x90000000 /lib/firmware/imx8mp_m7_DDR_rpmsg_lite_str_echo_
rtos.elf
- rproc load 0 0x90000000 ${filesize}
- rproc start 0
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Some areas needs to be initialized by using memcpy_toio and memset_io.
Following Linux Kernel commit: 40df0a91b2a5 ("remoteproc: add is_iomem to
da_to_va"), add this to U-Boot.
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Add support for the optional 'phy-supply' property in the ENETC MDIO
driver. This allows the driver to enable and manage the PHY's power
supply via the regulator framework when specified in device tree.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
This patch adds SPL Kconfig option (SPL_PHY_IMX8MQ_USB) for the i.MX8MQ,
i.MX8MP, i.MX95, and i.MX94 USB3.0 PHY driver, allowing the driver to be
compiled and probed in SPL stage.
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Since the EHCI USB driver is shared across i.MX91, i.MX93, i.MX94, and
i.MX95, the condition check is updated to use IMX9.
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Reviewed-by: Marek Vasut <marek.vasut@mailbox.org>
If OF_CONTROL is on, ti-musb.c registers a "ti-musb-wrapper" driver
that requires UCLASS_MISC. Hence, select MISC if both OF_CONTROL
and USB_MUSB_TI are selected.
Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
eMMC erase and write support on RK3528 is somewhat unreliable, sometime
e.g. mmc erase and write commands will fail with an error.
Use the delay line lock value for half card clock cycle, DLL_LOCK_VALUE,
to set a manual xx_TAP_VALUE to fix the unreliable eMMC support.
This is only enabled for RK3528, remaining SoCs still use the automatic
tap value, (DLL_LOCK_VALUE * 2) % 256, same value we configure manually
for RK3528.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add dummy implementation of set_rate for SCLK_GPU and SCLK_WIFI_PMU to
allow use of dts/upstream assigned-clocks in cru and pmucru nodes.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
A variety of Qualcomm features/fixes for this cycle, notably with a few
new platforms gaining support:
* Initial support for SDM670 (similar to SDM845), SM6350, and SM7150
platforms is added
* USB and UART issues on MSM8916 are addressed (improving stability/
reliability)
* Firmware loading is implemented for the GENI serial engine, this is
used on some platforms to load firmware for i2c/spi/uart to work
Some additional patches like binman support for building MBN files still
need some additional work.
CI: 8ef6ac07b3/pipelines
