Commit Graph

100349 Commits

Author SHA1 Message Date
Yannic Moog
3ae668b9d2 binman: mark optional missing blobs as absent
Optional blobs should mark themselves as absent to avoid being packed
into an image.
Extend the documentation of this behaviour. Although the documentation
implied this before, the "optional" property had not been explained
properly before.
The behaviour will change as now absent entries are no longer
packed into an image. The image map will also reflect this.
As a result, the CheckForProblems() function will no longer alert on
optional (blob) entries. This is because the missing optional images
were removed before CheckForProblems is called.
Adjust the testExtblobOptional test case to highlight that we are
testing not only an optional image but the image is missing as well. The
behaviour for these is different where the latter will not be packaged
into the image.

Reported-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Yannic Moog <y.moog@phytec.de>
Reviewed-by: Bryan Brattlof <bb@ti.com>
2025-06-26 09:54:05 -06:00
Yannic Moog
a657d87f08 binman: drop "faked" return value from check_fake_fname
check_fake_fname sets the faked member of the entry. Use that member
to get the faked status instead of a returned value indicating the same.
Add type annotations to the modified functions while at it.

Signed-off-by: Yannic Moog <y.moog@phytec.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bryan Brattlof <bb@ti.com>
2025-06-26 09:54:05 -06:00
Yao Zi
548d997229 ram: Move Kconfig options into their own menu entry
RAM drivers using Device Model currently lack of their own Kconfig menu
entry, which makes Kconfig put all options of the class in the top-level
menu of device drivers. These options are also incorrectly grouped with
pinctrl options in the generated .config, which is hard to read. Let's
create a menu entry for these drivers.

Fixes: 6c51df6859 ("dm: Add support for RAM drivers")
Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
2025-06-12 16:14:33 -06:00
Aristo Chen
0805e46486 bootstage: Fix typo
Fix typo from heder to header

Signed-off-by: Aristo Chen <aristo.chen@canonical.com>
2025-06-12 16:14:33 -06:00
Richard Weinberger
9fe2e4b464 fdt: Make sure there is no stale initrd left
Although if we don't setup an initrd, there could be a stale initrd
setting from the previous boot firmware in the live device tree. So,
make sure there is no setting left if we don't want an initrd.

This can happen when booting on a Raspberry Pi. The boot firmware can
happily load an initrd before us and configuring the addresses in the
live device tree we get handed over.

Especially the setting `auto_initramfs` in config.txt is dangerous.
When enabled (default), the firmware tries to be smart and looks for
initramfs files.

Signed-off-by: Richard Weinberger <richard@nod.at>
2025-06-12 16:13:51 -06:00
Tony Dinh
53cc4332b3 ext4fs: Fix: Read outside partition error (take 2)
Use lbaint_t for blknr to avoid overflow in ext4fs_read_file().

Background:

blknr (block number) used in ext4fs_read_file() could be increased to a
very large value and causes a wrap around at 32 bit signed integer max,
thus becomes negative. This results in an out-of-normal range for sector
number (during the assignment delayed_start = blknr) where delayed_start
sector is typed uint64 lbaint_t. This causes the "Read outside partition"
error.

Looks like we also have this overflown problem in ext4_write.c that needs
to be addressed.

This patch was tested on the Synology DS116 (Armada 385) board, and a
4TB Seagate HDD.

Signed-off-by: Tony Dinh <mibodhi@gmail.com>
2025-06-12 13:22:26 -06:00
Bryan Brattlof
52c0290526 binman: add atf-bl1 to etypes
Some SoCs require a Trusted Firmware-A (TF-A) AP Trusted ROM (BL1) to
initialize the SoC before U-Boot can run properly. Add an atf-bl1 etype
so we can properly package BL1 into a final binary

Signed-off-by: Bryan Brattlof <bb@ti.com>
Acked-by: Simon Glass <sjg@chromium.org>
2025-06-12 13:22:23 -06:00
Emanuele Ghidoli
79ae5510a2 arm: mach-k3: j784s4: Call do_board_detect() before DDR probing
Call do_board_detect() hook before the K3 DDRSS driver gets probed.
It will allow boards to adjust DDR timings in do_board_detect().

Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
2025-06-12 13:19:59 -06:00
Tom Rini
d142036b4c Merge patch series "Update the kbuild system to 5.1"
Ilias Apalodimas <ilias.apalodimas@linaro.org> says:

Another series backporting and merging patches from Linux 5.1 kbuild.
There is still a gap that I plan to update after this series gets
merged [0]

[0] 5da099cef0

Link: https://lore.kernel.org/r/20250611202449.2317279-1-ilias.apalodimas@linaro.org
2025-06-11 16:22:53 -06:00
Ilias Apalodimas
070b81458a kbuild: fix single target build for external module
Backported from kernel
commit e07db28eea38 ("kbuild: fix single target build for external module")

It's worth noting that crmodverdir is empty for U-Boot.
Just backport it to make diffing easier

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-06-11 16:21:36 -06:00
Ilias Apalodimas
45acf56e59 kbuild: make 'archprepare' depend on 'scripts'
Backported from kernel
commit 059bc9fc375e ("kbuild: make 'archprepare' depend on 'scripts'")

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-06-11 16:21:36 -06:00
Ilias Apalodimas
4a247d1376 kbuild: mark prepare0 as PHONY to fix external module build
Backported from kernel
commit e00d88804814 ("kbuild: mark prepare0 as PHONY to fix external module build")

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-06-11 16:21:36 -06:00
Ilias Apalodimas
27529f1cb0 kbuild: skip parsing pre sub-make code for recursion
Backported from kernel
commit 221cc2d27ddc ("kbuild: skip parsing pre sub-make code for recursion")

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-06-11 16:21:36 -06:00
Ilias Apalodimas
d1b6489ef1 kbuild: do not overwrite .gitignore in output directory
Backported from kernel
commit 156e7cbb3ef5 ("kbuild: do not overwrite .gitignore in output directory")

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-06-11 16:21:36 -06:00
Ilias Apalodimas
057a53b570 gcc-9: silence 'address-of-packed-member' warning
Backported from kernel
commit 6f303d60534c ("gcc-9: silence 'address-of-packed-member' warning")

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-06-11 16:21:36 -06:00
Ilias Apalodimas
931f04a85a kbuild: remove meaningless prepare2 target
Backported from kernel
commit 4f1c1008e786 ("kbuild: remove meaningless prepare2 target")

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-06-11 16:21:36 -06:00
Ilias Apalodimas
156fdc57f7 kbuild: gitignore output directory
Backported from kernel
commit 3a51ff344204 ("kbuild: gitignore output directory"

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-06-11 16:21:36 -06:00
Ilias Apalodimas
c4a52fbb67 kbuild: use -Werror=implicit-... instead of -Werror-implicit-...
Backported from kernel
commit b89f25ea7892 ("kbuild: use -Werror=implicit-... instead of -Werror-implicit-..."

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-06-11 16:21:36 -06:00
Ilias Apalodimas
3991f85e4c kbuild: clang: choose GCC_TOOLCHAIN_DIR not on LD
Backported from kernel
commit ad15006cc784 ("kbuild: clang: choose GCC_TOOLCHAIN_DIR not on LD")

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-06-11 16:21:36 -06:00
Ilias Apalodimas
a76fb6981f kbuild: use assignment instead of define ... endef for filechk_* rules
Backported from kernel
commit ba97df45581f ("kbuild: use assignment instead of define ... endef for filechk_* rules")

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-06-11 16:21:36 -06:00
Ilias Apalodimas
0ebda5f1f0 kbuild: add -Werror=implicit-int flag unconditionally
Backported from kernel
commit 61a0902a06d6a ("kbuild: add -Werror=implicit-int flag unconditionally")

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-06-11 16:21:36 -06:00
Ilias Apalodimas
7e81e690d7 kbuild: add -fno-PIE flag unconditionally
Backport from kernel
commit 42a92bccd213 ("kbuild: add -fno-PIE flag unconditionally")

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-06-11 16:21:36 -06:00
Tom Rini
ae297ca722 Merge patch series "dm: core: use {s,u}32 instead of int for dev_read_{s,u}32_default"
Quentin Schulz <foss+uboot@0leil.net> says:

Out of all the dev_read_*_default functions, only two do not properly
use the type as argument and return type: dev_read_u32_default and
dev_read_s32_default. They both use int instead of u32/s32.

Considering that it's generally not guaranteed that an int is 4 bytes
but also for consistency sake, let's have them use the expected type.

Note that I have not tested this, just stumbled upon that inconsistency
by chance.

Link: https://lore.kernel.org/r/20250528-dev_read_x32_default-v1-0-6ab1734dd7a2@cherry.de
2025-06-11 13:31:45 -06:00
Quentin Schulz
ad03050e26 dm: core: use s32 instead of int for dev_read_s32_default
dev_read_s32_default is for getting an s32 from a Device Tree property
and allows to take a default value if that property is missing.

Considering it calls ofnode_read_u32_default which takes a u32 and
returns a u32, it should do the same instead of using an int, especially
considering that int size is typically architecture-specific, as opposed
to s32/u32.

s32 and u32 being the same size, dev_read_s32* functions calling
ofnode_read_u32_default shouldn't be an issue (at the type level at
least) as the information will be stored appropriately in 4B regardless
of the sign.

This incidentally matches all other dev_read_*_default functions.

Fixes: a1b17e4f4c ("dm: core: Add a function to read into a unsigned int")
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2025-06-11 13:31:35 -06:00
Quentin Schulz
b4b66e2f29 dm: core: use u32 instead of int for dev_read_u32_default
dev_read_u32_default is for getting a u32 from a Device Tree property
and allows to take a default value if that property is missing.

Considering it calls ofnode_read_u32_default which takes a u32 and
returns a u32, it should do the same instead of using an int, especially
considering that int size is typically architecture-specific, as opposed
to u32.

This incidentally matches all other dev_read_*_default functions (except
dev_read_s32_default which will be tackled in the next commit).

Fixes: 47a0fd3bad ("dm: core: Implement live tree 'read' functions")
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2025-06-11 13:31:35 -06:00
Tom Rini
4b5cb57611 Merge tag 'u-boot-stm32-20250611' of https://source.denx.de/u-boot/custodians/u-boot-stm into next
CI: https://source.denx.de/u-boot/custodians/u-boot-stm/-/pipelines/26607

- Add clock and reset drivers support for STM32MP25
- Add STM32H747-Discovery board support
- Add tamp_nvram driver
- Add SPL support and clock tree init to STM32MP13 RCC driver
- Add STM32MP13xx ram support
- Add support for STM32 Image V2.0 for STM32MP13xx
- Fix SYSRAM size on STM32MP13xx
- Fix DBGMCU macro on STM32MP13xx
- Auto-detect ROM API table on STM32MP15xx
2025-06-11 12:00:36 -06:00
Dario Binacchi
7ab0ee3a59 board: stm32: add stm32h747-discovery board support
The board includes an STM32H747XI SoC with the following resources:
 - 2 Mbytes Flash
 - 1 Mbyte SRAM
 - LCD-TFT controller
 - MIPI-DSI interface
 - FD-CAN
 - USB 2.0 high-speed/full-speed
 - Ethernet MAC
 - camera interface

Detailed information can be found at:
https://www.st.com/en/evaluation-tools/stm32h747i-disco.html

Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2025-06-11 12:00:36 -06:00
Dario Binacchi
366f0bfe4f ARM: dts: stm32: add stm32h747i-disco-u-boot DTS file
Add stm32h747i-disco-u-boot DTS file with FMC SDRAM node and its
pinmux settings.

Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2025-06-11 12:00:36 -06:00
Dario Binacchi
cb348ba58f ARM: dts: stm32: support STM32h747i-disco board
The board includes an STM32H747XI SoC with the following resources:
 - 2 Mbytes Flash
 - 1 Mbyte SRAM
 - LCD-TFT controller
 - MIPI-DSI interface
 - FD-CAN
 - USB 2.0 high-speed/full-speed
 - Ethernet MAC
 - camera interface

Detailed information can be found at:
https://www.st.com/en/evaluation-tools/stm32h747i-disco.html

Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Link: https://lore.kernel.org/r/20250427074404.3278732-9-dario.binacchi@amarulasolutions.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>

[ upstream commit: 49ba8fc6eab63165639ffbb9f976222d39739cab ]

(cherry picked from commit 19c508dc3d584dc81c0cc6a05576f436022db5b6)
2025-06-11 12:00:32 -06:00
Dario Binacchi
3a310f59c3 ARM: dts: stm32: add an extra pin map for USART1 on stm32h743
Add an additional pin map configuration for using the USART1 controller
on the stm32h743 MCU.

Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Link: https://lore.kernel.org/r/20250427074404.3278732-8-dario.binacchi@amarulasolutions.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>

[ upstream commit: 8e71dfe46a4a1e9505b1a327470f879b63388968 ]

(cherry picked from commit 9d5ec2c9c5d5131e701447c5c32aaf6c688c6e01)
2025-06-11 12:00:19 -06:00
Dario Binacchi
1addd0e429 ARM: dts: stm32: add pin map for UART8 controller on stm32h743
Add a pin map configuration for using the UART8 controller on the
stm32h743 MCU.

Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Link: https://lore.kernel.org/r/20250427074404.3278732-7-dario.binacchi@amarulasolutions.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>

[ upstream commit: 47d16ab94b8e5e85aedba3cd22cfdf3877bf1dfb ]

(cherry picked from commit 59621a6472cd6eeb748ed6d6202a21d0f3cc5a83)
2025-06-11 12:00:15 -06:00
Dario Binacchi
d4fe7cd8ca ARM: dts: stm32: add uart8 node for stm32h743 MCU
Add support for UART8 by applying the settings specified in the
reference manual RM0433.

Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Link: https://lore.kernel.org/r/20250427074404.3278732-6-dario.binacchi@amarulasolutions.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>

[ upstream commit: 07aa43adae2363c3734055aeba0789536fa0f8f2 ]

(cherry picked from commit 8fe35c381c7c6db1b95c80be551afada1e9f28e0)
2025-06-11 12:00:10 -06:00
Dario Binacchi
e543e8b409 dt-bindings: clock: stm32h7: rename USART{7,8}_CK to UART{7,8}_CK
As stated in the reference manual RM0433, the STM32H743 MCU has
USART1/2/3/6, UART4/5/7/8, and LPUART1. The patches make all the clock
macros for the serial ports consistent with the documentation.

Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250427074404.3278732-5-dario.binacchi@amarulasolutions.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>

[ upstream commit: ecab3c40fa49a2073c4c916ebff9496a6b5db7bd ]

(cherry picked from commit aae9a01929183784bf3e2a8001aba408bd0dadf3)
2025-06-11 12:00:05 -06:00
Dario Binacchi
484f098b2f dt-bindings: arm: stm32: add compatible for stm32h747i-disco board
The board includes an STM32H747XI SoC with the following resources:
 - 2 Mbytes Flash
 - 1 MByte SRAM
 - LCD-TFT controller
 - MIPI-DSI interface
 - FD-CAN
 - USB 2.0 high-speed/full-speed
 - Ethernet MAC
 - camera interface

Detailed information can be found at:
https://www.st.com/en/evaluation-tools/stm32h747i-disco.html

Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250427074404.3278732-3-dario.binacchi@amarulasolutions.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>

[ upstream commit: 815d49f61ea049075482161f897aa13e1ae30cbb ]

(cherry picked from commit 06f64674b332c7db4ac56a4dccb0e960d25bea24)
2025-06-11 12:00:01 -06:00
Dario Binacchi
5d15b43052 ARM: dts: stm32h7-pinctrl: add _a suffix to u[s]art_pins phandles
Allow expanding possible configurations for the same peripheral,
consistent with the scheme adopted in Linux.

Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Link: https://lore.kernel.org/r/20250427074404.3278732-2-dario.binacchi@amarulasolutions.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>

[ upstream commit: 6a36dca4375fce51b627f5a985a79fc8b8bd7f55 ]

(cherry picked from commit 9a72c83f2e670087ae2d6dc54d2926f16c6762d0)
2025-06-11 11:59:57 -06:00
Simeon Marijon
6b9ecdfe9a stm32mp: Add tamp_nvram driver
TAMP backup registers will be exposed as nvmem cells.

Each registers ([0..127] for STM32MP2, [0..31] for STM32MP1) could be
exposed as nvmem cells under the nvram node in device tree

Signed-off-by: Simeon Marijon <simeon.marijon@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2025-06-11 09:42:56 +02:00
Marek Vasut
3f2eb09c22 tools: stm32image: Add support for STM32 Image V2.0
Add support for generating STM32 Image V2.0, which is used by STM32MP13xx.
The image header layout is similar to STM32MP15xx STM32 Image V1.0, but is
different enough to justify duplicate functions to generate the v2 image.
This code at least attempts to align the V1 and V2 image handling where
possible.

Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
2025-06-11 09:42:56 +02:00
Marek Vasut
447d1bd05a ram: stm32mp1: Add STM32MP13xx support
Add support for configuring DRAM controller on STM32MP13xx SoC.
The DRAM controller is basically identical to the DWC controller
on STM32MP15xx SoC, except the bus width is reduced from 32bit to
16bit and a few registers and bits are therefore not present.

Handle the difference by factoring these parts out. Use IS_ENABLE()
as much as possible to assure code which is not enabled on builds
for a single SoC gets compiled out. Handle the different offset of
RCC_DDRITFCR register and missing DDRC2 clock the same way.

Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
2025-06-11 09:42:56 +02:00
Marek Vasut
0298696b1e clk: stm32mp13: Add SPL support and clock tree init to STM32MP13 RCC driver
Add SPL support and clock tree init to STM32MP13 RCC driver. This
consists of two parts, make SCMI into an optional dependency and
add clock tree initialization. The SCMI dependency is made optional
first by registering the few core clock provided by SCMI clock as
fixed clock, and second by letting the clock core parse out the
clock configuration from SoC registers. The clock initialization
code is derived from STM32MP15xx clock tree initialization code,
which is almost identical, except for the use of new PLL2000 for
PLL1 on STM32MP13xx .

Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
2025-06-11 09:42:56 +02:00
Marek Vasut
b2c50bd30b clk: stm32mp13: Fix typo in STM32MP13 RCC driver
Fix basic typo, missing t in security . No functional change .

Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2025-06-11 09:42:55 +02:00
Marek Vasut
ecd6fd02e1 ARM: stm32: Auto-detect ROM API table on STM32MP15xx
The ROM API table location is passed to the SPL by BootROM in register r0,
make use of this, store the content of r0 and later use it to access the
ROM API table to determine current boot device.

Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2025-06-11 09:42:55 +02:00
Marek Vasut
d4972d5b59 ARM: stm32: Fix DBGMCU macro on STM32MP13xx
The DBGMCU block is available at address 0x50081000 both on STM32MP13xx
and on STM32MP15xx . There is no reason to limit the DBGMCU macro being
set only on STM32MP15xx , remove the ifdeffery.

Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2025-06-11 09:42:55 +02:00
Marek Vasut
380d6f8c19 ARM: stm32: Fix SYSRAM size on STM32MP13xx
The STM32MP13xx has only 128 kiB of SYSRAM starting at address 0x2ffe0000 .
The STM32MP15xx has 256 kiB of SYSRAM starting at address 0x2ffc0000 . Make
sure both SoCs configure ARMV7_SECURE_BASE correctly . Define the SYSRAM
base in stm32.h to be consistent with the STM32MP15xx macro.

Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2025-06-11 09:42:55 +02:00
Marek Vasut
7df29a172a ARM: stm32: Drop unnecessary space
Drop a space after tab, no functional change.

Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2025-06-11 09:42:55 +02:00
Patrice Chotard
38aa59bb36 configs: stm32mp25: increase SYS_MALLOC_F_LEN to 0x60000
Due activation of SCMI, we need to increase SYS_MALLOC_F_LEN value
to avoid following message:

U-Boot 2025.04-01224-g75b77a2a6d31-dirty (Apr 25 2025 - 11:23:30 +0200)

alloc space exhausted ptr 400040 limit 400000
alloc space exhausted ptr 400020 limit 400000
alloc space exhausted ptr 400060 limit 400000
alloc space exhausted ptr 400060 limit 400000

Set SYS_MALLOC_F_LEN to 0x60000 to fix this issue.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2025-06-11 09:42:55 +02:00
Patrice Chotard
1cdb64ad3a configs: stm32mp13: increase SYS_MALLOC_F_LEN to 0x210000
Due SCMI update to protocol v2.0, we need to increase
SYS_MALLOC_F_LEN value to avoid following message:
alloc space exhausted ptr 200040 limit 200000

Set SYS_MALLOC_F_LEN to 0x210000 to fix this issue.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2025-06-11 09:42:55 +02:00
Patrice Chotard
fddf9886d2 ARM: dts: stm32: switch from fixed to scmi clocks for stm32mp257f-ev1
SCMI clocks are now available, switch from fixed to SCMI clocks.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2025-06-11 09:42:55 +02:00
Gabriel Fernandez
0994a627c2 reset: stm32mp25: add stm32mp25 reset driver
Implement STM32MP25 reset drivers using stm32-core-reset API.
This reset stm32-reset-core API and will be able to use DT binding
index started from 0.

This patch also moves legacy reset into stm32 directory reset.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2025-06-11 09:42:55 +02:00
Gabriel Fernandez
901e0d95df clk: stm32: fix clock counter
In RCC the ops of the CCF registered CLK device can be called directly,
this patch avoid recursive call of clk_ function done by CCF clock
framework which update the clock information, for example
clk_enable is called 2 times, clkp->enable_count is increased 2 times.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Lukasz Majewski <lukma@denx.de>
Cc: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2025-06-11 09:42:55 +02:00
Patrick Delaunay
51954665a7 phy: stm32-usbphyc: manage properly the clk identifier with CCF
Add private uclass data for "stm32-usbphyc-clk" as it is not done
by the driver model.

This clk struct is needed by CCF to save the unique id used to identify
each clock.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Lukasz Majewski <lukma@denx.de>
Cc: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2025-06-11 09:42:55 +02:00