CI: https://source.denx.de/u-boot/custodians/u-boot-tpm/-/pipelines/29283
An update on AB subsystem allowing multiple FWU metadata
storage drivers to be selected simultaneously instead of
being mutually exclusive. The board can then select the
appropriate driver at runtime based on the devicetree
description.
The cdns3_bind() function is responsible for identifying the appropriate
driver to bind to the USB Controller's device-tree node. If the device-tree
node has the 'dr_mode' property set to 'otg', the existing approach fails
to bind a driver, leading to loss of functionality.
To address this, use the VBUS Valid field of the OTG Status register to
determine the role as follows:
- If VBUS Valid field is set, it indicates that a USB Host is supplying
power and the Controller should assume the Peripheral role.
- If VBUS Valid field is clear, it indicates the absence of a USB Host and
the Controller should assume the Host role.
Additionally, when 'dr_mode' happens to be 'otg' and the STRAP settings
are not specified, use VBUS Valid to determine the role in cdns3_drd_init()
and assign it to cdns->dr_mode.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: Marek Vasut <marek.vasut@mailbox.org>
Pull request efi-next-2026-02-15
CI: https://source.denx.de/u-boot/custodians/u-boot-efi/-/jobs/1380382
UEFI:
* Add MBR support to EFI_PARTITION_INFO_PROTOCOL
* disk: part_dos: Move header to the main include directory
* disk: part_dos: Align dos_partition_t with struct partition
* disk: part_efi: Remove redundant struct partition definition
* disk: part_dos: Document part_get_info_extended() helper function
* disk: part_dos: Refactor to allow retrieving raw MBR partition data
* efi_loader: disk: Extend EFI_PARTITION_INFO_PROTOCOL to support MBR
* efi_selftest: Enhance MBR test for PARTITION_INFO_PROTOCOL
* Prepare for supporting more stores (e.g. SPI-flash) for EFI variables.
* efi_var: Unify read/write access helper function
* efi_loader: Setup default location for UEFI Variables storing
* efi_var_file: refactor to move buffer functions
EFI_VARIABLE_FILE_STORE is only available when FAT_WRITE is enabled but
that's not valid for all platforms and dependency should be covered.
Also Kconfig behavior is that if default option is not valid then Kconfig
selects the first presented valid option instead hence it is better to
record EFI_VARIABLE_NO_STORE as safe default option.
Suggested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
efi_var_to/from_file() suggest method where variables are placed. But there
is no reason for it and generic name can be used to wire also different
locations for variables.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on AML-S905D3-CC
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Currently efi_var_file.c has functions to store/read
EFI variables to/from memory buffer. These functions
can be used with other EFI variable stores so move
them out to efi_var_common.c
Signed-off-by: Shantur Rathore <i@shantur.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on AML-S905D3-CC
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
The EFI_PARTITION_INFO_PROTOCOL test was added before the protocol fully
supported MBR partitions. As a result, it lacked specific checks for the
content of the raw MBR partition record.
Now that MBR support has been implemented, enhance the selftest to provide
coverage for the MBR entries too.
This verifies that the protocol correctly reads and exposes MBR partition
records and prevents this functionality to regress due future changes.
Signed-off-by: Javier Martinez Canillas <javierm@redhat.com>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
The EFI_PARTITION_INFO_PROTOCOL provides detailed information about
partitions. The UEFI specification mentions that both GPT and MBR
partition schemes are supported, but the U-Boot implementation only
supports the former.
This can cause compatibility issues for platforms whose boot ROM only
supports MBR. This change adds support for MBR partition tables to
the protocol, making U-Boot compatible with systems that require a
legacy MBR table.
Signed-off-by: Javier Martinez Canillas <javierm@redhat.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Refactor the part_get_info_extended() helper function (which already
recursively traverses DOS partitions) to optionally return the raw MBR
partition structure (dos_partition_t).
This allows other subsystems, such as EFI, to retrieve the partition
details in the legacy MBR format.
Signed-off-by: Javier Martinez Canillas <javierm@redhat.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
The function receives many parameters but these are not documented.
Add a description for these to make it easier to follow what it does.
Suggested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Javier Martinez Canillas <javierm@redhat.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Now that dos_partition_t and struct partition are identical, the duplicated
data structure definition in the part_efi.h header can just be removed.
This results in a single, shared definition for MBR partition table
entries, instead of having the same definition in two different places.
Signed-off-by: Javier Martinez Canillas <javierm@redhat.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
The dos_partition_t struct defined in part_dos.h is nearly identical to
the struct partition defined in part_efi.h. They differ primarily in how
define their starting sector and number of sectors fields.
The former uses unsigned char arrays while the latter uses __le32 types.
Using __le32 is preferable, as it removes the ambiguity and potential
misuse of a raw byte array. This also aligns the structure with how the
Linux kernel defines it nowadays, which is the original source of it.
To prepare for future consolidation where one of the data structures can
be removed, this change aligns both definitions and updates all accessors
for dos_partition_t.
Signed-off-by: Javier Martinez Canillas <javierm@redhat.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
There are two different struct definitions for MBR partition table
entries: one in part_dos.h and a nearly identical one in part_efi.h.
To enable future consolidation of these two structures, move part_dos.h
to the main include directory. This makes it accessible from other parts
of the codebase, such as part_efi.h, and is the first step toward removing
the redundant definition.
Signed-off-by: Javier Martinez Canillas <javierm@redhat.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
The size of the memory allocated for the EFI Conformance Profiles Table is
computed with `num_entries' always equal to zero, which is incorrect when
CONFIG_EFI_EBBR_2_1_CONFORMANCE is enabled.
This can be verified by allocating the ECPT memory with malloc() instead of
efi_allocate_pool(), building u-boot with sandbox_defconfig and
CONFIG_VALGRIND=y, and by finally running the following command:
valgrind --suppressions=scripts/u-boot.supp \
./u-boot -T -c 'efidebug tables'
Fix this by using an array of the supported profiles GUIDs instead, which
should also be easier to extend in the future as U-Boot should publish the
GUIDs for all supported EBBR revisions.
Fixes: 6b92c17352 ("efi: Create ECPT table")
Suggested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Vincent Stehlé <vincent.stehle@arm.com>
Cc: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Cc: Tom Rini <trini@konsulko.com>
Cc: Jose Marinho <jose.marinho@arm.com>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
The read_blocks() function from the Block IO protocol is a UEFI function;
make sure to call it from within U-Boot using the EFI_CALL() macro.
To demonstrate the issue on an AArch64 machine, define the DEBUG macro in
include/efi_loader.h and build u-boot with sandbox_defconfig, then download
and uncompress the ACS-DT image [1], and finally execute the following
command:
$ ./u-boot -T -c " \
host bind 0 systemready-dt_acs_live_image.wic; \
setenv loadaddr 0x10000; \
load host 0 \${loadaddr} EFI/BOOT/Shell.efi; \
bootefi \${loadaddr} \${fdtcontroladdr}"
The following assertion should fail:
lib/efi_loader/efi_net.c:858: efi_network_timer_notify: Assertion `__efi_entry_check()' failed.
This happens due to the following EFIAPI functions call chain:
efi_start_image()
efi_disk_read_blocks()
(due to the missing EFI_CALL, entry_count == 2)
efi_network_timer_notify()
Link: https://github.com/ARM-software/arm-systemready/releases/download/v25.12_DT_3.1.1/systemready-dt_acs_live_image.wic.xz [1]
Fixes: ce3dbc5d08 ("efi_loader: add UEFI GPT measurement")
Signed-off-by: Vincent Stehlé <vincent.stehle@arm.com>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
Cc: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Cc: Tom Rini <trini@konsulko.com>
Cc: Masahisa Kojima <kojima.masahisa@socionext.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Acked-by: Masahisa Kojima <kojima.masahisa@socionext.com>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
This pull request updates SoCFPGA platforms with DDR improvements, new
board support, Agilex5 enhancements and general cleanup across the
codebase.
DDR and memory handling
* Add DRAM size checking support for Arria10.
* Widen MEM_TOTAL_CAPACITY mask handling in IOSSM mailbox driver.
* Assign unit address to memory node for improved memory
representation and consistency.
Agilex / Agilex5 updates
* Restore multi-DTB support for NAND boot and fix NAND clock handling.
* Enable SD card UHS mode and eMMC HS200/HS400 mode support on Agilex5.
* Fix DT property naming conventions for Agilex5.
* Exclude AGILEX_L4_SYS_FREE_CLK from clock enable/disable operations
to avoid unintended clock control.
New board support
* Add support for CoreCourse Cyclone V boards:
* AC501
* AC550
Including device trees, QTS configuration, defconfigs and maintainers
entries.
Fixes and cleanup
* Fix GEN5 handoff script path.
* Remove incorrect CONFIG_SPL_LDSCRIPT settings.
* Replace legacy TARGET namespace and perform related cleanup across
SoCFPGA code.
* General Kconfig, build and SoCFPGA maintenance updates.
Overall this pull request improves platform robustness, adds new board
coverage and cleans up legacy configuration usage across the SoCFPGA
U-Boot codebase.
[trini: Change TARGET_SOCFPGA_CYCLONE5 to ARCH_SOCFPGA_CYCLONE5 in the
new platforms this added]
Signed-off-by: Tom Rini <trini@konsulko.com>
Add a test when delay is set to 0 to improve performances
by 20% on ARM based systems
Signed-off-by: Jean-Marie Verdun <verdun@hpe.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
TARGET namespace is for machines / boards / what-have-you that
building U-Boot for. Simply replace from TARGET to ARCH
make things more clear and proper for ALL SoCFPGA.
Signed-off-by: Brian Sune <briansune@gmail.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
# Conflicts:
# drivers/ddr/altera/Makefile
Enable high-speed eMMC modes on Agilex5 SoC development kit for
improved storage performance.
Defconfig changes:
- Enable CONFIG_MMC_HS400_SUPPORT and CONFIG_SPL_MMC_HS400_SUPPORT
Device tree changes:
- Add mmc-hs200-1_8v and mmc-hs400-1_8v capabilities
- Add sdhci-caps-mask to mask SDHCI_CLOCK_V3_BASE_MASK bits
- Add sdhci-caps to set 200MHz base clock and 8-bit bus width
- Add PHY and controller timing configuration for HS200 mode
- Add PHY and controller timing configuration for HS400 mode
Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@altera.com>
Acked-by: Tien Fong Chee <tien.fong.chee@altera.com>
Enable Ultra High Speed (UHS-I) mode support for SD cards on
Agilex5 SoC development kit.
Defconfig changes:
- Enable CONFIG_MMC_UHS_SUPPORT and CONFIG_SPL_MMC_UHS_SUPPORT
Device tree changes:
- Remove no-1-8-v to allow 1.8V signaling for UHS modes
- Add sd-uhs-sdr50 and sd-uhs-sdr104 capabilities
- Add sdhci-caps and sdhci-caps-mask for proper capability reporting
- Add PHY and controller timing configuration
Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@altera.com>
Acked-by: Tien Fong Chee <tien.fong.chee@altera.com>
Replace underscores with hyphens in the PHY timing configuration
property names to follow standard devicetree naming conventions:
- phy-gate-lpbk_ctrl-delay-sd-ds -> phy-gate-lpbk-ctrl-delay-sd-ds
- phy-gate-lpbk_ctrl-delay-sd-hs -> phy-gate-lpbk-ctrl-delay-sd-hs
Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@altera.com>
Acked-by: Tien Fong Chee <tien.fong.chee@altera.com> Best regards, Tien
The previous mask for MEM_TOTAL_CAPACITY_INTF was limited to 8 bits,
which could truncate DDR size values on larger-memory systems.
Update INTF_CAPACITY_GBITS_MASK to 32 bits to correctly represent
the full capacity field according to the hardware specification.
Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com>
Signed-off-by: Chen Huei Lok <chen.huei.lok@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com> Best regards,
AGILEX_L4_SYS_FREE_CLK is a free-running clock with no gate control in
hardware, therefore attempting to enable or disable it is not applicable.
Update the clock driver to explicitly exclude this clock ID from
enable/disable operations by returning -EOPNOTSUPP in bitmask_from_clk_id()
and treating this as a no-op in the socfpga_clk_enable() and
socfpga_clk_disable() functions.
This prevents unnecessary register access for clocks that cannot be gated
and ensures clean handling when the clock is present in the device tree.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
Assign unit address of 0 to memory node following latest Linux convention.
Without this unit address, SPL will not be able to retrieve proper memory
node values set from the device tree.
Update all dts files which includes the common .dtsi to add unit address
as well.
Fixes: e291277689 ("sync socfpga common u-boot dts")
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
Add DRAM size checking compare between size from device tree and actual
hardware.
Trigger hang if DRAM size from device tree is greater than actual hardware.
Display warning message if DRAM size mismatch between device tree and
actual hardware.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com> Best regards,
In v2025.10, the Agilex clock driver was updated to support
clk_enable() and clk_disable() using clock-ID based bitmasks.
However, only AGILEX_NAND_CLK was implemented, while the NAND DT
node still referenced both nand and nand_x clocks.
Since AGILEX_NAND_X_CLK is not defined in the clock driver or the
clock-ID specification, clk_enable() failed during NAND probe.
As a result, the Denali NAND controller never completed
initialization.
Fix this by mapping the NAND X clock to the existing l4_mp clock
bitmask, aligning the DT expectations with the clock driver and
restoring proper NAND controller initialization.
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
These platforms set CONFIG_SPL_LDSCRIPT to a file that doesn't exist,
and in turn were using the default of arch/arm/cpu/armv8/u-boot-spl.lds
instead.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
From v2025.10 onward, Agilex platforms use the upstream Linux device
tree sources instead of local copies.
To continue using a single defconfig while supporting NAND boot,
restore Multi-DTB support and update the DT paths to the upstream
intel directory.
NAND boot is configured to use FDT-1, while other boot flows
continue to use the default device tree.
No functional change is intended for non-NAND boot paths.
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
`dram_init()` is called by R5 SPL and U-Boot, both. It starts by
computing the size of the RAM. In verdin-am62(p), it does so by calling
`get_ram_size()`. This function computes the size of the RAM by writing
over the RAM.
When R5 computes the size of the RAM, it does not update the DT with
this size. As a result, when A53 invokes `dram_init()` again, it has to
compute the size through `get_ram_size()` again.
Commit 13c54cf588 and 0c3a6f748c add firewall over ATF's and OPTEE's
regions. This firewall is added during the R5 SPL stage of boot. So when
A53 attempts to write over RAM in `get_ram_size()`, it writes over the
protected region. Since A53 is a non-secure core, this is blocked by the
firewall.
To fix this, do the following:
* Implement `spl_perform_board_fixups()` function for verdin-am62
and verdin-am62p. Make this function call `fixup_memory_node()`,
which updates the DT.
* Add an if-block in `dram_init()`, to ensure that only R5 is able
to call `get_ram_size()`, and that A53 reads this size from the
DT.
Signed-off-by: Suhaas Joshi <s-joshi@ti.com>
Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com>
In theory, for the same vendor, we should use the same instructions as
the spi-nor-core implementation.
Fixes: 72151ad10f ("mtd: spi-nor-core: Add Cypress manufacturer ID in set_4byte")
Fixes: 5bf3f3dd11 ("mtd: spi-nor: Enable QE bit for ISSI flash")
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
These chips are internally made of two/four dies with linear addressing
capabilities to make it transparent to the user that two/four dies were
used. There is one drawback however, the read status operation is racy
as the status bit only gives the active die status and not the status of
the other die. For commands affecting the two dies, it means if another
command is sent too fast after the first die has returned a valid
status (deviation can be up to 200us), the chip will get corrupted/in an
unstable state.
The solution adopted here is to iterate manually over all internal
dies (which takes about 30us per die) until all are ready. This approach
will always be faster than a blind delay which represents the maximum
deviation, while also being totally safe.
A flash-specific hook for the status register read had to be
implemented. Testing with the flash_speed benchmark in Linux shown no
difference with the existing performances (using the regular status read
core function).
As the presence of multiple dies is not filled in these chips SFDP
tables (the table containing the crucial information is optional), we
need to manually wire the hook.
This change is adapted from Linux.
Link: https://lore.kernel.org/all/20250110-winbond-6-12-rc1-nor-volatile-bit-v3-1-735363f8cc7d@bootlin.com/
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Invert the conditional when to exit, and fall back to common code
in the default case. This should have no functional impact on either
code path.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
The spi_slave_of_to_plat() is called from one place, spi_child_post_bind().
Squash it into the later and remove the public declaration, make this
function local static. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Some Winbond Flash chips share the same device ID. Names are not that
important for the SPI Flash, hence we don't need these duplicate ID
definitions. And the Flash size of w25q512jv is actually wrong. Clean
them up to keep the source file tidy.
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Change the Kconfig from a "choice" to a conditional block, allowing
multiple FWU metadata storage drivers to be selected simultaneously
instead of being mutually exclusive.
This enables systems with FWU metadata on different storage types
(e.g., both GPT-partitioned block devices and MTD devices) to have
both drivers compiled in. The board can then select the appropriate
driver at runtime based on the devicetree description.
The change converts FWU_MDATA to a menuconfig and replaces the
"choice/endchoice" block with "if FWU_MDATA/endif", making
FWU_MDATA_GPT_BLK default to 'y' for backward compatibility.
Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
Acked-by: Sughosh Ganu <sughosh.ganu@arm.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Add a GPIO controller driver that provides configurable delays when
setting GPIO output values. This is useful for hardware that requires
specific timing delays during power sequencing or GPIO state changes.
The driver wraps underlying GPIO controllers and adds programmable
ramp-up and ramp-down delays specified in microseconds through the
device tree. Each GPIO can have independent delay timings.
Device tree binding matches Linux.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/575998efc6ba0e405640789cf8d05f0b633f496e.1770105146.git.michal.simek@amd.com
Although the pinctrl pm requests are implemented in the PMU firmware,
PM_QUERY_DATA is actually implemented in ATF. In SPL (or when running in
EL3), ATF is not yet running, so we need to implement this API
ourselves. Do the bare minimum, allowing SPL to enumerate functions, but
don't bother with groups. Groups take up a lot of space, and can be
emulated with pins. For example, a node like
display-port {
mux {
groups = "dpaux0_1";
function = "dpaux0";
};
};
can be replaced by
display-port {
mux {
pins = "MIO34", "MIO35", "MIO36", "MIO37";
function = "dpaux0";
};
};
While this isn't backwards-compatible with existing devicetrees, it's
more than enough for SPL where we may only need to mux one or two pins.
Add SPL_PINCTRL_ZYNQMP to ensure there's no SPL size growth when pinctrl
is enabled in U-Boot but isn't necessary for SPL. The only config this
would affect is Kria, but SPL_PINCTRL_GENERIC is disabled so
SPL_PINCTRL_ZYNQMP is not selected.
Signed-off-by: Sean Anderson <sean.anderson@linux.dev>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20260129184011.3932790-1-sean.anderson@linux.dev
Move DRAM bank detection from fdtdec to custom implementation to
ensure memory banks are populated before get_page_table_size() is
called during MMU initialization.
The current fdtdec-based approach populates gd->bd->bi_dram[] too
late in the boot sequence, causing get_page_table_size() to be
called with unpopulated DRAM information. This prevents dynamic
page table sizing based on actual memory configuration.
Parse /memory nodes in dram_init() to fill versal2_mem_map[]
early enough for MMU setup. Supports up to
CONFIG_NR_DRAM_BANKS (36) non-contiguous banks with high memory
regions (>4GB) and use __weak get_page_table_size implementation
to estimate page table size based on the populated DRAM banks.
Signed-off-by: Pranav Sanwal <pranav.sanwal@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20260129120021.1328653-3-pranav.sanwal@amd.com
Add get_next_memory_node() function declaration to fdtdec.h to support
iterating through multiple memory nodes in device tree. This function
is used to enumerate memory banks when the system has non-contiguous
or multiple memory regions defined with device_type = "memory".
The function implementation already exists in lib/fdtdec.c (lines
1298-1305) but was missing the public declaration in the header file.
This patch adds the declaration and includes dm/ofnode_decl.h for the
ofnode type definition.
This is needed for platforms that require early memory enumeration
before standard fdtdec_setup_memory_banksize() is called, particularly
for dynamic MMU page table size calculation based on actual DRAM
configuration.
Signed-off-by: Pranav Sanwal <pranav.sanwal@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20260129120021.1328653-2-pranav.sanwal@amd.com
Add support for reading RTC clock from device tree using clock
framework also update the default calibration value to 0x7FFF
as per RTC specifications.
Falls back to 'calibration' property if clock unavailable, and uses
default calibration if neither is present. Only writes calibration when
hardware register reads zero.
The calibration write previously in zynqmp_rtc_set() has been moved to
the probe function. The earlier implementation wrote calibration on
every time update to clear the tick counter, but since calibration is
now dynamically configured from clock framework or device tree during probe,
it only requires one-time initialization. This avoids repeated tick
counter resets and unnecessary overhead.
Signed-off-by: Pranav Tilak <pranav.vinaytilak@amd.com>
Reviewed-by: Tomas Melin <tomas.melin@vaisala.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20260120110056.3640303-1-pranav.vinaytilak@amd.com
`dram_init()` is called by R5 SPL and U-Boot, both. It starts by
computing the size of the RAM. In verdin-am62(p), it does so by calling
`get_ram_size()`. This function computes the size of the RAM by writing
over the RAM.
When R5 computes the size of the RAM, it does not update the DT with
this size. As a result, when A53 invokes `dram_init()` again, it has to
compute the size through `get_ram_size()` again.
Commit 13c54cf588 and 0c3a6f748c add firewall over ATF's and OPTEE's
regions. This firewall is added during the R5 SPL stage of boot. So when
A53 attempts to write over RAM in `get_ram_size()`, it writes over the
protected region. Since A53 is a non-secure core, this is blocked by the
firewall.
To fix this, do the following:
* Implement `spl_perform_board_fixups()` function for verdin-am62
and verdin-am62p. Make this function call `fixup_memory_node()`,
which updates the DT.
* Add an if-block in `dram_init()`, to ensure that only R5 is able
to call `get_ram_size()`, and that A53 reads this size from the
DT.
Signed-off-by: Suhaas Joshi <s-joshi@ti.com>
Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com>
