Commit Graph

105784 Commits

Author SHA1 Message Date
Padmarao Begari
6b743f66d8 xilinx: mbv: Update defconfigs as per memory map
U-Boot SPL should be executed from LMB BRAM, where its text
and data sections are located, while the heap and stack are
allocated in DDR memory.

Because on the MB-V platform, after power-up, reset, or FPGA
load, execution begins from LMB BRAM at address 0x0. Therefore,
the SPL binary must be placed in BRAM to support this boot flow.
Without it, the system can only be booted via JTAG.

A 64KB LMB BRAM region is allocated for U-Boot SPL, starting at
address 0x0. This region contains the SPL's text, data, and device
tree blob (DTB) sections. The .bss section is placed separately at
address 0xF000.

	_________________0xFFFF
	|BSS            |
	|_______________|0xF000
	|DTB            |
	|_______________|
	|Data           |
	|_______________|
	|Text           |
	|_______________|0x0000

A 2MB region of DDR memory is allocated for U-Boot SPL, with the
heap starting at address 0x80000000 and the stack at 0x80200000.

	_________________0xBFFFFFFF
	|Full U-Boot    |
	|_______________|0x80400000
	|Load FIT Image |
	|_______________|0x80200000
	|Stack          |
	|_______________|
	|Heap           |
	|_______________|0x80000000

Since LMB BRAM is a limited resource with a practical size
constraint of 64KB - it cannot accommodate all runtime data.
Therefore, the heap and stack are placed at the beginning of
DDR memory to ensure sufficient space for SPL execution.

Signed-off-by: Padmarao Begari <padmarao.begari@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/ed4a3618875869287b87b6b57fd55f4c6a36f046.1765206211.git.michal.simek@amd.com
2025-12-19 08:25:27 +01:00
Padmarao Begari
c8898f12d3 board: xilinx: add SPL boot device support
Add board_boot_order() function and remove spl_boot_device()
function because it is called from weak board_boot_order().

Add support to U-Boot SPL for booting from RAM or SPI, as
configured in defconfig.

Signed-off-by: Padmarao Begari <padmarao.begari@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/a1f26a9392128309a1affed28b14809845714c21.1764747417.git.michal.simek@amd.com
2025-12-19 08:25:27 +01:00
Padmarao Begari
3af56e2e55 xilinx: mbv: Remove debug UART support
Remove debug UART support as it is intended for development and
debugging purposes, and should not be enabled in production builds.

Signed-off-by: Padmarao Begari <padmarao.begari@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/6eaad47c30990ffd230d21c7158bc7234cda1752.1764747346.git.michal.simek@amd.com
2025-12-19 08:25:27 +01:00
Padmarao Begari
794cbdb08c xilinx: mbv: Disable SPL GZIP
GZIP compression is disabled to reduce the SPL size by 12KB.

Signed-off-by: Padmarao Begari <padmarao.begari@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/339520b249a3c69a36faf5432cbd581459563e32.1764747291.git.michal.simek@amd.com
2025-12-19 08:25:27 +01:00
Michal Simek
e94fe1c16d xilinx: mbv32: Disable floating point
MB-V 32 has optional single precision FPU (64bit has single and double
precision FPU) but there is no use and reason to enable FPU by default
that's why disable it.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/2c043ed05643fee200a79eb08bfd5c0041663bd2.1764746430.git.michal.simek@amd.com
2025-12-19 08:25:27 +01:00
Padmarao Begari
38e3f9658e i2c: cdns: Add timeout for RXDV status bit polling
Add a timeout mechanism when waiting for the RXDV (Receive Data
Valid) status bit to be set before reading data from the FIFO.
This prevents infinite polling loops that could occur if the
hardware doesn't respond as expected.

The timeout is set to 1000ms (CDNS_I2C_RXDV_TIMEOUT_MS) and uses
the wait_for_bit_le32() function to poll the status register. If
the timeout expires, an error code is returned.

Signed-off-by: Padmarao Begari <padmarao.begari@amd.com>
Reviewed-by: Heiko Schocher <hs@nabladev.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/ba53d57c179f3390b32bc6094f3ffb5f4cde931e.1764169953.git.michal.simek@amd.com
2025-12-19 08:25:27 +01:00
Michal Simek
e9ce819f93 xilinx: versal: Get rid of xlnx-versal-power.h from bindings
Remove xlnx-versal-power.h dt binding header because they should be moved
directly to folder where DTs are. In the Linux kernel this shift already
started by moving xlnx-zynqmp-clk.h to arch/arm64/boot/dts/xilinx/ folder.

U-Boot is using only one PD_DEV_OSPI constact which is moved to
zynqmp_firmware.h header. But handling around it should be fixed anyway
because no driver should be calling xilinx_pm_request() directly.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/a0f0154ef89929517c3217efe025e8021a910b90.1764233963.git.michal.simek@amd.com
2025-12-19 08:25:27 +01:00
Michal Simek
29427fdf71 arm64: versal2: Read and show multiboot value
SOC can boot from different boot medias and also different offsets that's
why by default show multiboot value to be aware which image system is
booting out of. It is especially useful for systems with A/B update
enabled.
Also limit zynqmp_pm_get_pmc_multi_boot_reg() usage only for Versal and
Versal Gen 2.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/fd7564ce2f51d965c273e939e98de01beb92e6f5.1764232124.git.michal.simek@amd.com
2025-12-19 08:25:27 +01:00
Venkatesh Yadav Abbarapu
b6391d1d9b cadence_qspi: Update the delays for flash reset
Updating the delays for flash reset in the mini u-boot case.
These experimental delay values by looking at different flash device
vendors datasheets.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/3fd0641a164a4d628fdf28a94771829f3bf9cb0c.1764181308.git.michal.simek@amd.com
2025-12-19 08:25:27 +01:00
Michal Simek
857a3b49c3 cadence_qspi: Remove duplicated return
The commit 6d234a79e9 ("cadence_qspi: Refactor the flash reset
functionality") introduced two returns in cadence_spi_probe() that's why
remove it.

Fixes: 6d234a79e9 ("cadence_qspi: Refactor the flash reset functionality")
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/5f6d6db9c301daf10ddb707a9031f1a467d6ebf1.1764180937.git.michal.simek@amd.com
2025-12-19 08:25:27 +01:00
Venkatesh Yadav Abbarapu
b869d31797 arm64: versal2: Enable reset and poweroff via sysreset framework
reset and poweroff are called via hooks in psci driver which is going
around sysreset framework that's why enable sysreset drivers and do
reset and poweroff via this framework.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/a0b13b17fbf99fd16341b68b649ec08ef2b3536a.1764170621.git.michal.simek@amd.com
2025-12-19 08:25:27 +01:00
Venkatesh Yadav Abbarapu
a4b96effec arm64: versal2: Update the text base and dtb address
Update the TEXT_BASE and DTB address as per the new memory map.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/6c6eeab25c8bc8739127fb40e1a941920d04fc77.1764170621.git.michal.simek@amd.com
2025-12-19 08:25:27 +01:00
Michal Simek
9d5b4f63be arm64: versal2: Enable USB5744 usb hub
USB hub is available on the first evaluation board called vek385.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/4cd72e28bc0e2a9720fe5481dcab2e923d708b34.1764170621.git.michal.simek@amd.com
2025-12-19 08:25:27 +01:00
Michal Simek
358b5e6201 xilinx: amd: Enable the PCA9541 I2C Bus arbiter
Enable the new PCA9541 i2c bus arbiter on AMD/Xilinx SOCs by default.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/edfb7e7a6e800484d3ac3bf45a4f83adfcdd1754.1764170621.git.michal.simek@amd.com
2025-12-19 08:25:27 +01:00
Venkatesh Yadav Abbarapu
16eaf907d5 common: memtop: Update the MEM_RGN_COUNT macro to 64
Crashes are occurring due to the number of reserved memory regions
exceeding the current maximum limit of 16. It is recommended to
increase the supported number of memory regions to 64, as newer
platforms may utilize more reserved regions.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/d9f73d26af832e19dfd79a4b7bfcf09c498a4873.1764169780.git.michal.simek@amd.com
2025-12-19 08:25:27 +01:00
Padmarao Begari
66a9a431ee board: xilinx: Retry FRU EEPROM read on timeout
Wrap the dm_i2c_read() call is used for FRU EEPROM reads in a
retry loop, attempting up to EEPROM_FRU_READ_RETRY times if a
-ETIMEDOUT error is returned. The loop exits immediately on
success or any error other than -ETIMEDOUT. This improves
robustness against transient I2C timeouts during FRU detection
and decoding.

Signed-off-by: Padmarao Begari <padmarao.begari@amd.com>
Reviewed-by: Matthias Brugger <mbrugger@suse.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/9556d204c351d2dc40176a31dab11f789fd1cc7f.1763542221.git.michal.simek@amd.com
2025-12-19 08:25:27 +01:00
Michal Simek
b2a8ac7820 arm64: xilinx: Remove unnecessary #address/size-cells
GEMs are using mdio node that's why don't need cells description in the
node.
SPIs should be using partitions subnode that's why don't need to have
cells description in the node
Also no need to specify cells in DT overlay root node when there is no
child which needs it.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/7612a3817480f4089aea3e14cca07d585f8fddb5.1763551956.git.michal.simek@amd.com
2025-12-19 08:25:27 +01:00
Michal Simek
55e097ec88 spi: cadence: Remove cdns,is-dma DT property
cdns,is-dma is not documented property that's why setup CQSPI_DMA_MODE
quirk to enable DMA mode based on compatible string. And also change
compatible string for mini configurations also with recording compatible
string in the driver (Compatible string is already the part of existing DT
binding).

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/f109829793900e57558d98ed22caf80c1a72b232.1762787994.git.michal.simek@amd.com
2025-12-19 08:25:27 +01:00
Michal Simek
7c1e037048 clk: versal: Enable clock driver for Versal Gen 2
Versal Gen 2 is using enhancement SMC format but in near future SCMI client
should be used. This patch is just bridging this gap till SCMI server is
fully tested.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/e83c665408d1453a464dd02cd2a25bb0ed267131.1762788250.git.michal.simek@amd.com
2025-12-19 08:25:26 +01:00
Michal Simek
a078ebb86f firmware: xilinx: Add support for enhancement SMC format
Versal Gen 2 is using different SMC format that's why firmware and clock
drivers needs to be align with it.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/16bdee56fd75113c6d531bae7a8a34900b10280d.1762788250.git.michal.simek@amd.com
2025-12-19 08:25:26 +01:00
Michal Simek
ac9494e96b clk: versal: Cleanup driver
Remove unneeded debug messages, parenthesis and fix error message.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/5b6fbcff1025415adc97e3e17eeb18863df4383e.1762778011.git.michal.simek@amd.com
2025-12-19 08:25:26 +01:00
Michal Simek
2b7255cfa0 clk: versal: Add support for CLK_AUTO_ID
When CLK_AUTO_ID is enabled 8 higher bits of clk->id is unique clock
identifier in clk uclass that's why it is necessary to mask lower bits
which are clock ID.
Also check that ID not bigger then maximum supported clock.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/647f1d2c7d274c1106558a655386ef92e0baf2c8.1762778011.git.michal.simek@amd.com
2025-12-19 08:25:26 +01:00
Michal Simek
16f0332b18 clk: versal: Use __data macro for moving variable to data section
The commit 1b267fe182 ("firmware: xilinx: Prepare code for new SMC
firmware format") introduce new __data macro that's why use it in clock
driver too.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/eac8d0ab60a018d6c59aa28c49691839a3eec174.1762511327.git.michal.simek@amd.com
2025-12-19 08:25:26 +01:00
Padmarao Begari
24308102cd board: xilinx: Update ESRT after copying GUID
The EFI System Resource Table (ESRT) is updated after the firmware
image GUID is copied to the fw_images structure. This ensures that
the ESRT accurately reflects the current firmware resources.

Signed-off-by: Padmarao Begari <padmarao.begari@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20251104125725.1628068-1-padmarao.begari@amd.com
2025-12-19 08:25:26 +01:00
Tom Rini
d24f4ae654 test/py, buildman: Update filelock package version
The GitHub dependabot tool has reported a "medium" priority bug
CVE-2025-68146, with this package. Update to the patched version.

Reported-by: GitHub dependabot
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-12-18 10:28:10 -06:00
Quentin Schulz
24ab2b9684 doc: pytest: fix typo in multiple config options example for buildconfigspec
The option should be 'net_lwip' and not 'net lwip' (see all usage of it
in the test code base).

Fixes: 2bac578c5a ("test: allow multiple config options in buildconfigspec")
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
2025-12-18 10:26:35 -06:00
Marek Vasut
2333d446b7 cmd: nvedit: Validate argument count before use
Avoid NULL pointer dereference in case 'env select' is invoked
without parameters, check the arg count and make sure it is at
least 2, otherwise print usage.

The crash is easy to trigger e.g. in sandbox:
$ ./u-boot -Tc "env select"

Fixes: a97d22ebba ("cmd: env: add env select command")
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Tested-by: Vincent Stehlé <vincent.stehle@arm.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-12-18 10:26:22 -06:00
Anshul Dalal
d865f2f016 doc: board: ti: fix alt name for tispl.bin in DFU mode
The alt name for tispl binary is "tispl.bin" and not "tispl", this patch
fixes the documentation to the correct alt name.

Fixes: def64b4937 ("doc: board: Add document for DFU boot on am62x SoCs")
Fixes: 3633fdbb6b ("ti: add support for AM6254atl SiP")

Signed-off-by: Anshul Dalal <anshuld@ti.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
2025-12-18 10:25:44 -06:00
Tom Rini
8d210fa37f Merge tag 'net-20251218' of https://source.denx.de/u-boot/custodians/u-boot-net
Pull request net-20251218.

net-lwip:
- Avoid NULL dereference in _set_cacert()
- Fix filename handling in TFTP
2025-12-18 10:24:39 -06:00
Heinrich Schuchardt
a8a81af848 cmd: lwip/wget: avoid NULL dereference in _set_cacert()
Running `wget cacert builtin` leads to a crash in _set_cacert():

    Unhandled exception: Load access fault

Function _set_cacert() dereferences variable wget_info.
We must initialize it before executing the cacert sub-command.

Fixes: d3761a31ef ("lwip: split net/lwip/wget.c")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-12-18 16:27:15 +01:00
Andrew Goodbody
8910efa71b net: lwip: tftp: Fix filename handling
The code to choose the filename to use does not cope with no name set at
all. Firstly the test for a name in net_boot_file_name tests the pointer
rather than the string it points to. Secondly the cleanup on exit in
this case attempts to free a global variable. Fix both issues.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
2025-12-18 16:27:15 +01:00
Tom Rini
930eff5416 Merge tag 'u-boot-socfpga-next-20251217' of https://source.denx.de/u-boot/custodians/u-boot-socfpga into next
This pull request brings together a set of fixes and enhancements across
the SoCFPGA platform family, with a focus on MMC/SPL robustness, EFI
boot enablement, and Agilex5 SD/eMMC support.

CI: https://source.denx.de/u-boot/custodians/u-boot-socfpga/-/pipelines/28776

Highlights:

  *
    SPL / MMC:
      o
        Fix Kconfig handling for
        SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
      o
        Correct raw sector calculations and respect explicit sector values
        when loading U-Boot from MMC in SPL
      o
        Adjust raw MMC loading logic for SoCFPGA platforms
  *
    EFI boot:
      o
        Permit EFI booting on SoCFPGA platforms
      o
        Disable mkeficapsule tool build for Arria 10 where unsupported
  *
    Agilex5:
      o
        Upgrade SDHCI controller from SD4HC to SD6HC
      o
        Enable MMC and Cadence SDHCI support in defconfig
      o
        Add dedicated eMMC device tree and defconfig for Agilex5 SoCDK
      o
        Revert incorrect GPIO configuration for SDIO_SEL
      o
        Refine U-Boot DT handling for SD and eMMC boot variants
  *
    SPI:
      o
        Allow disabling the DesignWare SPI driver in SPL via Kconfig
  *
    Board / configuration fixes:
      o
        Enable random MAC address generation for Cyclone V
      o
        Fix DE0-Nano-SoC boot configuration
      o
        Remove obsolete or conflicting options from multiple legacy
        SoCFPGA defconfigs
2025-12-18 08:06:10 -06:00
Jan Kiszka
6f419247ba configs: socfpga: Permit EFI booting
Commit f369e1564c turned those off because the SPL size grew too
large. It also argued that those boards would never support EFI booting.
The former is correct, therefore keep CONFIG_SPL_EFI_PARTITION off.
CONFIG_SPL_ISO_PARTITION is default off. What is not correct is that
those boards are limited to legacy boot - you just need a hybrid
partition table to make both the bootrom and UEFI happy.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-12-17 18:50:33 +08:00
Jan Kiszka
217eb9b119 configs: socfpga: Fix de0_nano_soc boot
By default, the de0_nano_soc used raw sectors, but the address became
invalid due the raw-mode refactorings. With loading via partition type
fixed, we can switch to that mode which is in line with what the ROM
loader does.

Fixes: 2a00d73d08 ("spl: mmc: Try to clean up raw-mode options")
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-12-17 18:50:32 +08:00
Jan Kiszka
1cf1b504f4 arch: arm: mach-socfpga: Adjust a raw sectors for MMC loading of U-Boot from SPL
If U-Boot is located on MMC, SPL and U-Boot proper are glued together.
More precisely, SPL is stored 4 times. Take this and its padding into
account and adjust sector number via board_spl_mmc_get_uboot_raw_sector.
This allows loading from a partition, without the need to hard-code the
offset via SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-12-17 18:50:32 +08:00
Jan Kiszka
62584916c9 spl: mmc: Respect sector value passed to mmc_load_image_raw_partition
This function and the sector parameter evolved over the time. By now,
sector is influenced by spl_mmc_get_uboot_raw_sector which allows to
adjust the read sector with an offset that U-Boot proper may have inside
the partition. That used to work by chance if both
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR and
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION were enabled. Since
2a00d73d08 they are a choice, and we need to drop the condition to
maintain this feature.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-12-17 18:50:32 +08:00
Jan Kiszka
94d0c1d3ed spl: mmc: Account for SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE being a choice
Add SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE as condition where so
far SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION was enough - though often
by chance as both options were enabled.

Reorder the #ifdef blocks at this chance to follow the order in the
Kconfig menu.

Fixes: 2a00d73d08 ("spl: mmc: Try to clean up raw-mode options")
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-12-17 18:50:32 +08:00
Jan Kiszka
a47b1e165e spl: Kconfig: Add missing SPL_LOAD_BLOCK for SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
We need to explicitly select SPL_LOAD_BLOCK when USE_PARTITION_TYPE is
enabled, just like the other choices do.

Fixes: 2a00d73d08 ("spl: mmc: Try to clean up raw-mode options")
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-12-17 18:50:31 +08:00
Ralph Siemsen
136d750c2e spi: designware: Allow disabling designware driver in SPL
To reduce SPL size, make it possible to exclude designware driver,
while keeping it enabled in the main u-boot.

Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
Reviewed-by: Sean Anderson <sean.anderson@seco.com>
2025-12-17 18:50:31 +08:00
Alif Zakuan Yuslaimi
26eb2cda39 configs: arria10: Disable mkeficapsule tool build
mkeficapsule tool will be built by default if EFI_LOADER is set due to
commit b7a625b1ce ("tools: Build mkeficapsule tool by default if
EFI_LOADER is set").

This will cause compilation error on all our SoCFPGA devices, hence we will
be disabling this config as we do not utilize this tool.

Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-12-17 18:50:31 +08:00
Tanmay Kathpalia
ed7725c25e arm: dts: socfpga: agilex5: Add dedicated eMMC device tree support
Add dedicated device tree support for eMMC configuration on the Agilex5
SoCDK board, providing an alternative to the default SD card setup.

Changes to socfpga_agilex5.dtsi:
-
- Configure always-on regulator for stable eMMC operation

New device tree files:
- socfpga_agilex5_socdk_emmc.dts: Main eMMC device tree configuration
  * Configure for eMMC operation (no-sd, no-sdio, non-removable)
  * Set 8-bit bus width and high speed capability
  * Add timing parameters for legacy and SDR modes
  * Configure voltage supplies for eMMC power and I/O
  * Add fixed 1.8V regulator for eMMC I/O voltage supply

- socfpga_agilex5_socdk_emmc-u-boot.dtsi: U-Boot specific additions
  * Include common Agilex5 U-Boot configurations
  * Set SPL boot order with eMMC support
  * Enable necessary peripherals for boot-time operation

Configuration files:
- configs/socfpga_agilex5_emmc_defconfig: eMMC-specific configuration
  * Inherit from base Agilex5 configuration
  * Disable GPIO regulator support (not needed for fixed eMMC setup)
  * Set eMMC-specific device tree

Build system integration:
- Add socfpga_agilex5_socdk_emmc.dtb target to Makefile

Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-12-17 18:49:48 +08:00
Tanmay Kathpalia
77387f05c0 configs: socfpga_agilex5: Enable MMC and Cadence SDHCI support
Enable MMC support with Cadence SDHCI controller for both SPL and
U-Boot proper on Agilex5 platform to support SD card operations in
legacy and high speed timing modes.

MMC controller configuration:
- Enable MMC subsystem (CONFIG_MMC=y, CONFIG_DM_MMC=y)
- Add Cadence SDHCI controller support (CONFIG_MMC_SDHCI_CADENCE=y)
- Enable SDHCI with ADMA support for better performance
- Add MMC command support for user interaction

SPL configuration:
- Enable MMC support in SPL (CONFIG_SPL_DM_MMC=y)
- Add SDHCI ADMA support in SPL (CONFIG_SPL_MMC_SDHCI_ADMA=y)
- Enable GPIO support in SPL (CONFIG_SPL_DWAPB_GPIO=y)

Voltage regulator support:
- Add device model regulator framework (CONFIG_DM_REGULATOR=y)
- Enable fixed voltage regulator support for card power
- Add GPIO-controlled regulator for I/O voltage switching
- Include regulator support in SPL for early initialization

These changes enable SD card functionality with legacy and high speed
timing modes, providing proper voltage regulation and GPIO control
for the Agilex5 SoCDK platform.

Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-12-17 16:15:31 +08:00
Tanmay Kathpalia
eb36736730 arm: dts: socfpga: agilex5: Upgrade SDHCI controller from SD4HC to SD6HC
Upgrade the SDHCI Cadence controller from SD4HC to SD6HC for Agilex5
platform to support the newer controller version with enhanced features.

Key changes:
- Remove combophy0 node and associated references as SD6HC doesn't require
  separate PHY configuration node
- Upgrade MMC controller compatible from "cdns,sd4hc" to "cdns,sd6hc"
- Add Agilex5-specific compatible string "altr,agilex5-sd6hc" for
  platform-specific optimizations

Hardware configuration updates:
- Add voltage regulator support:
  * sd_emmc_power: Fixed 3.3V regulator for card power supply
  * sd_io_1v8_reg: GPIO-controlled regulator for 1.8V/3.3V I/O switching
- Configure proper reset control with named resets including combophy
  reset
- Add GPIO control via portb pin 3 for voltage switching

SD card operation:
- Configure for SD card specific operation (no-mmc, cap-sd-highspeed)
- Set maximum frequency to 200MHz
- Configure timing parameters for SD modes:
  * Default Speed (DS) and UHS-I SDR12 mode timing:
  * High Speed and UHS-I SDR25 mode timing:
- Add PHY timing delays for optimal signal integrity

Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-12-17 16:15:31 +08:00
Tanmay Kathpalia
029e6f250c Revert "arch: arm: dts: agilex5: Set SDIO_SEL GPIO pin as output"
Remove GPIO hog configuration for SDIO_SEL pin as it is now handled
through the voltage regulator framework for SD ultra high speed mode
support. The GPIO pin 3 on portb controller is used to control the
level shifter for SD card I/O voltage switching.

The regulator-based approach provides proper voltage switching control
for UHS-I modes (SDR50, SDR104) while maintaining compatibility with
the MMC subsystem's voltage switching protocols.

This reverts commit b0dbc9fcb7.

Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-12-17 16:15:31 +08:00
Alif Zakuan Yuslaimi
85a3ee15e0 configs: cyclone5: Enable random MAC address
Enable CONFIG_NET_RANDOM_ETHADDR to allow U-Boot to assign a random MAC
address during Ethernet initialization when a valid MAC is not programmed
in hardware.

This avoids network initialization failures and MAC address conflicts,
especially on boards used for development or shipped without a
factory-programmed MAC.

Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-12-17 16:15:31 +08:00
Tom Rini
a333d9e59f Merge patch series "fit: print conf node compatibles + use property string constants"
Quentin Schulz <foss+uboot@0leil.net> says:

This does a bit of "cleanup" by reusing constants for some FIT
properties instead of having the same string in multiple places.

Additionally, this adds a new constant for the compatible property in
FIT configuration nodes[1] which is useful for FIT images with multiple
FIT configuration nodes to support multiple devices in the same blob.
U-Boot will try to figure out which node to select based on that
compatible[2].

However, if this property is missing (and the first blob in the fdt
property of the configuration node is uncompressed), the compatible from
the root node of the associated kernel FDT will be used for the
autoselection mechanism. For now, I only print the property if it
exists, but maybe it'd make sense to expose the fallback one if it's
missing. I guess we can implement that later on if desired.

[1] https://fitspec.osfw.foundation/#optional-properties compatible paragraph
[2] https://fitspec.osfw.foundation/#select-a-configuration-to-boot

Link: https://lore.kernel.org/r/20251203-fit-compat-v2-0-0fea56f23809@cherry.de
2025-12-16 11:40:54 -06:00
Quentin Schulz
6c7d3ba292 boot/fit: print all configuration node compatibles
Fit conf node may have a compatible property[1] which stores the
compatible of the first blob in the fdt property of the node. This can
be used to automatically select the proper conf node based on the
compatible from the running U-Boot (matching the former's compatible
with the latter)[2].

This brings the ability to mkimage/dumpimage to print the compatibles of
the configuration node(s). U-Boot CLI commands such as iminfo also see
this addition to their output.

[1] https://fitspec.osfw.foundation/#optional-properties compatible paragraph
[2] https://fitspec.osfw.foundation/#select-a-configuration-to-boot

Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
2025-12-16 11:39:38 -06:00
Quentin Schulz
3059eb0c27 boot/fit: declare (and use) new constant for conf's compatible prop
Fit conf node may have a compatible property[1] which stores the root
compatible of the first blob in the fdt property of the node. This can
be used to automatically select the proper conf node based on the
compatible from the running U-Boot (matching the former's compatible
with the latter)[2].

This adds (and uses) this constant for FIT node parsing.

Note that this property may also appear in fpga image nodes[3] but that
isn't done in this commit.

[1] https://fitspec.osfw.foundation/#optional-properties compatible paragraph
[2] https://fitspec.osfw.foundation/#select-a-configuration-to-boot
[3] https://fitspec.osfw.foundation/#images-node 2.3.2 Conditionally mandatory property

Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
2025-12-16 11:39:38 -06:00
Quentin Schulz
883359e152 lib: rsa: use FIT_ALGO_PROP constant instead of "algo" in FIT
Some FIT image properties have their string represented in
include/image.h via constants. FIT_ALGO_PROP does exist and would fit the
bill so let's use it instead of using a hardcoded string.

Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
2025-12-16 11:39:38 -06:00
Quentin Schulz
634dcda259 boot/fit: use constants for property strings
Some properties have their string represented in include/image.h via
constants, so let's use those constants instead of using a hardcoded
string.

Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
2025-12-16 11:39:38 -06:00