Commit Graph

101967 Commits

Author SHA1 Message Date
Junhui Liu
94a1f8fe47 usb: dwc2: Fix incorrect ULPI_UTMI_SEL bit setting
The ULPI_UTMI_SEL bit in the DWC2 driver was set incorrectly. According
to the datasheet [1], this bit should be set to 0 for UTMI interface and 1
for ULPI interface. The existing code had this logic reversed,
causing the interface selection to be incorrect.

This commit corrects the ULPI_UTMI_SEL bit setting to match the
datasheet's description. Referencing the kernel's code [2] also confirms
this fix.

[1] https://rockchip.fr/RK312X%20TRM/chapter-26-usb-otg-2-0.pdf#page=30
[2] https://github.com/torvalds/linux/blob/v6.13-rc3/drivers/usb/dwc2/core.c#L1106

Reviewed-by: Marek Vasut <marex@denx.de>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
Link: https://lore.kernel.org/r/20250110-dwc2-dev-v4-2-987f4fd6f8b2@pigmoral.tech
Signed-off-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
2025-06-02 09:57:25 +02:00
Kongyang Liu
14f9041309 usb: dwc2: Extract register definitions to common header file
The same registers are accessed in both the otg and gatet drivers of
dwc2, and these registers are repeatedly defined in these two parts.
Extract register definitions into a common header file to reduce
redundancy and make the code more maintainable.

Signed-off-by: Kongyang Liu <seashell11234455@gmail.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
Link: https://lore.kernel.org/r/20250110-dwc2-dev-v4-1-987f4fd6f8b2@pigmoral.tech
Signed-off-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
2025-06-02 09:57:25 +02:00
Martin Kaistra
6759bd73e9 net: gem: ignore tx_clk if MII is used
If the MII interface is used, the PHY is the clock master, thus don't
set the clock rate. On Zynq-7000, this will prevent the following
error:
  zynq_gem ethernet@e000b000: failed to set tx clock rate 25000000

Signed-off-by: Martin Kaistra <martin.kaistra@linutronix.de>
Link: https://lore.kernel.org/r/20250415150400.136723-1-martin.kaistra@linutronix.de
Signed-off-by: Michal Simek <michal.simek@amd.com>
2025-06-02 09:13:49 +02:00
Frantisek Bohacek
90df44fb4f phy: zynqmp: Fix sgmii clk ctrl GTR lane bit shift
The bitshift in GEM_CLK_CTRL register is five bits, not two. There are
four bits for each GEM, and one bit reserved in between.

This has caused that using more than one GEM is impossible,
additionally corrupting the GEM0's configuration, leaving GEM0
unusable as well (ie. if GEM0 and GEM1 are used, GEM1 configuration is
going to write to GEM0's registers wrong value, leaving GEM0 unusable)

Signed-off-by: Frantisek Bohacek <rutherther@ditigal.xyz>
Link: https://lore.kernel.org/r/20250522060703.4863-1-rutherther@ditigal.xyz
Signed-off-by: Michal Simek <michal.simek@amd.com>
2025-06-02 09:13:48 +02:00
Naresh Kumar Ravulapalli
85f181b194 drivers: fpga: intel_sdm_mb: Flush cache before FPGA configuration
FPGA configuration encounters failure when the cache is not flushed.
Add cache flushing to the memory region that holds the FPGA
configuration bitstream.

Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com>
Link: https://lore.kernel.org/r/20250506012851.30039-1-nareshkumar.ravulapalli@altera.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2025-06-02 09:13:48 +02:00
Venkatesh Yadav Abbarapu
967eebcd85 pci: zynqmp: Fix the pcireg base
The pcireg base is not assigned to any address, reading the
pcireg base with PS_LINKUP_OFFSET which is incorrect and
giving random values. So update the pcireg base from
devicetree so that we can read the valid PCIE link status
and PHY ready status.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Link: https://lore.kernel.org/r/20250516092314.939424-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2025-06-02 09:13:48 +02:00
Tom Rini
3d9f63519d Merge tag 'u-boot-imx-next-20250601' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx into next
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/26436

- Add i.MX6UL clk driver.
- Improve the .MX6UL NAND controller performance.
- Add imx6ulz BSH SMM M2B board.
- Several improvements for imx8m venice boards.
2025-06-01 09:36:18 -06:00
Michael Trimarchi
c7b82b4aab bsh: imx6ulz_smm_m2: Add imx6ulz BSH SMM M2B board
Introduce the BSH SystemMaster (SMM) M2B board. Notably, the M2B is
designed to leverage the existing device tree of its predecessor, the M2.
The primary distinction arises from memory incompatibilities with the M2.
To address this, we've implemented a configuration system that allows for
selective inclusion of the desired memory components.

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2025-05-31 16:59:28 -03:00
Michael Trimarchi
8642939ee0 configs/imx6ulz_smm_m2_defconfig: Enable clock framework
Enable the clock framework on the m2 platform.
This helps to increase the NAND controller performance.

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2025-05-31 16:59:12 -03:00
Michael Trimarchi
404a4c84d8 mtd: nand: Add support for EDO mode 1-5 to IMX6ULL platform
The clock driver allows to boost the NAND performance
controller. Make changes to let it use the new clock driver

=> time nand read ${loadaddr} kernel

NAND read: device 0 offset 0x500000, size 0x800000
 8388608 bytes read: OK

time: 0.488 seconds

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2025-05-31 16:59:12 -03:00
Michael Trimarchi
1c513b9edf mtd: mxs_nand_dt: Move from clk_get/clk_enable to clk_bulk api
Make simple the clock registration and enable and allow later
to add support for other platforms

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2025-05-31 16:59:11 -03:00
Michael Trimarchi
0f53197c3d clk: imx: add i.MX6UL clk driver
Add i.MX6UL clk driver for i.MX6UL CLK driver model usage

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
Tested-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2025-05-31 16:59:11 -03:00
Tim Harvey
37195f8413 imx8mp-venice-gw74xx: add w_disable2 gpio configuration
The GW74xx D revision has added a M2SKT_WDIS2# GPIO which routes to the
W_DISABLE2# pin of the M.2 socket.

Add the iomux and a line name for this and rename the existing
m2_wdis# signal to m2_wdis1#.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2025-05-30 19:10:56 -03:00
Tim Harvey
314469b6ba board: venice: append configuration string to model
Append the optional board configuration string to the model info.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2025-05-30 19:10:56 -03:00
Tim Harvey
41bc2d5334 board: venice: update model representation for venice-flex
Update the model string representation for the Venice-Flex product
family (GW8xxx).

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2025-05-30 19:10:56 -03:00
Tim Harvey
da9e2218af board: venice: add FSA support
The Gateworks Flexible Socket Adapters adapt common
busses such as SDIO/UART/USB/PCI to various connectors
such as M.2 B-Key, M.2 E-Key, M.2 M-Key, and MiniPCIe.

Each FSA has an EEPROM onboard describing its details as well as an
optional port-expander for configurable GPIO's.

Add support for identifying the FSA's and configuring their
details such as user description and GPIO's:
 - enable pca953x, pca954x and eeprom support for communicating
   with the I2C eeprom and gpio port expander on the FSA
 - add FSA detection support
 - add FSA gpio configuration support

Each FSA is identified in the device-tree by an alias to it's I2C
bus where an eeprom@54 node must exist as well as an gpio@20 node
for an io-expander. These nodes must be enabled so that
they can be probed to determine if they are actually present in
the system. If not present or not enabled the gpio expander can
not be used. This also requires livetree as the gpio expander
node if not present must be disabled.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2025-05-30 19:10:56 -03:00
Tim Harvey
9eebca1025 board: venice: add imx8mp-gw82xx support
The Gateworks GW82XX-2X is an ARM based single board computer (SBC)
comprised of the i.MX8M Plus based gw702x SoM and the gw82xx
baseboard featuring:
 - i.MX8M Plus SoC
 - LPDDR4 DRAM
 - eMMC FLASH
 - Gateworks System Controller (GSC)
 - microSD (1.8V/3.3V Capable)
 - panel status bi-color LED
 - pushbutton switch
 - fan controller with tachometer
 - USB Type-C connector
 - PCIe switch
 - 2x GbE RJ45 connectors
 - multi-protocol RS232/RS485/RS422 Serial ports
 - 2x Flexible Socket Adapters with SDIO/UART/USB/PCIe
   (for M.2 and miniPCIe expansion)
 - 2x isolated CAN
 - GPS
 - accelerometer
 - magnetometer
 - off-board connectors for: SPI, GPIO, I2C, ADC
 - Wide range DC power input
 - support for 802.3at PoE (via adapter)

Add support for it by providing its device-tree.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2025-05-30 19:10:56 -03:00
Tim Harvey
5e72676890 board: venice: flip logic for GSC supervisor enable
Flip the logic used to determine if a board has the proper hardware to
support enabling the GSC voltage supervisor so that we do not need to
keep adding new models to the list.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2025-05-30 19:10:56 -03:00
Tim Harvey
b1ead5a224 board: venice: use SOM model for PMIC adjustment on SOM
Use the SOM model to adjust PMIC settings on SOM's.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2025-05-30 19:10:56 -03:00
Tim Harvey
ea04f7261e board: venice: use baseboard model for family
The venice family of baseboards which is normally GW7xxx
is being expanded to GW8xxx so we need to use the baseboard
number instead of the som.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2025-05-30 19:10:56 -03:00
Tim Harvey
c83ab82640 board: venice: fix dram size for GW7901-SP486
The GW7901-SP486 with the exception of the -C revision has 2GB DRAM
loaded but incorrectly specifies 1GB in the EEPROM. Adjust the DRAM size
to account for this.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2025-05-30 19:10:55 -03:00
Tim Harvey
1bf9f1e550 board: venice: fix dram bus config for GW7902/GW7903/GW7904
The GW7902/GW7903/GW7904 have an alternate databus layout affecting a few
of the DDRC and DDR PHY registers.

The 512MB configuration used this alternate bus layout. Change
the 512MB config to the standard bus configuration and add a generic
function to patch the DDRC/PHY configs for the alternate bus layout.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2025-05-30 19:10:55 -03:00
Tim Harvey
66e8b17eee board: venice: move soc-specific dram config into soc-specific files
Move the determination of the dram timings into the soc-specific files.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2025-05-30 19:10:55 -03:00
Tim Harvey
2f1c3e1f9e configs: imx8m*_venice: enable GPT support
Enable support for working with General Partition Tables via the 'gpt'
command. Also enable support for generating random UUID's for GPT.

See: doc/README.gpt for examples

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2025-05-30 19:10:55 -03:00
Tim Harvey
ea26f2ac4c configs: imx8m*_venice: enable several commands useful for scripting
enable cat, xxd, and the ability for setexpr to return values in
variables which are all useful for scripting.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2025-05-30 19:10:55 -03:00
Tom Rini
6e03ca2409 Merge tag 'dm-pull-30may25' of git://git.denx.de/u-boot-dm into next
Bring in recent expo enhancements:
- multi-line text
- highlighting of menu items
- rationalisation of menu and expo code
- support for object alignment
- editable strings
- various bug fixes and tweaks

This also includes some required abuf improvements.
2025-05-30 13:53:50 -06:00
Eddie Kovsky
b22a276f03 image: android: fix ramdisk default address
Commit 21e7fa0e3a ("image: android: handle ramdisk default address")
changed the default behavior for header versions less than or equal to 2.

The ramdisk address (img_data.ramdisk_ptr) is only assigned to *rd_data
if the physical load address (img_data.ramdisk_addr) is equal to 0 or
the Android default ramdisk address.

    /* Ramdisk can be used in-place, use current ptr */
    if (img_data.ramdisk_addr == 0 ||
            img_data.ramdisk_addr == ANDROID_IMAGE_DEFAULT_RAMDISK_ADDR) {
        *rd_data = img_data.ramdisk_ptr;
    } else {
        ramdisk_ptr = img_data.ramdisk_addr;
        *rd_data = ramdisk_ptr;
        memcpy((void *)(ramdisk_ptr), (void *)img_data.ramdisk_ptr,
                img_data.ramdisk_size);
    }

When the img_data.ramdisk_addr and the img_data.kernel_addr are the same
*rd_data needs to be assigned to the ramdisk address (ramdisk_ptr), not
the physical address (ramdisk_addr).

As a result of the current behavior, we can no longer boot a kernel on
the Renesas R-Car S4 board.

Add an additional check to the if clause so that the ramdisk address is
assigned when the kernel address and the ramdisk address are the same,
restoring the previous default behavior.

Fixes: 21e7fa0e3a ("image: android: handle ramdisk default address")
Signed-off-by: Eddie Kovsky <ekovsky@redhat.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Tested-by: Mattijs Korpershoek <mkorpershoek@kernel.org> # khadas vim3
2025-05-30 13:44:05 -06:00
Benjamin ROBIN
b8f282b8e0 bootm: Fix bmi->images pointer not initialized in some cases
When building with only bootz command, without bootm, images pointer
inside bootm_info structure is not initialized. And since this structure
is stored in stack, the generated error is kind of random, but most of
the time this will generate: "ramdisk - allocation error".

Also, after analysis, this problem could occur with the command booti,
if the command bootm is disabled.

Currently bootm_init() is called by: do_bootz(), do_bootm(), do_booti()
and by do_stm32prog(). And all of these commands execute bootm_run_states()
which access the images pointer stored into bootm_info structure.

So, to fix this issue, just do the assignment unconditionally.

Fixes: c2211ff651 ("bootm: Add more fields to bootm_info")
Signed-off-by: Benjamin ROBIN <dev@benjarobin.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
2025-05-30 13:43:37 -06:00
Benjamin ROBIN
6aa9c0f453 env: Fix network support when CONFIG_NET_LWIP is set
When lwIP (CONFIG_NET_LWIP) is used instead of legacy stack (CONFIG_NET),
environment flags support associated with network was not built: restore
support of "i" and "m" environment flags.

Signed-off-by: Benjamin ROBIN <dev@benjarobin.fr>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2025-05-30 13:43:24 -06:00
Tom Rini
5eb1b78438 Merge patch series "test/py: enable HTTP testing"
Adriano Cordova <adrianox@gmail.com> says:

Enable HTTP server in CI to support HTTP tests in pytest

QEMU does not emulate an HTTP server, unlike other services like DHCP or TFTP.
To enable HTTP  tests during CI runs, start a simple Python HTTP server
on port 80. This allows tests that require HTTP access to run.

The HTTP server is launched on the host. For QEMU environments launched
with '-netdev,user' this means that the HTTP server runs together with DHCP
at 10.0.2.2.  HTTP testing needs to be explicitly enabled with
env__efi_helloworld_net_http_test_skip = False.

We also default `WGET=y` in `ARCH_QEMU` configurations so that these HTTP
tests are included automatically when using QEMU in CI.

Link: https://lore.kernel.org/r/20250516085256.30386-1-adriano.cordova@canonical.com
2025-05-30 11:19:45 -06:00
Adriano Cordova
ec1d9f3fe8 cmd/Kconfig: select CMD_WGET if ARCH_QEMU
select CMD_WGET for ARCH_QEMU. This way HTTP can be tested
on the qemu platforms in CI.

Signed-off-by: Adriano Cordova <adriano.cordova@canonical.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-05-30 11:19:44 -06:00
Adriano Cordova
3e58991339 CI testing: add http server to CI tests
Add an http server to CI tests so that HTTP booting and
loading can be tested.

Signed-off-by: Adriano Cordova <adriano.cordova@canonical.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-05-30 11:19:43 -06:00
Marek Vasut
e15282f943 image: Fix FIT image loadable section custom processing
The original commit always generated linker list entries with the same
entry variable name, because _function passed to ll_entry_declare() is
not a variable and therefore was interpreted as fixed string. Change it
to _type which is a variable and which does allow generation of multiple
unique linker list entries, one for each U_BOOT_FIT_LOADABLE_HANDLER().

Fixes: d7be50921e ("image: Add FIT image loadable section custom processing")
Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
2025-05-30 10:19:24 -06:00
Tom Rini
c7f360f20d Gitlab: Rework sjg-lab calling test.py to be closer to test.py stage
There are a few differences between how the test.py stage invokes
test.py and how the sjg-lab stage invokes test.py. As a start of making
both the code and the output and artifacts similar, this updates the
sjg-lab stage with the following:
- Pass "-ra" so that we get the summary information in the job
- Make use of TEST_PY_EXTRA for passing "--capture=tee-sys"
- Re-order some of the arguments to be the same order when possible.

And most importantly:
- Create and save as an artifact the junitxml output.

The last part here is the kind of test result information that in the
future we should determine how to archive for future reference.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-05-30 10:19:02 -06:00
Tom Rini
2ab0f0d058 Merge patch series "Almost complete DM_SERIAL migration"
Tom Rini <trini@konsulko.com> says:

In a private thread, Simon asked about what's needed to get PowerPC
migrated to DM_SERIAL. I went and took a look, and to complete the
entire DM_SERIAL migration (excluding SPL/TPL) we're actually nearly
there. This series first migrates PowerPC (and some NXP Layerscape
boards that share history more clearly with PowerPC parts), with the
biggest change being to make sure we still use the correct legacy
drivers in SPL/TPL (where SPL is extremely constrained). With that out
of the way, I looked at what was left. With two exceptions, it's
platforms which can be trivially enabled for conversion, and so we do
that.

Link: https://lore.kernel.org/r/20250502201226.1369013-1-trini@konsulko.com
2025-05-30 10:17:40 -06:00
Tom Rini
b5321da5cc global: Convert almost all remaining non-DM_SERIAL users
This converts almost all of the remaining non-DM_SERIAL users to enable
DM_SERIAL. These are platforms where there have long been other SoC
boards that have switched and so it's been a matter of inertia keeping
these from being converted. Do so now.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-05-30 10:16:51 -06:00
Tom Rini
191b10ac70 PowerPC / Layerscape: Finish migration to DM_SERIAL
Migrate the few ARM Layerscape platforms that had not been switched
along with all remaining PowerPC platforms to DM_SERIAL. For PowerPC,
this means that platforms which use SPL/TPL, keeping the non-DM serial
driver enabled there as they do not use DM. We also rework the guards
on how to define CFG_SYS_NS16550_CLK so that this is mostly in one place
now.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-05-30 10:16:51 -06:00
Simon Glass
44fc287387 expo: Drop the special theme code for bootflow_menu
The expo now has all that is needed to apply a suitable theme, so drop
this unnecessary code. Any further tweaks can be added to the generic
expo code.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-30 09:49:33 +01:00
Simon Glass
8a9d40b047 expo: Set up menu fully in bootflow_menu_start()
Apply the theme, calculate dimensions, highlight the menu and arrange
the scene correctly, so that everything is ready to go when the expo
is rendered.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-30 09:49:33 +01:00
Simon Glass
f769735f88 expo: Split setting up the menu from adding items
Some callers may wish to add items later as they are discovered. Split
the setup code into its own function, to permit this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-30 09:49:33 +01:00
Simon Glass
06a9d88e4d expo: Update bootflow_menu_poll() to return a sequence ID
Rather than returning a bootflow, return the index of the bootflow. This
will allow callers to do their own translation to bootflows or some
other data structure.

Also return a special code when the user tries to move the pointer, so
that the caller can cancel the boot-menu timeout, if this is in use.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-30 09:49:33 +01:00
Simon Glass
f8f8f822c3 expo: Improve the visual appearance of the menu
The menu is currently quite basic. Make use of some recently added
features in expo, to:

- Show proper prompts
- Highlight the current item
- Centre text
- Use multi-line text instead of two independent lines
- Put a box around the items

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-30 09:49:32 +01:00
Simon Glass
ddd1c97653 expo: Provide a way to position things relative to display
It is often necessary to centre objects within the display area. Add a
special position value to indicate this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-30 09:49:32 +01:00
Simon Glass
8d7ae52d77 expo: Drop the render from expo_poll()
Within tests it is useful to be able to control rendering of the expo.
Drop the automatic call to expo_render() within expo_poll() and adjust
its callers to handle this instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-30 09:49:32 +01:00
Simon Glass
5bca479897 expo: Adjust expo_poll() to avoid looping forever
If the user does not quickly provide some input, exit so that other
things can be done, such as searching for the next OS.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-30 09:49:32 +01:00
Simon Glass
0dc8c7740c expo: Support highlighting menu items
Expo normally uses a pointer to show the current item. Add support for
highlighting as well, since this makes it easier for the user to see the
current item.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-30 09:49:32 +01:00
Simon Glass
86acc21d85 expo: Add forward declarations to scene_internal.h
Provide some forward declarations for types used in this file, to keep
the LSP happy and avoid errors if the caller happens not to include the
required header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-30 09:49:32 +01:00
Simon Glass
bebc3547b2 expo: Drop the gap between groups of menu items
The gap is intended to separate options which are on different bootdevs,
but most of the time there is only one. So drop this gap.

Keep the code around in case it becomes useful to have it in the style,
or based on some other mechanism.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-30 09:49:32 +01:00
Simon Glass
3c35fb03d5 expo: Use a simpler name for USB media
For USB devices we use the string 'usb_mass_storage' which is a bit
verbose. Use 'USB' instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-30 09:49:32 +01:00
Simon Glass
e005f18b93 expo: Begin implementation of a text editor
It is useful to be able to edit text, e.g. to allow the user to edit the
environment or the command-line arguments for the OS.

Add the beginnings of an implementation. Future work is needed to finish
this: keypress handling and scrolling. For now it just displays the
text.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-30 09:49:32 +01:00