Commit Graph

28063 Commits

Author SHA1 Message Date
Frieder Schrempf
7056aad696 imx6dl-sielaff: Convert to OF_UPSTREAM
Switch to OF_UPSTREAM to make use of the upstream devicetree.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2025-07-24 07:58:59 -03:00
Tom Rini
d0b9b9a80f Merge patch series "mkimage: validate default configuration reference"
Aristo Chen <jj251510319013@gmail.com> says:

This patch series introduces a validation step in `mkimage` to ensure that
the `default` property under the `/configurations` node in a FIT image
references a valid subnode. If the referenced node does not exist, mkimage
now prints an error and fails early. This helps prevent runtime failures
when U-Boot attempts to boot using an undefined configuration.

The first patch implements the validation logic in `fit_image.c`. The second
patch fixes an invalid default configuration reference exposed by this new
check in the `k3-am65-iot2050-boot-image.dtsi`. The final patch adds a test
case to verify that mkimage correctly fails when an invalid default
configuration is present in the ITS file.

This series improves the robustness of FIT image generation and helps
catch malformed image trees during build time.

Link: https://lore.kernel.org/r/20250715130317.3886-1-aristo.chen@canonical.com
2025-07-23 13:12:22 -06:00
Aristo Chen
f7b03695d4 arm: k3-am65-iot2050: Fix invalid default configuration reference
mkimage introduced a validation step to ensure that the 'default'
property under the /configurations node in a FIT image refers to a
valid subnode. This exposed an issue in the
k3-am65-iot2050-boot-image.dtsi, where the 'default' property was set to
"ti/k3-am6528-iot2050-basic" and "ti/k3-am6528-iot2050-basic-pg2", which
do not correspond to actual configuration node names.

This patch updates both /configurations nodes to reference the correct
subnode.

Without this fix, mkimage will fail with an error:
"ERROR: Default configuration 'ti/k3-am6528-iot2050-basic' not found
under /configurations"

An upcoming commit will validate the if the default configuration exists

Signed-off-by: Aristo Chen <aristo.chen@canonical.com>
2025-07-23 13:12:16 -06:00
Holger Brunck
6175371f66 arm: ls1021a-pg-wcom: add i2c mux node and eeprom
We are now using the DM code for the i2c mux and to read out the
inventory eeprom. Therefore we need to add the nodes to the specific DTS
files.

Signed-off-by: Holger Brunck <holger.brunck@hitachienergy.com>
2025-07-22 13:53:03 -06:00
Gokul Praveen
7d41363977 configs: KASLR OPTEE RNG support for K3 devices
KASLR, or Kernel Address Space Layout Randomization, is a security
feature in the Linux kernel that randomizes the memory location
where the kernel is loaded during boot.

OP-TEE RNG is a Random Number Generator (RNG) component within the
Open Portable Trusted Execution Environment (OP-TEE) which provides
a random number to U-BOOT and U-BOOT provides this random number
as seed value to the LINUX kernel for KASLR.

Add KASLR OPTEE RNG support across K3 devices by enabling the required
configs.

Signed-off-by: Gokul Praveen <g-praveen@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com>
2025-07-22 10:16:06 -06:00
Tom Rini
786e1f6dea sandbox: Add dummy sync()
In order to compile more drivers, add an empty sync() function.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-07-18 12:22:11 -06:00
Tom Rini
0f83825802 Merge tag 'u-boot-imx-master-20250717' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/27088

- Add support for the i.MX95 B0 version.
- Enable standard boot for phycore-imx8mp.
- Kconfig fixes for i.MX MMC and FSL_SEC_MON.
- Support 4Gb single die variant of the i.MX8MM Venice board.
2025-07-17 11:42:46 -06:00
Holger Brunck
94354e3a92 armv8: ls1043a: make some erratas dependent from USB
These erratas are only useful if USB is enabled. If it is disabled
these erratas might cause issues.

Signed-off-by: Holger Brunck <holger.brunck@hitachienergy.com>
2025-07-17 09:58:22 -03:00
David Zang
c71ea4b9a4 soc: imx8ulp: Add celsius unit for temperature
Make temperature unit (celsius) more clear to reduce confusion.

Signed-off-by: David Zang <davidzangcs@gmail.com>
2025-07-17 09:57:55 -03:00
Tom Rini
d4a9ce26cb nxp: Move FSL_SEC_MON related options to arch/Kconfig.nxp
The options related to FSL_SEC_MON are part of the chain of trust
related options and should be under that menu, so move it there.
Furthermore we don't need to prompt for the driver itself but do need to
allow for configuration of the monitor endianess.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-07-17 09:57:39 -03:00
Tom Rini
7e42f3671d arm: imx: Remove unused mxcmmc driver
As no platforms use this driver anymore, remove it.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-07-17 09:57:23 -03:00
Alice Guo
9936724aa9 imx95_evk: Add i.MX95 B0 support
i.MX95 B0 uses image container format v2 and needs DUMMY_DDR so that
update imximage.cfg and container.cfg for it.

Signed-off-by: Alice Guo <alice.guo@nxp.com>
2025-07-17 09:56:33 -03:00
Ye Li
42337445b5 spl: imx: Add support for new PQC container
To support PQC container format which is used for post quantum
authentication on new i.MX parts like i.MX94

The major changes compared to legacy container format is in
signature block, new container tag and version, and new alignment
of container header.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
2025-07-17 09:56:33 -03:00
Ye Li
cadc0abe65 arm: imx: Update ELE get_info structure for i.MX94
Since i.MX94, the ELE get_info structure is updated to add
OEM PQC SRK hash, so update it.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
2025-07-17 09:56:33 -03:00
Yao Zi
e875813600 riscv: dts: th1520: Describe GMACs and enable them on Lichee Pi 4A
TH1520 SoC ships two MAC controllers based on Designware Ethernet IP
that are capable of Gigabit operation. Describe them in SoC devicetree
and enable them for Lichee Pi 4A.

Signed-off-by: Yao Zi <ziyao@disroot.org>
Acked-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-07-17 14:37:40 +08:00
Yao Zi
12b90ea3c2 riscv: cpu: th1520: Limit upper RAM boundary to 4 GiB
TH1520 SoC ships DMA peripherals that could only reach the first 32-bit
range of memory, for example, the GMAC controllers. Let's limit the
usable top of RAM below 4GiB to ensure DMA allocations are accessible to
all peripherals.

Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-07-17 14:37:40 +08:00
Rasmus Villemoes
343a30aba3 arm: dts: am335x-evm: remove duplicate chosen node
The stdout-path property is already set to this value in the other
chosen node ~15 lines above.

Signed-off-by: Rasmus Villemoes <ravi@prevas.dk>
2025-07-16 10:56:28 -06:00
Tom Rini
d0ed963690 global: Make ARCH_MISC_INIT a selected symbol
This symbol is not something that the user should be enabling or
disabling but rather the developer for a particular board should select
it when required.

This is mostly size neutral, however a few places do have changes. In
the case of i.MX6ULL systems, it is always the case that
arch_misc_init() could call setup_serial_number() and do useful work,
but was not enabled widely, but now is. In the case of i.MX23/28
systems, we should be able to call mx28_fixup_vt() again here, so do so.
Finally, some platforms were calling arch_misc_init() and then not doing
anything and this results in removing the option.

Acked-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-07-11 11:33:25 -06:00
Tom Rini
b4528976e7 Merge patch series "Create uclass for HW AES cryptographic devices"
Svyatoslav Ryhel <clamor95@gmail.com> says:

Add uclass for HW AES cryptographic devices found on some devices, like
Tegra20/Tegra30 SoC AES engine.

Link: https://lore.kernel.org/r/20250629105711.24687-1-clamor95@gmail.com
2025-07-11 11:33:25 -06:00
Svyatoslav Ryhel
e82ba0be9b test: dm: add AES engine test
Create a basic test suit for AES DM uclass that covers all available
operations.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2025-07-11 10:43:29 -06:00
Tom Rini
561134e04d Merge tag 'u-boot-imx-master-20250710' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/27010

- Fix the i.MX8M Nano GPU path.
- Enable RNG support for KASLR on Toradex i.MX8 boards.
- Enable watchdog and clock driver for imx6ulz_smm_m2b.
- Tighten dependencies on CMD_BLOB.
- Remove the rest of i.MX31 support.
2025-07-11 08:38:53 -06:00
Tom Rini
6bb0679377 Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sh
- SH Ether clean ups, RZ/A1 clean ups, RZ/A1 Genmai support
- Gen3 EEPROM DT node clean up
- V4H SA0 BootROM compatible binman etype, SCIF compatible SREC
  generation for Gen4
2025-07-10 16:44:08 -06:00
Magnus Damm
25adecf094 ARM: renesas: Add support for the r7s72100 Genmai board
Add r7s72100 Genmai board support. Serial console, NOR Flash and
Ethernet are known to work however on-board SDRAM is not yet enabled.

Signed-off-by: Magnus Damm <damm@opensource.se>
2025-07-10 19:26:56 +02:00
Marek Vasut
64a2c3731f arm64: renesas: Switch R-Car V4H to renesas_rcar4_sa0 binman etype
Replace current ad-hoc generation of SA0 header with renesas_rcar4_sa0 binman
etype on Renesas R-Car V4H. The new binman etype generates header which is
almost identical to the current ad-hoc SA0 header, with one difference, the
load length matches the actual payload size, which slightly improves boot time.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-07-10 19:26:56 +02:00
Marek Vasut
48ec1fd4f4 arm64: dts: renesas: Clean up sysinfo EEPROM DT description on R-Car Gen3
Most of the sysinfo EEPROM node eeprom@50 is now part of the core DTs,
remove duplicate DT properties from *-u-boot.dtsi . Adjust the phandle
reference to i2c-eeprom in sysinfo node using <&{i2c_*/eeprom@50}> to
avoid need for DT label. No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-07-10 19:26:56 +02:00
Marek Vasut
26758c24b9 arm64: renesas: Add Renesas R-Car Gen4 SCIF/HSCIF loader SREC generation
Add Renesas R-Car Gen4 SCIF/HSCIF loader compatible SREC generation.
This is a regular U-Boot SPL SREC augmented with a short header which
describes where to store the received data and how much data to store.
This header is interpreted by the R-Car Gen4 BootROM SCIF/HSCIF loader.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-07-10 19:26:55 +02:00
Marek Vasut
f85d97b26c arm64: renesas: Convert SCIF SREC from u-boot-spl.bin
Convert u-boot-spl.bin instead of u-boot-spl ELF into SCIF loader
compatible SREC. The u-boot-spl.bin includes SPL DT, while the ELF
does not, which leads to failure to start SPL via SCIF loader due
to missing SPL DT. Fix this by using u-boot-spl.bin which includes
the DT.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-07-10 19:26:55 +02:00
Tom Rini
7faaa16a47 sandbox: Add some missing {clr,set,clrset}bits variants
Add the 16, 32 and 64bit versions of the non-endian {clr,set,clrset}bits
macros.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-07-10 08:40:47 -06:00
Alexander Stein
76f11d6de3 arm: imx: imx8m: soc: Fix i.MX8M Nano GPU paths
The SoC node is called 'soc@0', even on NXP branch 6.6-fslc. This fixes
the boot on i.MX8M Nano DualLite, as there is no GPU.

Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
2025-07-10 08:02:11 -03:00
Tom Rini
b284c34725 arm: imx: Remove the rest of i.MX31 support
With the removal of the last i.MX31 platform we can remove the rest of
the underlying architecture code as well.

Fixes: f247354708 ("arm: Remove mx31pdk board")
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
2025-07-10 08:02:11 -03:00
Tom Rini
bbca681cde Merge patch series "board: ti: am33xx: Add Ethernet support for Beaglebone Green Eco"
Romain Gantois <romain.gantois@bootlin.com> says:

This is version one of my series which enables Ethernet support on the BBGE
board. This requires three main changes:

 - Describing the MAC<->PHY link and DP83867 PHY accurately in the device
   tree
 - Enabling the RGMII1 pinmux configuration
 - Enabling the DP83867 driver

These changes are all applied in patch 2.

Patch 1 enables excluding the DP83867 driver from SPL. This is done to
avoid size issues when adding the DP83867 driver to the am335x-evm
defconfig.

Link: https://lore.kernel.org/r/20250626-bbge-ethernet-v1-0-5b544fb1898f@bootlin.com
2025-07-09 08:45:33 -06:00
Romain Gantois
48b1f8a396 board: ti: am33xx: Add Ethernet support for Beaglebone Green Eco
Currently, the Ethernet interface of the BBGE board isn't properly
supported.

To support this interface, describe the MAC<->PHY RGMII link and the
DP83867 PHY in the BBGE device tree. Enable the DP83867 PHY driver in
U-Boot Proper and mux the relevant RGMII lines.

Signed-off-by: Romain Gantois <romain.gantois@bootlin.com>
Tested-by: Judith Mendez <jm@ti.com>
2025-07-09 08:45:27 -06:00
Tom Rini
971bd7614c Merge patch series "Improve Verdin AM62P thermal setup by generalizing ft_board_setup_ex()"
João Paulo Gonçalves <jpaulo.silvagoncalves@gmail.com> says:

In some use cases, board-specific device tree changes must not be overwritten
by system fixups. Although U-Boot provides ft_board_setup_ex() for this
purpose, it is currently only used on TI Keystone. This series makes
ft_board_setup_ex() a generic option, allowing its use by other architectures
and boards.

Additionally, considering that Toradex Verdin-AM62P hardware lifetime
guarantees are based on a 105°C junction temperature (while TI AM62Px supports
up to 125°C), this series implements necessary changes within TI K3 AM62P and
Toradex board code. These changes include exporting common fixup device Tree
functions used in TI K3 for board-code access and also fixup for AM62P thermal
zones to correctly reflect the number of CPU nodes according to the SoC part
number.

Link: https://lore.kernel.org/r/20250623-am62p-fdt-fixup-trip-points-v1-0-12355eb6a72f@toradex.com
2025-07-09 08:40:36 -06:00
João Paulo Gonçalves
7f4baa866d arm: mach-k3: am62p: fixup thermal cooling device by cpu number
TI AM62Px devices support CPU throttling based on thermal alerts.
However, the device tree assumes a 4-core configuration. Since the AM62P
also supports 2-core configurations, add a fixup to dynamically adjust
the cooling-device nodes within thermal zones based on the actual number
of CPU cores available.

Signed-off-by: João Paulo Gonçalves <joao.goncalves@toradex.com>
2025-07-09 08:40:03 -06:00
João Paulo Gonçalves
9e672e4260 arm: mach-k3: Export common fdt fixups for use in board code
Avoid code duplication by making the common TI K3 device tree fixup
functions to be reusable by board-specific code.

Signed-off-by: João Paulo Gonçalves <joao.goncalves@toradex.com>
2025-07-09 08:40:03 -06:00
João Paulo Gonçalves
2b7c6b6f3c boot: Make ft_board_setup_ex() generic
In some use cases, board-specific device tree changes must not be
overwritten by system fixups. Although U-Boot provides
ft_board_setup_ex() for this purpose, it is currently only used on TI
Keystone. Make ft_board_setup_ex() to be a generic option, allowing its
use by other architectures/boards. To maintain backward compatibility,
enable it by default on TI Keystone.

Signed-off-by: João Paulo Gonçalves <joao.goncalves@toradex.com>
2025-07-09 08:40:03 -06:00
Tom Rini
a591af1123 include/spl_gpio.h: Audit include list
This file does not need <asm/gpio.h> so remove it. This file does
however need <linux/types.h> so add that in. This also shows that
arch/arm/mach-rockchip/rk3399/rk3399.c and board/lg/star/star.c were
indirectly getting <asm/gpio.h> from here, so add <asm/gpio.h> to them.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-07-08 13:11:12 -06:00
Michal Simek
14f627bf43 xilinx: Remove simple-bus description from mini configurations
simple bus node and drivers not bringing up any value for mini
configuration that's why remove it and disable drivers for it to save some
space.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/a51b11fa21c504a19701ebdccc1e61e899e1aed5.1751016029.git.michal.simek@amd.com
2025-07-08 14:58:43 +02:00
Tom Rini
4216a86343 arm: zynqmp: Remove local copy of 'dt-bindings/clock/xlnx-zynqmp-clk.h'
As part of the recent cleanup of dt-bindigns header files we did not
remove our copy of dt-bindings/clock/xlnx-zynqmp-clk.h at the time. This
is because the difference between ours and current upstream is that
current upstream has a #warning to not use it and to instead use
xlnx-zynqmp-clk.h. So we change zynqmp-clk-ccf.dtsi to use the other
and upstream-only file and then delete our dt-bindings file.

Signed-off-by: Tom Rini <trini@konsulko.com>
Tested-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20250612181128.340232-1-trini@konsulko.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2025-07-08 14:58:43 +02:00
Yao Zi
c7e27f9a4a riscv: cpu: th1520: Enable pinctrl by default
Select PINCTRL_TH1520 in CPU Kconfig entry and update defconfig for
existing TH1520-based boards to ensure PINCTRL is enabled.

Signed-off-by: Yao Zi <ziyao@disroot.org>
Acked-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-07-03 18:10:58 +08:00
Yao Zi
a4f9013e31 riscv: dts: th1520: Add pin controllers
Describe the three pin controllers integrated in TH1520 SoC. Since we
don't have support for clocks in the AON region, a dummy fixed-clock
node is added to supply the pin controller locating in it.

Signed-off-by: Yao Zi <ziyao@disroot.org>
Acked-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-07-03 18:10:58 +08:00
Ben Dooks
364627596c riscv: byteorder: add test for big-endian
Test for big-endian either via __RISCVEB__ which migth be
rather old, or check the BYTE_ORDER if the compiler defines
it (which should be any modern gcc like v12)

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Acked-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-07-03 18:10:50 +08:00
Ben Dooks
7bd65e89ad riscv: add build support for big-endian
Add support to build code big-endian if the board supports
it. Updates the makefile to pass the correct compiler and
elf flags.

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Reviewed-by: Tom Rini <trini@konsulko.com>
2025-07-03 18:10:50 +08:00
Yao Zi
ddb52eac41 riscv: dts: th1520: Preserve CLINT node for SPL
Preserve CLINT node for SPL, whose IPI functionality is essential for
operation of a multi-core system.

Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-07-03 16:14:13 +08:00
Yao Zi
f28911368e riscv: cpu: th1520: Add a routine to bring up secondary cores
On coldboot, only HART 0 among the four HARTs of TH1520 is brought up by
hardware, and the remaining HARTs are in reset states, requiring manual
setup of reset address and deassertion to function normal. Introduce a
routine to do the work.

Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-07-03 16:14:13 +08:00
Yao Zi
5afad3d4a3 riscv: cpu: th1520: Setup CPU feature CSRs in harts_early_init
C910 cores integrated in TH1520 SoC provide various customized CSRs for
configuring core behavior, including cache coherency and timing, branch
predication, and clock gating for internal components.

This patch sets them up for efficient operation and satisfying
requirements of an SMP system.

Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-07-03 16:14:13 +08:00
Yao Zi
4153ceb0fe riscv: aclint_ipi: Support T-Head C900 CLINT
Although timer component of the CLINT isn't fully compatible with the
generic RISC-V ACLINT, the IPI component behaves the same.

As the CLINT doesn't have corresponding riscv_aclint_timer driver
available, let's try looking for a compatible SYSCON device directly
when no riscv_aclint_timer device could be found on IPI initialization.

Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-07-03 16:14:13 +08:00
Giulio Benetti
a14da5ed61 arch/arm/include/asm/arch-imxrt/gpio.h: imxrt gpio use common gpio.h
The current file defines a struct gpio_regs identical to the one in
<asm/mach-imx/gpio.h>. To eliminate code duplication and align with
the approach used for i.MX8M, include the common header instead of
redefining the struct.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2025-06-29 10:08:10 -03:00
Lukasz Majewski
612421af51 arm: pinctrl: Define .mux_mask field for NXP's SoC
The commit e8a9521e64
("vf500/vf610: synchronise device trees with linux")
has synchronized U-Boot's DTS with v5.19 Linux kernel.
It turned out that in Linux's upstream iomuxc node description the
'fsl,mux_mask' was missing, so the U-Boot's pinctrl driver for NXP's
Vybrid SoC was not working properly.

As by default the mux mask was set to 0, for example the vf610 based
boards (like BK4) were bricked, due to misconfiguration of gpio at
early boot stage.

The fix for all NXP eligible boards is to define .mux_mask field for
soc specific *pinctrl_soc_info structure and use it directly in pinctrl
MMIO driver, without the need to read the "fsl,mux_mask" property from
device tree.

This change brings the NXP's pinctrl driver in U-Boot closer to Linux
upstream one.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com> #for i.MX8ULP
2025-06-29 10:07:55 -03:00
Lukasz Majewski
ecf8169ef8 dts: pcm052: bk4: Use proper compatible for QSPI SPI-NOR memory
In the contemporary U-Boot the "spi-flash" compatible is used only when
CONFIG_$(PHASE_)SPI_FLASH_TINY is defined so spi-nor-tiny.c is compiled.

As vf610 devices are not using SPL at all, the SPI_FLASH_TINY is not
defined and no QSPI flash child nodes are considered as valid ones.

The result is that the 'sf probe' command fails and SPI NOR memory is not
accessible on e.g. BK4 device.

The fix is to use proper compatible - in this case "jedec,spi-nor".

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2025-06-29 10:07:23 -03:00