Commit Graph

97032 Commits

Author SHA1 Message Date
Marek Vasut
eaf2ed4eb4 arm64: dts: renesas: Drop OF_UPSTREAM conversion remnant
This DTC_FLAGS assignment is no longer necessary as all R-Car Gen2/Gen3/Gen4
platforms have been converted to OF_UPSTREAM and matching DTC_FLAGS assignment
is present in dts/upstream/src/arm64/Makefile . Drop the remnant.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-29 16:55:31 +01:00
Marek Vasut
2fd7a04e7c arm64: renesas: Align configuration headers
Align R-Car Gen2/Gen3/Gen4 configuration header file to look
basically the same way across these three SoC generations.
There are subtle difference between the remaining bits in
those files across SoC generations, but the common bits are
now aligned. There is not much left in those headers either,
most of the configuration is now converted to Kconfig.

Specifically for R-Car Gen3, GIC registers have been moved
to architecture specific header file rcar-gen3-base.h , the
rest of the changes here are comment changes and indentation
changes.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-29 16:55:31 +01:00
Marek Vasut
ec53fdee5b arm64: renesas: Add Renesas R-Car V4H SPL implementation
Add support for building U-Boot SPL for Renesas R-Car Gen4 R8A779G0 V4H SoC.
The SPL initializes the DBSC5 DRAM controller, RT-VRAM and loads and starts
U-Boot proper on the Cortex-A76 core.

The SoC BootROM can not boot the CA76 core directly, instead the SPL starts
on the CR52 core which immediately brings up the CA76 core, which in turn
starts executing the actual SPL. This is achieved by placing a tiny bit of
precompiled Aarch32 code at the very beginning of the SPL. The code consists
of some 32 instructions, uses APMU to configure CA76 start address to offset
0x80 Bytes from start of the SPL, and uses APMU to start the CA76 core. The
code parts the CR52 core in an endless loop once the CA76 core got started.

The 32 instructions are completely arbitrary number, so is the offset 0x80
Bytes from start of SPL, because 0x80 = 128 decimal and 128 / 4 bytes per
instruction is 32 instructions. The 32 instructions turned out to be enough
to started the CA76 and 0x80 is nicely aligned.

Once the SPL completes hardware initialization, the SPL loads U-Boot proper.
The u-boot.itb proper fitImage contains 64bit build on u-boot-nodtb.bin and
a DT for R8A779G0 V4H White Hawk board and is generated by binman. The
u-boot.itb is loaded from SPI NOR offset 0x80000.

In order to install this setup on an existing R8A779G0 V4H White Hawk board,
build using r8a779g0_whitehawk_defconfig, generate SPI NOR image flash.bin
and write flash.bin to SPI NOR offset 0x0 . Finally, configure board MD pin
switches according to the R8A779G0 V4H White Hawk board documentation for
40 MHz SPI NOR boot using DMA and restart the board.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-29 16:55:31 +01:00
Marek Vasut
6a32d5b54f arm64: renesas: Make bottom 128 MiB of DRAM available in EL3
In case U-Boot runs in EL3, which is the highest privilege level on ARM64,
there can be no firmware running that would restrict access to the bottom
128 MiB of DRAM. In fact, it is likely that U-Boot would have to load that
firmware into those bottom 128 MiB of DRAM and start that firmware.

Make those bottom 128 MiB of DRAM available in case U-Boot runs in EL3 to
allow loading the firmware to that area.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-29 16:55:31 +01:00
Marek Vasut
cf096e7d73 arm64: renesas: Split R-Car Gen3 and Gen4 common board code
Split common board code for R-Car Gen3 and Gen4 into separate files.
The R-Car Gen3 board code contains fixups specific to TFA which are
no longer required on R-Car Gen4, keep those fixups in its own file
so they would not interfere with Gen4.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-29 16:55:31 +01:00
Marek Vasut
caefe8a1b4 arm64: renesas: Deduplicate R-Car Gen4 board files
All R-Car Gen4 board files are copies of one another at this point.
Deduplicate them into single board/renesas/rcar-common/gen4-common.c
and remove all the duplicates. The one exception is R-Car V3U Falcon
board, which enables RWDT reset in board_init(), conditionally build
RWDT enablement in board_init() in the new common code for V3U.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-29 16:55:31 +01:00
Marek Vasut
67440c8642 arm64: renesas: Make stub PSCI implementation available on 64bit R-Car SoCs
Make the R-Car V3U stub PSCI implementation available on 64bit R-Car SoCs.
This implementation is useful during early board bring up, where it can
supplant missing fully-featured PSCI implementation. Note that this PSCI
implementation is very basic and offers only SoC reset functionality. It
is unable to enable or disable secondary CPU cores nor does it offer any
suspend/resume functionality.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-29 16:55:31 +01:00
Marek Vasut
94255316db arm64: dts: renesas: Add R8A779G0 V4H DBSC5 and RT-VRAM DT nodes
Describe DBSC5 DRAM controller and RT-VRAM configuration interface
as two new DT nodes in R-Car Gen4 R8A779G0 U-Boot DT extras file.
This node is used by the U-Boot SPL for R8A779G0 SoC, where the
DBSC5 and RT-VRAM drivers bind to these nodes and bring up the
DRAM controller and RT-VRAM settings respectively, so U-Boot
proper can be loaded into DRAM and started on Cortex A76 core.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-29 16:55:31 +01:00
Marek Vasut
7366aacf8e ram: renesas: Add Renesas R-Car Gen4 DBSC5 driver
Add Renesas R-Car Gen4 DBSC5 DRAM controller driver. This driver is currently
capable of bringing LPDDR5 DRAM on Renesas R-Car V4H Whitehawk board. Further
boards can be supported by supplying board specific DRAM configuration data
via dbsc5_get_board_data(). Support for R-Car V4M is not implemented, however
the driver is already mostly prepared to support this SoC.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-29 16:55:31 +01:00
Marek Vasut
476b886a6f pinctrl: renesas: Convert to IS_ENABLED() macro
Use the IS_ENABLED() macro to reduce amount of #ifdef use in the driver
and improve code coverage. With IS_ENABLED() macro, the code is compiled
and then optimized out, which prevents bitrot.

In case no PFC table matches the SoC in use, do not probe the driver
and instead exit with -ENODEV. This should never happen under normal
conditions, because this would mean the driver DT compatible string
match happened, but the list in probe() cannot match the model listed
in match data associated with the compatible string on which the match
did happen.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-29 16:55:31 +01:00
Tom Rini
d580a013cc Merge patch series "vbe: Series part E"
Simon Glass <sjg@chromium.org> says:

This includes various patches towards implementing the VBE abrec
bootmeth in U-Boot. It mostly focuses on SPL tweaks and adjusting what
fatures are available in VPL.

Link: https://lore.kernel.org/r/20241219182907.2609704-1-sjg@chromium.org
2024-12-27 15:16:39 -06:00
Simon Glass
6f1b27a724 hash: Plumb crc8 into the hash functions
Add an entry for crc8, with watchdog handling.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2024-12-27 15:16:10 -06:00
Simon Glass
286b48c957 boot: Imply CRC8 with VBE
VBE uses a crc8 checksum to verify that the nvdata is valid, so make
sure it is available if VBE is enabled.

Signed-off-by: Simon Glass <sjg@chromium.org>
2024-12-27 15:16:10 -06:00
Simon Glass
ded772fafa lib: Allow crc8 in TPL and VPL
Provide options to enable the CRC8 feature in TPL and VPL builds.

Signed-off-by: Simon Glass <sjg@chromium.org>
2024-12-27 15:16:10 -06:00
Simon Glass
8dfbd79812 boot: Allow use of FIT in TPL and VPL
With VBE we want to use FIT in all phases of the boot. Add Kconfig
options to support this.

Disable the options for sandbox_vpl for now.

Signed-off-by: Simon Glass <sjg@chromium.org>
2024-12-27 15:16:10 -06:00
Simon Glass
0b0e0f273d spl: lib: Allow for decompression in any SPL build
Add Kconfig symbols and update the Makefile rules so that decompression
can be used in TPL and VPL

Signed-off-by: Simon Glass <sjg@chromium.org>
2024-12-27 15:16:10 -06:00
Simon Glass
e6c09c8cc4 spl: Add some more debugging to load_simple_fit()
Add debugging of image-loading progress. Fix a stale comment in the
function comment while we are here.

Signed-off-by: Simon Glass <sjg@chromium.org>
2024-12-27 15:16:10 -06:00
Simon Glass
03b94635d8 spl: Drop a duplicate variable in boot_from_devices()
The variable 'ret' is defined twice, which is not intended. This may
have been a local merge error.

Signed-off-by: Simon Glass <sjg@chromium.org>
Fixes: 2eefeb6d893 ("spl: Report a loader failure")
2024-12-27 15:16:10 -06:00
Simon Glass
7a585b9d6a spl: Drop use of uintptr_t
U-Boot uses ulong for addresses. It is confusing to use uintptr_t in a
few places, since it makes people wonder if the types are compatible.
Change the few occurences in SPL to use ulong

Signed-off-by: Simon Glass <sjg@chromium.org>
2024-12-27 15:16:10 -06:00
Simon Glass
7f67b6fa83 spl: Support a relocated stack in any XPL phase
The current check looks only at SPL, but TPL or VPL might have a
different setting. Update the condition.

Signed-off-by: Simon Glass <sjg@chromium.org>
2024-12-27 15:16:10 -06:00
Simon Glass
a7d4d11944 spl: Allow serial to be disabled in any XPL phase
The current check looks only at SPL, but TPL or VPL might have a
different setting. Update the condition.

Signed-off-by: Simon Glass <sjg@chromium.org>
2024-12-27 15:16:10 -06:00
Simon Glass
5f158d8832 spl: Report a loader failure
If a loader returns an error code it is silently ignored. Show a message
to at least provide some feedback to the user.

Signed-off-by: Simon Glass <sjg@chromium.org>
2024-12-27 15:16:10 -06:00
Simon Glass
92a4fd0a29 Support setting a maximum size for the VPL image
Add a size limit for VPL, to match those for SPL and TPL

Signed-off-by: Simon Glass <sjg@chromium.org>
2024-12-27 15:16:10 -06:00
Simon Glass
1bfbf09d5c malloc: Provide a simple malloc for VPL
The VPL phase may want to use the smaller malloc() implementation, so
add an option for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2024-12-27 15:16:10 -06:00
Simon Glass
c44c83f1fb malloc: Show amount of used space when memory runs out
Show a bit more information when malloc() space is exhausted and
debugging is enabled.

Signed-off-by: Simon Glass <sjg@chromium.org>
2024-12-27 15:16:10 -06:00
Simon Glass
4702647528 boot: Respect the load_op in fit_image_load()
Some code has crept in which ignores this parameter. Fix this and add a
little debugging.

Signed-off-by: Simon Glass <sjg@chromium.org>
Fixes: b1307f884a ("fit: Support compression for non-kernel components (e.g. FDT)")
2024-12-27 15:16:10 -06:00
Simon Glass
19574e35f4 bootstd: Avoid sprintf() in SPL when creating bootdevs
The name of the bootdev device is not that important, particular in SPL.
Save a little code space by using a simpler name.

Signed-off-by: Simon Glass <sjg@chromium.org>
2024-12-27 15:16:10 -06:00
Simon Glass
771f0e9877 boot: Allow FIT to fall back from best-match option
When the best-match feature fails to find something, use the provided
config name as a fallback. The allows SPL to select a suitable config
when best-match is enabled.

Signed-off-by: Simon Glass <sjg@chromium.org>
2024-12-27 15:16:10 -06:00
Simon Glass
9922227ac5 image: Add a prototype for fit_image_get_phase()
This function exists but is not exported. Add a prototype so it can be
used elsewhere.

Signed-off-by: Simon Glass <sjg@chromium.org>
2024-12-27 15:16:10 -06:00
Simon Glass
8369dd058a spl: mmc: Avoid size growth in spl_mmc_find_device() debug
The for() loop ends up being in the code even if the log_debug() does
nothing. Add a condition to fix this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2024-12-27 15:16:10 -06:00
Tim Harvey
aa233d26bd board: gateworks: venice: rename GW7905 to GW7500
The GW7905 was renamed to GW7500 before release. Change the various
names in the dt files and references.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2024-12-27 14:34:45 -06:00
Tom Rini
5cfbf8c364 Merge tag 'v2025.01-rc5' into next
Prepare v2025.01-rc5
2024-12-25 22:31:04 -06:00
Tom Rini
2c366eb1cd Merge branch 'next-pinctrl' of https://source.denx.de/u-boot/custodians/u-boot-sh into next 2024-12-25 22:30:48 -06:00
Marek Vasut
545208247d pinctrl: renesas: Minimize R8A779H0 V4M PFC tables
Reduce the PFC tables by ifdeffing out pinmux settings which are
unlikely to be used by U-Boot. This helps reduce the size of the
bootloader in the 10 kiB range. This includes conditional build
of these PFC additions:

- Audio
- CAN/CANFD
- INTC/INTC-EX
- MSIOF
- PWM
- SSI

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-25 19:29:47 +01:00
Marek Vasut
a69f8cb9e2 pinctrl: renesas: Minimize R8A779G0 V4H PFC tables
Reduce the PFC tables by ifdeffing out pinmux settings which are
unlikely to be used by U-Boot. This helps reduce the size of the
bootloader in the 10 kiB range. This includes conditional build
of these PFC additions:

- Audio
- CAN/CANFD
- DU
- INTC-EX
- MSIOF
- PWM
- SSI

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-25 19:29:47 +01:00
Marek Vasut
35c5ac0d53 pinctrl: renesas: Minimize R8A779F0 S4 PFC tables
Reduce the PFC tables by ifdeffing out pinmux settings which are
unlikely to be used by U-Boot. This helps reduce the size of the
bootloader in the 10 kiB range. This includes conditional build
of these PFC additions:

- INTC-EX
- MSIOF

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-25 19:29:47 +01:00
Marek Vasut
15c51cc62d pinctrl: renesas: Minimize R8A779A0 V3U PFC tables
Reduce the PFC tables by ifdeffing out pinmux settings which are
unlikely to be used by U-Boot. This helps reduce the size of the
bootloader in the 10 kiB range. This includes conditional build
of these PFC additions:

- CAN/CANFD
- DU
- INTC-EX
- MSIOF
- PWM

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-25 19:29:47 +01:00
Marek Vasut
59c9ca0ba3 pinctrl: renesas: Minimize R8A77995 D3 PFC tables
Reduce the PFC tables by ifdeffing out pinmux settings which are
unlikely to be used by U-Boot. This helps reduce the size of the
bootloader in the 10 kiB range. This includes conditional build
of these PFC additions:

- Audio
- CAN/CANFD
- DU
- MSIOF
- PWM
- SSI
- VIN

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-25 19:29:47 +01:00
Marek Vasut
1ee288a6aa pinctrl: renesas: Minimize R8A77990 E3 PFC tables
Reduce the PFC tables by ifdeffing out pinmux settings which are
unlikely to be used by U-Boot. This helps reduce the size of the
bootloader in the 10 kiB range. This includes conditional build
of these PFC additions:

- Audio
- CAN/CANFD
- DU
- INTC/INTC-EX
- MSIOF
- PWM
- SSI
- VIN

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-25 19:29:47 +01:00
Marek Vasut
fa51edbab6 pinctrl: renesas: Minimize R8A77980 V3H PFC tables
Reduce the PFC tables by ifdeffing out pinmux settings which are
unlikely to be used by U-Boot. This helps reduce the size of the
bootloader in the 10 kiB range. This includes conditional build
of these PFC additions:

- CANFD
- DU
- INTC-EX
- MSIOF
- PWM
- VIN

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-25 19:29:47 +01:00
Marek Vasut
a046f58f33 pinctrl: renesas: Minimize R8A77970 V3M PFC tables
Reduce the PFC tables by ifdeffing out pinmux settings which are
unlikely to be used by U-Boot. This helps reduce the size of the
bootloader in the 10 kiB range. This includes conditional build
of these PFC additions:

- CANFD
- DU
- INTC-EX
- MSIOF
- PWM
- VIN

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-25 19:29:47 +01:00
Marek Vasut
d020179cf0 pinctrl: renesas: Minimize R8A77965 M3-N PFC tables
Reduce the PFC tables by ifdeffing out pinmux settings which are
unlikely to be used by U-Boot. This helps reduce the size of the
bootloader in the 10 kiB range. This includes conditional build
of these PFC additions:

- Audio
- CAN/CANFD
- DU
- INTC-EX
- MSIOF
- PWM
- SSI
- VIN

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-25 19:29:47 +01:00
Marek Vasut
0edacf1a41 pinctrl: renesas: Minimize R8A77960 M3-W and R8A77961 M3-W+ PFC tables
Reduce the PFC tables by ifdeffing out pinmux settings which are
unlikely to be used by U-Boot. This helps reduce the size of the
bootloader in the 10 kiB range. This includes conditional build
of these PFC additions:

- Audio
- CAN/CANFD
- DU
- INTC-EX
- MSIOF
- PWM
- SSI
- VIN

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-25 19:29:47 +01:00
Marek Vasut
2890251ead pinctrl: renesas: Minimize R8A77951 H3 PFC tables
Reduce the PFC tables by ifdeffing out pinmux settings which are
unlikely to be used by U-Boot. This helps reduce the size of the
bootloader in the 10 kiB range. This includes conditional build
of these PFC additions:

- Audio
- CAN/CANFD
- DU
- INTC-EX
- MSIOF
- PWM
- SSI
- VIN

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-25 19:29:47 +01:00
Marek Vasut
7f19150405 pinctrl: renesas: Minimize R8A7794 E2 PFC tables
Reduce the PFC tables by ifdeffing out pinmux settings which are
unlikely to be used by U-Boot. This helps reduce the size of the
bootloader in the 10 kiB range. This includes conditional build
of these PFC additions:

- Audio
- CAN
- DU
- INTC
- MSIOF
- PWM
- SSI
- VIN

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-25 19:29:47 +01:00
Marek Vasut
7db1d1fadf pinctrl: renesas: Minimize R8A7792 V2H PFC tables
Reduce the PFC tables by ifdeffing out pinmux settings which are
unlikely to be used by U-Boot. This helps reduce the size of the
bootloader in the 10 kiB range. This includes conditional build
of these PFC additions:

- CAN
- DU
- INTC
- MSIOF
- VIN

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-25 19:29:47 +01:00
Marek Vasut
6671e9aebd pinctrl: renesas: Minimize R8A7791 M2-W and R8A7793 M2-N PFC tables
Reduce the PFC tables by ifdeffing out pinmux settings which are
unlikely to be used by U-Boot. This helps reduce the size of the
bootloader in the 10 kiB range. This includes conditional build
of these PFC additions:

- Audio
- CAN
- DU
- INTC
- MSIOF
- PWM
- SSI
- VIN

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-25 19:29:47 +01:00
Marek Vasut
2f3bd7ca26 pinctrl: renesas: Minimize R8A7790 H2 PFC tables
Reduce the PFC tables by ifdeffing out pinmux settings which are
unlikely to be used by U-Boot. This helps reduce the size of the
bootloader in the 10 kiB range. This includes conditional build
of these PFC additions:

- Audio
- CAN
- DU
- INTC
- MSIOF
- PWM
- SSI
- VIN

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-25 19:29:47 +01:00
Marek Vasut
e6e3d70632 pinctrl: renesas: Add Kconfig symbol for conditional build of full PFC tables
By default the pin multiplexing tables used by U-Boot are reduced
to keep the size of the bootloader low. This option allows build of
full pin multiplexing tables the same way they are included in the
Linux kernel. This includes pin multiplexing options for Audio, CAN,
CANFD, DU, INTC, INTC-EX, MSIOF, PWM, SSI, for which there is no
U-Boot driver. This option is disabled by default.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-25 19:29:47 +01:00
Tom Rini
6a042f830f Subtree merge tag 'v6.12-dts' of dts repo [1] into dts/upstream
[1] https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git

Based on what "git diff" suggests, rename a device tree for
imx8mm_venice_defconfig and imx8mp_venice_defconfig

Signed-off-by: Tom Rini <trini@konsulko.com>
---
Cc: Tim Harvey <tharvey@gateworks.com>
2024-12-24 13:33:03 -06:00