OP-TEE message UID check API can be useful to know whether OP-TEE
is enabled on not assuming the corresponding SMC call is properly
handled if OP-TEE is not supported.
This API can be used by platform code to know OP-TEE presence and
on that basis OP-TEE DT node can be added as part of DT fixups for
the OP-TEE driver probe to happen for both U-Boot and Linux.
Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://patch.msgid.link/20260127062341.723966-2-sumit.garg@kernel.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
Add a 100 ms delay after clearing the core soft reset bit to ensure
the DWC3 controller has sufficient time to complete its reset
sequence before subsequent register accesses.
Without this delay, USB initialization can fail on some Qualcomm
platforms, particularly when using super-speed capable PHYs like
the QMP USB3-DP Combo PHY on SC7280/QCM6490.
Taken from Linux commit f88359e1588b ("usb: dwc3: core: Do core softreset when switch mode")
Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Reviewed-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>
Link: https://patch.msgid.link/20251203110735.1959862-3-balaji.selvanathan@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
Commit ecba4380ad ("net: zynq_gem: Update the MDC clock divisor in the
probe function") changed zynq_gem_init() from a direct register write to
a read-modify-write pattern in order to preserve MDC clock divider bits.
However, the old speed selection bits (SPEED100/SPEED1000) are never
cleared before OR-ing in the new value.
When the PHY renegotiates at a different speed between successive calls
to zynq_gem_init() (e.g. link flapping from 1 Gbps to 100 Mbps on a
marginal cable), both SPEED100 and SPEED1000 end up set simultaneously
in NWCFG. This confuses the GEM hardware and no frames are received.
Fix by explicitly clearing both speed bits before merging the new
configuration, so only the currently negotiated speed is ever active.
Fixes: ecba4380ad ("net: zynq_gem: Update the MDC clock divisor in the probe function")
Signed-off-by: Rafał Hibner <rafal.hibner@secom.com.pl>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20260420074640.4036119-1-rafal.hibner@secom.com.pl
Reinitialize RX BDs and rewrite rxqbase on every init instead of only
on the first init. This ensures a clean BD state on every init for all
GEM configurations.
For AMD Versal Gen 2 10GBE this is required since the USX block
resets the RX DMA pointer to rxqbase on each init, so BDs must be
rebuilt each time to stay in sync with hardware.
Signed-off-by: Pranav Tilak <pranav.vinaytilak@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20260410093018.1461732-4-pranav.vinaytilak@amd.com
Add support for the DesignWare-based PCIe host controller found in
AMD Versal2 SoCs. This enables PCIe functionality (e.g. NVMe storage)
on boards such as the VEK385.
The driver builds on the existing pcie_dw_common infrastructure and
adds Versal2-specific handling: it maps the SLCR register region to
mask and clear TLP interrupt status bits, parses dbi/config/atu/slcr
register regions from device tree, and supports an optional PERST#
GPIO on child nodes for endpoint reset sequencing. The outbound iATU
is programmed for the non-prefetchable memory window from device tree
ranges.
Signed-off-by: Pranav Sanwal <pranav.sanwal@amd.com>
Link: https://lore.kernel.org/r/20260327121015.996806-2-pranav.sanwal@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
When a clock parent entry is DUMMY_PARENT (0xFFFFFFFE), masking it
with CLK_PARENTS_ID_MASK (0xFFFF) produces the value 0xFFFE (65534).
This value is stored in parent->id and later used as a clock array
index in versal_clock_get_parentid(). Since clock_max_idx is
typically 228, accessing clock[65534] is out-of-bounds, and the
garbage value read is used as a clock ID in subsequent clock rate
calculations, eventually causing U-Boot to crash. This is observed
as a crash during "clk dump" on AMD Versal Gen 2.
Fix this by setting parent->id = 0 for DUMMY_PARENT entries.
Fixes: 95105089af ("clk: versal: Add clock driver support")
Signed-off-by: Padmarao Begari <padmarao.begari@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20260327101053.900154-1-padmarao.begari@amd.com
Set the XAE_RAF_BCSTREJ_MASK bit in the Reset and Address Filter (RAF)
register during hardware initialization to make the MAC drop incoming
frames with broadcast destination address. This avoids unnecessary
broadcast traffic processing by the CPU.
Additionally, when IPv6 is not enabled (CONFIG_IPV6), also set the
XAE_RAF_MCSTREJ_MASK bit to reject multicast frames. Multicast
rejection is skipped when IPv6 is configured because IPv6 Neighbor
Discovery and DHCPv6 rely on multicast.
Expose the RAF register (offset 0x0) in struct axi_regs which was
previously hidden in a reserved array.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/07ad94eb8a3a9d80273a16a7ac8c7caaba607fe2.1774282153.git.michal.simek@amd.com
Currently, virtio_mmio_probe() returns 0 when it encounters an invalid
magic value, an unsupported version, or a dummy device (ID 0). In
U-Boot's driver model, returning 0 indicates a successful probe. This
causes the system to incorrectly register and activate invalid or
placeholder devices, potentially leading to undefined behavior or
crashes later on.
Update the probe function to return appropriate error codes (-ENODEV
for invalid magic values and dummy devices, and -ENXIO for unsupported
versions). This fix correctly instructs the DM to abort the binding
process.
Fixes: fdc4aca89e ("virtio: Add virtio over mmio transport driver")
Signed-off-by: Kuan-Wei Chiu <visitorckw@gmail.com>
Acked-by: Daniel Palmer <daniel@thingy.jp>
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/29880
- Convert TQMA7 boards to SPL.
- Use second Ethernet MAC also from fuse on i.MX dhelectronics boards.
- Add support for Toradex Verdin iMX95.
- Drop SPL_POWER_LEGACY from imx8m boards.
- Increase the Aquantia Ethernet PHY reset timeout.
signed_hdmi_imx8m.bin is already signed and has a IVT header. It should not
be put in u-boot-spl-mkimage.signed.bin. Move it to head of flash.bin
following NXP imx-mkimage. Keeping it in u-boot-spl-mkimage.signed.bin also
consumes a lot of TCM space which is not expected.
While moving it to head of flash.bin, other changes are required,
u-boot.itb is put at sector 768 per defconfig, so u-boot.itb binman
offset should be updated and it should be moved out from binman section.
Also binman symbol address are updated, so need to subtract u-boot-spl
image_pos + CONFIG_SPL_TEXT_BASE to find the correct location of ddr phy
firmware.
Because there is 1KB padding in HDMI firmware, use 32KB when burning
flash.bin to sd card.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Current timeout for PHY out of reset is 50ms which is too short.
Increase it to 2s to align with kernel.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Acked-by: Tim Harvey <tharvey@gateworks.com>
The generated .S files for fonts and splash screens use .incbin with the
full prerequisite path. When building with O= this bakes an absolute
path into the .S file. If the build directory is later used on a
different machine (e.g. in a container), the assembler cannot find the
source file.
Follow the existing DTB convention: rename the object targets to use
compound suffixes (.ttf.o, .bmp.o), switch the pattern rules from
direct $(call cmd,...) to FORCE + $(call if_changed,...), and register
the new suffixes with intermediate_targets so that kbuild loads their
.cmd files. This lets if_changed detect when the recorded command
(including source paths) has changed and regenerate the .S file
automatically.
The EFI rule is left unchanged since its prerequisite is a generated
file in the build directory, like the DTB and DTBO rules.
The intermediate_targets entries stay in scripts/Makefile.build rather
than moving to scripts/Makefile.lib-u-boot, because that file is
included before intermediate_targets is defined and 'targets' is ':=',
so a '$(call intermediate_targets, ...)' inside it would expand to
empty and silently drop the entries. To keep the upstream block
untouched, the U-Boot additions go in a separate 'targets +=' block
immediately below.
Suggested-by: Rasmus Villemoes <ravi@prevas.dk>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Rasmus Villemoes <ravi@prevas.dk>
Casey Connolly <casey.connolly@linaro.org> says:
This series implements various improvements to Linux header
compatibility, largely in preparation for a full port of Linux CCF but
many of these changes would also be helpful when porting other drivers.
Beside the basic header/compat stuff there are a few larger patches:
Patch 1 adds the "%pOF" format specifier to vsprintf, this behaves the
same as it does in Linux printing the name of the ofnode, but notably it
expects an ofnode pointer rather than a device_node.
Patch 2 adds an option to skip doing a full DM scan pre-relocation.
Some platforms like Qualcomm don't actually need devices to be probed
prior to relocation, it is also quite slow to scan the entire FDT before
caches are up. This option gets us to main loop 30-50% faster.
Unfortunately it isn't possible to totally skip DM since U-Boot will
panic if it can't find a serial port, but the serial uclass code will
bind the serial port itself by reading /chosen/stdout-path, however any
dependencies like clocks won't be found so this should only be enabled
if the serial driver gracefully handles missing clocks.
Patch 3 adds [k]strdup_const(), this works the same as the Linux version
saving a small amount of memory by avoiding duplicating strings stored
in .rodata, this is particularly useful for CCF.
Patch 4 adds 64-bit versions of some 32-bit ofnode utilities functions,
making it possible to parse 64-bit arrays.
Patch 6 provides a simple implementation of kref, this will be used
by CCF.
Patch 9 adds devm_krealloc() support to devres, it relies on storing
allocation sizes in the devres struct which will add a small overhead.
Link: https://lore.kernel.org/r/20260401-casey-ccf-compat-v2-0-414d5b7f040b@linaro.org
These are similar to their Linux counterparts, adding helpers
for reading arrays of 64-bit values with of_access and fdtdec
implementations.
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
The refactoring in commit 00d0ff7f81 ("clk: mediatek: refactor parent
rate lookup functions") introduced a regression where fixed PLL clocks
using mtk_clk_fixed_pll_ops are not properly recognized as valid parents
in the CLK_PARENT_APMIXED case.
Fixed PLL clocks are implemented using mtk_clk_fixed_pll_ops instead of
mtk_clk_apmixedsys_ops, but they can also serve as parent clocks in the
APMIXED domain. The parent lookup function needs to check for both
driver ops to properly resolve the parent clock device.
Add mtk_clk_fixed_pll_ops checks alongside mtk_clk_apmixedsys_ops checks
in mtk_find_parent_rate() to restore support for fixed PLL parent clocks.
Fixes: 00d0ff7f81 ("clk: mediatek: refactor parent rate lookup functions")
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Link: https://patch.msgid.link/923e50db696d910803828cd26b0ca0fbbfe11570.1776326933.git.weijie.gao@mediatek.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
