Add files that were forgotten

* Avoid flicker on the TRAB's VFD by synchronizing the enable with
the HSYNC/VSYNC. Requires new CPLD code (Version 101 for Rev. 100 boards, version 153 for Rev. 200 boards). * Patch by Vladimir Gurevich, 12 Mar 2003: Fix relocation problem of statically initialized string pointers in common/cmd_pci.c * Patch by Kai-Uwe Bl�m, 12 Mar 2003: Cleanup & bug fixes for JFFS2 code: - the memory mangement was broken. It caused havoc on malloc by writing beyond the block boundaries. - the length calculation for files was wrong, sometimes resulting in short file reads. - data copying now optionally takes fragment version numbers into account, to avoid copying from older data. See doc/README.JFFS2 for details.
2026-06-12 22:49:43 +03:00 · 2003-03-14 21:34:25 +00:00 · 2003-03-14 20:47:52 +00:00 · 2003-03-12 10:43:01 +00:00 · 2003-03-12 10:41:04 +00:00 · 2003-03-06 21:55:29 +00:00
119 changed files with 11699 additions and 1079 deletions
--- a/70
+++ b/70
@@ -2,6 +2,76 @@
 Changes since U-Boot 0.2.2:
 ======================================================================

+* Avoid flicker on the TRAB's VFD by synchronizing the enable with
+  the HSYNC/VSYNC. Requires new CPLD code (Version 101 for Rev. 100
+  boards, version 153 for Rev. 200 boards).
+
+* Patch by Vladimir Gurevich, 12 Mar 2003:
+  Fix relocation problem of statically initialized string pointers
+  in common/cmd_pci.c
+
+* Patch by Kai-Uwe Blöm, 12 Mar 2003:
+  Cleanup & bug fixes for JFFS2 code:
+  - the memory mangement was broken. It caused havoc on malloc by
+    writing beyond the block boundaries.
+  - the length calculation for files was wrong, sometimes resulting
+    in short file reads.
+  - data copying now optionally takes fragment version numbers into
+    account, to avoid copying from older data.
+  See doc/README.JFFS2 for details.
+
+* Patch by Josef Wagner, 12 Mar 2003:
+  - 16/32 MB and 50/80 MHz support with auto-detection for IP860
+  - ETH05 and BEDBUG support for CU824
+  - added support for MicroSys CPC45
+  - new BOOTROM/FLASH0 and DOC base for PM826
+
+* Patch by Robert Schwebel, 12 Mar 2003:
+  Fix the chpart command on innokom board
+
+* Name cleanup:
+  mv include/asm-i386/ppcboot-i386.h include/asm-i386/u-boot-i386.h
+  s/PPCBoot/U-Boot/ in some files
+  s/pImage/uImage/  in some files
+
+* Patch by Detlev Zundel, 15 Jan 2003:
+  Fix '' command line quoting
+
+* Patch by The LEOX team, 19 Jan 2003:
+  - add support for the ELPT860 board
+  - add support for Dallas ds164x RTC
+
+* Patches by David Müller, 31 Jan 2003:
+  - minimal setup for CardBus bridges
+  - add EEPROM read/write support in the CS8900 driver
+  - add support for the builtin I2C controller in the Samsung s3c24x0 chips
+  - add support for MPL's VCMA9 (Samsung s3c2410 based) board
+
+* Patch by Steven Scholz, 04 Feb 2003:
+  add support for RTC DS1307
+
+* Patch by Reinhard Meyer, 5 Feb 2003:
+  fix PLPRCR/SCCR init sequence on 8xx to allow for
+  changes of EBDF by software
+
+* Patch by Vladimir Gurevich, 07 Feb 2003:
+  "API-compatibility patch" for 4xx I2C driver
+
+* TRAB fixes / extensions:
+  - Restore VFD brightness as saved in environment
+  - add support for FGujitsu flashes
+  - make sure both buzzers are turned off (drive low level)
+
+* Patches by Robert Schwebel, 06 Mar 2003:
+  - fix bug in BOOTP code (must use NetCopyIP)
+  - update of CSB226 port
+  - clear BSS segment on XScale
+  - added support for i2c_init_board() function
+  - update to the Innokom plattform
+
+* Extend support for redundand environments for configurations where
+  environment size < sector size
+
 * Patch by Rune Torgersen, 13 Feb 2003:
  Add support for Motorola MPC8266ADS board

--- a/5
+++ b/5
@@ -166,6 +166,11 @@ N: Thomas Lange
 E: thomas@corelatus.com
 D: Support for GTH board; lots of PCMCIA fixes

+N: The LEOX team
+E: team@leox.org
+D: Support for LEOX boards, DS164x RTC
+W: http://www.leox.org
+
 N: Raymond Lo
 E: lo@routefree.com
 D: Support for DOS partitions
--- a/5
+++ b/5
@@ -137,6 +137,10 @@ Thomas Lange <thomas@corelatus.com>

 	GTH			MPC860

+The LEOX team <team@leox.org>
+
+	ELPT860			MPC860T
+
 Eran Man <eran@nbase.co.il>

 	EVB64260_750CX		MPC750CX
@@ -247,6 +251,7 @@ Gary Jennejohn <gj@denx.de>
 David Müller <d.mueller@elsoft.ch>

 	smdk2410		ARM920T
+	VCMA9			ARM920T

 Rolf Offermanns <rof@sysgo.de>

--- a/32
+++ b/32
@@ -16,18 +16,18 @@ LIST=""

 LIST_8xx="	\
 	ADS860		AMX860		c2mon		CCM		\
-	cogent_mpc8xx	ESTEEM192E	ETX094		FADS823		\
-	FADS850SAR	FADS860T	FLAGADM		FPS850L		\
-	GEN860T		GENIETV		GTH		hermes		\
-	IAD210		ICU862_100MHz	IP860		IVML24		\
-	IVML24_128	IVML24_256	IVMS8		IVMS8_128	\
-	IVMS8_256	KUP4K           LANTEC	        lwmon   	\
-	MBX		MBX860T		MHPC		MVS1		\
-	NETVIA		NX823		pcu_e		R360MPI		\
-	RPXClassic	RPXlite		RRvision	SM850		\
-	SPD823TS	SXNI855T	TOP860		TQM823L		\
-	TQM823L_LCD	TQM850L		TQM855L		TQM860L		\
-	TQM860L_FEC	TTTech		v37				\
+	cogent_mpc8xx	ESTEEM192E	ETX094		ELPT860		\
+	FADS823		FADS850SAR	FADS860T	FLAGADM		\
+	FPS850L		GEN860T		GENIETV		GTH		\
+	hermes		IAD210		ICU862_100MHz	IP860		\
+	IVML24		IVML24_128	IVML24_256	IVMS8		\
+	IVMS8_128	IVMS8_256	KUP4K           LANTEC	        \
+	lwmon   	MBX		MBX860T		MHPC		\
+	MVS1		NETVIA		NX823		pcu_e		\
+	R360MPI		RPXClassic	RPXlite		RRvision	\
+	SM850		SPD823TS	SXNI855T	TOP860		\
+	TQM823L		TQM823L_LCD	TQM850L		TQM855L		\
+	TQM860L		TQM860L_FEC	TTTech		v37		\
 "

 #########################################################################
@@ -48,9 +48,9 @@ LIST_4xx="	\
 #########################################################################

 LIST_824x="	\
-	BMW		CU824		MOUSSE		MUSENKI		\
-	OXC		PN62		Sandpoint8240	Sandpoint8245	\
-	utx8245								\
+	BMW		CPC45		CU824		MOUSSE		\
+	MUSENKI		OXC		PN62		Sandpoint8240	\
+	Sandpoint8245	utx8245						\
 "

 #########################################################################
@@ -95,7 +95,7 @@ LIST_ARM7="impa7 ep7312"
 ## ARM9 Systems
 #########################################################################

-LIST_ARM9="smdk2400 smdk2410 trab"
+LIST_ARM9="smdk2400 smdk2410 trab VCMA9"

 #########################################################################
 ## Xscale Systems
--- a/39
+++ b/39
@@ -53,21 +53,6 @@ ifndef CROSS_COMPILE
 ifeq ($(HOSTARCH),ppc)
 CROSS_COMPILE =
 else
-##  #ifeq ($(CPU),mpc8xx)
-##  CROSS_COMPILE = ppc_8xx-
-##  #endif
-##  #ifeq ($(CPU),ppc4xx)
-##  #CROSS_COMPILE = ppc_4xx-
-##  #endif
-##  #ifeq ($(CPU),mpc824x)
-##  #CROSS_COMPILE = ppc_82xx-
-##  #endif
-##  #ifeq ($(CPU),mpc8260)
-##  #CROSS_COMPILE = ppc_82xx-
-##  #endif
-##  #ifeq ($(CPU),74xx_7xx)
-##  #CROSS_COMPILE = ppc_74xx-)
-##  #endif
 ifeq ($(ARCH),ppc)
 CROSS_COMPILE = ppc_8xx-
 endif
@@ -202,6 +187,9 @@ CCM_config:		unconfig
 cogent_mpc8xx_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx cogent

+ELPT860_config:		unconfig
+	@./mkconfig $(@:_config=) ppc mpc8xx elpt860 LEOX
+
 ESTEEM192E_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx esteem192e

@@ -457,9 +445,24 @@ WALNUT405_config:unconfig
 #########################################################################
 ## MPC824x Systems
 #########################################################################
+xtract_82xx = $(subst _ROMBOOT,,$(subst _L2,,$(subst _266MHz,,$(subst _300MHz,,$(subst _config,,$1)))))
+
 BMW_config: unconfig
 	@./mkconfig $(@:_config=) ppc mpc824x bmw

+CPC45_config	\
+CPC45_ROMBOOT_config:	unconfig
+	@./mkconfig $(call xtract_82xx,$@) ppc mpc824x cpc45
+	@cd ./include ;				\
+	if [ "$(findstring _ROMBOOT_,$@)" ] ; then \
+		echo "CONFIG_BOOT_ROM = y" >> config.mk ; \
+		echo "... booting from 8-bit flash" ; \
+	else \
+		echo "CONFIG_BOOT_ROM = n" >> config.mk ; \
+		echo "... booting from 64-bit flash" ; \
+	fi; \
+	echo "export CONFIG_BOOT_ROM" >> config.mk;
+
 CU824_config: unconfig
 	@./mkconfig $(@:_config=) ppc mpc824x cu824

@@ -487,7 +490,6 @@ utx8245_config: unconfig
 #########################################################################
 ## MPC8260 Systems
 #########################################################################
-xtract_82xx = $(subst _ROMBOOT,,$(subst _L2,,$(subst _266MHz,,$(subst _300MHz,,$(subst _config,,$1)))))

 cogent_mpc8260_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8260 cogent
@@ -638,6 +640,9 @@ trab_big_flash_config:	unconfig
 		}
 	@./mkconfig -a $(call xtract_trab,$@) arm arm920t trab

+VCMA9_config	:	unconfig
+	@./mkconfig $(@:_config=) arm arm920t vcma9 mpl
+
 #########################################################################
 ## ARM720T Systems
 #########################################################################
@@ -668,7 +673,7 @@ lubbock_config	:	unconfig
 # i386
 #========================================================================
 #########################################################################
-## AMD SC520 CDP 
+## AMD SC520 CDP
 #########################################################################
 sc520_cdp_config	:	unconfig
 	@./mkconfig $(@:_config=) i386 i386 sc520_cdp
--- a/20
+++ b/20
@@ -145,6 +145,8 @@ Directory Hierarchy:
 - cpu/mpc8260	Files specific to Motorola MPC8260 CPU
 - cpu/ppc4xx	Files specific to IBM	   4xx	   CPUs

+- board/LEOX/   Files specific to boards manufactured by The LEOX team
+- board/LEOX/elpt860	Files specific to ELPT860 boards
 - board/RPXClassic
 		Files specific to RPXClassic boards
 - board/RPXlite	Files specific to RPXlite    boards
@@ -338,7 +340,7 @@ The following options need to be configured:
 		CONFIG_GTH,        CONFIG_RPXClassic, CONFIG_rsdproto,
 		CONFIG_IAD210,     CONFIG_RPXlite,    CONFIG_sbc8260,
 		CONFIG_EBONY,      CONFIG_sacsng,     CONFIG_FPS860L,
-		CONFIG_V37
+		CONFIG_V37,        CONFIG_ELPT860

 		ARM based boards:
 		-----------------
@@ -624,7 +626,9 @@ The following options need to be configured:
 		CONFIG_RTC_MPC8xx	- use internal RTC of MPC8xx
 		CONFIG_RTC_PCF8563	- use Philips PCF8563 RTC
 		CONFIG_RTC_MC146818	- use MC146818 RTC
+		CONFIG_RTC_DS1307	- use Maxim, Inc. DS1307 RTC
 		CONFIG_RTC_DS1337	- use Maxim, Inc. DS1337 RTC
+		CONFIG_RTC_DS164x	- use Dallas DS164x RTC

 - Timestamp Support:

@@ -897,6 +901,17 @@ The following options need to be configured:
 		controls the rate of data transfer.  The data rate thus
 		is 1 / (I2C_DELAY * 4).

+		CFG_I2C_INIT_BOARD
+
+                When a board is reset during an i2c bus transfer
+                chips might think that the current transfer is still
+                in progress. On some boards it is possible to access
+                the i2c SCLK line directly, either by using the
+                processor pin as a GPIO or by having a second pin
+                connected to the bus. If this option is defined a
+                custom i2c_init_board() routine in boards/xxx/board.c
+                is run early in the boot sequence.
+
 - SPI Support:	CONFIG_SPI

 		Enables SPI driver (so far only tested with
@@ -1043,7 +1058,7 @@ The following options need to be configured:

 		If CONFIG_ENV_OVERWRITE is #defined in your config
 		file, the write protection for vendor parameters is
-		completely disabled. Anybody can change or delte
+		completely disabled. Anybody can change or delete
 		these parameters.

 		Alternatively, if you #define _both_ CONFIG_ETHADDR
@@ -1704,6 +1719,7 @@ configurations; the following names are supported:
    FPS850L_config	  Sandpoint8240_config	sbc8260_config
    GENIETV_config	  TQM823L_config	PIP405_config
    GEN860T_config	  EBONY_config		FPS860L_config
+    ELPT860_config

 Note: for some board special configuration names may exist; check  if
      additional  information is available from the board vendor; for
--- a/board/LEOX/elpt860/Makefile
+++ b/board/LEOX/elpt860/Makefile
@@ -0,0 +1,47 @@
+#######################################################################
+#
+# Copyright (C) 2000, 2001, 2002, 2003
+# The LEOX team <team@leox.org>, http://www.leox.org
+#
+# LEOX.org is about the development of free hardware and software resources
+#   for system on chip.
+#
+# Description: U-Boot port on the LEOX's ELPT860 CPU board
+# ~~~~~~~~~~~
+#
+#######################################################################
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+#######################################################################
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $^
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
--- a/board/LEOX/elpt860/README.LEOX
+++ b/board/LEOX/elpt860/README.LEOX
@@ -0,0 +1,424 @@
+=============================================================================
+
+             U-Boot port on the LEOX's ELPT860 CPU board
+             -------------------------------------------
+
+LEOX.org is about the development of free hardware and software resources
+         for system on chip.
+
+For more information, contact The LEOX team <team@leox.org>
+
+References:
+~~~~~~~~~~
+    1) Get the last stable release from denx.de:
+           o ftp://ftp.denx.de/pub/u-boot/u-boot-0.2.0.tar.bz2
+    2) Get the current CVS snapshot:
+           o cvs -d:pserver:anonymous@cvs.u-boot.sourceforge.net:/cvsroot/u-boot login
+           o cvs -z6 -d:pserver:anonymous@cvs.u-boot.sourceforge.net:/cvsroot/u-boot co -P u-boot
+
+=============================================================================
+
+The ELPT860 CPU board has the following features:
+
+Processor:	- MPC860T @ 50MHz
+		- PowerPC Core
+		- 65 MIPS
+		- Caches: D->4KB, I->4KB
+		- CPM: 4 SCCs, 2 SMCs
+		- Ethernet 10/100
+		- SPI, I2C, PCMCIA, Parallel
+
+CPU board:	- DRAM:   16 MB
+		- FLASH: 512 KB + (2 * 4 MB)
+		- NVRAM: 128 KB
+		- 1 Serial link
+		- 2 Ethernet 10 BaseT Channels
+
+On power-up the processor jumps to the address of 0x02000100
+
+Thus, U-Boot is configured to reside in flash starting at the address of
+0x02001000.  The environment space is located in NVRAM separately from
+U-Boot, at the address of 0x03000000.
+
+=============================================================================
+
+                        U-Boot test results
+
+=============================================================================
+
+
+##################################################
+# Operation on the serial console (SMC1)
+##############################
+
+U-Boot 0.2.2 (Jan 19 2003 - 11:08:39)
+
+CPU:   XPC860xxZPnnB at 50 MHz: 4 kB I-Cache 4 kB D-Cache FEC present
+         *** Warning: CPU Core has Silicon Bugs -- Check the Errata ***
+Board: ### No HW ID - assuming ELPT860
+DRAM:  16 MB
+FLASH: 512 kB
+In:    serial
+Out:   serial
+Err:   serial
+Net:   SCC ETHERNET
+
+Type "run nfsboot" to mount root filesystem over NFS
+
+Hit any key to stop autoboot:  0
+LEOX_elpt860: help
+askenv  - get environment variables from stdin
+autoscr - run script from memory
+base    - print or set address offset
+bdinfo  - print Board Info structure
+bootm   - boot application image from memory
+bootp   - boot image via network using BootP/TFTP protocol
+bootd   - boot default, i.e., run 'bootcmd'
+cmp     - memory compare
+coninfo - print console devices and informations
+cp      - memory copy
+crc32   - checksum calculation
+echo    - echo args to console
+erase   - erase FLASH memory
+flinfo  - print FLASH memory information
+go      - start application at address 'addr'
+help    - print online help
+iminfo  - print header information for application image
+loadb   - load binary file over serial line (kermit mode)
+loads   - load S-Record file over serial line
+loop    - infinite loop on address range
+md      - memory display
+mm      - memory modify (auto-incrementing)
+mtest   - simple RAM test
+mw      - memory write (fill)
+nm      - memory modify (constant address)
+printenv- print environment variables
+protect - enable or disable FLASH write protection
+rarpboot- boot image via network using RARP/TFTP protocol
+reset   - Perform RESET of the CPU
+run     - run commands in an environment variable
+saveenv - save environment variables to persistent storage
+setenv  - set environment variables
+sleep   - delay execution for some time
+tftpboot- boot image via network using TFTP protocol
+               and env variables ipaddr and serverip
+version - print monitor version
+?       - alias for 'help'
+
+##################################################
+# Environment Variables (CFG_ENV_IS_IN_NVRAM)
+##############################
+
+LEOX_elpt860: printenv
+bootdelay=5
+loads_echo=1
+baudrate=9600
+stdin=serial
+stdout=serial
+stderr=serial
+ethaddr=00:03:ca:00:64:df
+ipaddr=192.168.0.30
+netmask=255.255.255.0
+serverip=192.168.0.1
+nfsserverip=192.168.0.1
+preboot=echo;echo Type "run nfsboot" to mount root filesystem over NFS;echo
+gatewayip=192.168.0.1
+ramargs=setenv bootargs root=/dev/ram rw
+rootargs=setenv rootpath /tftp/$(ipaddr)
+nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(nfsserverip):$(rootpath)
+addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(nfsserverip):$(gatewayip):$(netmask):$(hostname):eth0:
+ramboot=tftp 400000 /home/leox/pMulti;run ramargs;bootm
+nfsboot=tftp 400000 /home/leox/uImage;run rootargs;run nfsargs;run addip;bootm
+bootcmd=run ramboot
+clocks_in_mhz=1
+
+Environment size: 730/16380 bytes
+
+##################################################
+# Flash Memory Information
+##############################
+
+LEOX_elpt860: flinfo
+
+Bank # 1: AMD AM29F040   (4 Mbits)
+  Size: 512 KB in 8 Sectors
+  Sector Start Addresses:
+    02000000 (RO) 02010000 (RO) 02020000 (RO) 02030000 (RO) 02040000     
+    02050000      02060000      02070000     
+
+##################################################
+# Board Information Structure
+##############################
+
+LEOX_elpt860: bdinfo
+memstart    = 0x00000000
+memsize     = 0x01000000
+flashstart  = 0x02000000
+flashsize   = 0x00080000
+flashoffset = 0x00030000
+sramstart   = 0x00000000
+sramsize    = 0x00000000
+immr_base   = 0xFF000000
+bootflags   = 0x00000001
+intfreq     =     50 MHz
+busfreq     =     50 MHz
+ethaddr     = 00:03:ca:00:64:df
+IP addr     = 192.168.0.30
+baudrate    =   9600 bps
+
+##################################################
+# Image Download and run over serial port
+#    hello_world (S-Record image)
+#    ===> 1) Enter "loads" command into U-Boot monitor
+#    ===> 2) From TeraTerm's bar menu, Select 'File/Send file...'
+#            Then select 'hello_world.srec' with the file browser
+##############################
+
+U-Boot 0.2.2 (Jan 19 2003 - 11:08:39)
+
+CPU:   XPC860xxZPnnB at 50 MHz: 4 kB I-Cache 4 kB D-Cache FEC present
+         *** Warning: CPU Core has Silicon Bugs -- Check the Errata ***
+Board: ### No HW ID - assuming ELPT860
+DRAM:  16 MB
+FLASH: 512 kB
+In:    serial
+Out:   serial
+Err:   serial
+Net:   SCC ETHERNET
+
+Type "run nfsboot" to mount root filesystem over NFS
+
+Hit any key to stop autoboot:  0
+LEOX_elpt860: loads
+## Ready for S-Record download ...
+S804040004F3050154000501709905014C000501388D
+## First Load Addr = 0x00040000
+## Last  Load Addr = 0x0005018B
+## Total Size      = 0x0001018C = 65932 Bytes
+## Start Addr      = 0x00040004
+LEOX_elpt860: go 40004 This is a test !!!
+## Starting application at 0x00040004 ...
+Hello World
+argc = 6
+argv[0] = "40004"
+argv[1] = "This"
+argv[2] = "is"
+argv[3] = "a"
+argv[4] = "test"
+argv[5] = "!!!"
+argv[6] = "<NULL>"
+Hit any key to exit ...
+
+## Application terminated, rc = 0x0
+
+##################################################
+# Image download and run over ethernet interface
+#    Linux-2.4.4 (uImage) + Root filesystem mounted over NFS
+##############################
+
+U-Boot 0.2.2 (Jan 19 2003 - 11:08:39)
+
+CPU:   XPC860xxZPnnB at 50 MHz: 4 kB I-Cache 4 kB D-Cache FEC present
+         *** Warning: CPU Core has Silicon Bugs -- Check the Errata ***
+Board: ### No HW ID - assuming ELPT860
+DRAM:  16 MB
+FLASH: 512 kB
+In:    serial
+Out:   serial
+Err:   serial
+Net:   SCC ETHERNET
+
+Type "run nfsboot" to mount root filesystem over NFS
+
+Hit any key to stop autoboot:  0
+LEOX_elpt860: run nfsboot
+ARP broadcast 1
+TFTP from server 192.168.0.1; our IP address is 192.168.0.30
+Filename '/home/leox/uImage'.
+Load address: 0x400000
+Loading: #################################################################
+         #############################
+done
+Bytes transferred = 477294 (7486e hex)
+## Booting image at 00400000 ...
+   Image Name:   Linux-2.4.4
+   Image Type:   PowerPC Linux Kernel Image (gzip compressed)
+   Data Size:    477230 Bytes = 466 kB = 0 MB
+   Load Address: 00000000
+   Entry Point:  00000000
+   Verifying Checksum ... OK
+   Uncompressing Kernel Image ... OK
+Linux version 2.4.4-rthal5 (leox@p5ak6650) (gcc version 2.95.3 20010315 (release/MontaVista)) #1 Wed Jul 3 10:23:53 CEST 2002
+On node 0 totalpages: 4096
+zone(0): 4096 pages.
+zone(1): 0 pages.
+zone(2): 0 pages.
+Kernel command line: root=/dev/nfs rw nfsroot=192.168.0.1:/tftp/192.168.0.30 ip=192.168.0.30:192.168.0.1:192.168.0.1:255.255.255.0::eth0:
+rtsched version <20010618.1050.24>
+Decrementer Frequency: 3125000
+Warning: real time clock seems stuck!
+Calibrating delay loop... 49.76 BogoMIPS
+Memory: 14720k available (928k kernel code, 384k data, 44k init, 0k highmem)
+Dentry-cache hash table entries: 2048 (order: 2, 16384 bytes)
+Buffer-cache hash table entries: 1024 (order: 0, 4096 bytes)
+Page-cache hash table entries: 4096 (order: 2, 16384 bytes)
+Inode-cache hash table entries: 1024 (order: 1, 8192 bytes)
+POSIX conformance testing by UNIFIX
+Linux NET4.0 for Linux 2.4
+Based upon Swansea University Computer Society NET3.039
+Starting kswapd v1.8
+CPM UART driver version 0.03
+ttyS0 on SMC1 at 0x0280, BRG1
+block: queued sectors max/low 9701kB/3233kB, 64 slots per queue
+RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize
+eth0: CPM ENET Version 0.2 on SCC1, 00:03:ca:00:64:df
+NET4: Linux TCP/IP 1.0 for NET4.0
+IP Protocols: ICMP, UDP, TCP
+IP: routing cache hash table of 512 buckets, 4Kbytes
+TCP: Hash tables configured (established 1024 bind 1024)
+NET4: Unix domain sockets 1.0/SMP for Linux NET4.0.
+Looking up port of RPC 100003/2 on 192.168.0.1
+Looking up port of RPC 100005/2 on 192.168.0.1
+VFS: Mounted root (nfs filesystem).
+Freeing unused kernel memory: 44k init
+INIT: version 2.78 booting
+                Welcome to DENX Embedded Linux Environment
+                Press 'I' to enter interactive startup.
+Mounting proc filesystem:  [  OK  ]
+Configuring kernel parameters:  [  OK  ]
+Cannot access the Hardware Clock via any known method.
+Use the --debug option to see the details of our search for an access method.
+Setting clock : Wed Dec 31 19:00:11 EST 1969 [  OK  ]
+Activating swap partitions:  [  OK  ]
+Setting hostname 192.168.0.30:  [  OK  ]
+Finding module dependencies:
+[  OK  ]
+Checking filesystems
+Checking all file systems.
+[  OK  ]
+Mounting local filesystems:  [  OK  ]
+Enabling swap space:  [  OK  ]
+INIT: Entering runlevel: 3
+Entering non-interactive startup
+Starting system logger: [  OK  ]
+Starting kernel logger: [  OK  ]
+Starting xinetd: [  OK  ]
+
+192 login: root
+Last login: Wed Dec 31 19:00:41 on ttyS0
+bash-2.04#
+
+##################################################
+# Image download and run over ethernet interface
+#    Linux-2.4.4 + Root filesystem mounted from RAM (pMulti)
+##############################
+
+U-Boot 0.2.2 (Jan 19 2003 - 11:08:39)
+
+CPU:   XPC860xxZPnnB at 50 MHz: 4 kB I-Cache 4 kB D-Cache FEC present
+         *** Warning: CPU Core has Silicon Bugs -- Check the Errata ***
+Board: ### No HW ID - assuming ELPT860
+DRAM:  16 MB
+FLASH: 512 kB
+In:    serial
+Out:   serial
+Err:   serial
+Net:   SCC ETHERNET
+
+Type "run nfsboot" to mount root filesystem over NFS
+
+Hit any key to stop autoboot:  0
+LEOX_elpt860: run ramboot
+ARP broadcast 1
+TFTP from server 192.168.0.1; our IP address is 192.168.0.30
+Filename '/home/leox/pMulti'.
+Load address: 0x400000
+Loading: #################################################################
+         #################################################################
+         #################################################################
+         #################################################################
+         #################################################################
+         ########################################################
+done
+Bytes transferred = 1947816 (1db8a8 hex)
+## Booting image at 00400000 ...
+   Image Name:   linux-2.4.4-2002-03-21 Multiboot
+   Image Type:   PowerPC Linux Multi-File Image (gzip compressed)
+   Data Size:    1947752 Bytes = 1902 kB = 1 MB
+   Load Address: 00000000
+   Entry Point:  00000000
+   Contents:
+   Image 0:   477230 Bytes = 466 kB = 0 MB
+   Image 1:  1470508 Bytes = 1436 kB = 1 MB
+   Verifying Checksum ... OK
+   Uncompressing Multi-File Image ... OK
+   Loading Ramdisk to 00e44000, end 00fab02c ... OK
+Linux version 2.4.4-rthal5 (leox@p5ak6650) (gcc version 2.95.3 20010315 (release/MontaVista)) #1 Wed Jul 3 10:23:53 CEST 2002
+On node 0 totalpages: 4096
+zone(0): 4096 pages.
+zone(1): 0 pages.
+zone(2): 0 pages.
+Kernel command line: root=/dev/ram rw
+rtsched version <20010618.1050.24>
+Decrementer Frequency: 3125000
+Warning: real time clock seems stuck!
+Calibrating delay loop... 49.76 BogoMIPS
+Memory: 13280k available (928k kernel code, 384k data, 44k init, 0k highmem)
+Dentry-cache hash table entries: 2048 (order: 2, 16384 bytes)
+Buffer-cache hash table entries: 1024 (order: 0, 4096 bytes)
+Page-cache hash table entries: 4096 (order: 2, 16384 bytes)
+Inode-cache hash table entries: 1024 (order: 1, 8192 bytes)
+POSIX conformance testing by UNIFIX
+Linux NET4.0 for Linux 2.4
+Based upon Swansea University Computer Society NET3.039
+Starting kswapd v1.8
+CPM UART driver version 0.03
+ttyS0 on SMC1 at 0x0280, BRG1
+block: queued sectors max/low 8741kB/2913kB, 64 slots per queue
+RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize
+eth0: CPM ENET Version 0.2 on SCC1, 00:03:ca:00:64:df
+RAMDISK: Compressed image found at block 0
+Freeing initrd memory: 1436k freed
+NET4: Linux TCP/IP 1.0 for NET4.0
+IP Protocols: ICMP, UDP, TCP
+IP: routing cache hash table of 512 buckets, 4Kbytes
+TCP: Hash tables configured (established 1024 bind 1024)
+IP-Config: Incomplete network configuration information.
+NET4: Unix domain sockets 1.0/SMP for Linux NET4.0.
+VFS: Mounted root (ext2 filesystem).
+Freeing unused kernel memory: 44k iné
+init started:  BusyBox v0.60.2 (2002.07.01-12:06+0000) multi-call Configuring hostname
+Configuring lo...
+Configuring eth0...
+Configuring Gateway...
+
+Please press Enter to activate this console.
+
+ELPT860 login: root
+Password:
+Welcome to Linux-2.4.4 for ELPT CPU board (MPC860T @ 50MHz)
+
+                                              a8888b.
+                                             d888888b.
+                                             8P"YP"Y88
+     _      _                                8|o||o|88
+    | |    |_|                               8'    .88
+    | |     _ ____  _   _  _  _              8`._.' Y8.
+    | |    | |  _ \| | | |\ \/ /            d/      `8b.
+    | |___ | | | | | |_| |/    \          .dP   .     Y8b.
+    |_____||_|_| |_|\____|\_/\_/         d8:'   "   `::88b.
+                                        d8"           `Y88b
+                                       :8P     '       :888
+                                        8a.    :      _a88P
+                                      ._/"Yaa_ :    .| 88P|
+                                      \    YP"      `| 8P  `.
+                                      /     \._____.d|    .'
+                                      `--..__)888888P`._.'
+login[21]: root login  on `ttyS0'
+
+
+
+BusyBox v0.60.3 (2002.07.20-10:39+0000) Built-in shell (ash)
+Enter 'help' for a list of built-in commands.
+
+root@ELPT860:~ #
--- a/board/LEOX/elpt860/config.mk
+++ b/board/LEOX/elpt860/config.mk
@@ -0,0 +1,36 @@
+#######################################################################
+#
+# Copyright (C) 2000, 2001, 2002, 2003
+# The LEOX team <team@leox.org>, http://www.leox.org
+#
+# LEOX.org is about the development of free hardware and software resources
+#   for system on chip.
+#
+# Description: U-Boot port on the LEOX's ELPT860 CPU board
+# ~~~~~~~~~~~
+#
+#######################################################################
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+#######################################################################
+
+#
+# ELPT860 board
+#
+
+TEXT_BASE = 0x02000000
+#TEXT_BASE = 0x00FB0000
--- a/board/LEOX/elpt860/elpt860.c
+++ b/board/LEOX/elpt860/elpt860.c
@@ -0,0 +1,399 @@
+/*
+**=====================================================================
+**
+** Copyright (C) 2000, 2001, 2002, 2003
+** The LEOX team <team@leox.org>, http://www.leox.org
+**
+** LEOX.org is about the development of free hardware and software resources
+**   for system on chip.
+**
+** Description: U-Boot port on the LEOX's ELPT860 CPU board
+** ~~~~~~~~~~~
+**
+**=====================================================================
+**
+** This program is free software; you can redistribute it and/or
+** modify it under the terms of the GNU General Public License as
+** published by the Free Software Foundation; either version 2 of
+** the License, or (at your option) any later version.
+**
+** This program is distributed in the hope that it will be useful,
+** but WITHOUT ANY WARRANTY; without even the implied warranty of
+** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+** GNU General Public License for more details.
+**
+** You should have received a copy of the GNU General Public License
+** along with this program; if not, write to the Free Software
+** Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+** MA 02111-1307 USA
+**
+**=====================================================================
+*/
+
+/*
+** Note 1: In this file, you have to provide the following functions:
+** ------
+**              int             board_pre_init(void)
+**              int             checkboard(void)
+**              long int        initdram(int board_type)
+** called from 'board_init_f()' into 'common/board.c'
+**
+**              void            reset_phy(void)
+** called from 'board_init_r()' into 'common/board.c'
+*/
+
+#include <common.h>
+#include <mpc8xx.h>
+
+/* ------------------------------------------------------------------------- */
+
+static long int dram_size (long int, long int *, long int);
+
+/* ------------------------------------------------------------------------- */
+
+#define	_NOT_USED_	0xFFFFFFFF
+
+const uint init_sdram_table[] =
+{
+  /*
+   * Single Read. (Offset 0 in UPMA RAM)
+   */
+  0x0FFCCC04, 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04,
+  0xFFFFFC04, /* last */
+  /*
+   * SDRAM Initialization (offset 5 in UPMA RAM)
+   *
+   * This is no UPM entry point. The following definition uses
+   * the remaining space to establish an initialization
+   * sequence, which is executed by a RUN command.
+   *
+   */
+  0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04,  /* last */
+  /*
+   * Burst Read. (Offset 8 in UPMA RAM)
+   */
+  0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
+  0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
+  0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04,
+  0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, /* last */
+  /*
+   * Single Write. (Offset 18 in UPMA RAM)
+   */
+  0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04,
+  0xFFFFFC04, 0xFFFFFC04, 0x0FFFFC04, 0xFFFFFC04, /* last */
+  /*
+   * Burst Write. (Offset 20 in UPMA RAM)
+   */
+  0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
+  0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04,
+  0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC34, 0x0FAC0C34,
+  0xFFFFFC05, 0xFFFFFC04, 0x0FFCFC04, 0xFFFFFC05, /* last */
+};
+
+const uint sdram_table[] =
+{
+  /*
+   * Single Read. (Offset 0 in UPMA RAM)
+   */
+  0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF3C04, 
+  0xFF0FFC00, /* last */
+  /*
+   * SDRAM Initialization (offset 5 in UPMA RAM)
+   *
+   * This is no UPM entry point. The following definition uses
+   * the remaining space to establish an initialization
+   * sequence, which is executed by a RUN command.
+   *
+   */
+  0x0FFCCC04, 0xFFAFFC05, 0xFFAFFC05, /* last */
+  /*
+   * Burst Read. (Offset 8 in UPMA RAM)
+   */
+  0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF3C04, 
+  0xF00FFC00, 0xF00FFC00, 0xF00FFC00, 0xFF0FFC00,
+  0x0FFCCC04, 0xFFAFFC05, 0xFFAFFC04, 0xFFAFFC04, 
+  0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, /* last */
+  /*
+   * Single Write. (Offset 18 in UPMA RAM)
+   */
+  0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF0C00, 
+  0xFF0FFC04, 0x0FFCCC04, 0xFFAFFC05, /* last */
+  _NOT_USED_, 
+  /*
+   * Burst Write. (Offset 20 in UPMA RAM)
+   */
+  0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC00, 0x00AF0C00, 
+  0xF00FFC00, 0xF00FFC00, 0xF00FFC04, 0x0FFCCC04, 
+  0xFFAFFC04, 0xFFAFFC05, 0xFFAFFC04, 0xFFAFFC04, 
+  0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, /* last */
+  /*
+   * Refresh  (Offset 30 in UPMA RAM)
+   */
+  0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, 
+  0xFFFFFC05, 0xFFFFFC04, 0xFFFFFC05, _NOT_USED_, 
+  0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, /* last */
+  /*
+   * Exception. (Offset 3c in UPMA RAM)
+   */
+  0x0FFFFC34, 0x0FAC0C34, 0xFFFFFC05, 0xFFAFFC04, /* last */
+};
+
+/* ------------------------------------------------------------------------- */
+
+#define CFG_PC4    0x0800
+
+#define CFG_DS1    CFG_PC4
+
+/*
+ * Very early board init code (fpga boot, etc.)
+ */
+int
+board_pre_init (void)
+{
+  volatile immap_t *immr = (immap_t *) CFG_IMMR;
+
+  /* 
+   * Light up the red led on ELPT860 pcb (DS1) (PCDAT) 
+   */
+  immr->im_ioport.iop_pcdat &= ~CFG_DS1;   /* PCDAT (DS1 = 0)                */
+  immr->im_ioport.iop_pcpar &= ~CFG_DS1;   /* PCPAR (0=general purpose I/O)  */
+  immr->im_ioport.iop_pcdir |=  CFG_DS1;   /* PCDIR (I/O: 0=input, 1=output) */
+
+  return ( 0 );    /* success */
+}
+
+/*
+ * Check Board Identity:
+ *
+ * Test ELPT860 ID string
+ *
+ * Return 1 if no second DRAM bank, otherwise returns 0
+ */
+
+int 
+checkboard (void)
+{
+    unsigned char *s = getenv("serial#");
+
+    if ( !s || strncmp(s, "ELPT860", 7) )
+      printf ("### No HW ID - assuming ELPT860\n");
+    
+    return ( 0 );    /* success */
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int 
+initdram (int board_type)
+{
+    volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+    volatile memctl8xx_t *memctl = &immap->im_memctl;
+    long int              size8, size9;
+    long int              size_b0 = 0;
+
+    /*
+     * This sequence initializes SDRAM chips on ELPT860 board
+     */
+    upmconfig(UPMA, (uint *)init_sdram_table, 
+	      sizeof(init_sdram_table)/sizeof(uint));
+
+    memctl->memc_mptpr = 0x0200;
+    memctl->memc_mamr  = 0x18002111;
+
+    memctl->memc_mar   = 0x00000088;
+    memctl->memc_mcr   = 0x80002000;	/* CS1: SDRAM bank 0 */
+
+    upmconfig(UPMA, (uint *)sdram_table, 
+	      sizeof(sdram_table)/sizeof(uint));
+
+    /*
+     * Preliminary prescaler for refresh (depends on number of
+     * banks): This value is selected for four cycles every 62.4 us
+     * with two SDRAM banks or four cycles every 31.2 us with one
+     * bank. It will be adjusted after memory sizing.
+     */
+    memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
+
+    /*
+     * The following value is used as an address (i.e. opcode) for
+     * the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If
+     * the port size is 32bit the SDRAM does NOT "see" the lower two
+     * address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for
+     * MICRON SDRAMs:
+     * ->    0 00 010 0 010
+     *       |  |   | |   +- Burst Length = 4
+     *       |  |   | +----- Burst Type   = Sequential
+     *       |  |   +------- CAS Latency  = 2
+     *       |  +----------- Operating Mode = Standard
+     *       +-------------- Write Burst Mode = Programmed Burst Length
+     */
+    memctl->memc_mar   = 0x00000088;
+
+    /*
+     * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
+     * preliminary addresses - these have to be modified after the
+     * SDRAM size has been determined.
+     */
+    memctl->memc_or1   = CFG_OR1_PRELIM;
+    memctl->memc_br1   = CFG_BR1_PRELIM;
+
+    memctl->memc_mamr  = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
+
+    udelay (200);
+
+    /* perform SDRAM initializsation sequence */
+
+    memctl->memc_mcr   = 0x80002105;	/* CS1: SDRAM bank 0 */
+    udelay (1);
+    memctl->memc_mcr   = 0x80002230;	/* CS1: SDRAM bank 0 - execute twice */
+    udelay (1);
+
+    memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
+
+    udelay (1000);
+
+    /*
+     * Check Bank 0 Memory Size for re-configuration
+     *
+     * try 8 column mode
+     */
+    size8 = dram_size (CFG_MAMR_8COL, 
+		       (ulong *) SDRAM_BASE1_PRELIM, 
+		       SDRAM_MAX_SIZE);
+
+    udelay (1000);
+
+    /*
+     * try 9 column mode
+     */
+    size9 = dram_size (CFG_MAMR_9COL, 
+		       (ulong *) SDRAM_BASE1_PRELIM, 
+		       SDRAM_MAX_SIZE);
+
+    if ( size8 < size9 )    /* leave configuration at 9 columns	*/
+      {
+	size_b0 = size9;
+	/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */
+      } 
+    else                  /* back to 8 columns			*/
+      {
+	size_b0 = size8;
+	memctl->memc_mamr = CFG_MAMR_8COL;
+	udelay (500);
+	/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */
+      }
+    
+    udelay (1000);
+
+    /*
+     * Adjust refresh rate depending on SDRAM type, both banks
+     * For types > 128 MBit leave it at the current (fast) rate
+     */
+    if ( size_b0 < 0x02000000 ) 
+      {
+	/* reduce to 15.6 us (62.4 us / quad) */
+	memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
+	udelay (1000);
+      }
+
+    /*
+     * Final mapping: map bigger bank first
+     */
+    memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
+    memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+
+    {
+      unsigned long reg;
+      
+      /* adjust refresh rate depending on SDRAM type, one bank */
+      reg = memctl->memc_mptpr;
+      reg >>= 1;	/* reduce to CFG_MPTPR_1BK_8K / _4K */
+      memctl->memc_mptpr = reg;
+    }
+
+    udelay(10000);
+    
+    return (size_b0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+
+static long int 
+dram_size (long int   mamr_value, 
+	   long int  *base, 
+	   long int   maxsize)
+{
+  volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+  volatile memctl8xx_t *memctl = &immap->im_memctl;
+  volatile long int    *addr;
+  ulong                 cnt, val;
+  ulong                 save[32];    /* to make test non-destructive */
+  unsigned char         i = 0;
+  
+  memctl->memc_mamr = mamr_value;
+  
+  for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) 
+    {
+      addr = base + cnt;    /* pointer arith! */
+      
+      save[i++] = *addr;
+      *addr     = ~cnt;
+    }
+  
+  /* write 0 to base address */
+  addr    = base;
+  save[i] = *addr;
+  *addr   = 0;
+  
+  /* check at base address */
+  if ( (val = *addr) != 0 ) 
+    {
+      *addr = save[i];
+
+      return (0);
+    }
+  
+  for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1) 
+    {
+      addr = base + cnt;    /* pointer arith! */
+      
+      val   = *addr;
+      *addr = save[--i];
+      
+      if ( val != (~cnt) ) 
+	{
+	  return (cnt * sizeof(long));
+	}
+    }
+
+  return (maxsize);
+}
+
+/* ------------------------------------------------------------------------- */
+
+#define CFG_PA1     0x4000
+#define CFG_PA2     0x2000
+
+#define CFG_LBKs    (CFG_PA2 | CFG_PA1)
+
+void
+reset_phy (void)
+{
+  volatile immap_t *immr = (immap_t *) CFG_IMMR;
+  
+  /*
+   * Ensure LBK LXT901 ethernet 1 & 2 = 0 ... for normal loopback in effect
+   *                                          and no AUI loopback
+   */
+  immr->im_ioport.iop_padat &= ~CFG_LBKs;  /* PADAT (LBK eth 1&2 = 0)        */
+  immr->im_ioport.iop_papar &= ~CFG_LBKs;  /* PAPAR (0=general purpose I/O)  */
+  immr->im_ioport.iop_padir |=  CFG_LBKs;  /* PADIR (I/O: 0=input, 1=output) */
+}
--- a/board/LEOX/elpt860/flash.c
+++ b/board/LEOX/elpt860/flash.c
@@ -0,0 +1,615 @@
+/*
+**=====================================================================
+**
+** Copyright (C) 2000, 2001, 2002, 2003
+** The LEOX team <team@leox.org>, http://www.leox.org
+**
+** LEOX.org is about the development of free hardware and software resources
+**   for system on chip.
+**
+** Description: U-Boot port on the LEOX's ELPT860 CPU board
+** ~~~~~~~~~~~
+**
+**=====================================================================
+**
+** This program is free software; you can redistribute it and/or
+** modify it under the terms of the GNU General Public License as
+** published by the Free Software Foundation; either version 2 of
+** the License, or (at your option) any later version.
+**
+** This program is distributed in the hope that it will be useful,
+** but WITHOUT ANY WARRANTY; without even the implied warranty of
+** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+** GNU General Public License for more details.
+**
+** You should have received a copy of the GNU General Public License
+** along with this program; if not, write to the Free Software
+** Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+** MA 02111-1307 USA
+**
+**=====================================================================
+*/
+
+/*
+** Note 1: In this file, you have to provide the following variable:
+** ------
+**              flash_info_t    flash_info[CFG_MAX_FLASH_BANKS]
+** 'flash_info_t' structure is defined into 'include/flash.h'
+** and defined as extern into 'common/cmd_flash.c'
+**
+** Note 2: In this file, you have to provide the following functions:
+** ------
+**              unsigned long   flash_init(void)
+** called from 'board_init_r()' into 'common/board.c'
+**
+**              void            flash_print_info(flash_info_t *info)
+** called from 'do_flinfo()' into 'common/cmd_flash.c'
+**
+**              int             flash_erase(flash_info_t *info,
+**                                          int           s_first,
+**                                          int           s_last)
+** called from 'do_flerase()' & 'flash_sect_erase()' into 'common/cmd_flash.c'
+**
+**              int             write_buff (flash_info_t *info,
+**                                          uchar        *src,
+**                                          ulong         addr,
+**                                          ulong         cnt)
+** called from 'flash_write()' into 'common/cmd_flash.c'
+*/
+
+#include <common.h>
+#include <mpc8xx.h>
+
+
+#ifndef	CFG_ENV_ADDR
+#  define CFG_ENV_ADDR	(CFG_FLASH_BASE + CFG_ENV_OFFSET)
+#endif
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+/*-----------------------------------------------------------------------
+ * Internal Functions
+ */
+static void   flash_get_offsets (ulong base, flash_info_t *info);
+static ulong  flash_get_size (volatile unsigned char *addr, flash_info_t *info);
+
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static int write_byte (flash_info_t *info, ulong dest, uchar data);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long 
+flash_init (void)
+{
+  volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+  volatile memctl8xx_t *memctl = &immap->im_memctl;
+  unsigned long         size_b0;
+  int i;
+  
+  /* Init: no FLASHes known */
+  for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) 
+    {
+      flash_info[i].flash_id = FLASH_UNKNOWN;
+    }
+  
+  /* Static FLASH Bank configuration here - FIXME XXX */
+  
+  size_b0 = flash_get_size ((volatile unsigned char *)FLASH_BASE0_PRELIM, 
+			    &flash_info[0]);
+  
+  if ( flash_info[0].flash_id == FLASH_UNKNOWN ) 
+    {
+      printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+	      size_b0, size_b0<<20);
+    }
+  
+  /* Remap FLASH according to real size */
+  memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK);
+  memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_PS_8 | BR_V;
+  
+  /* Re-do sizing to get full correct info */
+  size_b0 = flash_get_size ((volatile unsigned char *)CFG_FLASH_BASE, 
+			    &flash_info[0]);
+  
+  flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+  
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+  /* monitor protection ON by default */
+  flash_protect (FLAG_PROTECT_SET,
+		 CFG_MONITOR_BASE,
+		 CFG_MONITOR_BASE + CFG_MONITOR_LEN-1,
+		 &flash_info[0]);
+#endif
+  
+#ifdef	CFG_ENV_IS_IN_FLASH
+  /* ENV protection ON by default */
+  flash_protect(FLAG_PROTECT_SET,
+		CFG_ENV_ADDR,
+		CFG_ENV_ADDR + CFG_ENV_SIZE-1,
+		&flash_info[0]);
+#endif
+
+  flash_info[0].size = size_b0;
+  
+  return (size_b0);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void 
+flash_get_offsets (ulong          base, 
+		   flash_info_t  *info)
+{
+  int i;
+
+#define SECTOR_64KB    0x00010000
+
+  /* set up sector start adress table */
+  for (i = 0; i < info->sector_count; i++) 
+    {
+      info->start[i] = base + (i * SECTOR_64KB);
+    }
+}
+
+/*-----------------------------------------------------------------------
+ */
+void 
+flash_print_info (flash_info_t *info)
+{
+  int i;
+  
+  if ( info->flash_id == FLASH_UNKNOWN ) 
+    {
+      printf ("missing or unknown FLASH type\n");
+      return;
+    }
+
+  switch ( info->flash_id & FLASH_VENDMASK ) 
+    {
+    case FLASH_MAN_AMD:	printf ("AMD ");		break;
+    case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+    case FLASH_MAN_STM: printf ("STM (Thomson) ");      break;
+    default:		printf ("Unknown Vendor ");	break;
+    }
+  
+  switch ( info->flash_id & FLASH_TYPEMASK ) 
+    {
+    case FLASH_AM040:   printf ("AM29F040   (4 Mbits)\n");
+      break;
+    default:	        printf ("Unknown Chip Type\n");
+      break;
+    }
+  
+  printf ("  Size: %ld KB in %d Sectors\n", 
+	  info->size >> 10, info->sector_count);
+  
+  printf ("  Sector Start Addresses:");
+  for (i=0; i<info->sector_count; ++i) 
+    {
+      if ((i % 5) == 0)
+	printf ("\n   ");
+      printf (" %08lX%s",
+	      info->start[i],
+	      info->protect[i] ? " (RO)" : "     "
+	      );
+    }
+  printf ("\n");
+
+  return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong 
+flash_get_size (volatile unsigned char *addr, 
+                flash_info_t           *info)
+{
+  short i;
+  uchar value;
+  ulong base = (ulong)addr;
+
+  /* Write auto select command: read Manufacturer ID */
+  addr[0x0555] = 0xAA;
+  addr[0x02AA] = 0x55;
+  addr[0x0555] = 0x90;
+  
+  value = addr[0];
+
+  switch ( value ) 
+    {
+      /*    case AMD_MANUFACT: */
+    case 0x01:
+      info->flash_id = FLASH_MAN_AMD;
+      break;
+      /*    case FUJ_MANUFACT: */
+    case 0x04:
+      info->flash_id = FLASH_MAN_FUJ;
+      break;
+      /*    case STM_MANUFACT: */
+    case 0x20:
+      info->flash_id = FLASH_MAN_STM;
+      break;
+
+    default:
+      info->flash_id = FLASH_UNKNOWN;
+      info->sector_count = 0;
+      info->size = 0;
+      return (0);			/* no or unknown flash	*/
+    }
+  
+  value = addr[1];			/* device ID		*/
+  
+  switch ( value ) 
+    {
+    case STM_ID_F040B:
+    case AMD_ID_F040B:
+      info->flash_id += FLASH_AM040;    /* 4 Mbits = 512k * 8  */
+      info->sector_count = 8;
+      info->size = 0x00080000;
+      break;
+
+    default:
+      info->flash_id = FLASH_UNKNOWN;
+      return (0);			/* => no or unknown flash */
+    }
+
+  /* set up sector start adress table */
+  for (i = 0; i < info->sector_count; i++) 
+    {
+      info->start[i] = base + (i * 0x00010000);
+    }
+  
+  /* check for protected sectors */
+  for (i = 0; i < info->sector_count; i++) 
+    {
+      /* read sector protection at sector address, (A7 .. A0) = 0x02 */
+      /* D0 = 1 if protected */
+      addr = (volatile unsigned char *)(info->start[i]);
+      info->protect[i] = addr[2] & 1;
+    }
+
+  /*
+   * Prevent writes to uninitialized FLASH.
+   */
+  if ( info->flash_id != FLASH_UNKNOWN ) 
+    {
+      addr = (volatile unsigned char *)info->start[0];
+      
+      *addr = 0xF0;	/* reset bank */
+    }
+  
+  return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int
+flash_erase (flash_info_t  *info, 
+	     int            s_first, 
+	     int            s_last)
+{
+  volatile unsigned char *addr = (volatile unsigned char *)(info->start[0]);
+  int flag, prot, sect, l_sect;
+  ulong start, now, last;
+  
+  if ( (s_first < 0) || (s_first > s_last) ) 
+    {
+      if ( info->flash_id == FLASH_UNKNOWN ) 
+	{
+	  printf ("- missing\n");
+	} 
+      else 
+	{
+	  printf ("- no sectors to erase\n");
+	}
+      return ( 1 );
+    }
+
+  if ( (info->flash_id == FLASH_UNKNOWN) ||
+       (info->flash_id > FLASH_AMD_COMP) ) 
+    {
+      printf ("Can't erase unknown flash type %08lx - aborted\n",
+	      info->flash_id);
+      return ( 1 );
+    }
+  
+  prot = 0;
+  for (sect=s_first; sect<=s_last; ++sect) 
+    {
+      if ( info->protect[sect] ) 
+	{
+	  prot++;
+	}
+    }
+  
+  if ( prot ) 
+    {
+      printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+    } 
+  else 
+    {
+      printf ("\n");
+    }
+  
+  l_sect = -1;
+  
+  /* Disable interrupts which might cause a timeout here */
+  flag = disable_interrupts();
+  
+  addr[0x0555] = 0xAA;
+  addr[0x02AA] = 0x55;
+  addr[0x0555] = 0x80;
+  addr[0x0555] = 0xAA;
+  addr[0x02AA] = 0x55;
+  
+  /* Start erase on unprotected sectors */
+  for (sect = s_first; sect<=s_last; sect++) 
+    {
+      if (info->protect[sect] == 0)    /* not protected */
+	{
+	  addr = (volatile unsigned char *)(info->start[sect]);
+	  addr[0] = 0x30;
+	  l_sect = sect;
+	}
+    }
+  
+  /* re-enable interrupts if necessary */
+  if ( flag )
+    enable_interrupts();
+  
+  /* wait at least 80us - let's wait 1 ms */
+  udelay (1000);
+  
+  /*
+   * We wait for the last triggered sector
+   */
+  if ( l_sect < 0 )
+    goto DONE;
+  
+  start = get_timer (0);
+  last  = start;
+  addr = (volatile unsigned char *)(info->start[l_sect]);
+  while ( (addr[0] & 0x80) != 0x80 ) 
+    {
+      if ( (now = get_timer(start)) > CFG_FLASH_ERASE_TOUT ) 
+	{
+	  printf ("Timeout\n");
+	  return ( 1 );
+	}
+      /* show that we're waiting */
+      if ( (now - last) > 1000 )     /* every second */
+	{
+	  putc ('.');
+	  last = now;
+	}
+    }
+  
+DONE:
+  /* reset to read mode */
+  addr = (volatile unsigned char *)info->start[0];
+  addr[0] = 0xF0;	/* reset bank */
+  
+  printf (" done\n");
+  
+  return ( 0 );
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int 
+write_buff (flash_info_t  *info, 
+	    uchar         *src, 
+	    ulong          addr, 
+	    ulong          cnt)
+{
+  ulong cp, wp, data;
+  uchar bdata;
+  int i, l, rc;
+
+  if ( (info->flash_id & FLASH_TYPEMASK) == FLASH_AM040 )
+    {
+      /* Width of the data bus: 8 bits */
+
+      wp = addr;
+      
+      while ( cnt )
+	{
+	  bdata = *src++;
+	  
+	  if ( (rc = write_byte(info, wp, bdata)) != 0 )
+	    {
+	      return (rc);
+	    }
+	  
+	  ++wp;
+	  --cnt;
+	}
+
+      return ( 0 );
+    }
+  else
+    {
+      /* Width of the data bus: 32 bits */
+
+      wp = (addr & ~3);	/* get lower word aligned address */
+      
+      /*
+       * handle unaligned start bytes
+       */
+      if ( (l = addr - wp) != 0 ) 
+	{
+	  data = 0;
+	  for (i=0, cp=wp; i<l; ++i, ++cp) 
+	    {
+	      data = (data << 8) | (*(uchar *)cp);
+	    }
+	  for (; i<4 && cnt>0; ++i) 
+	    {
+	      data = (data << 8) | *src++;
+	      --cnt;
+	      ++cp;
+	    }
+	  for (; cnt==0 && i<4; ++i, ++cp) 
+	    {
+	      data = (data << 8) | (*(uchar *)cp);
+	    }
+	  
+	  if ( (rc = write_word(info, wp, data)) != 0 ) 
+	    {
+	      return (rc);
+	    }
+	  wp += 4;
+	}
+      
+      /*
+       * handle word aligned part
+       */
+      while ( cnt >= 4 ) 
+	{
+	  data = 0;
+	  for (i=0; i<4; ++i) 
+	    {
+	      data = (data << 8) | *src++;
+	    }
+	  if ( (rc = write_word(info, wp, data)) != 0 ) 
+	    {
+	      return (rc);
+	    }
+	  wp  += 4;
+	  cnt -= 4;
+	}
+      
+      if ( cnt == 0 ) 
+	{
+	  return (0);
+	}
+      
+      /*
+       * handle unaligned tail bytes
+       */
+      data = 0;
+      for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) 
+	{
+	  data = (data << 8) | *src++;
+	  --cnt;
+	}
+      for (; i<4; ++i, ++cp) 
+	{
+	  data = (data << 8) | (*(uchar *)cp);
+	}
+      
+      return (write_word(info, wp, data));
+    }
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int 
+write_word (flash_info_t  *info, 
+	    ulong          dest, 
+	    ulong          data)
+{
+  vu_long *addr = (vu_long*)(info->start[0]);
+  ulong start;
+  int flag;
+  
+  /* Check if Flash is (sufficiently) erased */
+  if ( (*((vu_long *)dest) & data) != data ) 
+    {
+      return (2);
+    }
+  /* Disable interrupts which might cause a timeout here */
+  flag = disable_interrupts();
+  
+  addr[0x0555] = 0x00AA00AA;
+  addr[0x02AA] = 0x00550055;
+  addr[0x0555] = 0x00A000A0;
+  
+  *((vu_long *)dest) = data;
+  
+  /* re-enable interrupts if necessary */
+  if ( flag )
+    enable_interrupts();
+
+  /* data polling for D7 */
+  start = get_timer (0);
+  while ( (*((vu_long *)dest) & 0x00800080) != (data & 0x00800080) ) 
+    {
+      if ( get_timer(start) > CFG_FLASH_WRITE_TOUT ) 
+	{
+	  return (1);
+	}
+    }
+
+  return (0);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a byte to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int 
+write_byte (flash_info_t  *info, 
+	    ulong          dest, 
+	    uchar          data)
+{
+  volatile unsigned char *addr = (volatile unsigned char *)(info->start[0]);
+  ulong  start;
+  int    flag;
+  
+  /* Check if Flash is (sufficiently) erased */
+  if ( (*((volatile unsigned char *)dest) & data) != data ) 
+    {
+      return (2);
+    }
+  /* Disable interrupts which might cause a timeout here */
+  flag = disable_interrupts();
+  
+  addr[0x0555] = 0xAA;
+  addr[0x02AA] = 0x55;
+  addr[0x0555] = 0xA0;
+  
+  *((volatile unsigned char *)dest) = data;
+  
+  /* re-enable interrupts if necessary */
+  if ( flag )
+    enable_interrupts();
+
+  /* data polling for D7 */
+  start = get_timer (0);
+  while ( (*((volatile unsigned char *)dest) & 0x80) != (data & 0x80) ) 
+    {
+      if ( get_timer(start) > CFG_FLASH_WRITE_TOUT ) 
+	{
+	  return (1);
+	}
+    }
+
+  return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
--- a/board/LEOX/elpt860/u-boot.lds
+++ b/board/LEOX/elpt860/u-boot.lds
@@ -0,0 +1,146 @@
+/*
+**=====================================================================
+**
+** Copyright (C) 2000, 2001, 2002, 2003
+** The LEOX team <team@leox.org>, http://www.leox.org
+**
+** LEOX.org is about the development of free hardware and software resources
+**   for system on chip.
+**
+** Description: U-Boot port on the LEOX's ELPT860 CPU board
+** ~~~~~~~~~~~
+**
+**=====================================================================
+**
+** This program is free software; you can redistribute it and/or
+** modify it under the terms of the GNU General Public License as
+** published by the Free Software Foundation; either version 2 of
+** the License, or (at your option) any later version.
+**
+** This program is distributed in the hope that it will be useful,
+** but WITHOUT ANY WARRANTY; without even the implied warranty of
+** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+** GNU General Public License for more details.
+**
+** You should have received a copy of the GNU General Public License
+** along with this program; if not, write to the Free Software
+** Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+** MA 02111-1307 USA
+**
+**=====================================================================
+*/
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o			(.text)
+    common/dlmalloc.o			(.text)
+    lib_ppc/ppcstring.o			(.text)
+    lib_generic/vsprintf.o		(.text)
+    lib_generic/crc32.o			(.text)
+    lib_generic/zlib.o			(.text)
+    lib_generic/string.o		(.text)
+    lib_ppc/cache.o			(.text)
+    lib_ppc/extable.o			(.text)
+    lib_ppc/time.o			(.text)
+    lib_ppc/ticks.o			(.text)
+
+    . = env_offset;
+    common/environment.o		(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
--- a/board/LEOX/elpt860/u-boot.lds.debug
+++ b/board/LEOX/elpt860/u-boot.lds.debug
@@ -0,0 +1,140 @@
+/*
+**=====================================================================
+**
+** Copyright (C) 2000, 2001, 2002, 2003
+** The LEOX team <team@leox.org>, http://www.leox.org
+**
+** LEOX.org is about the development of free hardware and software resources
+**   for system on chip.
+**
+** Description: U-Boot port on the LEOX's ELPT860 CPU board
+** ~~~~~~~~~~~
+**
+**=====================================================================
+**
+** This program is free software; you can redistribute it and/or
+** modify it under the terms of the GNU General Public License as
+** published by the Free Software Foundation; either version 2 of
+** the License, or (at your option) any later version.
+**
+** This program is distributed in the hope that it will be useful,
+** but WITHOUT ANY WARRANTY; without even the implied warranty of
+** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+** GNU General Public License for more details.
+**
+** You should have received a copy of the GNU General Public License
+** along with this program; if not, write to the Free Software
+** Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+** MA 02111-1307 USA
+**
+**=====================================================================
+*/
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o		(.text)
+    common/dlmalloc.o		(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+
+    . = env_offset;
+    common/environment.o	(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
+
--- a/board/MAI/bios_emulator/scitech/lib/debug/linux/gcc/glibc.so/readme.txt
+++ b/board/MAI/bios_emulator/scitech/lib/debug/linux/gcc/glibc.so/readme.txt
@@ -0,0 +1 @@
+This file is just to ensure that the directory is created.
--- a/board/MAI/bios_emulator/scitech/lib/debug/linux/gcc/libc.so/readme.txt
+++ b/board/MAI/bios_emulator/scitech/lib/debug/linux/gcc/libc.so/readme.txt
@@ -0,0 +1 @@
+This file is just to ensure that the directory is created.
--- a/board/MAI/bios_emulator/scitech/src/pm/os2/dossctl.obj
+++ b/board/MAI/bios_emulator/scitech/src/pm/os2/dossctl.obj
--- a/board/cpc45/Makefile
+++ b/board/cpc45/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2001-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o plx9030.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $^
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
--- a/board/cpc45/config.mk
+++ b/board/cpc45/config.mk
@@ -0,0 +1,36 @@
+#
+# (C) Copyright 2001-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# CPC45 board
+#
+
+
+ifeq ($(CONFIG_BOOT_ROM),y)
+	TEXT_BASE := 0xFFF00000
+	PLATFORM_CPPFLAGS += -DCONFIG_BOOT_ROM
+else
+	TEXT_BASE := 0xFFF00000
+endif
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)
--- a/board/cpc45/cpc45.c
+++ b/board/cpc45/cpc45.c
@@ -0,0 +1,173 @@
+/*
+ * (C) Copyright 2001
+ * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc824x.h>
+#include <asm/processor.h>
+#include <pci.h>
+
+int sysControlDisplay(int digit, uchar ascii_code);			
+extern void Plx9030Init(void);
+
+	/* We have to clear the initial data area here. Couldn't have done it
+	 * earlier because DRAM had not been initialized.
+	 */
+int board_pre_init(void)
+{
+
+	/* enable DUAL UART Mode on CPC45 */
+	*(uchar*)DUART_DCR |= 0x1;	/* set DCM bit */
+
+	return 0;
+}
+
+int checkboard(void)
+{
+/*
+	char  revision = BOARD_REV;
+*/
+	ulong busfreq  = get_bus_freq(0);
+	char  buf[32];
+
+	printf("CPC45 ");
+/*
+	printf("Revision %d ", revision);
+*/
+	printf("Local Bus at %s MHz\n", strmhz(buf, busfreq));
+
+	return 0;
+}
+
+long int initdram(int board_type)
+{
+	int              i, cnt;
+	volatile uchar * base      = CFG_SDRAM_BASE;
+	volatile ulong * addr;
+	ulong            save[32];
+	ulong            val, ret  = 0;
+
+	for (i=0, cnt=(CFG_MAX_RAM_SIZE / sizeof(long)) >> 1; cnt > 0; cnt >>= 1) {
+
+		addr = (volatile ulong *)base + cnt;
+		save[i++] = *addr;
+		*addr = ~cnt;
+	}
+
+	addr = (volatile ulong *)base;
+	save[i] = *addr;
+	*addr = 0;
+
+	if (*addr != 0) {
+		*addr = save[i];
+		goto Done;
+	}
+
+	for (cnt = 1; cnt <= CFG_MAX_RAM_SIZE / sizeof(long); cnt <<= 1) {
+		addr = (volatile ulong *)base + cnt;
+		val = *addr;
+		*addr = save[--i];
+		if (val != ~cnt) {
+			ulong new_bank0_end = cnt * sizeof(long) - 1;
+			ulong mear1  = mpc824x_mpc107_getreg(MEAR1);
+			ulong emear1 = mpc824x_mpc107_getreg(EMEAR1);
+			mear1 =  (mear1  & 0xFFFFFF00) |
+			  ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
+			emear1 = (emear1 & 0xFFFFFF00) |
+			  ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
+			mpc824x_mpc107_setreg(MEAR1,  mear1);
+			mpc824x_mpc107_setreg(EMEAR1, emear1);
+
+			ret = cnt * sizeof(long);
+			goto Done;
+		}
+	}
+
+	ret = CFG_MAX_RAM_SIZE;
+Done:
+	return ret;
+}
+
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+#ifndef CONFIG_PCI_PNP
+
+static struct pci_config_table pci_sandpoint_config_table[] = {
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
+	  pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
+				       PCI_ENET0_MEMADDR,
+				       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
+	{ }
+};
+#endif
+
+
+struct pci_controller hose = {
+#ifndef CONFIG_PCI_PNP
+	config_table: pci_sandpoint_config_table,
+#endif
+};
+
+void pci_init_board(void)
+{
+	pci_mpc824x_init(&hose);
+
+	/* init PCI_to_LOCAL Bus BRIDGE */
+	Plx9030Init();
+
+	sysControlDisplay(0,' ');
+	sysControlDisplay(1,'C');
+	sysControlDisplay(2,'P');
+	sysControlDisplay(3,'C');
+	sysControlDisplay(4,' ');
+	sysControlDisplay(5,'4');
+	sysControlDisplay(6,'5');
+	sysControlDisplay(7,' ');
+
+}
+
+/**************************************************************************
+*
+* sysControlDisplay - controls one of the Alphanum. Display digits.
+*
+* This routine will write an ASCII character to the display digit requested.
+*
+* SEE ALSO:
+*
+* RETURNS: NA
+*/
+
+int sysControlDisplay
+    (
+    int digit, 			/* number of digit 0..7 */
+    uchar ascii_code		/* ASCII code */
+    )
+{
+	if ((digit < 0) || (digit > 7))
+		return (-1);
+
+	*((volatile uchar*)(DISP_CHR_RAM + digit)) = ascii_code;
+
+	return (0);
+}
+
--- a/board/cpc45/flash.c
+++ b/board/cpc45/flash.c
@@ -0,0 +1,493 @@
+/*
+ * (C) Copyright 2001-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc824x.h>
+#include <asm/processor.h>
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+# ifndef  CFG_ENV_ADDR
+#  define CFG_ENV_ADDR	(CFG_FLASH_BASE + CFG_ENV_OFFSET)
+# endif
+# ifndef  CFG_ENV_SIZE
+#  define CFG_ENV_SIZE	CFG_ENV_SECT_SIZE
+# endif
+# ifndef  CFG_ENV_SECT_SIZE
+#  define CFG_ENV_SECT_SIZE  CFG_ENV_SIZE
+# endif
+#endif
+
+#define FLASH_BANK_SIZE 0x800000
+#define MAIN_SECT_SIZE  0x40000
+#define PARAM_SECT_SIZE 0x8000
+
+flash_info_t    flash_info[CFG_MAX_FLASH_BANKS];
+
+static int write_data (flash_info_t *info, ulong dest, ulong *data);
+static void write_via_fpu(vu_long *addr, ulong *data);
+static __inline__ unsigned long get_msr(void);
+static __inline__ void set_msr(unsigned long msr);
+
+/*---------------------------------------------------------------------*/
+#undef	DEBUG_FLASH
+
+/*---------------------------------------------------------------------*/
+#ifdef DEBUG_FLASH
+#define DEBUGF(fmt,args...) printf(fmt ,##args)
+#else
+#define DEBUGF(fmt,args...)
+#endif
+/*---------------------------------------------------------------------*/
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init(void)
+{
+    int i, j;
+    ulong size = 0;
+    uchar tempChar;
+
+   /* Enable flash writes on CPC45 */
+
+    tempChar = BOARD_CTRL;
+
+    tempChar |= (B_CTRL_FWPT_1 | B_CTRL_FWRE_1);
+
+    tempChar &= ~(B_CTRL_FWPT_0 | B_CTRL_FWRE_0);
+
+    BOARD_CTRL = tempChar;
+
+
+    for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+    	vu_long *addr = (vu_long *)(CFG_FLASH_BASE + i * FLASH_BANK_SIZE);
+
+	addr[0] = 0x00900090;
+
+	DEBUGF ("Flash bank # %d:\n"
+		"\tManuf. ID @ 0x%08lX: 0x%08lX\n"
+		"\tDevice ID @ 0x%08lX: 0x%08lX\n",
+		i,
+		(ulong)(&addr[0]), addr[0],
+		(ulong)(&addr[2]), addr[2]);
+
+
+	if ((addr[0] == addr[1]) && (addr[0] == INTEL_MANUFACT) &&
+	    (addr[2] == addr[3]) && (addr[2] == INTEL_ID_28F160F3T))
+	{
+
+	    flash_info[i].flash_id = (FLASH_MAN_INTEL & FLASH_VENDMASK) |
+	    			     (INTEL_ID_28F160F3T & FLASH_TYPEMASK);
+
+	} else {
+	    flash_info[i].flash_id = FLASH_UNKNOWN;
+	    addr[0] = 0xFFFFFFFF;
+	    goto Done;
+	}
+
+	DEBUGF ("flash_id = 0x%08lX\n", flash_info[i].flash_id);
+
+	addr[0] = 0xFFFFFFFF;
+
+	flash_info[i].size = FLASH_BANK_SIZE;
+	flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
+	memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+	for (j = 0; j < flash_info[i].sector_count; j++) {
+		if (j > 30) {
+			flash_info[i].start[j] = CFG_FLASH_BASE +
+			                         i * FLASH_BANK_SIZE +
+			                         (MAIN_SECT_SIZE * 31) + (j - 31) * PARAM_SECT_SIZE;
+		} else {
+			flash_info[i].start[j] = CFG_FLASH_BASE +
+			                         i * FLASH_BANK_SIZE +
+			                         j * MAIN_SECT_SIZE;
+		}
+	}
+	size += flash_info[i].size;
+    }
+
+    /* Protect monitor and environment sectors
+     */
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + FLASH_BANK_SIZE
+    flash_protect(FLAG_PROTECT_SET,
+              CFG_MONITOR_BASE,
+              CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
+              &flash_info[1]);
+#else
+    flash_protect(FLAG_PROTECT_SET,
+              CFG_MONITOR_BASE,
+              CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
+              &flash_info[0]);
+#endif
+#endif
+
+#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR)
+#if CFG_ENV_ADDR >= CFG_FLASH_BASE + FLASH_BANK_SIZE
+    flash_protect(FLAG_PROTECT_SET,
+              CFG_ENV_ADDR,
+              CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+              &flash_info[1]);
+#else
+    flash_protect(FLAG_PROTECT_SET,
+              CFG_ENV_ADDR,
+              CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+              &flash_info[0]);
+#endif
+#endif
+
+Done:
+    return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	switch ((i = info->flash_id & FLASH_VENDMASK)) {
+	case (FLASH_MAN_INTEL & FLASH_VENDMASK):
+		printf ("Intel: ");
+		break;
+	default:
+		printf ("Unknown Vendor 0x%04x ", i);
+		break;
+	}
+
+	switch ((i = info->flash_id & FLASH_TYPEMASK)) {
+	case (INTEL_ID_28F160F3T & FLASH_TYPEMASK):
+		printf ("28F160F3T (16Mbit)\n");
+		break;
+	default:
+		printf ("Unknown Chip Type 0x%04x\n", i);
+		goto Done;
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; i++) {
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+		printf (" %08lX%s", info->start[i],
+				info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+
+Done:
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong start, now, last;
+
+	DEBUGF ("Erase flash bank %d sect %d ... %d\n",
+		info - &flash_info[0], s_first, s_last);
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) !=
+	    (FLASH_MAN_INTEL & FLASH_VENDMASK)) {
+		printf ("Can erase only Intel flash types - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	start = get_timer (0);
+	last  = start;
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			vu_long *addr = (vu_long *)(info->start[sect]);
+
+			DEBUGF ("Erase sect %d @ 0x%08lX\n",
+				sect, (ulong)addr);
+
+			/* Disable interrupts which might cause a timeout
+			 * here.
+			 */
+			flag = disable_interrupts();
+
+			addr[0] = 0x00500050;	/* clear status register */
+			addr[0] = 0x00200020;	/* erase setup */
+			addr[0] = 0x00D000D0;	/* erase confirm */
+
+			addr[1] = 0x00500050;	/* clear status register */
+			addr[1] = 0x00200020;	/* erase setup */
+			addr[1] = 0x00D000D0;	/* erase confirm */
+
+			/* re-enable interrupts if necessary */
+			if (flag)
+				enable_interrupts();
+
+			/* wait at least 80us - let's wait 1 ms */
+			udelay (1000);
+
+			while (((addr[0] & 0x00800080) != 0x00800080) ||
+			       ((addr[1] & 0x00800080) != 0x00800080) ) {
+				if ((now=get_timer(start)) >
+				           CFG_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					addr[0] = 0x00B000B0; /* suspend erase */
+					addr[0] = 0x00FF00FF; /* to read mode  */
+					return 1;
+				}
+
+				/* show that we're waiting */
+				if ((now - last) > 1000) {  /* every second  */
+					putc ('.');
+					last = now;
+				}
+			}
+
+			addr[0] = 0x00FF00FF;
+		}
+	}
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+#define	FLASH_WIDTH	8	/* flash bus width in bytes */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong wp, cp, msr;
+	int l, rc, i;
+	ulong data[2];
+	ulong *datah = &data[0];
+	ulong *datal = &data[1];
+
+	DEBUGF ("Flash write_buff: @ 0x%08lx, src 0x%08lx len %ld\n",
+		addr, (ulong)src, cnt);
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+
+	msr = get_msr();
+	set_msr(msr | MSR_FP);
+
+	wp = (addr & ~(FLASH_WIDTH-1));	/* get lower aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		*datah = *datal = 0;
+
+		for (i = 0, cp = wp; i < l; i++, cp++) {
+			if (i >= 4) {
+				*datah = (*datah << 8) |
+				                ((*datal & 0xFF000000) >> 24);
+			}
+
+			*datal = (*datal << 8) | (*(uchar *)cp);
+		}
+		for (; i < FLASH_WIDTH && cnt > 0; ++i) {
+			char tmp;
+
+			tmp = *src;
+
+			src++;
+
+			if (i >= 4) {
+				*datah = (*datah << 8) |
+			                        ((*datal & 0xFF000000) >> 24);
+			}
+
+			*datal = (*datal << 8) | tmp;
+
+			--cnt; ++cp;
+		}
+
+		for (; cnt == 0 && i < FLASH_WIDTH; ++i, ++cp) {
+			if (i >= 4) {
+				*datah = (*datah << 8) |
+				                ((*datal & 0xFF000000) >> 24);
+			}
+
+			*datal = (*datah << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_data(info, wp, data)) != 0) {
+			set_msr(msr);
+			return (rc);
+		}
+
+		wp += FLASH_WIDTH;
+	}
+
+	/*
+	 * handle FLASH_WIDTH aligned part
+	 */
+	while (cnt >= FLASH_WIDTH) {
+		*datah = *(ulong *)src;
+		*datal = *(ulong *)(src + 4);
+		if ((rc = write_data(info, wp, data)) != 0) {
+			set_msr(msr);
+			return (rc);
+		}
+		wp  += FLASH_WIDTH;
+		cnt -= FLASH_WIDTH;
+		src += FLASH_WIDTH;
+	}
+
+	if (cnt == 0) {
+		set_msr(msr);
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	*datah = *datal = 0;
+	for (i = 0, cp = wp; i < FLASH_WIDTH && cnt > 0; ++i, ++cp) {
+		char tmp;
+
+      		tmp = *src;
+
+		src++;
+
+		if (i >= 4) {
+			*datah = (*datah << 8) | ((*datal & 0xFF000000) >> 24);
+		}
+
+		*datal = (*datal << 8) | tmp;
+
+		--cnt;
+	}
+
+	for (; i < FLASH_WIDTH; ++i, ++cp) {
+		if (i >= 4) {
+			*datah = (*datah << 8) | ((*datal & 0xFF000000) >> 24);
+		}
+
+		*datal = (*datal << 8) | (*(uchar *)cp);
+	}
+
+	rc = write_data(info, wp, data);
+	set_msr(msr);
+
+	return (rc);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t *info, ulong dest, ulong *data)
+{
+	vu_long *addr = (vu_long *)dest;
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if (((addr[0] & data[0]) != data[0]) ||
+	    ((addr[1] & data[1]) != data[1]) ) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0] = 0x00400040;		/* write setup */
+	write_via_fpu(addr, data);
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	start = get_timer (0);
+
+	while (((addr[0] & 0x00800080) != 0x00800080) ||
+	       ((addr[1] & 0x00800080) != 0x00800080) ) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			addr[0] = 0x00FF00FF;	/* restore read mode */
+			return (1);
+		}
+	}
+
+	addr[0] = 0x00FF00FF;	/* restore read mode */
+
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void write_via_fpu(vu_long *addr, ulong *data)
+{
+	__asm__ __volatile__ ("lfd  1, 0(%0)" : : "r" (data));
+	__asm__ __volatile__ ("stfd 1, 0(%0)" : : "r" (addr));
+}
+/*-----------------------------------------------------------------------
+ */
+static __inline__ unsigned long get_msr(void)
+{
+    unsigned long msr;
+
+    __asm__ __volatile__ ("mfmsr %0" : "=r" (msr) :);
+    return msr;
+}
+
+static __inline__ void set_msr(unsigned long msr)
+{
+    __asm__ __volatile__ ("mtmsr %0" : : "r" (msr));
+}
--- a/board/cpc45/plx9030.c
+++ b/board/cpc45/plx9030.c
@@ -0,0 +1,174 @@
+/* Plx9030.c - system configuration module for PLX9030 PCI to Local Bus Bridge */
+/*
+ * (C) Copyright 2002-2003
+ * Josef Wagner, MicroSys GmbH, wagner@microsys.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ *   Date       Modification                                      by
+ * -------      ----------------------------------------------    ---
+ * 30sep02      converted from VxWorks to LINUX                   wa
+*/
+
+
+/*
+DESCRIPTION
+
+This is the configuration module for the PLX9030 PCI to Local Bus Bridge.
+It configures the Chip select lines for SRAM (CS0), ST16C552 (CS1,CS2), Display and local
+registers (CS3) on CPC45.
+*/
+
+/* includes */
+
+#include <common.h>
+#include <malloc.h>
+#include <net.h>
+#include <asm/io.h>
+#include <pci.h>
+
+/* imports */
+
+
+/* defines */
+#define	PLX9030_VENDOR_ID	0x10B5
+#define	PLX9030_DEVICE_ID	0x9030
+
+#undef PLX_DEBUG
+
+/* PLX9030 register offsets  */
+#define	P9030_LAS0RR	0x00
+#define	P9030_LAS1RR 	0x04
+#define	P9030_LAS2RR	0x08
+#define	P9030_LAS3RR	0x0c
+#define	P9030_EROMRR	0x10
+#define	P9030_LAS0BA	0x14
+#define	P9030_LAS1BA	0x18
+#define	P9030_LAS2BA	0x1c
+#define	P9030_LAS3BA	0x20
+#define	P9030_EROMBA	0x24
+#define	P9030_LAS0BRD	0x28
+#define	P9030_LAS1BRD	0x2c
+#define	P9030_LAS2BRD	0x30
+#define	P9030_LAS3BRD	0x34
+#define	P9030_EROMBRD	0x38
+#define	P9030_CS0BASE	0x3C
+#define	P9030_CS1BASE	0x40
+#define	P9030_CS2BASE	0x44
+#define	P9030_CS3BASE	0x48
+#define	P9030_INTCSR 	0x4c
+#define	P9030_CNTRL  	0x50
+#define	P9030_GPIOC	0x54
+
+/* typedefs */
+
+
+/* locals */
+
+static struct pci_device_id supported[] = {
+	{ PLX9030_VENDOR_ID, PLX9030_DEVICE_ID },
+	{ }
+};
+
+/* forward declarations */
+void sysOutLong(ulong address, ulong value);
+
+
+/***************************************************************************
+*
+* Plx9030Init - init CS0..CS3 for CPC45
+*
+*
+* RETURNS: N/A
+*/
+
+void Plx9030Init (void)
+{
+    pci_dev_t   devno;
+    ulong	membaseCsr;	  /* base address of device memory space */
+    int		idx = 0;	  /* general index */
+
+
+    /* find plx9030 device */
+
+    if ((devno = pci_find_devices(supported, idx++)) < 0)
+    {
+	printf("No PLX9030 device found !!\n");
+	return;
+    }
+
+
+#ifdef PLX_DEBUG
+	printf("PLX 9030 device found ! devno = 0x%x\n",devno);
+#endif
+
+	membaseCsr   = PCI_PLX9030_MEMADDR;
+
+	/* set base address */
+	pci_write_config_dword(devno, PCI_BASE_ADDRESS_0, membaseCsr);
+
+	/* enable mapped memory and IO addresses */
+	pci_write_config_dword(devno,
+			       PCI_COMMAND,
+			       PCI_COMMAND_MEMORY |
+			       PCI_COMMAND_MASTER);
+
+
+	/* configure GBIOC */
+	sysOutLong((membaseCsr + P9030_GPIOC),   0x00000FC0);		/* CS2/CS3 enable */
+
+	/* configure CS0 (SRAM) */
+	sysOutLong((membaseCsr + P9030_LAS0BA),  0x00000001);		/* enable space base */
+	sysOutLong((membaseCsr + P9030_LAS0RR),  0x0FE00000);		/* 2 MByte */
+	sysOutLong((membaseCsr + P9030_LAS0BRD), 0x51928900);		/* 4 wait states */
+	sysOutLong((membaseCsr + P9030_CS0BASE), 0x00100001);		/* enable 2 MByte */	
+	/* remap CS0 (SRAM) */
+	pci_write_config_dword(devno, PCI_BASE_ADDRESS_2, SRAM_BASE);
+
+	/* configure CS1 (ST16552 / CHAN A) */
+	sysOutLong((membaseCsr + P9030_LAS1BA),  0x00400001);		/* enable space base */
+	sysOutLong((membaseCsr + P9030_LAS1RR),  0x0FFFFF00);		/* 256 byte */
+	sysOutLong((membaseCsr + P9030_LAS1BRD), 0x55122900);		/* 4 wait states */
+	sysOutLong((membaseCsr + P9030_CS1BASE), 0x00400081);		/* enable 256 Byte */	
+	/* remap CS1 (ST16552 / CHAN A) */
+	/* remap CS1 (ST16552 / CHAN A) */
+	pci_write_config_dword(devno, PCI_BASE_ADDRESS_3, ST16552_A_BASE);
+
+	/* configure CS2 (ST16552 / CHAN B) */
+	sysOutLong((membaseCsr + P9030_LAS2BA),  0x00800001);		/* enable space base */
+	sysOutLong((membaseCsr + P9030_LAS2RR),  0x0FFFFF00);		/* 256 byte */
+	sysOutLong((membaseCsr + P9030_LAS2BRD), 0x55122900);		/* 4 wait states */
+	sysOutLong((membaseCsr + P9030_CS2BASE), 0x00800081);		/* enable 256 Byte */	
+	/* remap CS2 (ST16552 / CHAN B) */
+	pci_write_config_dword(devno, PCI_BASE_ADDRESS_4, ST16552_B_BASE);
+
+	/* configure CS3 (BCSR) */
+	sysOutLong((membaseCsr + P9030_LAS3BA),  0x00C00001);		/* enable space base */
+	sysOutLong((membaseCsr + P9030_LAS3RR),  0x0FFFFF00);		/* 256 byte */
+	sysOutLong((membaseCsr + P9030_LAS3BRD), 0x55357A80);		/* 9 wait states */
+	sysOutLong((membaseCsr + P9030_CS3BASE), 0x00C00081);		/* enable 256 Byte */	
+	/* remap CS3 (DISPLAY and BCSR) */
+	pci_write_config_dword(devno, PCI_BASE_ADDRESS_5, BCSR_BASE);
+}
+
+void sysOutLong(ulong address, ulong value)
+{
+	*(ulong*)address = cpu_to_le32(value);
+}
+
--- a/board/cpc45/u-boot.lds
+++ b/board/cpc45/u-boot.lds
@@ -0,0 +1,128 @@
+/*
+ * (C) Copyright 2001-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc824x/start.o	(.text)
+    lib_ppc/board.o (.text)
+    lib_ppc/ppcstring.o	(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_generic/zlib.o		(.text)
+
+		. = DEFINED(env_offset) ? env_offset : .;
+    common/environment.o (.text)
+
+		*(.text)
+
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+
+  _end = . ;
+  PROVIDE (end = .);
+}
+
--- a/board/cradle/u-boot.lds
+++ b/board/cradle/u-boot.lds
@@ -47,7 +47,9 @@ SECTIONS
 	armboot_end_data = .;

        . = ALIGN(4);
+	bss_start = .;
        .bss : { *(.bss) }
+	bss_end = .;

 	armboot_end = .;
 }
--- a/board/csb226/csb226.c
+++ b/board/csb226/csb226.c
@@ -32,10 +32,30 @@
 # define SHOW_BOOT_PROGRESS(arg)
 #endif

-/*
- * Miscelaneous platform dependent initialisations
+/** 
+ * misc_init_r: - misc initialisation routines
 */

+int misc_init_r(void)
+{
+#if 0	
+	uchar *str;
+	
+	/* determine if the software update key is pressed during startup */
+	/* not ported yet... */
+	if (GPLR0 & 0x00000800) {
+		printf("using bootcmd_normal (sw-update button not pressed)\n");
+		str = getenv("bootcmd_normal");
+	} else {
+		printf("using bootcmd_update (sw-update button pressed)\n");
+		str = getenv("bootcmd_update");
+	}
+
+	setenv("bootcmd",str);
+#endif	
+	return 0;
+}	
+

 /** 
 * board_init: - setup some data structures
--- a/board/csb226/flash.c
+++ b/board/csb226/flash.c
@@ -45,44 +45,44 @@ flash_info_t    flash_info[CFG_MAX_FLASH_BANKS];

 ulong flash_init(void)
 {
-    int i, j;
-    ulong size = 0;
+	int i, j;
+	ulong size = 0;

 	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
-	ulong flashbase = 0;
-	flash_info[i].flash_id =
-	  (INTEL_MANUFACT & FLASH_VENDMASK) |
-	  (INTEL_ID_28F128J3 & FLASH_TYPEMASK);
-	flash_info[i].size = FLASH_BANK_SIZE;
-	flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
-	memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+		ulong flashbase = 0;
+		flash_info[i].flash_id =
+	  		(INTEL_MANUFACT & FLASH_VENDMASK) |
+	  		(INTEL_ID_28F128J3 & FLASH_TYPEMASK);
+		flash_info[i].size = FLASH_BANK_SIZE;
+		flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
+		memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);

 		switch (i) {
-           case 0:
-	        flashbase = PHYS_FLASH_1;
-                break;
-           default:
-	        panic("configured to many flash banks!\n");
-                break;
-        }
+			case 0:
+				flashbase = PHYS_FLASH_1;
+				break;
+			default:
+				panic("configured to many flash banks!\n");
+				break;
+		}
 		for (j = 0; j < flash_info[i].sector_count; j++) {
-	    flash_info[i].start[j] = flashbase + j*MAIN_SECT_SIZE;
+			flash_info[i].start[j] = flashbase + j*MAIN_SECT_SIZE;
+		}
+		size += flash_info[i].size;
 	}
-	size += flash_info[i].size;
-    }

 	/* Protect monitor and environment sectors */
-    flash_protect(FLAG_PROTECT_SET,
-		  CFG_FLASH_BASE,
-		  CFG_FLASH_BASE + _armboot_end_data - _armboot_start,
-		  &flash_info[0]);
+	flash_protect(FLAG_PROTECT_SET,
+			CFG_FLASH_BASE,
+			CFG_FLASH_BASE + _armboot_end_data - _armboot_start,
+			&flash_info[0]);

-    flash_protect(FLAG_PROTECT_SET,
-		  CFG_ENV_ADDR,
-		  CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
-		  &flash_info[0]);
+	flash_protect(FLAG_PROTECT_SET,
+			CFG_ENV_ADDR,
+			CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+			&flash_info[0]);

-    return size;
+	return size;
 }


@@ -94,43 +94,43 @@ ulong flash_init(void)

 void flash_print_info  (flash_info_t *info)
 {
-    int i, j;
+	int i, j;

 	for (j=0; j<CFG_MAX_FLASH_BANKS; j++) {

 		switch (info->flash_id & FLASH_VENDMASK) {

-        case (INTEL_MANUFACT & FLASH_VENDMASK):
-	        printf("Intel: ");
-	        break;
-        default:
-	        printf("Unknown Vendor ");
-	        break;
-        }
+			case (INTEL_MANUFACT & FLASH_VENDMASK):
+				printf("Intel: ");
+				break;
+			default:
+				printf("Unknown Vendor ");
+				break;
+		}

 		switch (info->flash_id & FLASH_TYPEMASK) {

-        case (INTEL_ID_28F128J3 & FLASH_TYPEMASK):
-	        printf("28F128J3 (128Mbit)\n");
-	        break;
-        default:
-	        printf("Unknown Chip Type\n");
+			case (INTEL_ID_28F128J3 & FLASH_TYPEMASK):
+				printf("28F128J3 (128Mbit)\n");
+				break;
+			default:
+				printf("Unknown Chip Type\n");
 				return;
-        }
+		}

-        printf("  Size: %ld MB in %d Sectors\n",
-	        info->size >> 20, info->sector_count);
+		printf("  Size: %ld MB in %d Sectors\n", 
+			info->size >> 20, info->sector_count);

-        printf("  Sector Start Addresses:");
+		printf("  Sector Start Addresses:");
 		for (i = 0; i < info->sector_count; i++) {
 			if ((i % 5) == 0) printf ("\n   ");
 	        
-	        printf (" %08lX%s", info->start[i],
-		        info->protect[i] ? " (RO)" : "     ");
-        }
-        printf ("\n");
-        info++;
-    }
+			printf (" %08lX%s", info->start[i],
+				info->protect[i] ? " (RO)" : "     ");
+		}
+		printf ("\n");
+		info++;
+	}
 }


@@ -139,46 +139,47 @@ void flash_print_info  (flash_info_t *info)
 *
 */

-int	flash_erase (flash_info_t *info, int s_first, int s_last)
+int flash_erase(flash_info_t *info, int s_first, int s_last)
 {
-    int flag, prot, sect;
-    int rc = ERR_OK;
+	int flag, prot, sect;
+	int rc = ERR_OK;

-    if (info->flash_id == FLASH_UNKNOWN)
-	return ERR_UNKNOWN_FLASH_TYPE;
+	if (info->flash_id == FLASH_UNKNOWN)
+		return ERR_UNKNOWN_FLASH_TYPE;

-    if ((s_first < 0) || (s_first > s_last)) {
-	return ERR_INVAL;
-    }
+	if ((s_first < 0) || (s_first > s_last)) {
+		return ERR_INVAL;
+	}

 	if ((info->flash_id & FLASH_VENDMASK) != (INTEL_MANUFACT & FLASH_VENDMASK))
-	return ERR_UNKNOWN_FLASH_VENDOR;
-
-    prot = 0;
-    for (sect=s_first; sect<=s_last; ++sect) {
+		return ERR_UNKNOWN_FLASH_VENDOR;
+	
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
 		if (info->protect[sect]) prot++;
 	}

 	if (prot) return ERR_PROTECTED;

-    /*
-     * Disable interrupts which might cause a timeout
-     * here. Remember that our exception vectors are
-     * at address 0 in the flash, and we don't want a
-     * (ticker) exception to happen while the flash
-     * chip is in programming mode.
-     */
-    flag = disable_interrupts();
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */

-    /* Start erase on unprotected sectors */
-    for (sect = s_first; sect<=s_last && !ctrlc(); sect++) {
+	flag = disable_interrupts();

-	printf("Erasing sector %2d ... ", sect);
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last && !ctrlc(); sect++) {

-	/* arm simple, non interrupt dependent timer */
-	reset_timer_masked();
+		printf("Erasing sector %2d ... ", sect);

-	if (info->protect[sect] == 0) {	/* not protected */
+		/* arm simple, non interrupt dependent timer */
+		reset_timer_masked();
+
+		if (info->protect[sect] == 0) {	/* not protected */
 			u32 * volatile addr = (u32 * volatile)(info->start[sect]);

 			/* erase sector:                                    */
@@ -190,32 +191,32 @@ int	flash_erase (flash_info_t *info, int s_first, int s_last)
 			*addr = 0x00D000D0;	/* erase confirm */

 			while ((*addr & 0x00800080) != 0x00800080) {
-		if (get_timer_masked() > CFG_FLASH_ERASE_TOUT) {
+				if (get_timer_masked() > CFG_FLASH_ERASE_TOUT) {
 					*addr = 0x00B000B0; /* suspend erase*/
 					*addr = 0x00FF00FF; /* read mode    */
-		    rc = ERR_TIMOUT;
-		    goto outahere;
-		}
-	    }
+					rc = ERR_TIMOUT;
+					goto outahere;
+				}
+			}

 			*addr = 0x00500050; /* clear status register cmd.   */
 			*addr = 0x00FF00FF; /* resest to read mode          */

-	}
+		}
 		
-	printf("ok.\n");
-    }
+		printf("ok.\n");
+	}

 	if (ctrlc()) printf("User Interrupt!\n");

-outahere:
+	outahere:

-    /* allow flash to settle - wait 10 ms */
-    udelay_masked(10000);
+	/* allow flash to settle - wait 10 ms */
+	udelay_masked(10000);

 	if (flag) enable_interrupts();

-    return rc;
+	return rc;
 }


@@ -230,71 +231,71 @@ outahere:

 static int write_word (flash_info_t *info, ulong dest, ushort data)
 {
-    ushort *addr = (ushort *)dest, val;
-    int rc = ERR_OK;
-    int flag;
+	u32 * volatile addr = (u32 * volatile)dest, val;
+	int rc = ERR_OK;
+	int flag;

 	/* Check if Flash is (sufficiently) erased */
 	if ((*addr & data) != data) return ERR_NOT_ERASED;

-    /*
-     * Disable interrupts which might cause a timeout
-     * here. Remember that our exception vectors are
-     * at address 0 in the flash, and we don't want a
-     * (ticker) exception to happen while the flash
-     * chip is in programming mode.
-     */
-    flag = disable_interrupts();
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+	flag = disable_interrupts();

-    /* clear status register command */
-    *addr = 0x50;
+	/* clear status register command */
+	*addr = 0x50;

-    /* program set-up command */
-    *addr = 0x40;
+	/* program set-up command */
+	*addr = 0x40;

-    /* latch address/data */
-    *addr = data;
+	/* latch address/data */
+	*addr = data;

-    /* arm simple, non interrupt dependent timer */
-    reset_timer_masked();
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked();

-    /* wait while polling the status register */
+	/* wait while polling the status register */
 	while(((val = *addr) & 0x80) != 0x80) {
-	if (get_timer_masked() > CFG_FLASH_WRITE_TOUT) {
-	    rc = ERR_TIMOUT;
+		if (get_timer_masked() > CFG_FLASH_WRITE_TOUT) {
+			rc = ERR_TIMOUT;
 			*addr = 0xB0; /* suspend program command */
-	    goto outahere;
+			goto outahere;
+		}
 	}
-    }

-    if(val & 0x1A) {	/* check for error */
-        printf("\nFlash write error %02x at address %08lx\n",
-    	   (int)val, (unsigned long)dest);
-        if(val & (1<<3)) {
-	    printf("Voltage range error.\n");
-	    rc = ERR_PROG_ERROR;
-	    goto outahere;
-        }
-        if(val & (1<<1)) {
-	    printf("Device protect error.\n");
-	    rc = ERR_PROTECTED;
-	    goto outahere;
-        }
-        if(val & (1<<4)) {
-	    printf("Programming error.\n");
-	    rc = ERR_PROG_ERROR;
-	    goto outahere;
-        }
-        rc = ERR_PROG_ERROR;
-        goto outahere;
-    }
+	if(val & 0x1A) {	/* check for error */
+		printf("\nFlash write error %02x at address %08lx\n",
+			(int)val, (unsigned long)dest);
+		if(val & (1<<3)) {
+			printf("Voltage range error.\n");
+			rc = ERR_PROG_ERROR;
+			goto outahere;
+		}
+		if(val & (1<<1)) {
+			printf("Device protect error.\n");
+			rc = ERR_PROTECTED;
+			goto outahere;
+		}
+		if(val & (1<<4)) {
+			printf("Programming error.\n");
+			rc = ERR_PROG_ERROR;
+			goto outahere;
+		}
+		rc = ERR_PROG_ERROR;
+		goto outahere;
+	}

-outahere:
+	outahere:

 	*addr = 0xFF; /* read array command */
 	if (flag) enable_interrupts();

-    return rc;
+	return rc;
 }


@@ -311,63 +312,64 @@ outahere:

 int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
 {
-    ulong cp, wp;
-    ushort data;
-    int l;
-    int i, rc;
+	ulong cp, wp;
+	ushort data;
+	int l;
+	int i, rc;

-    wp = (addr & ~1);	/* get lower word aligned address */
+	wp = (addr & ~1);	/* get lower word aligned address */

-    /*
-     * handle unaligned start bytes
-     */
-    if ((l = addr - wp) != 0) {
-	data = 0;
-	for (i=0, cp=wp; i<l; ++i, ++cp) {
-	    data = (data >> 8) | (*(uchar *)cp << 8);
-	}
-	for (; i<2 && cnt>0; ++i) {
-	    data = (data >> 8) | (*src++ << 8);
-	    --cnt;
-	    ++cp;
-	}
-	for (; cnt==0 && i<2; ++i, ++cp) {
-	    data = (data >> 8) | (*(uchar *)cp << 8);
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *)cp << 8);
+		}
+		for (; i<2 && cnt>0; ++i) {
+			data = (data >> 8) | (*src++ << 8);
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<2; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *)cp << 8);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 2;
 	}

-	if ((rc = write_word(info, wp, data)) != 0) {
-	    return (rc);
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 2) {
+		/* data = *((vushort*)src); */
+		data = *((ushort*)src);
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		src += 2;
+		wp  += 2;
+		cnt -= 2;
 	}
-	wp += 2;
-    }
-
-    /*
-     * handle word aligned part
-     */
-    while (cnt >= 2) {
-	/* data = *((vushort*)src); */
-	data = *((ushort*)src);
-	if ((rc = write_word(info, wp, data)) != 0) {
-	    return (rc);
-	}
-	src += 2;
-	wp  += 2;
-	cnt -= 2;
-    }

 	if (cnt == 0) return ERR_OK;

-    /*
-     * handle unaligned tail bytes
-     */
-    data = 0;
-    for (i=0, cp=wp; i<2 && cnt>0; ++i, ++cp) {
-	data = (data >> 8) | (*src++ << 8);
-	--cnt;
-    }
-    for (; i<2; ++i, ++cp) {
-	data = (data >> 8) | (*(uchar *)cp << 8);
-    }
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<2 && cnt>0; ++i, ++cp) {
+		data = (data >> 8) | (*src++ << 8);
+		--cnt;
+	}
+	for (; i<2; ++i, ++cp) {
+		data = (data >> 8) | (*(uchar *)cp << 8);
+	}

-    return write_word(info, wp, data);
+	return write_word(info, wp, data);
 }
+
--- a/board/csb226/memsetup.S
+++ b/board/csb226/memsetup.S
@@ -313,17 +313,23 @@ mem_init:
 	/*          documented in SDRAM data sheets. The address(es) used   */
 	/*          for this purpose must not be cacheable.                 */

-	ldr	r3,	=CFG_DRAM_BASE
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
+	/*          There should 9 writes, since the first write doesn't    */
+	/*          trigger a refresh cycle on PXA250. See Intel PXA250 and */
+	/*          PXA210 Processors Specification Update,                 */
+	/*          Jan 2003, Errata #116, page 30.                         */


+	ldr	r3,	=CFG_DRAM_BASE
+	str	r2, [r3]
+	str	r2, [r3]
+	str	r2, [r3]
+	str	r2, [r3]
+	str	r2, [r3]
+	str	r2, [r3]
+	str	r2, [r3]
+	str	r2, [r3]
+	str	r2, [r3]
+
 	/* Step 4g: Write MDCNFG with enable bits asserted                  */
 	/*          (MDCNFG:DEx set to 1).                                  */

@@ -339,7 +345,6 @@ mem_init:

 	/* We are finished with Intel's memory controller initialisation    */

-
 	/* ---------------------------------------------------------------- */
 	/* Disable (mask) all interrupts at interrupt controller            */
 	/* ---------------------------------------------------------------- */
@@ -378,10 +383,11 @@ initclks:
        str     r2,  [r1]

 	/* enable the 32Khz oscillator for RTC and PowerManager             */
+/*
        ldr     r1,  =OSCC
        mov     r2,  #OSCC_OON
        str     r2,  [r1]
-
+*/
 	/* NOTE:  spin here until OSCC.OOK get set, meaning the PLL         */
 	/* has settled.                                                     */
 60:
@@ -404,8 +410,7 @@ initclks:

 	/* FIXME */

-#define NODEBUG
-#ifdef NODEBUG
+#ifndef DEBUG
 	/*Disable software and data breakpoints */
 	mov	r0,#0
 	mcr	p15,0,r0,c14,c8,0  /* ibcr0 */
@@ -415,7 +420,6 @@ initclks:
 	/*Enable all debug functionality */
 	mov	r0,#0x80000000
 	mcr	p14,0,r0,c10,c0,0  /* dcsr */
-
 #endif

        /* ---------------------------------------------------------------- */
--- a/board/csb226/u-boot.lds
+++ b/board/csb226/u-boot.lds
@@ -47,7 +47,9 @@ SECTIONS
 	armboot_end_data = .;

        . = ALIGN(4);
+	bss_start = .;
        .bss : { *(.bss) }
+	bss_end = .;

 	armboot_end = .;
 }
--- a/board/cu824/cu824.c
+++ b/board/cu824/cu824.c
@@ -98,11 +98,11 @@ Done:
 */
 #ifndef CONFIG_PCI_PNP
 static struct pci_config_table pci_sandpoint_config_table[] = {
-	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
-	  PCI_BUS(CFG_ETH_DEV_FN), PCI_DEV(CFG_ETH_DEV_FN), PCI_FUNC(CFG_ETH_DEV_FN),
-	  pci_cfgfunc_config_device, { CFG_ETH_IOBASE,
-				       0,
-				       PCI_COMMAND_IO | PCI_COMMAND_MASTER }},
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
+	  pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
+				       PCI_ENET0_MEMADDR,
+				       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
+
 	{ }
 };
 #endif
--- a/board/emk/top860/config.mk
+++ b/board/emk/top860/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# TOP860 board
+#
+
+TEXT_BASE = 0x80000000
--- a/board/innokom/flash.c
+++ b/board/innokom/flash.c
@@ -31,12 +31,223 @@
 #include <common.h>
 #include <asm/arch/pxa-regs.h>

-#define FLASH_BANK_SIZE 0x02000000
-#define MAIN_SECT_SIZE  0x40000         /* 2x16 = 256k per sector */
+#if defined CFG_JFFS_CUSTOM_PART
+#include <jffs2/jffs2.h>
+#endif
+
+/* Debugging macros ------------------------------------------------------  */
+
+#undef FLASH_DEBUG
+//#define FLASH_DEBUG 1
+
+/* Some debug macros */
+#if (FLASH_DEBUG > 2 )
+#define PRINTK3(args...) printf(args)
+#else
+#define PRINTK3(args...)
+#endif
+
+#if FLASH_DEBUG > 1
+#define PRINTK2(args...) printf(args)
+#else
+#define PRINTK2(args...)
+#endif
+
+#ifdef FLASH_DEBUG
+#define PRINTK(args...) printf(args)
+#else
+#define PRINTK(args...)
+#endif
+
+/* ------------------------------------------------------------------------ */
+
+/* Development system: we have only 16 MB Flash                             */
+#ifdef CONFIG_MTD_INNOKOM_16MB
+#define FLASH_BANK_SIZE 0x01000000	/* 16 MB (during development)       */
+#define MAIN_SECT_SIZE  0x00020000	/* 128k per sector                  */
+#endif
+
+/* Production system: we have 64 MB Flash                                   */
+#ifdef CONFIG_MTD_INNOKOM_64MB
+#define FLASH_BANK_SIZE 0x04000000	/* 64 MB                            */
+#define MAIN_SECT_SIZE  0x00020000	/* 128k per sector                  */
+#endif

 flash_info_t    flash_info[CFG_MAX_FLASH_BANKS];


+#if defined CFG_JFFS_CUSTOM_PART
+
+/**
+ * jffs2_part_info - get information about a JFFS2 partition
+ *
+ * @part_num: number of the partition you want to get info about
+ * @return:   struct part_info* in case of success, 0 if failure
+ */
+
+static struct part_info part;
+static int current_part = -1;
+
+#ifdef CONFIG_MTD_INNOKOM_16MB
+#ifdef CONFIG_MTD_INNOKOM_64MB
+#error Please define only one CONFIG_MTD_INNOKOM_XXMB option.
+#endif
+struct part_info* jffs2_part_info(int part_num) {
+	void *jffs2_priv_saved = part.jffs2_priv;
+
+	PRINTK2("jffs2_part_info: part_num=%i\n",part_num);
+
+	if (current_part == part_num)
+		return &part;
+
+	/* u-boot partition                                                 */
+	if(part_num==0){
+		memset(&part, 0, sizeof(part));
+		
+		part.offset=(char*)0x00000000;
+		part.size=256*1024;
+		
+		/* Mark the struct as ready */
+		current_part = part_num;
+
+		PRINTK("part.offset = 0x%08x\n",(unsigned int)part.offset);
+		PRINTK("part.size   = 0x%08x\n",(unsigned int)part.size);
+	}
+
+	/* primary OS+firmware partition                                    */
+	if(part_num==1){
+		memset(&part, 0, sizeof(part));
+		
+		part.offset=(char*)0x00040000;
+		part.size=768*1024;
+		
+		/* Mark the struct as ready */
+		current_part = part_num;
+
+		PRINTK("part.offset = 0x%08x\n",(unsigned int)part.offset);
+		PRINTK("part.size   = 0x%08x\n",(unsigned int)part.size);
+	}
+	
+	/* secondary OS+firmware partition                                  */
+	if(part_num==2){
+		memset(&part, 0, sizeof(part));
+		
+		part.offset=(char*)0x00100000;
+		part.size=8*1024*1024;
+		
+		/* Mark the struct as ready */
+		current_part = part_num;
+
+		PRINTK("part.offset = 0x%08x\n",(unsigned int)part.offset);
+		PRINTK("part.size   = 0x%08x\n",(unsigned int)part.size);
+	}
+
+	/* data partition */
+	if(part_num==3){
+		memset(&part, 0, sizeof(part));
+		
+		part.offset=(char*)0x00900000;
+		part.size=7*1024*1024;
+		
+		/* Mark the struct as ready */
+		current_part = part_num;
+
+		PRINTK("part.offset = 0x%08x\n",(unsigned int)part.offset);
+		PRINTK("part.size   = 0x%08x\n",(unsigned int)part.size);
+	}
+	
+	if (current_part == part_num) {
+		part.usr_priv = &current_part;
+		part.jffs2_priv = jffs2_priv_saved;
+		return &part;
+	}
+
+	PRINTK("jffs2_part_info: end of partition table\n");
+	return 0;
+}
+#endif /* CONFIG_MTD_INNOKOM_16MB */
+
+#ifdef CONFIG_MTD_INNOKOM_64MB
+#ifdef CONFIG_MTD_INNOKOM_16MB
+#error Please define only one CONFIG_MTD_INNOKOM_XXMB option.
+#endif
+struct part_info* jffs2_part_info(int part_num) {
+	void *jffs2_priv_saved = part.jffs2_priv;
+
+	PRINTK2("jffs2_part_info: part_num=%i\n",part_num);
+
+	if (current_part == part_num)
+		return &part;
+
+	/* u-boot partition                                                 */
+	if(part_num==0){
+		memset(&part, 0, sizeof(part));
+		
+		part.offset=(char*)0x00000000;
+		part.size=256*1024;
+		
+		/* Mark the struct as ready */
+		current_part = part_num;
+
+		PRINTK("part.offset = 0x%08x\n",(unsigned int)part.offset);
+		PRINTK("part.size   = 0x%08x\n",(unsigned int)part.size);
+	}
+
+	/* primary OS+firmware partition                                    */
+	if(part_num==1){
+		memset(&part, 0, sizeof(part));
+		
+		part.offset=(char*)0x00040000;
+		part.size=16*1024*1024-128*1024;
+		
+		/* Mark the struct as ready */
+		current_part = part_num;
+
+		PRINTK("part.offset = 0x%08x\n",(unsigned int)part.offset);
+		PRINTK("part.size   = 0x%08x\n",(unsigned int)part.size);
+	}
+	
+	/* secondary OS+firmware partition                                  */
+	if(part_num==2){
+		memset(&part, 0, sizeof(part));
+		
+		part.offset=(char*)0x01020000;
+		part.size=16*1024*1024-128*1024;
+		
+		/* Mark the struct as ready */
+		current_part = part_num;
+
+		PRINTK("part.offset = 0x%08x\n",(unsigned int)part.offset);
+		PRINTK("part.size   = 0x%08x\n",(unsigned int)part.size);
+	}
+
+	/* data partition */
+	if(part_num==3){
+		memset(&part, 0, sizeof(part));
+		
+		part.offset=(char*)0x02000000;
+		part.size=32*1024*1024;
+		
+		/* Mark the struct as ready */
+		current_part = part_num;
+
+		PRINTK("part.offset = 0x%08x\n",(unsigned int)part.offset);
+		PRINTK("part.size   = 0x%08x\n",(unsigned int)part.size);
+	}
+	
+	if (current_part == part_num) {
+		part.usr_priv = &current_part;
+		part.jffs2_priv = jffs2_priv_saved;
+		return &part;
+	}
+
+	PRINTK("jffs2_part_info: end of partition table\n");
+	return 0;
+}
+#endif /* CONFIG_MTD_INNOKOM_64MB */
+#endif /* defined CFG_JFFS_CUSTOM_PART */
+
+
 /**
 * flash_init: - initialize data structures for flash chips
 *
@@ -71,10 +282,10 @@ ulong flash_init(void)
 		size += flash_info[i].size;
 	}

-	/* Protect monitor and environment sectors */
+	/* Protect u-boot sectors */
 	flash_protect(FLAG_PROTECT_SET,
 			CFG_FLASH_BASE,
-			CFG_FLASH_BASE + _armboot_end_data - _armboot_start,
+			CFG_FLASH_BASE + (256*1024) - 1,
 			&flash_info[0]);

 #ifdef CFG_ENV_IS_IN_FLASH
@@ -120,13 +331,13 @@ void flash_print_info  (flash_info_t *info)
 				return;
 		}

-		printf("  Size: %ld MB in %d Sectors\n",
+		printf("  Size: %ld MB in %d Sectors\n", 
 			info->size >> 20, info->sector_count);

 		printf("  Sector Start Addresses:");
 		for (i = 0; i < info->sector_count; i++) {
 			if ((i % 5) == 0) printf ("\n   ");
-
+	        
 			printf (" %08lX%s", info->start[i],
 				info->protect[i] ? " (RO)" : "     ");
 		}
@@ -155,7 +366,7 @@ int flash_erase(flash_info_t *info, int s_first, int s_last)

 	if ((info->flash_id & FLASH_VENDMASK) != (INTEL_MANUFACT & FLASH_VENDMASK))
 		return ERR_UNKNOWN_FLASH_VENDOR;
-
+	
 	prot = 0;
 	for (sect=s_first; sect<=s_last; ++sect) {
 		if (info->protect[sect]) prot++;
@@ -178,34 +389,40 @@ int flash_erase(flash_info_t *info, int s_first, int s_last)

 		printf("Erasing sector %2d ... ", sect);

+		PRINTK("\n");
+
 		/* arm simple, non interrupt dependent timer */
 		reset_timer_masked();

 		if (info->protect[sect] == 0) {	/* not protected */
-			u32 * volatile addr = (u32 * volatile)(info->start[sect]);
+			u16 * volatile addr = (u16 * volatile)(info->start[sect]);

-			/* erase sector:                                    */
-			/* The strata flashs are aligned side by side on    */
-			/* the data bus, so we have to write the commands   */
-			/* to both chips here:                              */
+			PRINTK("unlocking sector\n");
+			*addr = 0x0060;
+			*addr = 0x00d0;
+			*addr = 0x00ff;

-			*addr = 0x00200020;	/* erase setup */
-			*addr = 0x00D000D0;	/* erase confirm */
+			PRINTK("erasing sector\n");
+			*addr = 0x0020;
+			PRINTK("confirming erase\n");
+			*addr = 0x00D0;

-			while ((*addr & 0x00800080) != 0x00800080) {
+			while ((*addr & 0x0080) != 0x0080) {
+				PRINTK(".");
 				if (get_timer_masked() > CFG_FLASH_ERASE_TOUT) {
-					*addr = 0x00B000B0; /* suspend erase*/
-					*addr = 0x00FF00FF; /* read mode    */
+					*addr = 0x00B0; /* suspend erase*/
+					*addr = 0x00FF; /* read mode    */
 					rc = ERR_TIMOUT;
 					goto outahere;
 				}
 			}
-
-			*addr = 0x00500050; /* clear status register cmd.   */
-			*addr = 0x00FF00FF; /* resest to read mode          */
-
+			
+			PRINTK("clearing status register\n");
+			*addr = 0x0050; 
+			PRINTK("resetting to read mode");
+			*addr = 0x00FF; 
 		}
-
+		
 		printf("ok.\n");
 	}

@@ -233,7 +450,7 @@ int flash_erase(flash_info_t *info, int s_first, int s_last)

 static int write_word (flash_info_t *info, ulong dest, ushort data)
 {
-	ushort *addr = (ushort *)dest, val;
+	volatile u16 *addr = (u16 *)dest, val;
 	int rc = ERR_OK;
 	int flag;

--- a/board/innokom/innokom.c
+++ b/board/innokom/innokom.c
@@ -25,6 +25,7 @@

 #include <common.h>
 #include <asm/arch/pxa-regs.h>
+#include <asm/mach-types.h>

 #ifdef CONFIG_SHOW_BOOT_PROGRESS
 # define SHOW_BOOT_PROGRESS(arg)        show_boot_progress(arg)
@@ -32,9 +33,50 @@
 # define SHOW_BOOT_PROGRESS(arg)
 #endif

-/*
- * Miscelaneous platform dependent initialisations
+/**
+ * i2c_init_board - reset i2c bus. When the board is powercycled during a
+ * bus transfer it might hang; for details see doc/I2C_Edge_Conditions.
+ * The Innokom board has GPIO70 connected to SCLK which can be toggled
+ * until all chips think that their current cycles are finished.
 */
+void i2c_init_board(void)
+{
+	int i;
+
+	/* set gpio pin to output */
+        GPDR(70) |= GPIO_bit(70);
+	for (i = 0; i < 11; i++) {
+		GPCR(70) = GPIO_bit(70);
+		udelay(10);
+		GPSR(70)  = GPIO_bit(70);
+		udelay(10);
+	}
+        /* set gpio pin to input */
+        GPDR(70) &= ~GPIO_bit(70);
+}
+
+
+/**
+ * misc_init_r: - misc initialisation routines
+ */
+
+int misc_init_r(void)
+{
+	uchar *str;
+
+	/* determine if the software update key is pressed during startup   */
+	if (GPLR0 & 0x00000800) {
+		printf("using bootcmd_normal (sw-update button not pressed)\n");
+		str = getenv("bootcmd_normal");
+	} else {
+		printf("using bootcmd_update (sw-update button pressed)\n");
+		str = getenv("bootcmd_update");
+	}
+
+	setenv("bootcmd",str);
+
+	return 0;
+}


 /**
@@ -51,7 +93,7 @@ int board_init (void)
 	/* so we do _nothing_ here */

 	/* arch number of Innokom board */
-	gd->bd->bi_arch_number = 258;
+	gd->bd->bi_arch_number = MACH_TYPE_INNOKOM;

 	/* adress of boot parameters */
 	gd->bd->bi_boot_params = 0xa0000100;
--- a/board/innokom/memsetup.S
+++ b/board/innokom/memsetup.S
@@ -38,6 +38,9 @@ DRAM_SIZE:  .long   CFG_DRAM_SIZE
   sub  pc,pc,#4
   .endm

+_TEXT_BASE:
+	.word	TEXT_BASE
+

 /*
 * 	Memory setup
@@ -222,6 +225,12 @@ mem_init:
        /* Step 2c: Write FLYCNFG  FIXME: what's that???                    */
        /* ---------------------------------------------------------------- */

+        /* test if we run from flash or RAM - RAM/BDI: don't setup RAM      */
+	adr	r3, mem_init		/* r0 <- current position of code   */
+	ldr	r2, =mem_init
+	cmp	r3, r2			/* skip init if in place            */
+	beq	initirqs
+

 	/* ---------------------------------------------------------------- */
        /* Step 2d: Initialize Timing for Sync Memory (SDCLK0)              */
@@ -313,17 +322,23 @@ mem_init:
 	/*          documented in SDRAM data sheets. The address(es) used   */
 	/*          for this purpose must not be cacheable.                 */

-	ldr	r3,	=CFG_DRAM_BASE
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
+	/*          There should 9 writes, since the first write doesn't    */
+	/*          trigger a refresh cycle on PXA250. See Intel PXA250 and */
+	/*          PXA210 Processors Specification Update,                 */
+	/*          Jan 2003, Errata #116, page 30.                         */


+	ldr	r3,	=CFG_DRAM_BASE
+	str	r2, [r3]
+	str	r2, [r3]
+	str	r2, [r3]
+	str	r2, [r3]
+	str	r2, [r3]
+	str	r2, [r3]
+	str	r2, [r3]
+	str	r2, [r3]
+	str	r2, [r3]
+
 	/* Step 4g: Write MDCNFG with enable bits asserted                  */
 	/*          (MDCNFG:DEx set to 1).                                  */

@@ -339,7 +354,6 @@ mem_init:

 	/* We are finished with Intel's memory controller initialisation    */

-
 	/* ---------------------------------------------------------------- */
 	/* Disable (mask) all interrupts at interrupt controller            */
 	/* ---------------------------------------------------------------- */
@@ -405,8 +419,7 @@ initclks:

 	/* FIXME */

-#define NODEBUG
-#ifdef NODEBUG
+#ifndef DEBUG
 	/*Disable software and data breakpoints */
 	mov	r0,#0
 	mcr	p15,0,r0,c14,c8,0  /* ibcr0 */
@@ -416,7 +429,6 @@ initclks:
 	/*Enable all debug functionality */
 	mov	r0,#0x80000000
 	mcr	p14,0,r0,c10,c0,0  /* dcsr */
-
 #endif

        /* ---------------------------------------------------------------- */
--- a/board/innokom/u-boot.lds
+++ b/board/innokom/u-boot.lds
@@ -47,7 +47,9 @@ SECTIONS
 	armboot_end_data = .;

        . = ALIGN(4);
+	bss_start = .;
        .bss : { *(.bss) }
+	bss_end = .;

 	armboot_end = .;
 }
--- a/board/ip860/ip860.c
+++ b/board/ip860/ip860.c
@@ -28,7 +28,8 @@
 /* ------------------------------------------------------------------------- */

 static long int dram_size (long int, long int *, long int);
-
+unsigned long ip860_get_dram_size(void);
+unsigned long ip860_get_clk_freq (void);
 /* ------------------------------------------------------------------------- */

 #define	_NOT_USED_	0xFFFFFFFF
@@ -82,8 +83,22 @@ const uint sdram_table[] = {
 	_NOT_USED_, _NOT_USED_, _NOT_USED_,
 };

-/* ------------------------------------------------------------------------- */

+/* ------------------------------------------------------------------------- */
+int board_pre_init(void)
+{
+    volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+    volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+/* init BCSR chipselect line for ip860_get_clk_freq() and ip860_get_dram_size() */
+    memctl->memc_or4 = CFG_OR4;
+    memctl->memc_br4 = CFG_BR4;
+
+    return 0;
+}
+
+
+/* ------------------------------------------------------------------------- */

 /*
 * Check Board Identity:
@@ -127,6 +142,7 @@ long int initdram (int board_type)
 	volatile immap_t *immap = (immap_t *) CFG_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	long int size;
+	ulong refresh_val;

 	upmconfig (UPMA, (uint *) sdram_table,
 			   sizeof (sdram_table) / sizeof (uint));
@@ -134,7 +150,17 @@ long int initdram (int board_type)
 	/*
 	 * Preliminary prescaler for refresh
 	 */
-	memctl->memc_mptpr = 0x0400;
+	if (ip860_get_clk_freq() == 50000000)
+	{
+		memctl->memc_mptpr = 0x0400;
+		refresh_val = 0xC3000000;
+	}
+	else
+	{
+		memctl->memc_mptpr = 0x0200;
+		refresh_val = 0x9C000000;
+	}
+

 	memctl->memc_mar = 0x00000088;

@@ -151,18 +177,22 @@ long int initdram (int board_type)

 	/* perform SDRAM initializsation sequence */

-	memctl->memc_mamr = 0xC3804114;
-	memctl->memc_mcr = 0x80004105;	/* run precharge pattern from loc 5 */
-	udelay (1);
-	memctl->memc_mamr = 0xC3804118;
-	memctl->memc_mcr = 0x80004130;	/* run refresh pattern 8 times */
+	memctl->memc_mamr = 0x00804114 | refresh_val;
+	memctl->memc_mcr  = 0x80004105;	/* run precharge pattern from loc 5 */
+	udelay(1);
+	memctl->memc_mamr = 0x00804118 | refresh_val;
+	memctl->memc_mcr  = 0x80004130;	/* run refresh pattern 8 times */
+

 	udelay (1000);

 	/*
 	 * Check SDRAM Memory Size
 	 */
-	size = dram_size (CFG_MAMR, (ulong *) SDRAM_BASE, SDRAM_MAX_SIZE);
+	if (ip860_get_dram_size() == 16)
+		size = dram_size (refresh_val | 0x00804114, (ulong *)SDRAM_BASE, SDRAM_MAX_SIZE);
+	else
+		size = dram_size (refresh_val | 0x00906114, (ulong *)SDRAM_BASE, SDRAM_MAX_SIZE);

 	udelay (1000);

@@ -291,3 +321,68 @@ void reset_phy (void)
 }

 /* ------------------------------------------------------------------------- */
+
+unsigned long ip860_get_clk_freq(void)
+{
+	volatile ip860_bcsr_t	*bcsr   = (ip860_bcsr_t *)BCSR_BASE;
+	ulong temp;
+	uchar sysclk;
+
+	if ((bcsr->bd_status & 0x80) == 0x80)	/* bd_rev valid ? */
+		sysclk = (bcsr->bd_rev & 0x18) >> 3;
+	else
+		sysclk = 0x00;
+
+	switch (sysclk)
+	{
+		case 0x00:
+			temp = 50000000;
+			break;
+
+		case 0x01:
+			temp = 80000000;
+			break;
+
+		default:
+			temp = 50000000;
+			break;
+	}
+
+	return (temp);
+
+}
+
+
+/* ------------------------------------------------------------------------- */
+
+unsigned long ip860_get_dram_size(void)
+{
+	volatile ip860_bcsr_t	*bcsr   = (ip860_bcsr_t *)BCSR_BASE;
+	ulong temp;
+	uchar dram_size;
+
+	if ((bcsr->bd_status & 0x80) == 0x80)	/* bd_rev valid ? */
+		dram_size = (bcsr->bd_rev & 0xE0) >> 5;
+	else
+		dram_size = 0x00;	/* default is 16 MB */
+
+	switch (dram_size)
+	{
+		case 0x00:
+			temp = 16;
+			break;
+
+		case 0x01:
+			temp = 32;
+			break;
+
+		default:
+			temp = 16;
+			break;
+	}
+
+	return (temp);
+
+}
+
+/* ------------------------------------------------------------------------- */
--- a/board/lubbock/flash.c
+++ b/board/lubbock/flash.c
@@ -28,7 +28,7 @@
 #include <linux/byteorder/swab.h>


-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */

 /* Board support for 1 or 2 flash devices */
 #define FLASH_PORT_WIDTH32
@@ -53,50 +53,47 @@ flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 * Functions
 */
 static ulong flash_get_size (FPW *addr, flash_info_t *info);
-static int   write_data (flash_info_t *info, ulong dest, FPW data);
-static void  flash_get_offsets (ulong base, flash_info_t *info);
-void inline  spin_wheel(void);
+static int write_data (flash_info_t *info, ulong dest, FPW data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+void inline spin_wheel (void);

 /*-----------------------------------------------------------------------
 */

 unsigned long flash_init (void)
 {
-   int i;
-    ulong size = 0;
+	int i;
+	ulong size = 0;

-    for (i = 0; i < CFG_MAX_FLASH_BANKS; i++)
-    {
-        switch (i)
-        {
-           case 0:
-            flash_get_size((FPW *)PHYS_FLASH_1, &flash_info[i]);
-	         flash_get_offsets(PHYS_FLASH_1, &flash_info[i]);
-                break;
-           case 1:
-            flash_get_size((FPW *)PHYS_FLASH_2, &flash_info[i]);
-	         flash_get_offsets(PHYS_FLASH_2, &flash_info[i]);
-                break;
-           default:
-	        panic("configured to many flash banks!\n");
-                break;
-        }
-	size += flash_info[i].size;
-    }
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		switch (i) {
+		case 0:
+			flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
+			flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
+			break;
+		case 1:
+			flash_get_size ((FPW *) PHYS_FLASH_2, &flash_info[i]);
+			flash_get_offsets (PHYS_FLASH_2, &flash_info[i]);
+			break;
+		default:
+			panic ("configured to many flash banks!\n");
+			break;
+		}
+		size += flash_info[i].size;
+	}

-    /* Protect monitor and environment sectors
-     */
-    flash_protect(FLAG_PROTECT_SET,
-		  CFG_FLASH_BASE,
-		  CFG_FLASH_BASE + _armboot_end_data - _armboot_start,
-		  &flash_info[0]);
+	/* Protect monitor and environment sectors
+	 */
+	flash_protect ( FLAG_PROTECT_SET,
+			CFG_FLASH_BASE,
+			CFG_FLASH_BASE + _armboot_end_data - _armboot_start,
+			&flash_info[0] );

-    flash_protect(FLAG_PROTECT_SET,
-		  CFG_ENV_ADDR,
-		  CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
-		  &flash_info[0]);
+	flash_protect ( FLAG_PROTECT_SET,
+			CFG_ENV_ADDR,
+			CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0] );

-    return size;
+	return size;
 }

 /*-----------------------------------------------------------------------
@@ -119,39 +116,45 @@ static void flash_get_offsets (ulong base, flash_info_t *info)

 /*-----------------------------------------------------------------------
 */
-void flash_print_info  (flash_info_t *info)
+void flash_print_info (flash_info_t *info)
 {
 	int i;

 	if (info->flash_id == FLASH_UNKNOWN) {
 		printf ("missing or unknown FLASH type\n");
 		return;
-        }
+	}

 	switch (info->flash_id & FLASH_VENDMASK) {
-		case FLASH_MAN_INTEL:	printf ("INTEL ");		break;
-		default:		printf ("Unknown Vendor ");	break;
+	case FLASH_MAN_INTEL:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
 	}

 	switch (info->flash_id & FLASH_TYPEMASK) {
-   case FLASH_28F128J3A:
-				printf ("28F128J3A\n"); break;
-	default:		printf ("Unknown Chip Type\n"); break;
-        }
+	case FLASH_28F128J3A:
+		printf ("28F128J3A\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}

 	printf ("  Size: %ld MB in %d Sectors\n",
-	        info->size >> 20, info->sector_count);
+			info->size >> 20, info->sector_count);

 	printf ("  Sector Start Addresses:");
-	for (i=0; i<info->sector_count; ++i) {
-	        if ((i % 5) == 0)
-	        printf ("\n   ");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
 		printf (" %08lX%s",
 			info->start[i],
-			info->protect[i] ? " (RO)" : "     "
-		);
-        }
-        printf ("\n");
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
 	return;
 }

@@ -163,37 +166,37 @@ static ulong flash_get_size (FPW *addr, flash_info_t *info)
 	volatile FPW value;

 	/* Write auto select command: read Manufacturer ID */
-	addr[0x5555] = (FPW)0x00AA00AA;
-	addr[0x2AAA] = (FPW)0x00550055;
-	addr[0x5555] = (FPW)0x00900090;
+	addr[0x5555] = (FPW) 0x00AA00AA;
+	addr[0x2AAA] = (FPW) 0x00550055;
+	addr[0x5555] = (FPW) 0x00900090;

-   mb();
+	mb ();
 	value = addr[0];

-   switch (value) {
+	switch (value) {

-   case (FPW)INTEL_MANUFACT:
-      info->flash_id = FLASH_MAN_INTEL;
-      break;
+	case (FPW) INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;

 	default:
 		info->flash_id = FLASH_UNKNOWN;
 		info->sector_count = 0;
 		info->size = 0;
-		addr[0] = (FPW)0x00FF00FF;      /* restore read mode */
-		return (0);			/* no or unknown flash	*/
+		addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+		return (0);			/* no or unknown flash  */
 	}

-   mb();
-	value = addr[1];			/* device ID		*/
+	mb ();
+	value = addr[1];			/* device ID        */

-   switch (value) {
+	switch (value) {

-   case (FPW)INTEL_ID_28F128J3A:
-      info->flash_id += FLASH_28F128J3A;
-      info->sector_count = 128;
-      info->size = 0x02000000;
-      break;            /* => 16 MB     */
+	case (FPW) INTEL_ID_28F128J3A:
+		info->flash_id += FLASH_28F128J3A;
+		info->sector_count = 128;
+		info->size = 0x02000000;
+		break;				/* => 16 MB     */

 	default:
 		info->flash_id = FLASH_UNKNOWN;
@@ -204,9 +207,9 @@ static ulong flash_get_size (FPW *addr, flash_info_t *info)
 		printf ("** ERROR: sector count %d > max (%d) **\n",
 			info->sector_count, CFG_MAX_FLASH_SECT);
 		info->sector_count = CFG_MAX_FLASH_SECT;
-    }
+	}

-	addr[0] = (FPW)0x00FF00FF;      /* restore read mode */
+	addr[0] = (FPW) 0x00FF00FF;		/* restore read mode */

 	return (info->size);
 }
@@ -215,34 +218,34 @@ static ulong flash_get_size (FPW *addr, flash_info_t *info)
 /*-----------------------------------------------------------------------
 */

-int	flash_erase (flash_info_t *info, int s_first, int s_last)
+int flash_erase (flash_info_t *info, int s_first, int s_last)
 {
-    int flag, prot, sect;
-	ulong type, start, now, last;
+	int flag, prot, sect;
+	ulong type, start, last;
 	int rcode = 0;

-    if ((s_first < 0) || (s_first > s_last)) {
+	if ((s_first < 0) || (s_first > s_last)) {
 		if (info->flash_id == FLASH_UNKNOWN) {
 			printf ("- missing\n");
 		} else {
 			printf ("- no sectors to erase\n");
 		}
 		return 1;
-    }
+	}

 	type = (info->flash_id & FLASH_VENDMASK);
 	if ((type != FLASH_MAN_INTEL)) {
 		printf ("Can't erase unknown flash type %08lx - aborted\n",
 			info->flash_id);
 		return 1;
-    }
-
-    prot = 0;
-    for (sect=s_first; sect<=s_last; ++sect) {
-	if (info->protect[sect]) {
-	    prot++;
 	}
-    }
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}

 	if (prot) {
 		printf ("- Warning: %d protected sectors will not be erased!\n",
@@ -252,42 +255,42 @@ int	flash_erase (flash_info_t *info, int s_first, int s_last)
 	}

 	start = get_timer (0);
-	last  = start;
+	last = start;

-   /* Disable interrupts which might cause a timeout here */
-    flag = disable_interrupts();
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();

-    /* Start erase on unprotected sectors */
-	for (sect = s_first; sect<=s_last; sect++) {
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
 		if (info->protect[sect] == 0) {	/* not protected */
-			FPWV *addr = (FPWV *)(info->start[sect]);
+			FPWV *addr = (FPWV *) (info->start[sect]);
 			FPW status;

-	printf("Erasing sector %2d ... ", sect);
+			printf ("Erasing sector %2d ... ", sect);

-	/* arm simple, non interrupt dependent timer */
-	reset_timer_masked();
+			/* arm simple, non interrupt dependent timer */
+			reset_timer_masked ();

-			*addr = (FPW)0x00500050;	/* clear status register */
-			*addr = (FPW)0x00200020;	/* erase setup */
-			*addr = (FPW)0x00D000D0;	/* erase confirm */
+			*addr = (FPW) 0x00500050;	/* clear status register */
+			*addr = (FPW) 0x00200020;	/* erase setup */
+			*addr = (FPW) 0x00D000D0;	/* erase confirm */

-			while (((status = *addr) & (FPW)0x00800080) != (FPW)0x00800080) {
-		if (get_timer_masked() > CFG_FLASH_ERASE_TOUT) {
+			while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+				if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
 					printf ("Timeout\n");
-					*addr = (FPW)0x00B000B0; /* suspend erase	  */
-					*addr = (FPW)0x00FF00FF; /* reset to read mode */
+					*addr = (FPW) 0x00B000B0;	/* suspend erase     */
+					*addr = (FPW) 0x00FF00FF;	/* reset to read mode */
 					rcode = 1;
 					break;
-	}
-    }
+				}
+			}

-			*addr = 0x00500050; /* clear status register cmd.   */
-			*addr = 0x00FF00FF; /* resest to read mode          */
+			*addr = 0x00500050;	/* clear status register cmd.   */
+			*addr = 0x00FF00FF;	/* resest to read mode          */

 			printf (" done\n");
-        }
-        }
+		}
+	}
 	return rcode;
 }

@@ -301,7 +304,7 @@ int	flash_erase (flash_info_t *info, int s_first, int s_last)

 int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
 {
-    ulong cp, wp;
+	ulong cp, wp;
 	FPW data;
 	int count, i, l, rc, port_width;

@@ -317,67 +320,66 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
 	port_width = 4;
 #endif

-    /*
-     * handle unaligned start bytes
-     */
-    if ((l = addr - wp) != 0) {
-	data = 0;
-	for (i=0, cp=wp; i<l; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *)cp);
-	}
-		for (; i<port_width && cnt>0; ++i) {
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < port_width && cnt > 0; ++i) {
 			data = (data << 8) | *src++;
-	    --cnt;
-	    ++cp;
-	}
-		for (; cnt==0 && i<port_width; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *)cp);
-	}
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < port_width; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}

-		if ((rc = write_data(info, wp, SWAP(data))) != 0) {
-	    return (rc);
-	}
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
 		wp += port_width;
-    }
+	}

-    /*
-     * handle word aligned part
-     */
+	/*
+	 * handle word aligned part
+	 */
 	count = 0;
 	while (cnt >= port_width) {
 		data = 0;
-		for (i=0; i<port_width; ++i) {
+		for (i = 0; i < port_width; ++i) {
 			data = (data << 8) | *src++;
 		}
-		if ((rc = write_data(info, wp, SWAP(data))) != 0) {
-	    return (rc);
-	}
-		wp  += port_width;
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
 		cnt -= port_width;
-		if (count++ > 0x800)
-		{
-         spin_wheel();
+		if (count++ > 0x800) {
+			spin_wheel ();
 			count = 0;
 		}
-    }
-
-    if (cnt == 0) {
-		return (0);
-    }
-
-    /*
-     * handle unaligned tail bytes
-     */
-    data = 0;
-	for (i=0, cp=wp; i<port_width && cnt>0; ++i, ++cp) {
-		data = (data << 8) | *src++;
-	--cnt;
-    }
-	for (; i<port_width; ++i, ++cp) {
-		data = (data << 8) | (*(uchar *)cp);
 	}

-	return (write_data(info, wp, SWAP(data)));
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < port_width; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_data (info, wp, SWAP (data)));
 }

 /*-----------------------------------------------------------------------
@@ -388,45 +390,42 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
 */
 static int write_data (flash_info_t *info, ulong dest, FPW data)
 {
-	FPWV *addr = (FPWV *)dest;
+	FPWV *addr = (FPWV *) dest;
 	ulong status;
-	ulong start;
 	int flag;

 	/* Check if Flash is (sufficiently) erased */
 	if ((*addr & data) != data) {
-		printf("not erased at %08lx (%x)\n",(ulong)addr,*addr);
+		printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr);
 		return (2);
 	}
 	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
+	flag = disable_interrupts ();

-	*addr = (FPW)0x00400040;		/* write setup */
+	*addr = (FPW) 0x00400040;	/* write setup */
 	*addr = data;

 	/* arm simple, non interrupt dependent timer */
-	reset_timer_masked();
+	reset_timer_masked ();

 	/* wait while polling the status register */
-	while (((status = *addr) & (FPW)0x00800080) != (FPW)0x00800080) {
-		if (get_timer_masked() > CFG_FLASH_WRITE_TOUT) {
-			*addr = (FPW)0x00FF00FF;	/* restore read mode */
+	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+		if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
 			return (1);
 		}
-    }
+	}

-	*addr = (FPW)0x00FF00FF;	/* restore read mode */
+	*addr = (FPW) 0x00FF00FF;	/* restore read mode */

 	return (0);
 }

-void inline
-spin_wheel(void)
+void inline spin_wheel (void)
 {
-   static int r=0,p=0;
-   static char w[] = "\\/-";
+	static int p = 0;
+	static char w[] = "\\/-";

-   printf("\010%c", w[p]);
-   (++p == 3) ? (p = 0) : 0;
+	printf ("\010%c", w[p]);
+	(++p == 3) ? (p = 0) : 0;
 }
-
--- a/board/lubbock/u-boot.lds
+++ b/board/lubbock/u-boot.lds
@@ -47,7 +47,9 @@ SECTIONS
 	armboot_end_data = .;

        . = ALIGN(4);
+	bss_start = .;
        .bss : { *(.bss) }
+	bss_end = .;

 	armboot_end = .;
 }
--- a/board/mpl/common/common_util.c
+++ b/board/mpl/common/common_util.c
@@ -27,6 +27,7 @@
 #include <video_fb.h>
 #include "common_util.h"
 #include <asm/processor.h>
+#include <asm/byteorder.h>
 #include <i2c.h>
 #include <devices.h>
 #include <pci.h>
@@ -39,7 +40,7 @@ extern int mem_test(unsigned long start, unsigned long ramsize, int quiet);

 extern flash_info_t flash_info[];	/* info for FLASH chips */

-image_header_t header;
+static image_header_t header;



@@ -48,9 +49,18 @@ int mpl_prg(unsigned long src,unsigned long size)
 	unsigned long start;
 	flash_info_t *info;
 	int i,rc;
+#if defined(CONFIG_PIP405) || defined(CONFIG_MIP405)
 	unsigned long *magic = (unsigned long *)src;
+#endif

 	info = &flash_info[0];
+
+#if defined(CONFIG_PIP405) || defined(CONFIG_MIP405)
+	if(ntohl(magic[0]) != IH_MAGIC) {
+		printf("Bad Magic number\n");
+		return -1;
+	}
+
  	start = 0 - size;
 	for(i=info->sector_count-1;i>0;i--)
 	{
@@ -60,13 +70,25 @@ int mpl_prg(unsigned long src,unsigned long size)
 	}
 	/* set-up flash location */
 	/* now erase flash */
-	if(magic[0]!=IH_MAGIC) {
-		printf("Bad Magic number\n");
-		return -1;
-	}
 	printf("Erasing at %lx (sector %d) (start %lx)\n",
 				start,i,info->start[i]);
 	flash_erase (info, i, info->sector_count-1);
+
+#elif defined(CONFIG_VCMA9)
+	start = 0;
+	for (i = 0; i <info->sector_count; i++)
+	{
+		info->protect[i] = 0; /* unprotect this sector */
+		if (size < info->start[i])
+		    break;
+	}
+	/* set-up flash location */
+	/* now erase flash */
+	printf("Erasing at %lx (sector %d) (start %lx)\n",
+				start,0,info->start[0]);
+	flash_erase (info, 0, i);
+
+#endif
 	printf("flash erased, programming from 0x%lx 0x%lx Bytes\n",src,size);
 	if ((rc = flash_write ((uchar *)src, start, size)) != 0) {
 		puts ("ERROR ");
@@ -84,7 +106,7 @@ int mpl_prg_image(unsigned long ld_addr)
 	image_header_t *hdr=&header;
 	/* Copy header so we can blank CRC field for re-calculation */
 	memcpy (&header, (char *)ld_addr, sizeof(image_header_t));
-	if (hdr->ih_magic  != IH_MAGIC) {
+	if (ntohl(hdr->ih_magic)  != IH_MAGIC) {
 		printf ("Bad Magic Number\n");
 		return 1;
 	}
@@ -99,16 +121,16 @@ int mpl_prg_image(unsigned long ld_addr)
 	}
 	data = (ulong)&header;
 	len  = sizeof(image_header_t);
-	checksum = hdr->ih_hcrc;
+	checksum = ntohl(hdr->ih_hcrc);
 	hdr->ih_hcrc = 0;
 	if (crc32 (0, (char *)data, len) != checksum) {
 		printf ("Bad Header Checksum\n");
 		return 1;
 	}
 	data = ld_addr + sizeof(image_header_t);
-	len  = hdr->ih_size;
+	len  = ntohl(hdr->ih_size);
 	printf ("Verifying Checksum ... ");
-	if (crc32 (0, (char *)data, len) != hdr->ih_dcrc) {
+	if (crc32 (0, (char *)data, len) != ntohl(hdr->ih_dcrc)) {
 		printf ("Bad Data CRC\n");
 		return 1;
 	}
@@ -152,14 +174,14 @@ void set_backup_values(int overwrite)
 		}
 	}
 	memcpy(back.signature,"MPL\0",4);
-	i=getenv_r("serial#",back.serial_name,16);
-	if(i==0) {
+	i = getenv_r("serial#",back.serial_name,16);
+	if(i < 0) {
 		printf("Not possible to write Backup\n");
 		return;
 	}
 	back.serial_name[16]=0;
-	i=getenv_r("ethaddr",back.eth_addr,20);
-	if(i==0) {
+	i = getenv_r("ethaddr",back.eth_addr,20);
+	if(i < 0) {
 		printf("Not possible to write Backup\n");
 		return;
 	}
@@ -301,7 +323,7 @@ extern char *stdio_names[];

 void show_stdio_dev(void)
 {
-	/* Print informations */
+	/* Print information */
 	printf ("In:    ");
 	if (stdio_devices[stdin] == NULL) {
 		printf ("No input devices available!\n");
@@ -338,7 +360,7 @@ void show_stdio_dev(void)
 #define SW_CS_PRINTF(fmt,args...)
 #endif

-
+#if defined(CONFIG_PIP405) || defined(CONFIG_MIP405)
 int switch_cs(unsigned char boot)
 {
  	unsigned long pbcr;
@@ -391,7 +413,12 @@ int switch_cs(unsigned char boot)
 		return 0;
 	}
 }
-
+#elif defined(CONFIG_VCMA9)
+int switch_cs(unsigned char boot)
+{
+    return 0;
+}
+#endif /* CONFIG_VCMA9 */

 int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
--- a/board/mpl/vcma9/Makefile
+++ b/board/mpl/vcma9/Makefile
@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= vcma9.o flash.o cmd_vcma9.o
+OBJS	+= ../common/common_util.o ../common/memtst.o
+
+SOBJS	:= memsetup.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
--- a/board/mpl/vcma9/cmd_vcma9.c
+++ b/board/mpl/vcma9/cmd_vcma9.c
@@ -0,0 +1,144 @@
+/*
+ * (C) Copyright 2002
+ * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
+ *
+ * adapted for VCMA9
+ * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <command.h>
+#include "vcma9.h"
+#include "../common/common_util.h"
+
+#if defined(CONFIG_DRIVER_CS8900)
+#include <../drivers/cs8900.h>
+
+static uchar cs8900_chksum(ushort data)
+{
+	return((data >> 8) & 0x00FF) + (data & 0x00FF);
+}
+
+#endif
+
+extern void print_vcma9_info(void);
+extern int vcma9_cantest(void);
+extern int vcma9_nandtest(void);
+extern int vcma9_dactest(void);
+extern int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+
+/* ------------------------------------------------------------------------- */
+
+int do_vcma9(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	if (strcmp(argv[1], "info") == 0)
+	{
+		print_vcma9_info();
+	 	return 0;
+   	}
+#if defined(CONFIG_DRIVER_CS8900)
+	if (strcmp(argv[1], "cs8900_eeprom") == 0) {
+		if (strcmp(argv[2], "read") == 0) {
+			uchar addr; ushort data;
+
+			addr = simple_strtoul(argv[3], NULL, 16);
+			cs8900_e2prom_read(addr, &data);
+			printf("0x%2.2X: 0x%4.4X\n", addr, data);
+		} else if (strcmp(argv[2], "write") == 0) {
+			uchar addr; ushort data;
+
+			addr = simple_strtoul(argv[3], NULL, 16);
+			data = simple_strtoul(argv[4], NULL, 16);
+			cs8900_e2prom_write(addr, data);
+		} else if (strcmp(argv[2], "setaddr") == 0) {
+			uchar addr, i, csum; ushort data;
+
+			/* check for valid ethaddr */
+			for (i = 0; i < 6; i++)
+				if (gd->bd->bi_enetaddr[i] != 0)
+					break;
+
+			if (i < 6) {
+				addr = 1;
+				data = 0x2158;
+				cs8900_e2prom_write(addr, data);
+				csum = cs8900_chksum(data);
+				addr++;
+				for (i = 0; i < 6; i+=2) {
+					data = gd->bd->bi_enetaddr[i+1] << 8 |
+					       gd->bd->bi_enetaddr[i];
+					cs8900_e2prom_write(addr, data);
+					csum += cs8900_chksum(data);
+					addr++;
+				}
+				/* calculate header link byte */
+				data = 0xA100 | (addr * 2);
+				cs8900_e2prom_write(0, data);
+				csum += cs8900_chksum(data);
+				/* write checksum word */
+				cs8900_e2prom_write(addr, (0 - csum) << 8);
+			} else {
+				printf("\nplease defined 'ethaddr'\n");
+			}
+		} else if (strcmp(argv[2], "dump") == 0) {
+			uchar addr = 0, endaddr, csum; ushort data;
+
+			printf("Dump of CS8900 config device: ");
+			cs8900_e2prom_read(addr, &data);
+			if ((data & 0xE000) == 0xA000) {
+				endaddr = (data & 0x00FF) / 2;
+				csum = cs8900_chksum(data);
+				for (addr = 1; addr <= endaddr; addr++) {
+					cs8900_e2prom_read(addr, &data);
+					printf("\n0x%2.2X: 0x%4.4X", addr, data);
+					csum += cs8900_chksum(data);
+				}
+				printf("\nChecksum: %s", (csum == 0) ? "ok" : "wrong");
+			} else {
+				printf("no valid config found");
+			}
+			printf("\n");
+		}
+
+		return 0;
+	}
+#endif
+#if 0
+	if (strcmp(argv[1], "cantest") == 0) {
+		vcma9_cantest();
+		return 0;
+	}
+	if (strcmp(argv[1], "nandtest") == 0) {
+		vcma9_nandtest();
+		return 0;
+	}
+	if (strcmp(argv[1], "dactest") == 0) {
+		vcma9_dactest();
+		return 0;
+	}
+#endif
+
+	return (do_mplcommon(cmdtp, flag, argc, argv));
+}
+
--- a/board/mpl/vcma9/config.mk
+++ b/board/mpl/vcma9/config.mk
@@ -0,0 +1,24 @@
+#
+# (C) Copyright 2002
+# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+#
+# MPL VCMA9 board with S3C2410X (ARM920T) cpu
+#
+# see http://www.mpl.ch/ for more information about the MPL VCMA9
+#
+
+#
+# MPL VCMA9 has 1 bank of 64 MB DRAM
+#
+# 3000'0000 to 3400'0000
+#
+# Linux-Kernel is expected to be at 3000'8000, entry 3000'8000
+# optionally with a ramdisk at 3080'0000
+#
+# we load ourself to 33F0'0000
+#
+# download area is 3300'0000
+#
+
+
+TEXT_BASE = 0x33F00000
--- a/board/mpl/vcma9/flash.c
+++ b/board/mpl/vcma9/flash.c
@@ -0,0 +1,445 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+ulong myflush(void);
+
+
+#define FLASH_BANK_SIZE	PHYS_FLASH_SIZE
+#define MAIN_SECT_SIZE  0x10000		/* 64 KB */
+
+flash_info_t    flash_info[CFG_MAX_FLASH_BANKS];
+
+
+#define CMD_READ_ARRAY		0x000000F0
+#define CMD_UNLOCK1		0x000000AA
+#define CMD_UNLOCK2		0x00000055
+#define CMD_ERASE_SETUP		0x00000080
+#define CMD_ERASE_CONFIRM	0x00000030
+#define CMD_PROGRAM		0x000000A0
+#define CMD_UNLOCK_BYPASS	0x00000020
+
+#define MEM_FLASH_ADDR1		(*(volatile u16 *)(CFG_FLASH_BASE + (0x00000555 << 1)))
+#define MEM_FLASH_ADDR2		(*(volatile u16 *)(CFG_FLASH_BASE + (0x000002AA << 1)))
+
+#define BIT_ERASE_DONE		0x00000080
+#define BIT_RDY_MASK		0x00000080
+#define BIT_PROGRAM_ERROR	0x00000020
+#define BIT_TIMEOUT		0x80000000 /* our flag */
+
+#define READY 1
+#define ERR   2
+#define TMO   4
+
+/*-----------------------------------------------------------------------
+ */
+
+ulong flash_init(void)
+{
+    int i, j;
+    ulong size = 0;
+
+    for (i = 0; i < CFG_MAX_FLASH_BANKS; i++)
+    {
+	ulong flashbase = 0;
+	flash_info[i].flash_id =
+#if defined(CONFIG_AMD_LV400)
+	  (AMD_MANUFACT & FLASH_VENDMASK) |
+	  (AMD_ID_LV400B & FLASH_TYPEMASK);
+#elif defined(CONFIG_AMD_LV800)
+	  (AMD_MANUFACT & FLASH_VENDMASK) |
+	  (AMD_ID_LV800B & FLASH_TYPEMASK);
+#else
+#error "Unknown flash configured"
+#endif
+	flash_info[i].size = FLASH_BANK_SIZE;
+	flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
+	memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+	if (i == 0)
+	  flashbase = PHYS_FLASH_1;
+	else
+	  panic("configured to many flash banks!\n");
+	for (j = 0; j < flash_info[i].sector_count; j++)
+	{
+	    if (j <= 3)
+	    {
+		/* 1st one is 16 KB */
+		if (j == 0)
+		{
+			flash_info[i].start[j] = flashbase + 0;
+		}
+
+		/* 2nd and 3rd are both 8 KB */
+		if ((j == 1) || (j == 2))
+		{
+			flash_info[i].start[j] = flashbase + 0x4000 + (j-1)*0x2000;
+		}
+
+		/* 4th 32 KB */
+		if (j == 3)
+		{
+			flash_info[i].start[j] = flashbase + 0x8000;
+		}
+	    }
+	    else
+	    {
+		flash_info[i].start[j] = flashbase + (j - 3)*MAIN_SECT_SIZE;
+	    }
+	}
+	size += flash_info[i].size;
+    }
+
+    flash_protect(FLAG_PROTECT_SET,
+		  CFG_FLASH_BASE,
+		  CFG_FLASH_BASE + _armboot_end - _armboot_start,
+		  &flash_info[0]);
+
+    flash_protect(FLAG_PROTECT_SET,
+		  CFG_ENV_ADDR,
+		  CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+		  &flash_info[0]);
+
+    return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+    int i;
+
+    switch (info->flash_id & FLASH_VENDMASK)
+    {
+    case (AMD_MANUFACT & FLASH_VENDMASK):
+	printf("AMD: ");
+	break;
+    default:
+	printf("Unknown Vendor ");
+	break;
+    }
+
+    switch (info->flash_id & FLASH_TYPEMASK)
+    {
+    case (AMD_ID_LV400B & FLASH_TYPEMASK):
+	printf("1x Amd29LV400BB (4Mbit)\n");
+	break;
+    case (AMD_ID_LV800B & FLASH_TYPEMASK):
+	printf("1x Amd29LV800BB (8Mbit)\n");
+	break;
+    default:
+	printf("Unknown Chip Type\n");
+	goto Done;
+	break;
+    }
+
+    printf("  Size: %ld MB in %d Sectors\n",
+	   info->size >> 20, info->sector_count);
+
+    printf("  Sector Start Addresses:");
+    for (i = 0; i < info->sector_count; i++)
+    {
+	if ((i % 5) == 0)
+	{
+	    printf ("\n   ");
+	}
+	printf (" %08lX%s", info->start[i],
+		info->protect[i] ? " (RO)" : "     ");
+    }
+    printf ("\n");
+
+Done:
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+    ushort result;
+    int iflag, cflag, prot, sect;
+    int rc = ERR_OK;
+    int chip;
+
+    /* first look for protection bits */
+
+    if (info->flash_id == FLASH_UNKNOWN)
+	return ERR_UNKNOWN_FLASH_TYPE;
+
+    if ((s_first < 0) || (s_first > s_last)) {
+	return ERR_INVAL;
+    }
+
+    if ((info->flash_id & FLASH_VENDMASK) !=
+	(AMD_MANUFACT & FLASH_VENDMASK)) {
+	return ERR_UNKNOWN_FLASH_VENDOR;
+    }
+
+    prot = 0;
+    for (sect=s_first; sect<=s_last; ++sect) {
+	if (info->protect[sect]) {
+	    prot++;
+	}
+    }
+    if (prot)
+	return ERR_PROTECTED;
+
+    /*
+     * Disable interrupts which might cause a timeout
+     * here. Remember that our exception vectors are
+     * at address 0 in the flash, and we don't want a
+     * (ticker) exception to happen while the flash
+     * chip is in programming mode.
+     */
+    cflag = icache_status();
+    icache_disable();
+    iflag = disable_interrupts();
+
+    /* Start erase on unprotected sectors */
+    for (sect = s_first; sect<=s_last && !ctrlc(); sect++)
+    {
+	printf("Erasing sector %2d ... ", sect);
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked();
+
+	if (info->protect[sect] == 0)
+	{	/* not protected */
+	    vu_short *addr = (vu_short *)(info->start[sect]);
+
+	    MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+	    MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+	    MEM_FLASH_ADDR1 = CMD_ERASE_SETUP;
+
+	    MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+	    MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+	    *addr = CMD_ERASE_CONFIRM;
+
+	    /* wait until flash is ready */
+	    chip = 0;
+
+	    do
+	    {
+		result = *addr;
+
+		/* check timeout */
+		if (get_timer_masked() > CFG_FLASH_ERASE_TOUT)
+		{
+		    MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
+		    chip = TMO;
+		    break;
+		}
+
+		if (!chip && (result & 0xFFFF) & BIT_ERASE_DONE)
+			chip = READY;
+
+		if (!chip && (result & 0xFFFF) & BIT_PROGRAM_ERROR)
+			chip = ERR;
+
+	    }  while (!chip);
+
+	    MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
+
+	    if (chip == ERR)
+	    {
+		rc = ERR_PROG_ERROR;
+		goto outahere;
+	    }
+	    if (chip == TMO)
+	    {
+		rc = ERR_TIMOUT;
+		goto outahere;
+	    }
+
+	    printf("ok.\n");
+	}
+	else /* it was protected */
+	{
+	    printf("protected!\n");
+	}
+    }
+
+    if (ctrlc())
+      printf("User Interrupt!\n");
+
+outahere:
+    /* allow flash to settle - wait 10 ms */
+    udelay_masked(10000);
+
+    if (iflag)
+      enable_interrupts();
+
+    if (cflag)
+      icache_enable();
+
+    return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash
+ */
+
+volatile static int write_hword (flash_info_t *info, ulong dest, ushort data)
+{
+    vu_short *addr = (vu_short *)dest;
+    ushort result;
+    int rc = ERR_OK;
+    int cflag, iflag;
+    int chip;
+
+    /*
+     * Check if Flash is (sufficiently) erased
+     */
+    result = *addr;
+    if ((result & data) != data)
+        return ERR_NOT_ERASED;
+
+
+    /*
+     * Disable interrupts which might cause a timeout
+     * here. Remember that our exception vectors are
+     * at address 0 in the flash, and we don't want a
+     * (ticker) exception to happen while the flash
+     * chip is in programming mode.
+     */
+    cflag = icache_status();
+    icache_disable();
+    iflag = disable_interrupts();
+
+    MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+    MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+    MEM_FLASH_ADDR1 = CMD_PROGRAM;
+    *addr = data;
+
+    /* arm simple, non interrupt dependent timer */
+    reset_timer_masked();
+
+    /* wait until flash is ready */
+    chip = 0;
+    do
+    {
+	result = *addr;
+
+	/* check timeout */
+	if (get_timer_masked() > CFG_FLASH_ERASE_TOUT)
+	{
+	    chip = ERR | TMO;
+	    break;
+	}
+	if (!chip && ((result & 0x80) == (data & 0x80)))
+		chip = READY;
+
+	if (!chip && ((result & 0xFFFF) & BIT_PROGRAM_ERROR))
+	{
+		result = *addr;
+
+		if ((result & 0x80) == (data & 0x80))
+			chip = READY;
+		else
+			chip = ERR;
+	}
+
+    }  while (!chip);
+
+    *addr = CMD_READ_ARRAY;
+
+    if (chip == ERR || *addr != data)
+        rc = ERR_PROG_ERROR;
+
+    if (iflag)
+      enable_interrupts();
+
+    if (cflag)
+      icache_enable();
+
+    return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash.
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+    ulong cp, wp;
+    int l;
+    int i, rc;
+    ushort data;
+
+    wp = (addr & ~1);	/* get lower word aligned address */
+
+    /*
+     * handle unaligned start bytes
+     */
+    if ((l = addr - wp) != 0) {
+	data = 0;
+	for (i=0, cp=wp; i<l; ++i, ++cp) {
+	    data = (data >> 8) | (*(uchar *)cp << 8);
+	}
+	for (; i<2 && cnt>0; ++i) {
+	    data = (data >> 8) | (*src++ << 8);
+	    --cnt;
+	    ++cp;
+	}
+	for (; cnt==0 && i<2; ++i, ++cp) {
+	    data = (data >> 8) | (*(uchar *)cp << 8);
+	}
+
+	if ((rc = write_hword(info, wp, data)) != 0) {
+	    return (rc);
+	}
+	wp += 2;
+    }
+
+    /*
+     * handle word aligned part
+     */
+    while (cnt >= 2) {
+	data = *((vu_short*)src);
+	if ((rc = write_hword(info, wp, data)) != 0) {
+	    return (rc);
+	}
+	src += 2;
+	wp  += 2;
+	cnt -= 2;
+    }
+
+    if (cnt == 0) {
+	return ERR_OK;
+    }
+
+    /*
+     * handle unaligned tail bytes
+     */
+    data = 0;
+    for (i=0, cp=wp; i<2 && cnt>0; ++i, ++cp) {
+	data = (data >> 8) | (*src++ << 8);
+	--cnt;
+    }
+    for (; i<2; ++i, ++cp) {
+	data = (data >> 8) | (*(uchar *)cp << 8);
+    }
+
+    return write_hword(info, wp, data);
+}
--- a/board/mpl/vcma9/memsetup.S
+++ b/board/mpl/vcma9/memsetup.S
@@ -0,0 +1,160 @@
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
+ *                     Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
+ *
+ * Modified for the Samsung SMDK2410 by
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+
+#include <config.h>
+#include <version.h>
+
+
+/* some parameters for the board */
+
+#define BWSCON	0x48000000
+
+/* BWSCON */
+#define DW8		 	(0x0)
+#define DW16		 	(0x1)
+#define DW32		 	(0x2)
+#define WAIT		 	(0x1<<2)
+#define UBLB		 	(0x1<<3)
+
+#define B1_BWSCON	  	(DW16)
+#define B2_BWSCON	  	(DW32)
+#define B3_BWSCON	  	(DW32)
+#define B4_BWSCON	  	(DW16 + WAIT + UBLB)
+#define B5_BWSCON	  	(DW8 + UBLB)
+#define B6_BWSCON	  	(DW32)
+#define B7_BWSCON	  	(DW32)
+
+/* BANK0CON */
+#define B0_Tacs		 	0x0	/*  0clk */
+#define B0_Tcos		 	0x0	/*  0clk */
+#define B0_Tacc		 	0x5	/*  8clk */
+#define B0_Tcoh		 	0x0	/*  0clk */
+#define B0_Tah		 	0x0	/*  0clk */
+#define B0_Tacp		 	0x0     /* page mode is not used */
+#define B0_PMC		 	0x0	/* page mode disabled */
+
+/* BANK1CON */
+#define B1_Tacs		 	0x0	/*  0clk */
+#define B1_Tcos		 	0x0	/*  0clk */
+#define B1_Tacc		 	0x5	/*  8clk */
+#define B1_Tcoh		 	0x0	/*  0clk */
+#define B1_Tah		 	0x0	/*  0clk */
+#define B1_Tacp		 	0x0     /* page mode is not used */
+#define B1_PMC		 	0x0	/* page mode disabled */
+
+#define B2_Tacs		 	0x3	/*  4clk */
+#define B2_Tcos		 	0x3	/*  4clk */
+#define B2_Tacc		 	0x7     /* 14clk */
+#define B2_Tcoh		 	0x3	/*  4clk */
+#define B2_Tah		 	0x3	/*  4clk */
+#define B2_Tacp		 	0x0	/* page mode is not used */
+#define B2_PMC		 	0x0     /* page mode disabled */
+
+#define B3_Tacs		 	0x3	/*  4clk */
+#define B3_Tcos		 	0x3	/*  4clk */
+#define B3_Tacc		 	0x7     /* 14clk */
+#define B3_Tcoh		 	0x3	/*  4clk */
+#define B3_Tah		 	0x3	/*  4clk */
+#define B3_Tacp		 	0x0	/* page mode is not used */
+#define B3_PMC		 	0x0     /* page mode disabled */
+
+#define B4_Tacs		 	0x3	/*  4clk */
+#define B4_Tcos		 	0x1	/*  1clk */
+#define B4_Tacc		 	0x7	/* 14clk */
+#define B4_Tcoh		 	0x1	/*  1clk */
+#define B4_Tah		 	0x0	/*  0clk */
+#define B4_Tacp		 	0x0     /* page mode is not used */
+#define B4_PMC		 	0x0	/* page mode disabled */
+
+#define B5_Tacs		 	0x0	/*  0clk */
+#define B5_Tcos		 	0x3	/*  4clk */
+#define B5_Tacc		 	0x5	/*  8clk */
+#define B5_Tcoh		 	0x2	/*  2clk */
+#define B5_Tah		 	0x1	/*  1clk */
+#define B5_Tacp		 	0x0     /* page mode is not used */
+#define B5_PMC		 	0x0	/* page mode disabled */
+
+#define B6_MT		 	0x3	/* SDRAM */
+#define B6_Trcd	 	 	0x1	/* 3clk */
+#define B6_SCAN		 	0x2	/* 10bit */
+
+#define B7_MT		 	0x3	/* SDRAM */
+#define B7_Trcd		 	0x1	/* 3clk */
+#define B7_SCAN		 	0x2	/* 10bit */
+
+/* REFRESH parameter */
+#define REFEN		 	0x1	/* Refresh enable */
+#define TREFMD		 	0x0	/* CBR(CAS before RAS)/Auto refresh */
+#define Trp		 	0x0	/* 2clk */
+#define Trc		 	0x3	/* 7clk */
+#define Tchr		 	0x2	/* 3clk */
+#define REFCNT		 	1113	/* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */
+/**************************************/
+
+_TEXT_BASE:
+	.word	TEXT_BASE
+
+.globl memsetup
+memsetup:
+	/* memory control configuration */
+	/* make r0 relative the current location so that it */
+	/* reads SMRDATA out of FLASH rather than memory ! */
+	ldr     r0, =SMRDATA
+	ldr	r1, _TEXT_BASE
+	sub	r0, r0, r1
+	ldr	r1, =BWSCON	/* Bus Width Status Controller */
+	add     r2, r0, #13*4
+0:
+	ldr     r3, [r0], #4
+	str     r3, [r1], #4
+	cmp     r2, r0
+	bne     0b
+
+	/* everything is fine now */
+	mov	pc, lr
+
+	.ltorg
+/* the literal pools origin */
+
+SMRDATA:
+    .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
+    .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))
+    .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))
+    .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))
+    .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))
+    .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))
+    .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))
+    .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
+    .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
+    .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
+    .word 0x32
+    .word 0x30
+    .word 0x30
--- a/board/mpl/vcma9/u-boot.lds
+++ b/board/mpl/vcma9/u-boot.lds
@@ -0,0 +1,54 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+        . = 0x00000000;
+
+        . = ALIGN(4);
+	.text      :
+	{
+	  cpu/arm920t/start.o	(.text)
+	  *(.text)
+	}
+
+        . = ALIGN(4);
+        .rodata : { *(.rodata) }
+
+        . = ALIGN(4);
+        .data : { *(.data) }
+
+        . = ALIGN(4);
+        .got : { *(.got) }
+
+	armboot_end_data = .;
+
+        . = ALIGN(4);
+        .bss : { *(.bss) }
+
+	armboot_end = .;
+}
--- a/board/mpl/vcma9/vcma9.c
+++ b/board/mpl/vcma9/vcma9.c
@@ -0,0 +1,247 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <s3c2410.h>
+#include <i2c.h>
+
+#include "vcma9.h"
+#include "../common/common_util.h"
+
+/* ------------------------------------------------------------------------- */
+
+#define FCLK_SPEED 1
+
+#if FCLK_SPEED==0		/* Fout = 203MHz, Fin = 12MHz for Audio */
+#define M_MDIV	0xC3
+#define M_PDIV	0x4
+#define M_SDIV	0x1
+#elif FCLK_SPEED==1		/* Fout = 202.8MHz */
+#define M_MDIV	0xA1
+#define M_PDIV	0x3
+#define M_SDIV	0x1
+#endif
+
+#define USB_CLOCK 1
+
+#if USB_CLOCK==0
+#define U_M_MDIV	0xA1
+#define U_M_PDIV	0x3
+#define U_M_SDIV	0x1
+#elif USB_CLOCK==1
+#define U_M_MDIV	0x48
+#define U_M_PDIV	0x3
+#define U_M_SDIV	0x2
+#endif
+
+static inline void delay(unsigned long loops)
+{
+	__asm__ volatile ("1:\n"
+	  "subs %0, %1, #1\n"
+	  "bne 1b":"=r" (loops):"0" (loops));
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+int board_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* to reduce PLL lock time, adjust the LOCKTIME register */
+	rLOCKTIME = 0xFFFFFF;
+
+	/* configure MPLL */
+	rMPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
+
+	/* some delay between MPLL and UPLL */
+	delay (4000);
+
+	/* configure UPLL */
+	rUPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
+
+	/* some delay between MPLL and UPLL */
+	delay (8000);
+
+	/* set up the I/O ports */
+	rGPACON = 0x007FFFFF;
+	rGPBCON = 0x002AAAAA;
+	rGPBUP = 0x000002BF;
+	rGPCCON = 0xAAAAAAAA;
+	rGPCUP = 0x0000FFFF;
+	rGPDCON = 0xAAAAAAAA;
+	rGPDUP = 0x0000FFFF;
+	rGPECON = 0xAAAAAAAA;
+	rGPEUP = 0x000037F7;
+	rGPFCON = 0x00000000;
+	rGPFUP = 0x00000000;
+	rGPGCON = 0xFFEAFF5A;
+	rGPGUP = 0x0000F0DC;
+	rGPHCON = 0x0028AAAA;
+	rGPHUP = 0x00000656;
+
+	/* setup correct IRQ modes for NIC */
+	rEXTINT2 = (rEXTINT2 & ~(7<<8)) | (4<<8); /* rising edge mode */
+
+	/* init serial */
+	gd->baudrate = CONFIG_BAUDRATE;
+	gd->have_console = 1;
+	serial_init();
+
+	/* arch number of VCMA9-Board */
+	gd->bd->bi_arch_number = 227;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0x30000100;
+
+	icache_enable();
+	dcache_enable();
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+/*
+ * Get some Board/PLD Info
+ */
+
+static uchar Get_PLD_ID(void)
+{
+	return(*(volatile uchar *)PLD_ID_REG);
+}
+
+static uchar Get_PLD_BOARD(void)
+{
+	return(*(volatile uchar *)PLD_BOARD_REG);
+}
+
+static uchar Get_PLD_Version(void)
+{
+	return((Get_PLD_ID() >> 4) & 0x0F);
+}
+
+static uchar Get_PLD_Revision(void)
+{
+	return(Get_PLD_ID() & 0x0F);
+}
+
+static int Get_Board_Config(void)
+{
+	uchar config = Get_PLD_BOARD() & 0x03;
+
+	if (config == 3)
+	    return 1;
+	else
+	    return 0;
+}
+
+static uchar Get_Board_PCB(void)
+{
+	return(((Get_PLD_BOARD() >> 4) & 0x03) + 'A');
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard(void)
+{
+	unsigned char s[50];
+	int i;
+	backup_t *b = (backup_t *) s;
+
+	puts("Board: ");
+
+	i = getenv_r("serial#", s, 32);
+	if ((i < 0) || strncmp (s, "VCMA9", 5)) {
+		get_backup_values (b);
+		if (strncmp (b->signature, "MPL\0", 4) != 0) {
+			puts ("### No HW ID - assuming VCMA9");
+		} else {
+			b->serial_name[5] = 0;
+			printf ("%s-%d Rev %c SN: %s", b->serial_name, Get_Board_Config(),
+					Get_Board_PCB(), &b->serial_name[6]);
+		}
+	} else {
+		s[5] = 0;
+		printf ("%s-%d Rev %c SN: %s", s, Get_Board_Config(), Get_Board_PCB(),
+				&s[6]);
+	}
+	printf("\n");
+	return(0);
+}
+
+
+
+void print_vcma9_rev(void)
+{
+	printf("Board: VCMA9-%d Rev: %c (PLD Ver: %d, Rev: %d)\n",
+		Get_Board_Config(), Get_Board_PCB(),
+		Get_PLD_Version(), Get_PLD_Revision());
+}
+
+
+int last_stage_init(void)
+{
+	print_vcma9_rev();
+	show_stdio_dev();
+	check_env();
+	return 0;
+}
+
+/***************************************************************************
+ * some helping routines
+ */
+
+int overwrite_console(void)
+{
+	/* return TRUE if console should be overwritten */
+	return 0;
+}
+
+
+/************************************************************************
+* Print VCMA9 Info
+************************************************************************/
+void print_vcma9_info(void)
+{
+    print_vcma9_rev();
+}
+
+
--- a/board/mpl/vcma9/vcma9.h
+++ b/board/mpl/vcma9/vcma9.h
@@ -0,0 +1,43 @@
+/*
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+ /****************************************************************************
+ * Global routines used for VCMA9
+ *****************************************************************************/
+
+
+extern int  mem_test(unsigned long start, unsigned long ramsize,int mode);
+
+void print_vcma9_info(void);
+
+
+#define PLD_BASE_ADDRESS		0x2C000100
+#define PLD_ID_REG			(PLD_BASE_ADDRESS + 0)
+#define PLD_NIC_REG			(PLD_BASE_ADDRESS + 1)
+#define PLD_CAN_REG			(PLD_BASE_ADDRESS + 2)
+#define PLD_MISC_REG			(PLD_BASE_ADDRESS + 3)
+#define PLD_GPCD_REG			(PLD_BASE_ADDRESS + 4)
+#define PLD_BOARD_REG			(PLD_BASE_ADDRESS + 5)
+
+
+
--- a/board/pm826/config.mk
+++ b/board/pm826/config.mk
@@ -33,10 +33,10 @@
 #

 ifeq ($(CONFIG_BOOT_ROM),y)
-	TEXT_BASE := 0x60000000
+	TEXT_BASE := 0xFF800000
 	PLATFORM_CPPFLAGS += -DCONFIG_BOOT_ROM
 else
-	TEXT_BASE := 0x40000000
+	TEXT_BASE := 0xFF000000
 endif

 PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)
--- a/board/trab/flash.c
+++ b/board/trab/flash.c
@@ -124,11 +124,10 @@ void flash_print_info (flash_info_t * info)

 	switch (info->flash_id & FLASH_VENDMASK) {
 	case (FLASH_MAN_AMD & FLASH_VENDMASK):
-		printf ("AMD: ");
-		break;
-	default:
-		printf ("Unknown Vendor ");
-		break;
+			printf ("AMD ");		break;
+	case (FLASH_MAN_FUJ & FLASH_VENDMASK):
+			printf ("FUJITSU ");		break;
+	default:	printf ("Unknown Vendor ");	break;
 	}

 	switch (info->flash_id & FLASH_TYPEMASK) {
@@ -186,9 +185,12 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
 		return ERR_INVAL;
 	}

-	if ((info->flash_id & FLASH_VENDMASK) !=
-		(FLASH_MAN_AMD & FLASH_VENDMASK)) {
-		return ERR_UNKNOWN_FLASH_VENDOR;
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case (FLASH_MAN_AMD & FLASH_VENDMASK):	break;	/* OK */
+	case (FLASH_MAN_FUJ & FLASH_VENDMASK):	break;	/* OK */
+	default:
+		debug ("## flash_erase: unknown manufacturer\n");
+		return (ERR_UNKNOWN_FLASH_VENDOR);
 	}

 	prot = 0;
@@ -477,7 +479,9 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 	case AMD_MANUFACT:
 		info->flash_id = FLASH_MAN_AMD;
 		break;
-
+	case FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
 	default:
 		info->flash_id = FLASH_UNKNOWN;
 		info->sector_count = 0;
--- a/board/trab/trab.c
+++ b/board/trab/trab.c
@@ -30,6 +30,13 @@

 /* ------------------------------------------------------------------------- */

+#ifdef CFG_BRIGHTNESS
+static void spi_init(void);
+static void wait_transmit_done(void);
+static void tsc2000_write(unsigned int page, unsigned int reg, 
+						  unsigned int data);
+static void tsc2000_set_brightness(void);
+#endif
 #ifdef CONFIG_MODEM_SUPPORT
 static int key_pressed(void);
 extern void disable_putc(void);
@@ -104,6 +111,10 @@ int board_init ()
 	/* adress of boot parameters */
 	gd->bd->bi_boot_params = 0x0c000100;

+	/* Make sure both buzzers are turned off */
+	rPDCON |= 0x5400;
+	rPDDAT &= ~0xE0;
+
 #ifdef CONFIG_VFD
 	vfd_init_clocks();
 #endif /* CONFIG_VFD */
@@ -164,6 +175,9 @@ int misc_init_r (void)
 		free (str);
 	}

+#ifdef CFG_BRIGHTNESS
+	tsc2000_set_brightness();
+#endif
 	return (0);
 }

@@ -288,3 +302,74 @@ static int key_pressed(void)
 	return (compare_magic(KBD_DATA, CONFIG_MODEM_KEY_MAGIC) == 0);
 }
 #endif	/* CONFIG_MODEM_SUPPORT */
+
+#ifdef CFG_BRIGHTNESS
+
+#define SET_CS_TOUCH        (rPDDAT &= 0x5FF)
+#define CLR_CS_TOUCH        (rPDDAT |= 0x200)
+
+static void spi_init(void)
+{
+	int i;
+
+	/* Configure I/O ports. */
+ 	rPDCON = (rPDCON & 0xF3FFFF) | 0x040000;
+	rPGCON = (rPGCON & 0x0F3FFF) | 0x008000;
+	rPGCON = (rPGCON & 0x0CFFFF) | 0x020000;
+	rPGCON = (rPGCON & 0x03FFFF) | 0x080000;
+
+	CLR_CS_TOUCH;
+
+	rSPPRE = 0x1F; /* Baudrate ca. 514kHz */
+	rSPPIN = 0x01;  /* SPI-MOSI holds Level after last bit */
+	rSPCON = 0x1A;  /* Polling, Prescaler, Master, CPOL=0, CPHA=1 */
+
+	/* Dummy byte ensures clock to be low. */
+	for (i = 0; i < 10; i++) {
+		rSPTDAT = 0xFF;
+	}
+}
+
+static void wait_transmit_done(void)
+{
+	while (!(rSPSTA & 0x01)); /* wait until transfer is done */
+}
+
+static void tsc2000_write(unsigned int page, unsigned int reg, 
+						  unsigned int data)
+{
+	unsigned int command;
+
+	SET_CS_TOUCH;
+	command = 0x0000;
+	command |= (page << 11);
+	command |= (reg << 5);
+
+	rSPTDAT = (command & 0xFF00) >> 8;
+	wait_transmit_done();
+	rSPTDAT = (command & 0x00FF);
+	wait_transmit_done();
+	rSPTDAT = (data & 0xFF00) >> 8;
+	wait_transmit_done();
+	rSPTDAT = (data & 0x00FF);
+	wait_transmit_done();
+
+	CLR_CS_TOUCH;
+}
+
+static void tsc2000_set_brightness(void)
+{
+	uchar tmp[10];
+	int i, br;
+
+	spi_init();
+	tsc2000_write(1, 2, 0x0); /* Power up DAC */
+
+	i = getenv_r("brightness", tmp, sizeof(tmp));
+	br = (i > 0)
+		? (int) simple_strtoul (tmp, NULL, 10)
+		: CFG_BRIGHTNESS;
+
+	tsc2000_write(0, 0xb, br & 0xff);
+}
+#endif
--- a/board/trab/u-boot.lds
+++ b/board/trab/u-boot.lds
@@ -38,7 +38,7 @@ SECTIONS
 	  lib_generic/crc32.o	(.text)
 	  lib_generic/string.o	(.text)

-	. = env_offset;
+	. = DEFINED(env_offset) ? env_offset : .;
 	common/environment.o	(.ppcenv)

 	  *(.text)
--- a/board/trab/vfd.c
+++ b/board/trab/vfd.c
@@ -55,14 +55,28 @@
 #define BLAU	0x0C
 #define VIOLETT	0X0D

-ulong	vfdbase;
-ulong	frame_buf_size;
+/* MAGIC */
+#define	FRAME_BUF_SIZE	((256*4*56)/8)
 #define frame_buf_offs 4

+/* defines for starting Timer3 as CPLD-Clk */
+#define START3			(1 << 16)
+#define UPDATE3			(1 << 17)
+#define INVERT3			(1 << 18)
+#define RELOAD3			(1 << 19)
+
+/* CPLD-Register for controlling vfd-blank-signal */
+#define VFD_DISABLE	(*(volatile uchar *)0x04038000=0x0000)
+#define VFD_ENABLE	(*(volatile uchar *)0x04038000=0x0001)
+
 /* Supported VFD Types */
 #define	VFD_TYPE_T119C		1	/* Noritake T119C VFD */
 #define	VFD_TYPE_MN11236	2

+/*#define NEW_CPLD_CLK*/
+
+int vfd_board_id;
+
 /* taken from armboot/common/vfd.c */
 unsigned long adr_vfd_table[112][18][2][4][2];
 unsigned char bit_vfd_table[112][18][2][4][2];
@@ -76,19 +90,11 @@ void init_grid_ctrl(void)
 	ulong adr, grid_cycle;
 	unsigned int bit, display;
 	unsigned char temp, bit_nr;
-	ulong val;

 	/*
 	 * clear frame buffer (logical clear => set to "black")
 	 */
-	if (gd->vfd_inv_data == 0)
-		val = 0;
-	else
-		val = ~0;
-
-	for (adr = vfdbase; adr <= (vfdbase+7168); adr += 4) {
-		(*(volatile ulong*)(adr)) = val;
-	}
+	memset ((void *)(gd->fb_base), 0, FRAME_BUF_SIZE);

 	switch (gd->vfd_type) {
 	case VFD_TYPE_T119C:
@@ -98,16 +104,13 @@ void init_grid_ctrl(void)
 			     (grid_cycle + 200) * 4 +
 			     frame_buf_offs + display;
 			/* wrap arround if offset (see manual S3C2400) */
-			if (bit>=frame_buf_size*8)
-				bit = bit - (frame_buf_size * 8);
-			adr = vfdbase + (bit/32) * 4 + (3 - (bit%32) / 8);
+			if (bit>=FRAME_BUF_SIZE*8)
+				bit = bit - (FRAME_BUF_SIZE * 8);
+			adr = gd->fb_base + (bit/32) * 4 + (3 - (bit%32) / 8);
 			bit_nr = bit % 8;
 			bit_nr = (bit_nr > 3) ? bit_nr-4 : bit_nr+4;
 			temp=(*(volatile unsigned char*)(adr));
-			if (gd->vfd_inv_data)
-				temp &= ~(1<<bit_nr);
-			else
-				temp |=  (1<<bit_nr);
+			temp |=  (1<<bit_nr);
 			(*(volatile unsigned char*)(adr))=temp;

 			if(grid_cycle<55)
@@ -115,16 +118,13 @@ void init_grid_ctrl(void)
 			else
 				bit = grid_cycle*256*4+200*4+frame_buf_offs+display-4; 	/* grid nr. 0 */
 			/* wrap arround if offset (see manual S3C2400) */
-			if (bit>=frame_buf_size*8)
-				bit = bit-(frame_buf_size*8);
-			adr = vfdbase+(bit/32)*4+(3-(bit%32)/8);
+			if (bit>=FRAME_BUF_SIZE*8)
+				bit = bit-(FRAME_BUF_SIZE*8);
+			adr = gd->fb_base+(bit/32)*4+(3-(bit%32)/8);
 			bit_nr = bit%8;
 			bit_nr = (bit_nr>3)?bit_nr-4:bit_nr+4;
 			temp=(*(volatile unsigned char*)(adr));
-			if (gd->vfd_inv_data)
-				temp &= ~(1<<bit_nr);
-			else
-				temp |=  (1<<bit_nr);
+			temp |=  (1<<bit_nr);
 			(*(volatile unsigned char*)(adr))=temp;
 		}
 	    }
@@ -136,32 +136,26 @@ void init_grid_ctrl(void)
 			     (253 - grid_cycle) * 4 +
 			     frame_buf_offs + display;
 			/* wrap arround if offset (see manual S3C2400) */
-			if (bit>=frame_buf_size*8)
-				bit = bit - (frame_buf_size * 8);
-			adr = vfdbase + (bit/32) * 4 + (3 - (bit%32) / 8);
+			if (bit>=FRAME_BUF_SIZE*8)
+				bit = bit - (FRAME_BUF_SIZE * 8);
+			adr = gd->fb_base + (bit/32) * 4 + (3 - (bit%32) / 8);
 			bit_nr = bit % 8;
 			bit_nr = (bit_nr > 3) ? bit_nr-4 : bit_nr+4;
 			temp=(*(volatile unsigned char*)(adr));
-			if (gd->vfd_inv_data)
-				temp &= ~(1<<bit_nr);
-			else
-				temp |=  (1<<bit_nr);
+			temp |=  (1<<bit_nr);
 			(*(volatile unsigned char*)(adr))=temp;

 			if(grid_cycle<37)
 				bit = grid_cycle*256*4+(252-grid_cycle)*4+frame_buf_offs+display;

 			/* wrap arround if offset (see manual S3C2400) */
-			if (bit>=frame_buf_size*8)
-				bit = bit-(frame_buf_size*8);
-			adr = vfdbase+(bit/32)*4+(3-(bit%32)/8);
+			if (bit>=FRAME_BUF_SIZE*8)
+				bit = bit-(FRAME_BUF_SIZE*8);
+			adr = gd->fb_base+(bit/32)*4+(3-(bit%32)/8);
 			bit_nr = bit%8;
 			bit_nr = (bit_nr>3)?bit_nr-4:bit_nr+4;
 			temp=(*(volatile unsigned char*)(adr));
-			if (gd->vfd_inv_data)
-				temp &= ~(1<<bit_nr);
-			else
-				temp |=  (1<<bit_nr);
+			temp |=  (1<<bit_nr);
 			(*(volatile unsigned char*)(adr))=temp;
 		}
 	    }
@@ -254,9 +248,9 @@ void create_vfd_table(void)
 		for(color=0;color<2;color++) {
 		    for(display=0;display<4;display++) {
 			for(entry=0;entry<2;entry++) {
-			    unsigned long adr  = vfdbase;
+			    unsigned long adr  = gd->fb_base;
 			    unsigned int bit_nr = 0;
-			    
+
 			    if (vfd_table[x][y][color][display][entry]) {

 				pixel  = vfd_table[x][y][color][display][entry] + frame_buf_offs;
@@ -264,9 +258,9 @@ void create_vfd_table(void)
 				  * wrap arround if offset
 				  * (see manual S3C2400)
 				  */
-				if (pixel>=frame_buf_size*8)
-					pixel = pixel-(frame_buf_size*8);
-				adr    = vfdbase+(pixel/32)*4+(3-(pixel%32)/8);
+				if (pixel>=FRAME_BUF_SIZE*8)
+					pixel = pixel-(FRAME_BUF_SIZE*8);
+				adr    = gd->fb_base+(pixel/32)*4+(3-(pixel%32)/8);
 				bit_nr = pixel%8;
 				bit_nr = (bit_nr>3)?bit_nr-4:bit_nr+4;
 			    }
@@ -301,18 +295,11 @@ void set_vfd_pixel(unsigned char x, unsigned char y,
 	bit_nr = bit_vfd_table[x][y][color][display][0];
 	temp=(*(volatile unsigned char*)(adr));

-	if (gd->vfd_inv_data) {
-		if (value)
-			temp &= ~(1<<bit_nr);
-		else
-			temp |=  (1<<bit_nr);
-	} else {
-		if (value)
-			temp |=  (1<<bit_nr);
-		else
-			temp &= ~(1<<bit_nr);
-	}
-	
+	if (value)
+		temp |=  (1<<bit_nr);
+	else
+		temp &= ~(1<<bit_nr);
+
 	(*(volatile unsigned char*)(adr))=temp;
 }

@@ -369,33 +356,78 @@ void transfer_pic(int display, unsigned char *adr, int height, int width)
 * This function initializes VFD clock that is needed for the CPLD that
 * manages the keyboard.
 */
-int vfd_init_clocks(void)
+int vfd_init_clocks (void)
 {
-	/* Port-Pins als LCD-Ausgang */
-	rPCCON =   (rPCCON & 0xFFFFFF00)| 0x000000AA;
-	/* Port-Pins als LCD-Ausgang */
-	rPDCON =   (rPDCON & 0xFFFFFF03)| 0x000000A8;
-#ifdef WITH_VFRAME
-	/* mit VFRAME zum Messen */
-	rPDCON =   (rPDCON & 0xFFFFFF00)| 0x000000AA;
-#endif

-	rLCDCON2 = 0x000DC000;
-	rLCDCON3 = 0x0051000A;
-	rLCDCON4 = 0x00000001;
-	rLCDCON5 = 0x00000440;
+	/* try to determine display type from the value
+	 * defined by pull-ups
+	 */
+	rPCUP = (rPCUP & 0xFFF0);	/* activate  GPC0...GPC3 pullups */
+	rPCCON = (rPCCON & 0xFFFFFF00);	/* configure GPC0...GPC3 as inputs */
+	udelay (10);				/* allow signals to settle */
+	vfd_board_id = (~rPCDAT) & 0x000F;	/* read GPC0...GPC3 port pins */
+
+	VFD_DISABLE;				/* activate blank for the vfd */
+
+#define	NEW_CPLD_CLK
+
+#ifdef NEW_CPLD_CLK
+	if (vfd_board_id) {
+		/* If new board revision, then use PWM 3 as cpld-clock */
+		/* Enable 500 Hz timer for fill level sensor to operate properly */
+		/* Configure TOUT3 as functional pin, disable pull-up */
+		rPDCON &= ~0x30000;
+		rPDCON |= 0x20000;
+		rPDUP |= (1 << 8);
+
+		/* Configure the prescaler */
+		rTCFG0 &= ~0xff00;
+		rTCFG0 |= 0x0f00;
+
+		/* Select MUX input (divider) for timer3 (1/16) */
+		rTCFG1 &= ~0xf000;
+		rTCFG1 |= 0x3000;
+
+		/* Enable autoreload and set the counter and compare
+		 * registers to values for the 500 Hz clock
+		 * (for a given  prescaler (15) and divider (16)):
+		 * counter = (66000000 / 500) >> 9;
+		 */
+		rTCNTB3 = 0x101;
+		rTCMPB3 = 0x101 / 2;
+
+		/* Start timer */
+		rTCON = (rTCON | UPDATE3 | RELOAD3) & ~INVERT3;
+		rTCON = (rTCON | START3) & ~UPDATE3;
+	}
+#endif
+	/* If old board revision, then use vm-signal as cpld-clock */
+	rLCDCON2 = 0x00FFC000;
+	rLCDCON3 = 0x0007FF00;
+	rLCDCON4 = 0x00000000;
+	rLCDCON5 = 0x00000400;
 	rLCDCON1 = 0x00000B75;
+	/* VM (GPD1) is used as clock for the CPLD */
+	rPDCON = (rPDCON & 0xFFFFFFF3) | 0x00000008;
+
+	return 0;
 }

 /*
 * initialize LCD-Controller of the S3C2400 for using VFDs
+ *
+ * VFD detection depends on the board revision:
+ * starting from Rev. 200 a type code can be read from the data pins,
+ * driven by some pull-up resistors; all earlier systems must be
+ * manually configured. The type is set in the "vfd_type" environment
+ * variable.
 */
 int drv_vfd_init(void)
 {
 	char *tmp;
 	ulong palette;
 	static int vfd_init_done = 0;
-	int vfd_id;
+	int vfd_inv_data = 0;

 	DECLARE_GLOBAL_DATA_PTR;

@@ -403,24 +435,10 @@ int drv_vfd_init(void)
 		return (0);
 	vfd_init_done = 1;

-	/* try to determine display type from the value
-	 * defined by pull-ups
-	 */
-	rPCUP  = (rPCUP | 0x000F);	/* activate  GPC0...GPC3 pullups */
-	rPCCON = (rPCCON & 0xFFFFFF00);	/* configure GPC0...GPC3 as inputs */
+	debug("Detecting Revison of WA4-VFD: ID=0x%X\n", vfd_board_id);

-	vfd_id = (~rPCDAT) & 0x000F;	/* read GPC0...GPC3 port pins */
-	debug("Detecting Revison of WA4-VFD: ID=0x%X\n", vfd_id);
-
-	switch (vfd_id) {
-	case 0:				/* board revision <= Rev.100 */
-/*-----*/
-		gd->vfd_inv_data = 0;
-		if (0)
-			gd->vfd_type = VFD_TYPE_MN11236;
-		else
-			gd->vfd_type = VFD_TYPE_T119C;
-/*-----*/
+	switch (vfd_board_id) {
+	case 0:			/* board revision < Rev.200 */
 		if ((tmp = getenv ("vfd_type")) == NULL) {
 			break;
 		}
@@ -432,21 +450,20 @@ int drv_vfd_init(void)
 			/* cannot use printf for a warning here */
 			gd->vfd_type = 0;	/* unknown */
 		}
-		gd->vfd_inv_data = 0;

 		break;
-	default:			/* default to MN11236, data inverted */
+	default:		/* default to MN11236, data inverted */
 		gd->vfd_type = VFD_TYPE_MN11236;
-		gd->vfd_inv_data = 1;
+		vfd_inv_data = 1;
 		setenv ("vfd_type", "MN11236");
 	}
 	debug ("VFD type: %s%s\n",
 		(gd->vfd_type == VFD_TYPE_T119C)   ? "T119C" :
 		(gd->vfd_type == VFD_TYPE_MN11236) ? "MN11236" :
 		"unknown",
-		gd->vfd_inv_data ? ", inverted data" : "");
+		vfd_inv_data ? ", inverted data" : "");

-	vfdbase = gd->fb_base;
+	gd->fb_base = gd->fb_base;
 	create_vfd_table();
 	init_grid_ctrl();

@@ -462,11 +479,33 @@ int drv_vfd_init(void)
 	 * (wrap around)
 	 * see manual S3C2400
 	 */
+	/* Stopp LCD-Controller */
+	rLCDCON1 = 0x00000000;
 	/* frame buffer startadr */
-	rLCDSADDR1 = vfdbase >> 1;
+	rLCDSADDR1 = gd->fb_base >> 1;
 	/* frame buffer endadr */
-	rLCDSADDR2 = (vfdbase + frame_buf_size) >> 1;
+	rLCDSADDR2 = (gd->fb_base + FRAME_BUF_SIZE) >> 1;
 	rLCDSADDR3 = ((256/4));
+	rLCDCON2 = 0x000DC000;
+	rLCDCON3 = 0x0051000A;
+	rLCDCON4 = 0x00000001;
+	if (gd->vfd_type && vfd_inv_data)
+		rLCDCON5 = 0x000004C0;
+	else
+		rLCDCON5 = 0x00000440;
+
+	/* Port pins as LCD output */
+	rPCCON =   (rPCCON & 0xFFFFFF00)| 0x000000AA;
+	rPDCON =   (rPDCON & 0xFFFFFF03)| 0x000000A8;
+
+	/* Synchronize VFD enable with LCD controller to avoid flicker	*/
+	rLCDCON1 = 0x00000B75;			/* Start LCD-Controller	*/
+	while((rLCDCON5 & 0x180000)!=0x100000);	/* Wait for end of VSYNC */
+	while((rLCDCON5 & 0x060000)!=0x040000);	/* Wait for next HSYNC	*/
+	while((rLCDCON5 & 0x060000)==0x040000);
+	while((rLCDCON5 & 0x060000)!=0x000000);
+	if(gd->vfd_type)
+		VFD_ENABLE;

 	debug ("LCDSADDR1: %lX\n", rLCDSADDR1);
 	debug ("LCDSADDR2: %lX\n", rLCDSADDR2);
@@ -475,6 +514,17 @@ int drv_vfd_init(void)
 	return 0;
 }

+/*
+ * Disable VFD: should be run before resetting the system:
+ * disable VM, enable pull-up
+ */
+void disable_vfd (void)
+{
+	VFD_DISABLE;
+	rPDCON &= ~0xC;
+	rPDUP  &= ~0x2;
+}
+
 /************************************************************************/
 /* ** ROM capable initialization part - needed to reserve FB memory	*/
 /************************************************************************/
@@ -489,11 +539,8 @@ ulong vfd_setmem (ulong addr)
 {
 	ulong size;

-	/* MAGIC */
-	frame_buf_size = (256*4*56)/8;
-
 	/* Round up to nearest full page */
-	size = (frame_buf_size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1);
+	size = (FRAME_BUF_SIZE + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1);

 	debug ("Reserving %ldk for VFD Framebuffer at: %08lx\n", size>>10, addr);

--- a/board/v37/flash.c
+++ b/board/v37/flash.c
@@ -23,7 +23,7 @@

 /*
 * Yoo. Jonghoon, IPone, yooth@ipone.co.kr
- * PPCboot port on RPXlite board
+ * U-Boot port on RPXlite board
 *
 * Some of flash control words are modified. (from 2x16bit device
 * to 4x8bit device)
--- a/board/v37/v37.c
+++ b/board/v37/v37.c
@@ -23,7 +23,7 @@

 /*
 * Yoo. Jonghoon, IPone, yooth@ipone.co.kr
- * PPCboot port on RPXlite board
+ * U-Boot port on RPXlite board
 *
 * DRAM related UPMA register values are modified.
 * See RPXLite engineering note : 50MHz/60ns - UPM RAM WORDS
--- a/common/cmd_bootm.c
+++ b/common/cmd_bootm.c
@@ -623,7 +623,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
 	 */
 	(*kernel) (kbd, initrd_start, initrd_end, cmd_start, cmd_end);
 }
-#endif /* CONFIG_ARM */
+#endif /* CONFIG_PPC */

 static void
 do_bootm_netbsd (cmd_tbl_t *cmdtp, int flag,
--- a/common/cmd_fdos.c
+++ b/common/cmd_fdos.c
@@ -53,7 +53,7 @@ int do_fdosboot(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])

    /* pre-set Boot file name */
    if ((name = getenv("bootfile")) == NULL) {
-        name = "pImage";
+        name = "uImage";
    }

    switch (argc) {
--- a/common/cmd_jffs2.c
+++ b/common/cmd_jffs2.c
@@ -83,7 +83,7 @@ jffs2_part_info(int part_num)
 int
 do_jffs2_fsload(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
-	char *filename = "pImage";
+	char *filename = "uImage";
 	ulong offset = CFG_LOAD_ADDR;
 	int size;
 	struct part_info *part;
--- a/common/cmd_pci.c
+++ b/common/cmd_pci.c
@@ -115,28 +115,65 @@ void pciinfo(int BusNum, int ShortPCIListing)

 char* pci_classes_str(u8 class)
 {
-	static char *pci_classes[] = {
-		"Build before PCI Rev2.0",
-		"Mass storage controller",
-		"Network controller     ",
-		"Display controller     ",
-		"Multimedia device      ",
-		"Memory controller      ",
-		"Bridge device          ",
-		"Simple comm. controller",
-		"Base system peripheral ",
-		"Input device           ",
-		"Docking station        ",
-		"Processor              ",
-		"Serial bus controller  ",
-		"Reserved entry         ",
-		"Does not fit any class "
-	};
-
-	if (class < (sizeof pci_classes / sizeof *pci_classes))
-		return pci_classes[(int) class];
-
+	switch (class) {
+        case PCI_CLASS_NOT_DEFINED:
+                return "Build before PCI Rev2.0";
+                break;
+        case PCI_BASE_CLASS_STORAGE:
+                return "Mass storage controller";
+                break;
+        case PCI_BASE_CLASS_NETWORK:
+                return "Network controller     ";
+                break;
+        case PCI_BASE_CLASS_DISPLAY:
+                return "Display controller     ";
+                break;
+        case PCI_BASE_CLASS_MULTIMEDIA:
+                return "Multimedia device      ";
+                break;
+        case PCI_BASE_CLASS_MEMORY:
+                return "Memory controller      ";
+                break;
+        case PCI_BASE_CLASS_BRIDGE:
+                return "Bridge device          ";
+                break;
+        case PCI_BASE_CLASS_COMMUNICATION:
+                return "Simple comm. controller";
+                break;
+        case PCI_BASE_CLASS_SYSTEM:
+                return "Base system peripheral ";
+                break;
+        case PCI_BASE_CLASS_INPUT:
+                return "Input device           ";
+                break;
+        case PCI_BASE_CLASS_DOCKING:
+                return "Docking station        ";
+                break;
+        case PCI_BASE_CLASS_PROCESSOR:
+                return "Processor              ";
+                break;
+        case PCI_BASE_CLASS_SERIAL:
+                return "Serial bus controller  ";
+                break;
+        case PCI_BASE_CLASS_INTELLIGENT:
+                return "Intelligent controller ";
+                break;
+        case PCI_BASE_CLASS_SATELLITE:
+                return "Satellite controller   ";
+                break;
+        case PCI_BASE_CLASS_CRYPT:
+                return "Cryptographic device   ";
+                break;
+        case PCI_BASE_CLASS_SIGNAL_PROCESSING:
+                return "DSP                    ";
+                break;
+        case PCI_CLASS_OTHERS:
+                return "Does not fit any class ";
+                break;
+        default:
 	return  "???                    ";
+                break;
+	};
 }

 /*
--- a/common/console.c
+++ b/common/console.c
@@ -496,7 +496,7 @@ int console_init_r (void)
 	}

 #ifndef CFG_CONSOLE_INFO_QUIET
-	/* Print informations */
+	/* Print information */
 	printf ("In:    ");
 	if (stdio_devices[stdin] == NULL) {
 		printf ("No input devices available!\n");
--- a/common/env_flash.c
+++ b/common/env_flash.c
@@ -34,6 +34,7 @@
 #include <environment.h>
 #include <cmd_nvedit.h>
 #include <linux/stddef.h>
+#include <malloc.h>

 #if ((CONFIG_COMMANDS&(CFG_CMD_ENV|CFG_CMD_FLASH)) == (CFG_CMD_ENV|CFG_CMD_FLASH))
 #define CMD_SAVEENV
@@ -41,11 +42,6 @@
 #error Cannot use CFG_ENV_ADDR_REDUND without CFG_CMD_ENV & CFG_CMD_FLASH
 #endif

-#if defined(CFG_ENV_SECT_SIZE) && (CFG_ENV_SECT_SIZE > CFG_ENV_SIZE) && \
-    defined(CFG_ENV_ADDR_REDUND)
-#error CFG_ENV_ADDR_REDUND should not be used when CFG_ENV_SECT_SIZE > CFG_ENV_SIZE
-#endif
-
 #if defined(CFG_ENV_SIZE_REDUND) && (CFG_ENV_SIZE_REDUND < CFG_ENV_SIZE)
 #error CFG_ENV_SIZE_REDUND should not be less then CFG_ENV_SIZE
 #endif
@@ -80,8 +76,9 @@ static env_t *flash_addr = (env_t *)CFG_ENV_ADDR;
 #ifdef CFG_ENV_ADDR_REDUND
 static env_t *flash_addr_new = (env_t *)CFG_ENV_ADDR_REDUND;

-static ulong end_addr = CFG_ENV_ADDR + CFG_ENV_SIZE - 1;
-static ulong end_addr_new = CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1;
+/* CFG_ENV_ADDR is supposed to be on sector boundary */
+static ulong end_addr = CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1;
+static ulong end_addr_new = CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1;

 static uchar active_flag = 1;
 static uchar obsolete_flag = 0;
@@ -163,7 +160,11 @@ int  env_init(void)
 #ifdef CMD_SAVEENV
 int saveenv(void)
 {
+	char *saved_data = NULL;
 	int rc = 1;
+#if CFG_ENV_SECT_SIZE > CFG_ENV_SIZE
+	ulong up_data = 0;
+#endif

 	debug ("Protect off %08lX ... %08lX\n",
 		(ulong)flash_addr, end_addr);
@@ -179,6 +180,22 @@ int saveenv(void)
 		goto Done;
 	}

+#if CFG_ENV_SECT_SIZE > CFG_ENV_SIZE
+	up_data = (end_addr_new + 1 - ((long)flash_addr_new + CFG_ENV_SIZE));
+	debug ("Data to save 0x%x\n", up_data);
+	if (up_data) {
+		if ((saved_data = malloc(up_data)) == NULL) {
+			printf("Unable to save the rest of sector (%ld)\n", 
+				up_data);
+			goto Done;
+		}
+		memcpy(saved_data, 
+			(void *)((long)flash_addr_new + CFG_ENV_SIZE), up_data);
+		debug ("Data (start 0x%x, len 0x%x) saved at 0x%x\n", 
+			   (long)flash_addr_new + CFG_ENV_SIZE, 
+				up_data, saved_data);
+	}
+#endif
 	puts ("Erasing Flash...");
 	debug (" %08lX ... %08lX ...",
 		(ulong)flash_addr_new, end_addr_new);
@@ -212,6 +229,18 @@ int saveenv(void)
 	}
 	puts ("done\n");

+#if CFG_ENV_SECT_SIZE > CFG_ENV_SIZE
+	if (up_data) { /* restore the rest of sector */
+		debug ("Restoring the rest of data to 0x%x len 0x%x\n",
+			   (long)flash_addr_new + CFG_ENV_SIZE, up_data);
+		if (flash_write(saved_data, 
+				(long)flash_addr_new + CFG_ENV_SIZE, 
+				up_data)) {
+			flash_perror(rc);
+			goto Done;
+		}
+	}
+#endif
 	{
 		env_t * etmp = flash_addr;
 		ulong ltmp = end_addr;
@@ -226,6 +255,8 @@ int saveenv(void)
 	rc = 0;
 Done:

+	if (saved_data)
+		free (saved_data);
 	/* try to re-protect */
 	(void) flash_sect_protect (1, (ulong)flash_addr, end_addr);
 	(void) flash_sect_protect (1, (ulong)flash_addr_new, end_addr_new);
--- a/common/main.c
+++ b/common/main.c
@@ -640,8 +640,6 @@ static void process_macros (const char *input, char *output)
 	    case 0:			/* Waiting for (unescaped) $	*/
 		if ((c == '\'') && (prev != '\\')) {
 			state = 3;
-			if (inputcnt)
-				inputcnt--;
 			break;
 		}
 		if ((c == '$') && (prev != '\\')) {
@@ -694,8 +692,6 @@ static void process_macros (const char *input, char *output)
 	    case 3:			/* Waiting for '	*/
 		if ((c == '\'') && (prev != '\\')) {
 			state = 0;
-			if (inputcnt)
-				inputcnt--;
 		} else {
 			*(output++) = c;
 			outputcnt--;
--- a/cpu/arm920t/interrupts.c
+++ b/cpu/arm920t/interrupts.c
@@ -199,9 +199,9 @@ int interrupt_init (void)
 	/* load value for 10 ms timeout */
 	lastdec = rTCNTB4 = timer_load_val;
 	/* auto load, manual update of Timer 4 */
-	rTCON = 0x600000;
+	rTCON = (rTCON & ~0x0700000) | 0x600000;
 	/* auto load, start Timer 4 */
-	rTCON = 0x500000;
+	rTCON = (rTCON & ~0x0700000) | 0x500000;
 	timestamp = 0;

 	return (0);
@@ -296,8 +296,10 @@ ulong get_tbclk (void)

 #if defined(CONFIG_SMDK2400) || defined(CONFIG_TRAB)
 	tbclk = timer_load_val * 100;
-#elif defined(CONFIG_SMDK2410)
+#elif defined(CONFIG_SMDK2410) || defined(CONFIG_VCMA9)
 	tbclk = CFG_HZ;
+#else
+#	error "tbclk not configured"
 #endif

 	return tbclk;
--- a/cpu/arm920t/start.S
+++ b/cpu/arm920t/start.S
@@ -446,6 +446,9 @@ fiq:
 reset_cpu:
 #ifdef CONFIG_S3C2400
 	bl	disable_interrupts
+# ifdef CONFIG_TRAB
+	bl	disable_vfd
+# endif
 	ldr	r1, _rWTCON
 	ldr	r2, _rWTCNT
 	/* Disable watchdog */
--- a/cpu/mpc824x/drivers/i2c/i2c1.c
+++ b/cpu/mpc824x/drivers/i2c/i2c1.c
@@ -1128,6 +1128,15 @@ static void I2C_Set_Stat (unsigned int eumbbar, I2C_STAT stat)

 void i2c_init (int speed, int slaveadd)
 {
+#ifdef CFG_I2C_INIT_BOARD
+	/*
+	 * call board specific i2c bus reset routine before accessing the
+	 * environment, which might be in a chip on that bus. For details
+	 * about this problem see doc/I2C_Edge_Conditions.
+	 */
+	i2c_init_board();
+#endif
+
 #ifdef DEBUG
 	I2C_Initialize (0x7f, 0, (void *) printf);
 #else
--- a/cpu/mpc8260/i2c.c
+++ b/cpu/mpc8260/i2c.c
@@ -221,6 +221,13 @@ void i2c_init(int speed, int slaveadd)
 	volatile I2C_BD *rxbd, *txbd;
 	uint dpaddr;

+#ifdef CFG_I2C_INIT_BOARD        
+	/* call board specific i2c bus reset routine before accessing the   */
+	/* environment, which might be in a chip on that bus. For details   */
+	/* about this problem see doc/I2C_Edge_Conditions.                  */
+	i2c_init_board();
+#endif
+
 	dpaddr = *((unsigned short*)(&immap->im_dprambase[PROFF_I2C_BASE]));
 	if (dpaddr == 0) {
 	    /* need to allocate dual port ram */
--- a/cpu/mpc8xx/cpu_init.c
+++ b/cpu/mpc8xx/cpu_init.c
@@ -42,8 +42,8 @@ void cpu_init_f (volatile immap_t * immr)
 {
 #ifndef CONFIG_MBX
 	volatile memctl8xx_t *memctl = &immr->im_memctl;
-	ulong reg;
 #endif
+	ulong reg;

 	/* SYPCR - contains watchdog control (11-9) */

@@ -68,6 +68,14 @@ void cpu_init_f (volatile immap_t * immr)
 	immr->im_sitk.sitk_piscrk = KAPWR_KEY;
 	immr->im_sit.sit_piscr = CFG_PISCR;

+	/* System integration timers. Don't change EBDF! (15-27) */
+
+	immr->im_clkrstk.cark_sccrk = KAPWR_KEY;
+	reg = immr->im_clkrst.car_sccr;
+	reg &= SCCR_MASK;
+	reg |= CFG_SCCR;
+	immr->im_clkrst.car_sccr = reg;
+
 	/* PLL (CPU clock) settings (15-30) */

 	immr->im_clkrstk.cark_plprcrk = KAPWR_KEY;
@@ -88,14 +96,6 @@ void cpu_init_f (volatile immap_t * immr)
 #endif
 	immr->im_clkrst.car_plprcr = reg;

-	/* System integration timers. Don't change EBDF! (15-27) */
-
-	immr->im_clkrstk.cark_sccrk = KAPWR_KEY;
-	reg = immr->im_clkrst.car_sccr;
-	reg &= SCCR_MASK;
-	reg |= CFG_SCCR;
-	immr->im_clkrst.car_sccr = reg;
-
 	/*
 	 * Memory Controller:
 	 */
--- a/cpu/mpc8xx/i2c.c
+++ b/cpu/mpc8xx/i2c.c
@@ -215,6 +215,13 @@ i2c_init(int speed, int slaveaddr)
 	volatile I2C_BD *rxbd, *txbd;
 	uint dpaddr;

+#ifdef CFG_I2C_INIT_BOARD        
+	/* call board specific i2c bus reset routine before accessing the   */
+	/* environment, which might be in a chip on that bus. For details   */
+	/* about this problem see doc/I2C_Edge_Conditions.                  */
+	i2c_init_board();
+#endif
+
 #ifdef CFG_I2C_UCODE_PATCH
 	iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase];
 #else
--- a/cpu/ppc4xx/i2c.c
+++ b/cpu/ppc4xx/i2c.c
@@ -85,7 +85,15 @@ void i2c_init (int speed, int slaveadd)
 	unsigned long freqOPB;
 	int val, divisor;

+#ifdef CFG_I2C_INIT_BOARD        
+	/* call board specific i2c bus reset routine before accessing the   */
+	/* environment, which might be in a chip on that bus. For details   */
+	/* about this problem see doc/I2C_Edge_Conditions.                  */
+	i2c_init_board();
+#endif
+
 	/* Handle possible failed I2C state */
+	/* FIXME: put this into i2c_init_board()? */
 	_i2c_bus_reset ();

 	/* clear lo master address */
@@ -414,4 +422,23 @@ int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len)
        return (i2c_transfer( 0, chip<<1, &xaddr[4-alen], alen, buffer, len ) != 0);
 }

+/*-----------------------------------------------------------------------
+ * Read a register
+ */
+uchar i2c_reg_read(uchar i2c_addr, uchar reg)
+{
+	char buf;
+
+	i2c_read(i2c_addr, reg, 1, &buf, 1);
+
+	return(buf);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a register
+ */
+void i2c_reg_write(uchar i2c_addr, uchar reg, uchar val)
+{
+	i2c_write(i2c_addr, reg, 1, &val, 1);
+}
 #endif	/* CONFIG_HARD_I2C */
--- a/cpu/xscale/i2c.c
+++ b/cpu/xscale/i2c.c
@@ -41,6 +41,7 @@
 *	- I2C_PXA_SLAVE_ADDR 
 */

+#include <asm/arch/hardware.h>
 #include <asm/arch/pxa-regs.h>
 #include <i2c.h>

@@ -244,6 +245,12 @@ i2c_transfer_finish:

 void i2c_init(int speed, int slaveaddr)
 {
+#ifdef CFG_I2C_INIT_BOARD        
+	/* call board specific i2c bus reset routine before accessing the   */
+	/* environment, which might be in a chip on that bus. For details   */
+	/* about this problem see doc/I2C_Edge_Conditions.                  */
+	i2c_init_board();
+#endif
 }


--- a/cpu/xscale/start.S
+++ b/cpu/xscale/start.S
@@ -4,8 +4,10 @@
 *  Copyright (C) 1998	Dan Malek <dmalek@jlc.net>
 *  Copyright (C) 1999	Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
 *  Copyright (C) 2000	Wolfgang Denk <wd@denx.de>
- *  Copyright (c) 2001	Alex Züpke <azu@sysgo.de>
- *  Copyright (c) 2002	Kyle Harris <kharris@nexus-tech.net>
+ *  Copyright (C) 2001	Alex Züpke <azu@sysgo.de>
+ *  Copyright (C) 2002	Kyle Harris <kharris@nexus-tech.net>
+ *  Copyright (C) 2003  Robert Schwebel <r.schwebel@pengutronix.de>
+ *  Copyright (C) 2003  Kai-Uwe Bloehm <kai-uwe.bloem@auerswald.de>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
@@ -26,8 +28,6 @@
 * MA 02111-1307 USA
 */

-
-
 #include <config.h>
 #include <version.h>

@@ -83,6 +83,17 @@ _armboot_end_data:
 _armboot_end:
 	.word armboot_end

+/*
+ * This is defined in the board specific linker script
+ */
+.globl _bss_start	
+_bss_start:	
+	.word bss_start
+
+.globl _bss_end
+_bss_end:
+	.word bss_end
+
 /*
 * _armboot_real_end is the first usable RAM address behind armboot
 * and the various stacks
@@ -125,13 +136,16 @@ reset:

 	bl	cpu_init_crit		/* we do sys-critical inits	    */

-relocate:				/* relocate U-Boot to RAM	   */
-	adr	r0, _start		/* r0 <- current position of code */
+relocate:				/* relocate U-Boot to RAM	    */
+	adr	r0, _start		/* r0 <- current position of code   */
+	ldr	r1, _TEXT_BASE		/* test if we run from flash or RAM */	
+	cmp     r0, r1                  /* don't reloc during debug         */
+	beq     stack_setup
+
 	ldr	r2, _armboot_start
 	ldr	r3, _armboot_end
-	sub	r2, r3, r2		/* r2 <- size of armboot */
-	ldr	r1, _TEXT_BASE
-	add	r2, r0, r2		/* r2 <- source end address */
+	sub	r2, r3, r2		/* r2 <- size of armboot            */
+	add	r2, r0, r2		/* r2 <- source end address         */

 copy_loop:
 	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
@@ -140,10 +154,26 @@ copy_loop:
 	ble	copy_loop

 	/* Set up the stack						    */
+
+stack_setup:
+
 	ldr	r0, _uboot_reloc	/* upper 128 KiB: relocated uboot   */
 	sub	r0, r0, #CFG_MALLOC_LEN /* malloc area			    */
 					/* FIXME: bdinfo should be here	    */
-	sub	sp, r0, #12		/* leave 3 words for abort-stack */
+	sub	sp, r0, #12		/* leave 3 words for abort-stack    */
+
+clear_bss:
+
+	ldr	r0, _bss_start		/* find start of bss segment        */
+	add	r0, r0, #4		/* start at first byte of bss       */
+	ldr	r1, _bss_end		/* stop here                        */
+	mov 	r2, #0x00000000		/* clear                            */
+
+clbss_l:str	r2, [r0]		/* clear loop...                    */
+	add	r0, r0, #4
+	cmp	r0, r1
+	bne	clbss_l	 
+

 	ldr	pc, _start_armboot

@@ -159,7 +189,7 @@ _start_armboot: .word start_armboot
 /*									    */
 /****************************************************************************/

-	/* Interrupt-Controller base address				    */
+/* Interrupt-Controller base address				            */
 IC_BASE:	   .word	   0x40d00000
 #define ICMR	0x04

@@ -167,19 +197,19 @@ IC_BASE:	   .word	   0x40d00000
 RST_BASE:	.word	0x40f00030
 #define RCSR	0x00

-	/* Operating System Timer */
+/* Operating System Timer */
 OSTIMER_BASE:	.word	0x40a00000
 #define OSMR3	0x0C
 #define OSCR	0x10
 #define OWER	0x18
 #define OIER	0x1C

-	/* Clock Manager Registers					    */
-#ifdef CFG_CPUSPEED
+/* Clock Manager Registers					            */
 CC_BASE:	.word	0x41300000
 #define CCCR	0x00
 cpuspeed:	.word	CFG_CPUSPEED
-#endif
+
+
 	/* RS: ???							    */
 	.macro CPWAIT
 	mrc  p15,0,r0,c2,c0,0
@@ -195,13 +225,16 @@ cpu_init_crit:
 	mov	r1, #0x00
 	str	r1, [r0, #ICMR]

-#ifdef CFG_CPUSPEED
+#if defined(CFG_CPUSPEED)
+
 	/* set clock speed */
 	ldr	r0, CC_BASE
 	ldr	r1, cpuspeed
 	str	r1, [r0, #CCCR]
-	mov	r0, #3
+	mov	r0, #2
 	mcr	p14, 0, r0, c6, c0, 0
+
+setspeed_done:
 #endif

 	/*
@@ -405,15 +438,21 @@ fiq:

 #endif

-/************************************************************************/
-/*									*/
-/* Reset function: the PXA250 has no reset function, so we have to	*/
-/* perform a watchdog timeout to cause a reset.				*/
-/*									*/
-/************************************************************************/
+/****************************************************************************/
+/*                                                                          */
+/* Reset function: the PXA250 doesn't have a reset function, so we have to  */
+/* perform a watchdog timeout for a soft reset.                             */
+/*                                                                          */
+/****************************************************************************/
+
 	.align	5
 .globl reset_cpu
+
+	/* FIXME: this code is PXA250 specific. How is this handled on      */
+	/*        other XScale processors?                                  */
+
 reset_cpu:
+
 	/* We set OWE:WME (watchdog enable) and wait until timeout happens  */

 	ldr	r0, OSTIMER_BASE
@@ -432,3 +471,4 @@ reset_cpu:
 reset_endless:

 	b	reset_endless
+
--- a/doc/README-i386
+++ b/doc/README-i386
@@ -1,4 +1,4 @@
-This is my attempt to port PPCBoot to the i386 platform. This
+This is my attempt to port U-Boot to the i386 platform. This
 work was sponsored by my emplyer, Omicron Ceti AB. http://www.omicron.se

 It is currently capable of booting a linux bzImage from flash on
@@ -28,13 +28,13 @@ To use this code on the CDP:


 2) Program it in to the CDP flashbank with remon
-   ppcboot.bin should be programmed att offset 0x7e000 and the kernel at
+   u-boot.bin should be programmed att offset 0x7e000 and the kernel at
   offset 0. If you want to use a jffs2 root file system (not included here), 
   it should be  programmed to offset 0x100000.
   
   remon> z
   remon> yi
-   remon> ns ppcboot.bin 7e0000
+   remon> ns u-boot.bin 7e0000
   remon> ns bzImage 0
   remon> ns image.jffs2 100000

@@ -43,7 +43,7 @@ To use this code on the CDP:
   remon> z
   remon> g

-4) PPCboot should output some message and a prompt on the terminal, to
+4) U-Boot should output some message and a prompt on the terminal, to
   start the kernel issue the following command:
   
   BOOT> bootm
--- a/doc/README.IPHASE4539
+++ b/doc/README.IPHASE4539
@@ -332,10 +332,10 @@ Linux:
 	$ make IPHASE4539_config
 	$ make oldconfig
 	$ make dep
-	$ make pImage
-	$ cp -p arch/ppc/mbxboot/pImage /tftpboot
+	$ make uImage
+	$ cp -p arch/ppc/mbxboot/uImage /tftpboot

-	Load pImage via tftp and boot it.
+	Load uImage via tftp and boot it.


 Flash organisation:
--- a/doc/README.JFFS2
+++ b/doc/README.JFFS2
@@ -9,6 +9,14 @@ fsload  - load binary file from a file system image
 fsinfo  - print information about file systems
 ls      - list files in a directory

+If you boot from a partition which is mounted writable, and you
+update your boot environment by replacing single files on that
+partition, you should also define CFG_JFFS2_SORT_FRAGMENTS. Scanning
+the JFFS2 filesystem takes *much* longer with this feature, though.
+Sorting is done while inserting into the fragment list, which is
+more or less a bubble sort. That algorithm is known to be O(n^2),
+thus you should really consider if you can avoid it!
+

 There is two ways for JFFS2 to find the disk. The default way uses
 the flash_info structure to find the start of a JFFS2 disk (called
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -32,7 +32,7 @@ OBJS	= 3c589.o 5701rls.o bcm570x.o bcm570x_autoneg.o \
 	  eepro100.o i8042.o inca-ip_sw.o \
 	  natsemi.o ns16550.o ns8382x.o ns87308.o \
 	  pci.o pci_auto.o pci_indirect.o \
-	  pcnet.o sed13806.o serial.o \
+	  pcnet.o s3c24x0_i2c.o sed13806.o serial.o \
 	  smc91111.o smiLynxEM.o sym53c8xx.o \
 	  tigon3.o w83c553f.o

--- a/drivers/cs8900.c
+++ b/drivers/cs8900.c
@@ -272,6 +272,44 @@ retry:
 	return 0;
 }

+static void cs8900_e2prom_ready(void)
+{
+	while(get_reg(PP_SelfST) & SI_BUSY);
+}
+
+/***********************************************************/
+/* read a 16-bit word out of the EEPROM                    */
+/***********************************************************/
+
+int cs8900_e2prom_read(unsigned char addr, unsigned short *value)
+{
+	cs8900_e2prom_ready();
+	put_reg(PP_EECMD, EEPROM_READ_CMD | addr);
+	cs8900_e2prom_ready();
+	*value = get_reg(PP_EEData);
+
+	return 0;
+}
+
+
+/***********************************************************/
+/* write a 16-bit word into the EEPROM                     */
+/***********************************************************/
+
+int cs8900_e2prom_write(unsigned char addr, unsigned short value)
+{
+	cs8900_e2prom_ready();
+	put_reg(PP_EECMD, EEPROM_WRITE_EN);
+	cs8900_e2prom_ready();
+	put_reg(PP_EEData, value);
+	put_reg(PP_EECMD, EEPROM_WRITE_CMD | addr);
+	cs8900_e2prom_ready();
+	put_reg(PP_EECMD, EEPROM_WRITE_DIS);
+	cs8900_e2prom_ready();
+
+	return 0;
+}
+
 #endif	/* COMMANDS & CFG_NET */

 #endif	/* CONFIG_DRIVER_CS8900 */
--- a/drivers/cs8900.h
+++ b/drivers/cs8900.h
@@ -250,7 +250,9 @@
 #define EEPROM_WRITE_DIS	0x0000
 #define EEPROM_WRITE_CMD	0x0100
 #define EEPROM_READ_CMD		0x0200
+#define EEPROM_ERASE_CMD	0x0300

-
+extern int cs8900_e2prom_read(uchar, ushort *);
+extern int cs8900_e2prom_write(uchar, ushort);

 #endif /* CONFIG_DRIVER_CS8900 */
--- a/drivers/inca-ip_sw.c
+++ b/drivers/inca-ip_sw.c
--- a/drivers/pci_auto.c
+++ b/drivers/pci_auto.c
@@ -314,6 +314,16 @@ int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
 		pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_io);
 		break;

+	case PCI_CLASS_BRIDGE_CARDBUS:
+		/* just do a minimal setup of the bridge, let the OS take care of the rest */
+		pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_io);
+
+		DEBUGF("PCI Autoconfig: Found P2CardBus bridge, device %d\n",
+			PCI_DEV(dev));
+
+		hose->current_busno++;
+		break;
+
 	default:
 		pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_io);
 		break;
--- a/drivers/s3c24x0_i2c.c
+++ b/drivers/s3c24x0_i2c.c
@@ -0,0 +1,411 @@
+/*
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* This code should work for both the S3C2400 and the S3C2410
+ * as they seem to have the same I2C controller inside.
+ * The different address mapping is handled by the s3c24xx.h files below.
+ */
+
+#include <common.h>
+
+#ifdef CONFIG_DRIVER_S3C24X0_I2C
+
+#if defined(CONFIG_S3C2400)
+#include <s3c2400.h>
+#elif defined(CONFIG_S3C2410)
+#include <s3c2410.h>
+#endif
+#include <i2c.h>
+
+#ifdef CONFIG_HARD_I2C
+
+#define	IIC_WRITE	0
+#define IIC_READ	1
+
+#define IIC_OK		0
+#define IIC_NOK		1
+#define IIC_NACK	2
+#define IIC_NOK_LA	3		/* Lost arbitration */
+#define IIC_NOK_TOUT	4		/* time out */
+
+#define IICSTAT_BSY	0x20		/* Busy bit */
+#define IICSTAT_NACK	0x01		/* Nack bit */
+#define IICCON_IRPND	0x10		/* Interrupt pending bit */
+#define IIC_MODE_MT	0xC0		/* Master Transmit Mode */
+#define IIC_MODE_MR	0x80		/* Master Receive Mode */
+#define IIC_START_STOP	0x20		/* START / STOP */
+#define IIC_TXRX_ENA	0x10		/* I2C Tx/Rx enable */
+
+#define IIC_TIMEOUT 1			/* 1 seconde */
+
+
+static int GetIICSDA(void)
+{
+	return (rGPEDAT & 0x8000) >> 15;
+}
+
+#if 0
+static void SetIICSDA(int x)
+{
+	rGPEDAT = (rGPEDAT & ~0x8000) | (x&1) << 15;
+}
+#endif
+
+static void SetIICSCL(int x)
+{
+	rGPEDAT = (rGPEDAT & ~0x4000) | (x&1) << 14;
+}
+
+
+static int WaitForXfer(void)
+{
+    int i, status;
+
+    i = IIC_TIMEOUT * 1000;
+    status = rIICCON;
+    while ((i > 0) && !(status & IICCON_IRPND)) {
+    	udelay(1000);
+	status = rIICCON;
+	i--;
+    }
+
+    return(status & IICCON_IRPND) ? IIC_OK : IIC_NOK_TOUT;
+}
+
+static int IsACK(void)
+{
+    return(!(rIICSTAT & IICSTAT_NACK));
+}
+
+static void ReadWriteByte(void)
+{
+    rIICCON &= ~IICCON_IRPND;
+}
+
+void i2c_init (int speed, int slaveadd)
+{
+    ulong freq, pres = 16, div;
+    int i, status;
+
+    /* wait for some time to give previous transfer a chance to finish */
+
+    i = IIC_TIMEOUT * 1000;
+    status = rIICSTAT;
+    while ((i > 0) && (status & IICSTAT_BSY)) {
+	udelay(1000);
+	status = rIICSTAT;
+	i--;
+    }
+
+    if ((status & IICSTAT_BSY) || GetIICSDA() == 0) {
+	ulong old_gpecon = rGPECON;
+	/* bus still busy probably by (most) previously interrupted transfer */
+
+	/* set IICSDA and IICSCL (GPE15, GPE14) to GPIO */
+	rGPECON = (rGPECON & ~0xF0000000) | 0x10000000;
+
+	/* toggle IICSCL until bus idle */
+	SetIICSCL(0); udelay(1000);
+	i = 10;
+	while ((i > 0) && (GetIICSDA() != 1)) {
+		SetIICSCL(1); udelay(1000);
+		SetIICSCL(0); udelay(1000);
+		i--;
+	}
+	SetIICSCL(1); udelay(1000);
+
+	/* restore pin functions */
+	rGPECON = old_gpecon;
+    }
+
+    /* calculate prescaler and divisor values */
+    freq = get_PCLK();
+    if ((freq / pres / (16+1)) > speed)
+	/* set prescaler to 512 */
+	pres = 512;
+
+    div = 0;
+    while ((freq / pres / (div+1)) > speed)
+	div++;
+
+    /* set prescaler, divisor according to freq, also set
+       ACKGEN, IRQ */
+    rIICCON = (div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0);
+
+    /* init to SLAVE REVEIVE and set slaveaddr */
+    rIICSTAT = 0;
+    rIICADD = slaveadd;
+    /* program Master Transmit (and implicit STOP) */
+    rIICSTAT = IIC_MODE_MT | IIC_TXRX_ENA;
+
+}
+
+/*
+  cmd_type is 0 for write 1 for read.
+
+  addr_len can take any value from 0-255, it is only limited
+  by the char, we could make it larger if needed. If it is
+  0 we skip the address write cycle.
+
+*/
+static
+int i2c_transfer(unsigned char cmd_type,
+                 unsigned char chip,
+                 unsigned char addr[],
+                 unsigned char addr_len,
+                 unsigned char data[],
+		 unsigned short data_len)
+{
+    int i, status, result;
+
+    if (data == 0 || data_len == 0) {
+	/*Don't support data transfer of no length or to address 0*/
+	printf( "i2c_transfer: bad call\n" );
+	return IIC_NOK;
+    }
+
+    //CheckDelay();
+
+    /* Check I2C bus idle */
+    i = IIC_TIMEOUT * 1000;
+    status = rIICSTAT;
+    while ((i > 0) && (status & IICSTAT_BSY)) {
+	udelay(1000);
+	status = rIICSTAT;
+	i--;
+    }
+
+
+    if (status & IICSTAT_BSY) {
+	result = IIC_NOK_TOUT;
+        return(result);
+    }
+
+    rIICCON |= 0x80;
+
+    result = IIC_OK;
+
+    switch (cmd_type) {
+	case IIC_WRITE:
+	    if (addr && addr_len) {
+		rIICDS = chip;
+		/* send START */
+		rIICSTAT = IIC_MODE_MT | IIC_TXRX_ENA | IIC_START_STOP;
+		i = 0;
+		while ((i < addr_len) && (result == IIC_OK)) {
+		    result = WaitForXfer();
+		    rIICDS = addr[i];
+		    ReadWriteByte();
+		    i++;
+		}
+		i = 0;
+		while ((i < data_len) && (result == IIC_OK)) {
+		    result = WaitForXfer();
+		    rIICDS = data[i];
+		    ReadWriteByte();
+		    i++;
+		}
+	    } else {
+		rIICDS = chip;
+		/* send START */
+		rIICSTAT = IIC_MODE_MT | IIC_TXRX_ENA | IIC_START_STOP;
+		i = 0;
+		while ((i < data_len) && (result = IIC_OK)) {
+		    result = WaitForXfer();
+		    rIICDS = data[i];
+		    ReadWriteByte();
+		    i++;
+		}
+	    }
+
+	    if (result == IIC_OK)
+	        result = WaitForXfer();
+
+	    /* send STOP */
+	    rIICSTAT = IIC_MODE_MR | IIC_TXRX_ENA;
+	    ReadWriteByte();
+	    break;
+
+	case IIC_READ:
+	    if (addr && addr_len) {
+		rIICSTAT = IIC_MODE_MT | IIC_TXRX_ENA;
+		rIICDS = chip;
+		/* send START */
+		rIICSTAT |= IIC_START_STOP;
+		result = WaitForXfer();
+		if (IsACK()) {
+		    i = 0;
+		    while ((i < addr_len) && (result == IIC_OK)) {
+			rIICDS = addr[i];
+			ReadWriteByte();
+			result = WaitForXfer();
+			i++;
+		    }
+
+		    rIICDS = chip;
+		    /* resend START */
+		    rIICSTAT = IIC_MODE_MR | IIC_TXRX_ENA | IIC_START_STOP;
+		    ReadWriteByte();
+		    result = WaitForXfer();
+		    i = 0;
+		    while ((i < data_len) && (result == IIC_OK)) {
+			/* disable ACK for final READ */
+			if (i == data_len - 1)
+			    rIICCON &= ~0x80;
+			ReadWriteByte();
+			result = WaitForXfer();
+			data[i] = rIICDS;
+			i++;
+		    }
+		} else {
+		    result = IIC_NACK;
+		}
+
+	    } else {
+		rIICSTAT = IIC_MODE_MR | IIC_TXRX_ENA;
+		rIICDS = chip;
+		/* send START */
+		rIICSTAT |= IIC_START_STOP;
+		result = WaitForXfer();
+
+		if (IsACK()) {
+		    i = 0;
+		    while ((i < data_len) && (result == IIC_OK)) {
+			/* disable ACK for final READ */
+			if (i == data_len - 1)
+			    rIICCON &= ~0x80;
+		        ReadWriteByte();
+			result = WaitForXfer();
+			data[i] = rIICDS;
+			i++;
+		    }
+		} else {
+		    result = IIC_NACK;
+		}
+	    }
+
+	    /* send STOP */
+	    rIICSTAT = IIC_MODE_MR | IIC_TXRX_ENA;
+	    ReadWriteByte();
+	    break;
+
+	default:
+	    printf( "i2c_transfer: bad call\n" );
+    	    result = IIC_NOK;
+	    break;
+    }
+
+    return (result);
+}
+
+int i2c_probe (uchar chip)
+{
+    uchar buf[1];
+
+    buf[0] = 0;
+
+    /*
+     * What is needed is to send the chip address and verify that the
+     * address was <ACK>ed (i.e. there was a chip at that address which
+     * drove the data line low).
+     */
+    return(i2c_transfer (IIC_READ, chip << 1, 0, 0, buf, 1) != IIC_OK);
+}
+
+int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len)
+{
+    uchar xaddr[4];
+    int ret;
+
+    if ( alen > 4 ) {
+	printf ("I2C read: addr len %d not supported\n", alen);
+	return 1;
+    }
+
+    if ( alen > 0 ) {
+	xaddr[0] = (addr >> 24) & 0xFF;
+        xaddr[1] = (addr >> 16) & 0xFF;
+        xaddr[2] = (addr >> 8) & 0xFF;
+        xaddr[3] = addr & 0xFF;
+    }
+
+
+#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
+    /*
+     * EEPROM chips that implement "address overflow" are ones
+     * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
+     * address and the extra bits end up in the "chip address"
+     * bit slots. This makes a 24WC08 (1Kbyte) chip look like
+     * four 256 byte chips.
+     *
+     * Note that we consider the length of the address field to
+     * still be one byte because the extra address bits are
+     * hidden in the chip address.
+     */
+    if( alen > 0 )
+	chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
+#endif
+    if( (ret = i2c_transfer(IIC_READ, chip<<1, &xaddr[4-alen], alen, buffer, len )) != 0) {
+        printf( "I2c read: failed %d\n", ret);
+        return 1;
+    }
+    return 0;
+}
+
+int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len)
+{
+    uchar xaddr[4];
+
+    if ( alen > 4 ) {
+	printf ("I2C write: addr len %d not supported\n", alen);
+	return 1;
+    }
+
+    if ( alen > 0 ) {
+        xaddr[0] = (addr >> 24) & 0xFF;
+        xaddr[1] = (addr >> 16) & 0xFF;
+        xaddr[2] = (addr >> 8) & 0xFF;
+        xaddr[3] = addr & 0xFF;
+    }
+
+#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
+    /*
+     * EEPROM chips that implement "address overflow" are ones
+     * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
+     * address and the extra bits end up in the "chip address"
+     * bit slots. This makes a 24WC08 (1Kbyte) chip look like
+     * four 256 byte chips.
+     *
+     * Note that we consider the length of the address field to
+     * still be one byte because the extra address bits are
+     * hidden in the chip address.
+     */
+    if( alen > 0 )
+        chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
+#endif
+    return (i2c_transfer(IIC_WRITE, chip<<1, &xaddr[4-alen], alen, buffer, len ) != 0);
+}
+
+#endif	/* CONFIG_HARD_I2C */
+
+#endif /* CONFIG_DRIVER_S3C24X0_I2C */
--- a/fs/fdos/dev.c
+++ b/fs/fdos/dev.c
@@ -149,7 +149,7 @@ int check_dev (BootSector_t *boot, Fs_t *fs)
            __le16_to_cpu (boot -> TimeF));
    

-    /* informations are extracted from boot sector                           */
+    /* information is extracted from boot sector                           */
    heads = __le16_to_cpu (boot -> nheads);
    sectors = __le16_to_cpu (boot -> nsect);
    fs -> tot_sectors = __le32_to_cpu (boot -> bigsect);
--- a/fs/jffs2/jffs2_1pass.c
+++ b/fs/jffs2/jffs2_1pass.c
@@ -1,3 +1,4 @@
+/* vi: set sw=4 ts=4: */
 /*
 -------------------------------------------------------------------------
 * Filename:      jffs2.c
@@ -75,6 +76,42 @@
 *
 */

+/*
+ * Bugfixing by Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de>, (C) Mar/2003
+ *
+ * - overhaul of the memory management. Removed much of the "paper-bagging"
+ *   in that part of the code, fixed several bugs, now frees memory when
+ *   partition is changed.
+ *   It's still ugly :-(
+ * - fixed a bug in jffs2_1pass_read_inode where the file length calculation
+ *   was incorrect. Removed a bit of the paper-bagging as well.
+ * - removed double crc calculation for fragment headers in jffs2_private.h
+ *   for speedup.
+ * - scan_empty rewritten in a more "standard" manner (non-paperbag, that is).
+ * - spinning wheel now spins depending on how much memory has been scanned
+ * - lots of small changes all over the place to "improve" readability.
+ * - implemented fragment sorting to ensure that the newest data is copied
+ *   if there are multiple copies of fragments for a certain file offset.
+ *
+ * The fragment sorting feature must be enabled by CFG_JFFS2_SORT_FRAGMENTS.
+ * Sorting is done while adding fragments to the lists, which is more or less a
+ * bubble sort. This takes a lot of time, and is most probably not an issue if
+ * the boot filesystem is always mounted readonly.
+ *
+ * You should define it if the boot filesystem is mounted writable, and updates
+ * to the boot files are done by copying files to that filesystem.
+ *
+ *
+ * There's a big issue left: endianess is completely ignored in this code. Duh!
+ *
+ *
+ * You still should have paper bags at hand :-(. The code lacks more or less
+ * any comment, and is still arcane and difficult to read in places. As this
+ * is incompatible with any new code from the jffs2 maintainers anyway, it
+ * should probably be dumped and replaced by something like jffs2reader!
+ */
+
+
 #include <common.h>
 #include <config.h>
 #include <malloc.h>
@@ -88,124 +125,197 @@

 #include "jffs2_private.h"

-/* Compression names */
-static char *compr_names[] = {
-        "NONE",
-        "ZERO",
-        "RTIME",
-        "RUBINMIPS",
-        "COPY",
-        "DYNRUBIN",
-        "ZLIB" };

-static char spinner[] = { '|', '\\', '-', '/' };
+#define	NODE_CHUNK  	1024	/* size of memory allocation chunk in b_nodes */
+#define	SPIN_BLKSIZE	18  	/* spin after having scanned 1<<BLKSIZE bytes */
+
+/* Debugging switches */
+#undef	DEBUG_DIRENTS		/* print directory entry list after scan */
+#undef	DEBUG_FRAGMENTS		/* print fragment list after scan */
+#undef	DEBUG   			/* enable debugging messages */
+

-#define DEBUG
 #ifdef  DEBUG
 # define DEBUGF(fmt,args...)	printf(fmt ,##args)
 #else
 # define DEBUGF(fmt,args...)
 #endif

-#define MALLOC_CHUNK (10*1024)

+/* Compression names */
+static char *compr_names[] = {
+	"NONE",
+	"ZERO",
+	"RTIME",
+	"RUBINMIPS",
+	"COPY",
+	"DYNRUBIN",
+	"ZLIB"
+};
+
+/* Spinning wheel */
+static char spinner[] = { '|', '/', '-', '\\' };
+
+/* Memory management */
+struct mem_block {
+	u32	index;
+	struct mem_block *next;
+	struct b_node nodes[NODE_CHUNK];
+};
+
+
+static void
+free_nodes(struct b_list *list)
+{
+	while (list->listMemBase != NULL) {
+		struct mem_block *next = list->listMemBase->next;
+		free( list->listMemBase );
+		list->listMemBase = next;
+	}
+}

 static struct b_node *
-add_node(struct b_node *tail, u32 * count, u32 * memBase)
+add_node(struct b_list *list)
 {
-	u32 index;
-	u32 memLimit;
+	u32 index = 0;
+	struct mem_block *memBase;
 	struct b_node *b;

-	index = (*count) * sizeof(struct b_node) % MALLOC_CHUNK;
-	memLimit = MALLOC_CHUNK;
-
+	memBase = list->listMemBase;
+	if (memBase != NULL)
+		index = memBase->index;
 #if 0
 	putLabeledWord("add_node: index = ", index);
-	putLabeledWord("add_node: memLimit = ", memLimit);
-	putLabeledWord("add_node: memBase = ", *memBase);
+	putLabeledWord("add_node: memBase = ", list->listMemBase);
 #endif

-	/* we need not keep a list of bases since we'll never free the */
-	/* memory, just jump the the kernel */
-	if ((index == 0) || (index > memLimit)) {	/* we need mode space before we continue */
-		if ((*memBase = (u32) mmalloc(MALLOC_CHUNK)) == (u32) NULL) {
+	if (memBase == NULL || index >= NODE_CHUNK) {
+		/* we need more space before we continue */
+		memBase = mmalloc(sizeof(struct mem_block));
+		if (memBase == NULL) {
 			putstr("add_node: malloc failed\n");
 			return NULL;
 		}
+		memBase->next = list->listMemBase;
+		index = 0;
 #if 0
 		putLabeledWord("add_node: alloced a new membase at ", *memBase);
 #endif

 	}
 	/* now we have room to add it. */
-	b = (struct b_node *) (*memBase + index);
+	b = &memBase->nodes[index];
+	index ++;

-	/* null on first call */
-	if (tail)
-		tail->next = b;
-
-#if 0
-	putLabeledWord("add_node: tail = ", (u32) tail);
-	if (tail)
-		putLabeledWord("add_node: tail->next = ", (u32) tail->next);
-
-#endif
-
-#if 0
-	putLabeledWord("add_node: mb+i = ", (u32) (*memBase + index));
-	putLabeledWord("add_node: b = ", (u32) b);
-#endif
-	(*count)++;
-	b->next = (struct b_node *) NULL;
+	memBase->index = index;
+	list->listMemBase = memBase;
+	list->listCount++;
 	return b;
-
 }

-/* we know we have empties at the start offset so we will hop */
-/* t points that would be non F if there were a node here to speed this up. */
-struct jffs2_empty_node {
-	u32 first;
-	u32 second;
-};
+static struct b_node *
+insert_node(struct b_list *list, u32 offset)
+{
+	struct b_node *new;
+#ifdef CFG_JFFS2_SORT_FRAGMENTS
+	struct b_node *b, *prev;
+#endif
+
+	if (!(new = add_node(list))) {
+		putstr("add_node failed!\r\n");
+		return NULL;
+	}
+	new->offset = offset;
+
+#ifdef CFG_JFFS2_SORT_FRAGMENTS
+	if (list->listTail != NULL && list->listCompare(new, list->listTail))
+		prev = list->listTail;
+	else if (list->listLast != NULL && list->listCompare(new, list->listLast))
+		prev = list->listLast;
+	else
+		prev = NULL;
+
+	for (b = (prev ? prev->next : list->listHead);
+	     b != NULL && list->listCompare(new, b);
+	     prev = b, b = b->next) {
+		list->listLoops++;
+	}
+	if (b != NULL)
+		list->listLast = prev;
+
+	if (b != NULL) {
+		new->next = b;
+		if (prev != NULL)
+			prev->next = new;
+		else
+			list->listHead = new;
+	} else
+#endif
+	{
+		new->next = (struct b_node *) NULL;
+		if (list->listTail != NULL) {
+			list->listTail->next = new;
+			list->listTail = new;
+		} else {
+			list->listTail = list->listHead = new;
+		}
+	}
+
+	return new;
+}
+
+#ifdef CFG_JFFS2_SORT_FRAGMENTS
+static int compare_inodes(struct b_node *new, struct b_node *old)
+{
+	struct jffs2_raw_inode *jNew = (struct jffs2_raw_inode *)new->offset;
+	struct jffs2_raw_inode *jOld = (struct jffs2_raw_inode *)old->offset;
+
+	return jNew->version < jOld->version;
+}
+
+static int compare_dirents(struct b_node *new, struct b_node *old)
+{
+	struct jffs2_raw_dirent *jNew = (struct jffs2_raw_dirent *)new->offset;
+	struct jffs2_raw_dirent *jOld = (struct jffs2_raw_dirent *)old->offset;
+
+	return jNew->version > jOld->version;
+}
+#endif

 static u32
 jffs2_scan_empty(u32 start_offset, struct part_info *part)
 {
-	u32 max = part->size - sizeof(struct jffs2_raw_inode);
+	char *max = part->offset + part->size - sizeof(struct jffs2_raw_inode);
+	char *offset = part->offset + start_offset;

-	/* this would be either dir node_crc or frag isize */
-	u32 offset = start_offset + 32;
-	struct jffs2_empty_node *node;
-
-	start_offset += 4;
-	while (offset < max) {
-		node = (struct jffs2_empty_node *) (part->offset + offset);
-		if ((node->first == 0xFFFFFFFF) && (node->second == 0xFFFFFFFF)) {
-			/* we presume that there were no nodes in between and advance in a hop */
-			/* putLabeledWord("\t\tjffs2_scan_empty: empty at offset=",offset); */
-			start_offset = offset + 4;
-			offset = start_offset + 32;	/* orig 32 + 4 bytes for the second==0xfffff */
-		} else {
-			return start_offset;
-		}
+	while (offset < max && *(u32 *)offset == 0xFFFFFFFF) {
+		offset += sizeof(u32);
+		/* return if spinning is due */
+		if (((u32)offset & ((1 << SPIN_BLKSIZE)-1)) == 0) break;
 	}
-	return start_offset;
+
+	return offset - part->offset;
 }

 static u32
 jffs_init_1pass_list(struct part_info *part)
 {
-	if ( 0 != ( part->jffs2_priv=malloc(sizeof(struct b_lists)))){
-		struct b_lists *pL =(struct b_lists *)part->jffs2_priv;
+	struct b_lists *pL;

-		pL->dirListHead = pL->dirListTail = NULL;
-		pL->fragListHead = pL->fragListTail = NULL;
-		pL->dirListCount = 0;
-		pL->dirListMemBase = 0;
-		pL->fragListCount = 0;
-		pL->fragListMemBase = 0;
-		pL->partOffset = 0x0;
+	if (part->jffs2_priv != NULL) {
+		pL = (struct b_lists *)part->jffs2_priv;
+		free_nodes(&pL->frag);
+		free_nodes(&pL->dir);
+		free(pL);
+	}
+	if (NULL != (part->jffs2_priv = malloc(sizeof(struct b_lists)))) {
+		pL = (struct b_lists *)part->jffs2_priv;
+
+		memset(pL, 0, sizeof(*pL));
+#ifdef CFG_JFFS2_SORT_FRAGMENTS
+		pL->dir.listCompare = compare_dirents;
+		pL->frag.listCompare = compare_inodes;
+#endif
 	}
 	return 0;
 }
@@ -216,21 +326,18 @@ jffs2_1pass_read_inode(struct b_lists *pL, u32 inode, char *dest)
 {
 	struct b_node *b;
 	struct jffs2_raw_inode *jNode;
-	u32 totalSize = 1;
-	u32 oldTotalSize = 0;
-	u32 size = 0;
-	char *lDest = (char *) dest;
+	u32 totalSize = 0;
+	u16 latestVersion = 0;
+	char *lDest;
 	char *src;
 	long ret;
 	int i;
 	u32 counter = 0;
-	char totalSizeSet = 0;

-#if 0
-	b = pL->fragListHead;
-	while (b) {
+	for (b = pL->frag.listHead; b != NULL; b = b->next) {
 		jNode = (struct jffs2_raw_inode *) (b->offset);
 		if ((inode == jNode->ino)) {
+#if 0
 			putLabeledWord("\r\n\r\nread_inode: totlen = ", jNode->totlen);
 			putLabeledWord("read_inode: inode = ", jNode->ino);
 			putLabeledWord("read_inode: version = ", jNode->version);
@@ -241,58 +348,26 @@ jffs2_1pass_read_inode(struct b_lists *pL, u32 inode, char *dest)
 			putLabeledWord("read_inode: compr = ", jNode->compr);
 			putLabeledWord("read_inode: usercompr = ", jNode->usercompr);
 			putLabeledWord("read_inode: flags = ", jNode->flags);
-		}
-
-		b = b->next;
-	}
-
 #endif
-
-#if 1
-	b = pL->fragListHead;
-	while (b && (size < totalSize)) {
-		jNode = (struct jffs2_raw_inode *) (b->offset);
-		if ((inode == jNode->ino)) {
-			if ((jNode->isize == oldTotalSize) && (jNode->isize > totalSize)) {
-				/* 2 consecutive isizes indicate file length */
+			/* get actual file length from the newest node */
+			if (jNode->version >= latestVersion) {
 				totalSize = jNode->isize;
-				totalSizeSet = 1;
-			} else if (!totalSizeSet) {
-				totalSize = size + jNode->dsize + 1;
+				latestVersion = jNode->version;
 			}
-			oldTotalSize = jNode->isize;

 			if(dest) {
 				src = ((char *) jNode) + sizeof(struct jffs2_raw_inode);
-				/* lDest = (char *) (dest + (jNode->offset & ~3)); */
+				/* ignore data behind latest known EOF */
+				if (jNode->offset > totalSize)
+					continue;
+
 				lDest = (char *) (dest + jNode->offset);
 #if 0
-				putLabeledWord("\r\n\r\nread_inode: src = ", src);
+				putLabeledWord("read_inode: src = ", src);
 				putLabeledWord("read_inode: dest = ", lDest);
-				putLabeledWord("read_inode: dsize = ", jNode->dsize);
-				putLabeledWord("read_inode: csize = ", jNode->csize);
-				putLabeledWord("read_inode: version = ", jNode->version);
-				putLabeledWord("read_inode: isize = ", jNode->isize);
-				putLabeledWord("read_inode: offset = ", jNode->offset);
-				putLabeledWord("read_inode: compr = ", jNode->compr);
-				putLabeledWord("read_inode: flags = ", jNode->flags);
 #endif
 				switch (jNode->compr) {
 				case JFFS2_COMPR_NONE:
-#if 0
-					{
-						int i;
-
-						if ((dest > 0xc0092ff0) && (dest < 0xc0093000))
-							for (i = 0; i < first->length; i++) {
-								putLabeledWord("\tCOMPR_NONE: src =", src + i);
-								putLabeledWord("\tCOMPR_NONE: length =", first->length);
-								putLabeledWord("\tCOMPR_NONE: dest =", dest + i);
-								putLabeledWord("\tCOMPR_NONE: data =", (unsigned char) *(src + i));
-							}
-					}
-#endif
-
 					ret = (unsigned long) ldr_memcpy(lDest, src, jNode->dsize);
 					break;
 				case JFFS2_COMPR_ZERO:
@@ -320,22 +395,18 @@ jffs2_1pass_read_inode(struct b_lists *pL, u32 inode, char *dest)
 				}
 			}

-			size += jNode->dsize;
 #if 0
-			putLabeledWord("read_inode: size = ", size);
 			putLabeledWord("read_inode: totalSize = ", totalSize);
 			putLabeledWord("read_inode: compr ret = ", ret);
 #endif
 		}
-		b = b->next;
 		counter++;
 	}
-#endif

 #if 0
-	putLabeledWord("read_inode: returning = ", size);
+	putLabeledWord("read_inode: returning = ", totalSize);
 #endif
-	return size;
+	return totalSize;
 }

 /* find the inode from the slashless name given a parent */
@@ -354,18 +425,19 @@ jffs2_1pass_find_inode(struct b_lists * pL, const char *name, u32 pino)

 	counter = 0;
 	/* we need to search all and return the inode with the highest version */
-	for(b = pL->dirListHead;b;b=b->next,counter++) {
+	for(b = pL->dir.listHead; b; b = b->next, counter++) {
 		jDir = (struct jffs2_raw_dirent *) (b->offset);
-		if ((pino == jDir->pino) && (len == jDir->nsize) && (jDir->ino) &&	/* 0 for unlink */
+		if ((pino == jDir->pino) && (len == jDir->nsize) &&
+		    (jDir->ino) &&	/* 0 for unlink */
 		    (!strncmp(jDir->name, name, len))) {	/* a match */
 			if (jDir->version < version) continue;

-		        if(jDir->version==0) {
+		        if(jDir->version == 0) {
 			    	/* Is this legal? */
 				putstr(" ** WARNING ** ");
 				putnstr(jDir->name, jDir->nsize);
 				putstr(" is version 0 (in find, ignoring)\r\n");
-			} else if(jDir->version==version) {
+			} else if(jDir->version == version) {
 			    	/* Im pretty sure this isn't ... */
 				putstr(" ** ERROR ** ");
 				putnstr(jDir->name, jDir->nsize);
@@ -389,53 +461,53 @@ jffs2_1pass_find_inode(struct b_lists * pL, const char *name, u32 pino)

 static char *mkmodestr(unsigned long mode, char *str)
 {
-    static const char *l="xwr";
-    int mask=1, i;
-    char c;
+	static const char *l = "xwr";
+	int mask = 1, i;
+	char c;

-    switch (mode & S_IFMT) {
-        case S_IFDIR:    str[0]='d'; break;
-        case S_IFBLK:    str[0]='b'; break;
-        case S_IFCHR:    str[0]='c'; break;
-        case S_IFIFO:    str[0]='f'; break;
-        case S_IFLNK:    str[0]='l'; break;
-        case S_IFSOCK:   str[0]='s'; break;
-        case S_IFREG:    str[0]='-'; break;
-        default:        str[0]='?';
-    }
+	switch (mode & S_IFMT) {
+		case S_IFDIR:    str[0] = 'd'; break;
+		case S_IFBLK:    str[0] = 'b'; break;
+		case S_IFCHR:    str[0] = 'c'; break;
+		case S_IFIFO:    str[0] = 'f'; break;
+		case S_IFLNK:    str[0] = 'l'; break;
+		case S_IFSOCK:   str[0] = 's'; break;
+		case S_IFREG:    str[0] = '-'; break;
+		default:         str[0] = '?';
+	}

-    for(i=0;i<9;i++) {
-        c=l[i%3];
-        str[9-i]=(mode & mask)?c:'-';
-        mask=mask<<1;
-    }
+	for(i = 0; i < 9; i++) {
+		c = l[i%3];
+		str[9-i] = (mode & mask)?c:'-';
+		mask = mask<<1;
+	}

-    if(mode & S_ISUID) str[3]=(mode & S_IXUSR)?'s':'S';
-    if(mode & S_ISGID) str[6]=(mode & S_IXGRP)?'s':'S';
-    if(mode & S_ISVTX) str[9]=(mode & S_IXOTH)?'t':'T';
-    str[10]='\0';
-    return str;
+	if(mode & S_ISUID) str[3] = (mode & S_IXUSR)?'s':'S';
+	if(mode & S_ISGID) str[6] = (mode & S_IXGRP)?'s':'S';
+	if(mode & S_ISVTX) str[9] = (mode & S_IXOTH)?'t':'T';
+	str[10] = '\0';
+	return str;
 }

 static inline void dump_stat(struct stat *st, const char *name)
 {
-    char str[20];
-    char s[64], *p;
+	char str[20];
+	char s[64], *p;

-    if (st->st_mtime == (time_t)(-1))	/* some ctimes really hate -1 */
-        st->st_mtime = 1;
+	if (st->st_mtime == (time_t)(-1)) /* some ctimes really hate -1 */
+		st->st_mtime = 1;

-    ctime_r(&st->st_mtime, s/*, 64*/);   /* newlib ctime doesn't have buflen */
+	ctime_r(&st->st_mtime, s/*,64*/); /* newlib ctime doesn't have buflen */

-    if((p=strchr(s,'\n'))!=NULL) *p='\0';
-    if((p=strchr(s,'\r'))!=NULL) *p='\0';
+	if ((p = strchr(s,'\n')) != NULL) *p = '\0';
+	if ((p = strchr(s,'\r')) != NULL) *p = '\0';

 /*
-    printf("%6lo %s %8ld %s %s\n", st->st_mode, mkmodestr(st->st_mode, str),
-        st->st_size, s, name);
+	printf("%6lo %s %8ld %s %s\n", st->st_mode, mkmodestr(st->st_mode, str),
+		st->st_size, s, name);
 */

-    printf(" %s %8ld %s %s", mkmodestr(st->st_mode,str), st->st_size, s, name);
+	printf(" %s %8ld %s %s", mkmodestr(st->st_mode,str), st->st_size, s, name);
 }

 static inline u32 dump_inode(struct b_lists * pL, struct jffs2_raw_dirent *d, struct jffs2_raw_inode *i)
@@ -446,16 +518,16 @@ static inline u32 dump_inode(struct b_lists * pL, struct jffs2_raw_dirent *d, st
 	if(!d || !i) return -1;

 	strncpy(fname, d->name, d->nsize);
-	fname[d->nsize]='\0';
+	fname[d->nsize] = '\0';

 	memset(&st,0,sizeof(st));

-	st.st_mtime=i->mtime;
-	st.st_mode=i->mode;
-	st.st_ino=i->ino;
+	st.st_mtime = i->mtime;
+	st.st_mode = i->mode;
+	st.st_ino = i->ino;

 	/* neither dsize nor isize help us.. do it the long way */
-	st.st_size=jffs2_1pass_read_inode(pL, i->ino, NULL);
+	st.st_size = jffs2_1pass_read_inode(pL, i->ino, NULL);

 	dump_stat(&st, fname);

@@ -477,18 +549,18 @@ jffs2_1pass_list_inodes(struct b_lists * pL, u32 pino)
 	struct b_node *b;
 	struct jffs2_raw_dirent *jDir;

-	for(b = pL->dirListHead;b;b=b->next) {
+	for (b = pL->dir.listHead; b; b = b->next) {
 		jDir = (struct jffs2_raw_dirent *) (b->offset);
-		if ((pino == jDir->pino) && (jDir->ino)) {	/* 0 inode for unlink */
-			u32 i_version=0;
-			struct jffs2_raw_inode *jNode, *i=NULL;
-			struct b_node *b2 = pL->fragListHead;
+		if ((pino == jDir->pino) && (jDir->ino)) { /* ino=0 -> unlink */
+			u32 i_version = 0;
+			struct jffs2_raw_inode *jNode, *i = NULL;
+			struct b_node *b2 = pL->frag.listHead;

 			while (b2) {
 				jNode = (struct jffs2_raw_inode *) (b2->offset);
 				if (jNode->ino == jDir->ino
-				    && jNode->version>=i_version)
-					i=jNode;
+				    && jNode->version >= i_version)
+					i = jNode;
 				b2 = b2->next;
 			}

@@ -568,7 +640,7 @@ jffs2_1pass_resolve_inode(struct b_lists * pL, u32 ino)
 	unsigned char *src;

 	/* we need to search all and return the inode with the highest version */
-	for(b = pL->dirListHead; b; b=b->next) {
+	for(b = pL->dir.listHead; b; b = b->next) {
 		jDir = (struct jffs2_raw_dirent *) (b->offset);
 		if (ino == jDir->ino) {
 		    	if(jDir->version < version) continue;
@@ -593,8 +665,9 @@ jffs2_1pass_resolve_inode(struct b_lists * pL, u32 ino)
 	/* now we found the right entry again. (shoulda returned inode*) */
 	if (jDirFound->type != DT_LNK)
 		return jDirFound->ino;
-	/* so its a soft link so we follow it again. */
-	b2 = pL->fragListHead;
+
+	/* it's a soft link so we follow it again. */
+	b2 = pL->frag.listHead;
 	while (b2) {
 		jNode = (struct jffs2_raw_inode *) (b2->offset);
 		if (jNode->ino == jDirFound->ino) {
@@ -644,7 +717,8 @@ jffs2_1pass_search_list_inodes(struct b_lists * pL, const char *fname, u32 pino)
 			tmp[i] = c[i + 1];
 		tmp[i] = '\0';
 		/* only a failure if we arent looking at top level */
-		if (!(pino = jffs2_1pass_find_inode(pL, working_tmp, pino)) && (working_tmp[0])) {
+		if (!(pino = jffs2_1pass_find_inode(pL, working_tmp, pino)) &&
+		    (working_tmp[0])) {
 			putstr("find_inode failed for name=");
 			putstr(working_tmp);
 			putstr("\r\n");
@@ -674,29 +748,30 @@ jffs2_1pass_rescan_needed(struct part_info *part)
 {
 	struct b_node *b;
 	struct jffs2_unknown_node *node;
-	struct b_lists *pL=(struct b_lists *)part->jffs2_priv;
+	struct b_lists *pL = (struct b_lists *)part->jffs2_priv;

 	if (part->jffs2_priv == 0){
 		DEBUGF ("rescan: First time in use\n");
 		return 1;
 	}
 	/* if we have no list, we need to rescan */
-	if (pL->fragListCount == 0) {
+	if (pL->frag.listCount == 0) {
 		DEBUGF ("rescan: fraglist zero\n");
 		return 1;
 	}

-	/* or if we are scanninga new partition */
+	/* or if we are scanning a new partition */
 	if (pL->partOffset != part->offset) {
 		DEBUGF ("rescan: different partition\n");
 		return 1;
 	}
-	/* but suppose someone reflashed the root partition at the same offset... */
-	b = pL->dirListHead;
+	/* but suppose someone reflashed a partition at the same offset... */
+	b = pL->dir.listHead;
 	while (b) {
 		node = (struct jffs2_unknown_node *) (b->offset);
 		if (node->nodetype != JFFS2_NODETYPE_DIRENT) {
-			DEBUGF ("rescan: fs changed beneath me? (%lx)\n", (unsigned long) b->offset);
+			DEBUGF ("rescan: fs changed beneath me? (%lx)\n",
+					(unsigned long) b->offset);
 			return 1;
 		}
 		b = b->next;
@@ -704,12 +779,71 @@ jffs2_1pass_rescan_needed(struct part_info *part)
 	return 0;
 }

+#ifdef DEBUG_FRAGMENTS
+static void
+dump_fragments(struct b_lists *pL)
+{
+	struct b_node *b;
+	struct jffs2_raw_inode *jNode;
+
+	putstr("\r\n\r\n******The fragment Entries******\r\n");
+	b = pL->frag.listHead;
+	while (b) {
+		jNode = (struct jffs2_raw_inode *) (b->offset);
+		putLabeledWord("\r\n\tbuild_list: FLASH_OFFSET = ", b->offset);
+		putLabeledWord("\tbuild_list: totlen = ", jNode->totlen);
+		putLabeledWord("\tbuild_list: inode = ", jNode->ino);
+		putLabeledWord("\tbuild_list: version = ", jNode->version);
+		putLabeledWord("\tbuild_list: isize = ", jNode->isize);
+		putLabeledWord("\tbuild_list: atime = ", jNode->atime);
+		putLabeledWord("\tbuild_list: offset = ", jNode->offset);
+		putLabeledWord("\tbuild_list: csize = ", jNode->csize);
+		putLabeledWord("\tbuild_list: dsize = ", jNode->dsize);
+		putLabeledWord("\tbuild_list: compr = ", jNode->compr);
+		putLabeledWord("\tbuild_list: usercompr = ", jNode->usercompr);
+		putLabeledWord("\tbuild_list: flags = ", jNode->flags);
+		putLabeledWord("\tbuild_list: offset = ", b->offset);	// FIXME: ? [RS]
+		b = b->next;
+	}
+}
+#endif
+
+#ifdef DEBUG_DIRENTS
+static void
+dump_dirents(struct b_lists *pL)
+{
+	struct b_node *b;
+	struct jffs2_raw_dirent *jDir;
+
+	putstr("\r\n\r\n******The directory Entries******\r\n");
+	b = pL->dir.listHead;
+	while (b) {
+		jDir = (struct jffs2_raw_dirent *) (b->offset);
+		putstr("\r\n");
+		putnstr(jDir->name, jDir->nsize);
+		putLabeledWord("\r\n\tbuild_list: magic = ", jDir->magic);
+		putLabeledWord("\tbuild_list: nodetype = ", jDir->nodetype);
+		putLabeledWord("\tbuild_list: hdr_crc = ", jDir->hdr_crc);
+		putLabeledWord("\tbuild_list: pino = ", jDir->pino);
+		putLabeledWord("\tbuild_list: version = ", jDir->version);
+		putLabeledWord("\tbuild_list: ino = ", jDir->ino);
+		putLabeledWord("\tbuild_list: mctime = ", jDir->mctime);
+		putLabeledWord("\tbuild_list: nsize = ", jDir->nsize);
+		putLabeledWord("\tbuild_list: type = ", jDir->type);
+		putLabeledWord("\tbuild_list: node_crc = ", jDir->node_crc);
+		putLabeledWord("\tbuild_list: name_crc = ", jDir->name_crc);
+		putLabeledWord("\tbuild_list: offset = ", b->offset); 	// FIXME: ? [RS]
+		b = b->next;
+	}
+}
+#endif
+
 static u32
 jffs2_1pass_build_lists(struct part_info * part)
 {
 	struct b_lists *pL;
 	struct jffs2_unknown_node *node;
-	u32 offset;
+	u32 offset, oldoffset = 0;
 	u32 max = part->size - sizeof(struct jffs2_raw_inode);
 	u32 counter = 0;
 	u32 counter4 = 0;
@@ -722,71 +856,52 @@ jffs2_1pass_build_lists(struct part_info * part)
 	/* lcd_off(); */

 	/* if we are building a list we need to refresh the cache. */
-	/* note that since we don't free our memory, eventually this will be bad. */
-	/* but we're a bootldr so what the hell. */
 	jffs_init_1pass_list(part);
-	pL=(struct b_lists *)part->jffs2_priv;
+	pL = (struct b_lists *)part->jffs2_priv;
 	pL->partOffset = part->offset;
 	offset = 0;
 	printf("Scanning JFFS2 FS:   ");

 	/* start at the beginning of the partition */
 	while (offset < max) {
-	    	if (! (++counter%10000))
-			printf("\b\b%c ", spinner[(counter / 10000) % 4]);
+	    	if ((oldoffset >> SPIN_BLKSIZE) != (offset >> SPIN_BLKSIZE)) {
+			printf("\b\b%c ", spinner[counter++ % sizeof(spinner)]);
+			oldoffset = offset;
+		}

 		node = (struct jffs2_unknown_node *) (part->offset + offset);
 		if (node->magic == JFFS2_MAGIC_BITMASK && hdr_crc(node)) {
 			/* if its a fragment add it */
-			if (node->nodetype == JFFS2_NODETYPE_INODE && inode_crc((struct jffs2_raw_inode *) node)) {
-				if (!(pL->fragListTail = add_node(pL->fragListTail, &(pL->fragListCount),
-								  &(pL->fragListMemBase)))) {
-					putstr("add_node failed!\r\n");
+			if (node->nodetype == JFFS2_NODETYPE_INODE &&
+				    inode_crc((struct jffs2_raw_inode *) node)) {
+				if (insert_node(&pL->frag, (u32) part->offset +
+								offset) == NULL)
 					return 0;
-				}
-				pL->fragListTail->offset = (u32) (part->offset + offset);
-				if (!pL->fragListHead)
-					pL->fragListHead = pL->fragListTail;
 			} else if (node->nodetype == JFFS2_NODETYPE_DIRENT &&
 				   dirent_crc((struct jffs2_raw_dirent *) node)  &&
 				   dirent_name_crc((struct jffs2_raw_dirent *) node)) {
 				if (! (counterN%100))
 					printf("\b\b.  ");
-#if 0
-				printf("Found DIRENT @ 0x%lx\n", offset);
-				putstr("\r\nbuild_lists:p&l ->");
-				putnstr(((struct jffs2_raw_dirent *) node)->name, ((struct jffs2_raw_dirent *) node)->nsize);
-				putstr("\r\n");
-				putLabeledWord("\tpino = ", ((struct jffs2_raw_dirent *) node)->pino);
-				putLabeledWord("\tnsize = ", ((struct jffs2_raw_dirent *) node)->nsize);
-#endif
-
-				if (!(pL->dirListTail = add_node(pL->dirListTail, &(pL->dirListCount), &(pL->dirListMemBase)))) {
-					putstr("add_node failed!\r\n");
+				if (insert_node(&pL->dir, (u32) part->offset +
+								offset) == NULL)
 					return 0;
-				}
-				pL->dirListTail->offset = (u32) (part->offset + offset);
-#if 0
-				putLabeledWord("\ttail = ", (u32) pL->dirListTail);
-				putstr("\ttailName ->");
-				putnstr(((struct jffs2_raw_dirent *) (pL->dirListTail->offset))->name,
-					((struct jffs2_raw_dirent *) (pL->dirListTail->offset))->nsize);
-				putstr("\r\n");
-#endif
-				if (!pL->dirListHead)
-					pL->dirListHead = pL->dirListTail;
 				counterN++;
 			} else if (node->nodetype == JFFS2_NODETYPE_CLEANMARKER) {
 				if (node->totlen != sizeof(struct jffs2_unknown_node))
-					printf("OOPS Cleanmarker has bad size %d != %d\n", node->totlen, sizeof(struct jffs2_unknown_node));
+					printf("OOPS Cleanmarker has bad size "
+						"%d != %d\n", node->totlen,
+						sizeof(struct jffs2_unknown_node));
 			} else {
-				printf("Unknown node type: %x len %d offset 0x%x\n", node->nodetype, node->totlen, offset);
+				printf("Unknown node type: %x len %d "
+					"offset 0x%x\n", node->nodetype,
+					node->totlen, offset);
 			}
 			offset += ((node->totlen + 3) & ~3);
 			counterF++;
-		} else if (node->magic == JFFS2_EMPTY_BITMASK && node->nodetype == JFFS2_EMPTY_BITMASK) {
+		} else if (node->magic == JFFS2_EMPTY_BITMASK &&
+			   node->nodetype == JFFS2_EMPTY_BITMASK) {
 			offset = jffs2_scan_empty(offset, part);
-		} else {	/* if we know nothing of the filesystem, we just step and look. */
+		} else {	/* if we know nothing, we just step and look. */
 			offset += 4;
 			counter4++;
 		}
@@ -799,66 +914,21 @@ jffs2_1pass_build_lists(struct part_info * part)
 	/* splash(); */

 #if 0
-	putLabeledWord("dir entries = ", pL->dirListCount);
-	putLabeledWord("frag entries = ", pL->fragListCount);
+	putLabeledWord("dir entries = ", pL->dir.listCount);
+	putLabeledWord("frag entries = ", pL->frag.listCount);
 	putLabeledWord("+4 increments = ", counter4);
 	putLabeledWord("+file_offset increments = ", counterF);

 #endif

-#undef SHOW_ALL
-#undef SHOW_ALL_FRAGMENTS
+#ifdef DEBUG_DIRENTS
+	dump_dirents(pL);
+#endif

-#ifdef SHOW_ALL
-	{
-		struct b_node *b;
-		struct b_node *b2;
-		struct jffs2_raw_dirent *jDir;
-		struct jffs2_raw_inode *jNode;
+#ifdef DEBUG_FRAGMENTS
+	dump_fragments(pL);
+#endif

-		putstr("\r\n\r\n******The directory Entries******\r\n");
-		b = pL->dirListHead;
-		while (b) {
-			jDir = (struct jffs2_raw_dirent *) (b->offset);
-			putstr("\r\n");
-			putnstr(jDir->name, jDir->nsize);
-			putLabeledWord("\r\n\tbuild_list: magic = ", jDir->magic);
-			putLabeledWord("\tbuild_list: nodetype = ", jDir->nodetype);
-			putLabeledWord("\tbuild_list: hdr_crc = ", jDir->hdr_crc);
-			putLabeledWord("\tbuild_list: pino = ", jDir->pino);
-			putLabeledWord("\tbuild_list: version = ", jDir->version);
-			putLabeledWord("\tbuild_list: ino = ", jDir->ino);
-			putLabeledWord("\tbuild_list: mctime = ", jDir->mctime);
-			putLabeledWord("\tbuild_list: nsize = ", jDir->nsize);
-			putLabeledWord("\tbuild_list: type = ", jDir->type);
-			putLabeledWord("\tbuild_list: node_crc = ", jDir->node_crc);
-			putLabeledWord("\tbuild_list: name_crc = ", jDir->name_crc);
-			b = b->next;
-		}
-
-#ifdef SHOW_ALL_FRAGMENTS
-		putstr("\r\n\r\n******The fragment Entries******\r\n");
-		b = pL->fragListHead;
-		while (b) {
-			jNode = (struct jffs2_raw_inode *) (b->offset);
-			putLabeledWord("\r\n\tbuild_list: FLASH_OFFSET = ", b->offset);
-			putLabeledWord("\tbuild_list: totlen = ", jNode->totlen);
-			putLabeledWord("\tbuild_list: inode = ", jNode->ino);
-			putLabeledWord("\tbuild_list: version = ", jNode->version);
-			putLabeledWord("\tbuild_list: isize = ", jNode->isize);
-			putLabeledWord("\tbuild_list: atime = ", jNode->atime);
-			putLabeledWord("\tbuild_list: offset = ", jNode->offset);
-			putLabeledWord("\tbuild_list: csize = ", jNode->csize);
-			putLabeledWord("\tbuild_list: dsize = ", jNode->dsize);
-			putLabeledWord("\tbuild_list: compr = ", jNode->compr);
-			putLabeledWord("\tbuild_list: usercompr = ", jNode->usercompr);
-			putLabeledWord("\tbuild_list: flags = ", jNode->flags);
-			b = b->next;
-		}
-#endif /* SHOW_ALL_FRAGMENTS */
-	}
-
-#endif	/* SHOW_ALL */
 	/* give visual feedback that we are done scanning the flash */
 	led_blink(0x0, 0x0, 0x1, 0x1);	/* off, forever, on 100ms, off 100ms */
 	return 1;
@@ -875,13 +945,13 @@ jffs2_1pass_fill_info(struct b_lists * pL, struct b_jffs2_info * piL)
 	struct jffs2_raw_inode *jNode;
 	int i;

-	b = pL->fragListHead;
 	for (i = 0; i < JFFS2_NUM_COMPR; i++) {
 		piL->compr_info[i].num_frags = 0;
 		piL->compr_info[i].compr_sum = 0;
 		piL->compr_info[i].decompr_sum = 0;
 	}

+	b = pL->frag.listHead;
 	while (b) {
 		jNode = (struct jffs2_raw_inode *) (b->offset);
 		if (jNode->compr < JFFS2_NUM_COMPR) {
@@ -917,7 +987,7 @@ jffs2_1pass_ls(struct part_info * part, const char *fname)
 	long ret = 0;
 	u32 inode;

-	if (! (pl  = jffs2_get_list(part, "ls")))
+	if (! (pl = jffs2_get_list(part, "ls")))
 		return 0;

 	if (! (inode = jffs2_1pass_search_list_inodes(pl, fname, 1))) {
@@ -983,7 +1053,7 @@ jffs2_1pass_info(struct part_info * part)
 		return 0;

 	jffs2_1pass_fill_info(pl, &info);
-	for (i=0; i < JFFS2_NUM_COMPR; i++) {
+	for (i = 0; i < JFFS2_NUM_COMPR; i++) {
 		printf("Compression: %s\n", compr_names[i]);
 		printf("\tfrag count: %d\n", info.compr_info[i].num_frags);
 		printf("\tcompressed sum: %d\n", info.compr_info[i].compr_sum);
--- a/fs/jffs2/jffs2_private.h
+++ b/fs/jffs2/jffs2_private.h
@@ -3,23 +3,31 @@

 #include <jffs2/jffs2.h>

+
 struct b_node {
 	u32 offset;
 	struct b_node *next;
 };

+struct b_list {
+	struct b_node *listTail;
+	struct b_node *listHead;
+#ifdef CFG_JFFS2_SORT_FRAGMENTS
+	struct b_node *listLast;
+	int (*listCompare)(struct b_node *new, struct b_node *node);
+	u32 listLoops;
+#endif
+	u32 listCount;
+	struct mem_block *listMemBase;
+};
+
 struct b_lists {
 	char *partOffset;
-	struct b_node *dirListTail;
-	struct b_node *dirListHead;
-	u32 dirListCount;
-	u32 dirListMemBase;
-	struct b_node *fragListTail;
-	struct b_node *fragListHead;
-	u32 fragListCount;
-	u32 fragListMemBase;
+	struct b_list dir;
+	struct b_list frag;

 };
+
 struct b_compr_info {
 	u32 num_frags;
 	u32 compr_sum;
@@ -33,11 +41,14 @@ struct b_jffs2_info {
 static inline int
 hdr_crc(struct jffs2_unknown_node *node)
 {
+#if 1
        u32 crc = crc32_no_comp(0, (unsigned char *)node, sizeof(struct jffs2_unknown_node) - 4);
-        u32 crc_blah = crc32_no_comp(~0, (unsigned char *)node, sizeof(struct jffs2_unknown_node) - 4);
-
-        crc_blah ^= ~0;
+#else
+	/* what's the semantics of this? why is this here? */
+        u32 crc = crc32_no_comp(~0, (unsigned char *)node, sizeof(struct jffs2_unknown_node) - 4);

+        crc ^= ~0;
+#endif
        if (node->hdr_crc != crc) {
                return 0;
        } else {
--- a/include/asm-arm/arch-xscale/bitfield.h
+++ b/include/asm-arm/arch-xscale/bitfield.h
@@ -0,0 +1,113 @@
+/*
+ *	FILE    	bitfield.h
+ *
+ *	Version 	1.1
+ *	Author  	Copyright (c) Marc A. Viredaz, 1998
+ *	        	DEC Western Research Laboratory, Palo Alto, CA
+ *	Date    	April 1998 (April 1997)
+ *	System  	Advanced RISC Machine (ARM)
+ *	Language	C or ARM Assembly
+ *	Purpose 	Definition of macros to operate on bit fields.
+ */
+
+
+
+#ifndef __BITFIELD_H
+#define __BITFIELD_H
+
+#ifndef __ASSEMBLY__
+#define UData(Data)	((unsigned long) (Data))
+#else
+#define UData(Data)	(Data)
+#endif
+
+
+/*
+ * MACRO: Fld
+ *
+ * Purpose
+ *    The macro "Fld" encodes a bit field, given its size and its shift value
+ *    with respect to bit 0.
+ *
+ * Note
+ *    A more intuitive way to encode bit fields would have been to use their
+ *    mask. However, extracting size and shift value information from a bit
+ *    field's mask is cumbersome and might break the assembler (255-character
+ *    line-size limit).
+ *
+ * Input
+ *    Size      	Size of the bit field, in number of bits.
+ *    Shft      	Shift value of the bit field with respect to bit 0.
+ *
+ * Output
+ *    Fld       	Encoded bit field.
+ */
+
+#define Fld(Size, Shft)	(((Size) << 16) + (Shft))
+
+
+/*
+ * MACROS: FSize, FShft, FMsk, FAlnMsk, F1stBit
+ *
+ * Purpose
+ *    The macros "FSize", "FShft", "FMsk", "FAlnMsk", and "F1stBit" return
+ *    the size, shift value, mask, aligned mask, and first bit of a
+ *    bit field.
+ *
+ * Input
+ *    Field     	Encoded bit field (using the macro "Fld").
+ *
+ * Output
+ *    FSize     	Size of the bit field, in number of bits.
+ *    FShft     	Shift value of the bit field with respect to bit 0.
+ *    FMsk      	Mask for the bit field.
+ *    FAlnMsk   	Mask for the bit field, aligned on bit 0.
+ *    F1stBit   	First bit of the bit field.
+ */
+
+#define FSize(Field)	((Field) >> 16)
+#define FShft(Field)	((Field) & 0x0000FFFF)
+#define FMsk(Field)	(((UData (1) << FSize (Field)) - 1) << FShft (Field))
+#define FAlnMsk(Field)	((UData (1) << FSize (Field)) - 1)
+#define F1stBit(Field)	(UData (1) << FShft (Field))
+
+
+/*
+ * MACRO: FInsrt
+ *
+ * Purpose
+ *    The macro "FInsrt" inserts a value into a bit field by shifting the
+ *    former appropriately.
+ *
+ * Input
+ *    Value     	Bit-field value.
+ *    Field     	Encoded bit field (using the macro "Fld").
+ *
+ * Output
+ *    FInsrt    	Bit-field value positioned appropriately.
+ */
+
+#define FInsrt(Value, Field) \
+                	(UData (Value) << FShft (Field))
+
+
+/*
+ * MACRO: FExtr
+ *
+ * Purpose
+ *    The macro "FExtr" extracts the value of a bit field by masking and
+ *    shifting it appropriately.
+ *
+ * Input
+ *    Data      	Data containing the bit-field to be extracted.
+ *    Field     	Encoded bit field (using the macro "Fld").
+ *
+ * Output
+ *    FExtr     	Bit-field value.
+ */
+
+#define FExtr(Data, Field) \
+                	((UData (Data) >> FShft (Field)) & FAlnMsk (Field))
+
+
+#endif /* __BITFIELD_H */
--- a/include/asm-arm/arch-xscale/hardware.h
+++ b/include/asm-arm/arch-xscale/hardware.h
@@ -0,0 +1,153 @@
+/*
+ *  linux/include/asm-arm/arch-pxa/hardware.h
+ *
+ *  Author:	Nicolas Pitre
+ *  Created:	Jun 15, 2001
+ *  Copyright:	MontaVista Software Inc.
+ *  
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Note: This file was taken from linux-2.4.19-rmk4-pxa1
+ *
+ * - 2003/01/20 implementation specifics activated
+ *   Robert Schwebel <r.schwebel@pengutronix.de>
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <linux/config.h>
+#include <asm/mach-types.h>
+
+
+/*
+ * These are statically mapped PCMCIA IO space for designs using it as a
+ * generic IO bus, typically with ISA parts, hardwired IDE interfaces, etc.
+ * The actual PCMCIA code is mapping required IO region at run time.
+ */
+#define PCMCIA_IO_0_BASE	0xf6000000
+#define PCMCIA_IO_1_BASE	0xf7000000
+
+
+/*
+ * We requires absolute addresses.
+ */
+#define PCIO_BASE		0
+
+/*
+ * Workarounds for at least 2 errata so far require this.
+ * The mapping is set in mach-pxa/generic.c.
+ */
+#define UNCACHED_PHYS_0		0xff000000
+#define UNCACHED_ADDR		UNCACHED_PHYS_0
+
+/*
+ * Intel PXA internal I/O mappings:
+ *
+ * 0x40000000 - 0x41ffffff <--> 0xf8000000 - 0xf9ffffff
+ * 0x44000000 - 0x45ffffff <--> 0xfa000000 - 0xfbffffff
+ * 0x48000000 - 0x49ffffff <--> 0xfc000000 - 0xfdffffff
+ */
+
+/* FIXME: Only this does work for u-boot... find out why... [RS] */
+#define UBOOT_REG_FIX 1
+
+#ifndef UBOOT_REG_FIX
+#ifndef __ASSEMBLY__
+
+#define io_p2v(x)	( ((x) | 0xbe000000) ^ (~((x) >> 1) & 0x06000000) )
+#define io_v2p( x )	( ((x) & 0x41ffffff) ^ ( ((x) & 0x06000000) << 1) )
+
+/*
+ * This __REG() version gives the same results as the one above,  except
+ * that we are fooling gcc somehow so it generates far better and smaller
+ * assembly code for access to contigous registers.  It's a shame that gcc
+ * doesn't guess this by itself.
+ */
+#include <asm/types.h>
+typedef struct { volatile u32 offset[4096]; } __regbase;
+# define __REGP(x)	((__regbase *)((x)&~4095))->offset[((x)&4095)>>2]
+# define __REG(x)	__REGP(io_p2v(x))
+#endif
+
+/* Let's kick gcc's ass again... */
+# define __REG2(x,y)	\
+	( __builtin_constant_p(y) ? (__REG((x) + (y))) \
+				  : (*(volatile u32 *)((u32)&__REG(x) + (y))) )
+
+# define __PREG(x)	(io_v2p((u32)&(x)))
+
+#else
+
+# define __REG(x)	io_p2v(x)
+# define __PREG(x)	io_v2p(x)
+
+#endif
+#endif /* UBOOT_REG_FIX */
+	
+#ifdef UBOOT_REG_FIX
+# undef	io_p2v
+# undef __REG
+# ifndef __ASSEMBLY__
+#  define io_p2v(PhAdd)    (PhAdd)
+#  define __REG(x)	(*((volatile u32 *)io_p2v(x)))
+#  define __REG2(x,y)	(*(volatile u32 *)((u32)&__REG(x) + (y)))	
+# else
+#  define __REG(x) (x)	
+#endif /* UBOOT_REG_FIX */
+
+#include "pxa-regs.h"
+
+#ifndef __ASSEMBLY__
+
+/*
+ * GPIO edge detection for IRQs:
+ * IRQs are generated on Falling-Edge, Rising-Edge, or both.
+ * This must be called *before* the corresponding IRQ is registered.
+ * Use this instead of directly setting GRER/GFER.
+ */
+#define GPIO_FALLING_EDGE       1
+#define GPIO_RISING_EDGE        2
+#define GPIO_BOTH_EDGES         3
+extern void set_GPIO_IRQ_edge( int gpio_nr, int edge_mask );
+
+/*
+ * Handy routine to set GPIO alternate functions
+ */
+extern void set_GPIO_mode( int gpio_mode );
+
+/*
+ * return current lclk frequency in units of 10kHz
+ */
+extern unsigned int get_lclk_frequency_10khz(void);
+
+#endif
+
+
+/*
+ * Implementation specifics
+ */
+
+#ifdef CONFIG_ARCH_LUBBOCK
+#include "lubbock.h"
+#endif
+
+#ifdef CONFIG_ARCH_PXA_IDP
+#include "idp.h"
+#endif
+
+#ifdef CONFIG_ARCH_PXA_CERF
+#include "cerf.h"
+#endif
+
+#ifdef CONFIG_ARCH_CSB226
+#include "csb226.h"
+#endif
+
+#ifdef CONFIG_ARCH_INNOKOM
+#include "innokom.h"
+#endif
+
+#endif  /* _ASM_ARCH_HARDWARE_H */
--- a/include/asm-arm/global_data.h
+++ b/include/asm-arm/global_data.h
@@ -44,7 +44,6 @@ typedef	struct	global_data {
 #ifdef CONFIG_VFD
 	unsigned long	fb_base;	/* base address of frame buffer */
 	unsigned char	vfd_type;	/* display type */
-	unsigned char	vfd_inv_data;	/* inverted data lines ? */
 #endif
 #if 0
 	unsigned long	cpu_clk;	/* CPU clock in Hz!		*/
--- a/include/asm-arm/io.h
+++ b/include/asm-arm/io.h
@@ -71,22 +71,37 @@ extern void __raw_readsl(unsigned int addr, void *data, int longlen);
 #include <asm/arch/io.h>

 /*
- * IO definitions.  We define {out,in,outs,ins}[bwl] if __io is defined
- * by the machine.  Otherwise, these definitions are left for the machine
- * specific header files to pick up.
+ *  IO port access primitives
+ *  -------------------------
+ *
+ * The ARM doesn't have special IO access instructions; all IO is memory
+ * mapped.  Note that these are defined to perform little endian accesses
+ * only.  Their primary purpose is to access PCI and ISA peripherals.
+ *
+ * Note that for a big endian machine, this implies that the following
+ * big endian mode connectivity is in place, as described by numerious
+ * ARM documents:
+ *
+ *    PCI:  D0-D7   D8-D15 D16-D23 D24-D31
+ *    ARM: D24-D31 D16-D23  D8-D15  D0-D7
+ *
+ * The machine specific io.h include defines __io to translate an "IO"
+ * address to a memory address.
 *
 * Note that we prevent GCC re-ordering or caching values in expressions
 * by introducing sequence points into the in*() definitions.  Note that
 * __raw_* do not guarantee this behaviour.
+ *
+ * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
 */
 #ifdef __io
 #define outb(v,p)			__raw_writeb(v,__io(p))
-#define outw(v,p)			__raw_writew(v,__io(p))
-#define outl(v,p)			__raw_writel(v,__io(p))
+#define outw(v,p)			__raw_writew(cpu_to_le16(v),__io(p))
+#define outl(v,p)			__raw_writel(cpu_to_le32(v),__io(p))

-#define inb(p)		({ unsigned int __v = __raw_readb(__io(p)); __v; })
-#define inw(p)		({ unsigned int __v = __raw_readw(__io(p)); __v; })
-#define inl(p)		({ unsigned int __v = __raw_readl(__io(p)); __v; })
+#define inb(p)	({ unsigned int __v = __raw_readb(__io(p)); __v; })
+#define inw(p)	({ unsigned int __v = le16_to_cpu(__raw_readw(__io(p))); __v; })
+#define inl(p)	({ unsigned int __v = le32_to_cpu(__raw_readl(__io(p))); __v; })

 #define outsb(p,d,l)			__raw_writesb(__io(p),d,l)
 #define outsw(p,d,l)			__raw_writesw(__io(p),d,l)
@@ -171,20 +186,20 @@ extern void __readwrite_bug(const char *fn);
 */
 #ifdef __mem_pci

-#define readb(addr) ({ unsigned int __v = __raw_readb(__mem_pci(addr)); __v; })
-#define readw(addr) ({ unsigned int __v = __raw_readw(__mem_pci(addr)); __v; })
-#define readl(addr) ({ unsigned int __v = __raw_readl(__mem_pci(addr)); __v; })
+#define readb(c) ({ unsigned int __v = __raw_readb(__mem_pci(c)); __v; })
+#define readw(c) ({ unsigned int __v = le16_to_cpu(__raw_readw(__mem_pci(c))); __v; })
+#define readl(c) ({ unsigned int __v = le32_to_cpu(__raw_readl(__mem_pci(c))); __v; })

-#define writeb(val,addr)		__raw_writeb(val,__mem_pci(addr))
-#define writew(val,addr)		__raw_writew(val,__mem_pci(addr))
-#define writel(val,addr)		__raw_writel(val,__mem_pci(addr))
+#define writeb(v,c)		__raw_writeb(v,__mem_pci(c))
+#define writew(v,c)		__raw_writew(cpu_to_le16(v),__mem_pci(c))
+#define writel(v,c)		__raw_writel(cpu_to_le32(v),__mem_pci(c))

-#define memset_io(a,b,c)		_memset_io(__mem_pci(a),(b),(c))
-#define memcpy_fromio(a,b,c)		_memcpy_fromio((a),__mem_pci(b),(c))
-#define memcpy_toio(a,b,c)		_memcpy_toio(__mem_pci(a),(b),(c))
+#define memset_io(c,v,l)		_memset_io(__mem_pci(c),(v),(l))
+#define memcpy_fromio(a,c,l)		_memcpy_fromio((a),__mem_pci(c),(l))
+#define memcpy_toio(c,a,l)		_memcpy_toio(__mem_pci(c),(a),(l))

-#define eth_io_copy_and_sum(a,b,c,d) \
-				eth_copy_and_sum((a),__mem_pci(b),(c),(d))
+#define eth_io_copy_and_sum(s,c,l,b) \
+				eth_copy_and_sum((s),__mem_pci(c),(l),(b))

 static inline int
 check_signature(unsigned long io_addr, const unsigned char *signature,
@@ -218,14 +233,6 @@ out:

 #endif	/* __mem_pci */

-/*
- * remap a physical address `phys' of size `size' with page protection `prot'
- * into virtual address `from'
- */
-#define io_remap_page_range(from,phys,size,prot) \
-		remap_page_range(from,phys,size,prot)
-
-
 /*
 * If this architecture has ISA IO, then define the isa_read/isa_write
 * macros.
@@ -245,6 +252,10 @@ out:
 #define isa_eth_io_copy_and_sum(a,b,c,d) \
 				eth_copy_and_sum((a),__mem_isa(b),(c),(d))

+#ifndef PCI_MEMORY_VADDR	/* XXX problem not understood -- wd */
+#define	PCI_MEMORY_VADDR	0
+#endif	/* XXX */
+
 static inline int
 isa_check_signature(unsigned long io_addr, const unsigned char *signature,
 		    int length)
--- a/include/asm-arm/mach-types.h
+++ b/include/asm-arm/mach-types.h
--- a/include/asm-i386/ppcboot-i386.h
+++ b/include/asm-i386/ppcboot-i386.h
@@ -21,8 +21,8 @@
 * MA 02111-1307 USA
 */

-#ifndef _PPCBOOT_I386_H_
-#define _PPCBOOT_I386_H_	1
+#ifndef _U_BOOT_I386_H_
+#define _U_BOOT_I386_H_	1

 /* for the following variables, see start.S */
 extern ulong i386boot_start;	    /* code start (in flash) */
@@ -50,4 +50,4 @@ int	board_init(void);
 int	dram_init (void);


-#endif	/* _PPCBOOT_I386_H_ */
+#endif	/* _U_BOOT_I386_H_ */
--- a/include/cmd_bsp.h
+++ b/include/cmd_bsp.h
@@ -112,7 +112,19 @@ int do_pip405 (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
 int do_mip405 (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);

 #endif /* CONFIG_MIP405 */
-/* --------------------------------------------------------------------	*/
+/* ----- VCMA9 -----------------------------------------------------------------
+ */
+#if defined(CONFIG_VCMA9)
+
+#define	CMD_TBL_BSP MK_CMD_TBL_ENTRY(				\
+	"vcma9",	4,	6,	1,	do_vcma9,	\
+	"vcma9   - VCMA9 specific Cmds\n",			\
+	"flash mem [SrcAddr] - updates U-Boot with image in memory\n"					\
+),
+int do_vcma9 (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+
+#endif /* CONFIG_VCMA9 */
+/* ----------------------------------------------------------------------------*/

 /* ----- DASA_SIM ----------------------------------------------------- */
 #if defined(CONFIG_DASA_SIM)
--- a/include/cmd_console.h
+++ b/include/cmd_console.h
@@ -30,7 +30,7 @@
 #if (CONFIG_COMMANDS & CFG_CMD_CONSOLE)
 #define	CMD_TBL_CONINFO	MK_CMD_TBL_ENTRY(			\
 	"coninfo",	5,	3,	1,	do_coninfo,	\
-	"coninfo - print console devices and informations\n",	\
+	"coninfo - print console devices and information\n",	\
 	""		 		 			\
 ),
 int do_coninfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
--- a/include/common.h
+++ b/include/common.h
@@ -149,7 +149,7 @@ void    setenv       (char *, char *);
 # include <asm/u-boot-arm.h>	/* ARM version to be fixed! */
 #endif /* CONFIG_ARM */
 #ifdef CONFIG_I386		/* x86 version to be fixed! */
-# include <asm/ppcboot-i386.h>  
+# include <asm/u-boot-i386.h>  
 #endif /* CONFIG_I386 */

 void    pci_init      (void);
--- a/include/commproc.h
+++ b/include/commproc.h
@@ -595,6 +595,32 @@ typedef struct scc_enet {

 #endif	/* CONFIG_PCU_E, CONFIG_CCM */

+/***  ELPT860 *********************************************************/
+
+#ifdef CONFIG_ELPT860
+/* Bits in parallel I/O port registers that have to be set/cleared
+ * to configure the pins for SCC1 use.
+ */
+#  define PROFF_ENET        PROFF_SCC1
+#  define CPM_CR_ENET       CPM_CR_CH_SCC1
+#  define SCC_ENET          0
+
+#  define PA_ENET_RXD       ((ushort)0x0001)	/* PA 15 */
+#  define PA_ENET_TXD       ((ushort)0x0002)	/* PA 14 */
+#  define PA_ENET_RCLK      ((ushort)0x0100)	/* PA  7 */
+#  define PA_ENET_TCLK      ((ushort)0x0200)	/* PA  6 */
+
+#  define PC_ENET_TENA      ((ushort)0x0001)	/* PC 15 */
+#  define PC_ENET_CLSN      ((ushort)0x0010)	/* PC 11 */
+#  define PC_ENET_RENA      ((ushort)0x0020)	/* PC 10 */
+
+/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK1) to
+ * SCC1.  Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
+ */
+#  define SICR_ENET_MASK    ((uint)0x000000FF)
+#  define SICR_ENET_CLKRT   ((uint)0x00000025)
+#endif	/* CONFIG_ELPT860 */
+
 /***  ESTEEM 192E  **************************************************/
 #ifdef CONFIG_ESTEEM192E
 /* ESTEEM192E
--- a/include/configs/CPC45.h
+++ b/include/configs/CPC45.h
@@ -0,0 +1,448 @@
+/*
+ * (C) Copyright 2001-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ *
+ * Configuration settings for the CPC45 board.
+ *
+ */
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC824X		1
+#define CONFIG_MPC8245		1
+#define CONFIG_CPC45		1
+
+
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_BAUDRATE		9600
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#define CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz	*/
+
+#define CONFIG_PREBOOT	"echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+
+#define CONFIG_BOOTDELAY	5
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_BEDBUG  | \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_PCI	| \
+				0 /* CFG_CMD_DATE */	)
+
+/* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
+ */
+#include <cmd_confdefs.h>
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+
+#if 1
+#define	CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
+#endif
+#ifdef	CFG_HUSH_PARSER
+#define	CFG_PROMPT_HUSH_PS2	"> "
+#endif
+
+/* Print Buffer Size
+ */
+#define CFG_PBSIZE	(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
+
+#define	CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CFG_LOAD_ADDR	0x00100000	/* Default load address		*/
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+
+#define CFG_SDRAM_BASE	    0x00000000
+
+#if defined(CONFIG_BOOT_ROM)
+#define CFG_FLASH_BASE	    0xFF000000
+#else
+#define CFG_FLASH_BASE	    0xFF800000
+#endif
+
+#define CFG_RESET_ADDRESS   0xFFF00100
+
+#define CFG_EUMB_ADDR	    0xFCE00000
+
+#define CFG_MONITOR_BASE    TEXT_BASE
+
+#define CFG_MONITOR_LEN	    (256 << 10) /* Reserve 256 kB for Monitor	*/
+#define CFG_MALLOC_LEN	    (128 << 10) /* Reserve 128 kB for malloc()	*/
+
+#define CFG_MEMTEST_START   0x00004000	/* memtest works on		*/
+#define CFG_MEMTEST_END	    0x02000000	/* 0 ... 32 MB in DRAM		*/
+
+	/* Maximum amount of RAM.
+	 */
+#define CFG_MAX_RAM_SIZE    0x10000000
+
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#undef CFG_RAMBOOT
+#else
+#define CFG_RAMBOOT
+#endif
+
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area
+ */
+
+	/* Size in bytes reserved for initial data
+	 */
+#define CFG_GBL_DATA_SIZE    128
+
+#define CFG_INIT_RAM_ADDR     0x40000000
+#define CFG_INIT_RAM_END      0x1000
+#define CFG_GBL_DATA_OFFSET  (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+
+/*
+ * NS16550 Configuration
+ */
+#define CFG_NS16550		
+#define CFG_NS16550_SERIAL
+
+#define CFG_NS16550_REG_SIZE	1
+
+#define CFG_NS16550_CLK		get_bus_freq(0)
+
+#define CFG_NS16550_COM1	(CFG_EUMB_ADDR + 0x4500)
+#define CFG_NS16550_COM2	(CFG_EUMB_ADDR + 0x4600)
+#define	DUART_DCR		(CFG_EUMB_ADDR + 0x4511)
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ * For the detail description refer to the MPC8240 user's manual.
+ */
+
+#define CONFIG_SYS_CLK_FREQ  33000000
+#define CFG_HZ		     1000
+/*
+ * SDRAM Configuration Settings
+ * Please note: currently only 64 and 128 MB SDRAM size supported
+ * set CFG_SDRAM_SIZE to 64 or 128
+ * Memory configuration using SPD information stored on the SODIMMs
+ * not yet supported.
+ */
+ 
+#define	CFG_SDRAM_SIZE    64		/* SDRAM size -- 64 or 128 MB supported */
+
+	/* Bit-field values for MCCR1.
+	 */
+#define CFG_ROMNAL	    0
+#define CFG_ROMFAL	    7
+
+#if (CFG_SDRAM_SIZE == 64)			/* 64 MB */
+#define CFG_BANK0_ROW	0			/* SDRAM bank 7-0 row address */
+#elif (CFG_SDRAM_SIZE == 128)			/* 128 MB */
+#define CFG_BANK0_ROW	2			/* SDRAM bank 7-0 row address */
+#else
+#  error "SDRAM size not supported"
+#endif
+#define CFG_BANK1_ROW	0	
+#define CFG_BANK2_ROW	0
+#define CFG_BANK3_ROW	0
+#define CFG_BANK4_ROW	0
+#define CFG_BANK5_ROW	0
+#define CFG_BANK6_ROW	0
+#define CFG_BANK7_ROW	0
+
+	/* Bit-field values for MCCR2.
+	 */
+#define CFG_REFINT	    430	    /* Refresh interval			*/
+
+	/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
+	 */
+#define CFG_BSTOPRE	    192
+
+	/* Bit-field values for MCCR3.
+	 */
+#define CFG_REFREC	    2	    /* Refresh to activate interval	*/
+#define CFG_RDLAT	    3	    /* Data latancy from read command	*/
+
+	/* Bit-field values for MCCR4.
+	 */
+#define CFG_PRETOACT	    2	    /* Precharge to activate interval	*/
+#define CFG_ACTTOPRE	    5	    /* Activate to Precharge interval	*/
+#define CFG_SDMODE_CAS_LAT  2	    /* SDMODE CAS latancy		*/
+#define CFG_SDMODE_WRAP	    0	    /* SDMODE wrap type			*/
+#define CFG_SDMODE_BURSTLEN 2	    /* SDMODE Burst length		*/
+#define CFG_ACTORW	    2
+#define CFG_REGISTERD_TYPE_BUFFER 1
+#define CFG_EXTROM	    1
+#define CFG_REGDIMM	    0
+
+/* Memory bank settings.
+ * Only bits 20-29 are actually used from these vales to set the
+ * start/end addresses. The upper two bits will always be 0, and the lower
+ * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
+ * address. Refer to the MPC8240 book.
+ */
+
+#define CFG_BANK0_START	    0x00000000
+#define CFG_BANK0_END	    (CFG_MAX_RAM_SIZE - 1)
+#define CFG_BANK0_ENABLE    1
+#define CFG_BANK1_START	    0x3ff00000
+#define CFG_BANK1_END	    0x3fffffff
+#define CFG_BANK1_ENABLE    0
+#define CFG_BANK2_START	    0x3ff00000
+#define CFG_BANK2_END	    0x3fffffff
+#define CFG_BANK2_ENABLE    0
+#define CFG_BANK3_START	    0x3ff00000
+#define CFG_BANK3_END	    0x3fffffff
+#define CFG_BANK3_ENABLE    0
+#define CFG_BANK4_START	    0x3ff00000
+#define CFG_BANK4_END	    0x3fffffff
+#define CFG_BANK4_ENABLE    0
+#define CFG_BANK5_START	    0x3ff00000
+#define CFG_BANK5_END	    0x3fffffff
+#define CFG_BANK5_ENABLE    0
+#define CFG_BANK6_START	    0x3ff00000
+#define CFG_BANK6_END	    0x3fffffff
+#define CFG_BANK6_ENABLE    0
+#define CFG_BANK7_START	    0x3ff00000
+#define CFG_BANK7_END	    0x3fffffff
+#define CFG_BANK7_ENABLE    0
+
+#define CFG_ODCR	    0xff
+
+#define CFG_IBAT0L  (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT0U  (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_IBAT1L  (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT1U  (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+
+#define CFG_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CFG_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_IBAT3L  (0xFC000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CFG_IBAT3U  (0xFC000000 | BATU_BL_64M | BATU_VS | BATU_VP)
+
+#define CFG_DBAT0L  CFG_IBAT0L
+#define CFG_DBAT0U  CFG_IBAT0U
+#define CFG_DBAT1L  CFG_IBAT1L
+#define CFG_DBAT1U  CFG_IBAT1U
+#define CFG_DBAT2L  CFG_IBAT2L
+#define CFG_DBAT2U  CFG_IBAT2U
+#define CFG_DBAT3L  CFG_IBAT3L
+#define CFG_DBAT3U  CFG_IBAT3U
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ	    (8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* Max number of flash banks		*/
+#define CFG_MAX_FLASH_SECT	39	/* Max number of sectors in one bank	*/
+#define INTEL_ID_28F160F3T	0x88F388F3	/*  16M = 1M x 16 top boot sector	*/
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+	/* Warining: environment is not EMBEDDED in the ppcboot code.
+	 * It's stored in flash separately.
+	 */
+#define CFG_ENV_IS_IN_FLASH	    1
+
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x7C0000)
+#define CFG_ENV_SIZE		0x4000	/* Size of the Environment		*/
+#define CFG_ENV_OFFSET		0	/* starting right at the beginning	*/
+#define CFG_ENV_SECT_SIZE	0x8000 /* Size of the Environment Sector	*/
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM		0x02	/* Software reboot			*/
+
+
+#define	SRAM_BASE		0x80000000	/* SRAM base address 	*/
+#define	SRAM_END		0x801FFFFF
+
+/*---------------------------------------------------------------------*/
+/* CPC45 Memory Map                                                    */
+/*---------------------------------------------------------------------*/
+#define	SRAM_BASE	0x80000000	/* SRAM base address            */
+#define	ST16552_A_BASE	0x80200000	/* ST16552 channel A		*/
+#define	ST16552_B_BASE	0x80400000	/* ST16552 channel A		*/
+#define	BCSR_BASE	0x80600000	/* board control / status registers */
+#define	DISPLAY_BASE	0x80600040	/* DISPLAY base			*/
+#define	PCMCIA_MEM_BASE	0x81000000	/* PCMCIA memory window base        */
+#define	PCMCIA_IO_BASE	0xFE000000	/* PCMCIA IO window base            */
+
+
+/*---------------------------------------------------------------------*/
+/* CPC45 Control/Status Registers                                      */
+/*---------------------------------------------------------------------*/
+#define	IRQ_ENA_1		*((volatile uchar*)(BCSR_BASE + 0x00))
+#define	IRQ_STAT_1		*((volatile uchar*)(BCSR_BASE + 0x01))
+#define	IRQ_ENA_2		*((volatile uchar*)(BCSR_BASE + 0x02))
+#define	IRQ_STAT_2		*((volatile uchar*)(BCSR_BASE + 0x03))
+#define	BOARD_CTRL		*((volatile uchar*)(BCSR_BASE + 0x04))
+#define	BOARD_STAT		*((volatile uchar*)(BCSR_BASE + 0x05))
+#define	WDG_START		*((volatile uchar*)(BCSR_BASE + 0x06))
+#define	WDG_PRESTOP		*((volatile uchar*)(BCSR_BASE + 0x06))
+#define	WDG_STOP		*((volatile uchar*)(BCSR_BASE + 0x06))
+#define	BOARD_REV		*((volatile uchar*)(BCSR_BASE + 0x07))
+
+/* IRQ_ENA_1 bit definitions */
+#define	I_ENA_1_IERA	0x80		/* INTA enable 			*/
+#define	I_ENA_1_IERB	0x40		/* INTB enable			*/
+#define	I_ENA_1_IERC	0x20		/* INTC enable			*/
+#define	I_ENA_1_IERD	0x10		/* INTD enable			*/
+
+/* IRQ_STAT_1 bit definitions */
+#define	I_STAT_1_INTA	0x80		/* INTA status			*/
+#define	I_STAT_1_INTB	0x40		/* INTB status			*/
+#define	I_STAT_1_INTC	0x20		/* INTC status			*/
+#define	I_STAT_1_INTD	0x10		/* INTD status			*/
+
+/* IRQ_ENA_2 bit definitions */
+#define	I_ENA_2_IEAB	0x80		/* ABORT IRQ enable		*/
+#define	I_ENA_2_IEK1	0x40		/* KEY1 IRQ enable		*/
+#define	I_ENA_2_IEK2	0x20		/* KEY2 IRQ enable		*/ 
+#define	I_ENA_2_IERT	0x10		/* RTC IRQ enable		*/
+#define	I_ENA_2_IESM	0x08		/* LM81 IRQ enable		*/
+#define	I_ENA_2_IEDG	0x04		/* DEGENERATING IRQ enable	*/
+#define	I_ENA_2_IES2	0x02		/* ST16552/B IRQ enable		*/
+#define	I_ENA_2_IES1	0x01		/* ST16552/A IRQ enable		*/
+
+/* IRQ_STAT_2 bit definitions */
+#define	I_STAT_2_ABO	0x80		/* ABORT IRQ status		*/
+#define	I_STAT_2_KY1	0x40		/* KEY1 IRQ status		*/
+#define	I_STAT_2_KY2	0x20		/* KEY2 IRQ status		*/ 
+#define	I_STAT_2_RTC	0x10		/* RTC IRQ status		*/
+#define	I_STAT_2_SMN	0x08		/* LM81 IRQ status		*/ 
+#define	I_STAT_2_DEG	0x04		/* DEGENERATING IRQ status	*/
+#define	I_STAT_2_SIO2	0x02		/* ST16552/B IRQ status		*/
+#define	I_STAT_2_SIO1	0x01		/* ST16552/A IRQ status		*/
+
+/* BOARD_CTRL bit definitions */
+#define	USER_LEDS		2			/* 2 user LEDs	*/
+
+#if (USER_LEDS == 4)
+#define	B_CTRL_WRSE		0x80
+#define	B_CTRL_KRSE		0x40
+#define	B_CTRL_FWRE		0x20		/* Flash write enable		*/
+#define	B_CTRL_FWPT		0x10		/* Flash write protect		*/
+#define	B_CTRL_LED3		0x08		/* LED 3 control		*/
+#define	B_CTRL_LED2		0x04		/* LED 2 control		*/
+#define	B_CTRL_LED1		0x02		/* LED 1 control		*/
+#define	B_CTRL_LED0		0x01		/* LED 0 control		*/
+#else
+#define	B_CTRL_WRSE		0x80
+#define	B_CTRL_KRSE		0x40
+#define	B_CTRL_FWRE_1		0x20		/* Flash write enable		*/
+#define	B_CTRL_FWPT_1		0x10		/* Flash write protect		*/
+#define	B_CTRL_LED1		0x08		/* LED 1 control		*/
+#define	B_CTRL_LED0		0x04		/* LED 0 control		*/
+#define	B_CTRL_FWRE_0		0x02		/* Flash write enable		*/
+#define	B_CTRL_FWPT_0		0x01		/* Flash write protect		*/
+#endif
+
+/* BOARD_STAT bit definitions */
+#define	B_STAT_WDGE		0x80
+#define	B_STAT_WDGS		0x40
+#define	B_STAT_WRST		0x20
+#define	B_STAT_KRST		0x10
+#define	B_STAT_CSW3		0x08		/* sitch bit 3 status		*/
+#define	B_STAT_CSW2		0x04		/* sitch bit 2 status		*/
+#define	B_STAT_CSW1		0x02		/* sitch bit 1 status		*/
+#define	B_STAT_CSW0		0x01		/* sitch bit 0 status		*/
+
+/*---------------------------------------------------------------------*/
+/* Display addresses                                                   */
+/*---------------------------------------------------------------------*/
+#define	DISP_UDC_RAM	(DISPLAY_BASE + 0x08)	/* UDC RAM	       */
+#define	DISP_CHR_RAM	(DISPLAY_BASE + 0x18)	/* character Ram       */
+#define	DISP_FLASH	(DISPLAY_BASE + 0x20)	/* Flash Ram           */
+
+#define	DISP_UDC_ADR	*((volatile uchar*)(DISPLAY_BASE + 0x00))	/* UDC Address Reg.    */
+#define	DISP_CWORD	*((volatile uchar*)(DISPLAY_BASE + 0x10))	/* Control Word Reg.   */
+
+#define	DISP_DIG0	*((volatile uchar*)(DISP_CHR_RAM + 0x00))	/* Digit 0 address     */      
+#define	DISP_DIG1	*((volatile uchar*)(DISP_CHR_RAM + 0x01))	/* Digit 0 address     */      
+#define	DISP_DIG2	*((volatile uchar*)(DISP_CHR_RAM + 0x02))	/* Digit 0 address     */
+#define	DISP_DIG3	*((volatile uchar*)(DISP_CHR_RAM + 0x03))	/* Digit 0 address     */      
+#define	DISP_DIG4	*((volatile uchar*)(DISP_CHR_RAM + 0x04))	/* Digit 0 address     */      
+#define	DISP_DIG5	*((volatile uchar*)(DISP_CHR_RAM + 0x05))	/* Digit 0 address     */
+#define	DISP_DIG6	*((volatile uchar*)(DISP_CHR_RAM + 0x06))	/* Digit 0 address     */      
+#define	DISP_DIG7	*((volatile uchar*)(DISP_CHR_RAM + 0x07))	/* Digit 0 address     */      
+
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_PCI			/* include pci support			*/
+#undef CONFIG_PCI_PNP
+
+#define CONFIG_NET_MULTI		/* Multi ethernet cards support 	*/
+
+#define CONFIG_EEPRO100
+
+#define PCI_ENET0_IOADDR	0x00104000
+#define PCI_ENET0_MEMADDR	0x82000000
+#define	PCI_PLX9030_MEMADDR	0x82100000
+#endif	/* __CONFIG_H */
--- a/include/configs/CPU86.h
+++ b/include/configs/CPU86.h
@@ -171,7 +171,7 @@
 				 CFG_CMD_EEPROM | \
 				 CFG_CMD_DATE	| \
 				 CFG_CMD_I2C	| \
-				 CFG_CMD_DOC)
+				 CFG_CMD_DOC	)

 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
@@ -329,8 +329,8 @@
 #define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
 #define CFG_EEPROM_PAGE_WRITE_BITS	4
 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
-#define CFG_ENV_OFFSET		0
-#define CFG_ENV_SIZE		2048
+#define CFG_ENV_OFFSET		512
+#define CFG_ENV_SIZE		(2048 - 512)
 #endif

 /*
--- a/include/configs/CU824.h
+++ b/include/configs/CU824.h
@@ -60,9 +60,10 @@
 #define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)

 #define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_BEDBUG  | \
 				CFG_CMD_DHCP	| \
 				CFG_CMD_PCI	| \
-				0/* CFG_CMD_DATE */	)
+				0 /* CFG_CMD_DATE */	)

 /* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
 */
@@ -302,4 +303,7 @@
 #define CFG_ETH_DEV_FN	     0x7800
 #define CFG_ETH_IOBASE	     0x00104000

+#define CONFIG_EEPRO100
+#define PCI_ENET0_IOADDR	0x00104000
+#define PCI_ENET0_MEMADDR	0x80000000
 #endif	/* __CONFIG_H */
--- a/include/configs/ELPT860.h
+++ b/include/configs/ELPT860.h
@@ -0,0 +1,390 @@
+/*
+**=====================================================================
+**
+** Copyright (C) 2000, 2001, 2002, 2003
+** The LEOX team <team@leox.org>, http://www.leox.org
+**
+** LEOX.org is about the development of free hardware and software resources
+**   for system on chip.
+**
+** Description: U-Boot port on the LEOX's ELPT860 CPU board
+** ~~~~~~~~~~~
+**
+**=====================================================================
+**
+** This program is free software; you can redistribute it and/or
+** modify it under the terms of the GNU General Public License as
+** published by the Free Software Foundation; either version 2 of
+** the License, or (at your option) any later version.
+**
+** This program is distributed in the hope that it will be useful,
+** but WITHOUT ANY WARRANTY; without even the implied warranty of
+** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+** GNU General Public License for more details.
+**
+** You should have received a copy of the GNU General Public License
+** along with this program; if not, write to the Free Software
+** Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+** MA 02111-1307 USA
+**
+**=====================================================================
+*/
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC860		1	/* It's a MPC860, in fact a 860T CPU */
+#define CONFIG_MPC860T		1
+#define CONFIG_ELPT860		1	/* ...on a LEOX's ELPT860 CPU board */
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		    */
+#undef	  CONFIG_8xx_CONS_SMC2
+#undef	  CONFIG_8xx_CONS_NONE
+
+#define CONFIG_CLOCKS_IN_MHZ    1  /* Clock passed to Linux (<2.4.5) in MHz */
+#define CONFIG_8xx_GCLK_FREQ    50000000       /* MPC860T runs at 50MHz */
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define CONFIG_BOARD_PRE_INIT   1       /* Call board_pre_init          */
+
+/* BOOT arguments */
+#define CONFIG_PREBOOT                                                     \
+     "echo;"	                                                           \
+     "echo Type \"run nfsboot\" to mount root filesystem over NFS;"        \
+     "echo"
+
+#undef	  CONFIG_BOOTARGS	
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+    "ramargs=setenv bootargs root=/dev/ram rw\0"			\
+    "rootargs=setenv rootpath /tftp/$(ipaddr)\0"			\
+    "nfsargs=setenv bootargs root=/dev/nfs rw "				\
+        "nfsroot=$(serverip):$(rootpath)\0"				\
+    "addip=setenv bootargs $(bootargs) "				\
+        "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"		\
+        ":$(hostname):eth0:off panic=1\0"				\
+    "ramboot=tftp 400000 /home/paugaml/pMulti;"				\
+        "run ramargs;bootm\0"						\
+    "nfsboot=tftp 400000 /home/paugaml/uImage;"				\
+        "run rootargs;run nfsargs;run addip;bootm\0"			\
+    ""
+#define CONFIG_BOOTCOMMAND	"run ramboot"
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+#undef	  CONFIG_WATCHDOG		/* watchdog disabled		*/
+#undef	  CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
+#undef	  CONFIG_RTC_MPC8xx		/* internal RTC MPC8xx unused	*/
+#define CONFIG_RTC_DS164x       1       /* RTC is a Dallas DS1646       */
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	  CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#define CONFIG_COMMANDS	        ( CONFIG_CMD_DFL | \
+                                  CFG_CMD_ASKENV | \
+                                  CFG_CMD_DATE   )
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT     "LEOX_elpt860: "	/* Monitor Command Prompt	*/
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#  define CFG_CBSIZE	 256		/* Console I/O Buffer Size	*/
+#endif
+
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS	  16		/* max number of command args	*/
+#define CFG_BARGSIZE	  CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x00400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x00C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CFG_LOAD_ADDR		0x00100000	/* default load address	*/
+
+#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+
+/*
+ * Environment Variables and Storages
+ */
+#define CONFIG_ENV_OVERWRITE    1  /* Allow Overwrite of serial# & ethaddr */
+
+#undef    CFG_ENV_IS_IN_NVRAM          /* Environment is in NVRAM       */
+#undef    CFG_ENV_IS_IN_EEPROM         /* Environment is in I2C EEPROM  */
+#define CFG_ENV_IS_IN_FLASH     1      /* Environment is in FLASH       */
+
+#define CONFIG_BAUDRATE		9600   /* console baudrate = 9600 bps   */
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#define CONFIG_ETHADDR          00:01:77:00:60:40
+#define CONFIG_IPADDR           192.168.0.30
+#define CONFIG_NETMASK          255.255.255.0
+
+#define CONFIG_SERVERIP         192.168.0.1
+#define CONFIG_GATEWAYIP        192.168.0.1
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xFF000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define	CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0x02000000
+#define CFG_NVRAM_BASE          0x03000000
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+#  if defined(DEBUG)
+#    define CFG_MONITOR_LEN	(320 << 10)  /* Reserve 320 kB for Monitor  */
+#  else
+#    define CFG_MONITOR_LEN	(256 << 10)  /* Reserve 256 kB for Monitor  */
+#  endif
+#else
+#  if defined(DEBUG)
+#    define CFG_MONITOR_LEN	(256 << 10)  /* Reserve 256 kB for Monitor  */
+#  else
+#    define CFG_MONITOR_LEN	(192 << 10)  /* Reserve 192 kB for Monitor  */
+#  endif
+#endif
+
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define	CFG_MALLOC_LEN		(128 << 10)  /* Reserve 128 kB for malloc() */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)    /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks        */
+#define CFG_MAX_FLASH_SECT	8	/* max number of sectors on one chip */
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)   */
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)   */
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+#  define CFG_ENV_OFFSET        0x10000	/* Offset   of Environment Sector    */
+#  define CFG_ENV_SIZE          0x10000 /* Total Size of Environment Sector  */
+#endif
+
+/*-----------------------------------------------------------------------
+ * NVRAM organization
+ */
+#define CFG_NVRAM_BASE_ADDR     CFG_NVRAM_BASE /* Base address of NVRAM area */
+#define CFG_NVRAM_SIZE          ((128*1024)-8) /* clock regs resident in the */
+                                               /*   8 top NVRAM locations    */
+
+#if defined(CFG_ENV_IS_IN_NVRAM)
+#  define CFG_ENV_ADDR          CFG_NVRAM_BASE /* Base address of NVRAM area */
+#  define CFG_ENV_SIZE          0x4000	/* Total Size of Environment Sector  */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs               */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CACHELINE_SHIFT	 4      /* log base 2 of the above value     */
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#  define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT  | SYPCR_BME | SYPCR_SWF | \
+                         SYPCR_SWE  | SYPCR_SWRI | SYPCR_SWP)
+#else
+#  define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT  | SYPCR_BME | SYPCR_SWF | \
+                                                   SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#define CFG_SIUMCR	(SIUMCR_DBGC11)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ * Once-per-Second Interrupt, Alarm Interrupt, RTC freezing enabled, RTC
+ *  enabled
+ */
+#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit - leave PLL multiplication factor unchanged !
+ */
+#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	 SCCR_EBDF11
+#define CFG_SCCR	(SCCR_TBS     | \
+			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+
+/*-----------------------------------------------------------------------
+ * Chip Selects + SDRAM timings + Memory Periodic Timer Prescaler
+ *-----------------------------------------------------------------------
+ *
+ */
+#ifdef DEBUG
+#  define CFG_DER		0xFFE7400F	/* Debug Enable Register */
+#else
+#  define CFG_DER		0
+#endif
+
+/*
+ * Init Memory Controller:
+ * ~~~~~~~~~~~~~~~~~~~~~~
+ *
+ * BR0 and OR0 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	CFG_FLASH_BASE	/* FLASH bank #0          */
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CFG_PRELIM_OR_AM	0xFF000000	/* 16 MB between each CSx */
+
+/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 0, SCY = 8, EHTR = 0	  */
+#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV2 | OR_BI | OR_SCY_8_CLK)
+
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
+
+/*
+ * BR1 and OR1 (SDRAM)
+ *
+ */
+#define SDRAM_BASE1_PRELIM	CFG_SDRAM_BASE	/* SDRAM bank #0        */
+#define	SDRAM_MAX_SIZE		0x02000000	/* 32 MB MAX for CS1    */
+
+/* SDRAM timing:                                                        */
+#define CFG_OR_TIMING_SDRAM	0x00000000
+
+#define CFG_OR1_PRELIM	((2 * CFG_PRELIM_OR_AM) | CFG_OR_TIMING_SDRAM )
+#define CFG_BR1_PRELIM	((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+/*
+ * BR2 and OR2 (NVRAM)
+ *
+ */
+#define NVRAM_BASE1_PRELIM	CFG_NVRAM_BASE	/* NVRAM bank #0        */
+#define	NVRAM_MAX_SIZE		0x00020000	/* 128 KB MAX for CS2   */
+
+#define CFG_OR2_PRELIM	        0xFFF80160
+#define CFG_BR2_PRELIM	((NVRAM_BASE1_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
+
+/*
+ * Memory Periodic Timer Prescaler
+ */
+
+/* periodic timer for refresh */
+#define CFG_MAMR_PTA	        97     /* start with divider for 100 MHz */
+
+/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
+#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16	  /* setting for 2 banks */
+#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32	  /* setting for 1 bank  */
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit  */
+#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8    /* setting for 2 banks */
+#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16   /* setting for 1 bank  */
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    | \
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    | \
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+/*-----------------------------------------------------------------------
+ * Internal Definitions
+ *-----------------------------------------------------------------------
+ *
+ */
+
+/*
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD	0x01             /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02             /* Software reboot                  */
+
+
+#endif	/* __CONFIG_H */
--- a/include/configs/IP860.h
+++ b/include/configs/IP860.h
@@ -35,6 +35,7 @@

 #define CONFIG_MPC860		1	/* This is a MPC860 CPU		*/
 #define CONFIG_IP860		1	/* ...on a IP860 board		*/
+#define CONFIG_BOARD_PRE_INIT	1	    /* Call board_pre_init	*/

 #define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
 #define CONFIG_BAUDRATE		9600
@@ -45,10 +46,6 @@
 #define CONFIG_PREBOOT	"echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" \
 "\0load=tftp \"/tftpboot/u-boot.bin\"\0update=protect off 1:0;era 1:0;cp.b 100000 10000000 $(filesize)\0"

-#define CONFIG_ETHADDR	00:30:bf:01:02:d2
-#define CONFIG_IPADDR	10.0.0.5
-#define CONFIG_SERVERIP	10.0.0.2
-
 #undef	CONFIG_BOOTARGS
 #define CONFIG_BOOTCOMMAND							\
 	"bootp; "								\
@@ -230,10 +227,13 @@
 			 SIUMCR_DBGC11 | SIUMCR_MLRC10)

 /*-----------------------------------------------------------------------
- * Clock Setting - the IP860 has no 32kHz clock, so automatic detection fails
+ * Clock Setting - get clock frequency from Board Revision Register 
 *-----------------------------------------------------------------------
 */
-#define	CONFIG_8xx_GCLK_FREQ	50000000
+#ifndef __ASSEMBLY__
+extern  unsigned long           ip860_get_clk_freq (void);
+#endif
+#define	CONFIG_8xx_GCLK_FREQ	ip860_get_clk_freq()

 /*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control				11-26
@@ -430,6 +430,8 @@ typedef	struct ip860_bcsr_s {
 	unsigned char	wd_trigger;	/* +1A Watchdog trigger register	*/
 	unsigned char	reservedD;
 	unsigned char	rmw_req;	/* +1C RMW request register		*/
+	unsigned char	reservedE;
+	unsigned char	bd_rev;		/* +1E Board Revision register		*/
 } ip860_bcsr_t;
 #endif	/* __ASSEMBLY__ */

--- a/include/configs/PM826.h
+++ b/include/configs/PM826.h
@@ -158,9 +158,9 @@
 #define CONFIG_COMMANDS		(CONFIG_CMD_DFL	| \
 				 CFG_CMD_BEDBUG	| \
 				 CFG_CMD_DATE	| \
+				 CFG_CMD_DOC	| \
 				 CFG_CMD_EEPROM | \
-				 CFG_CMD_I2C	| \
-				 CFG_CMD_DOC)
+				 CFG_CMD_I2C	)

 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
@@ -211,11 +211,11 @@
 * Flash and Boot ROM mapping
 */

-#define	CFG_BOOTROM_BASE	0x60000000
+#define	CFG_BOOTROM_BASE	0xFF800000
 #define	CFG_BOOTROM_SIZE	0x00080000
-#define	CFG_FLASH0_BASE		0x40000000
+#define	CFG_FLASH0_BASE		0xFF000000
 #define	CFG_FLASH0_SIZE		0x02000000
-#define CFG_DOC_BASE		0x60000000
+#define CFG_DOC_BASE		0xFF800000
 #define CFG_DOC_SIZE		0x00100000


@@ -245,8 +245,8 @@
 #define CFG_I2C_EEPROM_ADDR_LEN	1
 #define CFG_EEPROM_PAGE_WRITE_BITS	4
 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
-#define CFG_ENV_OFFSET		0
-#define CFG_ENV_SIZE		2048
+#define CFG_ENV_OFFSET		512
+#define CFG_ENV_SIZE		(2048 - 512)
 #endif

 /*-----------------------------------------------------------------------
--- a/include/configs/PN62.h
+++ b/include/configs/PN62.h
@@ -70,7 +70,7 @@
 			"root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
 			"ip=$(ipaddr):$(serverip)::$(netmask):pn62:eth0:off;" \
 			"loadp 100000; bootm"
-			/* "tftpboot 100000 pImage; bootm" */
+			/* "tftpboot 100000 uImage; bootm" */
 #else
 /* Boot Linux with RAMdisk based filesystem (initrd, BusyBox) */
 #define CONFIG_BOOTCOMMAND \
--- a/include/configs/RRvision.h
+++ b/include/configs/RRvision.h
@@ -75,7 +75,7 @@
 		"setenv filesize;saveenv\0"				\
 	"kernel_addr=40040000\0"					\
 	"ramdisk_addr=40100000\0"					\
-	"kernel_img=/tftpboot/pImage\0"					\
+	"kernel_img=/tftpboot/uImage\0"					\
 	"kernel_load=tftp 200000 $(kernel_img)\0"			\
 	"net_nfs=run kernel_load nfsargs addip addtty;bootm\0"		\
 	"flash_nfs=run nfsargs addip addtty;bootm $(kernel_addr)\0"	\
--- a/include/configs/SPD823TS.h
+++ b/include/configs/SPD823TS.h
@@ -74,7 +74,7 @@
 #define CONFIG_IPADDR		10.0.0.98
 #define CONFIG_SERVERIP		10.0.0.1
 #undef	CONFIG_BOOTCOMMAND
-#define CONFIG_BOOTCOMMAND	"tftp 200000 pImage;bootm 200000"
+#define CONFIG_BOOTCOMMAND	"tftp 200000 uImage;bootm 200000"
 /*----------------------------------------------------------------------*/

 /*
--- a/include/configs/TQM823L.h
+++ b/include/configs/TQM823L.h
@@ -71,7 +71,7 @@
 		"bootm $(kernel_addr) $(ramdisk_addr)\0"		\
 	"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0"	\
 	"rootpath=/opt/eldk/ppc_8xx\0"					\
-	"bootfile=/tftpboot/TQM860L/pImage\0"				\
+	"bootfile=/tftpboot/TQM860L/uImage\0"				\
 	"kernel_addr=40040000\0"					\
 	"ramdisk_addr=40100000\0"					\
 	""
--- a/Show More
+++ b/Show More
Author	SHA1	Message	Date
wdenk	1957dd29d9	Add files that were forgotten	2003-03-14 21:34:25 +00:00
wdenk	06d01dbe00	* Avoid flicker on the TRAB's VFD by synchronizing the enable with the HSYNC/VSYNC. Requires new CPLD code (Version 101 for Rev. 100 boards, version 153 for Rev. 200 boards). * Patch by Vladimir Gurevich, 12 Mar 2003: Fix relocation problem of statically initialized string pointers in common/cmd_pci.c * Patch by Kai-Uwe Bl�m, 12 Mar 2003: Cleanup & bug fixes for JFFS2 code: - the memory mangement was broken. It caused havoc on malloc by writing beyond the block boundaries. - the length calculation for files was wrong, sometimes resulting in short file reads. - data copying now optionally takes fragment version numbers into account, to avoid copying from older data. See doc/README.JFFS2 for details.	2003-03-14 20:47:52 +00:00
wdenk	09127c6096	Cleanup compiler warning	2003-03-12 10:43:01 +00:00
wdenk	3bac351370	* Patch by Josef Wagner, 12 Mar 2003: - 16/32 MB and 50/80 MHz support with auto-detection for IP860 - ETH05 and BEDBUG support for CU824 - added support for MicroSys CPC45 - new BOOTROM/FLASH0 and DOC base for PM826 * Patch by Robert Schwebel, 12 Mar 2003: Fix the chpart command on innokom board * Name cleanup: mv include/asm-i386/ppcboot-i386.h include/asm-i386/u-boot-i386.h s/PPCBoot/U-Boot/ in some files s/pImage/uImage/ in some files * Patch by Detlev Zundel, 15 Jan 2003: Fix '' command line quoting * Patch by The LEOX team, 19 Jan 2003: - add support for the ELPT860 board - add support for Dallas ds164x RTC	2003-03-12 10:41:04 +00:00
wdenk	1cb8e980c4	* Patches by David M�ller, 31 Jan 2003: - minimal setup for CardBus bridges - add EEPROM read/write support in the CS8900 driver - add support for the builtin I2C controller in the Samsung s3c24x0 chips - add support for MPL's VCMA9 (Samsung s3c2410 based) board * Patch by Steven Scholz, 04 Feb 2003: add support for RTC DS1307 * Patch by Reinhard Meyer, 5 Feb 2003: fix PLPRCR/SCCR init sequence on 8xx to allow for changes of EBDF by software * Patch by Vladimir Gurevich, 07 Feb 2003: "API-compatibility patch" for 4xx I2C driver	2003-03-06 21:55:29 +00:00
wdenk	500545cc6b	Fix problem with default #defines Cleanup compiler warning	2003-03-06 14:23:06 +00:00
wdenk	47cd00fa70	* Patches by Robert Schwebel, 06 Mar 2003: - fix bug in BOOTP code (must use NetCopyIP) - update of CSB226 port - clear BSS segment on XScale - added support for i2c_init_board() function - update to the Innokom plattform * Extend support for redundand environments for configurations where environment size < sector size	2003-03-06 13:39:27 +00:00
				`@@ -0,0 +1 @@`
				`This file is just to ensure that the directory is created.`