* Patch by David Updegraff, 22 Apr 2003:

update for CrayL1 board

* Patch by Pantelis Antoniou, 21 Apr 2003:
  add boot support for ARTOS (a proprietary OS)

* Patch by Steven Scholz, 11 Apr 2003:
  Add support for RTC DS1338

* Patch by Rod Boyce, 24 Jan 2003:
  Fix counting of extended partitions in diskboot command

CHANGELOG

@@ -1,7 +1,75 @@
 ======================================================================
-Changes since U-Boot 0.3.0:
+Changes since U-Boot 0.3.1:
 ======================================================================
 
+* Patch by David Updegraff, 22 Apr 2003:
+  update for CrayL1 board
+
+* Patch by Pantelis Antoniou, 21 Apr 2003:
+  add boot support for ARTOS (a proprietary OS)
+
+* Patch by Steven Scholz, 11 Apr 2003:
+  Add support for RTC DS1338
+
+* Patch by Rod Boyce, 24 Jan 2003:
+  Fix counting of extended partitions in diskboot command
+
+* Patch by Christophe Lindheimer, 20 May 2003:
+  allow the use of CFG_LOADS when CFG_NO_FLASH is set
+
+* Fix SDRAM timing on Purple board
+
+* Add support for CompactFlash on ATC board
+  (includes support for Intel 82365 and compatible PC Card controllers,
+  and Yenta-compatible PCI-to-CardBus controllers)
+
+* Patch by Mathijs Haarman, 08 May 2003:
+  Add lan91c96 driver (tested on Lubbock and custom PXA250 board only)
+
+* Fix problem with usage of "true" (undefined in current versions of bfd.h)
+
+* Add support for Promess ATC board
+
+* Patch by Keith Outwater, 28 Apr 2003:
+  - Miscellaneous corrections and additions to GEN860T board specific code.
+  - Added GEN860_SC variant to GEN860T.
+  - Miscellaneous corrections to GEN860T documentation.
+  - Correct duplicate entry in U-Boot CREDITS file.
+  - Add GEN860T_SC entry in MAINTAINERS file.
+  - Update CREDITS file with GEN860T_SC info.
+
+* Update Smiths Aerospace addresses in MAINTAINERS file
+
+* Fix error handling in hush's version of "run" command
+
+* LWMON extensions:
+  - Splashscreen support
+  - modem support
+  - sysmon support
+  - temperature dependend enabling of LCD
+
+* Allow booting from old "PPCBoot" disk partitions
+
+* Add support for TQM8255 Board / MPC8255 CPU
+
+======================================================================
+Changes for U-Boot 0.3.1:
+======================================================================
+
+* Make sure Block Lock Bits get cleared in R360MPI flash driver
+
+* MPC823 LCD driver: Fill color map backwards, to allow for steady
+  display when Linux takes over
+
+* Patch by Erwin Rol, 27 Feb 2003:
+  Add support for RTEMS (this time for real).
+
+* Add support for "bmp info" and "bmp display" commands to load
+  bitmap images; this can be used (for example in a "preboot"
+  command) to display a splash screen very quickly after poweron.
+
+* Add support for 133 MHz clock on INCA-IP board
+
 * Patch by Lutz Dennig, 10 Apr 2003:
   Update for R360MPI board
 

CREDITS

@@ -26,6 +26,10 @@ N: Guillaume Alexandre
 E: guillaume.alexandre@gespac.ch
 D: Add PCIPPC6 configuration
 
+N: Pantelis Antoniou
+E: panto@intracom.gr
+D: NETVIA board support, ARTOS support.
+
 N: Pierre Aubert
 E: <p.aubert@staubli.com>
 D: Support for RPXClassic board
@@ -212,13 +216,9 @@ E: rof@sysgo.de
 D: Initial support for SSV-DNP1110, SMC91111 driver
 W: www.elinos.com
 
-N: Keith Outwater
-E: Keith_Outwater@mvis.com
-D: Support for GEN860T board
-
 N: Keith Outwater
 E: keith_outwater@mvis.com
-D: Support for generic/custom MPC860T board (GEN860T)
+D: Support for generic/custom MPC860T boards (GEN860T, GEN860T_SC)
 
 N: Frank Panno
 E: fpanno@delphintech.com
@@ -238,6 +238,10 @@ N: Stefan Roese
 E: stefan.roese@esd-electronics.com
 D: IBM PPC401/403/405GP Support; Windows environment support
 
+N: Erwin Rol
+E: erwin@muffin.org
+D: boot support for RTEMS
+
 N: Neil Russell
 E: caret@c-side.com
 D: Author of LiMon-1.4.2, which contributed some ideas

MAINTAINERS

@@ -28,7 +28,7 @@ Pantelis Antoniou <panto@intracom.gr>
 
 	NETVIA			MPC8xx
 
-Jerry Van Baren <vanbaren_gerald@si.com>
+Jerry Van Baren <gerald.vanbaren@smiths-aerospace.com>
 
 	sacsng			MPC8260
 
@@ -80,6 +80,11 @@ Wolfgang Denk <wd@denx.de>
 	CU824			MPC8240
 	Sandpoint8240		MPC8240
 
+	ATC			MPC8250
+	PM825			MPC8250
+
+	TQM8255			MPC8255
+
 	CPU86			MPC8260
 	PM826			MPC8260
 	TQM8260			MPC8260
@@ -87,7 +92,7 @@ Wolfgang Denk <wd@denx.de>
 	PCIPPC2			MPC750
 	PCIPPC6			MPC750
 
-Jon Diekema <diekema_jon@si.com>
+Jon Diekema <jon.diekema@smiths-aerospace.com>
 
 	sbc8260			MPC8260
 
@@ -160,6 +165,7 @@ Scott McNutt <smcnutt@artesyncp.com>
 Keith Outwater <Keith_Outwater@mvis.com>
 
 	GEN860T			MPC860T
+	GEN860T_SC		MPC860T
 
 Frank Panno <fpanno@delphintech.com>
 

MAKEALL

@@ -26,16 +26,16 @@ LIST_8xx="	\
 	ADS860		AMX860		c2mon		CCM		\
 	cogent_mpc8xx	ESTEEM192E	ETX094		ELPT860		\
 	FADS823		FADS850SAR	FADS860T	FLAGADM		\
-	FPS850L		GEN860T		GENIETV		GTH		\
-	hermes		IAD210		ICU862_100MHz	IP860		\
-	IVML24		IVML24_128	IVML24_256	IVMS8		\
-	IVMS8_128	IVMS8_256	KUP4K           LANTEC	        \
-	lwmon   	MBX		MBX860T		MHPC		\
-	MVS1		NETVIA		NX823		pcu_e		\
-	R360MPI		RPXClassic	RPXlite		RRvision	\
-	SM850		SPD823TS	svm_sc8xx	SXNI855T	\
-	TOP860		TQM823L		TQM823L_LCD	TQM850L		\
-	TQM855L		TQM860L		TQM860L_FEC	TTTech		\
+	FPS850L		GEN860T		GEN860T_SC	GENIETV		\
+	GTH		hermes		IAD210		ICU862_100MHz	\
+	IP860		IVML24		IVML24_128	IVML24_256	\
+	IVMS8		IVMS8_128	IVMS8_256	KUP4K           \
+	LANTEC	        lwmon   	MBX		MBX860T		\
+	MHPC		MVS1		NETVIA		NX823		\
+	pcu_e		R360MPI		RPXClassic	RPXlite		\
+	RRvision	SM850		SPD823TS	svm_sc8xx	\
+	SXNI855T	TOP860		TQM823L		TQM823L_LCD	\
+	TQM850L		TQM855L		TQM860L		TTTech		\
 	v37								\
 "
 
@@ -63,14 +63,15 @@ LIST_824x="	\
 "
 
 #########################################################################
-## MPC8260 Systems
+## MPC8260 Systems (includes 8250, 8255 etc.)
 #########################################################################
 
 LIST_8260="	\
-	cogent_mpc8260	CPU86		ep8260		gw8260		\
-	hymod		IPHASE4539	MPC8260ADS	MPC8266ADS	\
-	PM826		ppmc8260	RPXsuper	rsdproto	\
-	sacsng		sbc8260		SCM		TQM8260		\
+	atc		cogent_mpc8260	CPU86		ep8260		\
+	gw8260		hymod		IPHASE4539	MPC8260ADS	\
+	MPC8266ADS	PM826		ppmc8260	RPXsuper	\
+	rsdproto	sacsng		sbc8260		SCM		\
+	TQM8260								\
 "
 
 #########################################################################

Makefile

@@ -212,8 +212,16 @@ FADS860T_config:	unconfig
 FLAGADM_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx flagadm
 
+xtract_GEN860T = $(subst _SC,,$(subst _config,,$1))
+
+GEN860T_SC_config	\
 GEN860T_config: unconfig
-	@./mkconfig $(@:_config=) ppc mpc8xx gen860t
+	@ >include/config.h
+	@[ -z "$(findstring _SC,$@)" ] || \
+		{ echo "#define CONFIG_SC" >>include/config.h ; \
+		  echo "With reduced H/W feature set (SC)..." ; \
+		}
+	@./mkconfig -a $(call xtract_GEN860T,$@) ppc mpc8xx gen860t
 
 GENIETV_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx genietv
@@ -337,7 +345,7 @@ TOP860_config:		unconfig
 # All boards can come with 50 MHz (default), 66MHz or 80MHz clock,
 # but only 855 and 860 boards may come with FEC
 # and 823 boards may have LCD support
-xtract_8xx = $(subst _66MHz,,$(subst _80MHz,,$(subst _LCD,,$(subst _FEC,,$(subst _config,,$1)))))
+xtract_8xx = $(subst _66MHz,,$(subst _80MHz,,$(subst _LCD,,$(subst _config,,$1))))
 
 FPS850L_config		\
 FPS860L_config		\
@@ -360,10 +368,6 @@ TQM862L_config		\
 TQM862L_66MHz_config	\
 TQM862L_80MHz_config:	unconfig
 	@ >include/config.h
-	@[ -z "$(findstring _FEC,$@)" ] || \
-		{ echo "#define CONFIG_FEC_ENET"	>>include/config.h ; \
-		  echo "... with FEC support" ; \
-		}
 	@[ -z "$(findstring _66MHz,$@)" ] || \
 		{ echo "#define CONFIG_66MHz"		>>include/config.h ; \
 		  echo "... with 66MHz system clock" ; \
@@ -579,10 +583,13 @@ sbc8260_config:	unconfig
 SCM_config:		unconfig
 	@./mkconfig $(@:_config=) ppc mpc8260 SCM siemens
 
+TQM8255_config	\
 TQM8260_config	\
 TQM8260_L2_config	\
+TQM8255_266MHz_config	\
 TQM8260_266MHz_config	\
 TQM8260_L2_266MHz_config \
+TQM8255_300MHz_config	\
 TQM8260_300MHz_config:	unconfig
 	@ >include/config.h
 	@if [ "$(findstring _L2_,$@)" ] ; then \
@@ -600,7 +607,12 @@ TQM8260_300MHz_config:	unconfig
 		{ echo "#define CONFIG_300MHz"	>>include/config.h ; \
 		  echo "... with 300MHz system clock" ; \
 		}
-	@./mkconfig -a $(call xtract_82xx,$@) ppc mpc8260 tqm8260
+	@[ -z "$(findstring TQM8255_,$@)" ] || \
+		{ echo "#define CONFIG_MPC8255"	>>include/config.h ; }
+	@./mkconfig -a TQM8260 ppc mpc8260 tqm8260
+
+atc_config:	unconfig
+	@./mkconfig $(@:_config=) ppc mpc8260 atc
 
 #########################################################################
 ## 74xx/7xx Systems
@@ -735,6 +747,7 @@ clean:
 	rm -f tools/easylogo/easylogo tools/bmp_logo
 	rm -f tools/gdb/astest tools/gdb/gdbcont tools/gdb/gdbsend
 	rm -f tools/env/fw_printenv tools/env/fw_setenv
+	rm -f board/cray/L1/bootscript.c board/cray/L1/bootscript.image
 
 clobber:	clean
 	find . -type f \

README

@@ -180,7 +180,7 @@ Directory Hierarchy:
 		Files specific to EVB64260   boards
 - board/fads	Files specific to FADS	     boards
 - board/flagadm Files specific to FLAGADM    boards
-- board/gen860t Files specific to GEN860T    boards
+- board/gen860t Files specific to GEN860T and GEN860T_SC    boards
 - board/genietv Files specific to GENIETV    boards
 - board/gth	Files specific to GTH	     boards
 - board/hermes	Files specific to HERMES     boards
@@ -343,7 +343,8 @@ The following options need to be configured:
 		CONFIG_GTH,        CONFIG_RPXClassic, CONFIG_rsdproto,
 		CONFIG_IAD210,     CONFIG_RPXlite,    CONFIG_sbc8260,
 		CONFIG_EBONY,      CONFIG_sacsng,     CONFIG_FPS860L,
-		CONFIG_V37,        CONFIG_ELPT860,    CONFIG_CMI
+		CONFIG_V37,        CONFIG_ELPT860,    CONFIG_CMI,
+		CONFIG_NETVIA
 
 		ARM based boards:
 		-----------------
@@ -638,6 +639,7 @@ The following options need to be configured:
 		CONFIG_RTC_MC146818	- use MC146818 RTC
 		CONFIG_RTC_DS1307	- use Maxim, Inc. DS1307 RTC
 		CONFIG_RTC_DS1337	- use Maxim, Inc. DS1337 RTC
+		CONFIG_RTC_DS1338	- use Maxim, Inc. DS1338 RTC
 		CONFIG_RTC_DS164x	- use Dallas DS164x RTC
 
 - Timestamp Support:
@@ -695,6 +697,18 @@ The following options need to be configured:
 		CONFIG_NS8382X
 		Support for National dp8382[01] gigabit chips.
 
+- NETWORK Support (other):
+
+		CONFIG_DRIVER_LAN91C96
+		Support for SMSC's LAN91C96 chips.
+
+			CONFIG_LAN91C96_BASE
+			Define this to hold the physical address
+			of the LAN91C96's I/O space
+
+			CONFIG_LAN91C96_USE_32_BIT
+			Define this to enable 32 bit addressing
+
 - USB Support:
 		At the moment only the UHCI host controller is
 		supported (PIP405, MIP405); define
@@ -789,6 +803,18 @@ The following options need to be configured:
 		Normally display is black on white background; define
 		CFG_WHITE_ON_BLACK to get it inverted.
 
+- Spash Screen Support: CONFIG_SPLASH_SCREEN
+
+                If this option is set, the environment is checked for
+                a variable "splashimage". If found, the usual display
+                of logo, copyright and system information on the LCD
+                is supressed and the BMP image at the address
+                specified in "splashimage" is loaded instead. The
+                console is redirected to the "nulldev", too. This
+                allows for a "silent" boot where a splash screen is
+                loaded very quickly after power-on.
+
+
 - Ethernet address:
 		CONFIG_ETHADDR
 		CONFIG_ETH2ADDR
@@ -1726,7 +1752,7 @@ configurations; the following names are supported:
     FPS850L_config	  Sandpoint8240_config	sbc8260_config
     GENIETV_config	  TQM823L_config	PIP405_config
     GEN860T_config	  EBONY_config		FPS860L_config
-    ELPT860_config	  cmi_mpc5xx_config
+    ELPT860_config	  cmi_mpc5xx_config	NETVIA_config
 
 Note: for some board special configuration names may exist; check  if
       additional  information is available from the board vendor; for
@@ -2042,8 +2068,8 @@ defines the following image properties:
 
 * Target Operating System (Provisions for OpenBSD, NetBSD, FreeBSD,
   4.4BSD, Linux, SVR4, Esix, Solaris, Irix, SCO, Dell, NCR, VxWorks,
-  LynxOS, pSOS, QNX;
-  Currently supported: Linux, NetBSD, VxWorks, QNX).
+  LynxOS, pSOS, QNX, RTEMS, ARTOS;
+  Currently supported: Linux, NetBSD, VxWorks, QNX, RTEMS, ARTOS).
 * Target CPU Architecture (Provisions for Alpha, ARM, Intel x86,
   IA64, MIPS, MIPS, PowerPC, IBM S390, SuperH, Sparc, Sparc 64 Bit;
   Currently supported: PowerPC).

board/atc/Makefile

@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $^
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################

board/atc/atc.c

@@ -0,0 +1,378 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc8260.h>
+#include <pci.h>
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A configuration */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PA31 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII COL */
+	/* PA30 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII CRS */
+	/* PA29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC1 MII TX_ER */
+	/* PA28 */ {   1,   1,   1,   1,   0,   0   }, /* FCC1 MII TX_EN */
+	/* PA27 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII RX_DV */
+	/* PA26 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII RX_ER */
+	/* PA25 */ {   1,   0,   0,   1,   0,   0   }, /* FCC2 MII MDIO */
+	/* PA24 */ {   1,   0,   0,   1,   0,   0   }, /* FCC2 MII MDC */
+	/* PA23 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 MII MDIO */
+	/* PA22 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 MII MDC */
+	/* PA21 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[3] */
+	/* PA20 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[2] */
+	/* PA19 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[1] */
+	/* PA18 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[0] */
+	/* PA17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[0] */
+	/* PA16 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[1] */
+	/* PA15 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[2] */
+	/* PA14 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[3] */
+	/* PA13 */ {   1,   0,   0,   1,   0,   0   }, /* FCC2 MII TXSL1 */
+	/* PA12 */ {   1,   0,   0,   1,   0,   1   }, /* FCC2 MII TXSL0 */
+	/* PA11 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 MII TXSL1 */
+	/* PA10 */ {   1,   0,   0,   1,   0,   1   }, /* FCC1 MII TXSL0 */
+#if 1
+	/* PA9  */ {   0,   1,   0,   1,   0,   0   }, /* SMC2 TXD */
+	/* PA8  */ {   0,   1,   0,   0,   0,   0   }, /* SMC2 RXD */
+#else
+	/* PA9  */ {   1,   1,   0,   1,   0,   0   }, /* SMC2 TXD */
+	/* PA8  */ {   1,   1,   0,   0,   0,   0   }, /* SMC2 RXD */
+#endif
+	/* PA7  */ {   0,   0,   0,   0,   0,   0   }, /* PA7 */
+	/* PA6  */ {   1,   0,   0,   1,   0,   1   }, /* FCC2 MII PAUSE */
+	/* PA5  */ {   1,   0,   0,   1,   0,   1   }, /* FCC1 MII PAUSE */
+	/* PA4  */ {   1,   0,   0,   1,   0,   0   }, /* FCC2 MII PWRDN */
+	/* PA3  */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 MII PWRDN */
+	/* PA2  */ {   0,   0,   0,   0,   0,   0   }, /* PA2 */
+	/* PA1  */ {   1,   0,   0,   0,   0,   0   }, /* FCC2 MII MDINT */
+	/* PA0  */ {   1,   0,   0,   1,   0,   0   }  /* FCC1 MII MDINT */
+    },
+
+    /* Port B configuration */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
+	/* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
+	/* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
+	/* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
+	/* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
+	/* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
+	/* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
+	/* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
+	/* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
+	/* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
+	/* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
+	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
+	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
+	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
+	/* PB17 */ {   0,   0,   0,   0,   0,   0   }, /* PB17 */
+	/* PB16 */ {   0,   0,   0,   0,   0,   0   }, /* PB16 */
+	/* PB15 */ {   0,   0,   0,   0,   0,   0   }, /* PB15 */
+	/* PB14 */ {   0,   0,   0,   0,   0,   0   }, /* PB14 */
+	/* PB13 */ {   0,   0,   0,   0,   0,   0   }, /* PB13 */
+	/* PB12 */ {   0,   0,   0,   0,   0,   0   }, /* PB12 */
+	/* PB11 */ {   0,   0,   0,   0,   0,   0   }, /* PB11 */
+	/* PB10 */ {   0,   0,   0,   0,   0,   0   }, /* PB10 */
+	/* PB9  */ {   0,   0,   0,   0,   0,   0   }, /* PB9 */
+	/* PB8  */ {   0,   0,   0,   0,   0,   0   }, /* PB8 */
+	/* PB7  */ {   0,   0,   0,   0,   0,   0   }, /* PB7 */
+	/* PB6  */ {   0,   0,   0,   0,   0,   0   }, /* PB6 */
+	/* PB5  */ {   0,   0,   0,   0,   0,   0   }, /* PB5 */
+	/* PB4  */ {   0,   0,   0,   0,   0,   0   }, /* PB4 */
+	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* PB3 */
+	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* PB2 */
+	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* PB1 */
+	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* PB0 */
+    },
+
+    /* Port C */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PC31 */ {   0,   0,   0,   0,   0,   0   }, /* PC31 */
+	/* PC30 */ {   0,   0,   0,   0,   0,   0   }, /* PC30 */
+	/* PC29 */ {   1,   0,   0,   0,   0,   0   }, /* SCC1 CTS */
+	/* PC28 */ {   1,   0,   0,   0,   0,   0   }, /* SCC2 CTS */
+	/* PC27 */ {   0,   0,   0,   0,   0,   0   }, /* PC27 */
+	/* PC26 */ {   0,   0,   0,   0,   0,   0   }, /* PC26 */
+	/* PC25 */ {   0,   0,   0,   0,   0,   0   }, /* PC25 */
+	/* PC24 */ {   0,   0,   0,   0,   0,   0   }, /* PC24 */
+	/* PC23 */ {   0,   0,   0,   0,   0,   0   }, /* FDC37C78 DACFD */
+	/* PC22 */ {   0,   0,   0,   0,   0,   0   }, /* FDC37C78 DNFD */
+	/* PC21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RX_CLK */
+	/* PC20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII TX_CLK */
+	/* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK */
+	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII TX_CLK */
+	/* PC17 */ {   0,   0,   0,   0,   0,   0   }, /* PC17 */
+	/* PC16 */ {   0,   0,   0,   0,   0,   0   }, /* PC16 */
+#if 0
+	/* PC15 */ {   0,   0,   0,   0,   0,   0   }, /* PC15 */
+#else
+	/* PC15 */ {   1,   1,   0,   1,   0,   0   }, /* PC15 */
+#endif
+	/* PC14 */ {   0,   0,   0,   0,   0,   0   }, /* PC14 */
+	/* PC13 */ {   0,   0,   0,   0,   0,   0   }, /* PC13 */
+	/* PC12 */ {   0,   0,   0,   0,   0,   0   }, /* PC12 */
+	/* PC11 */ {   0,   0,   0,   0,   0,   0   }, /* PC11 */
+	/* PC10 */ {   0,   0,   0,   0,   0,   0   }, /* PC10 */
+	/* PC9  */ {   0,   0,   0,   0,   0,   0   }, /* FC9 */
+	/* PC8  */ {   0,   0,   0,   0,   0,   0   }, /* PC8 */
+	/* PC7  */ {   0,   0,   0,   0,   0,   0   }, /* PC7 */
+	/* PC6  */ {   0,   0,   0,   0,   0,   0   }, /* PC6 */
+	/* PC5  */ {   0,   0,   0,   0,   0,   0   }, /* PC5 */
+	/* PC4  */ {   0,   0,   0,   0,   0,   0   }, /* PC4 */
+	/* PC3  */ {   0,   0,   0,   0,   0,   0   }, /* PC3 */
+	/* PC2  */ {   0,   0,   0,   0,   0,   0   }, /* PC2 */
+	/* PC1  */ {   0,   0,   0,   0,   0,   0   }, /* PC1 */
+	/* PC0  */ {   0,   0,   0,   0,   0,   0   }, /* FDC37C78 DRQFD */
+    },
+
+    /* Port D */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 RXD */
+	/* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 TXD */
+	/* PD29 */ {   1,   0,   0,   1,   0,   0   }, /* SCC1 RTS */
+	/* PD28 */ {   1,   1,   0,   0,   0,   0   }, /* SCC2 RXD */
+	/* PD27 */ {   1,   1,   0,   1,   0,   0   }, /* SCC2 TXD */
+	/* PD26 */ {   1,   0,   0,   1,   0,   0   }, /* SCC2 RTS */
+	/* PD25 */ {   0,   0,   0,   0,   0,   0   }, /* PD25 */
+	/* PD24 */ {   0,   0,   0,   0,   0,   0   }, /* PD24 */
+	/* PD23 */ {   0,   0,   0,   0,   0,   0   }, /* PD23 */
+	/* PD22 */ {   0,   0,   0,   0,   0,   0   }, /* PD22 */
+	/* PD21 */ {   0,   0,   0,   0,   0,   0   }, /* PD21 */
+	/* PD20 */ {   0,   0,   0,   0,   0,   0   }, /* PD20 */
+	/* PD19 */ {   0,   0,   0,   0,   0,   0   }, /* PD19 */
+	/* PD18 */ {   0,   0,   0,   0,   0,   0   }, /* PD18 */
+	/* PD17 */ {   0,   0,   0,   0,   0,   0   }, /* PD17 */
+	/* PD16 */ {   0,   0,   0,   0,   0,   0   }, /* PD16 */
+#if defined(CONFIG_SOFT_I2C)
+	/* PD15 */ {   1,   0,   0,   1,   1,   1   }, /* I2C SDA */
+	/* PD14 */ {   1,   0,   0,   1,   1,   1   }, /* I2C SCL */
+#else
+#if defined(CONFIG_HARD_I2C)
+	/* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
+#else /* normal I/O port pins */
+	/* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
+#endif
+#endif
+	/* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
+	/* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
+	/* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
+	/* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
+	/* PD9  */ {   1,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
+	/* PD8  */ {   1,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
+	/* PD7  */ {   0,   0,   0,   0,   0,   0   }, /* PD7 */
+	/* PD6  */ {   0,   0,   0,   0,   0,   0   }, /* PD6 */
+	/* PD5  */ {   0,   0,   0,   0,   0,   0   }, /* PD5 */
+#if 0
+	/* PD4  */ {   0,   0,   0,   0,   0,   0   }, /* PD4 */
+#else
+	/* PD4  */ {   1,   1,   1,   0,   0,   0   }, /* PD4 */
+#endif
+	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* PD3 */
+	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* PD2 */
+	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* PD1 */
+	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* PD0 */
+    }
+};
+
+/* ------------------------------------------------------------------------- */
+
+/* Check Board Identity:
+ */
+int checkboard (void)
+{
+	printf ("Board: ATC\n");
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
+ *
+ * This routine performs standard 8260 initialization sequence
+ * and calculates the available memory size. It may be called
+ * several times to try different SDRAM configurations on both
+ * 60x and local buses.
+ */
+static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
+			  ulong orx, volatile uchar * base)
+{
+	volatile uchar c = 0xff;
+	ulong cnt, val;
+	volatile ulong *addr;
+	volatile uint *sdmr_ptr;
+	volatile uint *orx_ptr;
+	int i;
+	ulong save[32];		/* to make test non-destructive */
+	ulong maxsize;
+
+	/* We must be able to test a location outsize the maximum legal size
+	 * to find out THAT we are outside; but this address still has to be
+	 * mapped by the controller. That means, that the initial mapping has
+	 * to be (at least) twice as large as the maximum expected size.
+	 */
+	maxsize = (1 + (~orx | 0x7fff)) / 2;
+
+	/* Since CFG_SDRAM_BASE is always 0 (??), we assume that
+	 * we are configuring CS1 if base != 0
+	 */
+	sdmr_ptr = &memctl->memc_psdmr;
+	orx_ptr = &memctl->memc_or2;
+
+	*orx_ptr = orx;
+
+	/*
+	 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
+	 *
+	 * "At system reset, initialization software must set up the
+	 *  programmable parameters in the memory controller banks registers
+	 *  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
+	 *  system software should execute the following initialization sequence
+	 *  for each SDRAM device.
+	 *
+	 *  1. Issue a PRECHARGE-ALL-BANKS command
+	 *  2. Issue eight CBR REFRESH commands
+	 *  3. Issue a MODE-SET command to initialize the mode register
+	 *
+	 *  The initial commands are executed by setting P/LSDMR[OP] and
+	 *  accessing the SDRAM with a single-byte transaction."
+	 *
+	 * The appropriate BRx/ORx registers have already been set when we
+	 * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
+	 */
+
+	*sdmr_ptr = sdmr | PSDMR_OP_PREA;
+	*base = c;
+
+	*sdmr_ptr = sdmr | PSDMR_OP_CBRR;
+	for (i = 0; i < 8; i++)
+		*base = c;
+
+	*sdmr_ptr = sdmr | PSDMR_OP_MRW;
+	*(base + CFG_MRS_OFFS) = c;	/* setting MR on address lines */
+
+	*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
+	*base = c;
+
+	/*
+	 * Check memory range for valid RAM. A simple memory test determines
+	 * the actually available RAM size between addresses `base' and
+	 * `base + maxsize'. Some (not all) hardware errors are detected:
+	 * - short between address lines
+	 * - short between data lines
+	 */
+	i = 0;
+	for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
+		addr = (volatile ulong *) base + cnt;	/* pointer arith! */
+		save[i++] = *addr;
+		*addr = ~cnt;
+	}
+
+	addr = (volatile ulong *) base;
+	save[i] = *addr;
+	*addr = 0;
+
+	if ((val = *addr) != 0) {
+		*addr = save[i];
+		return (0);
+	}
+
+	for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
+		addr = (volatile ulong *) base + cnt;	/* pointer arith! */
+		val = *addr;
+		*addr = save[--i];
+		if (val != ~cnt) {
+			/* Write the actual size to ORx
+			 */
+			*orx_ptr = orx | ~(cnt * sizeof (long) - 1);
+			return (cnt * sizeof (long));
+		}
+	}
+	return (maxsize);
+}
+
+long int initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8260_t *memctl = &immap->im_memctl;
+
+#ifndef CFG_RAMBOOT
+	ulong size8, size9;
+#endif
+	long psize;
+
+	psize = 8 * 1024 * 1024;
+
+	memctl->memc_mptpr = CFG_MPTPR;
+	memctl->memc_psrt = CFG_PSRT;
+
+#ifndef CFG_RAMBOOT
+	/* 60x SDRAM setup:
+	 */
+	size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL,
+			  (uchar *) CFG_SDRAM_BASE);
+	size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR2_9COL,
+			  (uchar *) CFG_SDRAM_BASE);
+
+	if (size8 < size9) {
+		psize = size9;
+		printf ("(60x:9COL) ");
+	} else {
+		psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL,
+				  (uchar *) CFG_SDRAM_BASE);
+		printf ("(60x:8COL) ");
+	}
+
+#endif	/* CFG_RAMBOOT */
+
+	icache_enable ();
+
+	return (psize);
+}
+
+#if (CONFIG_COMMANDS & CFG_CMD_DOC)
+extern void doc_probe (ulong physadr);
+void doc_init (void)
+{
+	doc_probe (CFG_DOC_BASE);
+}
+#endif
+
+#ifdef	CONFIG_PCI
+struct pci_controller hose;
+
+extern void pci_mpc8250_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+	pci_mpc8250_init(&hose);
+}
+#endif

board/atc/config.mk

@@ -0,0 +1,43 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# ATC boards
+#
+
+# This should be equal to the CFG_FLASH_BASE define in config_atc.h
+# for the "final" configuration, with U-Boot in flash, or the address
+# in RAM where U-Boot is loaded at for debugging.
+#
+
+ifeq ($(CONFIG_BOOT_ROM),y)
+	TEXT_BASE := 0xFF800000
+	PLATFORM_CPPFLAGS += -DCONFIG_BOOT_ROM
+else
+	TEXT_BASE := 0xFF000000
+endif
+
+# RAM version
+#TEXT_BASE := 0x100000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)

board/atc/flash.c

@@ -0,0 +1,663 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it
+ *        has nothing to do with the flash chip being 8-bit or 16-bit.
+ */
+#ifdef CONFIG_FLASH_16BIT
+typedef unsigned short FLASH_PORT_WIDTH;
+typedef volatile unsigned short FLASH_PORT_WIDTHV;
+#define	FLASH_ID_MASK	0xFFFF
+#else
+typedef unsigned long FLASH_PORT_WIDTH;
+typedef volatile unsigned long FLASH_PORT_WIDTHV;
+#define	FLASH_ID_MASK	0xFFFFFFFF
+#endif
+
+#define FPW	FLASH_PORT_WIDTH
+#define FPWV	FLASH_PORT_WIDTHV
+
+#define ORMASK(size) ((-size) & OR_AM_MSK)
+
+#define FLASH_CYCLE1	0x0555
+#define FLASH_CYCLE2	0x02aa
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(FPWV *addr, flash_info_t *info);
+static void flash_reset(flash_info_t *info);
+static int write_word_intel(flash_info_t *info, FPWV *dest, FPW data);
+static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data);
+static void flash_get_offsets(ulong base, flash_info_t *info);
+static flash_info_t *flash_get_info(ulong base);
+
+/*-----------------------------------------------------------------------
+ * flash_init()
+ *
+ * sets up flash_info and returns size of FLASH (bytes)
+ */
+unsigned long flash_init (void)
+{
+	unsigned long size = 0;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i < CFG_MAX_FLASH_BANKS; ++i) {
+#if 0
+		ulong flashbase = (i == 0) ? PHYS_FLASH_1 : PHYS_FLASH_2;
+#else
+		ulong flashbase = CFG_FLASH_BASE;
+#endif
+
+		memset(&flash_info[i], 0, sizeof(flash_info_t));
+
+		flash_info[i].size = 
+			flash_get_size((FPW *)flashbase, &flash_info[i]);
+
+		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+			printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx\n",
+			i, flash_info[i].size);
+		}
+		
+		size += flash_info[i].size;
+	}
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_MONITOR_BASE,
+		      CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+		      flash_get_info(CFG_MONITOR_BASE));
+#endif
+
+#ifdef	CFG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_ENV_ADDR,
+		      CFG_ENV_ADDR+CFG_ENV_SIZE-1,
+		      flash_get_info(CFG_ENV_ADDR));
+#endif
+
+
+	return size ? size : 1;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_reset(flash_info_t *info)
+{
+	FPWV *base = (FPWV *)(info->start[0]);
+
+	/* Put FLASH back in read mode */
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
+		*base = (FPW)0x00FF00FF;	/* Intel Read Mode */
+	else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
+		*base = (FPW)0x00F000F0;	/* AMD Read Mode */
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	/* set up sector start address table */
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL
+	    && (info->flash_id & FLASH_BTYPE)) {
+		int bootsect_size;	/* number of bytes/boot sector	*/
+		int sect_size;		/* number of bytes/regular sector */
+
+		bootsect_size = 0x00002000 * (sizeof(FPW)/2);
+		sect_size =     0x00010000 * (sizeof(FPW)/2);
+
+		/* set sector offsets for bottom boot block type	*/
+		for (i = 0; i < 8; ++i) {
+			info->start[i] = base + (i * bootsect_size);
+		}
+		for (i = 8; i < info->sector_count; i++) {
+			info->start[i] = base + ((i - 7) * sect_size);
+		}
+	}
+	else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD
+		 && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U) {
+
+		int sect_size;		/* number of bytes/sector */
+
+		sect_size = 0x00010000 * (sizeof(FPW)/2);
+
+		/* set up sector start address table (uniform sector type) */
+		for( i = 0; i < info->sector_count; i++ )
+			info->start[i] = base + (i * sect_size);
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+static flash_info_t *flash_get_info(ulong base)
+{
+	int i;
+	flash_info_t * info;
+	
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) {
+		info = & flash_info[i];
+		if (info->start[0] <= base && base < info->start[0] + info->size)
+			break;
+	}
+	
+	return i == CFG_MAX_FLASH_BANKS ? 0 : info;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+void flash_print_info (flash_info_t *info)
+{
+	int i;
+	uchar *boottype;
+	uchar *bootletter;
+	uchar *fmt;
+	uchar botbootletter[] = "B";
+	uchar topbootletter[] = "T";
+	uchar botboottype[] = "bottom boot sector";
+	uchar topboottype[] = "top boot sector";
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_BM:	printf ("BRIGHT MICRO ");	break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	case FLASH_MAN_SST:	printf ("SST ");		break;
+	case FLASH_MAN_STM:	printf ("STM ");		break;
+	case FLASH_MAN_INTEL:	printf ("INTEL ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	/* check for top or bottom boot, if it applies */
+	if (info->flash_id & FLASH_BTYPE) {
+		boottype = botboottype;
+		bootletter = botbootletter;
+	}
+	else {
+		boottype = topboottype;
+		bootletter = topbootletter;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM640U:
+		fmt = "29LV641D (64 Mbit, uniform sectors)\n";
+		break;
+        case FLASH_28F800C3B:
+        case FLASH_28F800C3T:
+		fmt = "28F800C3%s (8 Mbit, %s)\n";
+		break;
+	case FLASH_INTEL800B:
+	case FLASH_INTEL800T:
+		fmt = "28F800B3%s (8 Mbit, %s)\n";
+		break;
+        case FLASH_28F160C3B:
+        case FLASH_28F160C3T:
+		fmt = "28F160C3%s (16 Mbit, %s)\n";
+		break;
+	case FLASH_INTEL160B:
+	case FLASH_INTEL160T:
+		fmt = "28F160B3%s (16 Mbit, %s)\n";
+		break;
+        case FLASH_28F320C3B:
+        case FLASH_28F320C3T:
+		fmt = "28F320C3%s (32 Mbit, %s)\n";
+		break;
+	case FLASH_INTEL320B:
+	case FLASH_INTEL320T:
+		fmt = "28F320B3%s (32 Mbit, %s)\n";
+		break;
+        case FLASH_28F640C3B:
+        case FLASH_28F640C3T:
+		fmt = "28F640C3%s (64 Mbit, %s)\n";
+		break;
+	case FLASH_INTEL640B:
+	case FLASH_INTEL640T:
+		fmt = "28F640B3%s (64 Mbit, %s)\n";
+		break;
+	default:
+		fmt = "Unknown Chip Type\n";
+		break;
+	}
+
+	printf (fmt, bootletter, boottype);
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20,
+		info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+
+		printf (" %08lX%s", info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+
+	printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+ulong flash_get_size (FPWV *addr, flash_info_t *info)
+{
+	/* Write auto select command: read Manufacturer ID */
+
+	/* Write auto select command sequence and test FLASH answer */
+	addr[FLASH_CYCLE1] = (FPW)0x00AA00AA;	/* for AMD, Intel ignores this */
+	addr[FLASH_CYCLE2] = (FPW)0x00550055;	/* for AMD, Intel ignores this */
+	addr[FLASH_CYCLE1] = (FPW)0x00900090;	/* selects Intel or AMD */
+
+	/* The manufacturer codes are only 1 byte, so just use 1 byte.
+	 * This works for any bus width and any FLASH device width.
+	 */
+	udelay(100);
+	switch (addr[0] & 0xff) {
+
+	case (uchar)AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+
+	case (uchar)INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		break;
+	}
+
+	/* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
+	if (info->flash_id != FLASH_UNKNOWN) switch (addr[1]) {
+
+	case (FPW)AMD_ID_LV640U:	/* 29LV640 and 29LV641 have same ID */
+		info->flash_id += FLASH_AM640U;
+		info->sector_count = 128;
+		info->size = 0x00800000 * (sizeof(FPW)/2);
+		break;				/* => 8 or 16 MB	*/
+
+	case (FPW)INTEL_ID_28F800C3B:
+		info->flash_id += FLASH_28F800C3B;
+		info->sector_count = 23;
+		info->size = 0x00100000 * (sizeof(FPW)/2);
+		break;				/* => 1 or 2 MB		*/
+
+	case (FPW)INTEL_ID_28F800B3B:
+		info->flash_id += FLASH_INTEL800B;
+		info->sector_count = 23;
+		info->size = 0x00100000 * (sizeof(FPW)/2);
+		break;				/* => 1 or 2 MB		*/
+
+	case (FPW)INTEL_ID_28F160C3B:
+		info->flash_id += FLASH_28F160C3B;
+		info->sector_count = 39;
+		info->size = 0x00200000 * (sizeof(FPW)/2);
+		break;				/* => 2 or 4 MB		*/
+
+	case (FPW)INTEL_ID_28F160B3B:
+		info->flash_id += FLASH_INTEL160B;
+		info->sector_count = 39;
+		info->size = 0x00200000 * (sizeof(FPW)/2);
+		break;				/* => 2 or 4 MB		*/
+
+	case (FPW)INTEL_ID_28F320C3B:
+		info->flash_id += FLASH_28F320C3B;
+		info->sector_count = 71;
+		info->size = 0x00400000 * (sizeof(FPW)/2);
+		break;				/* => 4 or 8 MB		*/
+
+	case (FPW)INTEL_ID_28F320B3B:
+		info->flash_id += FLASH_INTEL320B;
+		info->sector_count = 71;
+		info->size = 0x00400000 * (sizeof(FPW)/2);
+		break;				/* => 4 or 8 MB		*/
+
+	case (FPW)INTEL_ID_28F640C3B:
+		info->flash_id += FLASH_28F640C3B;
+		info->sector_count = 135;
+		info->size = 0x00800000 * (sizeof(FPW)/2);
+		break;				/* => 8 or 16 MB	*/
+
+	case (FPW)INTEL_ID_28F640B3B:
+		info->flash_id += FLASH_INTEL640B;
+		info->sector_count = 135;
+		info->size = 0x00800000 * (sizeof(FPW)/2);
+		break;				/* => 8 or 16 MB	*/
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* => no or unknown flash */
+	}
+
+	flash_get_offsets((ulong)addr, info);
+
+	/* Put FLASH back in read mode */
+	flash_reset(info);
+
+	return (info->size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	FPWV *addr;
+	int flag, prot, sect;
+	int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL;
+	ulong start, now, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_INTEL800B:
+	case FLASH_INTEL160B:
+	case FLASH_INTEL320B:
+	case FLASH_INTEL640B:
+	case FLASH_28F800C3B:
+	case FLASH_28F160C3B:
+	case FLASH_28F320C3B:
+	case FLASH_28F640C3B:
+	case FLASH_AM640U:
+		break;
+	case FLASH_UNKNOWN:
+	default:
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	last  = get_timer(0);
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last && rcode == 0; sect++) {
+
+		if (info->protect[sect] != 0)	/* protected, skip it */
+			continue;
+
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+
+		addr = (FPWV *)(info->start[sect]);
+		if (intel) {
+			*addr = (FPW)0x00500050; /* clear status register */
+			*addr = (FPW)0x00200020; /* erase setup */
+			*addr = (FPW)0x00D000D0; /* erase confirm */
+		}
+		else {
+			/* must be AMD style if not Intel */
+			FPWV *base;		/* first address in bank */
+
+			base = (FPWV *)(info->start[0]);
+			base[FLASH_CYCLE1] = (FPW)0x00AA00AA;	/* unlock */
+			base[FLASH_CYCLE2] = (FPW)0x00550055;	/* unlock */
+			base[FLASH_CYCLE1] = (FPW)0x00800080;	/* erase mode */
+			base[FLASH_CYCLE1] = (FPW)0x00AA00AA;	/* unlock */
+			base[FLASH_CYCLE2] = (FPW)0x00550055;	/* unlock */
+			*addr = (FPW)0x00300030;	/* erase sector */
+		}
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts();
+
+		start = get_timer(0);
+
+		/* wait at least 50us for AMD, 80us for Intel.
+		 * Let's wait 1 ms.
+		 */
+		udelay (1000);
+
+		while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) {
+			if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+				printf ("Timeout\n");
+
+				if (intel) {
+					/* suspend erase	*/
+					*addr = (FPW)0x00B000B0;
+				}
+
+				flash_reset(info);	/* reset to read mode */
+				rcode = 1;		/* failed */
+				break;
+			}
+
+			/* show that we're waiting */
+			if ((get_timer(last)) > CFG_HZ) {/* every second */
+				putc ('.');
+				last = get_timer(0);
+			}
+		}
+
+		/* show that we're waiting */
+		if ((get_timer(last)) > CFG_HZ) {	/* every second */
+			putc ('.');
+			last = get_timer(0);
+		}
+
+		flash_reset(info);	/* reset to read mode	*/
+	}
+
+	printf (" done\n");
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */
+	int bytes;	  /* number of bytes to program in current word		*/
+	int left;	  /* number of bytes left to program			*/
+	int i, res;
+
+	for (left = cnt, res = 0;
+		 left > 0 && res == 0;
+		 addr += sizeof(data), left -= sizeof(data) - bytes) {
+
+		bytes = addr & (sizeof(data) - 1);
+		addr &= ~(sizeof(data) - 1);
+
+		/* combine source and destination data so can program
+		 * an entire word of 16 or 32 bits
+		 */
+		for (i = 0; i < sizeof(data); i++) {
+			data <<= 8;
+			if (i < bytes || i - bytes >= left )
+				data += *((uchar *)addr + i);
+			else
+				data += *src++;
+		}
+
+		/* write one word to the flash */
+		switch (info->flash_id & FLASH_VENDMASK) {
+		case FLASH_MAN_AMD:
+			res = write_word_amd(info, (FPWV *)addr, data);
+			break;
+		case FLASH_MAN_INTEL:
+			res = write_word_intel(info, (FPWV *)addr, data);
+			break;
+		default:
+			/* unknown flash type, error! */
+			printf ("missing or unknown FLASH type\n");
+			res = 1;	/* not really a timeout, but gives error */
+			break;
+		}
+	}
+
+	return (res);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash for AMD FLASH
+ * A word is 16 or 32 bits, whichever the bus width of the flash bank
+ * (not an individual chip) is.
+ *
+ * returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data)
+{
+	ulong start;
+	int flag;
+	int res = 0;	/* result, assume success	*/
+	FPWV *base;		/* first address in flash bank	*/
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*dest & data) != data) {
+		return (2);
+	}
+
+
+	base = (FPWV *)(info->start[0]);
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	base[FLASH_CYCLE1] = (FPW)0x00AA00AA;	/* unlock */
+	base[FLASH_CYCLE2] = (FPW)0x00550055;	/* unlock */
+	base[FLASH_CYCLE1] = (FPW)0x00A000A0;	/* selects program mode */
+
+	*dest = data;		/* start programming the data	*/
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	start = get_timer (0);
+
+	/* data polling for D7 */
+	while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			*dest = (FPW)0x00F000F0;	/* reset bank */
+			res = 1;
+		}
+	}
+
+	return (res);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash for Intel FLASH
+ * A word is 16 or 32 bits, whichever the bus width of the flash bank
+ * (not an individual chip) is.
+ *
+ * returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word_intel (flash_info_t *info, FPWV *dest, FPW data)
+{
+	ulong start;
+	int flag;
+	int res = 0;	/* result, assume success	*/
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*dest & data) != data) {
+		return (2);
+	}
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	*dest = (FPW)0x00500050;	/* clear status register	*/
+	*dest = (FPW)0x00FF00FF;	/* make sure in read mode	*/
+	*dest = (FPW)0x00400040;	/* program setup		*/
+
+	*dest = data;		/* start programming the data	*/
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	start = get_timer (0);
+
+	while (res == 0 && (*dest & (FPW)0x00800080) != (FPW)0x00800080) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			*dest = (FPW)0x00B000B0;	/* Suspend program	*/
+			res = 1;
+		}
+	}
+
+	if (res == 0 && (*dest & (FPW)0x00100010))
+		res = 1;	/* write failed, time out error is close enough	*/
+
+	*dest = (FPW)0x00500050;	/* clear status register	*/
+	*dest = (FPW)0x00FF00FF;	/* make sure in read mode	*/
+
+	return (res);
+}

board/atc/u-boot.lds

@@ -0,0 +1,118 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc8260/start.o	(.text)
+    *(.text)
+    common/environment.o(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
+

board/cray/L1/L1.c

@@ -27,7 +27,9 @@
 #include <command.h>
 #include <cmd_nvedit.h>
 #include <cmd_bootm.h>
+#include <cmd_boot.h>
 #include <rtc.h>
+#include <post.h>
 #include <net.h>
 #include <malloc.h>
 
@@ -53,17 +55,19 @@
  * space.
  * on the server this looks like:
  *
- * option space U-Boot;
- * option U-Boot.initrd    code 3 = string;
- * option U-Boot.bootcmd   code 4 = string;
- * option U-Boot.bootflags code 5 = string;
- * option U-Boot.rootdev   code 6 = string;
+ * option space CRAYL1;
+ * option CRAYL1.initrd     code 3 = string;
+ * ..etc...
  */
 #define DHCP_VENDOR_SPECX   43
 #define DHCP_VX_INITRD       3
 #define DHCP_VX_BOOTCMD      4
-#define DHCP_VX_BOOTFLAGS    5
+#define DHCP_VX_BOOTARGS     5
 #define DHCP_VX_ROOTDEV      6
+#define DHCP_VX_FROMFLASH    7
+#define DHCP_VX_BOOTSCRIPT   8
+#define DHCP_VX_RCFILE	     9
+#define DHCP_VX_MAGIC        10
 
 /* Things DHCP server can tellme about.  If there's no flash address, then
  * they dont participate in 'update' to flash, and we force their values
@@ -89,18 +93,29 @@ static dhcp_item_t Things[] = {
 /* and the other way.. */
 	{DHCP_VENDOR_SPECX, DHCP_VX_INITRD, NULL, "initrd"},
 	{DHCP_VENDOR_SPECX, DHCP_VX_BOOTCMD, NULL, "bootcmd"},
-	{DHCP_VENDOR_SPECX, DHCP_VX_BOOTFLAGS, NULL, NULL},
+	{DHCP_VENDOR_SPECX, DHCP_VX_FROMFLASH, NULL, "fromflash"},
+	{DHCP_VENDOR_SPECX, DHCP_VX_BOOTSCRIPT, NULL, "bootscript"},
+	{DHCP_VENDOR_SPECX, DHCP_VX_RCFILE, NULL, "rcfile"},
+	{DHCP_VENDOR_SPECX, DHCP_VX_BOOTARGS, NULL, "xbootargs"},
 	{DHCP_VENDOR_SPECX, DHCP_VX_ROOTDEV, NULL, NULL},
+	{DHCP_VENDOR_SPECX, DHCP_VX_MAGIC, NULL, NULL}
 };
 
 #define N_THINGS ((sizeof(Things))/(sizeof(dhcp_item_t)))
 
-static void init_ecc_sdram (void);
+extern char bootscript[];
+
+/* Here is the boot logic as HUSH script. Overridden by any TFP provided
+ * bootscript file.
+ */
+
+static void init_sdram (void);
 
 /* ------------------------------------------------------------------------- */
 int board_pre_init (void)
 {
-	init_ecc_sdram ();
+	/* Running from ROM: global data is still READONLY */
+	init_sdram ();
 	mtdcr (uicsr, 0xFFFFFFFF);	/* clear all ints */
 	mtdcr (uicer, 0x00000000);	/* disable all ints */
 	mtdcr (uiccr, 0x00000020);	/* set all but FPGA SMI to be non-critical */
@@ -116,6 +131,7 @@ int checkboard (void)
 {
 	return (0);
 }
+/* ------------------------------------------------------------------------- */
 
 /* ------------------------------------------------------------------------- */
 int misc_init_r (void)
@@ -124,6 +140,7 @@ int misc_init_r (void)
 	image_header_t *hdr;
 	time_t timestamp;
 	struct rtc_time tm;
+	char bootcmd[32];
 
 	hdr = (image_header_t *) (CFG_MONITOR_BASE - sizeof (image_header_t));
 	timestamp = (time_t) hdr->ih_time;
@@ -143,6 +160,8 @@ int misc_init_r (void)
 			setenv ("ethaddr", e);
 		}
 	}
+	sprintf (bootcmd,"autoscript %X",(unsigned)bootscript);
+	setenv ("bootcmd", bootcmd);
 	return (0);
 }
 
@@ -168,11 +187,11 @@ void rtc_reset (void)
 }
 
 /* ------------------------------------------------------------------------- */
-/*  Do sdram bank init in C so I can read it..
+/*  Do sdram bank init in C so I can read it..no console to print to yet!
  */
-static void init_ecc_sdram (void)
+static void init_sdram (void)
 {
-	unsigned long tmp, *p;
+ unsigned long tmp;
 
 	/* write SDRAM bank 0 register */
 	mtdcr (memcfga, mem_mb0cf);
@@ -202,33 +221,78 @@ static void init_ecc_sdram (void)
 	mtdcr (memcfgd, 0x90800000);
 	udelay (200);
 
-/* disable ECC on all banks */
+/* initially, disable ECC on all banks */
+	udelay (200);
 	mtdcr (memcfga, mem_ecccf);
 	tmp = mfdcr (memcfgd);
 	tmp &= 0xff0fffff;
 	mtdcr (memcfga, mem_ecccf);
 	mtdcr (memcfgd, tmp);
 
-/* set up SDRAM Controller with ECC enabled */
+	return;
+}
+
+extern int memory_post_test (int flags);
+
+int testdram (void)
+{
+ unsigned long tmp;
+	uint *pstart = (uint *) 0x00000000;
+	uint *pend = (uint *) L1_MEMSIZE;
+	uint *p;
+
+	if (getenv_r("booted",NULL,0) <= 0)
+	{
+		printf ("testdram..");
+	/*AA*/
+		for (p = pstart; p < pend; p++)
+			*p = 0xaaaaaaaa;
+		for (p = pstart; p < pend; p++) {
+			if (*p != 0xaaaaaaaa) {
+				printf ("SDRAM test fails at: %08x, was %08x expected %08x\n", 
+						(uint) p, *p, 0xaaaaaaaa);
+				return 1;
+			}
+		}
+	/*55*/
+		for (p = pstart; p < pend; p++)
+			*p = 0x55555555;
+		for (p = pstart; p < pend; p++) {
+			if (*p != 0x55555555) {
+				printf ("SDRAM test fails at: %08x, was %08x expected %08x\n", 
+						(uint) p, *p, 0x55555555);
+				return 1;
+			}
+		}
+	/*addr*/
+		for (p = pstart; p < pend; p++)
+			*p = (unsigned)p;
+		for (p = pstart; p < pend; p++) {
+			if (*p != (unsigned)p) {
+				printf ("SDRAM test fails at: %08x, was %08x expected %08x\n", 
+						(uint) p, *p, (uint)p);
+				return 1;
+			}
+		}
+		printf ("Success. ");
+	}
+	printf ("Enable ECC..");
+
 	mtdcr (memcfga, mem_mcopt1);
 	tmp = (mfdcr (memcfgd) & ~0xFFE00000) | 0x90800000;
 	mtdcr (memcfga, mem_mcopt1);
 	mtdcr (memcfgd, tmp);
 	udelay (600);
-
-/* fill all the memory */
-	for (p = (unsigned long) 0; ((unsigned long) p < L1_MEMSIZE);
-		 *p++ = 0L);
+	for (p = (unsigned long) 0; ((unsigned long) p < L1_MEMSIZE); *p++ = 0L)
+		;
 	udelay (400);
 	mtdcr (memcfga, mem_ecccf);
 	tmp = mfdcr (memcfgd);
-
-/* enable ECC on bank 0 */
 	tmp |= 0x00800000;
 	mtdcr (memcfgd, tmp);
 	udelay (400);
-
-	return;
+	printf ("enabled.\n");
+	return (0);
 }
 
 /* ------------------------------------------------------------------------- */
@@ -250,7 +314,9 @@ static u8 *dhcp_env_update (u8 thing, u8 * pop)
 
 /* set env. */
 	if (Things[thing].envname)
+	{
 		setenv (Things[thing].envname, Things[thing].dhcpvalue);
+	}
 	return (Things[thing].dhcpvalue);
 }
 
@@ -285,9 +351,9 @@ u8 *dhcp_vendorex_proc (u8 * pop)
 		     oplen -= sub_oplen, sub_op += (sub_oplen + 2)) {
 			for (thing = 0; thing < N_THINGS; thing++) {
 			    if (*sub_op == Things[thing].dhcp_vendor_option) {
-				if (!(retval = dhcp_env_update (thing, sub_op))) {
-					return NULL;
-				}
+					if (!(retval = dhcp_env_update (thing, sub_op))) {
+						return NULL;
+					}
 			    }
 			}
 		}
@@ -298,5 +364,5 @@ u8 *dhcp_vendorex_proc (u8 * pop)
 					return NULL;
 		}
 	}
-	return (thing >= N_THINGS ? NULL : pop);
+	return (pop);
 }

board/cray/L1/Makefile

@@ -25,18 +25,28 @@ include $(TOPDIR)/config.mk
 
 LIB	= lib$(BOARD).a
 
-OBJS	= $(BOARD).o flash.o
-SOBJS	= init.o
+OBJS	= $(BOARD).o flash.o bootscript.o
+SOBJS	= init.o 
 
 $(LIB):	$(OBJS) $(SOBJS)
 	$(AR) crv $@ $^
 
 clean:
-	rm -f $(SOBJS) $(OBJS)
+	rm -f $(SOBJS) $(OBJS) bootscript.c bootscript.image
 
 distclean:	clean
 	rm -f $(LIB) core *.bak .depend
 
+$(BOARD).o: $(BOARD).c bootscript.o
+
+bootscript.o: bootscript.c
+
+bootscript.c: bootscript.image
+	od -t x1 -v -A x $^ | awk -f x2c.awk > $@
+
+bootscript.image: bootscript.hush Makefile
+	-$(TOPDIR)/tools/mkimage -A ppc -O linux -T script -C none -a 0 -e 0 -n bootscript -d  bootscript.hush $@
+
 #########################################################################
 
 .depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)

board/cray/L1/bootscript.hush

@@ -0,0 +1,117 @@
+# $Header$
+# hush bootscript for PPCBOOT on L1
+# note: all #s are in hex, do _NOT_ prefix it with 0x
+
+flash_rfs=ffc00000
+flash_krl=fff00000
+tftp_addr=100000
+tftp2_addr=1000000
+
+if printenv booted
+then
+	echo already booted before
+else
+	echo first boot in environment, create and save settings
+	setenv booted OK
+	saveenv
+fi
+
+setenv autoload no
+# clear out stale env stuff, so we get fresh from dhcp.
+for setting in initrd fromflash kernel rootfs rootpath
+do
+setenv $setting
+done
+
+dhcp
+
+# if host provides us with a different bootscript, us it.
+if printenv bootscript
+	then
+	tftp $tftp_addr $bootcript
+	if imi $tftp_addr
+	then
+		autoscript $tftp_addr
+	fi
+fi
+
+# default base kernel arguments.
+setenv bootargs $xbootargs devfs=mount ip=$ipaddr:$serverip:$gatewayip:$netmask:L1:eth0:off wdt=120
+
+# Have a kernel in flash?
+if imi $flash_krl
+then
+	echo ok kernel to boot from $flash_krl
+	setenv kernel $flash_krl
+else
+	echo no kernel to boot from $flash_krl, need tftp
+fi
+
+# Have a rootfs in flash? 
+echo test for SQUASHfs at $flash_rfs
+
+if imi $flash_rfs
+then
+	echo appears to be a good initrd image at base of flash OK
+	setenv rootfs $flash_rfs
+else
+	echo no image at base of flash, need nfsroot or initrd
+fi
+
+# I boot from flash if told to and I can.
+if printenv fromflash && printenv kernel && printenv rootfs
+then
+	echo booting entirely from flash
+	setenv bootargs root=/dev/ram0 rw $bootargs
+	bootm $kernel $rootfs
+	echo oh no failed so I try some other stuff
+fi
+
+# TFTP down a kernel
+if printenv bootfile
+then 
+	tftp $tftp_addr $bootfile
+	setenv kernel $tftp_addr
+	echo I will boot the TFTP kernel
+else
+	if printenv kernel
+	then
+		echo no bootfile specified, will use one from flash
+	else
+		setenv bootfile /opt/crayx1/craymcu/l1/flash/linux.image
+		echo OH NO! we have no bootfile,nor flash kernel! try default: $bootfile
+		tftp $tftp_addr $bootfile
+		setenv kernel $tftp_addr
+	fi
+fi
+
+# the rootfs.
+if printenv rootpath
+then
+	echo rootpath is $rootpath
+	if printenv initrd
+	then 
+		echo initrd is also specified, so use $initrd
+		tftp $tftp2_addr $initrd
+		setenv bootargs root=/dev/ram0 rw cwsroot=$serverip:$rootpath $bootargs
+		bootm $kernel $tftp2_addr
+	else
+		echo initrd is not specified, so use NFSROOT $rootpat
+		setenv bootargs root=/dev/nfs ro nfsroot=$serverip:$rootpath $bootargs
+		bootm $kernel
+	fi
+else
+	echo we have no rootpath check for one in flash
+	if printenv rootfs
+	then
+		echo I will use the one in flash
+		setenv bootargs root=/dev/mtdblock/0 ro rootfstype=squashfs $bootargs
+		bootm $kernel
+	else
+		setenv rootpath /export/crayl1
+		echo OH NO! we have no rootpath,nor flash kernel! try default: $rootpath
+		setenv bootargs root=/dev/mtdblock/0 ro rootfstype=squashfs $bootargs
+		bootm $kernel
+	fi
+fi
+reset

board/cray/L1/patchme

@@ -0,0 +1,30 @@
+# master confi.mk
+echo "CROSS_COMPILE = powerpc-linux-"	>>include/config.mk
+
+# patch the examples/Makefile to ignore return value from OBJCOPY
+sed  -e 's/$(OBJCOPY)/-&/' < examples/Makefile > examples/makefile
+
+# add a built target for mkimage on the target architecture
+sed  -e 's/^all:.*$/all: .depend envcrc mkimage mkimage.ppc/' < tools/Makefile > tools/makefile
+
+cat <<EOF >>tools/makefile
+mkimage.ppc : mkimage.o.ppc crc32.o.ppc
+	powerpc-linux-gcc -msoft-float -Wall -Wstrict-prototypes -o \$@ \$^
+	powerpc-linux-strip $@
+
+XFLAGS="-D__KERNEL__  -I../include -DCONFIG_4xx -Wall -Wstict-prototypes"
+mkimage.o.ppc: mkimage.c
+	powerpc-linux-gcc -msoft-float -Wall -I../include -c -o \$@ \$^
+
+crc32.o.ppc: crc32.c
+	powerpc-linux-gcc -msoft-float -Wall -I../include -c -o \$@ \$^
+
+EOF
+
+# make an image by default out of the u-boot image
+sed  -e 's/^all:.*$/all: u-boot.image /' < Makefile > makefile
+cat <<EOF >>makefile
+u-boot.image:  u-boot.bin
+	tools/mkimage -A ppc -O linux -T firmware -C none -a 0 -e 0 -n U-Boot -d \$^ \$@
+
+EOF

board/cray/L1/x2c.awk

@@ -0,0 +1,6 @@
+#!/bin/awk
+BEGIN { print "unsigned char bootscript[] = { \n"}
+{ for (i = 2; i <= NF ; i++ ) printf "0x"$i","
+  print ""
+}
+END { print "\n};\n" }

board/gen860t/README

@@ -1,8 +1,7 @@
-
 This directory contains board specific code for a generic MPC860T based
 embedded computer, called 'GEN860T'.  The design is generic in the sense that
 common, readily available components are used and that the architecture of the
-system is i(relatively) straightforward:
+system is relatively straightforward:
 
 	One eight bit wide boot (FLASH) memory
 	32 bit main memory using SDRAM
@@ -23,14 +22,14 @@ hearing from you, especially if you discover bugs or find ways to improve the
 quality of this U-Boot port.
 
 Here are the salient features of the system:
-Clock						:	33 Mhz oscillator
-Processor core frequency	:	66 Mhz  if in 1:2:1 mode; can also run 1:1
-Bus frequency				:	33 Mhz
+Clock						:	33.3 Mhz oscillator
+Processor core frequency	:	66.6 Mhz  if in 1:2:1 mode; can also run 1:1
+Bus frequency				:	33.3 Mhz
 
 Main memory:
 	Type	: SDRAM
 	Width	: 32 bits
-	Size	: 64 megabytes
+	Size	: 64 mibibytes
 	Chip	: Two Micron MT48LC16M16A2TG-7E
 	CS		: MPC860T CS1*/UPMA
 	UPMA CONNECTIONS:
@@ -42,7 +41,7 @@ Main memory:
 Boot memory:
 	Type	: FLASH
 	Width	: 8 bits
-	Size	: 16 megabytes
+	Size	: 16 mibibytes
 	Chip	: One Intel 28F128J3A (StrataFlash)
 	CS		: MPC860T CS0*/GPCM (this is the "boot" chip select)
 
@@ -56,7 +55,7 @@ EEPROM memory:
 Filesystem memory:
 	Type	: NAND FLASH (Toshiba)
 	Width	: 8 bits (i.e. interface to DOC is 8 bits)
-	Size	: 32 megabytes
+	Size	: 32 mibibytes
 	Chip	: One DiskOnCHip Millenium Plus (DOC 2000+)
 	CS		: MPC860T CS2*/GPCM
 
@@ -92,6 +91,12 @@ Miscellaneous:
 	Mil-Std 1553 databus interface on CS5*/GPCM.
 	Audio sounder (beeper) with digital volume control connected to SPKROUT.
 
+SC variant:
+	A reduced-feature version of the GEN860T port is also supported: GEN860T_SC.
+	The 'SC' variant only provides support for the Virtex FPGA, SDRAM main
+	memory, EEPROM and flash memory.  The system clock frequency is reduced
+	to 24 MHz.
+
 Issues:
 	The DOC 2000+ returns 0x40 as its device ID when probed using the method
 	desxribed in the DOC datasheet.  Unfortunately, the U-Boot DOC driver
@@ -105,11 +110,11 @@ Status:
 	in MTD for this device.  I wish I had known this sooner :(
 
 The GEN860T board specific files and configuration is based on the work
-of others who have contributed to U-Boot. The copright and license notices
+of others who have contributed to U-Boot. The copyright and license notices
 of these authors have been retained wherever their code has been reused.
 All new code to support the GEN860T board is:
 
-	(C) Copyright 2001-2002
+	(C) Copyright 2001-2003
 	Keith Outwater (keith_outwater@mvis.com)
 
 and the following license applies:

board/gen860t/gen860t.c

@@ -271,18 +271,12 @@ misc_init_r (void)
 int
 last_stage_init(void)
 {
+#if !defined(CONFIG_SC)
 	unsigned char buf[256];
 	int i;
 
 	/*
-	 * Set LEDs here since status LED init code has already run
-	 */
-	status_led_set(STATUS_LED_BIT1, STATUS_LED_ON);
-	status_led_set(STATUS_LED_BIT3, STATUS_LED_ON);
-
-	/*
-	 * Turn the beeper volume all the way down in case this is a warm
-	 * boot.
+	 * Turn the beeper volume all the way down in case this is a warm boot.
 	 */
 	set_beeper_volume(-64);
 	init_beeper();
@@ -294,6 +288,18 @@ last_stage_init(void)
 	if (i > 0) {
 		do_beeper(buf);
 	}
+#endif
 	return 0;
 }
+
+/*
+ * Stub to make POST code happy.  Can't self-poweroff, so just hang.
+ */
+void
+board_poweroff(void)
+{
+	puts("### Please power off the board ###\n");
+    while (1);
+}
+
 /* vim: set ts=4 sw=4 tw=78 : */

board/gen860t/ioport.c

@@ -42,8 +42,9 @@
 const mpc8xx_iop_conf_t iop_conf_tab[NUM_PORTS][PORT_BITS] = {
     /*
 	 * Port A configuration
-	 * Pin		Signal				Type	Active		Initial state
-	 * PA7 		fpgaProgramLowOut	Out		Low			High
+	 * Pin	Signal					Type	Active	Initial state
+	 * PA7 	fpgaProgramLowOut		Out		Low			High
+	 * PA1 	fpgaCoreVoltageFailLow	In		Low			N/A
 	 */
     {	/*	    conf ppar psor pdir podr pdat pint	   function 		*/
 	/* N/A  */ { 0,   0,   0,   0,   0,   0,   0 }, /* No pin			*/
@@ -62,22 +63,32 @@ const mpc8xx_iop_conf_t iop_conf_tab[NUM_PORTS][PORT_BITS] = {
 	/* PA4  */ { 1,   0,   0,   1,   0,   0,   0 }, /* red bicolor LED 0*/
 	/* PA3  */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
 	/* PA2  */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+#if !defined(CONFIG_SC)
+	/* PA1  */ { 1,   0,   0,   0,   0,   0,   0 }, /*	fpgaCoreVoltageFail*/
+#else
 	/* PA1  */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+#endif
 	/* PA0  */ { 0,   0,   0,   0,   0,   0,   0 }  /*	*/
     },
 
 	/*
+	 * Port B configuration
 	 * Pin		Signal			Type		Active		Initial state
 	 * PB14		docBusyLowIn	In			Low			X
 	 * PB15		gpio1Sig		Out			High		Low
 	 * PB16		fpgaDoneBi		In			High		X
-	 * PB17		swBitOkLowOut	Out			Low			Low
+	 * PB17		swBitOkLowOut	Out			Low			High
 	 * PB19		speakerVolSig	Out/Hi-Z	High/Low	High (Hi-Z)
 	 * PB22		fpgaInitLowBi	In			Low			X
 	 * PB23		batteryOkSig	In			High		X
-     */
-    {	/*	    conf ppar psor pdir podr pdat pint 	  function			*/
-	/* PB31 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	 * PB31		pulseCatcherClr	Out			High		0
+	 */
+	{	/*	    conf ppar psor pdir podr pdat pint 	  function			*/
+#if !defined(CONFIG_SC)
+	/* PB31 */ { 0,	  0,   0,   0,   0,   0,   0 }, /*	*/
+#else
+	/* PB31 */ { 1,   0,   0,   1,   0,   0,   0 }, /* pulseCatcherClr	*/
+#endif
 	/* PB30 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
 	/* PB29 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
 	/* PB28 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
@@ -85,19 +96,32 @@ const mpc8xx_iop_conf_t iop_conf_tab[NUM_PORTS][PORT_BITS] = {
 	/* PB26 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
 	/* PB25 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
 	/* PB24 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+#if !defined(CONFIG_SC)
 	/* PB23 */ { 1,   0,   0,   0,   0,   0,   0 }, /* batteryOk		*/
+#else
+	/* PB23 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+#endif
 	/* PB22 */ { 1,   0,   0,   0,   0,   0,   0 }, /* fpgaInitLowBi	*/
 	/* PB21 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
 	/* PB20 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+#if !defined(CONFIG_SC)
 	/* PB19 */ { 1,   0,   0,   1,   1,   1,   0 }, /* speakerVol		*/
+#else
+	/* PB19 */ { 0,   0,   0,   1,   1,   1,   0 }, /*	*/
+#endif
 	/* PB18 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
-	/* PB17 */ { 1,   0,   0,   1,   0,   0,   0 }, /* swBitOkLow		*/
+	/* PB17 */ { 1,   0,   0,   1,   0,   1,   0 }, /* swBitOkLow		*/
 	/* PB16 */ { 1,   0,   0,   0,   0,   0,   0 }, /* fpgaDone			*/
 	/* PB15 */ { 1,   0,   0,   1,   0,   0,   0 }, /* gpio1			*/
+#if !defined(CONFIG_SC)
 	/* PB14 */ { 1,   0,   0,   0,   0,   0,   0 }  /* docBusyLow		*/
-    },
+#else
+	/* PB14 */ { 0,   0,   0,   0,   0,   0,   0 }  /* 	*/
+#endif
+	},
 
 	/*
+	 * Port C configuration
 	 * Pin		Signal				Type	Active		Initial state
 	 * PC4		i2cBus1EnSig		Out		High		High
 	 * PC5		i2cBus2EnSig		Out		High		High
@@ -108,29 +132,48 @@ const mpc8xx_iop_conf_t iop_conf_tab[NUM_PORTS][PORT_BITS] = {
 	 * PC12		systemBitOkIn		In		High		X
 	 * PC15		selfDreqLow			In		Low			X
 	 */
-    {	/*	    conf ppar psor pdir podr pdat pint 	  function			*/
+	{	/*	    conf ppar psor pdir podr pdat pint 	  function			*/
 	/* N/A	*/ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
 	/* N/A	*/ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
 	/* PC15 */ { 1,   0,   0,   0,   0,   0,   0 }, /* selfDreqLowIn	*/
 	/* PC14 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
 	/* PC13 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+#if !defined(CONFIG_SC)
 	/* PC12 */ { 1,   0,   0,   0,   0,   0,   0 }, /* systemBitOkIn	*/
+#else
+	/* PC12 */ { 0,   0,   0,   0,   0,   0,   0 }, /* 	*/
+#endif
 	/* PC11 */ { 1,   0,   0,   1,   0,   1,   0 }, /* fpgaResetLowOut	*/
+#if !defined(CONFIG_SC)
 	/* PC10 */ { 1,   0,   0,   1,   0,   1,   0 }, /* i2cBus4EnSig		*/
+#else
+	/* PC10 */ { 0,   0,   0,   1,   0,   1,   0 }, /*	*/
+#endif
 	/* PC9  */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+#if !defined(CONFIG_SC)
 	/* PC8  */ { 1,   0,   0,   1,   0,   1,   0 }, /* i2cBus3EnSig		*/
+#else
+	/* PC8  */ { 0,   0,   0,   1,   0,   1,   0 }, /*	*/
+#endif
 	/* PC7  */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
 	/* PC6  */ { 1,   0,   0,   1,   0,   1,   0 }, /* gpio0			*/
+#if !defined(CONFIG_SC)
 	/* PC5  */ { 1,   0,   0,   1,   0,   1,   0 }, /* i2cBus2EnSig		*/
 	/* PC4  */ { 1,   0,   0,   1,   0,   1,   0 }, /* i2cBus1EnSig		*/
+#else
+	/* PC5  */ { 0,   0,   0,   1,   0,   1,   0 }, /*	*/
+	/* PC4  */ { 0,   0,   0,   1,   0,   1,   0 }, /*	*/
+#endif
 	/* N/A  */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
 	/* N/A  */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
 	/* N/A  */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
 	/* N/A  */ { 0,   0,   0,   0,   0,   0,   0 }  /*	*/
-    },
+	},
 
-    /* Port D configuration */
-    {	/*	    conf ppar psor pdir podr pdat pint 	   function			*/
+	/*
+	 * Port D configuration
+	 */
+	{	/*	    conf ppar psor pdir podr pdat pint 	   function			*/
 	/* N/A  */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
 	/* N/A  */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
 	/* PD15 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
@@ -149,7 +192,7 @@ const mpc8xx_iop_conf_t iop_conf_tab[NUM_PORTS][PORT_BITS] = {
 	/* N/A  */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
 	/* N/A  */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
 	/* N/A  */ { 0,   0,   0,   0,   0,   0,   0 }  /*	*/
-    }
+	}
 };
 
 /*

board/gen860t/u-boot-flashenv.lds

@@ -0,0 +1,132 @@
+/*
+ * Linker command file for the GEN860T board when the environment is
+ * stored in flash memory.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+SECTIONS
+{
+  /*
+   * Read-only sections, merged into text segment:
+   */
+  . = + SIZEOF_HEADERS;
+  .interp        : { *(.interp)		}
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)	}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)	}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)	}
+  .rela.got      : { *(.rela.got)	}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)	}
+  .rela.bss      : { *(.rela.bss)	}
+  .rel.plt       : { *(.rel.plt)	}
+  .rela.plt      : { *(.rela.plt)	}
+  .init          : { *(.init)		}
+  .plt           : { *(.plt)		}
+  .text :
+  {
+    cpu/mpc8xx/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /*
+   * Read-write section, merged into data segment:
+   */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data:
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  
+  _end = . ;
+  PROVIDE (end = .);
+
+  .ppcenv:
+  {
+    . = env_offset;
+    common/environment.o
+  }
+}

board/gen860t/u-boot.lds

@@ -56,15 +56,6 @@ SECTIONS
   .text :
   {
     cpu/mpc8xx/start.o		(.text)
-    common/dlmalloc.o		(.text)
-    lib_ppc/ppcstring.o		(.text)
-    lib_generic/vsprintf.o	(.text)
-    lib_generic/crc32.o		(.text)
-    lib_generic/zlib.o		(.text)
-
-/*    . = env_offset;
-    common/environment.o(.text) */
-
     *(.text)
     *(.fixup)
     *(.got1)
@@ -128,8 +119,6 @@ SECTIONS
    *(.bss)
    *(COMMON)
   }
-
   _end = . ;
   PROVIDE (end = .);
 }
-

board/incaip/memsetup.S

@@ -49,13 +49,11 @@
 #define MC_LATENCY(value)       0x1038(value)
 #define MC_TREFRESH(value)      0x1040(value)
 
-#if CPU_CLOCK_RATE==150000000   /* 150 MHz clock for the MIPS core */
 #define CGU_MODUL_BASE          0xBF107000
 #define CGU_PLL1CR(value)       0x0008(value)
 #define CGU_DIVCR(value)        0x0010(value)
 #define CGU_MUXCR(value)        0x0014(value)
 #define CGU_PLL1SR(value)       0x000C(value)
-#endif
 
 	.globl	memsetup
 memsetup:
@@ -67,12 +65,12 @@ memsetup:
 	li	t1, 0xA0000041
 	sw	t1, EBU_ADDSEL0(t0)
 
-#if CPU_CLOCK_RATE==150000000   /* 150 MHz clock for the MIPS core */
-	li	t1, 0xA841417E
-	sw	t1, EBU_BUSCON0(t0)   /* value set up by magic flash word */
+#if CPU_CLOCK_RATE==100000000	/* 100 MHz clock for the MIPS core */
+	lw	t1, EBU_BUSCON0(t0)  /* value set up by magic flash word */
 	sw	t1, EBU_BUSCON2(t0)
-#else /* 100 MHz */
-	lw	t1, EBU_BUSCON0(t0)   /* value set up by magic flash word */
+#else /* 150 MHz or 133 MHz */
+	li	t1, 0x8841417E
+	sw	t1, EBU_BUSCON0(t0)
 	sw	t1, EBU_BUSCON2(t0)
 #endif
 
@@ -85,10 +83,10 @@ memsetup:
 	li	t1, 0xBE0000F1
  	sw	t1, EBU_ADDSEL1(t0)
 
-#if CPU_CLOCK_RATE==150000000   /* 150 MHz clock for the MIPS core */
-	li	t1, 0x684143FD
-#else /* 100 MHz */
+#if CPU_CLOCK_RATE==100000000   /* 100 MHz clock for the MIPS core */
 	li	t1, 0x684142BD
+#else /* 150 MHz or 133 MHz */
+	li	t1, 0x684143FD
 #endif
  	sw	t1, EBU_BUSCON1(t0)
 
@@ -105,6 +103,14 @@ b1:
 	beq     t1, zero, b1
 	li      t1, 0x80000001
 	sw      t1, CGU_MUXCR(t0)
+#elif CPU_CLOCK_RATE==133000000	/* 133 MHz clock for the MIPS core */
+	li	t0, CGU_MODUL_BASE
+	li	t1, 0x80000054
+	sw	t1, CGU_DIVCR(t0)
+	li	t1, 0x80000000
+	sw	t1, CGU_MUXCR(t0)
+	li	t1, 0x800B0001
+	sw	t1, CGU_PLL1CR(t0)
 #endif
 
 	/* SDRAM Initialization.

board/lwmon/lwmon.c

@@ -47,11 +47,18 @@ V* Verification:  dzu@denx.de
 
 /*------------------------ Local prototypes ---------------------------*/
 static long int dram_size (long int, long int *, long int);
+static void kbd_init (void);
+static int compare_magic (uchar *kbd_data, uchar *str);
 
 
 /*--------------------- Local macros and constants --------------------*/
 #define	_NOT_USED_	0xFFFFFFFF
 
+#ifdef CONFIG_MODEM_SUPPORT
+static int key_pressed(void);
+extern void disable_putc(void);
+#endif /* CONFIG_MODEM_SUPPORT */
+
 /*
  * 66 MHz SDRAM access using UPM A
  */
@@ -396,6 +403,7 @@ int board_pre_init (void)
 	immr->im_cpm.cp_pbodr &= ~PB_ENET_TENA;
 	immr->im_cpm.cp_pbdat &= ~PB_ENET_TENA;	/* set to 0 = disabled */
 	immr->im_cpm.cp_pbdir |= PB_ENET_TENA;
+
 	return (0);
 }
 
@@ -466,38 +474,45 @@ static uchar *key_match (uchar *);
 #define	KEYBD_SET_DEBUGMODE	'#'	/* Magic key to enable debug output */
 
 /***********************************************************************
-F* Function:     int misc_init_r (void) P*A*Z*
+F* Function:     int board_postclk_init (void) P*A*Z*
  *
 P* Parameters:   none
 P*
 P* Returnvalue:  int
-P*                - 0 is always returned, even in the case of a keyboard
-P*                    error.
+P*                - 0 is always returned.
  *
-Z* Intention:    This function is the misc_init_r() method implementation
+Z* Intention:    This function is the board_postclk_init() method implementation
 Z*               for the lwmon board.
-Z*               The keyboard controller is initialized and the result
-Z*               of a read copied to the environment variable "keybd".
-Z*               If KEYBD_SET_DEBUGMODE is defined, a check is made for
-Z*               this key, and if found display to the LCD will be enabled.
-Z*               The keys in "keybd" are checked against the magic
-Z*               keycommands defined in the environment.
-Z*               See also key_match().
  *
-D* Design:       wd@denx.de
-C* Coding:       wd@denx.de
-V* Verification: dzu@denx.de
  ***********************************************************************/
-int misc_init_r (void)
+int board_postclk_init (void)
 {
+	DECLARE_GLOBAL_DATA_PTR;
+
+	kbd_init();
+
+#ifdef CONFIG_MODEM_SUPPORT
+	if (key_pressed()) {
+		disable_putc();	/* modem doesn't understand banner etc */
+		gd->do_mdm_init = 1;
+	}
+#endif
+
+	return (0);
+}
+
+static void kbd_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
 	uchar kbd_data[KEYBD_DATALEN];
 	uchar tmp_data[KEYBD_DATALEN];
-	uchar keybd_env[2 * KEYBD_DATALEN + 1];
 	uchar val, errcd;
-	uchar *str;
 	int i;
 
 	i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+	
+	gd->kbd_status = 0;
 
 	/* Read initial keyboard error code */
 	val = KEYBD_CMD_READ_STATUS;
@@ -508,7 +523,7 @@ int misc_init_r (void)
 	/* clear "irrelevant" bits. Recommended by Martin Rajek, LWN */
 	errcd &= ~(KEYBD_STATUS_H_RESET|KEYBD_STATUS_BROWNOUT);
 	if (errcd) {
-		printf ("KEYBD: Error %02X\n", errcd);
+		gd->kbd_status |= errcd << 8;
 	}
 	/* Reset error code and verify */
 	val = KEYBD_CMD_RESET_ERRORS;
@@ -521,28 +536,10 @@ int misc_init_r (void)
 
 	val &= KEYBD_STATUS_MASK;	/* clear unused bits */
 	if (val) {			/* permanent error, report it */
-		printf ("*** Keyboard error code %02X ***\n", val);
-		sprintf (keybd_env, "%02X", val);
-		setenv ("keybd", keybd_env);
-		return 0;
+		gd->kbd_status |= val;
+		return;
 	}
 
-	/*
-	 * Now we know that we have a working  keyboard,  so  disable
-	 * all output to the LCD except when a key press is detected.
-	 */
-
-	if ((console_assign (stdout, "serial") < 0) ||
-		(console_assign (stderr, "serial") < 0)) {
-		printf ("Can't assign serial port as output device\n");
-	}
-
-	/* Read Version */
-	val = KEYBD_CMD_READ_VERSION;
-	i2c_write (kbd_addr, 0, 0, &val, 1);
-	i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_VERSIONLEN);
-	printf ("KEYBD: Version %d.%d\n", kbd_data[0], kbd_data[1]);
-
 	/*
 	 * Read current keyboard state.
 	 *
@@ -569,6 +566,73 @@ int misc_init_r (void)
 		memcpy (tmp_data, kbd_data, KEYBD_DATALEN);
 		udelay (5000);
 	}
+}
+
+/***********************************************************************
+F* Function:     int misc_init_r (void) P*A*Z*
+ *
+P* Parameters:   none
+P*
+P* Returnvalue:  int
+P*                - 0 is always returned, even in the case of a keyboard
+P*                    error.
+ *
+Z* Intention:    This function is the misc_init_r() method implementation
+Z*               for the lwmon board.
+Z*               The keyboard controller is initialized and the result
+Z*               of a read copied to the environment variable "keybd".
+Z*               If KEYBD_SET_DEBUGMODE is defined, a check is made for
+Z*               this key, and if found display to the LCD will be enabled.
+Z*               The keys in "keybd" are checked against the magic
+Z*               keycommands defined in the environment.
+Z*               See also key_match().
+ *
+D* Design:       wd@denx.de
+C* Coding:       wd@denx.de
+V* Verification: dzu@denx.de
+ ***********************************************************************/
+int misc_init_r (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	uchar kbd_data[KEYBD_DATALEN];
+	uchar keybd_env[2 * KEYBD_DATALEN + 1];
+	uchar kbd_init_status = gd->kbd_status >> 8;
+	uchar kbd_status = gd->kbd_status;
+	uchar val;
+	uchar *str;
+	int i;
+
+	if (kbd_init_status) {
+		printf ("KEYBD: Error %02X\n", kbd_init_status);
+	}
+	if (kbd_status) {		/* permanent error, report it */
+		printf ("*** Keyboard error code %02X ***\n", kbd_status);
+		sprintf (keybd_env, "%02X", kbd_status);
+		setenv ("keybd", keybd_env);
+		return 0;
+	}
+
+	/*
+	 * Now we know that we have a working  keyboard,  so  disable
+	 * all output to the LCD except when a key press is detected.
+	 */
+
+	if ((console_assign (stdout, "serial") < 0) ||
+		(console_assign (stderr, "serial") < 0)) {
+		printf ("Can't assign serial port as output device\n");
+	}
+
+	/* Read Version */
+	val = KEYBD_CMD_READ_VERSION;
+	i2c_write (kbd_addr, 0, 0, &val, 1);
+	i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_VERSIONLEN);
+	printf ("KEYBD: Version %d.%d\n", kbd_data[0], kbd_data[1]);
+
+	/* Read current keyboard state */
+	val = KEYBD_CMD_READ_KEYS;
+	i2c_write (kbd_addr, 0, 0, &val, 1);
+	i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
 
 	for (i = 0; i < KEYBD_DATALEN; ++i) {
 		sprintf (keybd_env + i + i, "%02X", kbd_data[i]);
@@ -598,6 +662,56 @@ int misc_init_r (void)
 static uchar kbd_magic_prefix[] = "key_magic";
 static uchar kbd_command_prefix[] = "key_cmd";
 
+static int compare_magic (uchar *kbd_data, uchar *str)
+{
+	uchar compare[KEYBD_DATALEN-1];
+	uchar *nxt;
+	int i;
+
+	/* Don't include modifier byte */
+	memcpy (compare, kbd_data+1, KEYBD_DATALEN-1);
+
+	for (; str != NULL; str = (*nxt) ? nxt+1 : nxt) {
+		uchar c;
+		int k;
+
+		c = (uchar) simple_strtoul (str, (char **) (&nxt), 16);
+
+		if (str == nxt) {	/* invalid character */
+			break;
+		}
+
+		/*
+		 * Check if this key matches the input.
+		 * Set matches to zero, so they match only once
+		 * and we can find duplicates or extra keys
+		 */
+		for (k = 0; k < sizeof(compare); ++k) {
+			if (compare[k] == '\0')	/* only non-zero entries */
+				continue;
+			if (c == compare[k]) {	/* found matching key */
+				compare[k] = '\0';
+				break;
+			}
+		}
+		if (k == sizeof(compare)) {
+			return -1;		/* unmatched key */
+		}
+	}
+
+	/*
+	 * A full match leaves no keys in the `compare' array,
+	 */
+	for (i = 0; i < sizeof(compare); ++i) {
+		if (compare[i])
+		{
+			return -1;
+		}
+	}
+
+	return 0;
+}
+
 /***********************************************************************
 F* Function:     static uchar *key_match (uchar *kbd_data) P*A*Z*
  *
@@ -627,12 +741,9 @@ V* Verification: dzu@denx.de
  ***********************************************************************/
 static uchar *key_match (uchar *kbd_data)
 {
-	uchar compare[KEYBD_DATALEN-1];
 	uchar magic[sizeof (kbd_magic_prefix) + 1];
-	uchar extra;
-	uchar *str, *nxt, *suffix;
+	uchar *suffix;
 	uchar *kbd_magic_keys;
-	int i;
 
 	/*
 	 * The following string defines the characters that can pe appended
@@ -653,50 +764,7 @@ static uchar *key_match (uchar *kbd_data)
 #if 0
 		printf ("### Check magic \"%s\"\n", magic);
 #endif
-		/* Don't include modifier byte */
-		memcpy (compare, kbd_data+1, KEYBD_DATALEN-1);
-
-		extra = 0;
-
-		for (str= getenv(magic); str != NULL; str = (*nxt) ? nxt+1 : nxt) {
-			uchar c;
-			int k;
-
-			c = (uchar) simple_strtoul (str, (char **) (&nxt), 16);
-
-			if (str == nxt) {	/* invalid character */
-				break;
-			}
-
-			/*
-			 * Check if this key matches the input.
-			 * Set matches to zero, so they match only once
-			 * and we can find duplicates or extra keys
-			 */
-			for (k = 0; k < sizeof(compare); ++k) {
-				if (compare[k] == '\0')	/* only non-zero entries */
-					continue;
-				if (c == compare[k]) {	/* found matching key */
-					compare[k] = '\0';
-					break;
-				}
-			}
-			if (k == sizeof(compare)) {
-				extra = 1;		/* unmatched key */
-			}
-		}
-
-		/*
-		 * A full match leaves no keys in the `compare' array,
-		 * and has no extra keys
-		 */
-
-		for (i = 0; i < sizeof(compare); ++i) {
-			if (compare[i])
-				break;
-		}
-
-		if ((i == sizeof(compare)) && (extra == 0)) {
+		if (compare_magic(kbd_data, getenv(magic)) == 0) {
 			uchar cmd_name[sizeof (kbd_command_prefix) + 1];
 			char *cmd;
 
@@ -815,7 +883,9 @@ int do_kbd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	uchar val;
 	int i;
 
+#if 0 /* Done in kbd_init */
 	i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+#endif
 
 	/* Read keys */
 	val = KEYBD_CMD_READ_KEYS;
@@ -964,3 +1034,18 @@ void board_poweroff (void)
 
     while (1);
 }
+
+#ifdef CONFIG_MODEM_SUPPORT
+static int key_pressed(void)
+{
+	uchar kbd_data[KEYBD_DATALEN];
+	uchar val;
+
+	/* Read keys */
+	val = KEYBD_CMD_READ_KEYS;
+	i2c_write (kbd_addr, 0, 0, &val, 1);
+	i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
+
+	return (compare_magic(kbd_data, CONFIG_MODEM_KEY_MAGIC) == 0);
+}
+#endif	/* CONFIG_MODEM_SUPPORT */

board/purple/memsetup.S

@@ -26,10 +26,13 @@
 #include <version.h>
 #include <asm/regdef.h>
 
+#define MC_IOGP	0xBF800800
 
 	.globl	memsetup
 memsetup:
-
+	li	t0, MC_IOGP
+	li	t1, 0xf24
+	sw	t1, 0(t0)
 	j	ra
 	nop
 

board/purple/purple.c

@@ -51,6 +51,69 @@ extern int	asc_serial_getc 	(void);
 extern int	asc_serial_tstc 	(void);
 extern void	asc_serial_setbrg 	(void);
 
+static void sdram_timing_init (ulong size)
+{
+	register uint pass;
+	register uint done;
+	register uint count;
+	register uint p0, p1, p2, p3, p4;
+	register uint addr;
+
+#define WRITE_MC_IOGP_1 *(uint *)0xbf800800 = (p1<<14)+(p2<<13)+(p4<<8)+(p0<<4)+p3;
+#define WRITE_MC_IOGP_2 *(uint *)0xbf800800 = (p1<<14)+(p2<<13)+((p4-16)<<8)+(p0<<4)+p3;
+
+	done = 0;
+	p0 = 2;
+	while (p0 < 4 && done == 0) {
+	    p1 = 0;
+	    while (p1 < 2 && done == 0) {
+		p2 = 0;
+		while (p2 < 2 && done == 0) {
+		    p3 = 0;
+		    while (p3 < 16 && done == 0) {
+			count = 0;
+			p4 = 0;
+			while (p4 < 32 && done == 0) {
+			    WRITE_MC_IOGP_1;
+
+			    for (addr = KSEG1 + 0x4000;
+				 addr < KSEG1ADDR (size);
+				 addr = addr + 4) {
+					*(uint *) addr = 0xaa55aa55;
+			    }
+
+			    pass = 1;
+
+			    for (addr = KSEG1 + 0x4000;
+				 addr < KSEG1ADDR (size) && pass == 1;
+				 addr = addr + 4) {
+					if (*(uint *) addr != 0xaa55aa55)
+						pass = 0;
+			    }
+
+			    if (pass == 1) {
+				count++;
+			    } else {
+				count = 0;
+			    }
+
+			    if (count == 32) {
+				WRITE_MC_IOGP_2;
+				done = 1;
+			    }
+			    p4++;
+			}
+			p3++;
+		    }
+		    p2++;
+		}
+		p1++;
+	    }
+	    p0++;
+	    if (p0 == 1)
+		p0++;
+	}
+}
 
 long int initdram(int board_type)
 {
@@ -64,6 +127,11 @@ long int initdram(int board_type)
 	int	rows	= (cfgpb0 & 0xF0) >> 4;
 	int	dw	= cfgdw & 0xF;
 	ulong	size	= (1 << (rows + cols)) * (1 << (dw - 1)) * CFG_NB;
+	void (*  sdram_init) (ulong);
+
+	sdram_init = (void (*)(ulong)) KSEG0ADDR(&sdram_timing_init);
+
+	sdram_init(0x10000);
 
 	return size;
 }

board/r360mpi/flash.c

@@ -206,6 +206,12 @@ static ulong flash_get_size (FPW * addr, flash_info_t * info)
 {
 	FPW value;
 
+	/* Make sure Block Lock Bits get cleared */
+	addr[0] = (FPW) 0x00FF00FF;
+	addr[0] = (FPW) 0x00600060;
+	addr[0] = (FPW) 0x00D000D0;
+	addr[0] = (FPW) 0x00FF00FF;
+
 	/* Write auto select command: read Manufacturer ID */
 	addr[0x5555] = (FPW) 0x00AA00AA;
 	addr[0x2AAA] = (FPW) 0x00550055;

board/tqm8260/tqm8260.c

@@ -200,7 +200,7 @@ int checkboard (void)
 
 	puts ("Board: ");
 
-	if (!i || strncmp (str, "TQM8260", 7)) {
+	if (!i || strncmp (str, "TQM82", 5)) {
 		puts ("### No HW ID - assuming TQM8260\n");
 		return (0);
 	}

common/Makefile

@@ -28,7 +28,7 @@ LIB	= libcommon.a
 AOBJS	=
 
 COBJS	= main.o altera.o bedbug.o \
-	  cmd_autoscript.o cmd_bedbug.o cmd_boot.o \
+	  cmd_autoscript.o cmd_bedbug.o cmd_bmp.o cmd_boot.o \
 	  cmd_bootm.o cmd_cache.o cmd_console.o cmd_date.o \
 	  cmd_dcr.o cmd_diag.o cmd_doc.o cmd_nand.o cmd_dtt.o \
 	  cmd_eeprom.o cmd_elf.o cmd_fdc.o cmd_fdos.o cmd_flash.o \

common/cmd_bmp.c

@@ -0,0 +1,118 @@
+/*
+ * (C) Copyright 2002
+ * Dtlev Zundel, DENX Software Engineering, dzu@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * BMP handling routines
+ */
+
+#include <common.h>
+#include <bmp_layout.h>
+#include <command.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_BMP)
+
+static int bmp_info (ulong addr);
+static int bmp_display (ulong addr);
+
+/*
+ * Subroutine:  do_bmp
+ *
+ * Description: Handler for 'bmp' command..
+ *
+ * Inputs:	argv[1] contains the subcommand
+ *
+ * Return:      None
+ *
+ */
+int do_bmp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	ulong addr;
+
+	switch (argc) {
+	case 2:		/* use load_addr as default address */
+		addr = load_addr;
+		break;
+	case 3:		/* use argument */
+		addr = simple_strtoul(argv[2], NULL, 16);
+		break;
+	default:
+		printf ("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+	}
+
+	/* Allow for short names
+	 * Adjust length if more sub-commands get added
+	 */
+	if (strncmp(argv[1],"info",1) == 0) {
+		return (bmp_info(addr));
+	} else if (strncmp(argv[1],"display",1) == 0) {
+		return (bmp_display(addr));
+	} else {
+		printf ("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+	}
+}
+
+/*
+ * Subroutine:  bmp_info
+ *
+ * Description: Show information about bmp file in memory
+ *
+ * Inputs:	addr		address of the bmp file
+ *
+ * Return:      None
+ *
+ */
+static int bmp_info(ulong addr)
+{
+	bmp_image_t *bmp=(bmp_image_t *)addr;
+	if (!((bmp->header.signature[0]=='B') &&
+	      (bmp->header.signature[1]=='M'))) {
+		printf("There is no valid bmp file at the given address\n");
+		return(1);
+	}
+	printf("Image size    : %d x %d\n", le32_to_cpu(bmp->header.width),
+	       le32_to_cpu(bmp->header.height));
+	printf("Bits per pixel: %d\n", le16_to_cpu(bmp->header.bit_count));
+	printf("Compression   : %d\n", le32_to_cpu(bmp->header.compression));
+	return(0);
+}
+
+/*
+ * Subroutine:  bmp_display
+ *
+ * Description: Display bmp file located in memory
+ *
+ * Inputs:	addr		address of the bmp file
+ *
+ * Return:      None
+ *
+ */
+static int bmp_display(ulong addr)
+{
+	extern int lcd_display_bitmap (ulong);
+
+	return (lcd_display_bitmap (addr));
+}
+
+#endif /* (CONFIG_COMMANDS & CFG_CMD_BMP) */

common/cmd_boot.c

@@ -332,6 +332,7 @@ load_serial (ulong offset)
 		case SREC_DATA3:
 		case SREC_DATA4:
 		    store_addr = addr + offset;
+#ifndef CFG_NO_FLASH
 		    if (addr2info(store_addr)) {
 			int rc;
 
@@ -340,7 +341,9 @@ load_serial (ulong offset)
 				flash_perror (rc);
 				return (~0);
 			}
-		    } else {
+		    } else
+#endif
+		    {
 			memcpy ((char *)(store_addr), binbuf, binlen);
 		    }
 		    if ((store_addr) < start_addr)

common/cmd_bootm.c

@@ -31,6 +31,7 @@
 #include <image.h>
 #include <malloc.h>
 #include <zlib.h>
+#include <environment.h>
 #include <asm/byteorder.h>
 #if (CONFIG_COMMANDS & CFG_CMD_DATE) || defined(CONFIG_TIMESTAMP)
 #include <rtc.h>
@@ -98,12 +99,16 @@ static boot_os_Fcn do_bootm_linux;
 extern boot_os_Fcn do_bootm_linux;
 #endif
 static boot_os_Fcn do_bootm_netbsd;
+static boot_os_Fcn do_bootm_rtems;
 #if (CONFIG_COMMANDS & CFG_CMD_ELF)
 static boot_os_Fcn do_bootm_vxworks;
 static boot_os_Fcn do_bootm_qnxelf;
 int do_bootvx ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] );
 int do_bootelf (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] );
 #endif /* CFG_CMD_ELF */
+#if defined(CONFIG_ARTOS) && defined(CONFIG_PPC)
+static boot_os_Fcn do_bootm_artos;
+#endif
 
 image_header_t header;
 
@@ -321,6 +326,12 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	    do_bootm_netbsd (cmdtp, flag, argc, argv,
 			     addr, len_ptr, verify);
 	    break;
+	    
+	case IH_OS_RTEMS:
+	    do_bootm_rtems (cmdtp, flag, argc, argv,
+			     addr, len_ptr, verify);
+	    break;
+	     
 #if (CONFIG_COMMANDS & CFG_CMD_ELF)
 	case IH_OS_VXWORKS:
 	    do_bootm_vxworks (cmdtp, flag, argc, argv,
@@ -331,6 +342,12 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 			      addr, len_ptr, verify);
 	    break;
 #endif /* CFG_CMD_ELF */
+#ifdef CONFIG_ARTOS
+	case IH_OS_ARTOS:
+	    do_bootm_artos  (cmdtp, flag, argc, argv,
+			     addr, len_ptr, verify);
+	    break;
+#endif
 	}
 
 	SHOW_BOOT_PROGRESS (-9);
@@ -710,6 +727,99 @@ do_bootm_netbsd (cmd_tbl_t *cmdtp, int flag,
 	(*loader) (gd->bd, img_addr, consdev, cmdline);
 }
 
+#if defined(CONFIG_ARTOS) && defined(CONFIG_PPC)
+
+/* Function that returns a character from the environment */
+extern uchar (*env_get_char)(int);
+
+static void
+do_bootm_artos (cmd_tbl_t *cmdtp, int flag,
+		int	argc, char *argv[],
+		ulong	addr,
+		ulong	*len_ptr,
+		int	verify)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	ulong top;
+	char *s, *cmdline;
+	char **fwenv, **ss;
+	int i, j, nxt, len, envno, envsz;
+	bd_t *kbd;
+	void (*entry)(bd_t *bd, char *cmdline, char **fwenv, ulong top);
+	image_header_t *hdr = &header;
+
+	/*
+	 * Booting an ARTOS kernel image + application
+	 */
+
+	/* this used to be the top of memory, but was wrong... */
+#ifdef CONFIG_PPC
+	/* get stack pointer */
+	asm volatile ("mr %0,1" : "=r"(top) );
+#endif
+	debug ("## Current stack ends at 0x%08lX ", top);
+
+	top -= 2048;		/* just to be sure */
+	if (top > CFG_BOOTMAPSZ)
+		top = CFG_BOOTMAPSZ;
+	top &= ~0xF;
+
+	debug ("=> set upper limit to 0x%08lX\n", top);
+
+	/* first check the artos specific boot args, then the linux args*/
+	if ((s = getenv("abootargs")) == NULL && (s = getenv("bootargs")) == NULL)
+		s = "";
+
+	/* get length of cmdline, and place it */
+	len = strlen(s);
+	top = (top - (len + 1)) & ~0xF;
+	cmdline = (char *)top;
+	debug ("## cmdline at 0x%08lX ", top);
+	strcpy(cmdline, s);
+
+	/* copy bdinfo */
+	top = (top - sizeof(bd_t)) & ~0xF;
+	debug ("## bd at 0x%08lX ", top);
+	kbd = (bd_t *)top;
+	memcpy(kbd, gd->bd, sizeof(bd_t));
+
+	/* first find number of env entries, and their size */
+	envno = 0;
+	envsz = 0;
+	for (i = 0; env_get_char(i) != '\0'; i = nxt + 1) {
+		for (nxt = i; env_get_char(nxt) != '\0'; ++nxt)
+			;
+		envno++;
+		envsz += (nxt - i) + 1;	/* plus trailing zero */
+	}
+	envno++;	/* plus the terminating zero */
+	debug ("## %u envvars total size %u ", envno, envsz);
+
+	top = (top - sizeof(char **)*envno) & ~0xF;
+	fwenv = (char **)top;
+	debug ("## fwenv at 0x%08lX ", top);
+
+	top = (top - envsz) & ~0xF;
+	s = (char *)top;
+	ss = fwenv;
+
+	/* now copy them */
+	for (i = 0; env_get_char(i) != '\0'; i = nxt + 1) {
+		for (nxt = i; env_get_char(nxt) != '\0'; ++nxt)
+			;
+		*ss++ = s;
+		for (j = i; j < nxt; ++j)
+			*s++ = env_get_char(j);
+		*s++ = '\0';
+	}
+	*ss++ = NULL;	/* terminate */
+
+	entry = (void (*)(bd_t *, char *, char **, ulong))ntohl(hdr->ih_ep);
+	(*entry)(kbd, cmdline, fwenv, top);
+}
+#endif
+
+
 #if (CONFIG_COMMANDS & CFG_CMD_BOOTD)
 int do_bootd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
@@ -831,6 +941,10 @@ print_type (image_header_t *hdr)
 	case IH_OS_VXWORKS:	os = "VxWorks";			break;
 	case IH_OS_QNX:		os = "QNX";			break;
 	case IH_OS_U_BOOT:	os = "U-Boot";			break;
+	case IH_OS_RTEMS:	os = "RTEMS";			break;
+#ifdef CONFIG_ARTOS
+	case IH_OS_ARTOS:	os = "ARTOS";			break;
+#endif
 	default:		os = "Unknown OS";		break;
 	}
 
@@ -953,6 +1067,29 @@ int gunzip(void *dst, int dstlen, unsigned char *src, int *lenp)
 	return (0);
 }
 
+static void
+do_bootm_rtems (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[],
+		ulong addr, ulong *len_ptr, int verify)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	image_header_t *hdr = &header;
+	void	(*entry_point)(bd_t *);
+
+	entry_point = (void (*)(bd_t *)) hdr->ih_ep;
+
+	printf ("## Transferring control to RTEMS (at address %08lx) ...\n",
+		(ulong)entry_point);
+
+	SHOW_BOOT_PROGRESS (15);
+
+	/*
+	 * RTEMS Parameters:
+	 *   r3: ptr to board info data
+	 */
+
+	(*entry_point ) ( gd->bd );
+}
+
 #if (CONFIG_COMMANDS & CFG_CMD_ELF)
 static void
 do_bootm_vxworks (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[],

common/cmd_ide.c

@@ -404,7 +404,8 @@ int do_diskboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 		SHOW_BOOT_PROGRESS (-1);
 		return 1;
 	}
-	if (strncmp(info.type, BOOT_PART_TYPE, sizeof(info.type)) != 0) {
+	if ((strncmp(info.type, BOOT_PART_TYPE, sizeof(info.type)) != 0) &&
+	    (strncmp(info.type, BOOT_PART_COMP, sizeof(info.type)) != 0)) {
 		printf ("\n** Invalid partition type \"%.32s\""
 			" (expect \"" BOOT_PART_TYPE "\")\n",
 			info.type);

common/cmd_pcmcia.c

@@ -72,18 +72,24 @@ int pcmcia_on (void);
 
 #if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
 static int  pcmcia_off (void);
+#endif
+
+#ifdef CONFIG_I82365
+
+extern int i82365_init (void);
+extern void i82365_exit (void);
+
+#else /* ! CONFIG_I82365 */
+
+#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
 static int  hardware_disable(int slot);
 #endif
 static int  hardware_enable (int slot);
 static int  voltage_set(int slot, int vcc, int vpp);
-#ifdef CONFIG_IDE_8xx_PCCARD
-static void print_funcid (int func);
-static void print_fixed  (volatile uchar *p);
-static int  identify     (volatile uchar *p);
-static int  check_ide_device (int slot);
-#endif	/* CONFIG_IDE_8xx_PCCARD */
 
+#ifndef	CONFIG_I82365
 static u_int m8xx_get_graycode(u_int size);
+#endif	/* CONFIG_I82365 */
 #if 0
 static u_int m8xx_get_speed(u_int ns, u_int is_io);
 #endif
@@ -99,6 +105,15 @@ static u_int *pcmcia_pgcrx[2] = {
 
 #define PCMCIA_PGCRX(slot)	(*pcmcia_pgcrx[slot])
 
+#endif /* CONFIG_I82365 */
+
+#ifdef CONFIG_IDE_8xx_PCCARD
+static void print_funcid (int func);
+static void print_fixed  (volatile uchar *p);
+static int  identify     (volatile uchar *p);
+static int  check_ide_device (int slot);
+#endif	/* CONFIG_IDE_8xx_PCCARD */
+
 const char *indent = "\t   ";
 
 /* -------------------------------------------------------------------- */
@@ -128,6 +143,24 @@ int do_pinit (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 /* -------------------------------------------------------------------- */
 
+#ifdef CONFIG_I82365
+int pcmcia_on (void)
+{
+	u_int rc;
+
+	debug ("Enable PCMCIA " PCMCIA_SLOT_MSG "\n");
+
+	rc = i82365_init();
+
+	if (rc == 0)
+	{
+		rc = check_ide_device(0);
+	}
+
+	return (rc);
+}
+#else
+
 #if defined(CONFIG_LWMON)
 # define  CFG_PCMCIA_TIMING	(PCMCIA_SHT(9) | PCMCIA_SST(3) | PCMCIA_SL(12))
 #else
@@ -222,11 +255,22 @@ int pcmcia_on (void)
 	}
 	return (rc);
 }
+#endif /* CONFIG_I82365 */
 
 /* -------------------------------------------------------------------- */
 
 #if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
 
+#ifdef CONFIG_I82365
+static int pcmcia_off (void)
+{
+	printf ("Disable PCMCIA " PCMCIA_SLOT_MSG "\n");
+
+	i82365_exit();
+
+	return 0;
+}
+#else
 static int pcmcia_off (void)
 {
 	int i;
@@ -258,6 +302,7 @@ static int pcmcia_off (void)
 	hardware_disable(_slot_);
 	return 0;
 }
+#endif /* CONFIG_I82365 */
 
 #endif	/* CFG_CMD_PCMCIA */
 
@@ -2215,6 +2260,8 @@ static const u_int m8xx_size_to_gray[M8XX_SIZES_NO] =
 
 /* -------------------------------------------------------------------- */
 
+#ifndef	CONFIG_I82365
+
 static u_int m8xx_get_graycode(u_int size)
 {
 	u_int k;
@@ -2230,6 +2277,8 @@ static u_int m8xx_get_graycode(u_int size)
 	return k;
 }
 
+#endif	/* CONFIG_I82365 */
+
 /* -------------------------------------------------------------------- */
 
 #if 0

common/cmd_scsi.c

@@ -262,7 +262,8 @@ int do_scsiboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 		printf("error reading partinfo\n");
 		return 1;
 	}
-	if (strncmp(info.type, BOOT_PART_TYPE, sizeof(info.type)) != 0) {
+	if ((strncmp(info.type, BOOT_PART_TYPE, sizeof(info.type)) != 0) &&
+	    (strncmp(info.type, BOOT_PART_COMP, sizeof(info.type)) != 0)) {
 		printf ("\n** Invalid partition type \"%.32s\""
 			" (expect \"" BOOT_PART_TYPE "\")\n",
 			info.type);

common/cmd_usb.c

@@ -376,7 +376,8 @@ int do_usbboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 		info.size=2880;
 		printf("error reading partinfo...try to boot raw\n");
 	}
-	if (strncmp(info.type, BOOT_PART_TYPE, sizeof(info.type)) != 0) {
+	if ((strncmp(info.type, BOOT_PART_TYPE, sizeof(info.type)) != 0) &&
+	    (strncmp(info.type, BOOT_PART_COMP, sizeof(info.type)) != 0)) {
 		printf ("\n** Invalid partition type \"%.32s\""
 			" (expect \"" BOOT_PART_TYPE "\")\n",
 			info.type);

common/command.c

@@ -72,6 +72,7 @@
 #include <cmd_vfd.h>		/* load a bitmap to the VFDs on TRAB */
 #include <cmd_log.h>
 #include <cmd_fdos.h>
+#include <cmd_bmp.h>
 
 #ifdef CONFIG_AMIGAONEG3SE
 #include <cmd_menu.h>
@@ -231,6 +232,7 @@ cmd_tbl_t cmd_tbl[] = {
 	CMD_TBL_AUTOSCRIPT
 	CMD_TBL_BASE
 	CMD_TBL_BDINFO
+	CMD_TBL_BMP
 #ifdef CONFIG_AMIGAONEG3SE
 	CMD_TBL_BOOTA
 #endif

common/console.c

@@ -355,7 +355,7 @@ int console_init_f (void)
 	return (0);
 }
 
-#ifdef CFG_CONSOLE_IS_IN_ENV
+#if defined(CFG_CONSOLE_IS_IN_ENV) || defined(CONFIG_SPLASH_SCREEN)
 /* search a device */
 device_t *search_device (int flags, char *name)
 {
@@ -374,7 +374,7 @@ device_t *search_device (int flags, char *name)
 	}
 	return dev;
 }
-#endif /* CFG_CONSOLE_IS_IN_ENV */
+#endif /* CFG_CONSOLE_IS_IN_ENV || CONFIG_SPLASH_SCREEN */
 
 #ifdef CFG_CONSOLE_IS_IN_ENV
 /* Called after the relocation - use desired console functions */
@@ -469,6 +469,11 @@ int console_init_r (void)
 	device_t *inputdev = NULL, *outputdev = NULL;
 	int i, items = ListNumItems (devlist);
 
+#ifdef CONFIG_SPLASH_SCREEN
+	/* suppress all output if splash screen is enabled */
+	outputdev = search_device (DEV_FLAGS_OUTPUT, "nulldev");
+#endif
+
 	/* Scan devices looking for input and output devices */
 	for (i = 1;
 	     (i <= items) && ((inputdev == NULL) || (outputdev == NULL));

common/devices.c

@@ -37,6 +37,11 @@ list_t devlist = 0;
 device_t *stdio_devices[] = { NULL, NULL, NULL };
 char *stdio_names[MAX_FILES] = { "stdin", "stdout", "stderr" };
 
+#if defined(CONFIG_SPLASH_SCREEN) && !defined(CFG_DEVICE_NULLDEV)
+#define	CFG_DEVICE_NULLDEV	1
+#endif
+
+
 #ifdef CFG_DEVICE_NULLDEV
 void nulldev_putc(const char c)
 {

common/main.c

@@ -880,7 +880,7 @@ int do_run (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 			return 1;
 #else
 		if (parse_string_outer(arg,
-		    FLAG_PARSE_SEMICOLON | FLAG_EXIT_FROM_LOOP) == 0)
+		    FLAG_PARSE_SEMICOLON | FLAG_EXIT_FROM_LOOP) != 0)
 			return 1;
 #endif
 	}

cpu/mpc8260/Makefile

@@ -28,7 +28,7 @@ LIB	= lib$(CPU).a
 START	= start.o kgdb.o
 OBJS	= traps.o serial_smc.o serial_scc.o cpu.o cpu_init.o speed.o \
 	  interrupts.o ether_scc.o ether_fcc.o i2c.o commproc.o \
-	  bedbug_603e.o status_led.o pci.o
+	  bedbug_603e.o status_led.o pci.o spi.o
 
 all:	.depend $(START) $(LIB)
 

cpu/mpc8260/cpu.c

@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000
+ * (C) Copyright 2000-2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -22,12 +22,12 @@
  */
 
 /*
- * CPU specific code for the MPC8260
+ * CPU specific code for the MPC8255 / MPC8260 CPUs
  *
  * written or collected and sometimes rewritten by
  * Magnus Damm <damm@bitsmart.com>
  *
- * minor modifications by
+ * modified by
  * Wolfgang Denk <wd@denx.de>
  *
  * modified for 8260 by
@@ -64,7 +64,7 @@ int checkcpu (void)
 	if ((immr & IMMR_ISB_MSK) != CFG_IMMR)
 		return -1;	/* whoops! someone moved the IMMR */
 
-	printf ("MPC8260 (Rev %02x, Mask ", rev);
+	printf (CPU_ID_STR " (Rev %02x, Mask ", rev);
 
 	/*
 	 * the bottom 16 bits of the immr are the Part Number and Mask Number
@@ -101,6 +101,9 @@ int checkcpu (void)
 	case 0x0060:
 		printf ("A.0(A) 2K25A");
 		break;
+	case 0x0062:
+		printf ("B.1 4K25A");
+		break;
 	default:
 		printf ("unknown [immr=0x%04x,k=0x%04x]", m, k);
 		break;

cpu/mpc8260/cpu_init.c

@@ -250,7 +250,7 @@ int prt_8260_rsr (void)
 	int i;
 	char *sep;
 
-	puts ("MPC8260 Reset Status:");
+	puts (CPU_ID_STR " Reset Status:");
 
 	sep = " ";
 	for (i = 0; i < n; i++)

cpu/mpc8260/pci.c

@@ -95,7 +95,11 @@
  */
 
 #define PCI_MSTR_IO_LOCAL       0xA0000000          /* Local base */
+#ifdef CONFIG_ATC
+#define PCI_MSTR_IO_BUS         0x00000000          /* PCI base   */
+#else
 #define PCI_MSTR_IO_BUS         0xA0000000          /* PCI base   */
+#endif
 #define CPU_PCI_IO_START        PCI_MSTR_IO_LOCAL
 #define PCI_MSTR_IO_SIZE        0x10000000          /* 256MB */
 #define POCMR2_MASK_ATTRIB      (POCMR_MASK_256MB | POCMR_ENABLE | POCMR_PCI_IO)

cpu/mpc8260/speed.c

@@ -171,7 +171,7 @@ int prt_8260_clks (void)
 
 	cp = &corecnf_tab[corecnf];
 
-	printf ("MPC8260 Clock Configuration\n - Bus-to-Core Mult ");
+	printf (CPU_ID_STR " Clock Configuration\n - Bus-to-Core Mult ");
 
 	switch (cp->b2c_mult) {
 	case _byp:

cpu/mpc8260/spi.c

@@ -0,0 +1,435 @@
+/*
+ * Copyright (c) 2001 Navin Boppuri / Prashant Patel
+ *	<nboppuri@trinetcommunication.com>,
+ *	<pmpatel@trinetcommunication.com>
+ * Copyright (c) 2001 Gerd Mennchen <Gerd.Mennchen@icn.siemens.de>
+ * Copyright (c) 2001-2003 Wolfgang Denk, DENX Software Engineering, <wd@denx.de>.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * MPC8260 CPM SPI interface.
+ *
+ * Parts of this code are probably not portable and/or specific to
+ * the board which I used for the tests. Please send fixes/complaints
+ * to wd@denx.de
+ *
+ */
+
+#include <common.h>
+#include <asm/cpm_8260.h>
+#include <linux/ctype.h>
+#include <malloc.h>
+#include <post.h>
+#include <net.h>
+
+#if defined(CONFIG_SPI)
+
+/* Warning:
+ * You cannot enable DEBUG for early system initalization, i. e. when
+ * this driver is used to read environment parameters like "baudrate"
+ * from EEPROM which are used to initialize the serial port which is
+ * needed to print the debug messages...
+ */
+#undef	DEBUG
+
+#define SPI_EEPROM_WREN		0x06
+#define SPI_EEPROM_RDSR		0x05
+#define SPI_EEPROM_READ		0x03
+#define SPI_EEPROM_WRITE	0x02
+
+/* ---------------------------------------------------------------
+ * Offset for initial SPI buffers in DPRAM:
+ * We need a 520 byte scratch DPRAM area to use at an early stage.
+ * It is used between the two initialization calls (spi_init_f()
+ * and spi_init_r()).
+ * The value 0x2000 makes it far enough from the start of the data
+ * area (as well as from the stack pointer).
+ * --------------------------------------------------------------- */
+#ifndef	CFG_SPI_INIT_OFFSET
+#define	CFG_SPI_INIT_OFFSET	0x2000
+#endif
+
+#define CPM_SPI_BASE 0x100
+
+#ifdef	DEBUG
+
+#define	DPRINT(a)	printf a;
+/* -----------------------------------------------
+ * Helper functions to peek into tx and rx buffers
+ * ----------------------------------------------- */
+static const char * const hex_digit = "0123456789ABCDEF";
+
+static char quickhex (int i)
+{
+	return hex_digit[i];
+}
+
+static void memdump (void *pv, int num)
+{
+	int i;
+	unsigned char *pc = (unsigned char *) pv;
+
+	for (i = 0; i < num; i++)
+		printf ("%c%c ", quickhex (pc[i] >> 4), quickhex (pc[i] & 0x0f));
+	printf ("\t");
+	for (i = 0; i < num; i++)
+		printf ("%c", isprint (pc[i]) ? pc[i] : '.');
+	printf ("\n");
+}
+#else	/* !DEBUG */
+
+#define	DPRINT(a)
+
+#endif	/* DEBUG */
+
+/* -------------------
+ * Function prototypes
+ * ------------------- */
+void spi_init (void);
+
+ssize_t spi_read (uchar *, int, uchar *, int);
+ssize_t spi_write (uchar *, int, uchar *, int);
+ssize_t spi_xfer (size_t);
+
+/* -------------------
+ * Variables
+ * ------------------- */
+
+#define MAX_BUFFER	0x104
+
+/* ----------------------------------------------------------------------
+ * Initially we place the RX and TX buffers at a fixed location in DPRAM!
+ * ---------------------------------------------------------------------- */
+static uchar *rxbuf =
+  (uchar *)&((immap_t *)CFG_IMMR)->im_dprambase
+			[CFG_SPI_INIT_OFFSET];
+static uchar *txbuf =
+  (uchar *)&((immap_t *)CFG_IMMR)->im_dprambase
+			[CFG_SPI_INIT_OFFSET+MAX_BUFFER];
+
+/* **************************************************************************
+ *
+ *  Function:    spi_init_f
+ *
+ *  Description: Init SPI-Controller (ROM part)
+ *
+ *  return:      ---
+ *
+ * *********************************************************************** */
+void spi_init_f (void)
+{
+	unsigned int dpaddr;
+
+	volatile spi_t *spi;
+	volatile immap_t *immr;
+	volatile cpm8260_t *cp;
+	volatile cbd_t *tbdf, *rbdf;
+
+	immr = (immap_t *)  CFG_IMMR;
+	cp   = (cpm8260_t *) &immr->im_cpm;
+
+	*(ushort *)(&immr->im_dprambase[PROFF_SPI_BASE]) = PROFF_SPI;
+	spi  = (spi_t *)&immr->im_dprambase[PROFF_SPI];
+
+/* 1 */
+	/* ------------------------------------------------
+	 * Initialize Port D SPI pins
+	 * (we are only in Master Mode !)
+	 * ------------------------------------------------ */
+
+	/* --------------------------------------------
+	 * GPIO or per. Function
+	 * PPARD[16] = 1 [0x00008000] (SPIMISO)
+	 * PPARD[17] = 1 [0x00004000] (SPIMOSI)
+	 * PPARD[18] = 1 [0x00002000] (SPICLK)
+	 * PPARD[12] = 0 [0x00080000] -> GPIO: (CS for ATC EEPROM)
+	 * -------------------------------------------- */
+	immr->im_ioport.iop_ppard |=  0x0000E000;	/* set  bits	*/
+	immr->im_ioport.iop_ppard &= ~0x00080000;	/* reset bit	*/
+
+	/* ----------------------------------------------
+	 * In/Out or per. Function 0/1
+	 * PDIRD[16] = 0 [0x00008000] -> PERI1: SPIMISO
+	 * PDIRD[17] = 0 [0x00004000] -> PERI1: SPIMOSI
+	 * PDIRD[18] = 0 [0x00002000] -> PERI1: SPICLK
+	 * PDIRD[12] = 1 [0x00080000] -> GPIO OUT: CS for ATC EEPROM
+	 * ---------------------------------------------- */
+	immr->im_ioport.iop_pdird &= ~0x0000E000;
+	immr->im_ioport.iop_pdird |= 0x00080000;
+
+	/* ----------------------------------------------
+	 * special option reg.
+	 * PSORD[16] = 1 [0x00008000] -> SPIMISO
+	 * PSORD[17] = 1 [0x00004000] -> SPIMOSI
+	 * PSORD[18] = 1 [0x00002000] -> SPICLK
+	 * ---------------------------------------------- */
+	immr->im_ioport.iop_psord |= 0x0000E000;
+
+	/* Initialize the parameter ram.
+	 * We need to make sure many things are initialized to zero
+	 */
+	spi->spi_rstate	= 0;
+	spi->spi_rdp	= 0;
+	spi->spi_rbptr	= 0;
+	spi->spi_rbc	= 0;
+	spi->spi_rxtmp	= 0;
+	spi->spi_tstate	= 0;
+	spi->spi_tdp	= 0;
+	spi->spi_tbptr	= 0;
+	spi->spi_tbc	= 0;
+	spi->spi_txtmp	= 0;
+
+	/* Allocate space for one transmit and one receive buffer
+	 * descriptor in the DP ram
+	 */
+#ifdef CFG_ALLOC_DPRAM
+	dpaddr = m8260_cpm_dpalloc (sizeof(cbd_t)*2, 8);
+#else
+	dpaddr = CPM_SPI_BASE;
+#endif
+
+/* 3 */
+	/* Set up the SPI parameters in the parameter ram */
+	spi->spi_rbase = dpaddr;
+	spi->spi_tbase = dpaddr + sizeof (cbd_t);
+
+	/***********IMPORTANT******************/
+
+        /*
+         * Setting transmit and receive buffer descriptor pointers
+         * initially to rbase and tbase. Only the microcode patches
+         * documentation talks about initializing this pointer. This
+         * is missing from the sample I2C driver. If you dont
+         * initialize these pointers, the kernel hangs.
+	 */
+	spi->spi_rbptr = spi->spi_rbase;
+	spi->spi_tbptr = spi->spi_tbase;
+
+/* 4 */
+	/* Init SPI Tx + Rx Parameters */
+	while (cp->cp_cpcr & CPM_CR_FLG)
+		;
+	cp->cp_cpcr = mk_cr_cmd(CPM_CR_SPI_PAGE, CPM_CR_SPI_SBLOCK,
+							0, CPM_CR_INIT_TRX) | CPM_CR_FLG;
+	while (cp->cp_cpcr & CPM_CR_FLG)
+		;
+
+/* 6 */
+	/* Set to big endian. */
+	spi->spi_tfcr = CPMFCR_EB;
+	spi->spi_rfcr = CPMFCR_EB;
+
+/* 7 */
+	/* Set maximum receive size. */
+	spi->spi_mrblr = MAX_BUFFER;
+
+/* 8 + 9 */
+	/* tx and rx buffer descriptors */
+	tbdf = (cbd_t *) & immr->im_dprambase[spi->spi_tbase];
+	rbdf = (cbd_t *) & immr->im_dprambase[spi->spi_rbase];
+
+	tbdf->cbd_sc &= ~BD_SC_READY;
+	rbdf->cbd_sc &= ~BD_SC_EMPTY;
+
+	/* Set the bd's rx and tx buffer address pointers */
+	rbdf->cbd_bufaddr = (ulong) rxbuf;
+	tbdf->cbd_bufaddr = (ulong) txbuf;
+
+/* 10 + 11 */
+	immr->im_spi.spi_spie = SPI_EMASK;		/* Clear all SPI events	*/
+	immr->im_spi.spi_spim = 0x00;			/* Mask  all SPI events */
+
+
+	return;
+}
+
+/* **************************************************************************
+ *
+ *  Function:    spi_init_r
+ *
+ *  Description: Init SPI-Controller (RAM part) -
+ *		 The malloc engine is ready and we can move our buffers to
+ *		 normal RAM
+ *
+ *  return:      ---
+ *
+ * *********************************************************************** */
+void spi_init_r (void)
+{
+	volatile spi_t *spi;
+	volatile immap_t *immr;
+	volatile cpm8260_t *cp;
+	volatile cbd_t *tbdf, *rbdf;
+
+	immr = (immap_t *)  CFG_IMMR;
+	cp   = (cpm8260_t *) &immr->im_cpm;
+
+	spi  = (spi_t *)&immr->im_dprambase[PROFF_SPI];
+
+	/* tx and rx buffer descriptors */
+	tbdf = (cbd_t *) & immr->im_dprambase[spi->spi_tbase];
+	rbdf = (cbd_t *) & immr->im_dprambase[spi->spi_rbase];
+
+	/* Allocate memory for RX and TX buffers */
+	rxbuf = (uchar *) malloc (MAX_BUFFER);
+	txbuf = (uchar *) malloc (MAX_BUFFER);
+
+	rbdf->cbd_bufaddr = (ulong) rxbuf;
+	tbdf->cbd_bufaddr = (ulong) txbuf;
+
+	return;
+}
+
+/****************************************************************************
+ *  Function:    spi_write
+ **************************************************************************** */
+ssize_t spi_write (uchar *addr, int alen, uchar *buffer, int len)
+{
+	int i;
+
+	memset(rxbuf, 0, MAX_BUFFER);
+	memset(txbuf, 0, MAX_BUFFER);
+	*txbuf = SPI_EEPROM_WREN;		/* write enable		*/
+	spi_xfer(1);
+	memcpy(txbuf, addr, alen);
+	*txbuf = SPI_EEPROM_WRITE;		/* WRITE memory array	*/
+	memcpy(alen + txbuf, buffer, len);
+	spi_xfer(alen + len);
+						/* ignore received data	*/
+	for (i = 0; i < 1000; i++) {
+		*txbuf = SPI_EEPROM_RDSR;	/* read status		*/
+		txbuf[1] = 0;
+		spi_xfer(2);
+		if (!(rxbuf[1] & 1)) {
+			break;
+		}
+		udelay(1000);
+	}
+	if (i >= 1000) {
+		printf ("*** spi_write: Time out while writing!\n");
+	}
+
+	return len;
+}
+
+/****************************************************************************
+ *  Function:    spi_read
+ **************************************************************************** */
+ssize_t spi_read (uchar *addr, int alen, uchar *buffer, int len)
+{
+	memset(rxbuf, 0, MAX_BUFFER);
+	memset(txbuf, 0, MAX_BUFFER);
+	memcpy(txbuf, addr, alen);
+	*txbuf = SPI_EEPROM_READ;		/* READ memory array	*/
+
+	/*
+	 * There is a bug in 860T (?) that cuts the last byte of input
+	 * if we're reading into DPRAM. The solution we choose here is
+	 * to always read len+1 bytes (we have one extra byte at the
+	 * end of the buffer).
+	 */
+	spi_xfer(alen + len + 1);
+	memcpy(buffer, alen + rxbuf, len);
+
+	return len;
+}
+
+/****************************************************************************
+ *  Function:    spi_xfer
+ **************************************************************************** */
+ssize_t spi_xfer (size_t count)
+{
+	volatile immap_t *immr;
+	volatile cpm8260_t *cp;
+	volatile spi_t *spi;
+	cbd_t *tbdf, *rbdf;
+	int tm;
+
+	DPRINT (("*** spi_xfer entered ***\n"));
+
+	immr = (immap_t *) CFG_IMMR;
+	cp   = (cpm8260_t *) &immr->im_cpm;
+
+	spi  = (spi_t *)&immr->im_dprambase[PROFF_SPI];
+
+	tbdf = (cbd_t *) & immr->im_dprambase[spi->spi_tbase];
+	rbdf = (cbd_t *) & immr->im_dprambase[spi->spi_rbase];
+
+	/* Board-specific: Set CS for device (ATC EEPROM) */
+	immr->im_ioport.iop_pdatd &= ~0x00080000;
+
+	/* Setting tx bd status and data length */
+	tbdf->cbd_sc  = BD_SC_READY | BD_SC_LAST | BD_SC_WRAP;
+	tbdf->cbd_datlen = count;
+
+	DPRINT (("*** spi_xfer: Bytes to be xferred: %d ***\n",
+							tbdf->cbd_datlen));
+
+	/* Setting rx bd status and data length */
+	rbdf->cbd_sc = BD_SC_EMPTY | BD_SC_WRAP;
+	rbdf->cbd_datlen = 0;	 /* rx length has no significance */
+
+	immr->im_spi.spi_spmode = SPMODE_REV	|
+			SPMODE_MSTR	|
+			SPMODE_EN	|
+			SPMODE_LEN(8)	|	/* 8 Bits per char */
+			SPMODE_PM(0x8) ;	/* medium speed */
+	immr->im_spi.spi_spie = SPI_EMASK;		/* Clear all SPI events	*/
+	immr->im_spi.spi_spim = 0x00;			/* Mask  all SPI events */
+
+	/* start spi transfer */
+	DPRINT (("*** spi_xfer: Performing transfer ...\n"));
+	immr->im_spi.spi_spcom |= SPI_STR;		/* Start transmit */
+
+	/* --------------------------------
+	 * Wait for SPI transmit to get out
+	 * or time out (1 second = 1000 ms)
+	 * -------------------------------- */
+	for (tm=0; tm<1000; ++tm) {
+		if (immr->im_spi.spi_spie & SPI_TXB) {	/* Tx Buffer Empty */
+			DPRINT (("*** spi_xfer: Tx buffer empty\n"));
+			break;
+		}
+		if ((tbdf->cbd_sc & BD_SC_READY) == 0) {
+			DPRINT (("*** spi_xfer: Tx BD done\n"));
+			break;
+		}
+		udelay (1000);
+	}
+	if (tm >= 1000) {
+		printf ("*** spi_xfer: Time out while xferring to/from SPI!\n");
+	}
+	DPRINT (("*** spi_xfer: ... transfer ended\n"));
+
+#ifdef	DEBUG
+	printf ("\nspi_xfer: txbuf after xfer\n");
+	memdump ((void *) txbuf, 16);	/* dump of txbuf before transmit */
+	printf ("spi_xfer: rxbuf after xfer\n");
+	memdump ((void *) rxbuf, 16);	/* dump of rxbuf after transmit */
+	printf ("\n");
+#endif
+
+	/* Clear CS for device */
+	immr->im_ioport.iop_pdatd |= 0x00080000;
+
+	return count;
+}
+#endif	/* CONFIG_SPI */

cpu/mpc8xx/lcd.c

@@ -27,11 +27,15 @@
 
 #include <config.h>
 #include <common.h>
+#include <watchdog.h>
 #include <version.h>
 #include <stdarg.h>
 #include <lcdvideo.h>
 #include <linux/types.h>
 #include <devices.h>
+#if defined(CONFIG_POST)
+#include <post.h>
+#endif
 
 
 #ifdef CONFIG_LCD
@@ -39,12 +43,10 @@
 /************************************************************************/
 /* ** CONFIG STUFF -- should be moved to board config file		*/
 /************************************************************************/
-#ifndef CONFIG_EDT32F10
 #define CONFIG_LCD_LOGO
 #define LCD_INFO		/* Display Logo, (C) and system info	*/
-#endif
 
-#ifdef CONFIG_V37
+#if defined(CONFIG_V37) || defined(CONFIG_EDT32F10)
 #undef CONFIG_LCD_LOGO
 #undef LCD_INFO
 #endif
@@ -53,6 +55,14 @@
 /* #define CFG_INVERT_COLORS */	/* Not needed - adjust vl_dp instead 	*/
 /************************************************************************/
 
+/************************************************************************/
+/* ** BITMAP DISPLAY SUPPORT  -- should probably be moved elsewhere	*/
+/************************************************************************/
+
+#if (CONFIG_COMMANDS & CFG_CMD_BMP)
+#include <bmp_layout.h>
+#endif /* (CONFIG_COMMANDS & CFG_CMD_BMP) */
+
 /************************************************************************/
 /* ** FONT AND LOGO DATA						*/
 /************************************************************************/
@@ -976,7 +986,11 @@ static void lcd_enable (void)
 
 #if defined(CONFIG_LWMON)
     {	uchar c = pic_read (0x60);
+#if defined(CONFIG_LCD) && defined(CONFIG_LWMON) && (CONFIG_POST & CFG_POST_SYSMON)
+    	c |= 0x04;	/* Chip Enable LCD */
+#else
     	c |= 0x07;	/* Power on CCFL, Enable CCFL, Chip Enable LCD */
+#endif
 	pic_write (0x60, c);
     }
 #endif /* CONFIG_LWMON */
@@ -1046,6 +1060,8 @@ static void bitmap_plot (int x, int y)
 	/* Leave room for default color map */
 	cmap = (ushort *)&(cp->lcd_cmap[BMP_LOGO_OFFSET*sizeof(ushort)]);
 
+	WATCHDOG_RESET();
+
 	/* Set color map */
 	for (i=0; i<(sizeof(bmp_logo_palette)/(sizeof(ushort))); ++i) {
 		ushort colreg = bmp_logo_palette[i];
@@ -1058,14 +1074,117 @@ static void bitmap_plot (int x, int y)
 	bmap = &bmp_logo_bitmap[0];
 	fb   = (char *)(lcd_base + y * lcd_line_length + x);
 
+	WATCHDOG_RESET();
+
 	for (i=0; i<BMP_LOGO_HEIGHT; ++i) {
 		memcpy (fb, bmap, BMP_LOGO_WIDTH);
 		bmap += BMP_LOGO_WIDTH;
 		fb   += panel_info.vl_col;
 	}
+
+	WATCHDOG_RESET();
 }
 #endif /* CONFIG_LCD_LOGO */
 
+#if (CONFIG_COMMANDS & CFG_CMD_BMP)
+/*
+ * Display the BMP file located at address bmp_image.
+ * Only uncompressed
+ */
+int lcd_display_bitmap(ulong bmp_image)
+{
+	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	volatile cpm8xx_t *cp = &(immr->im_cpm);
+	ushort *cmap;
+	ushort i, j;
+	uchar *fb;
+	bmp_image_t *bmp=(bmp_image_t *)bmp_image;
+	uchar *bmap;
+	ushort padded_line;
+	unsigned long width, height;
+	unsigned colors,bpix;
+	unsigned long compression;
+
+	WATCHDOG_RESET();
+
+	if (!((bmp->header.signature[0]=='B') &&
+	      (bmp->header.signature[1]=='M'))) {
+		printf ("Error: no valid bmp image at %lx\n", bmp_image);
+		return 1;
+	}
+
+	width = le32_to_cpu (bmp->header.width);
+	height = le32_to_cpu (bmp->header.height);
+	colors = 1<<le16_to_cpu (bmp->header.bit_count);
+	compression = le32_to_cpu (bmp->header.compression);
+
+	bpix = NBITS(panel_info.vl_bpix);
+
+	if ((bpix != 1) && (bpix != 8)) {
+		printf ("Error: %d bit/pixel mode not supported by U-Boot\n",
+			bpix);
+		return 1;
+	}
+
+	if (bpix != le16_to_cpu(bmp->header.bit_count)) {
+		printf ("Error: %d bit/pixel mode, but BMP has %d bit/pixel\n",
+			bpix,
+			le16_to_cpu(bmp->header.bit_count));
+		return 1;
+	}
+
+	if (compression!=BMP_BI_RGB) {
+		printf ("Error: compression type %ld not supported\n",
+			compression);
+		return 1;
+	}
+
+	debug ("Display-bmp: %d x %d  with %d colors\n",
+	       width, height, colors);
+
+	if (bpix==8) {
+		/* Fill the entire color map */
+		cmap = (ushort *)&(cp->lcd_cmap[255*sizeof(ushort)]);
+
+		/* Set color map */
+		for (i = 0; i < colors; ++i) {
+			bmp_color_table_entry_t cte = bmp->color_table[i];
+			ushort colreg =
+				((cte.red>>4)   << 8) |
+				((cte.green>>4) << 4) |
+				(cte.blue>>4) ;
+#ifdef	CFG_INVERT_COLORS
+			colreg ^= 0xFFF;
+#endif
+			*cmap-- = colreg;
+		}
+
+		WATCHDOG_RESET();
+	}
+
+	padded_line = (width&0x3) ? ((width&~0x3)+4) : (width);
+	if (width>panel_info.vl_col)
+		width = panel_info.vl_col;
+	if (height>panel_info.vl_row)
+		height = panel_info.vl_row;
+
+	bmap = (uchar *)bmp + le32_to_cpu (bmp->header.data_offset);
+	fb   = (uchar *)
+		(lcd_base +
+		 (((height>=panel_info.vl_row) ? panel_info.vl_row : height)-1)
+		 * lcd_line_length);
+	for (i = 0; i < height; ++i) {
+		WATCHDOG_RESET();
+		for (j = 0; j < width ; j++)
+			*(fb++)=255-*(bmap++);
+		bmap += (width - padded_line);
+		fb   -= (width + lcd_line_length);
+	}
+
+	return (0);
+}
+#endif /* (CONFIG_COMMANDS & CFG_CMD_BMP) */
+
 /*----------------------------------------------------------------------*/
 
 static void *lcd_logo (void)
@@ -1077,6 +1196,19 @@ static void *lcd_logo (void)
 	char temp[32];
 #endif /* LCD_INFO */
 
+#ifdef CONFIG_SPLASH_SCREEN
+	char *s;
+	ulong addr;
+
+	if ((s = getenv("splashimage")) != NULL) {
+		addr = simple_strtoul(s, NULL, 16);
+
+		if (lcd_display_bitmap (addr) == 0) {
+			return ((void *)lcd_base);
+		}
+	}
+#endif	/* CONFIG_SPLASH_SCREEN */
+
 #ifdef CONFIG_LCD_LOGO
 	bitmap_plot (0, 0);
 #endif /* CONFIG_LCD_LOGO */
@@ -1086,7 +1218,7 @@ static void *lcd_logo (void)
 	sprintf (info, "%s (%s - %s) ", U_BOOT_VERSION, __DATE__, __TIME__);
 	lcd_drawchars (LCD_INFO_X, LCD_INFO_Y, info, strlen(info));
 
-	sprintf (info, "(C) 2002 DENX Software Engineering");
+	sprintf (info, "(C) 2003 DENX Software Engineering");
 	lcd_drawchars (LCD_INFO_X, LCD_INFO_Y + VIDEO_FONT_HEIGHT,
 					info, strlen(info));
 

cpu/mpc8xx/serial.c

@@ -246,6 +246,20 @@ serial_setbrg (void)
 		(((gd->cpu_clk / 16 / gd->baudrate)-1) << 1) | CPM_BRG_EN;
 }
 
+#ifdef CONFIG_MODEM_SUPPORT
+void disable_putc(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	gd->be_quiet = 1;
+}
+
+void enable_putc(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	gd->be_quiet = 0;
+}
+#endif
+
 void
 serial_putc(const char c)
 {
@@ -255,6 +269,13 @@ serial_putc(const char c)
         volatile immap_t	*im = (immap_t *)CFG_IMMR;
 	volatile cpm8xx_t	*cpmp = &(im->im_cpm);
 
+#ifdef CONFIG_MODEM_SUPPORT
+	DECLARE_GLOBAL_DATA_PTR;
+
+	if (gd->be_quiet)
+		return;
+#endif
+
 	if (c == '\n')
 		serial_putc ('\r');
 

disk/part_dos.c

@@ -169,7 +169,9 @@ static int get_partition_info_extended (block_dev_desc_t *dev_desc, int ext_part
                  * fdisk does not show the extended partitions that
                  * are not in the MBR
 		 */
-		if (pt->sys_ind != 0 && part_num == which_part) {
+		if ((pt->sys_ind != 0) &&
+		    (part_num == which_part) &&
+		    (is_extended(pt->sys_ind) == 0)) {
 			info->blksz = 512;
 			info->start = ext_part_sector + le32_to_int (pt->start4);
 			info->size  = le32_to_int (pt->size4);

doc/README.Purple

@@ -3,12 +3,36 @@ Installation Instructions:
 
 1. Put the s2 switch into the following position:
 
-	 1  0
+	Off On
 	------
 	|x   |
 	|   x|
-	|x   |	
-	|   X|	
+	|x   |
+	|   X|
+	------
+
+   Put the s3 switch into the following position:
+
+	Off On
+	------
+	| x  |
+	| x  |
+	|   x|
+	|   x|
+	------
+
+   Put the s4 switch into the following position:
+
+	Off On
+	------
+	|x   |
+	|x   |
+	|x   |
+	|x   |
+	|x   |
+	|   x|
+	|   x|
+	|x   |
 	------
 
 2. Connect to the serial console and to the BDI. Power on. On the
@@ -34,8 +58,17 @@ Installation Instructions:
 
 	prog 0xB0000000 <u-boot.bin> bin
 
-6. Power off. Restore the original S2 switch position. Power on.
-   U-Boot should come up.
+6. Power off. Restore the original S2 switch position:
+
+	Off On
+	------
+	|   x|
+	|   x|
+	|x   |
+	|   X|
+	------
+
+   Power on.  U-Boot should come up.
 
 
 
@@ -48,5 +81,5 @@ can't really check whether 'erase' is complete by polling flash as it
 is usually done. Instead, the flash driver simply waits for a given
 time and assumes that erase then has passed. This behaviour is
 identical to what the VxWorks driver does; also, the same timeout (6
-seconds) was chosen. Note that this timeout applies for each errase
+seconds) was chosen. Note that this timeout applies for each erase
 operation, i. e. per erased sector.

doc/README.commands

@@ -15,6 +15,7 @@ as		2
 autoscr		5
 base		2
 bdinfo		2
+bmp		3
 bootelf		7
 bootm		5
 bootp		5

drivers/Makefile

@@ -30,8 +30,8 @@ LIB	= libdrivers.a
 OBJS	= 3c589.o 5701rls.o at91rm9200_ether.o \
 	  bcm570x.o bcm570x_autoneg.o \
 	  cfb_console.o cs8900.o ct69000.o dc2114x.o \
-	  eepro100.o i8042.o inca-ip_sw.o \
-	  natsemi.o ns16550.o ns8382x.o ns87308.o \
+	  eepro100.o i8042.o i82365.o inca-ip_sw.o \
+	  lan91c96.o natsemi.o ns16550.o ns8382x.o ns87308.o \
 	  pci.o pci_auto.o pci_indirect.o \
 	  pcnet.o plb2800_eth.o \
 	  s3c24x0_i2c.o sed13806.o serial.o \

drivers/i82365.c

@@ -0,0 +1,590 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ ********************************************************************
+ *
+ * Lots of code copied from:
+ *
+ * i82365.c 1.352 - Linux driver for Intel 82365 and compatible
+ * PC Card controllers, and Yenta-compatible PCI-to-CardBus controllers.
+ * (C) 1999 David A. Hinds <dahinds@users.sourceforge.net>
+ */
+
+#include <common.h>
+
+#ifdef CONFIG_I82365
+
+#include <command.h>
+#include <pci.h>
+#include <pcmcia.h>
+#include <cmd_pcmcia.h>
+#include <asm/io.h>
+
+#include <pcmcia/ss.h>
+#include <pcmcia/i82365.h>
+#include <pcmcia/ti113x.h>
+#include <pcmcia/yenta.h>
+
+/* #define DEBUG */
+
+static struct pci_device_id supported[] = {
+	{PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1510},
+	{0, 0}
+};
+
+#define CYCLE_TIME	120
+
+#ifdef DEBUG
+static void i82365_dump_regions (pci_dev_t dev);
+#endif
+
+typedef struct socket_info_t {
+    pci_dev_t		dev;
+    u_short		bcr;
+    u_char		pci_lat, cb_lat, sub_bus, cache;
+    u_int		cb_phys;
+
+    socket_cap_t	cap;
+    ti113x_state_t	state;
+} socket_info_t;
+
+static socket_info_t socket;
+static socket_state_t state;
+static struct pccard_mem_map mem;
+static struct pccard_io_map io;
+
+/*====================================================================*/
+
+/* Some PCI shortcuts */
+
+static int pci_readb (socket_info_t * s, int r, u_char * v)
+{
+	return pci_read_config_byte (s->dev, r, v);
+}
+static int pci_writeb (socket_info_t * s, int r, u_char v)
+{
+	return pci_write_config_byte (s->dev, r, v);
+}
+static int pci_readw (socket_info_t * s, int r, u_short * v)
+{
+	return pci_read_config_word (s->dev, r, v);
+}
+static int pci_writew (socket_info_t * s, int r, u_short v)
+{
+	return pci_write_config_word (s->dev, r, v);
+}
+static int pci_readl (socket_info_t * s, int r, u_int * v)
+{
+	return pci_read_config_dword (s->dev, r, v);
+}
+static int pci_writel (socket_info_t * s, int r, u_int v)
+{
+	return pci_write_config_dword (s->dev, r, v);
+}
+
+#define cb_readb(s, r)		readb((s)->cb_phys + (r))
+#define cb_readl(s, r)		readl((s)->cb_phys + (r))
+#define cb_writeb(s, r, v)	writeb(v, (s)->cb_phys + (r))
+#define cb_writel(s, r, v)	writel(v, (s)->cb_phys + (r))
+
+/*====================================================================*/
+
+static u_char i365_get (socket_info_t * s, u_short reg)
+{
+	return cb_readb (s, 0x0800 + reg);
+}
+
+static void i365_set (socket_info_t * s, u_short reg, u_char data)
+{
+	cb_writeb (s, 0x0800 + reg, data);
+}
+
+static void i365_bset (socket_info_t * s, u_short reg, u_char mask)
+{
+	i365_set (s, reg, i365_get (s, reg) | mask);
+}
+
+static void i365_bclr (socket_info_t * s, u_short reg, u_char mask)
+{
+	i365_set (s, reg, i365_get (s, reg) & ~mask);
+}
+
+#if 0	/* not used */
+static void i365_bflip (socket_info_t * s, u_short reg, u_char mask, int b)
+{
+	u_char d = i365_get (s, reg);
+
+	i365_set (s, reg, (b) ? (d | mask) : (d & ~mask));
+}
+
+static u_short i365_get_pair (socket_info_t * s, u_short reg)
+{
+	return (i365_get (s, reg) + (i365_get (s, reg + 1) << 8));
+}
+#endif	/* not used */
+
+static void i365_set_pair (socket_info_t * s, u_short reg, u_short data)
+{
+	i365_set (s, reg, data & 0xff);
+	i365_set (s, reg + 1, data >> 8);
+}
+
+/*======================================================================
+
+    Code to save and restore global state information for TI 1130 and
+    TI 1131 controllers, and to set and report global configuration
+    options.
+    
+======================================================================*/
+
+static void ti113x_get_state (socket_info_t * s)
+{
+	ti113x_state_t *p = &s->state;
+
+	pci_readl (s, TI113X_SYSTEM_CONTROL, &p->sysctl);
+	pci_readb (s, TI113X_CARD_CONTROL, &p->cardctl);
+	pci_readb (s, TI113X_DEVICE_CONTROL, &p->devctl);
+	pci_readb (s, TI1250_DIAGNOSTIC, &p->diag);
+	pci_readl (s, TI12XX_IRQMUX, &p->irqmux);
+}
+
+static void ti113x_set_state (socket_info_t * s)
+{
+	ti113x_state_t *p = &s->state;
+
+	pci_writel (s, TI113X_SYSTEM_CONTROL, p->sysctl);
+	pci_writeb (s, TI113X_CARD_CONTROL, p->cardctl);
+	pci_writeb (s, TI113X_DEVICE_CONTROL, p->devctl);
+	pci_writeb (s, TI1250_MULTIMEDIA_CTL, 0);
+	pci_writeb (s, TI1250_DIAGNOSTIC, p->diag);
+	pci_writel (s, TI12XX_IRQMUX, p->irqmux);
+	i365_set_pair (s, TI113X_IO_OFFSET (0), 0);
+	i365_set_pair (s, TI113X_IO_OFFSET (1), 0);
+}
+
+static u_int ti113x_set_opts (socket_info_t * s)
+{
+	ti113x_state_t *p = &s->state;
+	u_int mask = 0xffff;
+
+	p->cardctl &= ~TI113X_CCR_ZVENABLE;
+	p->cardctl |= TI113X_CCR_SPKROUTEN;
+
+	return mask;
+}
+
+/*======================================================================
+
+    Routines to handle common CardBus options
+    
+======================================================================*/
+
+/* Default settings for PCI command configuration register */
+#define CMD_DFLT (PCI_COMMAND_IO|PCI_COMMAND_MEMORY| \
+		  PCI_COMMAND_MASTER|PCI_COMMAND_WAIT)
+
+static void cb_get_state (socket_info_t * s)
+{
+	pci_readb (s, PCI_CACHE_LINE_SIZE, &s->cache);
+	pci_readb (s, PCI_LATENCY_TIMER, &s->pci_lat);
+	pci_readb (s, CB_LATENCY_TIMER, &s->cb_lat);
+	pci_readb (s, CB_CARDBUS_BUS, &s->cap.cardbus);
+	pci_readb (s, CB_SUBORD_BUS, &s->sub_bus);
+	pci_readw (s, CB_BRIDGE_CONTROL, &s->bcr);
+}
+
+static void cb_set_state (socket_info_t * s)
+{
+	pci_writel (s, CB_LEGACY_MODE_BASE, 0);
+	pci_writel (s, PCI_BASE_ADDRESS_0, s->cb_phys);
+	pci_writew (s, PCI_COMMAND, CMD_DFLT);
+	pci_writeb (s, PCI_CACHE_LINE_SIZE, s->cache);
+	pci_writeb (s, PCI_LATENCY_TIMER, s->pci_lat);
+	pci_writeb (s, CB_LATENCY_TIMER, s->cb_lat);
+	pci_writeb (s, CB_CARDBUS_BUS, s->cap.cardbus);
+	pci_writeb (s, CB_SUBORD_BUS, s->sub_bus);
+	pci_writew (s, CB_BRIDGE_CONTROL, s->bcr);
+}
+
+static void cb_set_opts (socket_info_t * s)
+{
+	if (s->cache == 0)
+		s->cache = 8;
+	if (s->pci_lat == 0)
+		s->pci_lat = 0xa8;
+	if (s->cb_lat == 0)
+		s->cb_lat = 0xb0;
+}
+
+/*======================================================================
+
+    Power control for Cardbus controllers: used both for 16-bit and
+    Cardbus cards.
+    
+======================================================================*/
+
+static int cb_set_power (socket_info_t * s, socket_state_t * state)
+{
+	u_int reg = 0;
+
+	/* restart card voltage detection if it seems appropriate */
+	if ((state->Vcc == 0) && (state->Vpp == 0) &&
+		!(cb_readl (s, CB_SOCKET_STATE) & CB_SS_VSENSE))
+		cb_writel (s, CB_SOCKET_FORCE, CB_SF_CVSTEST);
+	switch (state->Vcc) {
+	case 0:
+		reg = 0;
+		break;
+	case 33:
+		reg = CB_SC_VCC_3V;
+		break;
+	case 50:
+		reg = CB_SC_VCC_5V;
+		break;
+	default:
+		return -1;
+	}
+	switch (state->Vpp) {
+	case 0:
+		break;
+	case 33:
+		reg |= CB_SC_VPP_3V;
+		break;
+	case 50:
+		reg |= CB_SC_VPP_5V;
+		break;
+	case 120:
+		reg |= CB_SC_VPP_12V;
+		break;
+	default:
+		return -1;
+	}
+	if (reg != cb_readl (s, CB_SOCKET_CONTROL))
+		cb_writel (s, CB_SOCKET_CONTROL, reg);
+	return 0;
+}
+
+/*======================================================================
+
+    Generic routines to get and set controller options
+    
+======================================================================*/
+
+static void get_bridge_state (socket_info_t * s)
+{
+	ti113x_get_state (s);
+	cb_get_state (s);
+}
+
+static void set_bridge_state (socket_info_t * s)
+{
+	cb_set_state (s);
+	i365_set (s, I365_GBLCTL, 0x00);
+	i365_set (s, I365_GENCTL, 0x00);
+	ti113x_set_state (s);
+}
+
+static void set_bridge_opts (socket_info_t * s)
+{
+	ti113x_set_opts (s);
+	cb_set_opts (s);
+}
+
+/*====================================================================*/
+
+static int i365_get_status (socket_info_t * s, u_int * value)
+{
+	u_int status;
+
+	status = i365_get (s, I365_STATUS);
+	*value = ((status & I365_CS_DETECT) == I365_CS_DETECT) ? SS_DETECT : 0;
+	if (i365_get (s, I365_INTCTL) & I365_PC_IOCARD) {
+		*value |= (status & I365_CS_STSCHG) ? 0 : SS_STSCHG;
+	} else {
+		*value |= (status & I365_CS_BVD1) ? 0 : SS_BATDEAD;
+		*value |= (status & I365_CS_BVD2) ? 0 : SS_BATWARN;
+	}
+	*value |= (status & I365_CS_WRPROT) ? SS_WRPROT : 0;
+	*value |= (status & I365_CS_READY) ? SS_READY : 0;
+	*value |= (status & I365_CS_POWERON) ? SS_POWERON : 0;
+
+	status = cb_readl (s, CB_SOCKET_STATE);
+	*value |= (status & CB_SS_32BIT) ? SS_CARDBUS : 0;
+	*value |= (status & CB_SS_3VCARD) ? SS_3VCARD : 0;
+	*value |= (status & CB_SS_XVCARD) ? SS_XVCARD : 0;
+	*value |= (status & CB_SS_VSENSE) ? 0 : SS_PENDING;
+	/* For now, ignore cards with unsupported voltage keys */
+	if (*value & SS_XVCARD)
+		*value &= ~(SS_DETECT | SS_3VCARD | SS_XVCARD);
+
+	return 0;
+}	/* i365_get_status */
+
+static int i365_set_socket (socket_info_t * s, socket_state_t * state)
+{
+	u_char reg;
+
+	set_bridge_state (s);
+
+	/* IO card, RESET flag */
+	reg = 0;
+	reg |= (state->flags & SS_RESET) ? 0 : I365_PC_RESET;
+	reg |= (state->flags & SS_IOCARD) ? I365_PC_IOCARD : 0;
+	i365_set (s, I365_INTCTL, reg);
+
+	reg = I365_PWR_NORESET;
+	if (state->flags & SS_PWR_AUTO)
+		reg |= I365_PWR_AUTO;
+	if (state->flags & SS_OUTPUT_ENA)
+		reg |= I365_PWR_OUT;
+
+	cb_set_power (s, state);
+	reg |= i365_get (s, I365_POWER) & (I365_VCC_MASK | I365_VPP1_MASK);
+
+	if (reg != i365_get (s, I365_POWER))
+		i365_set (s, I365_POWER, reg);
+
+	return 0;
+}	/* i365_set_socket */
+
+/*====================================================================*/
+
+static int i365_set_mem_map (socket_info_t * s, struct pccard_mem_map *mem)
+{
+	u_short base, i;
+	u_char map;
+
+	map = mem->map;
+	if ((map > 4) ||
+	    (mem->card_start > 0x3ffffff) ||
+	    (mem->sys_start > mem->sys_stop) ||
+	    (mem->speed > 1000)) {
+		return -1;
+	}
+
+	/* Turn off the window before changing anything */
+	if (i365_get (s, I365_ADDRWIN) & I365_ENA_MEM (map))
+		i365_bclr (s, I365_ADDRWIN, I365_ENA_MEM (map));
+
+	/* Take care of high byte, for PCI controllers */
+	i365_set (s, CB_MEM_PAGE (map), mem->sys_start >> 24);
+
+	base = I365_MEM (map);
+	i = (mem->sys_start >> 12) & 0x0fff;
+	if (mem->flags & MAP_16BIT)
+		i |= I365_MEM_16BIT;
+	if (mem->flags & MAP_0WS)
+		i |= I365_MEM_0WS;
+	i365_set_pair (s, base + I365_W_START, i);
+
+	i = (mem->sys_stop >> 12) & 0x0fff;
+	switch (mem->speed / CYCLE_TIME) {
+	case 0:
+		break;
+	case 1:
+		i |= I365_MEM_WS0;
+		break;
+	case 2:
+		i |= I365_MEM_WS1;
+		break;
+	default:
+		i |= I365_MEM_WS1 | I365_MEM_WS0;
+		break;
+	}
+	i365_set_pair (s, base + I365_W_STOP, i);
+
+	i = ((mem->card_start - mem->sys_start) >> 12) & 0x3fff;
+	if (mem->flags & MAP_WRPROT)
+		i |= I365_MEM_WRPROT;
+	if (mem->flags & MAP_ATTRIB)
+		i |= I365_MEM_REG;
+	i365_set_pair (s, base + I365_W_OFF, i);
+
+	/* Turn on the window if necessary */
+	if (mem->flags & MAP_ACTIVE)
+		i365_bset (s, I365_ADDRWIN, I365_ENA_MEM (map));
+	return 0;
+}	/* i365_set_mem_map */
+
+static int i365_set_io_map (socket_info_t * s, struct pccard_io_map *io)
+{
+	u_char map, ioctl;
+
+	map = io->map;
+	if ((map > 1) || (io->start > 0xffff) || (io->stop > 0xffff) ||
+		(io->stop < io->start))
+		return -1;
+	/* Turn off the window before changing anything */
+	if (i365_get (s, I365_ADDRWIN) & I365_ENA_IO (map))
+		i365_bclr (s, I365_ADDRWIN, I365_ENA_IO (map));
+	i365_set_pair (s, I365_IO (map) + I365_W_START, io->start);
+	i365_set_pair (s, I365_IO (map) + I365_W_STOP, io->stop);
+	ioctl = i365_get (s, I365_IOCTL) & ~I365_IOCTL_MASK (map);
+	if (io->speed)
+		ioctl |= I365_IOCTL_WAIT (map);
+	if (io->flags & MAP_0WS)
+		ioctl |= I365_IOCTL_0WS (map);
+	if (io->flags & MAP_16BIT)
+		ioctl |= I365_IOCTL_16BIT (map);
+	if (io->flags & MAP_AUTOSZ)
+		ioctl |= I365_IOCTL_IOCS16 (map);
+	i365_set (s, I365_IOCTL, ioctl);
+	/* Turn on the window if necessary */
+	if (io->flags & MAP_ACTIVE)
+		i365_bset (s, I365_ADDRWIN, I365_ENA_IO (map));
+	return 0;
+}	/* i365_set_io_map */
+
+/*====================================================================*/
+
+int i82365_init (void)
+{
+	u_int val;
+	int i;
+
+	if ((socket.dev = pci_find_devices (supported, 0)) < 0) {
+		/* Controller not found */
+		return 1;
+	}
+
+	pci_read_config_dword (socket.dev, PCI_BASE_ADDRESS_0, &socket.cb_phys);
+	socket.cb_phys &= ~0xf;
+
+	get_bridge_state (&socket);
+	set_bridge_opts (&socket);
+
+	i365_get_status (&socket, &val);
+
+	if (val & SS_DETECT) {
+		if (val & SS_3VCARD) {
+			state.Vcc = state.Vpp = 33;
+			puts (" 3.3V card found: ");
+		} else if (!(val & SS_XVCARD)) {
+			state.Vcc = state.Vpp = 50;
+			puts (" 5.0V card found: ");
+		} else {
+			printf ("i82365: unsupported voltage key\n");
+			state.Vcc = state.Vpp = 0;
+		}
+	} else {
+		/* No card inserted */
+		return 1;
+	}
+
+	state.flags = SS_IOCARD | SS_OUTPUT_ENA;
+	state.csc_mask = 0;
+	state.io_irq = 0;
+
+	i365_set_socket (&socket, &state);
+
+	for (i = 500; i; i--) {
+		if ((i365_get (&socket, I365_STATUS) & I365_CS_READY))
+			break;
+		udelay (1000);
+	}
+
+	if (i == 0) {
+		/* PC Card not ready for data transfer */
+		return 1;
+	}
+
+	mem.map = 0;
+	mem.flags = MAP_ATTRIB | MAP_ACTIVE;
+	mem.speed = 300;
+	mem.sys_start = CFG_PCMCIA_MEM_ADDR;
+	mem.sys_stop = CFG_PCMCIA_MEM_ADDR + CFG_PCMCIA_MEM_SIZE - 1;
+	mem.card_start = 0;
+
+	i365_set_mem_map (&socket, &mem);
+
+	io.map = 0;
+	io.flags = MAP_AUTOSZ | MAP_ACTIVE;
+	io.speed = 0;
+	io.start = 0x0100;
+	io.stop = 0x010F;
+
+	i365_set_io_map (&socket, &io);
+
+#ifdef DEBUG
+	i82365_dump_regions (socket.dev);
+#endif
+
+	return 0;
+}
+
+void i82365_exit (void)
+{
+	io.map = 0;
+	io.flags = 0;
+	io.speed = 0;
+	io.start = 0;
+	io.stop = 0x1;
+
+	i365_set_io_map (&socket, &io);
+
+	mem.map = 0;
+	mem.flags = 0;
+	mem.speed = 0;
+	mem.sys_start = 0;
+	mem.sys_stop = 0x1000;
+	mem.card_start = 0;
+
+	i365_set_mem_map (&socket, &mem);
+
+	socket.state.sysctl &= 0xFFFF00FF;
+
+	state.Vcc = state.Vpp = 0;
+
+	i365_set_socket (&socket, &state);
+}
+
+/*======================================================================
+
+    Debug stuff
+    
+======================================================================*/
+
+#ifdef DEBUG
+static void i82365_dump_regions (pci_dev_t dev)
+{
+	u_int tmp[2];
+	u_int *mem = (void *) sock.cb_phys;
+	u_char *cis = (void *) CFG_PCMCIA_MEM_ADDR;
+	u_char *ide = (void *) (CFG_ATA_BASE_ADDR + CFG_ATA_REG_OFFSET);
+
+	pci_read_config_dword (dev, 0x00, tmp + 0);
+	pci_read_config_dword (dev, 0x80, tmp + 1);
+
+	printf ("PCI CONF: %08X ... %08X\n", tmp[0], tmp[1]);
+	printf ("PCI MEM:  ... %08X ... %08X\n", mem[0x8 / 4], mem[0x800 / 4]);
+	printf ("CIS:      ...%c%c%c%c%c%c%c%c...\n",
+		cis[0x38], cis[0x3a], cis[0x3c], cis[0x3e],
+		cis[0x40], cis[0x42], cis[0x44], cis[0x48]);
+	printf ("CIS CONF: %02X %02X %02X ...\n",
+		cis[0x200], cis[0x202], cis[0x204]);
+	printf ("IDE:      %02X %02X %02X %02X %02X %02X %02X %02X\n",
+		ide[0], ide[1], ide[2], ide[3],
+		ide[4], ide[5], ide[6], ide[7]);
+}
+#endif	/* DEBUG */
+
+#endif /* CONFIG_I82365 */

drivers/lan91c96.c

@@ -0,0 +1,858 @@
+/*------------------------------------------------------------------------
+ * lan91c96.c
+ * This is a driver for SMSC's LAN91C96 single-chip Ethernet device, based
+ * on the SMC91111 driver from U-boot.
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Rolf Offermanns <rof@sysgo.de>
+ *
+ * Copyright (C) 2001 Standard Microsystems Corporation (SMSC)
+ *       Developed by Simple Network Magic Corporation (SNMC)
+ * Copyright (C) 1996 by Erik Stahlman (ES)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ * Information contained in this file was obtained from the LAN91C96
+ * manual from SMC.  To get a copy, if you really want one, you can find
+ * information under www.smsc.com.
+ *
+ *
+ * "Features" of the SMC chip:
+ *   6144 byte packet memory. ( for the 91C96 )
+ *   EEPROM for configuration
+ *   AUI/TP selection  ( mine has 10Base2/10BaseT select )
+ *
+ * Arguments:
+ * 	io	= for the base address
+ *	irq	= for the IRQ
+ *
+ * author:
+ * 	Erik Stahlman				( erik@vt.edu )
+ * 	Daris A Nevil				( dnevil@snmc.com )
+ *
+ *
+ * Hardware multicast code from Peter Cammaert ( pc@denkart.be )
+ *
+ * Sources:
+ *    o   SMSC LAN91C96 databook (www.smsc.com)
+ *    o   smc91111.c (u-boot driver)
+ *    o   smc9194.c (linux kernel driver)
+ *    o   lan91c96.c (Intel Diagnostic Manager driver)
+ *
+ * History:
+ * 	04/30/03  Mathijs Haarman	Modified smc91111.c (u-boot version)
+ *					for lan91c96
+ *---------------------------------------------------------------------------
+ */
+
+#include <common.h>
+#include <command.h>
+#include "lan91c96.h"
+#include <net.h>
+
+#ifdef CONFIG_DRIVER_LAN91C96
+
+#if (CONFIG_COMMANDS & CFG_CMD_NET)
+
+/*------------------------------------------------------------------------
+ *
+ * Configuration options, for the experienced user to change.
+ *
+ -------------------------------------------------------------------------*/
+
+/* Use power-down feature of the chip */
+#define POWER_DOWN	0
+
+/*
+ * Wait time for memory to be free.  This probably shouldn't be
+ * tuned that much, as waiting for this means nothing else happens
+ * in the system
+*/
+#define MEMORY_WAIT_TIME 16
+
+#define SMC_DEBUG 0
+
+#if (SMC_DEBUG > 2 )
+#define PRINTK3(args...) printf(args)
+#else
+#define PRINTK3(args...)
+#endif
+
+#if SMC_DEBUG > 1
+#define PRINTK2(args...) printf(args)
+#else
+#define PRINTK2(args...)
+#endif
+
+#ifdef SMC_DEBUG
+#define PRINTK(args...) printf(args)
+#else
+#define PRINTK(args...)
+#endif
+
+
+/*------------------------------------------------------------------------
+ *
+ * The internal workings of the driver.  If you are changing anything
+ * here with the SMC stuff, you should have the datasheet and know
+ * what you are doing.
+ *
+ *------------------------------------------------------------------------
+ */
+#define CARDNAME "LAN91C96"
+
+#define SMC_BASE_ADDRESS CONFIG_LAN91C96_BASE
+
+#define SMC_DEV_NAME "LAN91C96"
+#define SMC_ALLOC_MAX_TRY 5
+#define SMC_TX_TIMEOUT 30
+
+#define ETH_ZLEN 60
+
+#ifdef  CONFIG_LAN91C96_USE_32_BIT
+#define USE_32_BIT  1
+#else
+#undef USE_32_BIT
+#endif
+
+/*-----------------------------------------------------------------
+ *
+ *  The driver can be entered at any of the following entry points.
+ *
+ *-----------------------------------------------------------------
+ */
+
+extern int eth_init (bd_t * bd);
+extern void eth_halt (void);
+extern int eth_rx (void);
+extern int eth_send (volatile void *packet, int length);
+static int smc_hw_init (void);
+
+/*
+ * This is called by  register_netdev().  It is responsible for
+ * checking the portlist for the SMC9000 series chipset.  If it finds
+ * one, then it will initialize the device, find the hardware information,
+ * and sets up the appropriate device parameters.
+ * NOTE: Interrupts are *OFF* when this procedure is called.
+ *
+ * NB:This shouldn't be static since it is referred to externally.
+ */
+int smc_init (void);
+
+/*
+ * This is called by  unregister_netdev().  It is responsible for
+ * cleaning up before the driver is finally unregistered and discarded.
+ */
+void smc_destructor (void);
+
+/*
+ * The kernel calls this function when someone wants to use the device,
+ * typically 'ifconfig ethX up'.
+ */
+static int smc_open (void);
+
+
+/*
+ * This is called by the kernel in response to 'ifconfig ethX down'.  It
+ * is responsible for cleaning up everything that the open routine
+ * does, and maybe putting the card into a powerdown state.
+ */
+static int smc_close (void);
+
+/*
+ * This is a separate procedure to handle the receipt of a packet, to
+ * leave the interrupt code looking slightly cleaner
+ */
+static int smc_rcv (void);
+
+
+
+/* ------------------------------------------------------------
+ * Internal routines
+ * ------------------------------------------------------------
+ */
+
+static char smc_mac_addr[] = { 0xc0, 0x00, 0x00, 0x1b, 0x62, 0x9c };
+
+/*
+ * This function must be called before smc_open() if you want to override
+ * the default mac address.
+ */
+
+void smc_set_mac_addr (const char *addr)
+{
+	int i;
+
+	for (i = 0; i < sizeof (smc_mac_addr); i++) {
+		smc_mac_addr[i] = addr[i];
+	}
+}
+
+/*
+ * smc_get_macaddr is no longer used. If you want to override the default
+ * mac address, call smc_get_mac_addr as a part of the board initialisation.
+ */
+
+#if 0
+void smc_get_macaddr (byte * addr)
+{
+	/* MAC ADDRESS AT FLASHBLOCK 1 / OFFSET 0x10 */
+	unsigned char *dnp1110_mac = (unsigned char *) (0xE8000000 + 0x20010);
+	int i;
+
+
+	for (i = 0; i < 6; i++) {
+		addr[0] = *(dnp1110_mac + 0);
+		addr[1] = *(dnp1110_mac + 1);
+		addr[2] = *(dnp1110_mac + 2);
+		addr[3] = *(dnp1110_mac + 3);
+		addr[4] = *(dnp1110_mac + 4);
+		addr[5] = *(dnp1110_mac + 5);
+	}
+}
+#endif /* 0 */
+
+/***********************************************
+ * Show available memory                       *
+ ***********************************************/
+void dump_memory_info (void)
+{
+	word mem_info;
+	word old_bank;
+
+	old_bank = SMC_inw (LAN91C96_BANK_SELECT) & 0xF;
+
+	SMC_SELECT_BANK (0);
+	mem_info = SMC_inw (LAN91C96_MIR);
+	PRINTK2 ("Memory: %4d available\n", (mem_info >> 8) * 2048);
+
+	SMC_SELECT_BANK (old_bank);
+}
+
+/*
+ * A rather simple routine to print out a packet for debugging purposes.
+ */
+#if SMC_DEBUG > 2
+static void print_packet (byte *, int);
+#endif
+
+/* #define tx_done(dev) 1 */
+
+
+
+/* this does a soft reset on the device */
+static void smc_reset (void);
+
+/* Enable Interrupts, Receive, and Transmit */
+static void smc_enable (void);
+
+/* this puts the device in an inactive state */
+static void smc_shutdown (void);
+
+
+static int poll4int (byte mask, int timeout)
+{
+	int tmo = get_timer (0) + timeout * CFG_HZ;
+	int is_timeout = 0;
+	word old_bank = SMC_inw (LAN91C96_BANK_SELECT);
+
+	PRINTK2 ("Polling...\n");
+	SMC_SELECT_BANK (2);
+	while ((SMC_inw (LAN91C96_INT_STATS) & mask) == 0) {
+		if (get_timer (0) >= tmo) {
+			is_timeout = 1;
+			break;
+		}
+	}
+
+	/* restore old bank selection */
+	SMC_SELECT_BANK (old_bank);
+
+	if (is_timeout)
+		return 1;
+	else
+		return 0;
+}
+
+/*
+ * Function: smc_reset( void )
+ * Purpose:
+ *  	This sets the SMC91111 chip to its normal state, hopefully from whatever
+ * 	mess that any other DOS driver has put it in.
+ *
+ * Maybe I should reset more registers to defaults in here?  SOFTRST  should
+ * do that for me.
+ *
+ * Method:
+ *	1.  send a SOFT RESET
+ *	2.  wait for it to finish
+ *	3.  enable autorelease mode
+ *	4.  reset the memory management unit
+ *	5.  clear all interrupts
+ *
+*/
+static void smc_reset (void)
+{
+	PRINTK2 ("%s:smc_reset\n", SMC_DEV_NAME);
+
+	/* This resets the registers mostly to defaults, but doesn't
+	   affect EEPROM.  That seems unnecessary */
+	SMC_SELECT_BANK (0);
+	SMC_outw (LAN91C96_RCR_SOFT_RST, LAN91C96_RCR);
+
+	udelay (10);
+
+	/* Disable transmit and receive functionality */
+	SMC_outw (0, LAN91C96_RCR);
+	SMC_outw (0, LAN91C96_TCR);
+
+	/* set the control register */
+	SMC_SELECT_BANK (1);
+	SMC_outw (SMC_inw (LAN91C96_CONTROL) | LAN91C96_CTR_BIT_8,
+			  LAN91C96_CONTROL);
+
+	/* Disable all interrupts */
+	SMC_outb (0, LAN91C96_INT_MASK);
+}
+
+/*
+ * Function: smc_enable
+ * Purpose: let the chip talk to the outside work
+ * Method:
+ *	1.  Initialize the Memory Configuration Register
+ *	2.  Enable the transmitter
+ *	3.  Enable the receiver
+*/
+static void smc_enable ()
+{
+	PRINTK2 ("%s:smc_enable\n", SMC_DEV_NAME);
+	SMC_SELECT_BANK (0);
+
+	/* Initialize the Memory Configuration Register. See page
+	   49 of the LAN91C96 data sheet for details. */
+	SMC_outw (LAN91C96_MCR_TRANSMIT_PAGES, LAN91C96_MCR);
+
+	/* Initialize the Transmit Control Register */
+	SMC_outw (LAN91C96_TCR_TXENA, LAN91C96_TCR);
+	/* Initialize the Receive Control Register
+	 * FIXME:
+	 * The promiscuous bit set because I could not receive ARP reply
+	 * packets from the server when I send a ARP request. It only works
+	 * when I set the promiscuous bit
+	 */
+	SMC_outw (LAN91C96_RCR_RXEN | LAN91C96_RCR_PRMS, LAN91C96_RCR);
+}
+
+/*
+ * Function: smc_shutdown
+ * Purpose:  closes down the SMC91xxx chip.
+ * Method:
+ *	1. zero the interrupt mask
+ *	2. clear the enable receive flag
+ *	3. clear the enable xmit flags
+ *
+ * TODO:
+ *   (1) maybe utilize power down mode.
+ *	Why not yet?  Because while the chip will go into power down mode,
+ *	the manual says that it will wake up in response to any I/O requests
+ *	in the register space.   Empirical results do not show this working.
+ */
+static void smc_shutdown ()
+{
+	PRINTK2 (CARDNAME ":smc_shutdown\n");
+
+	/* no more interrupts for me */
+	SMC_SELECT_BANK (2);
+	SMC_outb (0, LAN91C96_INT_MASK);
+
+	/* and tell the card to stay away from that nasty outside world */
+	SMC_SELECT_BANK (0);
+	SMC_outb (0, LAN91C96_RCR);
+	SMC_outb (0, LAN91C96_TCR);
+}
+
+
+/*
+ * Function:  smc_hardware_send_packet(struct net_device * )
+ * Purpose:
+ *	This sends the actual packet to the SMC9xxx chip.
+ *
+ * Algorithm:
+ * 	First, see if a saved_skb is available.
+ *		( this should NOT be called if there is no 'saved_skb'
+ *	Now, find the packet number that the chip allocated
+ *	Point the data pointers at it in memory
+ *	Set the length word in the chip's memory
+ *	Dump the packet to chip memory
+ *	Check if a last byte is needed ( odd length packet )
+ *		if so, set the control flag right
+ * 	Tell the card to send it
+ *	Enable the transmit interrupt, so I know if it failed
+ * 	Free the kernel data if I actually sent it.
+ */
+static int smc_send_packet (volatile void *packet, int packet_length)
+{
+	byte packet_no;
+	unsigned long ioaddr;
+	byte *buf;
+	int length;
+	int numPages;
+	int try = 0;
+	int time_out;
+	byte status;
+
+
+	PRINTK3 ("%s:smc_hardware_send_packet\n", SMC_DEV_NAME);
+
+	length = ETH_ZLEN < packet_length ? packet_length : ETH_ZLEN;
+
+	/* allocate memory
+	 ** The MMU wants the number of pages to be the number of 256 bytes
+	 ** 'pages', minus 1 ( since a packet can't ever have 0 pages :) )
+	 **
+	 ** The 91C111 ignores the size bits, but the code is left intact
+	 ** for backwards and future compatibility.
+	 **
+	 ** Pkt size for allocating is data length +6 (for additional status
+	 ** words, length and ctl!)
+	 **
+	 ** If odd size then last byte is included in this header.
+	 */
+	numPages = ((length & 0xfffe) + 6);
+	numPages >>= 8;				/* Divide by 256 */
+
+	if (numPages > 7) {
+		printf ("%s: Far too big packet error. \n", SMC_DEV_NAME);
+		return 0;
+	}
+
+	/* now, try to allocate the memory */
+
+	SMC_SELECT_BANK (2);
+	SMC_outw (LAN91C96_MMUCR_ALLOC_TX | numPages, LAN91C96_MMU);
+
+  again:
+	try++;
+	time_out = MEMORY_WAIT_TIME;
+	do {
+		status = SMC_inb (LAN91C96_INT_STATS);
+		if (status & LAN91C96_IST_ALLOC_INT) {
+
+			SMC_outb (LAN91C96_IST_ALLOC_INT, LAN91C96_INT_STATS);
+			break;
+		}
+	} while (--time_out);
+
+	if (!time_out) {
+		PRINTK2 ("%s: memory allocation, try %d failed ...\n",
+				 SMC_DEV_NAME, try);
+		if (try < SMC_ALLOC_MAX_TRY)
+			goto again;
+		else
+			return 0;
+	}
+
+	PRINTK2 ("%s: memory allocation, try %d succeeded ...\n",
+			 SMC_DEV_NAME, try);
+
+	/* I can send the packet now.. */
+
+	ioaddr = SMC_BASE_ADDRESS;
+
+	buf = (byte *) packet;
+
+	/* If I get here, I _know_ there is a packet slot waiting for me */
+	packet_no = SMC_inb (LAN91C96_ARR);
+	if (packet_no & LAN91C96_ARR_FAILED) {
+		/* or isn't there?  BAD CHIP! */
+		printf ("%s: Memory allocation failed. \n", SMC_DEV_NAME);
+		return 0;
+	}
+
+	/* we have a packet address, so tell the card to use it */
+	SMC_outb (packet_no, LAN91C96_PNR);
+
+	/* point to the beginning of the packet */
+	SMC_outw (LAN91C96_PTR_AUTO_INCR, LAN91C96_POINTER);
+
+	PRINTK3 ("%s: Trying to xmit packet of length %x\n",
+			 SMC_DEV_NAME, length);
+
+#if SMC_DEBUG > 2
+	printf ("Transmitting Packet\n");
+	print_packet (buf, length);
+#endif
+
+	/* send the packet length ( +6 for status, length and ctl byte )
+	   and the status word ( set to zeros ) */
+#ifdef USE_32_BIT
+	SMC_outl ((length + 6) << 16, LAN91C96_DATA_HIGH);
+#else
+	SMC_outw (0, LAN91C96_DATA_HIGH);
+	/* send the packet length ( +6 for status words, length, and ctl */
+	SMC_outw ((length + 6), LAN91C96_DATA_HIGH);
+#endif /* USE_32_BIT */
+
+	/* send the actual data
+	 * I _think_ it's faster to send the longs first, and then
+	 * mop up by sending the last word.  It depends heavily
+	 * on alignment, at least on the 486.  Maybe it would be
+	 * a good idea to check which is optimal?  But that could take
+	 * almost as much time as is saved?
+	 */
+#ifdef USE_32_BIT
+	SMC_outsl (LAN91C96_DATA_HIGH, buf, length >> 2);
+	if (length & 0x2)
+		SMC_outw (*((word *) (buf + (length & 0xFFFFFFFC))),
+				  LAN91C96_DATA_HIGH);
+#else
+	SMC_outsw (LAN91C96_DATA_HIGH, buf, (length) >> 1);
+#endif /* USE_32_BIT */
+
+	/* Send the last byte, if there is one.   */
+	if ((length & 1) == 0) {
+		SMC_outw (0, LAN91C96_DATA_HIGH);
+	} else {
+		SMC_outw (buf[length - 1] | 0x2000, LAN91C96_DATA_HIGH);
+	}
+
+	/* and let the chipset deal with it */
+	SMC_outw (LAN91C96_MMUCR_ENQUEUE, LAN91C96_MMU);
+
+	/* poll for TX INT */
+	if (poll4int (LAN91C96_MSK_TX_INT, SMC_TX_TIMEOUT)) {
+		/* sending failed */
+		PRINTK2 ("%s: TX timeout, sending failed...\n", SMC_DEV_NAME);
+
+		/* release packet */
+		SMC_outw (LAN91C96_MMUCR_RELEASE_TX, LAN91C96_MMU);
+
+		/* wait for MMU getting ready (low) */
+		while (SMC_inw (LAN91C96_MMU) & LAN91C96_MMUCR_NO_BUSY) {
+			udelay (10);
+		}
+
+		PRINTK2 ("MMU ready\n");
+
+
+		return 0;
+	} else {
+		/* ack. int */
+		SMC_outw (LAN91C96_IST_TX_INT, LAN91C96_INT_STATS);
+
+		PRINTK2 ("%s: Sent packet of length %d \n", SMC_DEV_NAME, length);
+
+		/* release packet */
+		SMC_outw (LAN91C96_MMUCR_RELEASE_TX, LAN91C96_MMU);
+
+		/* wait for MMU getting ready (low) */
+		while (SMC_inw (LAN91C96_MMU) & LAN91C96_MMUCR_NO_BUSY) {
+			udelay (10);
+		}
+
+		PRINTK2 ("MMU ready\n");
+	}
+
+	return length;
+}
+
+/*-------------------------------------------------------------------------
+ * smc_destructor( struct net_device * dev )
+ *   Input parameters:
+ *	dev, pointer to the device structure
+ *
+ *   Output:
+ *	None.
+ *--------------------------------------------------------------------------
+ */
+void smc_destructor ()
+{
+	PRINTK2 (CARDNAME ":smc_destructor\n");
+}
+
+
+/*
+ * Open and Initialize the board
+ *
+ * Set up everything, reset the card, etc ..
+ *
+ */
+static int smc_open ()
+{
+	int i;			/* used to set hw ethernet address */
+
+	PRINTK2 ("%s:smc_open\n", SMC_DEV_NAME);
+
+	/* reset the hardware */
+
+	smc_reset ();
+	smc_enable ();
+
+	SMC_SELECT_BANK (1);
+
+	for (i = 0; i < 6; i += 2) {
+		word address;
+
+		address = smc_mac_addr[i + 1] << 8;
+		address |= smc_mac_addr[i];
+		SMC_outw (address, LAN91C96_IA0 + i);
+	}
+	return 0;
+}
+
+/*-------------------------------------------------------------
+ *
+ * smc_rcv -  receive a packet from the card
+ *
+ * There is ( at least ) a packet waiting to be read from
+ * chip-memory.
+ *
+ * o Read the status
+ * o If an error, record it
+ * o otherwise, read in the packet
+ *-------------------------------------------------------------
+ */
+static int smc_rcv ()
+{
+	int packet_number;
+	word status;
+	word packet_length;
+	int is_error = 0;
+
+#ifdef USE_32_BIT
+	dword stat_len;
+#endif
+
+
+	SMC_SELECT_BANK (2);
+	packet_number = SMC_inw (LAN91C96_FIFO);
+
+	if (packet_number & LAN91C96_FIFO_RXEMPTY) {
+		return 0;
+	}
+
+	PRINTK3 ("%s:smc_rcv\n", SMC_DEV_NAME);
+	/*  start reading from the start of the packet */
+	SMC_outw (LAN91C96_PTR_READ | LAN91C96_PTR_RCV |
+			  LAN91C96_PTR_AUTO_INCR, LAN91C96_POINTER);
+
+	/* First two words are status and packet_length */
+#ifdef USE_32_BIT
+	stat_len = SMC_inl (LAN91C96_DATA_HIGH);
+	status = stat_len & 0xffff;
+	packet_length = stat_len >> 16;
+#else
+	status = SMC_inw (LAN91C96_DATA_HIGH);
+	packet_length = SMC_inw (LAN91C96_DATA_HIGH);
+#endif
+
+	packet_length &= 0x07ff;	/* mask off top bits */
+
+	PRINTK2 ("RCV: STATUS %4x LENGTH %4x\n", status, packet_length);
+
+	if (!(status & FRAME_FILTER)) {
+		/* Adjust for having already read the first two words */
+		packet_length -= 4;		/*4; */
+
+
+
+		/* set odd length for bug in LAN91C111, */
+		/* which never sets RS_ODDFRAME */
+		/* TODO ? */
+
+
+#ifdef USE_32_BIT
+		PRINTK3 (" Reading %d dwords (and %d bytes) \n",
+			 packet_length >> 2, packet_length & 3);
+		/* QUESTION:  Like in the TX routine, do I want
+		   to send the DWORDs or the bytes first, or some
+		   mixture.  A mixture might improve already slow PIO
+		   performance  */
+		SMC_insl (LAN91C96_DATA_HIGH, NetRxPackets[0], packet_length >> 2);
+		/* read the left over bytes */
+		if (packet_length & 3) {
+			int i;
+
+			byte *tail = (byte *) (NetRxPackets[0] + (packet_length & ~3));
+			dword leftover = SMC_inl (LAN91C96_DATA_HIGH);
+
+			for (i = 0; i < (packet_length & 3); i++)
+				*tail++ = (byte) (leftover >> (8 * i)) & 0xff;
+		}
+#else
+		PRINTK3 (" Reading %d words and %d byte(s) \n",
+				 (packet_length >> 1), packet_length & 1);
+		SMC_insw (LAN91C96_DATA_HIGH, NetRxPackets[0], packet_length >> 1);
+
+#endif /* USE_32_BIT */
+
+#if	SMC_DEBUG > 2
+		printf ("Receiving Packet\n");
+		print_packet (NetRxPackets[0], packet_length);
+#endif
+	} else {
+		/* error ... */
+		/* TODO ? */
+		is_error = 1;
+	}
+
+	while (SMC_inw (LAN91C96_MMU) & LAN91C96_MMUCR_NO_BUSY)
+		udelay (1);		/* Wait until not busy */
+
+	/*  error or good, tell the card to get rid of this packet */
+	SMC_outw (LAN91C96_MMUCR_RELEASE_RX, LAN91C96_MMU);
+
+	while (SMC_inw (LAN91C96_MMU) & LAN91C96_MMUCR_NO_BUSY)
+		udelay (1);		/* Wait until not busy */
+
+	if (!is_error) {
+		/* Pass the packet up to the protocol layers. */
+		NetReceive (NetRxPackets[0], packet_length);
+		return packet_length;
+	} else {
+		return 0;
+	}
+
+}
+
+/*----------------------------------------------------
+ * smc_close
+ *
+ * this makes the board clean up everything that it can
+ * and not talk to the outside world.   Caused by
+ * an 'ifconfig ethX down'
+ *
+ -----------------------------------------------------*/
+static int smc_close ()
+{
+	PRINTK2 ("%s:smc_close\n", SMC_DEV_NAME);
+
+	/* clear everything */
+	smc_shutdown ();
+
+	return 0;
+}
+
+#if SMC_DEBUG > 2
+static void print_packet (byte * buf, int length)
+{
+#if 0
+	int i;
+	int remainder;
+	int lines;
+
+	printf ("Packet of length %d \n", length);
+
+	lines = length / 16;
+	remainder = length % 16;
+
+	for (i = 0; i < lines; i++) {
+		int cur;
+
+		for (cur = 0; cur < 8; cur++) {
+			byte a, b;
+
+			a = *(buf++);
+			b = *(buf++);
+			printf ("%02x%02x ", a, b);
+		}
+		printf ("\n");
+	}
+	for (i = 0; i < remainder / 2; i++) {
+		byte a, b;
+
+		a = *(buf++);
+		b = *(buf++);
+		printf ("%02x%02x ", a, b);
+	}
+	printf ("\n");
+#endif /* 0 */
+}
+#endif /* SMC_DEBUG > 2 */
+
+int eth_init (bd_t * bd)
+{
+	smc_open ();
+	return 0;
+}
+
+void eth_halt ()
+{
+	smc_close ();
+}
+
+int eth_rx ()
+{
+	return smc_rcv ();
+}
+
+int eth_send (volatile void *packet, int length)
+{
+	return smc_send_packet (packet, length);
+}
+
+int eth_hw_init ()
+{
+	return smc_hw_init ();
+}
+
+/*-------------------------------------------------------------------------
+ * smc_hw_init()
+ *
+ *   Function:
+ *      Reset and enable the device, check if the I/O space location
+ *      is correct
+ *
+ *   Input parameters:
+ *      None
+ *
+ *   Output:
+ *	0 --> success
+ *	1 --> error
+ *--------------------------------------------------------------------------
+ */
+static int smc_hw_init ()
+{
+	unsigned short status_test;
+
+	/* The attribute register of the LAN91C96 is located at address
+	   0x0e000000 on the lubbock platform */
+	volatile unsigned *attaddr = (unsigned *) (0x0e000000);
+
+	/* first reset, then enable the device. Sequence is critical */
+	attaddr[LAN91C96_ECOR] |= LAN91C96_ECOR_SRESET;
+	udelay (100);
+	attaddr[LAN91C96_ECOR] &= ~LAN91C96_ECOR_SRESET;
+	attaddr[LAN91C96_ECOR] |= LAN91C96_ECOR_ENABLE;
+
+	/* force 16-bit mode */
+	attaddr[LAN91C96_ECSR] &= ~LAN91C96_ECSR_IOIS8;
+	udelay (100);
+
+	/* check if the I/O address is correct, the upper byte of the
+	   bank select register should read 0x33 */
+
+	status_test = SMC_inw (LAN91C96_BANK_SELECT);
+	if ((status_test & 0xFF00) != 0x3300) {
+		printf ("Failed to initialize ethernetchip\n");
+		return 1;
+	}
+	return 0;
+}
+
+#endif /* COMMANDS & CFG_NET */
+
+#endif /* CONFIG_DRIVER_LAN91C96 */

drivers/lan91c96.h

@@ -0,0 +1,635 @@
+/*------------------------------------------------------------------------
+ * lan91c96.h
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Rolf Offermanns <rof@sysgo.de>
+ * Copyright (C) 2001 Standard Microsystems Corporation (SMSC)
+ *       Developed by Simple Network Magic Corporation (SNMC)
+ * Copyright (C) 1996 by Erik Stahlman (ES)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ * This file contains register information and access macros for
+ * the LAN91C96 single chip ethernet controller.  It is a modified
+ * version of the smc9111.h file.
+ *
+ * Information contained in this file was obtained from the LAN91C96
+ * manual from SMC. To get a copy, if you really want one, you can find
+ * information under www.smsc.com.
+ *
+ * Authors
+ * 	Erik Stahlman				( erik@vt.edu )
+ *	Daris A Nevil				( dnevil@snmc.com )
+ *
+ * History
+ * 04/30/03	Mathijs Haarman		Modified smc91111.h (u-boot version)
+ *		                        for lan91c96
+ *-------------------------------------------------------------------------
+ */
+#ifndef _LAN91C96_H_
+#define _LAN91C96_H_
+
+#include <asm/types.h>
+#include <asm/io.h>
+#include <config.h>
+
+/*
+ * This function may be called by the board specific initialisation code
+ * in order to override the default mac address.
+ */
+
+void smc_set_mac_addr(const char *addr);
+int eth_hw_init(void);
+
+
+/* I want some simple types */
+
+typedef unsigned char			byte;
+typedef unsigned short			word;
+typedef unsigned long int 		dword;
+
+/*
+ * DEBUGGING LEVELS
+ *
+ * 0 for normal operation
+ * 1 for slightly more details
+ * >2 for various levels of increasingly useless information
+ *    2 for interrupt tracking, status flags
+ *    3 for packet info
+ *    4 for complete packet dumps
+ */
+/*#define SMC_DEBUG 0 */
+
+/* Because of bank switching, the LAN91xxx uses only 16 I/O ports */
+
+#define	SMC_IO_EXTENT	16
+
+#ifdef CONFIG_PXA250
+
+#define	SMC_inl(r) 	(*((volatile dword *)(SMC_BASE_ADDRESS+( r * 4 ))))
+#define	SMC_inw(r) 	(*((volatile word *)(SMC_BASE_ADDRESS+( r * 4 ))))
+#define SMC_inb(p)	({ \
+	unsigned int __p = (unsigned int)(SMC_BASE_ADDRESS + (p * 4)); \
+	unsigned int __v = *(volatile unsigned short *)((__p) & ~1); \
+	if (__p & 1) __v >>= 8; \
+	else __v &= 0xff; \
+	__v; })
+
+#define	SMC_outl(d,r)	(*((volatile dword *)(SMC_BASE_ADDRESS+(r * 4))) = d)
+#define	SMC_outw(d,r)	(*((volatile word *)(SMC_BASE_ADDRESS+(r * 4))) = d)
+#define	SMC_outb(d,r)	({	word __d = (byte)(d);  \
+				word __w = SMC_inw((r)&~1);  \
+				__w &= ((r)&1) ? 0x00FF : 0xFF00;  \
+				__w |= ((r)&1) ? __d<<8 : __d;  \
+				SMC_outw(__w,(r)&~1);  \
+			})
+
+#define SMC_outsl(r,b,l)	({	int __i; \
+					dword *__b2; \
+					__b2 = (dword *) b; \
+					for (__i = 0; __i < l; __i++) { \
+					    SMC_outl( *(__b2 + __i), r ); \
+					} \
+				})
+
+#define SMC_outsw(r,b,l)	({	int __i; \
+					word *__b2; \
+					__b2 = (word *) b; \
+					for (__i = 0; __i < l; __i++) { \
+					    SMC_outw( *(__b2 + __i), r ); \
+					} \
+				})
+
+#define SMC_insl(r,b,l) 	({	int __i ;  \
+					dword *__b2;  \
+			    		__b2 = (dword *) b;  \
+			    		for (__i = 0; __i < l; __i++) {  \
+					  *(__b2 + __i) = SMC_inl(r);  \
+					  SMC_inl(0);  \
+					};  \
+				})
+
+#define SMC_insw(r,b,l) 	({	int __i ;  \
+					word *__b2;  \
+			    		__b2 = (word *) b;  \
+			    		for (__i = 0; __i < l; __i++) {  \
+					  *(__b2 + __i) = SMC_inw(r);  \
+					  SMC_inw(0);  \
+					};  \
+				})
+
+#define SMC_insb(r,b,l) 	({	int __i ;  \
+					byte *__b2;  \
+			    		__b2 = (byte *) b;  \
+			    		for (__i = 0; __i < l; __i++) {  \
+					  *(__b2 + __i) = SMC_inb(r);  \
+					  SMC_inb(0);  \
+					};  \
+				})
+
+#else /* if not CONFIG_PXA250 */
+
+/*
+ * We have only 16 Bit PCMCIA access on Socket 0
+ */
+
+#define	SMC_inw(r) 	(*((volatile word *)(SMC_BASE_ADDRESS+(r))))
+#define  SMC_inb(r)	(((r)&1) ? SMC_inw((r)&~1)>>8 : SMC_inw(r)&0xFF)
+
+#define	SMC_outw(d,r)	(*((volatile word *)(SMC_BASE_ADDRESS+(r))) = d)
+#define	SMC_outb(d,r)	({	word __d = (byte)(d);  \
+				word __w = SMC_inw((r)&~1);  \
+				__w &= ((r)&1) ? 0x00FF : 0xFF00;  \
+				__w |= ((r)&1) ? __d<<8 : __d;  \
+				SMC_outw(__w,(r)&~1);  \
+			})
+#if 0
+#define	SMC_outsw(r,b,l)	outsw(SMC_BASE_ADDRESS+(r), (b), (l))
+#else
+#define SMC_outsw(r,b,l)	({	int __i; \
+					word *__b2; \
+					__b2 = (word *) b; \
+					for (__i = 0; __i < l; __i++) { \
+					    SMC_outw( *(__b2 + __i), r); \
+					} \
+				})
+#endif
+
+#if 0
+#define	SMC_insw(r,b,l) 	insw(SMC_BASE_ADDRESS+(r), (b), (l))
+#else
+#define SMC_insw(r,b,l) 	({	int __i ;  \
+					word *__b2;  \
+			    		__b2 = (word *) b;  \
+			    		for (__i = 0; __i < l; __i++) {  \
+					  *(__b2 + __i) = SMC_inw(r);  \
+					  SMC_inw(0);  \
+					};  \
+				})
+#endif
+
+#endif
+
+/*
+ ****************************************************************************
+ *	Bank Select Field
+ ****************************************************************************
+ */
+#define LAN91C96_BANK_SELECT  14       // Bank Select Register
+#define LAN91C96_BANKSELECT (0x3UC << 0)
+#define BANK0               0x00
+#define BANK1               0x01
+#define BANK2               0x02
+#define BANK3               0x03
+#define BANK4               0x04
+
+/*
+ ****************************************************************************
+ *	EEPROM Addresses.
+ ****************************************************************************
+ */
+#define EEPROM_MAC_OFFSET_1    0x6020
+#define EEPROM_MAC_OFFSET_2    0x6021
+#define EEPROM_MAC_OFFSET_3    0x6022
+
+/*
+ ****************************************************************************
+ *	Bank 0 Register Map in I/O Space
+ ****************************************************************************
+ */
+#define LAN91C96_TCR          0        // Transmit Control Register
+#define LAN91C96_EPH_STATUS   2        // EPH Status Register
+#define LAN91C96_RCR          4        // Receive Control Register
+#define LAN91C96_COUNTER      6        // Counter Register
+#define LAN91C96_MIR          8        // Memory Information Register
+#define LAN91C96_MCR          10       // Memory Configuration Register
+
+/*
+ ****************************************************************************
+ *	Transmit Control Register - Bank 0 - Offset 0
+ ****************************************************************************
+ */
+#define LAN91C96_TCR_TXENA        (0x1U << 0)
+#define LAN91C96_TCR_LOOP         (0x1U << 1)
+#define LAN91C96_TCR_FORCOL       (0x1U << 2)
+#define LAN91C96_TCR_TXP_EN       (0x1U << 3)
+#define LAN91C96_TCR_PAD_EN       (0x1U << 7)
+#define LAN91C96_TCR_NOCRC        (0x1U << 8)
+#define LAN91C96_TCR_MON_CSN      (0x1U << 10)
+#define LAN91C96_TCR_FDUPLX       (0x1U << 11)
+#define LAN91C96_TCR_STP_SQET     (0x1U << 12)
+#define LAN91C96_TCR_EPH_LOOP     (0x1U << 13)
+#define LAN91C96_TCR_ETEN_TYPE    (0x1U << 14)
+#define LAN91C96_TCR_FDSE         (0x1U << 15)
+
+/*
+ ****************************************************************************
+ *	EPH Status Register - Bank 0 - Offset 2
+ ****************************************************************************
+ */
+#define LAN91C96_EPHSR_TX_SUC     (0x1U << 0)
+#define LAN91C96_EPHSR_SNGL_COL   (0x1U << 1)
+#define LAN91C96_EPHSR_MUL_COL    (0x1U << 2)
+#define LAN91C96_EPHSR_LTX_MULT   (0x1U << 3)
+#define LAN91C96_EPHSR_16COL      (0x1U << 4)
+#define LAN91C96_EPHSR_SQET       (0x1U << 5)
+#define LAN91C96_EPHSR_LTX_BRD    (0x1U << 6)
+#define LAN91C96_EPHSR_TX_DEFR    (0x1U << 7)
+#define LAN91C96_EPHSR_WAKEUP     (0x1U << 8)
+#define LAN91C96_EPHSR_LATCOL     (0x1U << 9)
+#define LAN91C96_EPHSR_LOST_CARR  (0x1U << 10)
+#define LAN91C96_EPHSR_EXC_DEF    (0x1U << 11)
+#define LAN91C96_EPHSR_CTR_ROL    (0x1U << 12)
+
+#define LAN91C96_EPHSR_LINK_OK    (0x1U << 14)
+#define LAN91C96_EPHSR_TX_UNRN    (0x1U << 15)
+
+#define LAN91C96_EPHSR_ERRORS     (LAN91C96_EPHSR_SNGL_COL  |    \
+                                   LAN91C96_EPHSR_MUL_COL   |    \
+                                   LAN91C96_EPHSR_16COL     |    \
+                                   LAN91C96_EPHSR_SQET      |    \
+                                   LAN91C96_EPHSR_TX_DEFR   |    \
+                                   LAN91C96_EPHSR_LATCOL    |    \
+                                   LAN91C96_EPHSR_LOST_CARR |    \
+                                   LAN91C96_EPHSR_EXC_DEF   |    \
+                                   LAN91C96_EPHSR_LINK_OK   |    \
+                                   LAN91C96_EPHSR_TX_UNRN)
+
+/*
+ ****************************************************************************
+ *	Receive Control Register - Bank 0 - Offset 4
+ ****************************************************************************
+ */
+#define LAN91C96_RCR_RX_ABORT     (0x1U << 0)
+#define LAN91C96_RCR_PRMS         (0x1U << 1)
+#define LAN91C96_RCR_ALMUL        (0x1U << 2)
+#define LAN91C96_RCR_RXEN         (0x1U << 8)
+#define LAN91C96_RCR_STRIP_CRC    (0x1U << 9)
+#define LAN91C96_RCR_FILT_CAR     (0x1U << 14)
+#define LAN91C96_RCR_SOFT_RST     (0x1U << 15)
+
+/*
+ ****************************************************************************
+ *	Counter Register - Bank 0 - Offset 6
+ ****************************************************************************
+ */
+#define LAN91C96_ECR_SNGL_COL     (0xFU << 0)
+#define LAN91C96_ECR_MULT_COL     (0xFU << 5)
+#define LAN91C96_ECR_DEF_TX       (0xFU << 8)
+#define LAN91C96_ECR_EXC_DEF_TX   (0xFU << 12)
+
+/*
+ ****************************************************************************
+ *	Memory Information Register - Bank 0 - OFfset 8
+ ****************************************************************************
+ */
+#define LAN91C96_MIR_SIZE        (0x18 << 0)    // 6144 bytes
+
+/*
+ ****************************************************************************
+ *	Memory Configuration Register - Bank 0 - Offset 10
+ ****************************************************************************
+ */
+#define LAN91C96_MCR_MEM_RES      (0xFFU << 0)
+#define LAN91C96_MCR_MEM_MULT     (0x3U << 9)
+#define LAN91C96_MCR_HIGH_ID      (0x3U << 12)
+
+#define LAN91C96_MCR_TRANSMIT_PAGES 0x6
+
+/*
+ ****************************************************************************
+ *	Bank 1 Register Map in I/O Space
+ ****************************************************************************
+ */
+#define LAN91C96_CONFIG       0        // Configuration Register
+#define LAN91C96_BASE         2        // Base Address Register
+#define LAN91C96_IA0          4        // Individual Address Register - 0
+#define LAN91C96_IA1          5        // Individual Address Register - 1
+#define LAN91C96_IA2          6        // Individual Address Register - 2
+#define LAN91C96_IA3          7        // Individual Address Register - 3
+#define LAN91C96_IA4          8        // Individual Address Register - 4
+#define LAN91C96_IA5          9        // Individual Address Register - 5
+#define LAN91C96_GEN_PURPOSE  10       // General Address Registers
+#define LAN91C96_CONTROL      12       // Control Register
+
+/*
+ ****************************************************************************
+ *	Configuration Register - Bank 1 - Offset 0
+ ****************************************************************************
+ */
+#define LAN91C96_CR_INT_SEL0      (0x1U << 1)
+#define LAN91C96_CR_INT_SEL1      (0x1U << 2)
+#define LAN91C96_CR_RES           (0x3U << 3)
+#define LAN91C96_CR_DIS_LINK      (0x1U << 6)
+#define LAN91C96_CR_16BIT         (0x1U << 7)
+#define LAN91C96_CR_AUI_SELECT    (0x1U << 8)
+#define LAN91C96_CR_SET_SQLCH     (0x1U << 9)
+#define LAN91C96_CR_FULL_STEP     (0x1U << 10)
+#define LAN91C96_CR_NO_WAIT       (0x1U << 12)
+
+/*
+ ****************************************************************************
+ *	Base Address Register - Bank 1 - Offset 2
+ ****************************************************************************
+ */
+#define LAN91C96_BAR_RA_BITS      (0x27U << 0)
+#define LAN91C96_BAR_ROM_SIZE     (0x1U << 6)
+#define LAN91C96_BAR_A_BITS       (0xFFU << 8)
+
+/*
+ ****************************************************************************
+ *	Control Register - Bank 1 - Offset 12
+ ****************************************************************************
+ */
+#define LAN91C96_CTR_STORE        (0x1U << 0)
+#define LAN91C96_CTR_RELOAD       (0x1U << 1)
+#define LAN91C96_CTR_EEPROM       (0x1U << 2)
+#define LAN91C96_CTR_TE_ENABLE    (0x1U << 5)
+#define LAN91C96_CTR_CR_ENABLE    (0x1U << 6)
+#define LAN91C96_CTR_LE_ENABLE    (0x1U << 7)
+#define LAN91C96_CTR_BIT_8        (0x1U << 8)
+#define LAN91C96_CTR_AUTO_RELEASE (0x1U << 11)
+#define LAN91C96_CTR_WAKEUP_EN    (0x1U << 12)
+#define LAN91C96_CTR_PWRDN        (0x1U << 13)
+#define LAN91C96_CTR_RCV_BAD      (0x1U << 14)
+
+/*
+ ****************************************************************************
+ *	Bank 2 Register Map in I/O Space
+ ****************************************************************************
+ */
+#define LAN91C96_MMU            0      // MMU Command Register
+#define LAN91C96_AUTO_TX_START  1      // Auto Tx Start Register
+#define LAN91C96_PNR            2      // Packet Number Register
+#define LAN91C96_ARR            3      // Allocation Result Register
+#define LAN91C96_FIFO           4      // FIFO Ports Register
+#define LAN91C96_POINTER        6      // Pointer Register
+#define LAN91C96_DATA_HIGH      8      // Data High Register
+#define LAN91C96_DATA_LOW       10     // Data Low Register
+#define LAN91C96_INT_STATS      12     // Interrupt Status Register - RO
+#define LAN91C96_INT_ACK        12     // Interrupt Acknowledge Register -WO
+#define LAN91C96_INT_MASK       13     // Interrupt Mask Register
+
+/*
+ ****************************************************************************
+ *	MMU Command Register - Bank 2 - Offset 0
+ ****************************************************************************
+ */
+#define LAN91C96_MMUCR_NO_BUSY    (0x1U << 0)
+#define LAN91C96_MMUCR_N1         (0x1U << 1)
+#define LAN91C96_MMUCR_N2         (0x1U << 2)
+#define LAN91C96_MMUCR_COMMAND    (0xFU << 4)
+#define LAN91C96_MMUCR_ALLOC_TX   (0x2U << 4)    // WXYZ = 0010
+#define LAN91C96_MMUCR_RESET_MMU  (0x4U << 4)    // WXYZ = 0100
+#define LAN91C96_MMUCR_REMOVE_RX  (0x6U << 4)    // WXYZ = 0110
+#define LAN91C96_MMUCR_REMOVE_TX  (0x7U << 4)    // WXYZ = 0111
+#define LAN91C96_MMUCR_RELEASE_RX (0x8U << 4)    // WXYZ = 1000
+#define LAN91C96_MMUCR_RELEASE_TX (0xAU << 4)    // WXYZ = 1010
+#define LAN91C96_MMUCR_ENQUEUE    (0xCU << 4)    // WXYZ = 1100
+#define LAN91C96_MMUCR_RESET_TX   (0xEU << 4)    // WXYZ = 1110
+
+/*
+ ****************************************************************************
+ *	Auto Tx Start Register - Bank 2 - Offset 1
+ ****************************************************************************
+ */
+#define LAN91C96_AUTOTX           (0xFFU << 0)
+
+/*
+ ****************************************************************************
+ *	Packet Number Register - Bank 2 - Offset 2
+ ****************************************************************************
+ */
+#define LAN91C96_PNR_TX           (0x1FU << 0)
+
+/*
+ ****************************************************************************
+ *	Allocation Result Register - Bank 2 - Offset 3
+ ****************************************************************************
+ */
+#define LAN91C96_ARR_ALLOC_PN     (0x7FU << 0)
+#define LAN91C96_ARR_FAILED       (0x1U << 7)
+
+/*
+ ****************************************************************************
+ *	FIFO Ports Register - Bank 2 - Offset 4
+ ****************************************************************************
+ */
+#define LAN91C96_FIFO_TX_DONE_PN  (0x1FU << 0)
+#define LAN91C96_FIFO_TEMPTY      (0x1U << 7)
+#define LAN91C96_FIFO_RX_DONE_PN  (0x1FU << 8)
+#define LAN91C96_FIFO_RXEMPTY     (0x1U << 15)
+
+/*
+ ****************************************************************************
+ *	Pointer Register - Bank 2 - Offset 6
+ ****************************************************************************
+ */
+#define LAN91C96_PTR_LOW          (0xFFU << 0)
+#define LAN91C96_PTR_HIGH         (0x7U << 8)
+#define LAN91C96_PTR_AUTO_TX      (0x1U << 11)
+#define LAN91C96_PTR_ETEN         (0x1U << 12)
+#define LAN91C96_PTR_READ         (0x1U << 13)
+#define LAN91C96_PTR_AUTO_INCR    (0x1U << 14)
+#define LAN91C96_PTR_RCV          (0x1U << 15)
+
+#define LAN91C96_PTR_RX_FRAME     (LAN91C96_PTR_RCV       |    \
+                                   LAN91C96_PTR_AUTO_INCR |    \
+                                   LAN91C96_PTR_READ)
+
+/*
+ ****************************************************************************
+ *	Data Register - Bank 2 - Offset 8
+ ****************************************************************************
+ */
+#define LAN91C96_CONTROL_CRC      (0x1U << 4)    // CRC bit
+#define LAN91C96_CONTROL_ODD      (0x1U << 5)    // ODD bit
+
+/*
+ ****************************************************************************
+ *	Interrupt Status Register - Bank 2 - Offset 12
+ ****************************************************************************
+ */
+#define LAN91C96_IST_RCV_INT      (0x1U << 0)
+#define LAN91C96_IST_TX_INT       (0x1U << 1)
+#define LAN91C96_IST_TX_EMPTY_INT (0x1U << 2)
+#define LAN91C96_IST_ALLOC_INT    (0x1U << 3)
+#define LAN91C96_IST_RX_OVRN_INT  (0x1U << 4)
+#define LAN91C96_IST_EPH_INT      (0x1U << 5)
+#define LAN91C96_IST_ERCV_INT     (0x1U << 6)
+#define LAN91C96_IST_RX_IDLE_INT  (0x1U << 7)
+
+/*
+ ****************************************************************************
+ *	Interrupt Acknowledge Register - Bank 2 - Offset 12
+ ****************************************************************************
+ */
+#define LAN91C96_ACK_TX_INT       (0x1U << 1)
+#define LAN91C96_ACK_TX_EMPTY_INT (0x1U << 2)
+#define LAN91C96_ACK_RX_OVRN_INT  (0x1U << 4)
+#define LAN91C96_ACK_ERCV_INT     (0x1U << 6)
+
+/*
+ ****************************************************************************
+ *	Interrupt Mask Register - Bank 2 - Offset 13
+ ****************************************************************************
+ */
+#define LAN91C96_MSK_RCV_INT      (0x1U << 0)
+#define LAN91C96_MSK_TX_INT       (0x1U << 1)
+#define LAN91C96_MSK_TX_EMPTY_INT (0x1U << 2)
+#define LAN91C96_MSK_ALLOC_INT    (0x1U << 3)
+#define LAN91C96_MSK_RX_OVRN_INT  (0x1U << 4)
+#define LAN91C96_MSK_EPH_INT      (0x1U << 5)
+#define LAN91C96_MSK_ERCV_INT     (0x1U << 6)
+#define LAN91C96_MSK_TX_IDLE_INT  (0x1U << 7)
+
+/*
+ ****************************************************************************
+ *	Bank 3 Register Map in I/O Space
+ **************************************************************************
+ */
+#define LAN91C96_MGMT_MDO         (0x1U << 0)
+#define LAN91C96_MGMT_MDI         (0x1U << 1)
+#define LAN91C96_MGMT_MCLK        (0x1U << 2)
+#define LAN91C96_MGMT_MDOE        (0x1U << 3)
+#define LAN91C96_MGMT_LOW_ID      (0x3U << 4)
+#define LAN91C96_MGMT_IOS0        (0x1U << 8)
+#define LAN91C96_MGMT_IOS1        (0x1U << 9)
+#define LAN91C96_MGMT_IOS2        (0x1U << 10)
+#define LAN91C96_MGMT_nXNDEC      (0x1U << 11)
+#define LAN91C96_MGMT_HIGH_ID     (0x3U << 12)
+
+/*
+ ****************************************************************************
+ *	Revision Register - Bank 3 - Offset 10
+ ****************************************************************************
+ */
+#define LAN91C96_REV_REVID        (0xFU << 0)
+#define LAN91C96_REV_CHIPID       (0xFU << 4)
+
+/*
+ ****************************************************************************
+ *	Early RCV Register - Bank 3 - Offset 12
+ ****************************************************************************
+ */
+#define LAN91C96_ERCV_THRESHOLD   (0x1FU << 0)
+#define LAN91C96_ERCV_RCV_DISCRD  (0x1U << 7)
+
+/*
+ ****************************************************************************
+ *	PCMCIA Configuration Registers
+ ****************************************************************************
+ */
+#define LAN91C96_ECOR    0x8000        // Ethernet Configuration Register
+#define LAN91C96_ECSR    0x8002        // Ethernet Configuration and Status
+
+/*
+ ****************************************************************************
+ *	PCMCIA Ethernet Configuration Option Register (ECOR)
+ ****************************************************************************
+ */
+#define LAN91C96_ECOR_ENABLE       (0x1U << 0)
+#define LAN91C96_ECOR_WR_ATTRIB    (0x1U << 2)
+#define LAN91C96_ECOR_LEVEL_REQ    (0x1U << 6)
+#define LAN91C96_ECOR_SRESET       (0x1U << 7)
+
+/*
+ ****************************************************************************
+ *	PCMCIA Ethernet Configuration and Status Register (ECSR)
+ ****************************************************************************
+ */
+#define LAN91C96_ECSR_INTR        (0x1U << 1)
+#define LAN91C96_ECSR_PWRDWN      (0x1U << 2)
+#define LAN91C96_ECSR_IOIS8       (0x1U << 5)
+
+/*
+ ****************************************************************************
+ *	Receive Frame Status Word - See page 38 of the LAN91C96 specification.
+ ****************************************************************************
+ */
+#define LAN91C96_TOO_SHORT        (0x1U << 10)
+#define LAN91C96_TOO_LONG         (0x1U << 11)
+#define LAN91C96_ODD_FRM          (0x1U << 12)
+#define LAN91C96_BAD_CRC          (0x1U << 13)
+#define LAN91C96_BROD_CAST        (0x1U << 14)
+#define LAN91C96_ALGN_ERR         (0x1U << 15)
+
+#define FRAME_FILTER              (LAN91C96_TOO_SHORT | LAN91C96_TOO_LONG  | LAN91C96_BAD_CRC   | LAN91C96_ALGN_ERR)
+
+/*
+ ****************************************************************************
+ *	Default MAC Address
+ ****************************************************************************
+ */
+#define MAC_DEF_HI  0x0800
+#define MAC_DEF_MED 0x3333
+#define MAC_DEF_LO  0x0100
+
+/*
+ ****************************************************************************
+ *	Default I/O Signature - 0x33
+ ****************************************************************************
+ */
+#define LAN91C96_LOW_SIGNATURE        (0x33U << 0)
+#define LAN91C96_HIGH_SIGNATURE       (0x33U << 8)
+#define LAN91C96_SIGNATURE (LAN91C96_HIGH_SIGNATURE | LAN91C96_LOW_SIGNATURE)
+
+#define LAN91C96_MAX_PAGES     6        // Maximum number of 256 pages.
+#define ETHERNET_MAX_LENGTH 1514
+
+
+
+/*-------------------------------------------------------------------------
+ *  I define some macros to make it easier to do somewhat common
+ * or slightly complicated, repeated tasks.
+ *-------------------------------------------------------------------------
+ */
+
+/* select a register bank, 0 to 3  */
+
+#define SMC_SELECT_BANK(x)  { SMC_outw( x, LAN91C96_BANK_SELECT ); }
+
+/* this enables an interrupt in the interrupt mask register */
+#define SMC_ENABLE_INT(x) {\
+		unsigned char mask;\
+		SMC_SELECT_BANK(2);\
+		mask = SMC_inb( LAN91C96_INT_MASK );\
+		mask |= (x);\
+		SMC_outb( mask, LAN91C96_INT_MASK ); \
+}
+
+/* this disables an interrupt from the interrupt mask register */
+
+#define SMC_DISABLE_INT(x) {\
+		unsigned char mask;\
+		SMC_SELECT_BANK(2);\
+		mask = SMC_inb( LAN91C96_INT_MASK );\
+		mask &= ~(x);\
+		SMC_outb( mask, LAN91C96_INT_MASK ); \
+}
+
+/*----------------------------------------------------------------------
+ * Define the interrupts that I want to receive from the card
+ *
+ * I want:
+ *  LAN91C96_IST_EPH_INT, for nasty errors
+ *  LAN91C96_IST_RCV_INT, for happy received packets
+ *  LAN91C96_IST_RX_OVRN_INT, because I have to kick the receiver
+ *-------------------------------------------------------------------------
+ */
+#define SMC_INTERRUPT_MASK   (LAN91C96_IST_EPH_INT | LAN91C96_IST_RX_OVRN_INT | LAN91C96_IST_RCV_INT)
+
+#endif  /* _LAN91C96_H_ */

drivers/pci_indirect.c

@@ -21,7 +21,7 @@
 #define cfg_read(val, addr, type, op)	*val = op((type)(addr))
 #define cfg_write(val, addr, type, op)	op((type *)(addr), (val))
 
-#ifdef CONFIG_PM826
+#if defined(CONFIG_PM826) || defined(CONFIG_ATC)
 #define INDIRECT_PCI_OP(rw, size, type, op, mask)			 \
 static int								 \
 indirect_##rw##_config_##size(struct pci_controller *hose, 		 \

include/asm-ppc/cpm_8260.h

@@ -170,7 +170,7 @@ typedef struct cpm_buf_desc {
  */
 #define PROFF_SMC1	(0)
 #define PROFF_SMC2	(64)
-
+#define PROFF_SPI	((16*1024) - 128)
 
 /* Define enough so I can at least use the serial port as a UART.
  */
@@ -737,6 +737,17 @@ typedef struct spi {
 #define SPMODE_LEN(x)	((((x)-1)&0xF)<<4)
 #define SPMODE_PM(x)	((x) &0xF)
 
+/* SPI Event/Mask register.
+*/
+#define SPI_EMASK		0x37	/* Event Mask				*/
+#define SPI_MME			0x20	/* Multi-Master Error			*/
+#define SPI_TXE			0x10	/* Transmit Error			*/
+#define SPI_BSY			0x04	/* Busy					*/
+#define SPI_TXB			0x02	/* Tx Buffer Empty			*/
+#define SPI_RXB			0x01	/* RX Buffer full/closed		*/
+
+#define SPI_STR			0x80	/* SPCOM: Start transmit		*/
+
 #define SPI_EB		((u_char)0x10)		/* big endian byte order */
 
 #define BD_IIC_START		((ushort)0x0400)

include/asm-ppc/global_data.h

@@ -70,10 +70,18 @@ typedef	struct	global_data {
 #endif
 #ifdef CONFIG_POST
 	unsigned long	post_log_word;  /* Record POST activities */
+	unsigned long	post_init_f_time;  /* When post_init_f started */
 #endif
 #ifdef CONFIG_BOARD_TYPES
 	unsigned long	board_type;
 #endif
+#ifdef CONFIG_MODEM_SUPPORT
+	unsigned long do_mdm_init;
+	unsigned long be_quiet;
+#endif
+#ifdef CONFIG_LWMON
+	unsigned long kbd_status;
+#endif	
 } gd_t;
 
 /*

include/bmp_layout.h

@@ -0,0 +1,77 @@
+/* (C) Copyright 2002
+ * Detlev Zundel, DENX Software Engineering, dzu@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************/
+/* ** Layout of a bmp file						*/
+/************************************************************************/
+
+#ifndef _BMP_H_
+#define _BMP_H_
+
+typedef struct bmp_color_table_entry {
+  __u8 blue;
+  __u8 green;
+  __u8 red;
+  __u8 reserved;
+} __attribute__((packed)) bmp_color_table_entry_t;
+
+/* When accessing these fields, remember that they are stored in little
+   endian format, so use linux macros, e.g. le32_to_cpu(width)          */
+
+typedef	struct bmp_header {
+  /* Header */
+  char signature[2];
+  __u32 file_size;
+  __u32 reserved;
+  __u32 data_offset;
+  /* InfoHeader */
+  __u32 size;
+  __u32 width;
+  __u32 height;
+  __u16 planes;
+  __u16 bit_count;
+  __u32 compression;
+  __u32 image_size;
+  __u32 x_pixels_per_m;
+  __u32 y_pixels_per_m;
+  __u32 colors_used;
+  __u32 colors_important;
+  /* ColorTable */
+  
+}  __attribute__((packed)) bmp_header_t;
+
+typedef struct bmp_image {
+  bmp_header_t header;
+  /* We use a zero sized array just as a placeholder for variable
+     sized array */
+  bmp_color_table_entry_t color_table[0];
+} bmp_image_t;
+
+/* Data in the bmp_image is aligned to this length */
+#define BMP_DATA_ALIGN 4
+
+/* Constants for the compression field */
+#define BMP_BI_RGB  0
+#define BMP_BI_RLE8 1
+#define BMP_BI_RLE4 2
+
+#endif /* _BMP_H_ */

include/cmd_bmp.h

@@ -0,0 +1,44 @@
+/* (C) Copyright 2002
+ * Detlev Zundel, DENX Software Engineering, dzu@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Bitmap display support
+ */
+#ifndef	_CMD_BMP_H
+#define	_CMD_BMP_H
+
+#include <common.h>
+#include <command.h>
+
+
+#if (CONFIG_COMMANDS & CFG_CMD_BMP)
+
+#define CMD_TBL_BMP	MK_CMD_TBL_ENTRY(				\
+	"bmp", 3,	3,	1,	do_bmp,				\
+	"bmp     - manipulate BMP image data\n",			\
+	"info <imageAddr>    - display image info\n"			\
+	"bmp display <imageAddr> - display image\n"			\
+),
+int do_bmp (cmd_tbl_t *cmdtp,  int flag, int argc, char *argv[]);
+
+#else
+#define CMD_TBL_BMP
+#endif
+
+#endif	/* _CMD_BMP_H */

include/cmd_confdefs.h

@@ -79,6 +79,7 @@
 #define CFG_CMD_FDOS	0x0000200000000000	/* Floppy DOS support		*/
 #define CFG_CMD_VFD	0x0000400000000000	/* VFD support (TRAB)		*/
 #define CFG_CMD_NAND	0x0000800000000000	/* NAND support        		*/
+#define CFG_CMD_BMP	0x0001000000000000	/* BMP support			*/
 
 #define CFG_CMD_ALL	0xFFFFFFFFFFFFFFFF	/* ALL commands			*/
 
@@ -87,6 +88,7 @@
  */
 #define CFG_CMD_NONSTD (CFG_CMD_ASKENV	| \
 			CFG_CMD_BEDBUG	| \
+			CFG_CMD_BMP	| \
 			CFG_CMD_BSP	| \
 			CFG_CMD_CACHE	| \
 			CFG_CMD_DATE	| \

include/cmd_disk.h

@@ -31,9 +31,10 @@
 #include <command.h>
 
 /*
- * Type string for PPC bootable partitions
+ * Type string for U-Boot bootable partitions
  */
-#define BOOT_PART_TYPE	"U-Boot"
+#define BOOT_PART_TYPE	"U-Boot"	/* primary boot partition type	*/
+#define BOOT_PART_COMP	"PPCBoot"	/* PPCBoot compatibility type	*/
 
 #if 0
 

include/common.h

@@ -198,7 +198,7 @@ extern void  pic_write (uchar reg, uchar val);
 # define CFG_DEF_EEPROM_ADDR CFG_I2C_EEPROM_ADDR
 #endif /* CONFIG_SPI || !defined(CFG_I2C_EEPROM_ADDR) */
 
-#if defined(CONFIG_PCU_E) || defined(CONFIG_CCM)
+#if defined(CONFIG_PCU_E) || defined(CONFIG_CCM) || defined(CONFIG_ATC)
 extern void spi_init_f (void);
 extern void spi_init_r (void);
 extern ssize_t spi_read  (uchar *, int, uchar *, int);

include/commproc.h

@@ -1365,7 +1365,7 @@ typedef struct scc_enet {
 /***  TQM855L, TQM860L, TQM862L  **************************************/
 
 #if defined(CONFIG_TQM855L) || \
-    defined(CONFIG_TQM860L)
+    defined(CONFIG_TQM860L) || \
     defined(CONFIG_TQM862L)
 
 # ifdef CONFIG_SCC1_ENET	/* use SCC for 10Mbps Ethernet	*/

include/configs/CRAYL1.h

@@ -41,43 +41,28 @@
 #define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
 #define CONFIG_MII		    1	/* MII PHY management */
 #define	CONFIG_PHY_ADDR		1	/* PHY address; handling of ENET */
-#define CONFIG_BOARD_PRE_INIT 1 /* setup for 405gp */
+#define CONFIG_BOARD_PRE_INIT 1 /* early setup for 405gp */
 #define CONFIG_MISC_INIT_R	1	/* so that a misc_init_r() is called */
 
 /* set PRAM to keep U-Boot out, mem= to keep linux out, and initrd_hi to
  * keep possible initrd ramdisk decompression out.  This is in k (1024 bytes)
- #define CONFIG_PRAM			16
+ #define CONFIG_PRAM			16 
  */
-#define	CONFIG_LOADADDR		0x100000
+#define	CONFIG_LOADADDR		0x100000	/* where TFTP images go */
 #undef CONFIG_BOOTARGS
 
-/* the logic is that booting is driven by what env vars get set from DHCP.
- * Normal DHCP sets things like serverip, rootpath, etc.
- * if printenv
+/* Bootcmd is overridden by the bootscript in board/cray/L1
  */
-#define	CFG_AUTOLOAD		"yes"
-#define CONFIG_BOOTCOMMAND	"dhcp;"\
-	"setenv bootargs devfs=mount;"\
-	"setenv bootargs ip=$ipaddr:$serverip:$gatewayip:$netmask:::off $bootargs;"\
-	"if printenv initrd;"\
-	"then;" \
-	 "setenv initrd_hi $mem;"\
-	 "tftp 1000000 $initrd;"\
-	 "setenv bootargs root=/dev/ram0 rw cwsroot=$serverip:$rootpath $bootargs;"\
-	 "bootm 100000 1000000;"\
-	"else;"\
-	 "setenv bootargs root=/dev/nfs ro nfsroot=$serverip:$rootpath $bootargs;"\
-	 "bootm 100000;"\
-	"fi;"
+#define	CFG_AUTOLOAD		"no"
+#define CONFIG_BOOTCOMMAND	"dhcp"
 
-#define CONFIG_EXTRA_ENV_SETTINGS ""
-
-/*
+/* 
  * ..during experiments..
  #define CONFIG_SERVERIP         10.0.0.1
- #define CONFIG_ETHADDR          00:40:a6:80:14:5
+ #define CONFIG_ETHADDR          00:40:a6:80:14:5 
  */
 #define CONFIG_HARD_I2C         1		/* hardware support for i2c */
+#define CONFIG_SDRAM_BANK0		1
 #define CFG_I2C_SPEED		    400000	/* I2C speed and slave address	*/
 #define CFG_I2C_SLAVE		    0x7F
 #define CFG_I2C_EEPROM_ADDR     0x57
@@ -87,6 +72,7 @@
 #define	CFG_HZ		             1000	/* decrementer freq: 1 ms ticks	*/
 #define CFG_HUSH_PARSER			1
 #define CFG_PROMPT_HUSH_PS2		"> "
+#define CONFIG_AUTOSCRIPT		1
 
 
 #define CONFIG_COMMANDS	 (\
@@ -106,6 +92,8 @@
 	CFG_CMD_RUN|\
 	CFG_CMD_I2C|\
 	CFG_CMD_EEPROM|\
+	CFG_CMD_DIAG|\
+	CFG_CMD_AUTOSCRIPT|\
 	CFG_CMD_SETGETDCR)
 
 /*
@@ -120,7 +108,13 @@
 	CONFIG_BOOTP_BOOTFILESIZE|\
 	CONFIG_BOOTP_BOOTPATH)
 
-/*
+/* 
+ * how many time to fail & restart a net-TFTP before giving up & resetting
+ * the board hoping that a reset of net interface might help..
+ */
+#define CONFIG_NET_RESET 5
+
+/* 
  * bauds.  Just to make it compile; in our case, I read the base_baud
  * from the DCR anyway, so its kinda-tied to the above ref. clock which in turn
  * drives the system clock.
@@ -145,6 +139,7 @@
 #define CFG_LOAD_ADDR   	0x100000/* where to load what we get from TFTP */
 #define CFG_TFTP_LOADADDR	CFG_LOAD_ADDR
 #define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
+#define CFG_DRAM_TEST		1
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
@@ -155,15 +150,8 @@
 #define CFG_FLASH_BASE		0xFFC00000
 #define CFG_MONITOR_BASE	TEXT_BASE
 
-#ifndef  CFG_HUSH_PARSER
-#define CFG_MONITOR_LEN		(128 * 1024)	/* Reserve 128 kB for Monitor	*/
-#define CFG_ENV_OFFSET		0x3D0000
-#else
-#define CFG_MONITOR_LEN		(192 * 1024)	/* Reserve 192 kB for Monitor	*/
-#define CFG_ENV_OFFSET		0x3FE000
-#endif
 
-#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
+#define CFG_MONITOR_LEN		(192 * 1024)	/* Reserve 192 kB for Monitor	*/
 
 /*
  * For booting Linux, the board info and command line data
@@ -180,11 +168,12 @@
 #define CFG_FLASH_WRITE_TOUT 500	/* Timeout for Flash Write (in ms)	*/
 
 /* BEG ENVIRONNEMENT FLASH: needs to be a whole FlashSector  */
+#define CFG_ENV_OFFSET		0x3c8000 
 #define CFG_ENV_IS_IN_FLASH	1	/* use FLASH for environment vars */
-#define	CFG_ENV_SIZE		0x1000	 /* Total Size of Environment Sector	*/
+#define	CFG_ENV_SIZE		0x1000	 /* Total Size of Environment area	*/
 #define CFG_ENV_SECT_SIZE	0x10000	 /* see README - env sector total size	*/
 
-/* Memory tests: U-Boot relocates itself to the top of Ram, so its at
+/* Memory tests: U-BOOT relocates itself to the top of Ram, so its at
  * 32meg-(128k+some_malloc_space+copy-of-ENV sector)..
  */
 #define CFG_SDRAM_SIZE		32		/* megs of ram */
@@ -193,6 +182,7 @@
 									/* to the end of the DRAM  */
 									/* less monitor and malloc area */
 #define CFG_STACK_USAGE		0x10000 /* Reserve 64k for the stack usage */
+#define CFG_MALLOC_LEN		(128 << 10)	/* 128k for malloc space */
 #define CFG_MEM_END_USAGE	( CFG_MONITOR_LEN \
                                 + CFG_MALLOC_LEN \
                                 + CFG_ENV_SECT_SIZE \
@@ -202,7 +192,7 @@
 /* END ENVIRONNEMENT FLASH */
 
 /*-----------------------------------------------------------------------
- * Cache Configuration.  Only used to ..?? clear it, I guess..
+ * Cache Configuration.  Only used to ..?? clear it, I guess.. 
  */
 #define CFG_DCACHE_SIZE		16384
 #define CFG_CACHELINE_SIZE	32
@@ -219,20 +209,26 @@
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in OnChipMem )
  */
-#if 0
-#define CFG_INIT_RAM_ADDR       0x40000000  /* use data cache               */
-#define CFG_INIT_RAM_END        0x2000  /* End of used area in RAM             */
-#else
+#if 1
+/* On Chip Memory location */
 #define CFG_TEMP_STACK_OCM	1
 #define CFG_OCM_DATA_ADDR	0xF0000000
 #define CFG_OCM_DATA_SIZE	0x1000
+
+#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
+#define CFG_GBL_DATA_SIZE      256  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
+#else
+#define CFG_OCM_DATA_ADDR	0xF0000000
+#define CFG_OCM_DATA_SIZE	0x1000
 #define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR 	/* inside of On Chip SRAM    */
 #define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE	/* End of On Chip SRAM	     */
-#endif
-
 #define CFG_GBL_DATA_SIZE	64	/* size in bytes reserved for initial data */
 #define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 #define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#endif
 
 /*-----------------------------------------------------------------------
  * Definitions for Serial Presence Detect EEPROM address

include/configs/GEN860T.h

@@ -38,14 +38,22 @@
 /*
  * Identify the board
  */
-#define CONFIG_IDENT_STRING				" GEN860T"
+#if !defined(CONFIG_SC)
+#define CONFIG_IDENT_STRING				" B2"
+#else
+#define CONFIG_IDENT_STRING				" SC"
+#endif
 
 /*
  * Don't depend on the RTC clock to determine clock frequency -
  * the 860's internal rtc uses a 32.768 KHz clock which is
  * generated by the DS1337 - and the DS1337 clock can be turned off.
  */
-#define	CONFIG_8xx_GCLK_FREQ			66600000
+#if !defined(CONFIG_SC)
+#define	CONFIG_8xx_GCLK_FREQ			66600000 
+#else
+#define	CONFIG_8xx_GCLK_FREQ			48000000
+#endif
 
 /*
  * The RS-232 console port is on SMC1
@@ -143,7 +151,7 @@
  * environment so that we can autoscript the full default environment.
  */
 #define CONFIG_ETHADDR					9a:52:63:15:85:25
-#define CONFIG_SERVERIP					10.0.4.200
+#define CONFIG_SERVERIP					10.0.4.201
 #define CONFIG_IPADDR					10.0.4.111
 
 /*
@@ -156,17 +164,20 @@
 #define	CFG_I2C_EEPROM_ADDR_LEN			2		/* need 16 bit address	*/
 #define CFG_ENV_EEPROM_SIZE				(32 * 1024)
 
-#undef	CONFIG_HARD_I2C
-#define CONFIG_SOFT_I2C
-
 /*
- * Configure software I2C support (taken from IP860 BSP).
- * The I2C bus is connected to the GEN860T's 'dedicated' I2C
- * pins, i.e. PB26 and PB27
+ * Enable I2C and select the hardware/software driver
  */
+#define CONFIG_HARD_I2C		1				/* CPM based I2C			*/
+#undef	CONFIG_SOFT_I2C        				/* Bit-banged I2C			*/
+
+#ifdef CONFIG_HARD_I2C
+#define	CFG_I2C_SPEED		100000			/* clock speed in Hz		*/
+#define CFG_I2C_SLAVE		0xFE			/* I2C slave address		*/
+#endif
+
+#ifdef CONFIG_SOFT_I2C
 #define PB_SCL				0x00000020		/* PB 26					*/
 #define PB_SDA				0x00000010		/* PB 27 					*/
-
 #define I2C_INIT			(immr->im_cpm.cp_pbdir |=  PB_SCL)
 #define I2C_ACTIVE			(immr->im_cpm.cp_pbdir |=  PB_SDA)
 #define I2C_TRISTATE		(immr->im_cpm.cp_pbdir &= ~PB_SDA)
@@ -176,15 +187,14 @@
 #define I2C_SCL(bit)		if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
 								else    immr->im_cpm.cp_pbdat &= ~PB_SCL
 #define I2C_DELAY			udelay(5)		/* 1/4 I2C clock duration	*/
-
-#define	CFG_I2C_SPEED		100000			/* clock speed in Hz		*/
-#define CFG_I2C_SLAVE		0xFE			/* I2C slave address		*/
+#endif
 
 /*
  * Allow environment overwrites by anyone
  */
 #define CONFIG_ENV_OVERWRITE
 
+#if !defined(CONFIG_SC)
 /*
  * The MPC860's internal RTC is horribly broken in rev D masks. Three
  * internal MPC860T circuit nodes were inadvertently left floating; this
@@ -193,35 +203,55 @@
  * reasonable battery can keep that kind RTC running during powerdown for any
  * length of time, so we use an external RTC on the I2C bus instead.
  */
-#undef	CONFIG_RTC_MPC8xx
 #define CONFIG_RTC_DS1337
-#define CFG_I2C_RTC_ADDR				0x68
+#define CFG_I2C_RTC_ADDR				0x68 
+
+#else
+/*
+ * No external RTC on SC variant, so we're stuck with the internal one.
+ */
+#define	CONFIG_RTC_MPC8xx
+#endif
 
 /*
- * Allow partial commands to be matched to uniqueness.
+ * Power On Self Test support
  */
-#define CFG_MATCH_PARTIAL_CMD
+#define CONFIG_POST			  ( CFG_POST_CACHE		| \
+								CFG_POST_MEMORY		| \
+								CFG_POST_CPU		| \
+								CFG_POST_UART		| \
+								CFG_POST_SPR )
+
+#ifdef CONFIG_POST
+#define CFG_CMD_POST_DIAG CFG_CMD_DIAG
+#else
+#define CFG_CMD_POST_DIAG		0
+#endif
 
 /*
  * List of available monitor commands.  Use the system default list
  * plus add some of the "non-standard" commands back in.
  * See ./cmd_confdefs.h
  */
-#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+#define BASE_CONFIG_COMMANDS	( CONFIG_CMD_DFL	| \
 								CFG_CMD_ASKENV	| \
 								CFG_CMD_DHCP	| \
 								CFG_CMD_I2C		| \
-								CFG_CMD_DOC		| \
 								CFG_CMD_EEPROM	| \
 								CFG_CMD_REGINFO	| \
 								CFG_CMD_IMMAP	| \
 								CFG_CMD_ELF		| \
 								CFG_CMD_DATE	| \
-								CFG_CMD_DATE	| \
 								CFG_CMD_FPGA	| \
 								CFG_CMD_MII 	| \
-								CFG_CMD_BEDBUG	\
-						      )
+								CFG_CMD_BEDBUG	| \
+								CFG_CMD_POST_DIAG )
+
+#if !defined(CONFIG_SC)
+#define	CONFIG_COMMANDS ( BASE_CONFIG_COMMANDS | CFG_CMD_DOC ) 
+#else
+#define CONFIG_COMMANDS	BASE_CONFIG_COMMANDS
+#endif
 
 /*
  * There is no IDE/PCMCIA hardware support on the board.
@@ -258,7 +288,12 @@
  * Verbose help from command monitor.
  */
 #define	CFG_LONGHELP
-#define	CFG_PROMPT			"gen860t> "
+#if !defined(CONFIG_SC)
+#define	CFG_PROMPT			"B2> "
+#else
+#define	CFG_PROMPT			"SC> "
+#endif
+
 
 /*
  * Use the "hush" command parser
@@ -393,15 +428,9 @@
 /*
  * Reserve memory for U-Boot.
  */
-#define CFG_MAX_U_BOOT_SECT	3
-
-#if defined(DEBUG)
-#define	CFG_MONITOR_LEN		(512 * 1024)
-#else
-#define	CFG_MONITOR_LEN		(256 * 1024)
-#endif
-
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define CFG_MAX_UBOOT_SECTS		4
+#define	CFG_MONITOR_LEN			(CFG_MAX_UBOOT_SECTS * CFG_FLASH_SECT_SIZE)
+#define CFG_MONITOR_BASE		CFG_FLASH_BASE
 
 /*
  * Select environment placement.  NOTE that u-boot.lds must
@@ -414,8 +443,14 @@
 #define CFG_ENV_SIZE			(2 * 1024)
 #define CFG_ENV_OFFSET			(CFG_ENV_EEPROM_SIZE - (8 * 1024))
 #else
-#define CFG_ENV_SIZE			(4 * 1024)
-#define CFG_ENV_OFFSET			(CFG_MAX_U_BOOT_SECT * CFG_FLASH_SECT_SIZE)
+#define CFG_ENV_SIZE			0x1000
+#define CFG_ENV_SECT_SIZE		CFG_FLASH_SECT_SIZE
+
+/*
+ * This ultimately gets passed right into the linker script, so we have to
+ * use a number :(
+ */
+#define CFG_ENV_OFFSET			0x060000
 #endif
 
 /*
@@ -439,7 +474,7 @@
 #endif
 
 /*------------------------------------------------------------------------
- * SYPCR - System Protection Control				UM 11-9
+ * SYPCR - System Protection Control							UM 11-9
  * -----------------------------------------------------------------------
  * SYPCR can only be written once after reset!
  *
@@ -523,6 +558,7 @@
  */
 #define SCCR_MASK   SCCR_EBDF11
 
+#if !defined(CONFIG_SC)
 #define CFG_SCCR	( SCCR_TBS			| 	/* timebase = GCLK/2	*/ \
 					  SCCR_COM00   		| 	/* full strength CLKOUT	*/ \
 					  SCCR_DFSYNC00 	| 	/* SYNCLK / 1 (normal)	*/ \
@@ -530,6 +566,17 @@
 					  SCCR_DFNL000		| \
 					  SCCR_DFNH000		  \
 					)
+#else
+#define CFG_SCCR	( SCCR_TBS			| 	/* timebase = GCLK/2	*/ \
+					  SCCR_COM00   		| 	/* full strength CLKOUT	*/ \
+					  SCCR_DFSYNC00 	| 	/* SYNCLK / 1 (normal)	*/ \
+					  SCCR_DFBRG00		| 	/* BRGCLK / 1 (normal)	*/ \
+					  SCCR_DFNL000		| \
+					  SCCR_DFNH000		| \
+					  SCCR_RTDIV		| \
+					  SCCR_RTSEL		  \
+					)
+#endif
 
 /*-----------------------------------------------------------------------
  * DER - Debug Enable Register									UM 37-46
@@ -695,10 +742,12 @@
 /*
  * Disk On Chip (millenium) configuration
  */
+#if !defined(CONFIG_SC)
 #define CFG_MAX_DOC_DEVICE	1
 #undef	CFG_DOC_SUPPORT_2000
 #define CFG_DOC_SUPPORT_MILLENNIUM
 #undef	CFG_DOC_PASSIVE_PROBE
+#endif
 
 /*
  * FEC interrupt assignment

include/configs/LANTEC.h

@@ -84,6 +84,7 @@
 #define CONFIG_CMD_NORMAL	(CONFIG_CMD_DFL & ~CFG_CMD_BOOTD)
 #define CONFIG_CMD_GDB		(CONFIG_CMD_NORMAL | CFG_CMD_KGDB)
 #define CONFIG_CMD_FULL		(CFG_CMD_ALL & ~CFG_CMD_BEDBUG	\
+					     & ~CFG_CMD_BMP	\
 					     & ~CFG_CMD_BSP	\
 					     & ~CFG_CMD_DOC	\
 					     & ~CFG_CMD_DTT	\

include/configs/MPC8260ADS.h

@@ -114,6 +114,7 @@
 
 #define CONFIG_COMMANDS		(CFG_CMD_ALL & ~( \
 				 CFG_CMD_BEDBUG | \
+				 CFG_CMD_BMP	| \
 				 CFG_CMD_BSP	| \
 				 CFG_CMD_DATE	| \
 				 CFG_CMD_DOC	| \

include/configs/MPC8266ADS.h

@@ -113,6 +113,7 @@
 
 #define CONFIG_COMMANDS		(CFG_CMD_ALL & ~( \
 				 CFG_CMD_BEDBUG | \
+				 CFG_CMD_BMP	| \
 				 CFG_CMD_BSP	| \
 				 CFG_CMD_DATE	| \
 				 CFG_CMD_DOC	| \

include/configs/NETVIA.h

@@ -345,4 +345,6 @@
 /* Ethernet at SCC2 */
 #define CONFIG_SCC2_ENET
 
+#define CONFIG_ARTOS			/* include ARTOS support */
+
 #endif	/* __CONFIG_H */

include/configs/R360MPI.h

@@ -40,6 +40,8 @@
 #undef  CONFIG_EDT32F10
 #define CONFIG_SHARP_LQ057Q3DC02
 
+#define	CONFIG_SPLASH_SCREEN
+
 #define MPC8XX_FACT             1		/* Multiply by 1	*/
 #define MPC8XX_XIN              50000000	/* 50 MHz in		*/
 #define CONFIG_8xx_GCLK_FREQ    50000000 /* define if can't use get_gclk_freq */
@@ -118,6 +120,7 @@
 #define CFG_I2C_TEM_ADDR	0x49	/* Temperature Sensors */
 
 #define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_BMP	| \
 				CFG_CMD_DHCP	| \
 				CFG_CMD_DATE	| \
 				CFG_CMD_I2C	| \

include/configs/TQM8260.h

@@ -33,6 +33,7 @@
  *	CONFIG_L2_CACHE
  *	CONFIG_266MHz
  *	CONFIG_300MHz
+ *	CONFIG_MPC8255
  */
 
 /*
@@ -202,11 +203,15 @@
 
 
 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
-#ifndef CONFIG_300MHz
-#define CONFIG_8260_CLKIN	66666666	/* in Hz */
-#else
-#define CONFIG_8260_CLKIN	83333000	/* in Hz */
-#endif
+#ifdef CONFIG_MPC8255
+#  define CONFIG_8260_CLKIN	66666666	/* in Hz */
+#else	/* !CONFIG_MPC8255 */
+# ifndef CONFIG_300MHz
+#  define CONFIG_8260_CLKIN	66666666	/* in Hz */
+# else
+#  define CONFIG_8260_CLKIN	83333000	/* in Hz */
+# endif
+#endif	/* CONFIG_MPC8255 */
 
 #if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
 #define CONFIG_BAUDRATE		230400
@@ -310,15 +315,19 @@
  * defines for the various registers affected by the HRCW e.g. changing
  * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
  */
-#if defined(CONFIG_266MHz)
-#define CFG_HRCW_MASTER		(HRCW_CIP | HRCW_ISB111 | HRCW_BMS | \
-				                              HRCW_MODCK_H0111)
-#elif defined(CONFIG_300MHz)
-#define CFG_HRCW_MASTER		(HRCW_CIP | HRCW_ISB111 | HRCW_BMS | \
-				                              HRCW_MODCK_H0110)
-#else
-#define CFG_HRCW_MASTER		(HRCW_CIP | HRCW_ISB111 | HRCW_BMS)
-#endif
+#define	__HRCW__ALL__		(HRCW_CIP | HRCW_ISB111 | HRCW_BMS)
+
+#ifdef	CONFIG_MPC8255
+#  define CFG_HRCW_MASTER	(__HRCW__ALL__ | HRCW_MODCK_H0111)
+#else	/* ! MPC8255 */
+# if defined(CONFIG_266MHz)
+#  define CFG_HRCW_MASTER	(__HRCW__ALL__ | HRCW_MODCK_H0111)
+# elif defined(CONFIG_300MHz)
+#  define CFG_HRCW_MASTER	(__HRCW__ALL__ | HRCW_MODCK_H0110)
+# else
+#  define CFG_HRCW_MASTER	(__HRCW__ALL__)
+# endif
+#endif	/* CONFIG_MPC8255 */
 
 /* no slaves so just fill with zeros */
 #define CFG_HRCW_SLAVE1		0

include/configs/TQM860L.h

@@ -92,6 +92,7 @@
 #define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
 				CFG_CMD_ASKENV	| \
 				CFG_CMD_DHCP	| \
+				CFG_CMD_ELF	| \
 				CFG_CMD_IDE	| \
 				CFG_CMD_DATE	)
 

include/configs/atc.h

@@ -0,0 +1,491 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC8260		1	/* This is an MPC8260 CPU		*/
+#define CONFIG_ATC		1	/* ...on a ATC board	*/
+
+/*
+ * select serial console configuration
+ *
+ * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
+ * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
+ * for SCC).
+ *
+ * if CONFIG_CONS_NONE is defined, then the serial console routines must
+ * defined elsewhere (for example, on the cogent platform, there are serial
+ * ports on the motherboard which are used for the serial console - see
+ * cogent/cma101/serial.[ch]).
+ */
+#define  CONFIG_CONS_ON_SMC		/* define if console on SMC */
+#undef CONFIG_CONS_ON_SCC		/* define if console on SCC */
+#undef  CONFIG_CONS_NONE		/* define if console on something else*/
+#define CONFIG_CONS_INDEX	2	/* which serial channel for console */
+
+#define CONFIG_BAUDRATE		115200
+
+/*
+ * select ethernet configuration
+ *
+ * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
+ * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
+ * for FCC)
+ *
+ * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
+ * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
+ * from CONFIG_COMMANDS to remove support for networking.
+ *
+ */
+#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC       */
+#undef	CONFIG_ETHER_NONE		/* define if ether on something else */
+#define CONFIG_ETHER_ON_FCC
+
+#define	CONFIG_NET_MULTI
+#define CONFIG_ETHER_ON_FCC2
+
+/*
+ * - Rx-CLK is CLK13
+ * - Tx-CLK is CLK14
+ * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
+ * - Enable Full Duplex in FSMR
+ */
+# define CFG_CMXFCR_MASK2	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
+# define CFG_CMXFCR_VALUE2	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
+# define CFG_CPMFCR_RAMTYPE	0
+# define CFG_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
+
+#define CONFIG_ETHER_ON_FCC3
+
+/*
+ * - Rx-CLK is CLK15
+ * - Tx-CLK is CLK16
+ * - RAM for BD/Buffers is on the local Bus (see 28-13)
+ * - Enable Half Duplex in FSMR
+ */
+# define CFG_CMXFCR_MASK3	(CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
+# define CFG_CMXFCR_VALUE3	(CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
+
+/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
+#define CONFIG_8260_CLKIN	64000000	/* in Hz */
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#undef	CONFIG_CLOCKS_IN_MHZ		/* clocks passsed to Linux in Hz */
+
+#define CONFIG_PREBOOT							\
+	"echo;"								\
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;"\
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND						\
+	"bootp;"							\
+	"setenv bootargs root=/dev/nfs rw "				\
+	"nfsroot=$(serverip):$(rootpath) " 				\
+	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;"\
+	"bootm"
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configuration options
+ */
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_COMMANDS		(CONFIG_CMD_DFL | \
+				 CFG_CMD_EEPROM | \
+				 CFG_CMD_PCI | \
+				 CFG_CMD_PCMCIA | \
+				 CFG_CMD_IDE)
+#define CONFIG_DOS_PARTITION
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END	0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CFG_LOAD_ADDR	0x100000	/* default load address	*/
+
+#define CFG_PIO_MODE		0	/* IDE interface in PIO Mode 0	*/
+
+#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#define	CFG_RESET_ADDRESS 0xFFF00100	/* "bad" address		*/
+
+#define CFG_ALLOC_DPRAM
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_SPI
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * Flash configuration
+ */
+
+#define CFG_BOOTROM_BASE	0xFF800000
+#define CFG_BOOTROM_SIZE	0x00080000
+#define CFG_FLASH_BASE		0xFF000000
+#define CFG_FLASH_SIZE		0x00800000
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks      */
+#define CFG_MAX_FLASH_SECT	128	/* max num of sects on one chip */
+
+#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
+#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
+
+#define CONFIG_FLASH_16BIT
+
+/*-----------------------------------------------------------------------
+ * Hard Reset Configuration Words
+ *
+ * if you change bits in the HRCW, you must also change the CFG_*
+ * defines for the various registers affected by the HRCW e.g. changing
+ * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
+ */
+#define CFG_HRCW_MASTER		(HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \
+				 HRCW_BPS10 | HRCW_DPPC10 |\
+				 HRCW_APPC10)
+
+/* no slaves so just fill with zeros */
+#define CFG_HRCW_SLAVE1		0
+#define CFG_HRCW_SLAVE2		0
+#define CFG_HRCW_SLAVE3		0
+#define CFG_HRCW_SLAVE4		0
+#define CFG_HRCW_SLAVE5		0
+#define CFG_HRCW_SLAVE6		0
+#define CFG_HRCW_SLAVE7		0
+
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xF0000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define CFG_INIT_RAM_END	0x2F00  /* End of used area in DPRAM    */
+#define CFG_GBL_DATA_SIZE	128 /* size in bytes reserved for initial data*/
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ *
+ * 60x SDRAM is mapped at CFG_SDRAM_BASE.
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_SDRAM_MAX_SIZE	0x08000000	/* max. 128 MB		*/
+#define CFG_MONITOR_BASE	TEXT_BASE
+#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor */
+#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/
+
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+# define CFG_RAMBOOT
+#endif
+
+#define	CONFIG_PCI
+#define	CONFIG_PCI_PNP
+
+#if 1
+/* environment is in Flash */
+#define CFG_ENV_IS_IN_FLASH	1
+# define CFG_ENV_ADDR		(CFG_FLASH_BASE+0x30000)
+# define CFG_ENV_SIZE		0x10000
+# define CFG_ENV_SECT_SIZE	0x10000
+#else
+#define CFG_ENV_IS_IN_EEPROM	1
+#define CFG_ENV_OFFSET		0
+#define CFG_ENV_SIZE		2048
+#define CFG_EEPROM_PAGE_WRITE_BITS	4	/* 16-byte page size	*/
+#endif
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH*/
+#define BOOTFLAG_WARM		0x02	/* Software reboot                 */
+
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * HIDx - Hardware Implementation-dependent Registers                    2-11
+ *-----------------------------------------------------------------------
+ * HID0 also contains cache control - initially enable both caches and
+ * invalidate contents, then the final state leaves only the instruction
+ * cache enabled. Note that Power-On and Hard reset invalidate the caches,
+ * but Soft reset does not.
+ *
+ * HID1 has only read-only information - nothing to set.
+ */
+#define CFG_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|\
+                         HID0_DCI|HID0_IFEM|HID0_ABE)
+#define CFG_HID0_FINAL  (HID0_IFEM|HID0_ABE)
+#define CFG_HID2        0
+
+/*-----------------------------------------------------------------------
+ * RMR - Reset Mode Register                                     5-5
+ *-----------------------------------------------------------------------
+ * turn on Checkstop Reset Enable
+ */
+#define CFG_RMR         RMR_CSRE
+
+/*-----------------------------------------------------------------------
+ * BCR - Bus Configuration                                       4-25
+ *-----------------------------------------------------------------------
+ */
+#define BCR_APD01	0x10000000
+#define CFG_BCR		(BCR_APD01|BCR_ETM|BCR_LETM)	/* 8260 mode */
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration                             4-31
+ *-----------------------------------------------------------------------
+ */
+#define CFG_SIUMCR      (SIUMCR_BBD|SIUMCR_DPPC10|SIUMCR_APPC10|\
+			 SIUMCR_CS10PC00|SIUMCR_BCTLC10)
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control                             4-35
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+                         SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
+#else
+#define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+                         SYPCR_SWRI|SYPCR_SWP)
+#endif /* CONFIG_WATCHDOG */
+
+/*-----------------------------------------------------------------------
+ * TMCNTSC - Time Counter Status and Control                     4-40
+ *-----------------------------------------------------------------------
+ * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
+ * and enable Time Counter
+ */
+#define CFG_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control                 4-42
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
+ * Periodic timer
+ */
+#define CFG_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock Control                                   9-8
+ *-----------------------------------------------------------------------
+ * Ensure DFBRG is Divide by 16
+ */
+#define CFG_SCCR        SCCR_DFBRG01
+
+/*-----------------------------------------------------------------------
+ * RCCR - RISC Controller Configuration                         13-7
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RCCR        0
+
+#define CFG_MIN_AM_MASK	0xC0000000
+/*-----------------------------------------------------------------------
+ * MPTPR - Memory Refresh Timer Prescaler Register              10-18
+ *-----------------------------------------------------------------------
+ */
+#define CFG_MPTPR       0x1F00
+
+/*-----------------------------------------------------------------------
+ * PSRT - Refresh Timer Register                                10-16
+ *-----------------------------------------------------------------------
+ */
+#define CFG_PSRT        0x0f
+
+/*-----------------------------------------------------------------------
+ * PSRT - SDRAM Mode Register                                   10-10
+ *-----------------------------------------------------------------------
+ */
+
+	/* SDRAM initialization values for 8-column chips
+	 */
+#define CFG_OR2_8COL	(CFG_MIN_AM_MASK		|\
+			 ORxS_BPD_4			|\
+			 ORxS_ROWST_PBI1_A7		|\
+			 ORxS_NUMR_12)
+
+#define CFG_PSDMR_8COL	(PSDMR_PBI			|\
+			 PSDMR_SDAM_A15_IS_A5		|\
+			 PSDMR_BSMA_A15_A17		|\
+			 PSDMR_SDA10_PBI1_A7		|\
+			 PSDMR_RFRC_7_CLK		|\
+			 PSDMR_PRETOACT_3W		|\
+			 PSDMR_ACTTORW_2W		|\
+			 PSDMR_LDOTOPRE_1C		|\
+			 PSDMR_WRC_1C			|\
+			 PSDMR_CL_2)
+
+	/* SDRAM initialization values for 9-column chips
+	 */
+#define CFG_OR2_9COL	(CFG_MIN_AM_MASK		|\
+			 ORxS_BPD_4			|\
+			 ORxS_ROWST_PBI1_A6		|\
+			 ORxS_NUMR_12)
+
+#define CFG_PSDMR_9COL	(PSDMR_PBI			|\
+			 PSDMR_SDAM_A16_IS_A5		|\
+			 PSDMR_BSMA_A15_A17		|\
+			 PSDMR_SDA10_PBI1_A6		|\
+			 PSDMR_RFRC_7_CLK		|\
+			 PSDMR_PRETOACT_3W		|\
+			 PSDMR_ACTTORW_2W		|\
+			 PSDMR_LDOTOPRE_1C		|\
+			 PSDMR_WRC_1C			|\
+			 PSDMR_CL_2)
+
+/*
+ * Init Memory Controller:
+ *
+ * Bank Bus     Machine PortSz  Device
+ * ---- ---     ------- ------  ------
+ *  0   60x     GPCM    8  bit  Boot ROM
+ *  1   60x     GPCM    64 bit  FLASH
+ *  2   60x     SDRAM   64 bit  SDRAM
+ *
+ */
+
+#define CFG_MRS_OFFS	0x00000000
+
+/* Bank 0 - FLASH
+ */
+#define CFG_BR0_PRELIM  ((CFG_FLASH_BASE & BRx_BA_MSK)  |\
+                         BRx_PS_16                      |\
+                         BRx_MS_GPCM_P                  |\
+                         BRx_V)
+
+#define CFG_OR0_PRELIM  (P2SZ_TO_AM(CFG_FLASH_SIZE)     |\
+                         ORxG_CSNT                      |\
+                         ORxG_ACS_DIV1                  |\
+                         ORxG_SCY_3_CLK                 |\
+                         ORxU_EHTR_8IDLE)
+
+
+/* Bank 2 - 60x bus SDRAM
+ */
+#ifndef CFG_RAMBOOT
+#define CFG_BR2_PRELIM  ((CFG_SDRAM_BASE & BRx_BA_MSK)  |\
+                         BRx_PS_64                      |\
+                         BRx_MS_SDRAM_P                 |\
+                         BRx_V)
+
+#define CFG_OR2_PRELIM	 CFG_OR2_8COL
+
+#define CFG_PSDMR	 CFG_PSDMR_8COL
+#endif /* CFG_RAMBOOT */
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CONFIG_I82365
+
+#define CFG_PCMCIA_MEM_ADDR	0x81000000
+#define CFG_PCMCIA_MEM_SIZE	0x1000
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card Adapter */
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE	 not supported	*/
+#undef	CONFIG_IDE_LED			/* LED	 for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_BASE_ADDR	0xa0000000
+
+/* Offset for data I/O			*/
+#define CFG_ATA_DATA_OFFSET	0x100
+
+/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	0x100
+
+/* Offset for alternate registers	*/
+#define CFG_ATA_ALT_OFFSET	0x108
+
+#endif	/* __CONFIG_H */

include/configs/ep8260.h

@@ -270,6 +270,7 @@
 /*
 */
 #define CONFIG_COMMANDS		(	CFG_CMD_ALL     & \
+					~CFG_CMD_BMP	& \
 					~CFG_CMD_BSP    & \
 					~CFG_CMD_DCR    & \
 					~CFG_CMD_DHCP   & \

include/configs/hymod.h

@@ -138,6 +138,7 @@
 
 #define CONFIG_COMMANDS		(CFG_CMD_ALL & ~( \
 					CFG_CMD_BEDBUG	| \
+					CFG_CMD_BMP	| \
 					CFG_CMD_DOC	| \
 					CFG_CMD_ELF	| \
 					CFG_CMD_FDC	| \

include/configs/incaip.h

@@ -31,8 +31,8 @@
 #define CONFIG_MIPS32		1	/* MIPS 4Kc CPU core	*/
 #define CONFIG_INCA_IP		1	/* on a INCA-IP Board	*/
 
-/* allowed values: 100000000 and 150000000 */
-#define CPU_CLOCK_RATE	150000000   /* 150 MHz clock for the MIPS core */
+/* allowed values: 100000000, 133000000, and 150000000 */
+#define CPU_CLOCK_RATE	133000000   /* 133 MHz clock for the MIPS core */
 
 #if CPU_CLOCK_RATE == 100000000
 #define INFINEON_EBU_BOOTCFG	0x20C4	/* CMULT = 4 for 100 MHz */

include/configs/lubbock.h

@@ -53,6 +53,8 @@
 /*
  * Hardware drivers
  */
+#define CONFIG_DRIVER_LAN91C96
+#define CONFIG_LAN91C96_BASE 0x0C000000
 
 /*
  * select serial console configuration
@@ -64,7 +66,7 @@
 
 #define CONFIG_BAUDRATE         115200
 
-#define CONFIG_COMMANDS         (CONFIG_CMD_DFL & ~CFG_CMD_NET)
+#define CONFIG_COMMANDS         (CONFIG_CMD_DFL)
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>

include/configs/lwmon.h

@@ -40,10 +40,13 @@
 #define CONFIG_LWMON		1	/* ...on a LWMON board		*/
 
 #define CONFIG_BOARD_PRE_INIT	1	/* Call board_pre_init		*/
+#define CONFIG_BOARD_POSTCLK_INIT 1	/* Call board_postclk_init	*/
 
 #define CONFIG_LCD		1	/* use LCD controller ...	*/
 #define CONFIG_HLD1045		1	/* ... with a HLD1045 display	*/
 
+#define	CONFIG_SPLASH_SCREEN		/* ... with splashscreen support*/
+
 #if 1
 #define CONFIG_8xx_CONS_SMC2	1	/* Console is on SMC2		*/
 #else
@@ -72,7 +75,8 @@
 				 CFG_POST_I2C	   | \
 				 CFG_POST_SPI	   | \
 				 CFG_POST_USB	   | \
-				 CFG_POST_SPR)
+				 CFG_POST_SPR	   | \
+				 CFG_POST_SYSMON)
 
 #define CONFIG_BOOTCOMMAND	"run flash_self"
 
@@ -134,7 +138,7 @@
 			else    immr->im_cpm.cp_pbdat &= ~PB_SDA
 #define I2C_SCL(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
 			else    immr->im_cpm.cp_pbdat &= ~PB_SCL
-#define I2C_DELAY	udelay(1)	/* 1/4 I2C clock duration */
+#define I2C_DELAY	udelay(2)	/* 1/4 I2C clock duration */
 #endif	/* CONFIG_SOFT_I2C */
 
 
@@ -153,6 +157,7 @@
 				CFG_CMD_EEPROM	| \
 				CFG_CMD_IDE	| \
 				CFG_CMD_BSP	| \
+				CFG_CMD_BMP	| \
 				CFG_CMD_POST_DIAG )
 #else
 #define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
@@ -162,6 +167,7 @@
 				CFG_CMD_EEPROM	| \
 				CFG_CMD_IDE	| \
 				CFG_CMD_BSP	| \
+				CFG_CMD_BMP	| \
 				CFG_CMD_POST_DIAG )
 #endif
 #define CONFIG_MAC_PARTITION
@@ -227,7 +233,7 @@
  */
 #define CFG_INIT_RAM_ADDR	CFG_IMMR
 #define CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_SIZE	68  /* size in bytes reserved for initial data */
 #define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 #define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
 
@@ -569,4 +575,9 @@
 #define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
 #define BOOTFLAG_WARM	0x02		/* Software reboot			*/
 
+#define CONFIG_MODEM_SUPPORT	1	/* enable modem initialization stuff */
+#undef CONFIG_MODEM_SUPPORT_DEBUG
+
+#define	CONFIG_MODEM_KEY_MAGIC	"3C+3F"	/* hold down these keys to enable modem */
+
 #endif	/* __CONFIG_H */

include/configs/purple.h

@@ -150,7 +150,8 @@
  * Temporary buffer for serial data until the real serial driver
  * is initialised (memtest will destroy this buffer)
  */
-#define CFG_SCONSOLE_ADDR     CFG_SDRAM_BASE
-#define CFG_SCONSOLE_SIZE     0x0002000
+#define CFG_SCONSOLE_ADDR     (CFG_SDRAM_BASE + CFG_INIT_SP_OFFSET - \
+			       CFG_DCACHE_SIZE / 2)
+#define CFG_SCONSOLE_SIZE     (CFG_DCACHE_SIZE / 4)
 
 #endif	/* __CONFIG_H */

include/image.h

@@ -45,6 +45,8 @@
 #define IH_OS_PSOS		15	/* pSOS		*/
 #define IH_OS_QNX		16	/* QNX		*/
 #define IH_OS_U_BOOT		17	/* Firmware	*/
+#define IH_OS_RTEMS		18	/* RTEMS	*/
+#define IH_OS_ARTOS		19	/* ARTOS	*/
 
 /*
  * CPU Architecture Codes (supported by Linux)

include/mpc8260.h

@@ -24,12 +24,19 @@
 /*
  * mpc8260.h
  *
- * MPC8260 specific definitions
+ * MPC8255 / MPC8260 specific definitions
  */
 
 #ifndef __MPC8260_H__
 #define __MPC8260_H__
 
+#ifdef CONFIG_MPC8255
+#define CPU_ID_STR	"MPC8255"
+#endif
+#ifndef CPU_ID_STR
+#define CPU_ID_STR	"MPC8260"
+#endif
+
 /*-----------------------------------------------------------------------
  * Exception offsets (PowerPC standard)
  */

include/pci_ids.h

@@ -439,6 +439,7 @@
 #define PCI_DEVICE_ID_TI_1211		0xac1e
 #define PCI_DEVICE_ID_TI_1251B		0xac1f
 #define PCI_DEVICE_ID_TI_1420		0xac51
+#define PCI_DEVICE_ID_TI_1510		0xac56
 
 #define PCI_VENDOR_ID_SONY		0x104d
 #define PCI_DEVICE_ID_SONY_CXD3222	0x8039

include/pcmcia.h

@@ -62,6 +62,8 @@
 # define CONFIG_PCMCIA_SLOT_B
 #elif defined(CONFIG_R360MPI)		/* The R360MPI use SLOT_B	*/
 # define CONFIG_PCMCIA_SLOT_B
+#elif defined(CONFIG_ATC)		/* The ATC use SLOT_A	*/
+# define CONFIG_PCMCIA_SLOT_A
 #else
 # error "PCMCIA Slot not configured"
 #endif

include/pcmcia/i82365.h

@@ -0,0 +1,154 @@
+/*
+ * i82365.h 1.21 2001/08/24 12:15:33
+ *
+ * The contents of this file are subject to the Mozilla Public License
+ * Version 1.1 (the "License"); you may not use this file except in
+ * compliance with the License. You may obtain a copy of the License
+ * at http://www.mozilla.org/MPL/
+ *
+ * Software distributed under the License is distributed on an "AS IS"
+ * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
+ * the License for the specific language governing rights and
+ * limitations under the License. 
+ *
+ * The initial developer of the original code is David A. Hinds
+ * <dahinds@users.sourceforge.net>.  Portions created by David A. Hinds
+ * are Copyright (C) 1999 David A. Hinds.  All Rights Reserved.
+ *
+ * Alternatively, the contents of this file may be used under the
+ * terms of the GNU General Public License version 2 (the "GPL"), in
+ * which case the provisions of the GPL are applicable instead of the
+ * above.  If you wish to allow the use of your version of this file
+ * only under the terms of the GPL and not to allow others to use
+ * your version of this file under the MPL, indicate your decision by
+ * deleting the provisions above and replace them with the notice and
+ * other provisions required by the GPL.  If you do not delete the
+ * provisions above, a recipient may use your version of this file
+ * under either the MPL or the GPL.
+ */
+
+#ifndef _LINUX_I82365_H
+#define _LINUX_I82365_H
+
+/* register definitions for the Intel 82365SL PCMCIA controller */
+
+/* Offsets for PCIC registers */
+#define I365_IDENT	0x00	/* Identification and revision */
+#define I365_STATUS	0x01	/* Interface status */
+#define I365_POWER	0x02	/* Power and RESETDRV control */
+#define I365_INTCTL	0x03	/* Interrupt and general control */
+#define I365_CSC	0x04	/* Card status change */
+#define I365_CSCINT	0x05	/* Card status change interrupt control */
+#define I365_ADDRWIN	0x06	/* Address window enable */
+#define I365_IOCTL	0x07	/* I/O control */
+#define I365_GENCTL	0x16	/* Card detect and general control */
+#define I365_GBLCTL	0x1E	/* Global control register */
+
+/* Offsets for I/O and memory window registers */
+#define I365_IO(map)	(0x08+((map)<<2))
+#define I365_MEM(map)	(0x10+((map)<<3))
+#define I365_W_START	0
+#define I365_W_STOP	2
+#define I365_W_OFF	4
+
+/* Flags for I365_STATUS */
+#define I365_CS_BVD1	0x01
+#define I365_CS_STSCHG	0x01
+#define I365_CS_BVD2	0x02
+#define I365_CS_SPKR	0x02
+#define I365_CS_DETECT	0x0C
+#define I365_CS_WRPROT	0x10
+#define I365_CS_READY	0x20	/* Inverted */
+#define I365_CS_POWERON	0x40
+#define I365_CS_GPI	0x80
+
+/* Flags for I365_POWER */
+#define I365_PWR_OFF	0x00	/* Turn off the socket */
+#define I365_PWR_OUT	0x80	/* Output enable */
+#define I365_PWR_NORESET 0x40	/* Disable RESETDRV on resume */
+#define I365_PWR_AUTO	0x20	/* Auto pwr switch enable */
+#define I365_VCC_MASK	0x18	/* Mask for turning off Vcc */
+/* There are different layouts for B-step and DF-step chips: the B
+   step has independent Vpp1/Vpp2 control, and the DF step has only
+   Vpp1 control, plus 3V control */
+#define I365_VCC_5V	0x10	/* Vcc = 5.0v */
+#define I365_VCC_3V	0x18	/* Vcc = 3.3v */
+#define I365_VPP2_MASK	0x0c	/* Mask for turning off Vpp2 */
+#define I365_VPP2_5V	0x04	/* Vpp2 = 5.0v */
+#define I365_VPP2_12V	0x08	/* Vpp2 = 12.0v */
+#define I365_VPP1_MASK	0x03	/* Mask for turning off Vpp1 */
+#define I365_VPP1_5V	0x01	/* Vpp2 = 5.0v */
+#define I365_VPP1_12V	0x02	/* Vpp2 = 12.0v */
+
+/* Flags for I365_INTCTL */
+#define I365_RING_ENA	0x80
+#define I365_PC_RESET	0x40
+#define I365_PC_IOCARD	0x20
+#define I365_INTR_ENA	0x10
+#define I365_IRQ_MASK	0x0F
+
+/* Flags for I365_CSC and I365_CSCINT*/
+#define I365_CSC_BVD1	0x01
+#define I365_CSC_STSCHG	0x01
+#define I365_CSC_BVD2	0x02
+#define I365_CSC_READY	0x04
+#define I365_CSC_DETECT	0x08
+#define I365_CSC_ANY	0x0F
+#define I365_CSC_GPI	0x10
+
+/* Flags for I365_ADDRWIN */
+#define I365_ADDR_MEMCS16	0x20
+#define I365_ENA_IO(map)	(0x40 << (map))
+#define I365_ENA_MEM(map)	(0x01 << (map))
+
+/* Flags for I365_IOCTL */
+#define I365_IOCTL_MASK(map)	(0x0F << (map<<2))
+#define I365_IOCTL_WAIT(map)	(0x08 << (map<<2))
+#define I365_IOCTL_0WS(map)	(0x04 << (map<<2))
+#define I365_IOCTL_IOCS16(map)	(0x02 << (map<<2))
+#define I365_IOCTL_16BIT(map)	(0x01 << (map<<2))
+
+/* Flags for I365_GENCTL */
+#define I365_CTL_16DELAY	0x01
+#define I365_CTL_RESET		0x02
+#define I365_CTL_GPI_ENA	0x04
+#define I365_CTL_GPI_CTL	0x08
+#define I365_CTL_RESUME		0x10
+#define I365_CTL_SW_IRQ		0x20
+
+/* Flags for I365_GBLCTL */
+#define I365_GBL_PWRDOWN	0x01
+#define I365_GBL_CSC_LEV	0x02
+#define I365_GBL_WRBACK		0x04
+#define I365_GBL_IRQ_0_LEV	0x08
+#define I365_GBL_IRQ_1_LEV	0x10
+
+/* Flags for memory window registers */
+#define I365_MEM_16BIT	0x8000	/* In memory start high byte */
+#define I365_MEM_0WS	0x4000
+#define I365_MEM_WS1	0x8000	/* In memory stop high byte */
+#define I365_MEM_WS0	0x4000
+#define I365_MEM_WRPROT	0x8000	/* In offset high byte */
+#define I365_MEM_REG	0x4000
+
+#define I365_REG(slot, reg)	(((slot) << 6) | (reg))
+
+/* Default ISA interrupt mask */
+#define I365_ISA_IRQ_MASK	0xdeb8	/* irq's 3-5,7,9-12,14,15 */
+
+/* Device ID's for PCI-to-PCMCIA bridges */
+
+#ifndef PCI_VENDOR_ID_INTEL
+#define PCI_VENDOR_ID_INTEL		0x8086
+#endif
+#ifndef PCI_DEVICE_ID_INTEL_82092AA_0
+#define PCI_DEVICE_ID_INTEL_82092AA_0	0x1221
+#endif
+#ifndef PCI_VENDOR_ID_OMEGA
+#define PCI_VENDOR_ID_OMEGA		0x119b
+#endif
+#ifndef PCI_DEVICE_ID_OMEGA_82C092G
+#define PCI_DEVICE_ID_OMEGA_82C092G	0x1221
+#endif
+
+#endif /* _LINUX_I82365_H */

include/pcmcia/ss.h

@@ -0,0 +1,133 @@
+/*
+ * ss.h 1.31 2001/08/24 12:16:13
+ *
+ * The contents of this file are subject to the Mozilla Public License
+ * Version 1.1 (the "License"); you may not use this file except in
+ * compliance with the License. You may obtain a copy of the License
+ * at http://www.mozilla.org/MPL/
+ *
+ * Software distributed under the License is distributed on an "AS IS"
+ * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
+ * the License for the specific language governing rights and
+ * limitations under the License. 
+ *
+ * The initial developer of the original code is David A. Hinds
+ * <dahinds@users.sourceforge.net>.  Portions created by David A. Hinds
+ * are Copyright (C) 1999 David A. Hinds.  All Rights Reserved.
+ *
+ * Alternatively, the contents of this file may be used under the
+ * terms of the GNU General Public License version 2 (the "GPL"), in
+ * which case the provisions of the GPL are applicable instead of the
+ * above.  If you wish to allow the use of your version of this file
+ * only under the terms of the GPL and not to allow others to use
+ * your version of this file under the MPL, indicate your decision by
+ * deleting the provisions above and replace them with the notice and
+ * other provisions required by the GPL.  If you do not delete the
+ * provisions above, a recipient may use your version of this file
+ * under either the MPL or the GPL.
+ */
+
+#ifndef _LINUX_SS_H
+#define _LINUX_SS_H
+
+/* For RegisterCallback */
+typedef struct ss_callback_t {
+    void	(*handler)(void *info, u_int events);
+    void	*info;
+} ss_callback_t;
+
+/* Definitions for card status flags for GetStatus */
+#define SS_WRPROT	0x0001
+#define SS_CARDLOCK	0x0002
+#define SS_EJECTION	0x0004
+#define SS_INSERTION	0x0008
+#define SS_BATDEAD	0x0010
+#define SS_BATWARN	0x0020
+#define SS_READY	0x0040
+#define SS_DETECT	0x0080
+#define SS_POWERON	0x0100
+#define SS_GPI		0x0200
+#define SS_STSCHG	0x0400
+#define SS_CARDBUS	0x0800
+#define SS_3VCARD	0x1000
+#define SS_XVCARD	0x2000
+#define SS_PENDING	0x4000
+
+/* for InquireSocket */
+typedef struct socket_cap_t {
+    u_int	features;
+    u_int	irq_mask;
+    u_int	map_size;
+    u_char	pci_irq;
+    u_char	cardbus;
+    struct pci_bus *cb_bus;
+    struct bus_operations *bus;
+} socket_cap_t;
+
+/* InquireSocket capabilities */
+#define SS_CAP_PAGE_REGS	0x0001
+#define SS_CAP_VIRTUAL_BUS	0x0002
+#define SS_CAP_MEM_ALIGN	0x0004
+#define SS_CAP_STATIC_MAP	0x0008
+#define SS_CAP_PCCARD		0x4000
+#define SS_CAP_CARDBUS		0x8000
+
+/* for GetSocket, SetSocket */
+typedef struct socket_state_t {
+    u_int	flags;
+    u_int	csc_mask;
+    u_char	Vcc, Vpp;
+    u_char	io_irq;
+} socket_state_t;
+
+/* Socket configuration flags */
+#define SS_PWR_AUTO	0x0010
+#define SS_IOCARD	0x0020
+#define SS_RESET	0x0040
+#define SS_DMA_MODE	0x0080
+#define SS_SPKR_ENA	0x0100
+#define SS_OUTPUT_ENA	0x0200
+#define SS_ZVCARD	0x0400
+
+/* Flags for I/O port and memory windows */
+#define MAP_ACTIVE	0x01
+#define MAP_16BIT	0x02
+#define MAP_AUTOSZ	0x04
+#define MAP_0WS		0x08
+#define MAP_WRPROT	0x10
+#define MAP_ATTRIB	0x20
+#define MAP_USE_WAIT	0x40
+#define MAP_PREFETCH	0x80
+
+/* Use this just for bridge windows */
+#define MAP_IOSPACE	0x20
+
+typedef struct pccard_io_map {
+    u_char	map;
+    u_char	flags;
+    u_short	speed;
+    u_short	start, stop;
+} pccard_io_map;
+
+typedef struct pccard_mem_map {
+    u_char	map;
+    u_char	flags;
+    u_short	speed;
+    u_long	sys_start, sys_stop;
+    u_int	card_start;
+} pccard_mem_map;
+
+typedef struct cb_bridge_map {
+    u_char	map;
+    u_char	flags;
+    u_int	start, stop;
+} cb_bridge_map;
+
+enum ss_service {
+    SS_RegisterCallback, SS_InquireSocket,
+    SS_GetStatus, SS_GetSocket, SS_SetSocket,
+    SS_GetIOMap, SS_SetIOMap, SS_GetMemMap, SS_SetMemMap,
+    SS_GetBridge, SS_SetBridge, SS_ProcSetup
+};
+
+#endif /* _LINUX_SS_H */

include/pcmcia/ti113x.h

@@ -0,0 +1,234 @@
+/*
+ * ti113x.h 1.31 2002/05/12 18:19:47
+ *
+ * The contents of this file are subject to the Mozilla Public License
+ * Version 1.1 (the "License"); you may not use this file except in
+ * compliance with the License. You may obtain a copy of the License
+ * at http://www.mozilla.org/MPL/
+ *
+ * Software distributed under the License is distributed on an "AS IS"
+ * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
+ * the License for the specific language governing rights and
+ * limitations under the License. 
+ *
+ * The initial developer of the original code is David A. Hinds
+ * <dahinds@users.sourceforge.net>.  Portions created by David A. Hinds
+ * are Copyright (C) 1999 David A. Hinds.  All Rights Reserved.
+ *
+ * Alternatively, the contents of this file may be used under the
+ * terms of the GNU General Public License version 2 (the "GPL"), in
+ * which case the provisions of the GPL are applicable instead of the
+ * above.  If you wish to allow the use of your version of this file
+ * only under the terms of the GPL and not to allow others to use
+ * your version of this file under the MPL, indicate your decision by
+ * deleting the provisions above and replace them with the notice and
+ * other provisions required by the GPL.  If you do not delete the
+ * provisions above, a recipient may use your version of this file
+ * under either the MPL or the GPL.
+ */
+
+#ifndef _LINUX_TI113X_H
+#define _LINUX_TI113X_H
+
+#ifndef PCI_VENDOR_ID_TI
+#define PCI_VENDOR_ID_TI		0x104c
+#endif
+
+#ifndef PCI_DEVICE_ID_TI_1130
+#define PCI_DEVICE_ID_TI_1130		0xac12
+#endif
+#ifndef PCI_DEVICE_ID_TI_1031
+#define PCI_DEVICE_ID_TI_1031		0xac13
+#endif
+#ifndef PCI_DEVICE_ID_TI_1131
+#define PCI_DEVICE_ID_TI_1131		0xac15
+#endif
+#ifndef PCI_DEVICE_ID_TI_1210
+#define PCI_DEVICE_ID_TI_1210		0xac1a
+#endif
+#ifndef PCI_DEVICE_ID_TI_1211
+#define PCI_DEVICE_ID_TI_1211		0xac1e
+#endif
+#ifndef PCI_DEVICE_ID_TI_1220
+#define PCI_DEVICE_ID_TI_1220		0xac17
+#endif
+#ifndef PCI_DEVICE_ID_TI_1221
+#define PCI_DEVICE_ID_TI_1221		0xac19
+#endif
+#ifndef PCI_DEVICE_ID_TI_1250A
+#define PCI_DEVICE_ID_TI_1250A		0xac16
+#endif
+#ifndef PCI_DEVICE_ID_TI_1225
+#define PCI_DEVICE_ID_TI_1225		0xac1c
+#endif
+#ifndef PCI_DEVICE_ID_TI_1251A
+#define PCI_DEVICE_ID_TI_1251A		0xac1d
+#endif
+#ifndef PCI_DEVICE_ID_TI_1251B
+#define PCI_DEVICE_ID_TI_1251B		0xac1f
+#endif
+#ifndef PCI_DEVICE_ID_TI_1410
+#define PCI_DEVICE_ID_TI_1410		0xac50
+#endif
+#ifndef PCI_DEVICE_ID_TI_1420
+#define PCI_DEVICE_ID_TI_1420		0xac51
+#endif
+#ifndef PCI_DEVICE_ID_TI_1450
+#define PCI_DEVICE_ID_TI_1450		0xac1b
+#endif
+#ifndef PCI_DEVICE_ID_TI_1451
+#define PCI_DEVICE_ID_TI_1451		0xac52
+#endif
+#ifndef PCI_DEVICE_ID_TI_1510
+#define PCI_DEVICE_ID_TI_1510		0xac56
+#endif
+#ifndef PCI_DEVICE_ID_TI_4410
+#define PCI_DEVICE_ID_TI_4410		0xac41
+#endif
+#ifndef PCI_DEVICE_ID_TI_4450
+#define PCI_DEVICE_ID_TI_4450		0xac40
+#endif
+#ifndef PCI_DEVICE_ID_TI_4451
+#define PCI_DEVICE_ID_TI_4451		0xac42
+#endif
+
+/* Register definitions for TI 113X PCI-to-CardBus bridges */
+
+/* System Control Register */
+#define TI113X_SYSTEM_CONTROL		0x80	/* 32 bit */
+#define  TI113X_SCR_SMIROUTE		0x04000000
+#define  TI113X_SCR_SMISTATUS		0x02000000
+#define  TI113X_SCR_SMIENB		0x01000000
+#define  TI113X_SCR_VCCPROT		0x00200000
+#define  TI113X_SCR_REDUCEZV		0x00100000
+#define  TI113X_SCR_CDREQEN		0x00080000
+#define  TI113X_SCR_CDMACHAN		0x00070000
+#define  TI113X_SCR_SOCACTIVE		0x00002000
+#define  TI113X_SCR_PWRSTREAM		0x00000800
+#define  TI113X_SCR_DELAYUP		0x00000400
+#define  TI113X_SCR_DELAYDOWN		0x00000200
+#define  TI113X_SCR_INTERROGATE		0x00000100
+#define  TI113X_SCR_CLKRUN_SEL		0x00000080
+#define  TI113X_SCR_PWRSAVINGS		0x00000040
+#define  TI113X_SCR_SUBSYSRW		0x00000020
+#define  TI113X_SCR_CB_DPAR		0x00000010
+#define  TI113X_SCR_CDMA_EN		0x00000008
+#define  TI113X_SCR_ASYNC_IRQ		0x00000004
+#define  TI113X_SCR_KEEPCLK		0x00000002
+#define  TI113X_SCR_CLKRUN_ENA		0x00000001  
+
+#define  TI122X_SCR_SER_STEP		0xc0000000
+#define  TI122X_SCR_INTRTIE		0x20000000
+#define  TI122X_SCR_P2CCLK		0x08000000
+#define  TI122X_SCR_CBRSVD		0x00400000
+#define  TI122X_SCR_MRBURSTDN		0x00008000
+#define  TI122X_SCR_MRBURSTUP		0x00004000
+#define  TI122X_SCR_RIMUX		0x00000001
+
+/* Multimedia Control Register */
+#define TI1250_MULTIMEDIA_CTL		0x84	/* 8 bit */
+#define  TI1250_MMC_ZVOUTEN		0x80
+#define  TI1250_MMC_PORTSEL		0x40
+#define  TI1250_MMC_ZVEN1		0x02
+#define  TI1250_MMC_ZVEN0		0x01
+
+#define TI1250_GENERAL_STATUS		0x85	/* 8 bit */
+#define TI1250_GPIO0_CONTROL		0x88	/* 8 bit */
+#define TI1250_GPIO1_CONTROL		0x89	/* 8 bit */
+#define TI1250_GPIO2_CONTROL		0x8a	/* 8 bit */
+#define TI1250_GPIO3_CONTROL		0x8b	/* 8 bit */
+#define TI12XX_IRQMUX			0x8c	/* 32 bit */
+
+/* Retry Status Register */
+#define TI113X_RETRY_STATUS		0x90	/* 8 bit */
+#define  TI113X_RSR_PCIRETRY		0x80
+#define  TI113X_RSR_CBRETRY		0x40
+#define  TI113X_RSR_TEXP_CBB		0x20
+#define  TI113X_RSR_MEXP_CBB		0x10
+#define  TI113X_RSR_TEXP_CBA		0x08
+#define  TI113X_RSR_MEXP_CBA		0x04
+#define  TI113X_RSR_TEXP_PCI		0x02
+#define  TI113X_RSR_MEXP_PCI		0x01
+
+/* Card Control Register */
+#define TI113X_CARD_CONTROL		0x91	/* 8 bit */
+#define  TI113X_CCR_RIENB		0x80
+#define  TI113X_CCR_ZVENABLE		0x40
+#define  TI113X_CCR_PCI_IRQ_ENA		0x20
+#define  TI113X_CCR_PCI_IREQ		0x10
+#define  TI113X_CCR_PCI_CSC		0x08
+#define  TI113X_CCR_SPKROUTEN		0x02
+#define  TI113X_CCR_IFG			0x01
+
+#define  TI1220_CCR_PORT_SEL		0x20
+#define  TI122X_CCR_AUD2MUX		0x04
+
+/* Device Control Register */
+#define TI113X_DEVICE_CONTROL		0x92	/* 8 bit */
+#define  TI113X_DCR_5V_FORCE		0x40
+#define  TI113X_DCR_3V_FORCE		0x20
+#define  TI113X_DCR_IMODE_MASK		0x06
+#define  TI113X_DCR_IMODE_ISA		0x02
+#define  TI113X_DCR_IMODE_SERIAL	0x04
+
+#define  TI12XX_DCR_IMODE_PCI_ONLY	0x00
+#define  TI12XX_DCR_IMODE_ALL_SERIAL	0x06
+
+/* Buffer Control Register */
+#define TI113X_BUFFER_CONTROL		0x93	/* 8 bit */
+#define  TI113X_BCR_CB_READ_DEPTH	0x08
+#define  TI113X_BCR_CB_WRITE_DEPTH	0x04
+#define  TI113X_BCR_PCI_READ_DEPTH	0x02
+#define  TI113X_BCR_PCI_WRITE_DEPTH	0x01
+
+/* Diagnostic Register */
+#define TI1250_DIAGNOSTIC		0x93	/* 8 bit */
+#define  TI1250_DIAG_TRUE_VALUE		0x80
+#define  TI1250_DIAG_PCI_IREQ		0x40
+#define  TI1250_DIAG_PCI_CSC		0x20
+#define  TI1250_DIAG_ASYNC_CSC		0x01
+
+/* DMA Registers */
+#define TI113X_DMA_0			0x94	/* 32 bit */
+#define TI113X_DMA_1			0x98	/* 32 bit */
+
+/* ExCA IO offset registers */
+#define TI113X_IO_OFFSET(map)		(0x36+((map)<<1))
+
+/* Data structure for tracking vendor-specific state */
+typedef struct ti113x_state_t {
+    u32			sysctl;		/* TI113X_SYSTEM_CONTROL */
+    u8			cardctl;	/* TI113X_CARD_CONTROL */
+    u8			devctl;		/* TI113X_DEVICE_CONTROL */
+    u8			diag;		/* TI1250_DIAGNOSTIC */
+    u32			irqmux;		/* TI12XX_IRQMUX */
+} ti113x_state_t;
+
+#define TI_PCIC_ID \
+    IS_TI1130, IS_TI1131, IS_TI1031, IS_TI1210, IS_TI1211,	\
+    IS_TI1220, IS_TI1221, IS_TI1225, IS_TI1250A, IS_TI1251A,	\
+    IS_TI1251B, IS_TI1410, IS_TI1420, IS_TI1450, IS_TI1451,	\
+    IS_TI1510, IS_TI4410, IS_TI4450, IS_TI4451
+
+#define TI_PCIC_INFO \
+    { "TI 1130",  IS_TI|IS_CARDBUS, ID(TI, 1130) }, \
+    { "TI 1131",  IS_TI|IS_CARDBUS, ID(TI, 1131) }, \
+    { "TI 1031",  IS_TI|IS_CARDBUS, ID(TI, 1031) }, \
+    { "TI 1210",  IS_TI|IS_CARDBUS, ID(TI, 1210) }, \
+    { "TI 1211",  IS_TI|IS_CARDBUS, ID(TI, 1211) }, \
+    { "TI 1220",  IS_TI|IS_CARDBUS, ID(TI, 1220) }, \
+    { "TI 1221",  IS_TI|IS_CARDBUS, ID(TI, 1221) }, \
+    { "TI 1225",  IS_TI|IS_CARDBUS, ID(TI, 1225) }, \
+    { "TI 1250A", IS_TI|IS_CARDBUS, ID(TI, 1250A) }, \
+    { "TI 1251A", IS_TI|IS_CARDBUS, ID(TI, 1251A) }, \
+    { "TI 1251B", IS_TI|IS_CARDBUS, ID(TI, 1251B) }, \
+    { "TI 1410",  IS_TI|IS_CARDBUS, ID(TI, 1410) }, \
+    { "TI 1420",  IS_TI|IS_CARDBUS, ID(TI, 1420) }, \
+    { "TI 1450",  IS_TI|IS_CARDBUS, ID(TI, 1450) }, \
+    { "TI 1451",  IS_TI|IS_CARDBUS, ID(TI, 1451) }, \
+    { "TI 1510",  IS_TI|IS_CARDBUS, ID(TI, 1510) }, \
+    { "TI 4410",  IS_TI|IS_CARDBUS, ID(TI, 4410) }, \
+    { "TI 4450",  IS_TI|IS_CARDBUS, ID(TI, 4450) }, \
+    { "TI 4451",  IS_TI|IS_CARDBUS, ID(TI, 4451) }
+
+#endif /* _LINUX_TI113X_H */

include/pcmcia/yenta.h

@@ -0,0 +1,156 @@
+/*
+ * yenta.h 1.20 2001/08/24 12:15:34
+ *
+ * The contents of this file are subject to the Mozilla Public License
+ * Version 1.1 (the "License"); you may not use this file except in
+ * compliance with the License. You may obtain a copy of the License
+ * at http://www.mozilla.org/MPL/
+ *
+ * Software distributed under the License is distributed on an "AS IS"
+ * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
+ * the License for the specific language governing rights and
+ * limitations under the License. 
+ *
+ * The initial developer of the original code is David A. Hinds
+ * <dahinds@users.sourceforge.net>.  Portions created by David A. Hinds
+ * are Copyright (C) 1999 David A. Hinds.  All Rights Reserved.
+ *
+ * Alternatively, the contents of this file may be used under the
+ * terms of the GNU General Public License version 2 (the "GPL"), in
+ * which case the provisions of the GPL are applicable instead of the
+ * above.  If you wish to allow the use of your version of this file
+ * only under the terms of the GPL and not to allow others to use
+ * your version of this file under the MPL, indicate your decision by
+ * deleting the provisions above and replace them with the notice and
+ * other provisions required by the GPL.  If you do not delete the
+ * provisions above, a recipient may use your version of this file
+ * under either the MPL or the GPL.
+ */
+
+#ifndef _LINUX_YENTA_H
+#define _LINUX_YENTA_H
+
+/* PCI Configuration Registers */
+
+#define PCI_STATUS_CAPLIST		0x10
+#define PCI_CB_CAPABILITY_POINTER	0x14	/* 8 bit */
+#define PCI_CAPABILITY_ID		0x00	/* 8 bit */
+#define  PCI_CAPABILITY_PM		0x01
+#define PCI_NEXT_CAPABILITY		0x01	/* 8 bit */
+#define PCI_PM_CAPABILITIES		0x02	/* 16 bit */
+#define  PCI_PMCAP_PME_D3COLD		0x8000
+#define  PCI_PMCAP_PME_D3HOT		0x4000
+#define  PCI_PMCAP_PME_D2		0x2000
+#define  PCI_PMCAP_PME_D1		0x1000
+#define  PCI_PMCAP_PME_D0		0x0800
+#define  PCI_PMCAP_D2_CAP		0x0400
+#define  PCI_PMCAP_D1_CAP		0x0200
+#define  PCI_PMCAP_DYN_DATA		0x0100
+#define  PCI_PMCAP_DSI			0x0020
+#define  PCI_PMCAP_AUX_PWR		0x0010
+#define  PCI_PMCAP_PMECLK		0x0008
+#define  PCI_PMCAP_VERSION_MASK		0x0007
+#define PCI_PM_CONTROL_STATUS		0x04	/* 16 bit */
+#define  PCI_PMCS_PME_STATUS		0x8000
+#define  PCI_PMCS_DATASCALE_MASK	0x6000
+#define  PCI_PMCS_DATASCALE_SHIFT	13
+#define  PCI_PMCS_DATASEL_MASK		0x1e00
+#define  PCI_PMCS_DATASEL_SHIFT		9
+#define  PCI_PMCS_PME_ENABLE		0x0100
+#define  PCI_PMCS_PWR_STATE_MASK	0x0003
+#define  PCI_PMCS_PWR_STATE_D0		0x0000
+#define  PCI_PMCS_PWR_STATE_D1		0x0001
+#define  PCI_PMCS_PWR_STATE_D2		0x0002
+#define  PCI_PMCS_PWR_STATE_D3		0x0003
+#define PCI_PM_BRIDGE_EXT		0x06	/* 8 bit */
+#define PCI_PM_DATA			0x07	/* 8 bit */
+
+#define CB_PRIMARY_BUS			0x18	/* 8 bit */
+#define CB_CARDBUS_BUS			0x19	/* 8 bit */
+#define CB_SUBORD_BUS			0x1a	/* 8 bit */
+#define CB_LATENCY_TIMER		0x1b	/* 8 bit */
+
+#define CB_MEM_BASE(m)			(0x1c + 8*(m))
+#define CB_MEM_LIMIT(m)			(0x20 + 8*(m))
+#define CB_IO_BASE(m)			(0x2c + 8*(m))
+#define CB_IO_LIMIT(m)			(0x30 + 8*(m))
+
+#define CB_BRIDGE_CONTROL		0x3e	/* 16 bit */
+#define  CB_BCR_PARITY_ENA		0x0001
+#define  CB_BCR_SERR_ENA		0x0002
+#define  CB_BCR_ISA_ENA			0x0004
+#define  CB_BCR_VGA_ENA			0x0008
+#define  CB_BCR_MABORT			0x0020
+#define  CB_BCR_CB_RESET		0x0040
+#define  CB_BCR_ISA_IRQ			0x0080
+#define  CB_BCR_PREFETCH(m)		(0x0100 << (m))
+#define  CB_BCR_WRITE_POST		0x0400
+
+#define CB_LEGACY_MODE_BASE		0x44
+
+/* Memory mapped registers */
+
+#define CB_SOCKET_EVENT			0x0000
+#define  CB_SE_CSTSCHG			0x00000001
+#define  CB_SE_CCD			0x00000006
+#define  CB_SE_CCD1			0x00000002
+#define  CB_SE_CCD2			0x00000004
+#define  CB_SE_PWRCYCLE			0x00000008
+
+#define CB_SOCKET_MASK			0x0004
+#define  CB_SM_CSTSCHG			0x00000001
+#define  CB_SM_CCD			0x00000006
+#define  CB_SM_PWRCYCLE			0x00000008
+
+#define CB_SOCKET_STATE			0x0008
+#define  CB_SS_CSTSCHG			0x00000001
+#define  CB_SS_CCD			0x00000006
+#define  CB_SS_CCD1			0x00000002
+#define  CB_SS_CCD2			0x00000004
+#define  CB_SS_PWRCYCLE			0x00000008
+#define  CB_SS_16BIT			0x00000010
+#define  CB_SS_32BIT			0x00000020
+#define  CB_SS_CINT			0x00000040
+#define  CB_SS_BADCARD			0x00000080
+#define  CB_SS_DATALOST			0x00000100
+#define  CB_SS_BADVCC			0x00000200
+#define  CB_SS_5VCARD			0x00000400
+#define  CB_SS_3VCARD			0x00000800
+#define  CB_SS_XVCARD			0x00001000
+#define  CB_SS_YVCARD			0x00002000
+#define  CB_SS_VSENSE			0x00003c86
+#define  CB_SS_5VSOCKET			0x10000000
+#define  CB_SS_3VSOCKET			0x20000000
+#define  CB_SS_XVSOCKET			0x40000000
+#define  CB_SS_YVSOCKET			0x80000000
+
+#define CB_SOCKET_FORCE			0x000c
+#define  CB_SF_CVSTEST			0x00004000
+
+#define CB_SOCKET_CONTROL		0x0010
+#define  CB_SC_VPP_MASK			0x00000007
+#define   CB_SC_VPP_OFF			0x00000000
+#define   CB_SC_VPP_12V			0x00000001
+#define   CB_SC_VPP_5V			0x00000002
+#define   CB_SC_VPP_3V			0x00000003
+#define   CB_SC_VPP_XV			0x00000004
+#define   CB_SC_VPP_YV			0x00000005
+#define  CB_SC_VCC_MASK			0x00000070
+#define   CB_SC_VCC_OFF			0x00000000
+#define   CB_SC_VCC_5V			0x00000020
+#define   CB_SC_VCC_3V			0x00000030
+#define   CB_SC_VCC_XV			0x00000040
+#define   CB_SC_VCC_YV			0x00000050
+#define  CB_SC_CCLK_STOP		0x00000080
+
+#define CB_SOCKET_POWER			0x0020
+#define  CB_SP_CLK_CTRL			0x00000001
+#define  CB_SP_CLK_CTRL_ENA		0x00010000
+#define  CB_SP_CLK_MODE			0x01000000
+#define  CB_SP_ACCESS			0x02000000
+
+/* Address bits 31..24 for memory windows for 16-bit cards,
+   accessable only by memory mapping the 16-bit register set */
+#define CB_MEM_PAGE(map)		(0x40 + (map))
+
+#endif /* _LINUX_YENTA_H */

include/post.h

@@ -54,8 +54,11 @@ struct post_test {
 	char *desc;
 	int flags;
 	int (*test) (int flags);
+	int (*init_f) (void);
+	void (*reloc) (void);
 	unsigned long testid;
 };
+int post_init_f (void);
 void post_bootmode_init (void);
 int post_bootmode_get (unsigned int * last_test);
 void post_bootmode_clear (void);
@@ -64,6 +67,7 @@ int post_run (char *name, int flags);
 int post_info (char *name);
 int post_log (char *format, ...);
 void post_reloc (void);
+unsigned long post_time_ms (unsigned long base);
 
 extern struct post_test post_list[];
 extern unsigned int post_list_size;
@@ -81,6 +85,7 @@ extern unsigned int post_list_size;
 #define CFG_POST_SPI		0x00000100
 #define CFG_POST_USB		0x00000200
 #define CFG_POST_SPR		0x00000400
+#define CFG_POST_SYSMON		0x00000800
 
 #endif /* CONFIG_POST */
 

include/status_led.h

@@ -97,20 +97,20 @@ void status_led_set  (int led, int state);
 # define STATUS_LED_DAT			im_ioport.iop_padat
 
 # define STATUS_LED_BIT			0x0800	/* Red LED 0 is on PA.4	*/
-# define STATUS_LED_PERIOD		(CFG_HZ / 2)
-# define STATUS_LED_STATE		STATUS_LED_BLINKING
+# define STATUS_LED_PERIOD		(CFG_HZ / 4)
+# define STATUS_LED_STATE		STATUS_LED_OFF
 # define STATUS_LED_BIT1		0x0400	/* Grn LED 1 is on PA.5	*/
-# define STATUS_LED_PERIOD1		(CFG_HZ / 2)
+# define STATUS_LED_PERIOD1		(CFG_HZ / 8)
 # define STATUS_LED_STATE1		STATUS_LED_BLINKING
 # define STATUS_LED_BIT2		0x0080	/* Red LED 2 is on PA.8	*/
-# define STATUS_LED_PERIOD2		(CFG_HZ / 2)
-# define STATUS_LED_STATE2		STATUS_LED_BLINKING
+# define STATUS_LED_PERIOD2		(CFG_HZ / 4)
+# define STATUS_LED_STATE2		STATUS_LED_OFF
 # define STATUS_LED_BIT3		0x0040	/* Grn LED 3 is on PA.9	*/
-# define STATUS_LED_PERIOD3		(CFG_HZ / 2)
-# define STATUS_LED_STATE3		STATUS_LED_BLINKING
+# define STATUS_LED_PERIOD3		(CFG_HZ / 4)
+# define STATUS_LED_STATE3		STATUS_LED_OFF
 
 # define STATUS_LED_ACTIVE		1	/* LED on for bit == 1	*/
-# define STATUS_LED_BOOT		0	/* Boot status on LED 1	*/
+# define STATUS_LED_BOOT		1	/* Boot status on LED 1	*/
 
 /*****  IVMS8  **********************************************************/
 #elif defined(CONFIG_IVMS8)

include/version.h

@@ -24,6 +24,6 @@
 #ifndef	__VERSION_H__
 #define	__VERSION_H__
 
-#define	U_BOOT_VERSION	"U-Boot 0.3.1"
+#define	U_BOOT_VERSION	"U-Boot 0.3.2"
 
 #endif	/* __VERSION_H__ */

lib_arm/board.c

@@ -42,6 +42,9 @@ const char version_string[] =
 extern void cs8900_get_enetaddr (uchar * addr);
 #endif
 
+#ifdef CONFIG_DRIVER_LAN91C96
+#include "../drivers/lan91c96.h"
+#endif
 /*
  * Begin and End of memory area for malloc(), and current "brk"
  */
@@ -275,6 +278,13 @@ void start_armboot (void)
 	cs8900_get_enetaddr (gd->bd->bi_enetaddr);
 #endif
 
+#ifdef CONFIG_DRIVER_LAN91C96
+	if (getenv ("ethaddr")) {
+		smc_set_mac_addr(gd->bd->bi_enetaddr);
+	}
+	/* eth_hw_init(); */
+#endif /* CONFIG_DRIVER_LAN91C96 */
+
 	/* Initialize from environment */
 	if ((s = getenv ("loadaddr")) != NULL) {
 		load_addr = simple_strtoul (s, NULL, 16);

lib_ppc/board.c

@@ -50,8 +50,10 @@
 #include <cmd_bedbug.h>
 #endif
 #ifdef CFG_ALLOC_DPRAM
+#if !defined(CONFIG_8260)
 #include <commproc.h>
 #endif
+#endif
 #include <version.h>
 #if defined(CONFIG_BAB7xx)
 #include <w83c553f.h>
@@ -277,8 +279,10 @@ init_fnc_t *init_sequence[] = {
 	get_clocks,		/* get CPU and bus clocks (etc.) */
 	init_timebase,
 #ifdef CFG_ALLOC_DPRAM
+#if !defined(CONFIG_8260)
 	dpram_init,
 #endif
+#endif
 #if defined(CONFIG_BOARD_POSTCLK_INIT)
 	board_postclk_init,
 #endif
@@ -307,6 +311,9 @@ init_fnc_t *init_sequence[] = {
 #endif
 #if defined(CONFIG_DTT)		/* Digital Thermometers and Thermostats */
 	dtt_init,
+#endif
+#ifdef CONFIG_POST
+	post_init_f,
 #endif
 	INIT_FUNC_WATCHDOG_RESET
 	init_func_ram,
@@ -976,6 +983,13 @@ void board_init_r (gd_t *id, ulong dest_addr)
 	}
 #endif
 
+#ifdef CONFIG_MODEM_SUPPORT
+ {
+	 extern int do_mdm_init;
+	 do_mdm_init = gd->do_mdm_init;
+ }
+#endif
+
 	/* Initialization complete - start the monitor */
 
 	/* main_loop() can return to retry autoboot, if so just run it again. */
@@ -993,6 +1007,104 @@ void hang (void)
 	for (;;);
 }
 
+#ifdef CONFIG_MODEM_SUPPORT
+/* called from main loop (common/main.c) */
+extern void  dbg(const char *fmt, ...);
+int mdm_init (void)
+{
+	char env_str[16];
+	char *init_str;
+	int i;
+	extern char console_buffer[];
+	static inline void mdm_readline(char *buf, int bufsiz);
+	extern void enable_putc(void);
+	extern int hwflow_onoff(int);
+
+	enable_putc(); /* enable serial_putc() */
+
+#ifdef CONFIG_HWFLOW
+	init_str = getenv("mdm_flow_control");
+	if (init_str && (strcmp(init_str, "rts/cts") == 0))
+		hwflow_onoff (1);
+	else
+		hwflow_onoff(-1);
+#endif
+
+	for (i = 1;;i++) {
+		sprintf(env_str, "mdm_init%d", i);
+		if ((init_str = getenv(env_str)) != NULL) {
+			serial_puts(init_str);
+			serial_puts("\n");
+			for(;;) {
+				mdm_readline(console_buffer, CFG_CBSIZE);
+				dbg("ini%d: [%s]", i, console_buffer);
+
+				if ((strcmp(console_buffer, "OK") == 0) ||
+					(strcmp(console_buffer, "ERROR") == 0)) {
+					dbg("ini%d: cmd done", i);
+					break;
+				} else /* in case we are originating call ... */
+					if (strncmp(console_buffer, "CONNECT", 7) == 0) {
+						dbg("ini%d: connect", i);
+						return 0;
+					}
+			}
+		} else
+			break; /* no init string - stop modem init */
+
+		udelay(100000);
+	}
+
+	udelay(100000);
+
+	/* final stage - wait for connect */
+	for(;i > 1;) { /* if 'i' > 1 - wait for connection
+				  message from modem */
+		mdm_readline(console_buffer, CFG_CBSIZE);
+		dbg("ini_f: [%s]", console_buffer);
+		if (strncmp(console_buffer, "CONNECT", 7) == 0) {
+			dbg("ini_f: connected");
+			return 0;
+		}
+	}
+
+	return 0;
+}
+
+/* 'inline' - We have to do it fast */
+static inline void mdm_readline(char *buf, int bufsiz)
+{
+	char c;
+	char *p;
+	int n;
+
+	n = 0;
+	p = buf;
+	for(;;) {
+		c = serial_getc();
+
+		/*		dbg("(%c)", c); */
+
+		switch(c) {
+		case '\r':
+			break;
+		case '\n':
+			*p = '\0';
+			return;
+
+		default:
+			if(n++ > bufsiz) {
+				*p = '\0';
+				return; /* sanity check */
+			}
+			*p = c;
+			p++;
+			break;
+		}
+	}
+}
+#endif
+
 #if 0 /* We could use plain global data, but the resulting code is bigger */
 /*
  * Pointer to initial global data area

post/Makefile

@@ -27,7 +27,7 @@ SUBDIRS = cpu
 LIB	= libpost.a
 
 AOBJS	= cache_8xx.o
-COBJS	= post.o tests.o cpu.o rtc.o watchdog.o memory.o i2c.o cache.o
+COBJS	= post.o tests.o cpu.o rtc.o watchdog.o memory.o i2c.o cache.o sysmon.o
 COBJS	+= uart.o ether.o usb.o spr.o
 
 include $(TOPDIR)/post/rules.mk

post/post.c

@@ -36,6 +36,30 @@
 
 #define BOOTMODE_MAGIC	0xDEAD0000
 
+int post_init_f (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	int res = 0;
+	unsigned int i;
+
+	for (i = 0; i < post_list_size; i++) {
+		struct post_test *test = post_list + i;
+
+		if (test->init_f && test->init_f()) {
+			res = -1;
+		}
+	}
+	
+	gd->post_init_f_time = post_time_ms(0);
+	if (!gd->post_init_f_time)
+	{
+		printf("post/post.c: post_time_ms seems not to be implemented\n");
+	}
+
+	return res;
+}
+
 void post_bootmode_init (void)
 {
 	DECLARE_GLOBAL_DATA_PTR;
@@ -365,7 +389,35 @@ void post_reloc (void)
 			addr = (ulong) (test->test) + gd->reloc_off;
 			test->test = (int (*)(int flags)) addr;
 		}
+
+		if (test->init_f) {
+			addr = (ulong) (test->init_f) + gd->reloc_off;
+			test->init_f = (int (*)(void)) addr;
+		}
+
+		if (test->reloc) {
+			addr = (ulong) (test->reloc) + gd->reloc_off;
+			test->reloc = (void (*)(void)) addr;
+			
+			test->reloc();
+		}
 	}
 }
 
+
+/*
+ * Some tests (e.g. SYSMON) need the time when post_init_f started,
+ * but we cannot use get_timer() at this point.
+ *
+ * On PowerPC we implement it using the timebase register.
+ */
+unsigned long post_time_ms (unsigned long base)
+{
+#ifdef CONFIG_PPC
+	return (unsigned long)get_ticks () / (get_tbclk () / CFG_HZ) - base;
+#else
+	return 0; /* Not implemented yet */
+#endif
+}
+
 #endif /* CONFIG_POST */

post/sysmon.c

@@ -0,0 +1,330 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <post.h>
+#include <common.h>
+
+#ifdef CONFIG_POST
+
+/*
+ * SYSMON test
+ *
+ * This test performs the system hardware monitoring.
+ * The test passes when all the following voltages and temperatures
+ * are within allowed ranges:
+ * 
+ * Board temperature
+ * Front temperature
+ * +3.3V CPU logic
+ * +5V logic
+ * +12V PCMCIA
+ * +12V CCFL
+ * +5V standby
+ * 
+ * CCFL is not enabled if temperature values are not within allowed ranges
+ *
+ * See the list off all parameters in the sysmon_table below
+ */
+
+#include <post.h>
+#include <watchdog.h>
+#include <i2c.h>
+
+#if CONFIG_POST & CFG_POST_SYSMON
+
+static int sysmon_temp_invalid = 0;
+
+/* #define DEBUG */
+
+#define	RELOC(x) if (x != NULL) x = (void *) ((ulong) (x) + gd->reloc_off)
+
+typedef struct sysmon_s sysmon_t;
+typedef struct sysmon_table_s sysmon_table_t;
+
+static void sysmon_lm87_init (sysmon_t * this);
+static void sysmon_pic_init (sysmon_t * this);
+static uint sysmon_i2c_read (sysmon_t * this, uint addr);
+static uint sysmon_i2c_read_sgn (sysmon_t * this, uint addr);
+static void sysmon_ccfl_disable (sysmon_table_t * this);
+static void sysmon_ccfl_enable (sysmon_table_t * this);
+
+struct sysmon_s
+{
+	uchar	chip;
+	void	(*init)(sysmon_t *);
+	uint	(*read)(sysmon_t *, uint);
+};
+
+static sysmon_t sysmon_lm87 =
+	{CFG_I2C_SYSMON_ADDR, sysmon_lm87_init, sysmon_i2c_read};
+static sysmon_t sysmon_lm87_sgn =
+	{CFG_I2C_SYSMON_ADDR, sysmon_lm87_init, sysmon_i2c_read_sgn};
+static sysmon_t sysmon_pic =
+	{CFG_I2C_PICIO_ADDR, sysmon_pic_init, sysmon_i2c_read};
+
+static sysmon_t * sysmon_list[] =
+{
+	&sysmon_lm87,
+	&sysmon_lm87_sgn,
+	&sysmon_pic,
+	NULL
+};
+
+struct sysmon_table_s
+{
+	char *		name;
+	char *		unit_name;
+	sysmon_t *	sysmon;
+	void		(*exec_before)(sysmon_table_t *);
+	void		(*exec_after)(sysmon_table_t *);
+
+	int		unit_div;
+	int		unit_min;
+	int		unit_max;
+	uint		val_mask;
+	uint		val_min;
+	uint		val_max;
+	int		val_valid;
+	uint		addr;
+};
+
+static sysmon_table_t sysmon_table[] =
+{
+    {"Board temperature", " C", &sysmon_lm87_sgn, NULL, sysmon_ccfl_disable,
+     1, -128, 127, 0xFF, 0x58, 0xD5, 0, 0x27},
+
+    {"Front temperature", " C", &sysmon_lm87, NULL, sysmon_ccfl_disable,
+     100, -27316, 8984, 0xFF, 0xA4, 0xFC, 0, 0x29},
+
+    {"+3.3V CPU logic", "V", &sysmon_lm87, NULL, NULL,
+     1000, 0, 4386, 0xFF, 0xB6, 0xC9, 0, 0x22},
+
+    {"+5V logic", "V", &sysmon_lm87, NULL, NULL,
+     1000, 0, 6630, 0xFF, 0xB6, 0xCA, 0, 0x23},
+
+    {"+12V PCMCIA", "V", &sysmon_lm87, NULL, NULL,
+     1000, 0, 15460, 0xFF, 0xBC, 0xD0, 0, 0x21},
+
+    {"+12V CCFL", "V", &sysmon_lm87, NULL, sysmon_ccfl_enable,
+     1000, 0, 15900, 0xFF, 0xB6, 0xCA, 0, 0x24},
+
+    {"+5V standby", "V", &sysmon_pic, NULL, NULL,
+     1000, 0, 6040, 0xFF, 0xC8, 0xDE, 0, 0x7C},
+};
+static int sysmon_table_size = sizeof(sysmon_table) / sizeof(sysmon_table[0]);
+
+static int conversion_done = 0;
+
+
+int sysmon_init_f (void)
+{
+	sysmon_t ** l;
+	ulong reg;
+
+	/* Power on CCFL, PCMCIA */
+	reg = pic_read  (0x60);
+	reg |= 0x09;
+	pic_write (0x60, reg);
+
+	for (l = sysmon_list; *l; l++)
+	{
+		(*l)->init(*l);
+	}
+	
+	return 0;
+}
+
+void sysmon_reloc (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	sysmon_t ** l;
+	sysmon_table_t * t;
+
+	for (l = sysmon_list; *l; l++)
+	{
+		RELOC(*l);
+		RELOC((*l)->init);
+		RELOC((*l)->read);
+	}
+
+	for (t = sysmon_table; t < sysmon_table + sysmon_table_size; t ++)
+	{
+		RELOC(t->exec_before);
+		RELOC(t->exec_after);
+		RELOC(t->sysmon);
+	}
+}
+
+static char * sysmon_unit_value (sysmon_table_t * s, uint val)
+{
+	static char buf[32];
+	int unit_val =
+	    s->unit_min + (s->unit_max - s->unit_min) * val / s->val_mask;
+	char * p;
+	int dec, frac;
+
+	sprintf(buf, "%+d", unit_val / s->unit_div);
+	
+	frac = (unit_val > 0 ? unit_val : -unit_val) % s->unit_div;
+	p = buf + strlen(buf);
+	
+	dec = s->unit_div;
+	
+	if (dec != 1)
+	{
+		*p++ = '.';
+	}
+	
+	for (dec /= 10; dec != 0; dec /= 10)
+	{
+		*p++ = '0' + frac / dec % 10;
+	}
+	
+	strcpy(p, s->unit_name);
+	
+	return buf;
+}
+
+static void sysmon_lm87_init (sysmon_t * this)
+{
+	uchar val;
+
+	/* Detect LM87 chip */
+	if (i2c_read(this->chip, 0x40, 1, &val, 1) || (val & 0x80) != 0 ||
+	    i2c_read(this->chip, 0x3E, 1, &val, 1) || val != 0x02)
+	{
+		printf("Error: LM87 not found at 0x%02X\n", this->chip);
+		return;
+	}
+	
+	/* Configure pins 5,6 as AIN */
+	val = 0x03;
+	if (i2c_write(this->chip, 0x16, 1, &val, 1))
+	{
+		printf("Error: can't write LM87 config register\n");
+		return;
+	}
+
+	/* Start monitoring */
+	val = 0x01;
+	if (i2c_write(this->chip, 0x40, 1, &val, 1))
+	{
+		printf("Error: can't write LM87 config register\n");
+		return;
+	}
+}
+
+static void sysmon_pic_init (sysmon_t * this)
+{
+}
+
+static uint sysmon_i2c_read (sysmon_t * this, uint addr)
+{
+	uchar val;
+	uint res = i2c_read(this->chip, addr, 1, &val, 1);
+
+	return res == 0 ? val : -1;
+}
+
+static uint sysmon_i2c_read_sgn (sysmon_t * this, uint addr)
+{
+	uchar val;
+	return i2c_read(this->chip, addr, 1, &val, 1) == 0 ?
+		128 + (signed char)val : -1;
+}
+
+static void sysmon_ccfl_disable (sysmon_table_t * this)
+{
+	if (!this->val_valid)
+	{
+		sysmon_temp_invalid = 1;
+	}
+}
+
+static void sysmon_ccfl_enable (sysmon_table_t * this)
+{
+	ulong reg;
+
+	if (!sysmon_temp_invalid)
+	{
+		reg = pic_read  (0x60);
+		reg |= 0x02;
+		pic_write (0x60, reg);
+	}
+}
+
+int sysmon_post_test (int flags)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	int res = 0;
+	sysmon_table_t * t;
+	uint val;
+
+	/*
+	 * The A/D conversion on the LM87 sensor takes 300 ms.
+	 */
+	if (! conversion_done)
+	{
+		while (post_time_ms(gd->post_init_f_time) < 300) WATCHDOG_RESET ();
+		conversion_done = 1;
+	}
+
+	for (t = sysmon_table; t < sysmon_table + sysmon_table_size; t ++)
+	{
+		if (t->exec_before)
+		{
+			t->exec_before(t);
+		}
+
+		val = t->sysmon->read(t->sysmon, t->addr);
+		t->val_valid = val >= t->val_min && val <= t->val_max;
+
+		if (t->exec_after)
+		{
+			t->exec_after(t);
+		}
+
+#ifndef DEBUG
+		if (!t->val_valid)
+#endif
+		{
+			printf("%-17s = %-10s ", t->name, sysmon_unit_value(t, val));
+			printf("allowed range");
+			printf(" %-8s ..", sysmon_unit_value(t, t->val_min));
+			printf(" %-8s", sysmon_unit_value(t, t->val_max));
+			printf("     %s\n", t->val_valid ? "OK" : "FAIL");
+		}
+
+		if (!t->val_valid)
+		{
+			res = -1;
+		}
+	}
+
+	return res;
+}
+
+#endif /* CONFIG_POST & CFG_POST_SYSMON */
+#endif /* CONFIG_POST */

post/tests.c

@@ -42,6 +42,12 @@ extern int ether_post_test (int flags);
 extern int spi_post_test (int flags);
 extern int usb_post_test (int flags);
 extern int spr_post_test (int flags);
+extern int sysmon_post_test (int flags);
+
+extern int sysmon_init_f (void);
+
+extern void sysmon_reloc (void);
+
 
 struct post_test post_list[] =
 {
@@ -52,6 +58,8 @@ struct post_test post_list[] =
         "This test verifies the CPU cache operation.",
         POST_RAM | POST_ALWAYS,
         &cache_post_test,
+        NULL,
+        NULL,
 	CFG_POST_CACHE
     },
 #endif
@@ -62,6 +70,8 @@ struct post_test post_list[] =
         "This test checks the watchdog timer.",
         POST_RAM | POST_POWERON | POST_POWERFAIL | POST_MANUAL | POST_REBOOT,
         &watchdog_post_test,
+        NULL,
+        NULL,
 	CFG_POST_WATCHDOG
     },
 #endif
@@ -72,6 +82,8 @@ struct post_test post_list[] =
         "This test verifies the I2C operation.",
         POST_RAM | POST_ALWAYS,
         &i2c_post_test,
+        NULL,
+        NULL,
 	CFG_POST_I2C
     },
 #endif
@@ -82,6 +94,8 @@ struct post_test post_list[] =
         "This test verifies the RTC operation.",
         POST_RAM | POST_POWERFAIL | POST_MANUAL,
         &rtc_post_test,
+        NULL,
+        NULL,
 	CFG_POST_RTC
     },
 #endif
@@ -92,6 +106,8 @@ struct post_test post_list[] =
         "This test checks RAM.",
         POST_ROM | POST_POWERON | POST_POWERFAIL | POST_PREREL,
         &memory_post_test,
+        NULL,
+        NULL,
 	CFG_POST_MEMORY
     },
 #endif
@@ -103,6 +119,8 @@ struct post_test post_list[] =
         " CPU.",
         POST_RAM | POST_ALWAYS,
         &cpu_post_test,
+        NULL,
+        NULL,
 	CFG_POST_CPU
     },
 #endif
@@ -113,6 +131,8 @@ struct post_test post_list[] =
         "This test verifies the UART operation.",
         POST_RAM | POST_POWERFAIL | POST_MANUAL,
         &uart_post_test,
+        NULL,
+        NULL,
 	CFG_POST_UART
     },
 #endif
@@ -123,6 +143,8 @@ struct post_test post_list[] =
         "This test verifies the ETHERNET operation.",
         POST_RAM | POST_ALWAYS | POST_MANUAL,
         &ether_post_test,
+        NULL,
+        NULL,
 	CFG_POST_ETHER
     },
 #endif
@@ -133,6 +155,8 @@ struct post_test post_list[] =
         "This test verifies the SPI operation.",
         POST_RAM | POST_ALWAYS | POST_MANUAL,
         &spi_post_test,
+        NULL,
+        NULL,
 	CFG_POST_SPI
     },
 #endif
@@ -143,6 +167,8 @@ struct post_test post_list[] =
         "This test verifies the USB operation.",
         POST_RAM | POST_ALWAYS | POST_MANUAL,
         &usb_post_test,
+        NULL,
+        NULL,
 	CFG_POST_USB
     },
 #endif
@@ -153,9 +179,23 @@ struct post_test post_list[] =
         "This test checks SPR contents.",
         POST_ROM | POST_ALWAYS | POST_PREREL,
         &spr_post_test,
+        NULL,
+        NULL,
 	CFG_POST_SPR
     },
 #endif
+#if CONFIG_POST & CFG_POST_SYSMON
+    {
+        "SYSMON test",
+        "sysmon",
+        "This test monitors system hardware.",
+        POST_RAM | POST_ALWAYS,
+        &sysmon_post_test,
+        &sysmon_init_f,
+        &sysmon_reloc,
+	CFG_POST_SYSMON
+    },
+#endif
 };
 
 unsigned int post_list_size = sizeof (post_list) / sizeof (struct post_test);

post/uart.c

@@ -73,7 +73,9 @@ static struct {
 static char *ctlr_name[2] = { "SMC", "SCC" };
 
 static int used_by_uart[2] = { -1, -1 };
+#if defined(SCC_ENET)
 static int used_by_ether[2] = { -1, -1 };
+#endif
 
 static int proff_smc[] = { PROFF_SMC1, PROFF_SMC2 };
 static int proff_scc[] =

rtc/ds1307.c

@@ -25,7 +25,7 @@
 
 /*
  * Date & Time support (no alarms) for Dallas Semiconductor (now Maxim)
- * DS1307 Real Time Clock (RTC).
+ * DS1307 and DS1338 Real Time Clock (RTC).
  *
  * based on ds1337.c
  */
@@ -35,7 +35,8 @@
 #include <rtc.h>
 #include <i2c.h>
 
-#if defined(CONFIG_RTC_DS1307) && (CONFIG_COMMANDS & CFG_CMD_DATE)
+#if (defined(CONFIG_RTC_DS1307) || defined(CONFIG_RTC_DS1338) ) && \
+    (CONFIG_COMMANDS & CFG_CMD_DATE)
 
 /*---------------------------------------------------------------------*/
 #undef DEBUG_RTC
@@ -200,4 +201,4 @@ static unsigned char bin2bcd (unsigned int n)
 	return (((n / 10) << 4) | (n % 10));
 }
 
-#endif /* CONFIG_RTC_DS1307 && (CFG_COMMANDS & CFG_CMD_DATE) */
+#endif /* (CONFIG_RTC_DS1307 || CONFIG_RTC_DS1338) && (CFG_COMMANDS & CFG_CMD_DATE) */

tools/env/fw_env.h

@@ -27,7 +27,7 @@
  * See included "fw_env.config" sample file (TRAB board)
  * for notes on configuration.
  */
-/*#define CONFIG_FILE     "/etc/fw_env.config" */
+#define CONFIG_FILE     "/etc/fw_env.config"
 
 #define HAVE_REDUND /* For systems with 2 env sectors */
 #define DEVICE1_NAME      "/dev/mtd1"

tools/gdb/astest.c

@@ -81,7 +81,7 @@ main(int ac, char **av)
 	close(ifd);
 	Error("bfd_fdopenr of file '%s' failed", ifn);
     }
-    bfdp->cacheable = true;
+    bfdp->cacheable = 1;
 
     if (!bfd_check_format(bfdp, bfd_object) ||
       (bfd_get_file_flags(bfdp) & EXEC_P) == 0) {