* Fix PCI problems on PPChameleonEVB

* TRAB auto-update: image type patch by Martin Krause, 17 Oct 2003

CHANGELOG

@@ -2,6 +2,14 @@
 Changes for U-Boot 1.0.0:
 ======================================================================
 
+* Add CompactFlash support for NSCU
+
+* Fix PCI problems on PPChameleonEVB
+
+* TRAB auto-update: Base decision if we have to strip the image
+  header on image type as encoded in the header
+  (include image type patch by Martin Krause, 17 Oct 2003)
+
 * Patches by Xianghua Xiao, 15 Oct 2003:
 
   - Added Motorola CPU 8540/8560 support (cpu/85xx)

README

@@ -2325,8 +2325,8 @@ defines the following image properties:
   LynxOS, pSOS, QNX, RTEMS, ARTOS;
   Currently supported: Linux, NetBSD, VxWorks, QNX, RTEMS, ARTOS, LynxOS).
 * Target CPU Architecture (Provisions for Alpha, ARM, Intel x86,
-  IA64, MIPS, MIPS, PowerPC, IBM S390, SuperH, Sparc, Sparc 64 Bit;
-  Currently supported: PowerPC).
+  IA64, MIPS, NIOS, PowerPC, IBM S390, SuperH, Sparc, Sparc 64 Bit;
+  Currently supported: ARM, Intel x86, MIPS, NIOS, PowerPC).
 * Compression Type (uncompressed, gzip, bzip2)
 * Load Address
 * Entry Point

board/trab/auto_update.c

@@ -260,7 +260,8 @@ au_check_valid(int idx, long nbytes)
 		printf ("Image %s wrong type\n", aufile[idx]);
 		return -1;
 	}
-	if ((idx == IDX_APP) && (hdr->ih_type != IH_TYPE_RAMDISK)) {
+	if ((idx == IDX_APP) && (hdr->ih_type != IH_TYPE_RAMDISK) 
+            && (hdr->ih_type != IH_TYPE_FILESYSTEM)) {
 		printf ("Image %s wrong type\n", aufile[idx]);
 		return -1;
 	}
@@ -352,8 +353,12 @@ au_do_update(int idx, long sz)
 	debug ("flash_sect_erase(%lx, %lx);\n", start, end);
 	flash_sect_erase(start, end);
 	wait_ms(100);
-	/* strip the header - except for the kernel and app */
-	if (idx == IDX_FIRMWARE || idx == IDX_DISK) {
+	/* strip the header - except for the kernel and ramdisk */
+	if (hdr->ih_type == IH_TYPE_KERNEL || hdr->ih_type == IH_TYPE_RAMDISK) {
+		addr = (char *)hdr;
+		off = sizeof(*hdr);
+		nbytes = sizeof(*hdr) + ntohl(hdr->ih_size);
+	} else {
 		addr = (char *)((char *)hdr + sizeof(*hdr));
 #ifdef AU_UPDATE_TEST
 		/* copy it to where Linux goes */
@@ -362,10 +367,6 @@ au_do_update(int idx, long sz)
 #endif
 		off = 0;
 		nbytes = ntohl(hdr->ih_size);
-	} else {
-		addr = (char *)hdr;
-		off = sizeof(*hdr);
-		nbytes = sizeof(*hdr) + ntohl(hdr->ih_size);
 	}
 
 	/* copy the data from RAM to FLASH */

common/cmd_pcmcia.c

@@ -160,7 +160,7 @@ int pcmcia_on (void)
 }
 #else
 
-#if defined(CONFIG_LWMON)
+#if defined(CONFIG_LWMON) || defined(CONFIG_NSCU)
 # define  CFG_PCMCIA_TIMING	(PCMCIA_SHT(9) | PCMCIA_SST(3) | PCMCIA_SL(12))
 #else
 # define  CFG_PCMCIA_TIMING	(PCMCIA_SHT(2) | PCMCIA_SST(4) | PCMCIA_SL(9))
@@ -594,8 +594,8 @@ static int hardware_enable(int slot)
 	sysp->sc_siumcr &= ~SIUMCR_DBGC11;	/* set DBGC to 00 */
 
 	/* clear interrupt state, and disable interrupts */
-	pcmp->pcmc_pscr =  PCMCIA_MASK(_slot_);
-	pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_);
+	pcmp->pcmc_pscr =  PCMCIA_MASK(slot);
+	pcmp->pcmc_per &= ~PCMCIA_MASK(slot);
 
 	/*
 	 * Disable interrupts, DMA, and PCMCIA buffers
@@ -604,10 +604,13 @@ static int hardware_enable(int slot)
 	debug ("Disable PCMCIA buffers and assert RESET\n");
 	reg  = 0;
 	reg |= __MY_PCMCIA_GCRX_CXRESET;	/* active high */
+#ifndef NSCU_OE_INV
 	reg |= __MY_PCMCIA_GCRX_CXOE;		/* active low  */
-	PCMCIA_PGCRX(_slot_) = reg;
+#endif
+	PCMCIA_PGCRX(slot) = reg;
 	udelay(500);
 
+#ifndef CONFIG_NSCU
 	/*
 	 * Configure Port C pins for
 	 * 5 Volts Enable and 3 Volts enable
@@ -617,6 +620,7 @@ static int hardware_enable(int slot)
 	/* remove all power */
 
 	immap->im_ioport.iop_pcdat &= ~(0x0002 | 0x0004);
+#endif
 
 	/*
 	 * Make sure there is a card in the slot, then configure the interface.
@@ -639,6 +643,7 @@ static int hardware_enable(int slot)
 		reg,
 		(reg&PCMCIA_VS1(slot))?"n":"ff",
 		(reg&PCMCIA_VS2(slot))?"n":"ff");
+#ifndef CONFIG_NSCU
 	if ((reg & mask) == mask) {
 		immap->im_ioport.iop_pcdat |= 0x0004;
 		puts (" 5.0V card found: ");
@@ -647,6 +652,13 @@ static int hardware_enable(int slot)
 		puts (" 3.3V card found: ");
 	}
 	immap->im_ioport.iop_pcdir |= (0x0002 | 0x0004);
+#else
+	if ((reg & mask) == mask) {
+		puts (" 5.0V card found: ");
+	} else {
+		puts (" 3.3V card found: ");
+	}
+#endif
 #if 0
 	/*  VCC switch error flag, PCMCIA slot INPACK_ pin */
 	cp->cp_pbdir &= ~(0x0020 | 0x0010);
@@ -655,10 +667,14 @@ static int hardware_enable(int slot)
 #endif
 	udelay(1000);
 	debug ("Enable PCMCIA buffers and stop RESET\n");
-	reg  =  PCMCIA_PGCRX(_slot_);
+	reg  =  PCMCIA_PGCRX(slot);
 	reg &= ~__MY_PCMCIA_GCRX_CXRESET;	/* active high */
+#ifndef NSCU_OE_INV
 	reg &= ~__MY_PCMCIA_GCRX_CXOE;		/* active low  */
-	PCMCIA_PGCRX(_slot_) = reg;
+#else
+	reg |= __MY_PCMCIA_GCRX_CXOE;		/* active low  */
+#endif
+	PCMCIA_PGCRX(slot) = reg;
 
 	udelay(250000);	/* some cards need >150 ms to come up :-( */
 
@@ -680,14 +696,18 @@ static int hardware_disable(int slot)
 	immap = (immap_t *)CFG_IMMR;
 	pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
 
+#ifndef CONFIG_NSCU
 	/* remove all power */
 	immap->im_ioport.iop_pcdat &= ~(0x0002 | 0x0004);
+#endif
 
 	debug ("Disable PCMCIA buffers and assert RESET\n");
 	reg  = 0;
 	reg |= __MY_PCMCIA_GCRX_CXRESET;	/* active high */
+#ifndef NSCU_OE_INV
 	reg |= __MY_PCMCIA_GCRX_CXOE;		/* active low  */
-	PCMCIA_PGCRX(_slot_) = reg;
+#endif
+	PCMCIA_PGCRX(slot) = reg;
 
 	udelay(10000);
 
@@ -695,7 +715,12 @@ static int hardware_disable(int slot)
 }
 #endif	/* CFG_CMD_PCMCIA */
 
-
+#ifdef CONFIG_NSCU
+static int voltage_set(int slot, int vcc, int vpp)
+{
+	return 0;
+}
+#else
 static int voltage_set(int slot, int vcc, int vpp)
 {
 	volatile immap_t	*immap;
@@ -714,10 +739,14 @@ static int voltage_set(int slot, int vcc, int vpp)
 	 * and assert RESET signal
 	 */
 	debug ("Disable PCMCIA buffers and assert RESET\n");
-	reg  = PCMCIA_PGCRX(_slot_);
+	reg  = PCMCIA_PGCRX(slot);
 	reg |= __MY_PCMCIA_GCRX_CXRESET;	/* active high */
+#ifndef NSCU_OE_INV
 	reg |= __MY_PCMCIA_GCRX_CXOE;		/* active low  */
-	PCMCIA_PGCRX(_slot_) = reg;
+#else
+	reg &= ~__MY_PCMCIA_GCRX_CXOE;		/* active low  */
+#endif
+	PCMCIA_PGCRX(slot) = reg;
 	udelay(500);
 
 	/*
@@ -755,16 +784,21 @@ static int voltage_set(int slot, int vcc, int vpp)
 
 done:
 	debug ("Enable PCMCIA buffers and stop RESET\n");
-	reg  =  PCMCIA_PGCRX(_slot_);
+	reg  =  PCMCIA_PGCRX(slot);
 	reg &= ~__MY_PCMCIA_GCRX_CXRESET;	/* active high */
+#ifndef NSCU_OE_INV
 	reg &= ~__MY_PCMCIA_GCRX_CXOE;		/* active low  */
-	PCMCIA_PGCRX(_slot_) = reg;
+#else
+	reg |= __MY_PCMCIA_GCRX_CXOE;		/* active low  */
+#endif
+	PCMCIA_PGCRX(slot) = reg;
 	udelay(500);
 
 	debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n",
 		slot+'A');
 	return (0);
 }
+#endif
 
 #endif	/* TQM8xxL */
 

include/configs/NSCU.h

@@ -35,6 +35,7 @@
 
 #define CONFIG_MPC855		1	/* This is a MPC855 CPU		*/
 #define CONFIG_TQM855M		1	/* ...on a TQM8xxM module	*/
+#define CONFIG_NSCU		1
 
 #define	CONFIG_8xx_CONS_SCC1	1	/* Console is on SMC1		*/
 
@@ -285,6 +286,9 @@
  *-----------------------------------------------------------------------
  *
  */
+/* NSCU use both slots, SLOT_A as "primary". */
+#define	CONFIG_PCMCIA_SLOT_A 1
+
 #define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
 #define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
 #define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
@@ -293,6 +297,9 @@
 #define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
 #define CFG_PCMCIA_IO_ADDR	(0xEC000000)
 #define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+#define PCMCIA_MEM_WIN_NO 	8 /* override default 4 in pcmcia.h */
+#define	PCMCIA_SOCKETS_NO 	2 /* we have two sockets */
+#define NSCU_OE_INV		1 /* PCMCIA_GCRX_CXOE is inverted on early boards */
 
 /*-----------------------------------------------------------------------
  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
@@ -305,10 +312,11 @@
 #undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
 #undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
 
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+#define CFG_IDE_MAXBUS		2	/* max. 2 IDE buses		*/
+#define CFG_IDE_MAXDEVICE	4	/* max. 2 drives per IDE bus	*/
 
 #define CFG_ATA_IDE0_OFFSET	0x0000
+#define CFG_ATA_IDE1_OFFSET	(4 * CFG_PCMCIA_MEM_SIZE) /* starts @ 4th window */
 
 #define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
 

include/configs/PPChameleonEVB.h

@@ -282,7 +282,7 @@
 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 
 #define CONFIG_PCI			/* include pci support	        */
-#define CONFIG_PCI_HOST	PCI_HOST_HOST   /* select pci host function     */
+#define CONFIG_PCI_HOST	PCI_HOST_AUTO   /* select pci host function     */
 #undef  CONFIG_PCI_PNP			/* do pci plug-and-play         */
 					/* resource configuration       */