Add Auto-MDIX support for INCA-IP

Last minute fixes / cleanup.
Fix typo.
2026-06-12 22:49:43 +03:00 · 2004-02-20 22:02:48 +00:00 · 2004-02-12 15:11:57 +00:00 · 2004-02-12 14:09:38 +00:00 · 2004-02-12 00:47:09 +00:00 · 2004-02-11 21:35:18 +00:00
209 changed files with 17442 additions and 6376 deletions
--- a/105
+++ b/105
@@ -1,7 +1,110 @@
 ======================================================================
-Changes since U-Boot 1.0.1:
+Changes for U-Boot 1.0.2:
 ======================================================================

+* Add Auto-MDIX support for INCA-IP
+
+* Some code cleanup
+
+* Patch by Josef Baumgartner, 10 Feb 2004:
+  Fixes for Coldfire port
+
+* Patch by Brad Kemp, 11 Feb 2004:
+  Fix CFI flash driver problems
+
+* Make sure to use a bus clock divider of 2 only when running TQM8xxM
+  modules at CPU clock frequencies above 66 MHz.
+
+* Optimize flash programming speed for LWMON (by another 100% :-)
+
+* Patch by Jian Zhang, 3 Feb 2004:
+  - Changed the incorrect FAT12BUFSIZE
+  - data_begin in fsdata can be negative. Changed it to be short.
+
+* Patches by Stephan Linz, 30 Jan 2004:
+  1: - board/altera/common/flash.c:flash_erase():
+       o allow interrupts befor get_timer() call
+       o check-up each erased sector and avoid unexpected timeouts
+     - board/altera/dk1c20/dk1s10.c:board_early_init_f():
+       o enclose sevenseg_set() in cpp condition
+     - remove the ASMI configuration for DK1S10_standard_32 (never present)
+     - fix some typed in mistakes in the NIOS documentation
+  2: - split DK1C20 configuration into several header files:
+       o two new files for each NIOS CPU description
+       o U-Boot related part is remaining in DK1C20.h
+  3: - split DK1S10 configuration into several header files:
+       o two new files for each NIOS CPU description
+       o U-Boot related part is remaining in DK1S10.h
+  4: - Add support for the Microtronix Linux Development Kit
+       NIOS CPU configuration at the Altera Nios Development Kit,
+       Stratix Edition (DK-1S10)
+  5: - Add documentation for the Altera Nios Development Kit,
+       Stratix Edition (DK-1S10)
+  6: - Add support for the Nios Serial Peripharel Interface (SPI)
+       (master only)
+  7: - Add support for the common U-Boot SPI framework at
+       RTC driver DS1306
+
+* Patch by Rahul Shanbhag, 28 Jan 2004:
+  Fix flash protection/locking handling for OMAP1610 innovator board.
+
+* Patch by Rolf Peukert, 28 Jan 2004:
+  fix flash write problems on CSB226 board (write with 32 bit bus width)
+
+* Patches by Mark Jonas, 16 Jan 2004:
+  - fix rounding error when calculating baudrates for MPC5200 PSCs
+  - make sure CFG_RAMBOOT and CFG_LOWBOOT are not enabled at the same
+    time which is not supported
+
+* Patch by Yuli Barcohen, 26 Jan 2004:
+  Allow bzip2 compression for small memory footprint boards
+
+* Patch by Brad Kemp, 21 Jan 2004:
+  Add support for CFI flash driver for both the Intel and the AMD
+  command sets.
+
+* Patch by Travis Sawyer, 20 Jan 2004:
+  Fix pci bridge auto enumeration of sibling p2p bridges.
+
+* Patch by Tolunay Orkun, 12 Jan 2004:
+  Add some delays as needed for Intel LXT971A PHY support
+
+* Patches by Stephan Linz, 09 Jan 2004:
+  - avoid warning: unused variable `piop' in board/altera/common/sevenseg.c
+  - make DK1C20 board configuration related to ASMI conform to
+    documentation
+
+* Patch by Anders Larsen, 09 Jan 2004:
+
+  ARM memory layout fixes: the abort-stack is now set up in the
+  correct RAM area, and the BSS is zeroed out as it should be.
+
+  Furthermore, the magic variables 'armboot_end' and 'armboot_end_data'
+  of the linker scripts are replaced by '__bss_start' and '_end',
+  resp., which is a further step to eliminate unnecessary differences
+  between the implementation of the CPU architectures.
+
+* Patch by liang a lei, 9 Jan 2004:
+  Fix Intel 28F128J3 ID in include/flash.h
+
+* Patch by Masami Komiya, 09 Jan 2004:
+  add support for TB0229 board (NEC VR4131 MIPS processor)
+
+* Patch by Leon Kukovec, 12 Dec 2003:
+  changed extern __inline__ into static __inline__ in
+  include/linux/byteorder/swab.h
+
+* Patch by Travis Sawyer, 30 Dec 2003:
+  Add support for IBM PPC440GX. Multiple EMAC Ethernet devices,
+  select MDI port based on enabled EMAC device.
+  Add support for XES Inc <http://www.xes-inc.com> XPedite1000 440GX
+  base PrPMC board.
+
+* Patch by Wolter Kamphuis, 15 Dec 2003:
+  made CONFIG_SILENT_CONSOLE usable on all architectures
+
+* Disable date command on TQM866M - there is no RTC on MPC866
+
 * Fix variable CPU clock for MPC859/866 systems for low CPU clocks

 * Implement adaptive SDRAM timing configuration based on actual CPU
--- a/4
+++ b/4
@@ -276,6 +276,10 @@ N: Neil Russell
 E: caret@c-side.com
 D: Author of LiMon-1.4.2, which contributed some ideas

+N: Travis B. Sawyer
+E: travis.sawyer@sandburst.com
+D: Support for IBM PPC440GX, XES XPedite1000 440GX PrPMC board.
+
 N: Paolo Scaffardi
 E: arsenio@tin.it
 D: FADS823 configuration, MPC823 video support, I2C, wireless keyboard, lots more
--- a/3
+++ b/3
@@ -64,6 +64,7 @@ LIST_4xx="	\
 	ML2		OCRTC		ORSG		PCI405		\
 	PIP405		PLU405          PMC405          PPChameleonEVB	\
 	VOH405          W7OLMC		W7OLMG          WALNUT405	\
+	XPEDITE1K							\
 "

 #########################################################################
@@ -176,7 +177,7 @@ LIST_x86="${LIST_I486}"

 LIST_nios="	\
 	DK1C20 DK1C20_standard_32					\
-	DK1S10 DK1S10_standard_32					\
+	DK1S10 DK1S10_standard_32 DK1S10_mtx_ldk_20			\
 "

 #-----------------------------------------------------------------------
--- a/15
+++ b/15
@@ -635,6 +635,9 @@ W7OLMG_config: unconfig
 WALNUT405_config:unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx walnut405

+XPEDITE1K_config:unconfig
+	@./mkconfig $(@:_config=) ppc ppc4xx xpedite1k
+
 #########################################################################
 ## MPC824x Systems
 #########################################################################
@@ -830,10 +833,10 @@ ZPC1900_config: unconfig
 #########################################################################

 M5272C3_config :		unconfig
-	@./mkconfig $(@:_config=) m68k coldfire m5272c3
+	@./mkconfig $(@:_config=) m68k mcf52x2 m5272c3

 M5282EVB_config :		unconfig
-	@./mkconfig $(@:_config=) m68k coldfire m5282evb
+	@./mkconfig $(@:_config=) m68k mcf52x2 m5282evb

 #########################################################################
 ## MPC85xx Systems
@@ -1024,6 +1027,9 @@ incaip_config: unconfig
 		}
 	@./mkconfig -a $(call xtract_incaip,$@) mips mips incaip

+tb0229_config: unconfig
+	@./mkconfig $(@:_config=) mips mips tb0229
+
 #########################################################################
 ## MIPS64 5Kc
 #########################################################################
@@ -1058,6 +1064,7 @@ DK1C20_config:	unconfig

 DK1S10_safe_32_config		\
 DK1S10_standard_32_config	\
+DK1S10_mtx_ldk_20_config	\
 DK1S10_config:	unconfig
 	@ >include/config.h
 	@[ -z "$(findstring _safe_32,$@)" ] || \
@@ -1068,6 +1075,10 @@ DK1S10_config:	unconfig
 		{ echo "#define CONFIG_NIOS_STANDARD_32 1" >>include/config.h ; \
 		  echo "... NIOS 'standard_32' configuration" ; \
 		}
+	@[ -z "$(findstring _mtx_ldk_20,$@)" ] || \
+		{ echo "#define CONFIG_NIOS_MTX_LDK_20 1" >>include/config.h ; \
+		  echo "... NIOS 'mtx_ldk_20' configuration" ; \
+		}
 	@[ -z "$(findstring DK1S10_config,$@)" ] || \
 		{ echo "#define CONFIG_NIOS_STANDARD_32 1" >>include/config.h ; \
 		  echo "... NIOS 'standard_32' configuration (DEFAULT)" ; \
--- a/222
+++ b/222
@@ -141,7 +141,7 @@ Directory Hierarchy:

 - cpu/74xx_7xx	Files specific to Motorola MPC74xx and 7xx CPUs
 - cpu/arm925t	Files specific to ARM	   925	   CPUs
- cpu/arm926ejs	Files specific to ARM	926	CPUs
+- cpu/arm926ejs Files specific to ARM	926	CPUs
 - cpu/mpc5xx	Files specific to Motorola MPC5xx  CPUs
 - cpu/mpc8xx	Files specific to Motorola MPC8xx  CPUs
 - cpu/mpc824x	Files specific to Motorola MPC824x CPUs
@@ -150,22 +150,22 @@ Directory Hierarchy:
 - cpu/ppc4xx	Files specific to IBM	   4xx	   CPUs


- board/LEOX/   Files specific to boards manufactured by The LEOX team
+- board/LEOX/	Files specific to boards manufactured by The LEOX team
 - board/LEOX/elpt860	Files specific to ELPT860 boards
 - board/RPXClassic
 		Files specific to RPXClassic boards
- board/RPXlite	Files specific to RPXlite    boards
+- board/RPXlite Files specific to RPXlite    boards
 - board/at91rm9200dk Files specific to AT91RM9200DK boards
 - board/c2mon	Files specific to c2mon	     boards
- board/cmi	Files specific to cmi        boards
+- board/cmi	Files specific to cmi	     boards
 - board/cogent	Files specific to Cogent     boards
 		(need further configuration)
 		Files specific to CPCIISER4  boards
- board/cpu86	Files specific to CPU86      boards
+- board/cpu86	Files specific to CPU86	     boards
 - board/cray/	Files specific to boards manufactured by Cray
- board/cray/L1		Files specific to L1         boards
+- board/cray/L1		Files specific to L1	     boards
 - board/cu824	Files specific to CU824	     boards
- board/ebony   Files specific to IBM Ebony board
+- board/ebony	Files specific to IBM Ebony board
 - board/eric	Files specific to ERIC	     boards
 - board/esd/	Files specific to boards manufactured by ESD
 - board/esd/adciop	Files specific to ADCIOP     boards
@@ -175,8 +175,8 @@ Directory Hierarchy:
 - board/esd/cpciiser4	Files specific to CPCIISER4  boards
 - board/esd/common	Common files for ESD boards
 - board/esd/dasa_sim	Files specific to DASA_SIM   boards
- board/esd/du405	Files specific to DU405      boards
- board/esd/ocrtc	Files specific to OCRTC      boards
+- board/esd/du405	Files specific to DU405	     boards
+- board/esd/ocrtc	Files specific to OCRTC	     boards
 - board/esd/pci405	Files specific to PCI405     boards
 - board/esteem192e
 		Files specific to ESTEEM192E boards
@@ -211,17 +211,17 @@ Directory Hierarchy:
 - board/mpl/common	Common files for MPL boards
 - board/mpl/pip405	Files specific to PIP405     boards
 - board/mpl/mip405	Files specific to MIP405     boards
- board/mpl/vcma9	Files specific to VCMA9      boards
- board/musenki	Files specific to MUSEKNI    boards
- board/mvs1	Files specific to MVS1       boards
- board/nx823   Files specific to NX823      boards
- board/oxc	Files specific to OXC        boards
+- board/mpl/vcma9	Files specific to VCMA9	     boards
+- board/musenki Files specific to MUSEKNI    boards
+- board/mvs1	Files specific to MVS1	     boards
+- board/nx823	Files specific to NX823	     boards
+- board/oxc	Files specific to OXC	     boards
 - board/omap1510inn
 		Files specific to OMAP 1510 Innovator boards
 - board/omap1610inn
 		Files specific to OMAP 1610 Innovator boards
- board/pcippc2	Files specific to PCIPPC2/PCIPPC6 boards
- board/pm826	Files specific to PM826      boards
+- board/pcippc2 Files specific to PCIPPC2/PCIPPC6 boards
+- board/pm826	Files specific to PM826	     boards
 - board/ppmc8260
 		Files specific to PPMC8260   boards
 - board/snmc/qs850	Files specific to QS850/823  boards
@@ -232,24 +232,24 @@ Directory Hierarchy:
 		Files specific to RSDproto   boards
 - board/sandpoint
 		Files specific to Sandpoint  boards
- board/sbc8260	Files specific to SBC8260    boards
+- board/sbc8260 Files specific to SBC8260    boards
 - board/sacsng	Files specific to SACSng     boards
 - board/siemens Files specific to boards manufactured by Siemens AG
 - board/siemens/CCM	Files specific to CCM	     boards
 - board/siemens/IAD210	Files specific to IAD210     boards
- board/siemens/SCM	Files specific to SCM        boards
+- board/siemens/SCM	Files specific to SCM	     boards
 - board/siemens/pcu_e	Files specific to PCU_E	     boards
 - board/sixnet	Files specific to SIXNET     boards
 - board/spd8xx	Files specific to SPD8xxTS   boards
 - board/tqm8260 Files specific to TQM8260    boards
 - board/tqm8xx	Files specific to TQM8xxL    boards
- board/w7o	Files specific to W7O        boards
+- board/w7o	Files specific to W7O	     boards
 - board/walnut405
 		Files specific to Walnut405  boards
- board/westel/	Files specific to boards manufactured by Westel Wireless
+- board/westel/ Files specific to boards manufactured by Westel Wireless
 - board/westel/amx860	Files specific to AMX860     boards
- board/utx8245	Files specific to UTX8245   boards
- board/zpc1900	Files specific to Zephyr Engineering ZPC.1900 board
+- board/utx8245 Files specific to UTX8245   boards
+- board/zpc1900 Files specific to Zephyr Engineering ZPC.1900 board

 Software Configuration:
 =======================
@@ -336,49 +336,49 @@ The following options need to be configured:
 		PowerPC based boards:
 		---------------------

-		CONFIG_ADCIOP,     CONFIG_ICU862      CONFIG_RPXsuper,
-		CONFIG_ADS860,     CONFIG_IP860,      CONFIG_SM850,
-		CONFIG_AMX860,     CONFIG_IPHASE4539, CONFIG_SPD823TS,
-		CONFIG_AR405,      CONFIG_IVML24,     CONFIG_SXNI855T,
-		CONFIG_BAB7xx,     CONFIG_IVML24_128, CONFIG_Sandpoint8240,
-		CONFIG_CANBT,      CONFIG_IVML24_256, CONFIG_Sandpoint8245,
-		CONFIG_CCM,        CONFIG_IVMS8,      CONFIG_TQM823L,
-		CONFIG_CPCI405,    CONFIG_IVMS8_128,  CONFIG_TQM850L,
+		CONFIG_ADCIOP,	   CONFIG_ICU862      CONFIG_RPXsuper,
+		CONFIG_ADS860,	   CONFIG_IP860,      CONFIG_SM850,
+		CONFIG_AMX860,	   CONFIG_IPHASE4539, CONFIG_SPD823TS,
+		CONFIG_AR405,	   CONFIG_IVML24,     CONFIG_SXNI855T,
+		CONFIG_BAB7xx,	   CONFIG_IVML24_128, CONFIG_Sandpoint8240,
+		CONFIG_CANBT,	   CONFIG_IVML24_256, CONFIG_Sandpoint8245,
+		CONFIG_CCM,	   CONFIG_IVMS8,      CONFIG_TQM823L,
+		CONFIG_CPCI405,	   CONFIG_IVMS8_128,  CONFIG_TQM850L,
 		CONFIG_CPCI4052,   CONFIG_IVMS8_256,  CONFIG_TQM855L,
 		CONFIG_CPCIISER4,  CONFIG_LANTEC,     CONFIG_TQM860L,
-		CONFIG_CPU86,      CONFIG_MBX,        CONFIG_TQM8260,
-		CONFIG_CRAYL1,     CONFIG_MBX860T,    CONFIG_TTTech,
-		CONFIG_CU824,      CONFIG_MHPC,       CONFIG_UTX8245,
+		CONFIG_CPU86,	   CONFIG_MBX,	      CONFIG_TQM8260,
+		CONFIG_CRAYL1,	   CONFIG_MBX860T,    CONFIG_TTTech,
+		CONFIG_CU824,	   CONFIG_MHPC,	      CONFIG_UTX8245,
 		CONFIG_DASA_SIM,   CONFIG_MIP405,     CONFIG_W7OLMC,
-		CONFIG_DU405,      CONFIG_MOUSSE,     CONFIG_W7OLMG,
-		CONFIG_ELPPC,      CONFIG_MPC8260ADS, CONFIG_WALNUT405,
-		CONFIG_ERIC,       CONFIG_MUSENKI,    CONFIG_ZUMA,
-		CONFIG_ESTEEM192E, CONFIG_MVS1,       CONFIG_c2mon,
-		CONFIG_ETX094,     CONFIG_NX823,      CONFIG_cogent_mpc8260,
+		CONFIG_DU405,	   CONFIG_MOUSSE,     CONFIG_W7OLMG,
+		CONFIG_ELPPC,	   CONFIG_MPC8260ADS, CONFIG_WALNUT405,
+		CONFIG_ERIC,	   CONFIG_MUSENKI,    CONFIG_ZUMA,
+		CONFIG_ESTEEM192E, CONFIG_MVS1,	      CONFIG_c2mon,
+		CONFIG_ETX094,	   CONFIG_NX823,      CONFIG_cogent_mpc8260,
 		CONFIG_EVB64260,   CONFIG_OCRTC,      CONFIG_cogent_mpc8xx,
-		CONFIG_FADS823,    CONFIG_ORSG,       CONFIG_ep8260,
-		CONFIG_FADS850SAR, CONFIG_OXC,        CONFIG_gw8260,
+		CONFIG_FADS823,	   CONFIG_ORSG,	      CONFIG_ep8260,
+		CONFIG_FADS850SAR, CONFIG_OXC,	      CONFIG_gw8260,
 		CONFIG_FADS860T,   CONFIG_PCI405,     CONFIG_hermes,
-		CONFIG_FLAGADM,    CONFIG_PCIPPC2,    CONFIG_hymod,
-		CONFIG_FPS850L,    CONFIG_PCIPPC6,    CONFIG_lwmon,
-		CONFIG_GEN860T,    CONFIG_PIP405,     CONFIG_pcu_e,
-		CONFIG_GENIETV,    CONFIG_PM826,      CONFIG_ppmc8260,
-		CONFIG_GTH,        CONFIG_RPXClassic, CONFIG_rsdproto,
-		CONFIG_IAD210,     CONFIG_RPXlite,    CONFIG_sbc8260,
-		CONFIG_EBONY,      CONFIG_sacsng,     CONFIG_FPS860L,
-		CONFIG_V37,        CONFIG_ELPT860,    CONFIG_CMI,
-		CONFIG_NETVIA,     CONFIG_RBC823,     CONFIG_ZPC1900,
+		CONFIG_FLAGADM,	   CONFIG_PCIPPC2,    CONFIG_hymod,
+		CONFIG_FPS850L,	   CONFIG_PCIPPC6,    CONFIG_lwmon,
+		CONFIG_GEN860T,	   CONFIG_PIP405,     CONFIG_pcu_e,
+		CONFIG_GENIETV,	   CONFIG_PM826,      CONFIG_ppmc8260,
+		CONFIG_GTH,	   CONFIG_RPXClassic, CONFIG_rsdproto,
+		CONFIG_IAD210,	   CONFIG_RPXlite,    CONFIG_sbc8260,
+		CONFIG_EBONY,	   CONFIG_sacsng,     CONFIG_FPS860L,
+		CONFIG_V37,	   CONFIG_ELPT860,    CONFIG_CMI,
+		CONFIG_NETVIA,	   CONFIG_RBC823,     CONFIG_ZPC1900,
 		CONFIG_MPC8540ADS, CONFIG_MPC8560ADS, CONFIG_QS850,
-		CONFIG_QS823,      CONFIG_QS860T,     CONFIG_DB64360,
+		CONFIG_QS823,	   CONFIG_QS860T,     CONFIG_DB64360,
 		CONFIG_DB64460,	   CONFIG_DUET_ADS

 		ARM based boards:
 		-----------------

 		CONFIG_HHP_CRADLE,  CONFIG_DNP1110,    CONFIG_EP7312,
-		CONFIG_IMPA7,       CONFIG_LART,       CONFIG_LUBBOCK,
+		CONFIG_IMPA7,	    CONFIG_LART,       CONFIG_LUBBOCK,
 		CONFIG_INNOVATOROMAP1510,	CONFIG_INNOVATOROMAP1610
-		CONFIG_SHANNON,     CONFIG_SMDK2400,   CONFIG_SMDK2410,
+		CONFIG_SHANNON,	    CONFIG_SMDK2400,   CONFIG_SMDK2410,
 		CONFIG_TRAB,	    CONFIG_VCMA9,      CONFIG_AT91RM9200DK


@@ -430,12 +430,12 @@ The following options need to be configured:

 		CFG_MEASURE_CPUCLK

-                Define this to measure the actual CPU clock instead
-                of relying on the correctness of the configured
-                values. Mostly useful for board bringup to make sure
-                the PLL is locked at the intended frequency. Note
-                that this requires a (stable) reference clock (32 kHz
-                RTC clock),
+		Define this to measure the actual CPU clock instead
+		of relying on the correctness of the configured
+		values. Mostly useful for board bringup to make sure
+		the PLL is locked at the intended frequency. Note
+		that this requires a (stable) reference clock (32 kHz
+		RTC clock),

 - Linux Kernel Interface:
 		CONFIG_CLOCKS_IN_MHZ
@@ -479,11 +479,11 @@ The following options need to be configured:
 						bit-blit (cf. smiLynxEM)
 			VIDEO_VISIBLE_COLS	visible pixel columns
 						(cols=pitch)
-			VIDEO_VISIBLE_ROWS      visible pixel rows
-			VIDEO_PIXEL_SIZE        bytes per pixel
+			VIDEO_VISIBLE_ROWS	visible pixel rows
+			VIDEO_PIXEL_SIZE	bytes per pixel
 			VIDEO_DATA_FORMAT	graphic data format
 						(0-5, cf. cfb_console.c)
-			VIDEO_FB_ADRS           framebuffer address
+			VIDEO_FB_ADRS		framebuffer address
 			VIDEO_KBD_INIT_FCT	keyboard int fct
 						(i.e. i8042_kbd_init())
 			VIDEO_TSTC_FCT		test char fct
@@ -619,15 +619,15 @@ The following options need to be configured:
 		CFG_CMD_AUTOSCRIPT Autoscript Support
 		CFG_CMD_BDI	  bdinfo
 		CFG_CMD_BEDBUG	  Include BedBug Debugger
-		CFG_CMD_BMP     * BMP support
+		CFG_CMD_BMP	* BMP support
 		CFG_CMD_BOOTD	  bootd
 		CFG_CMD_CACHE	  icache, dcache
 		CFG_CMD_CONSOLE	  coninfo
 		CFG_CMD_DATE	* support for RTC, date/time...
 		CFG_CMD_DHCP	  DHCP support
-		CFG_CMD_DIAG    * Diagnostics
-		CFG_CMD_DOC     * Disk-On-Chip Support
-		CFG_CMD_DTT       Digital Therm and Thermostat
+		CFG_CMD_DIAG	* Diagnostics
+		CFG_CMD_DOC	* Disk-On-Chip Support
+		CFG_CMD_DTT	  Digital Therm and Thermostat
 		CFG_CMD_ECHO	* echo arguments
 		CFG_CMD_EEPROM	* EEPROM read/write support
 		CFG_CMD_ELF	  bootelf, bootvx
@@ -637,37 +637,37 @@ The following options need to be configured:
 		CFG_CMD_FDOS	* Dos diskette Support
 		CFG_CMD_FLASH	  flinfo, erase, protect
 		CFG_CMD_FPGA	  FPGA device initialization support
-		CFG_CMD_HWFLOW  * RTS/CTS hw flow control
+		CFG_CMD_HWFLOW	* RTS/CTS hw flow control
 		CFG_CMD_I2C	* I2C serial bus support
 		CFG_CMD_IDE	* IDE harddisk support
 		CFG_CMD_IMI	  iminfo
-		CFG_CMD_IMLS      List all found images
+		CFG_CMD_IMLS	  List all found images
 		CFG_CMD_IMMAP	* IMMR dump support
 		CFG_CMD_IRQ	* irqinfo
-		CFG_CMD_JFFS2   * JFFS2 Support
+		CFG_CMD_JFFS2	* JFFS2 Support
 		CFG_CMD_KGDB	* kgdb
 		CFG_CMD_LOADB	  loadb
 		CFG_CMD_LOADS	  loads
 		CFG_CMD_MEMORY	  md, mm, nm, mw, cp, cmp, crc, base,
 				  loop, mtest
-		CFG_CMD_MISC      Misc functions like sleep etc
+		CFG_CMD_MISC	  Misc functions like sleep etc
 		CFG_CMD_MMC	  MMC memory mapped support
 		CFG_CMD_MII	  MII utility commands
-		CFG_CMD_NAND    * NAND support
+		CFG_CMD_NAND	* NAND support
 		CFG_CMD_NET	  bootp, tftpboot, rarpboot
 		CFG_CMD_PCI	* pciinfo
 		CFG_CMD_PCMCIA	* PCMCIA support
-		CFG_CMD_PING    * send ICMP ECHO_REQUEST to network host
-		CFG_CMD_PORTIO  * Port I/O
+		CFG_CMD_PING	* send ICMP ECHO_REQUEST to network host
+		CFG_CMD_PORTIO	* Port I/O
 		CFG_CMD_REGINFO * Register dump
 		CFG_CMD_RUN	  run command in env variable
-		CFG_CMD_SAVES     save S record dump
+		CFG_CMD_SAVES	  save S record dump
 		CFG_CMD_SCSI	* SCSI Support
-		CFG_CMD_SDRAM   * print SDRAM configuration information
+		CFG_CMD_SDRAM	* print SDRAM configuration information
 		CFG_CMD_SETGETDCR Support for DCR Register access (4xx only)
 		CFG_CMD_SPI	* SPI serial bus support
 		CFG_CMD_USB	* USB support
-		CFG_CMD_VFD     * VFD support (TRAB)
+		CFG_CMD_VFD	* VFD support (TRAB)
 		CFG_CMD_BSP	* Board SPecific functions
 		-----------------------------------------------
 		CFG_CMD_ALL	all
@@ -850,9 +850,9 @@ The following options need to be configured:
 		Following modes are supported  (* is default):

 			    800x600  1024x768  1280x1024
-	      256  (8bit)     303*      305       307
-	    65536 (16bit)     314       317       31a
-	16,7 Mill (24bit)     315       318       31b
+	      256  (8bit)     303*	305	  307
+	    65536 (16bit)     314	317	  31a
+	16,7 Mill (24bit)     315	318	  31b
 		(i.e. setenv videomode 317; saveenv; reset;)

 		CONFIG_VIDEO_SED13806
@@ -1031,7 +1031,7 @@ The following options need to be configured:
 		clock chips. See common/cmd_i2c.c for a description of the
 		command line interface.

-		CONFIG_HARD_I2C	selects the CPM hardware driver for I2C.
+		CONFIG_HARD_I2C selects the CPM hardware driver for I2C.

 		CONFIG_SOFT_I2C configures u-boot to use a software (aka
 		bit-banging) driver instead of CPM or similar hardware
@@ -1061,7 +1061,7 @@ The following options need to be configured:
 		(Optional). Any commands necessary to enable the I2C
 		controller or configure ports.

-		eg: #define I2C_INIT (immr->im_cpm.cp_pbdir |=  PB_SCL)
+		eg: #define I2C_INIT (immr->im_cpm.cp_pbdir |=	PB_SCL)

 		I2C_PORT

@@ -1099,7 +1099,7 @@ The following options need to be configured:

 		eg: #define I2C_SDA(bit) \
 			if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
-			else    immr->im_cpm.cp_pbdat &= ~PB_SDA
+			else	immr->im_cpm.cp_pbdat &= ~PB_SDA

 		I2C_SCL(bit)

@@ -1108,7 +1108,7 @@ The following options need to be configured:

 		eg: #define I2C_SCL(bit) \
 			if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
-			else    immr->im_cpm.cp_pbdat &= ~PB_SCL
+			else	immr->im_cpm.cp_pbdat &= ~PB_SCL

 		I2C_DELAY

@@ -1205,7 +1205,7 @@ The following options need to be configured:
 		Time to wait after FPGA configuration. The default is
 		200 mS.

- FPGA Support:	CONFIG_FPGA_COUNT
+- FPGA Support: CONFIG_FPGA_COUNT

 		Specify the number of FPGA devices to support.

@@ -1422,11 +1422,11 @@ The following options need to be configured:

  Arg	Where			When
    1	common/cmd_bootm.c	before attempting to boot an image
-   -1	common/cmd_bootm.c	Image header has bad     magic number
+   -1	common/cmd_bootm.c	Image header has bad	 magic number
    2	common/cmd_bootm.c	Image header has correct magic number
-   -2	common/cmd_bootm.c	Image header has bad     checksum
+   -2	common/cmd_bootm.c	Image header has bad	 checksum
    3	common/cmd_bootm.c	Image header has correct checksum
-   -3	common/cmd_bootm.c	Image data   has bad     checksum
+   -3	common/cmd_bootm.c	Image data   has bad	 checksum
    4	common/cmd_bootm.c	Image data   has correct checksum
   -4	common/cmd_bootm.c	Image is for unsupported architecture
    5	common/cmd_bootm.c	Architecture check OK
@@ -1439,10 +1439,10 @@ The following options need to be configured:
    8	common/cmd_bootm.c	Image Type check OK
   -9	common/cmd_bootm.c	Unsupported OS (not Linux, BSD, VxWorks, QNX)
    9	common/cmd_bootm.c	Start initial ramdisk verification
-  -10	common/cmd_bootm.c	Ramdisk header has bad     magic number
-  -11	common/cmd_bootm.c	Ramdisk header has bad     checksum
+  -10	common/cmd_bootm.c	Ramdisk header has bad	   magic number
+  -11	common/cmd_bootm.c	Ramdisk header has bad	   checksum
   10	common/cmd_bootm.c	Ramdisk header is OK
-  -12	common/cmd_bootm.c	Ramdisk data   has bad     checksum
+  -12	common/cmd_bootm.c	Ramdisk data   has bad	   checksum
   11	common/cmd_bootm.c	Ramdisk data   has correct checksum
   12	common/cmd_bootm.c	Ramdisk verification complete, start loading
  -13	common/cmd_bootm.c	Wrong Image Type (not PPC Linux Ramdisk)
@@ -1470,7 +1470,7 @@ The following options need to be configured:
   -1	common/cmd_nand.c	Read Error on boot device
   -1	common/cmd_nand.c	Image header has bad magic number

-   -1	common/env_common.c     Environment has a bad CRC, using default
+   -1	common/env_common.c	Environment has a bad CRC, using default


 Modem Support:
@@ -1643,7 +1643,11 @@ Configuration Settings:

 - CFG_FLASH_CFI:
 		Define if the flash driver uses extra elements in the
-		common flash structure for storing flash geometry
+		common flash structure for storing flash geometry.
+
+- CFG_FLASH_CFI_DRIVER
+		This option also enables the building of the cfi_flash driver
+		in the drivers directory

 - CFG_RX_ETH_BUFFER:
 		Defines the number of ethernet receive buffers. On some
@@ -1774,7 +1778,7 @@ to save the current settings.

 	- CFG_EEPROM_PAGE_WRITE_DELAY_MS:
 	  If defined, the number of milliseconds to delay between
-	  page writes.  The default is zero milliseconds.
+	  page writes.	The default is zero milliseconds.

 	- CFG_I2C_EEPROM_ADDR_LEN:
 	  The length in bytes of the EEPROM memory array address.  Note
@@ -1992,7 +1996,7 @@ change it to:
 	CROSS_COMPILE = ppc_4xx-


-U-Boot is intended to be  simple  to  build.  After  installing  the
+U-Boot is intended to be  simple  to  build.  After  installing	 the
 sources	 you must configure U-Boot for one specific board type. This
 is done by typing:

@@ -2020,7 +2024,7 @@ configurations; the following names are supported:
    at91rm9200dk_config	  omap1510inn_config	MPC8260ADS_config
    omap1610inn_config	  ZPC1900_config	MPC8540ADS_config
    MPC8560ADS_config	  QS850_config		QS823_config
-    QS860T_config         DUET_ADS_config
+    QS860T_config	  DUET_ADS_config

 Note: for some board special configuration names may exist; check  if
      additional  information is available from the board vendor; for
@@ -2136,15 +2140,15 @@ mw	- memory write (fill)
 cp	- memory copy
 cmp	- memory compare
 crc32	- checksum calculation
-imd     - i2c memory display
-imm     - i2c memory modify (auto-incrementing)
-inm     - i2c memory modify (constant address)
-imw     - i2c memory write (fill)
-icrc32  - i2c checksum calculation
-iprobe  - probe to discover valid I2C chip addresses
-iloop   - infinite loop on address range
-isdram  - print SDRAM configuration information
-sspi    - SPI utility commands
+imd	- i2c memory display
+imm	- i2c memory modify (auto-incrementing)
+inm	- i2c memory modify (constant address)
+imw	- i2c memory write (fill)
+icrc32	- i2c checksum calculation
+iprobe	- probe to discover valid I2C chip addresses
+iloop	- infinite loop on address range
+isdram	- print SDRAM configuration information
+sspi	- SPI utility commands
 base	- print or set address offset
 printenv- print environment variables
 setenv	- set environment variables
@@ -2473,7 +2477,7 @@ Example:
 	make uImage

 The "uImage" build target uses a special tool (in 'tools/mkimage') to
-encapsulate a compressed Linux kernel image with header  information,
+encapsulate a compressed Linux kernel image with header	 information,
 CRC32 checksum etc. for use with U-Boot. This is what we are doing:

 * build a standard "vmlinux" kernel image (in ELF binary format):
@@ -2860,9 +2864,9 @@ use "cu" for S-Record download ("loads" command).
 Nevertheless, if you absolutely want to use it try adding this
 configuration to your "File transfer protocols" section:

-	   Name    Program                      Name U/D FullScr IO-Red. Multi
-	X  kermit  /usr/bin/kermit -i -l %l -s   Y    U    Y       N      N
-	Y  kermit  /usr/bin/kermit -i -l %l -r   N    D    Y       N      N
+	   Name	   Program			Name U/D FullScr IO-Red. Multi
+	X  kermit  /usr/bin/kermit -i -l %l -s	 Y    U	   Y	   N	  N
+	Y  kermit  /usr/bin/kermit -i -l %l -r	 N    D	   Y	   N	  N


 NetBSD Notes:
@@ -2918,7 +2922,7 @@ models provide on-chip memory (like the IMMR area on MPC8xx and
 MPC826x processors), on others (parts of) the data cache can be
 locked as (mis-) used as memory, etc.

-	Chris Hallinan posted a good summary of  these  issues  to  the
+	Chris Hallinan posted a good summary of	 these	issues	to  the
 	u-boot-users mailing list:

 	Subject: RE: [U-Boot-Users] RE: More On Memory Bank x (nothingness)?
@@ -2987,7 +2991,7 @@ For PowerPC, the following registers have specific use:
 	R1:	stack pointer
 	R2:	TOC pointer
 	R3-R4:	parameter passing and return values
-	R5-R10:	parameter passing
+	R5-R10: parameter passing
 	R13:	small data area pointer
 	R30:	GOT pointer
 	R31:	frame pointer
--- a/board/altera/common/flash.c
+++ b/board/altera/common/flash.c
@@ -71,7 +71,6 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
 	volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
 	volatile CFG_FLASH_WORD_SIZE *addr2;
 	int prot, sect;
-	int any = 0;
 	unsigned oldpri;
 	ulong start;

@@ -94,6 +93,12 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
 		printf ("\n");
 	}

+#ifdef DEBUG
+	for (sect = s_first; sect <= s_last; sect++) {
+		printf("- Erase: Sect: %i @ 0x%08x\n", sect,  info->start[sect]);
+	}
+#endif
+
 	/* NOTE: disabling interrupts on Nios can be very bad since it
 	 * also disables the LO_LIMIT exception. It's better here to
 	 * set the interrupt priority to 3 & restore it when we're done.
@@ -114,26 +119,25 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
 			*addr = 0xaa;
 			*addr = 0x55;
 			*addr2 = 0x30;
-			any = 1;
+			/* Now just wait for 0xff & provide some user
+			 * feedback while we wait. Here we have to grant
+			 * timer interrupts. Otherwise get_timer() can't
+			 * work right. */
+			ipri(oldpri);
+			start = get_timer (0);
+			while (*addr2 != 0xff) {
+				udelay (1000 * 1000);
+				putc ('.');
+				if (get_timer (start) > CFG_FLASH_ERASE_TOUT) {
+					printf ("timeout\n");
+					return 1;
+				}
+			}
+			oldpri = ipri (3); /* disallow non important irqs again */
 		}
 	}

-	/* Now just wait for 0xff & provide some user feedback while
-	 * we wait.
-	 */
-	if (any) {
-		addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
-		start = get_timer (0);
-		while (*addr2 != 0xff) {
-			udelay (1000 * 1000);
-			putc ('.');
-			if (get_timer (start) > CFG_FLASH_ERASE_TOUT) {
-				printf ("timeout\n");
-				return 1;
-			}
-		}
-		printf ("\n");
-	}
+	printf ("\n");

 	/* Restore interrupt priority */
 	ipri (oldpri);
--- a/board/altera/common/sevenseg.c
+++ b/board/altera/common/sevenseg.c
@@ -44,7 +44,7 @@ static int sevenseg_init_done = 0;

 static inline void __sevenseg_set_masked (unsigned int mask, int value)
 {
-	nios_pio_t *piop = (nios_pio_t*)SEVENSEG_BASE;
+	nios_pio_t *piop __attribute__((unused)) = (nios_pio_t*)SEVENSEG_BASE;

 #ifdef	SEVENSEG_WRONLY	/* emulate read access */

@@ -97,7 +97,7 @@ static inline void __sevenseg_toggle_masked (unsigned int mask)

 static inline void __sevenseg_set (unsigned int value)
 {
-	nios_pio_t *piop = (nios_pio_t*)SEVENSEG_BASE;
+	nios_pio_t *piop __attribute__((unused)) = (nios_pio_t*)SEVENSEG_BASE;

 #ifdef	SEVENSEG_WRONLY	/* emulate read access */

@@ -126,7 +126,7 @@ static inline void __sevenseg_set (unsigned int value)

 static inline void __sevenseg_init (void)
 {
-	nios_pio_t *piop = (nios_pio_t*)SEVENSEG_BASE;
+	nios_pio_t *piop __attribute__((unused)) = (nios_pio_t*)SEVENSEG_BASE;

 	__sevenseg_set(0);

--- a/board/altera/dk1c20/dk1c20.c
+++ b/board/altera/dk1c20/dk1c20.c
@@ -33,8 +33,10 @@ void _default_hdlr (void)

 int board_early_init_f (void)
 {
+#if	defined(CONFIG_SEVENSEG)
 	/* init seven segment led display and switch off */
 	sevenseg_set(SEVENSEG_OFF);
+#endif
 	return 0;
 }

--- a/board/altera/dk1s10/dk1s10.c
+++ b/board/altera/dk1s10/dk1s10.c
@@ -33,14 +33,24 @@ void _default_hdlr (void)

 int board_early_init_f (void)
 {
+#if	defined(CONFIG_SEVENSEG)
 	/* init seven segment led display and switch off */
 	sevenseg_set(SEVENSEG_OFF);
+#endif
 	return 0;
 }

 int checkboard (void)
 {
 	puts ("Board: Altera Nios 1S10 Development Kit\n");
+#if     defined(CONFIG_NIOS_SAFE_32)
+	puts ("Conf.: Altera Safe 32 (safe_32)\n");
+#elif   defined(CONFIG_NIOS_STANDARD_32)
+	puts ("Conf.: Altera Standard 32 (standard_32)\n");
+#elif   defined(CONFIG_NIOS_MTX_LDK_20)
+	puts ("Conf.: Microtronix LDK 2.0 (LDK2)\n");
+#endif
+
 	return 0;
 }

--- a/board/altera/dk1s10/vectors.S
+++ b/board/altera/dk1s10/vectors.S
@@ -1,6 +1,7 @@
 /*
 * (C) Copyright 2003, Psyent Corporation <www.psyent.com>
 * Scott McNutt <smcnutt@psyent.com>
+ * Stephan Linz <linz@li-pro.net>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
@@ -21,6 +22,8 @@
 * MA 02111-1307 USA
 */

+#include <config.h>
+

 /*************************************************************************
 * Exception Vector Table
@@ -55,8 +58,14 @@
 	.align	4
 _vectors:

-	.long	_def_xhandler@h		/* Vector 0  - NMI */
-	.long	_cwp_lolimit@h		/* Vector 1  -  underflow */
+#if	defined(CFG_NIOS_CPU_OCI_BASE)
+	/* OCI does the reset job */
+	.long	_def_xhandler@h		/* Vector 0  - NMI / Reset */
+#else
+	/* there is no OCI, so we have to do a direct reset jump here */
+	.long	CFG_NIOS_CPU_RST_VECT	/* Vector 0  - Reset to GERMS */
+#endif
+	.long	_cwp_lolimit@h		/* Vector 1  - underflow */
 	.long	_cwp_hilimit@h		/* Vector 2  - overflow	*/

 	.long	_def_xhandler@h		/* Vector 3 - GNUPro debug */
@@ -72,7 +81,11 @@ _vectors:
 	.long	_def_xhandler@h		/* Vector 13 - future reserved */
 	.long	_def_xhandler@h		/* Vector 14 - future reserved */
 	.long	_def_xhandler@h		/* Vector 15 - future reserved */
+#if	(CFG_NIOS_TMRIRQ == 16)
+	.long	_timebase_int@h		/* Vector 16 - lopri timer*/
+#else
 	.long	_def_xhandler@h		/* Vector 16 */
+#endif
 	.long	_def_xhandler@h		/* Vector 17 */
 	.long	_def_xhandler@h		/* Vector 18 */
 	.long	_def_xhandler@h		/* Vector 19 */
@@ -106,7 +119,11 @@ _vectors:
 	.long	_def_xhandler@h		/* Vector 47 */
 	.long	_def_xhandler@h		/* Vector 48 */
 	.long	_def_xhandler@h		/* Vector 49 */
+#if	(CFG_NIOS_TMRIRQ == 50)
 	.long	_timebase_int@h		/* Vector 50 - lopri timer*/
+#else
+	.long	_def_xhandler@h		/* Vector 50 */
+#endif
 	.long	_def_xhandler@h		/* Vector 51 */
 	.long	_def_xhandler@h		/* Vector 52 */
 	.long	_def_xhandler@h		/* Vector 53 */
--- a/board/at91rm9200dk/u-boot.lds
+++ b/board/at91rm9200dk/u-boot.lds
@@ -45,14 +45,12 @@ SECTIONS
 	. = ALIGN(4);
 	.got : { *(.got) }

-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
-
-	armboot_end_data = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;

 	. = ALIGN(4);
+	__bss_start = .;
 	.bss : { *(.bss) }
-
-	armboot_end = .;
+	_end = .;
 }
--- a/board/bmw/flash.c
+++ b/board/bmw/flash.c
--- a/board/bmw/ns16550.c
+++ b/board/bmw/ns16550.c
@@ -9,49 +9,49 @@

 typedef struct NS16550 *NS16550_t;

-const NS16550_t COM_PORTS[] = { (NS16550_t) ((CFG_EUMB_ADDR) + 0x4500), (NS16550_t) ((CFG_EUMB_ADDR) + 0x4600)};
+const NS16550_t COM_PORTS[] =
+	{ (NS16550_t) ((CFG_EUMB_ADDR) + 0x4500),
+(NS16550_t) ((CFG_EUMB_ADDR) + 0x4600) };

-volatile struct NS16550 *
-NS16550_init(int chan, int baud_divisor)
+volatile struct NS16550 *NS16550_init (int chan, int baud_divisor)
 {
- volatile struct NS16550 *com_port;
- com_port = (struct NS16550 *) COM_PORTS[chan];
- com_port->ier = 0x00;
- com_port->lcr = LCR_BKSE;              /* Access baud rate */
- com_port->dll = baud_divisor & 0xff;   /* 9600 baud */
- com_port->dlm = (baud_divisor >> 8) & 0xff;
- com_port->lcr = LCR_8N1;               /* 8 data, 1 stop, no parity */
- com_port->mcr = MCR_RTS;     /* RTS/DTR */
- com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR;                  /* Clear & enable FIFOs */
-return (com_port);
+	volatile struct NS16550 *com_port;
+
+	com_port = (struct NS16550 *) COM_PORTS[chan];
+	com_port->ier = 0x00;
+	com_port->lcr = LCR_BKSE;	/* Access baud rate */
+	com_port->dll = baud_divisor & 0xff;	/* 9600 baud */
+	com_port->dlm = (baud_divisor >> 8) & 0xff;
+	com_port->lcr = LCR_8N1;	/* 8 data, 1 stop, no parity */
+	com_port->mcr = MCR_RTS;	/* RTS/DTR */
+	com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR;	/* Clear & enable FIFOs */
+	return (com_port);
 }

-void
-NS16550_reinit(volatile struct NS16550 *com_port, int baud_divisor)
+void NS16550_reinit (volatile struct NS16550 *com_port, int baud_divisor)
 {
- com_port->ier = 0x00;
- com_port->lcr = LCR_BKSE;              /* Access baud rate */
- com_port->dll = baud_divisor & 0xff;   /* 9600 baud */
- com_port->dlm = (baud_divisor >> 8) & 0xff;
- com_port->lcr = LCR_8N1;               /* 8 data, 1 stop, no parity */
- com_port->mcr = MCR_RTS;     /* RTS/DTR */
- com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR;                  /* Clear & enable FIFOs */
+	com_port->ier = 0x00;
+	com_port->lcr = LCR_BKSE;	/* Access baud rate */
+	com_port->dll = baud_divisor & 0xff;	/* 9600 baud */
+	com_port->dlm = (baud_divisor >> 8) & 0xff;
+	com_port->lcr = LCR_8N1;	/* 8 data, 1 stop, no parity */
+	com_port->mcr = MCR_RTS;	/* RTS/DTR */
+	com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR;	/* Clear & enable FIFOs */
 }

-void NS16550_putc(volatile struct NS16550 *com_port, unsigned char c)
+void NS16550_putc (volatile struct NS16550 *com_port, unsigned char c)
 {
- while ((com_port->lsr & LSR_THRE) == 0) ;
- com_port->thr = c;
+	while ((com_port->lsr & LSR_THRE) == 0);
+	com_port->thr = c;
 }

-unsigned char
-NS16550_getc(volatile struct NS16550 *com_port)
+unsigned char NS16550_getc (volatile struct NS16550 *com_port)
 {
- while ((com_port->lsr & LSR_DR) == 0) ;
- return (com_port->rbr);
+	while ((com_port->lsr & LSR_DR) == 0);
+	return (com_port->rbr);
 }

-int NS16550_tstc(volatile struct NS16550 *com_port)
+int NS16550_tstc (volatile struct NS16550 *com_port)
 {
- return ((com_port->lsr & LSR_DR) != 0);
+	return ((com_port->lsr & LSR_DR) != 0);
 }
--- a/board/bmw/ns16550.h
+++ b/board/bmw/ns16550.h
@@ -12,20 +12,19 @@
 */


-struct NS16550
- {
-  unsigned char rbrthrdlb;  /* 0 */
-  unsigned char ierdmb;     /* 1 */
-  unsigned char iirfcrafr;  /* 2 */
-  unsigned char lcr;         /* 3 */
-  unsigned char mcr;         /* 4 */
-  unsigned char lsr;         /* 5 */
-  unsigned char msr;         /* 6 */
-  unsigned char scr;         /* 7 */
-  unsigned char reserved[2]; /* 8 & 9 */
-  unsigned char dsr;         /* 10 */
-  unsigned char dcr;         /* 11 */
- };
+struct NS16550 {
+	unsigned char rbrthrdlb;	/* 0 */
+	unsigned char ierdmb;		/* 1 */
+	unsigned char iirfcrafr;	/* 2 */
+	unsigned char lcr;		/* 3 */
+	unsigned char mcr;		/* 4 */
+	unsigned char lsr;		/* 5 */
+	unsigned char msr;		/* 6 */
+	unsigned char scr;		/* 7 */
+	unsigned char reserved[2];	/* 8 & 9 */
+	unsigned char dsr;		/* 10 */
+	unsigned char dcr;		/* 11 */
+};


 #define rbr rbrthrdlb
@@ -37,44 +36,44 @@ struct NS16550
 #define fcr iirfcrafr
 #define afr iirfcrafr

-#define FCR_FIFO_EN     0x01    /*fifo enable*/
-#define FCR_RXSR        0x02    /*reciever soft reset*/
-#define FCR_TXSR        0x04    /*transmitter soft reset*/
-#define FCR_DMS		0x08    /* DMA Mode Select */
+#define FCR_FIFO_EN     0x01	/*fifo enable */
+#define FCR_RXSR        0x02	/*reciever soft reset */
+#define FCR_TXSR        0x04	/*transmitter soft reset */
+#define FCR_DMS		0x08	/* DMA Mode Select */

-#define MCR_RTS         0x02    /* Readyu to Send */
+#define MCR_RTS         0x02	/* Readyu to Send */
 #define MCR_LOOP	0x10	/* Local loopback mode enable */
 /* #define MCR_DTR         0x01    noton 8245 duart */
 /* #define MCR_DMA_EN      0x04    noton 8245 duart */
 /* #define MCR_TX_DFR      0x08    noton 8245 duart */

-#define LCR_WLS_MSK 0x03    /* character length slect mask*/
-#define LCR_WLS_5   0x00    /* 5 bit character length */
-#define LCR_WLS_6   0x01    /* 6 bit character length */
-#define LCR_WLS_7   0x02    /* 7 bit character length */
-#define LCR_WLS_8   0x03    /* 8 bit character length */
-#define LCR_STB     0x04    /* Number of stop Bits, off = 1, on = 1.5 or 2) */
-#define LCR_PEN     0x08    /* Parity eneble*/
-#define LCR_EPS     0x10    /* Even Parity Select*/
-#define LCR_STKP    0x20    /* Stick Parity*/
-#define LCR_SBRK    0x40    /* Set Break*/
-#define LCR_BKSE    0x80    /* Bank select enable - aka DLAB on 8245 */
+#define LCR_WLS_MSK 0x03	/* character length slect mask */
+#define LCR_WLS_5   0x00	/* 5 bit character length */
+#define LCR_WLS_6   0x01	/* 6 bit character length */
+#define LCR_WLS_7   0x02	/* 7 bit character length */
+#define LCR_WLS_8   0x03	/* 8 bit character length */
+#define LCR_STB     0x04	/* Number of stop Bits, off = 1, on = 1.5 or 2) */
+#define LCR_PEN     0x08	/* Parity eneble */
+#define LCR_EPS     0x10	/* Even Parity Select */
+#define LCR_STKP    0x20	/* Stick Parity */
+#define LCR_SBRK    0x40	/* Set Break */
+#define LCR_BKSE    0x80	/* Bank select enable - aka DLAB on 8245 */

-#define LSR_DR      0x01    /* Data ready */
-#define LSR_OE      0x02    /* Overrun */
-#define LSR_PE      0x04    /* Parity error */
-#define LSR_FE      0x08    /* Framing error */
-#define LSR_BI      0x10    /* Break */
-#define LSR_THRE    0x20    /* Xmit holding register empty */
-#define LSR_TEMT    0x40    /* Xmitter empty */
-#define LSR_ERR     0x80    /* Error */
+#define LSR_DR      0x01	/* Data ready */
+#define LSR_OE      0x02	/* Overrun */
+#define LSR_PE      0x04	/* Parity error */
+#define LSR_FE      0x08	/* Framing error */
+#define LSR_BI      0x10	/* Break */
+#define LSR_THRE    0x20	/* Xmit holding register empty */
+#define LSR_TEMT    0x40	/* Xmitter empty */
+#define LSR_ERR     0x80	/* Error */

 /* useful defaults for LCR*/
 #define LCR_8N1     0x03


-volatile struct NS16550 * NS16550_init(int chan, int baud_divisor);
-void NS16550_putc(volatile struct NS16550 *com_port, unsigned char c);
-unsigned char NS16550_getc(volatile struct NS16550 *com_port);
-int NS16550_tstc(volatile struct NS16550 *com_port);
-void NS16550_reinit(volatile struct NS16550 *com_port, int baud_divisor);
+volatile struct NS16550 *NS16550_init (int chan, int baud_divisor);
+void NS16550_putc (volatile struct NS16550 *com_port, unsigned char c);
+unsigned char NS16550_getc (volatile struct NS16550 *com_port);
+int NS16550_tstc (volatile struct NS16550 *com_port);
+void NS16550_reinit (volatile struct NS16550 *com_port, int baud_divisor);
--- a/board/cogent/mb.c
+++ b/board/cogent/mb.c
@@ -43,152 +43,166 @@

 const iop_conf_t iop_conf_tab[4][32] = {

-    /* Port A configuration */
-    {	/*	      conf ppar psor pdir podr pdat */
-	/* PA31 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA30 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA29 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA28 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA27 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA26 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA25 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA24 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA23 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA22 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA21 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA20 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA19 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA18 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA17 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA16 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA15 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA14 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA13 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA12 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA11 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA10 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA9  */ {   1,   1,   0,   1,   0,   0   },	/* SMC2 TXD */
-	/* PA8  */ {   1,   1,   0,   0,   0,   0   },	/* SMC2 RXD */
-	/* PA7  */ {   0,   0,   0,   0,   0,   0   },
-	/* PA6  */ {   0,   0,   0,   0,   0,   0   },
-	/* PA5  */ {   0,   0,   0,   0,   0,   0   },
-	/* PA4  */ {   0,   0,   0,   0,   0,   0   },
-	/* PA3  */ {   0,   0,   0,   0,   0,   0   },
-	/* PA2  */ {   0,   0,   0,   0,   0,   0   },
-	/* PA1  */ {   0,   0,   0,   0,   0,   0   },
-	/* PA0  */ {   0,   0,   0,   0,   0,   0   }
-    },
+	/* Port A configuration */
+	{			/*            conf ppar psor pdir podr pdat */
+	 /* PA31 */ {0, 0, 0, 0, 0, 0},
+	 /* PA30 */ {0, 0, 0, 0, 0, 0},
+	 /* PA29 */ {0, 0, 0, 0, 0, 0},
+	 /* PA28 */ {0, 0, 0, 0, 0, 0},
+	 /* PA27 */ {0, 0, 0, 0, 0, 0},
+	 /* PA26 */ {0, 0, 0, 0, 0, 0},
+	 /* PA25 */ {0, 0, 0, 0, 0, 0},
+	 /* PA24 */ {0, 0, 0, 0, 0, 0},
+	 /* PA23 */ {0, 0, 0, 0, 0, 0},
+	 /* PA22 */ {0, 0, 0, 0, 0, 0},
+	 /* PA21 */ {0, 0, 0, 0, 0, 0},
+	 /* PA20 */ {0, 0, 0, 0, 0, 0},
+	 /* PA19 */ {0, 0, 0, 0, 0, 0},
+	 /* PA18 */ {0, 0, 0, 0, 0, 0},
+	 /* PA17 */ {0, 0, 0, 0, 0, 0},
+	 /* PA16 */ {0, 0, 0, 0, 0, 0},
+	 /* PA15 */ {0, 0, 0, 0, 0, 0},
+	 /* PA14 */ {0, 0, 0, 0, 0, 0},
+	 /* PA13 */ {0, 0, 0, 0, 0, 0},
+	 /* PA12 */ {0, 0, 0, 0, 0, 0},
+	 /* PA11 */ {0, 0, 0, 0, 0, 0},
+	 /* PA10 */ {0, 0, 0, 0, 0, 0},
+					/* PA9  */ {1, 1, 0, 1, 0, 0},
+					/* SMC2 TXD */
+					/* PA8  */ {1, 1, 0, 0, 0, 0},
+					/* SMC2 RXD */
+	 /* PA7  */ {0, 0, 0, 0, 0, 0},
+	 /* PA6  */ {0, 0, 0, 0, 0, 0},
+	 /* PA5  */ {0, 0, 0, 0, 0, 0},
+	 /* PA4  */ {0, 0, 0, 0, 0, 0},
+	 /* PA3  */ {0, 0, 0, 0, 0, 0},
+	 /* PA2  */ {0, 0, 0, 0, 0, 0},
+	 /* PA1  */ {0, 0, 0, 0, 0, 0},
+	 /* PA0  */ {0, 0, 0, 0, 0, 0}
+	 },


-    {   /*	      conf ppar psor pdir podr pdat */
-	/* PB31 */ {   0,   0,   0,   0,   0,   0   },
-	/* PB30 */ {   0,   0,   0,   0,   0,   0   },
-	/* PB29 */ {   0,   0,   0,   0,   0,   0   },
-	/* PB28 */ {   0,   0,   0,   0,   0,   0   },
-	/* PB27 */ {   0,   0,   0,   0,   0,   0   },
-	/* PB26 */ {   0,   0,   0,   0,   0,   0   },
-	/* PB25 */ {   0,   0,   0,   0,   0,   0   },
-	/* PB24 */ {   0,   0,   0,   0,   0,   0   },
-	/* PB23 */ {   0,   0,   0,   0,   0,   0   },
-	/* PB22 */ {   0,   0,   0,   0,   0,   0   },
-	/* PB21 */ {   0,   0,   0,   0,   0,   0   },
-	/* PB20 */ {   0,   0,   0,   0,   0,   0   },
-	/* PB19 */ {   0,   0,   0,   0,   0,   0   },
-	/* PB18 */ {   0,   0,   0,   0,   0,   0   },
-	/* PB17 */ {   0,   0,   0,   0,   0,   0   },
-	/* PB16 */ {   0,   0,   0,   0,   0,   0   },
-	/* PB15 */ {   0,   0,   0,   0,   0,   0   },
-	/* PB14 */ {   0,   0,   0,   0,   0,   0   },
-	/* PB13 */ {   0,   0,   0,   0,   0,   0   },
-	/* PB12 */ {   0,   0,   0,   0,   0,   0   },
-	/* PB11 */ {   0,   0,   0,   0,   0,   0   },
-	/* PB10 */ {   0,   0,   0,   0,   0,   0   },
-	/* PB9  */ {   0,   0,   0,   0,   0,   0   },
-	/* PB8  */ {   0,   0,   0,   0,   0,   0   },
-	/* PB7  */ {   0,   0,   0,   0,   0,   0   },
-	/* PB6  */ {   0,   0,   0,   0,   0,   0   },
-	/* PB5  */ {   0,   0,   0,   0,   0,   0   },
-	/* PB4  */ {   0,   0,   0,   0,   0,   0   },
-	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
-    },
+	{			/*            conf ppar psor pdir podr pdat */
+	 /* PB31 */ {0, 0, 0, 0, 0, 0},
+	 /* PB30 */ {0, 0, 0, 0, 0, 0},
+	 /* PB29 */ {0, 0, 0, 0, 0, 0},
+	 /* PB28 */ {0, 0, 0, 0, 0, 0},
+	 /* PB27 */ {0, 0, 0, 0, 0, 0},
+	 /* PB26 */ {0, 0, 0, 0, 0, 0},
+	 /* PB25 */ {0, 0, 0, 0, 0, 0},
+	 /* PB24 */ {0, 0, 0, 0, 0, 0},
+	 /* PB23 */ {0, 0, 0, 0, 0, 0},
+	 /* PB22 */ {0, 0, 0, 0, 0, 0},
+	 /* PB21 */ {0, 0, 0, 0, 0, 0},
+	 /* PB20 */ {0, 0, 0, 0, 0, 0},
+	 /* PB19 */ {0, 0, 0, 0, 0, 0},
+	 /* PB18 */ {0, 0, 0, 0, 0, 0},
+	 /* PB17 */ {0, 0, 0, 0, 0, 0},
+	 /* PB16 */ {0, 0, 0, 0, 0, 0},
+	 /* PB15 */ {0, 0, 0, 0, 0, 0},
+	 /* PB14 */ {0, 0, 0, 0, 0, 0},
+	 /* PB13 */ {0, 0, 0, 0, 0, 0},
+	 /* PB12 */ {0, 0, 0, 0, 0, 0},
+	 /* PB11 */ {0, 0, 0, 0, 0, 0},
+	 /* PB10 */ {0, 0, 0, 0, 0, 0},
+	 /* PB9  */ {0, 0, 0, 0, 0, 0},
+	 /* PB8  */ {0, 0, 0, 0, 0, 0},
+	 /* PB7  */ {0, 0, 0, 0, 0, 0},
+	 /* PB6  */ {0, 0, 0, 0, 0, 0},
+	 /* PB5  */ {0, 0, 0, 0, 0, 0},
+	 /* PB4  */ {0, 0, 0, 0, 0, 0},
+					/* PB3  */ {0, 0, 0, 0, 0, 0},
+					/* pin doesn't exist */
+					/* PB2  */ {0, 0, 0, 0, 0, 0},
+					/* pin doesn't exist */
+					/* PB1  */ {0, 0, 0, 0, 0, 0},
+					/* pin doesn't exist */
+					/* PB0  */ {0, 0, 0, 0, 0, 0}
+					/* pin doesn't exist */
+	 },


-    {   /*	      conf ppar psor pdir podr pdat */
-	/* PC31 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC30 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC29 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC28 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC27 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC26 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC25 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC24 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC23 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC22 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC21 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC20 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC19 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC18 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC17 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC16 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC15 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC14 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC13 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC12 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC11 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC10 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC9  */ {   0,   0,   0,   0,   0,   0   },
-	/* PC8  */ {   0,   0,   0,   0,   0,   0   },
-	/* PC7  */ {   0,   0,   0,   0,   0,   0   },
-	/* PC6  */ {   0,   0,   0,   0,   0,   0   },
-	/* PC5  */ {   0,   0,   0,   0,   0,   0   },
-	/* PC4  */ {   0,   0,   0,   0,   0,   0   },
-	/* PC3  */ {   0,   0,   0,   0,   0,   0   },
-	/* PC2  */ {   0,   0,   0,   0,   0,   0   },
-	/* PC1  */ {   0,   0,   0,   0,   0,   0   },
-	/* PC0  */ {   0,   0,   0,   0,   0,   0   }
-    },
+	{			/*            conf ppar psor pdir podr pdat */
+	 /* PC31 */ {0, 0, 0, 0, 0, 0},
+	 /* PC30 */ {0, 0, 0, 0, 0, 0},
+	 /* PC29 */ {0, 0, 0, 0, 0, 0},
+	 /* PC28 */ {0, 0, 0, 0, 0, 0},
+	 /* PC27 */ {0, 0, 0, 0, 0, 0},
+	 /* PC26 */ {0, 0, 0, 0, 0, 0},
+	 /* PC25 */ {0, 0, 0, 0, 0, 0},
+	 /* PC24 */ {0, 0, 0, 0, 0, 0},
+	 /* PC23 */ {0, 0, 0, 0, 0, 0},
+	 /* PC22 */ {0, 0, 0, 0, 0, 0},
+	 /* PC21 */ {0, 0, 0, 0, 0, 0},
+	 /* PC20 */ {0, 0, 0, 0, 0, 0},
+	 /* PC19 */ {0, 0, 0, 0, 0, 0},
+	 /* PC18 */ {0, 0, 0, 0, 0, 0},
+	 /* PC17 */ {0, 0, 0, 0, 0, 0},
+	 /* PC16 */ {0, 0, 0, 0, 0, 0},
+	 /* PC15 */ {0, 0, 0, 0, 0, 0},
+	 /* PC14 */ {0, 0, 0, 0, 0, 0},
+	 /* PC13 */ {0, 0, 0, 0, 0, 0},
+	 /* PC12 */ {0, 0, 0, 0, 0, 0},
+	 /* PC11 */ {0, 0, 0, 0, 0, 0},
+	 /* PC10 */ {0, 0, 0, 0, 0, 0},
+	 /* PC9  */ {0, 0, 0, 0, 0, 0},
+	 /* PC8  */ {0, 0, 0, 0, 0, 0},
+	 /* PC7  */ {0, 0, 0, 0, 0, 0},
+	 /* PC6  */ {0, 0, 0, 0, 0, 0},
+	 /* PC5  */ {0, 0, 0, 0, 0, 0},
+	 /* PC4  */ {0, 0, 0, 0, 0, 0},
+	 /* PC3  */ {0, 0, 0, 0, 0, 0},
+	 /* PC2  */ {0, 0, 0, 0, 0, 0},
+	 /* PC1  */ {0, 0, 0, 0, 0, 0},
+	 /* PC0  */ {0, 0, 0, 0, 0, 0}
+	 },


-    {   /*	      conf ppar psor pdir podr pdat */
-	/* PD31 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD30 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD29 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD28 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD27 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD26 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD25 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD24 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD23 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD22 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD21 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD20 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD19 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD18 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD17 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD16 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD15 */ {   1,   1,   1,   0,   0,   0   },	/* I2C SDA */
-	/* PD14 */ {   1,   1,   1,   0,   0,   0   },	/* I2C SCL */
-	/* PD13 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD12 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD11 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD10 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD9  */ {   1,   1,   0,   1,   0,   0   },	/* SMC1 TXD */
-	/* PD8  */ {   1,   1,   0,   0,   0,   0   },	/* SMC1 RXD */
-	/* PD7  */ {   0,   0,   0,   0,   0,   0   },
-	/* PD6  */ {   0,   0,   0,   0,   0,   0   },
-	/* PD5  */ {   0,   0,   0,   0,   0,   0   },
-	/* PD4  */ {   0,   0,   0,   0,   0,   0   },
-	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
-    }
+	{			/*            conf ppar psor pdir podr pdat */
+	 /* PD31 */ {0, 0, 0, 0, 0, 0},
+	 /* PD30 */ {0, 0, 0, 0, 0, 0},
+	 /* PD29 */ {0, 0, 0, 0, 0, 0},
+	 /* PD28 */ {0, 0, 0, 0, 0, 0},
+	 /* PD27 */ {0, 0, 0, 0, 0, 0},
+	 /* PD26 */ {0, 0, 0, 0, 0, 0},
+	 /* PD25 */ {0, 0, 0, 0, 0, 0},
+	 /* PD24 */ {0, 0, 0, 0, 0, 0},
+	 /* PD23 */ {0, 0, 0, 0, 0, 0},
+	 /* PD22 */ {0, 0, 0, 0, 0, 0},
+	 /* PD21 */ {0, 0, 0, 0, 0, 0},
+	 /* PD20 */ {0, 0, 0, 0, 0, 0},
+	 /* PD19 */ {0, 0, 0, 0, 0, 0},
+	 /* PD18 */ {0, 0, 0, 0, 0, 0},
+	 /* PD17 */ {0, 0, 0, 0, 0, 0},
+	 /* PD16 */ {0, 0, 0, 0, 0, 0},
+					/* PD15 */ {1, 1, 1, 0, 0, 0},
+					/* I2C SDA */
+					/* PD14 */ {1, 1, 1, 0, 0, 0},
+					/* I2C SCL */
+	 /* PD13 */ {0, 0, 0, 0, 0, 0},
+	 /* PD12 */ {0, 0, 0, 0, 0, 0},
+	 /* PD11 */ {0, 0, 0, 0, 0, 0},
+	 /* PD10 */ {0, 0, 0, 0, 0, 0},
+					/* PD9  */ {1, 1, 0, 1, 0, 0},
+					/* SMC1 TXD */
+					/* PD8  */ {1, 1, 0, 0, 0, 0},
+					/* SMC1 RXD */
+	 /* PD7  */ {0, 0, 0, 0, 0, 0},
+	 /* PD6  */ {0, 0, 0, 0, 0, 0},
+	 /* PD5  */ {0, 0, 0, 0, 0, 0},
+	 /* PD4  */ {0, 0, 0, 0, 0, 0},
+					/* PD3  */ {0, 0, 0, 0, 0, 0},
+					/* pin doesn't exist */
+					/* PD2  */ {0, 0, 0, 0, 0, 0},
+					/* pin doesn't exist */
+					/* PD1  */ {0, 0, 0, 0, 0, 0},
+					/* pin doesn't exist */
+					/* PD0  */ {0, 0, 0, 0, 0, 0}
+					/* pin doesn't exist */
+	 }
 };

-#endif	/* CONFIG_8260 */
+#endif /* CONFIG_8260 */

 /* ------------------------------------------------------------------------- */

@@ -196,12 +210,11 @@ const iop_conf_t iop_conf_tab[4][32] = {
 * Check Board Identity:
 */

-int
-checkboard(void)
+int checkboard (void)
 {
-    puts ("Board: Cogent " COGENT_MOTHERBOARD " motherboard with a "
-	COGENT_CPU_MODULE " CPU Module\n");
-    return (0);
+	puts ("Board: Cogent " COGENT_MOTHERBOARD " motherboard with a "
+	      COGENT_CPU_MODULE " CPU Module\n");
+	return (0);
 }

 /* ------------------------------------------------------------------------- */
@@ -213,46 +226,44 @@ checkboard(void)

 int misc_init_f (void)
 {
-    printf ("DIPSW: ");
-    dipsw_init();
-    return (0);
+	printf ("DIPSW: ");
+	dipsw_init ();
+	return (0);
 }

 /* ------------------------------------------------------------------------- */

-long int
-initdram(int board_type)
+long int initdram (int board_type)
 {
 #if CONFIG_CMA111
-    return (32L * 1024L * 1024L);
+	return (32L * 1024L * 1024L);
 #else
-    unsigned char dipsw_val;
-    int dual, size0, size1;
-    long int memsize;
+	unsigned char dipsw_val;
+	int dual, size0, size1;
+	long int memsize;

-    dipsw_val = dipsw_cooked();
+	dipsw_val = dipsw_cooked ();

-    dual = dipsw_val & 0x01;
-    size0 = (dipsw_val & 0x08) >> 3;
-    size1 = (dipsw_val & 0x04) >> 2;
+	dual = dipsw_val & 0x01;
+	size0 = (dipsw_val & 0x08) >> 3;
+	size1 = (dipsw_val & 0x04) >> 2;

-    if (size0)
-	if (size1)
-	    memsize = 16L * 1024L * 1024L;
-	else
-	    memsize =  1L * 1024L * 1024L;
-    else
-	if (size1)
-	    memsize =  4L * 1024L * 1024L;
+	if (size0)
+		if (size1)
+			memsize = 16L * 1024L * 1024L;
+		else
+			memsize = 1L * 1024L * 1024L;
+	else if (size1)
+		memsize = 4L * 1024L * 1024L;
 	else {
-	    printf("[Illegal dip switch settings - assuming 16Mbyte SIMMs] ");
-	    memsize = 16L * 1024L * 1024L; /* shouldn't happen - guess 16M */
+		printf ("[Illegal dip switch settings - assuming 16Mbyte SIMMs] ");
+		memsize = 16L * 1024L * 1024L;	/* shouldn't happen - guess 16M */
 	}

-    if (dual)
-	memsize *= 2L;
+	if (dual)
+		memsize *= 2L;

-    return (memsize);
+	return (memsize);
 #endif
 }

@@ -265,21 +276,21 @@ initdram(int board_type)

 int misc_init_r (void)
 {
-    printf ("LCD:   ");
-    lcd_init();
+	printf ("LCD:   ");
+	lcd_init ();

 #if 0
-    printf ("RTC:   ");
-    rtc_init();
+	printf ("RTC:   ");
+	rtc_init ();

-    printf ("PAR:   ");
-    par_init();
+	printf ("PAR:   ");
+	par_init ();

-    printf ("KBM:   ");
-    kbm_init();
+	printf ("KBM:   ");
+	kbm_init ();

-    printf ("PCI:   ");
-    pci_init();
+	printf ("PCI:   ");
+	pci_init ();
 #endif
-    return (0);
+	return (0);
 }
--- a/board/cradle/u-boot.lds
+++ b/board/cradle/u-boot.lds
@@ -44,17 +44,12 @@ SECTIONS
 	. = ALIGN(4);
 	.got : { *(.got) }

-   __u_boot_cmd_start = .;
-   .u_boot_cmd : { *(.u_boot_cmd) }
-   __u_boot_cmd_end = .;
-
-	armboot_end_data = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;

 	. = ALIGN(4);
-	bss_start = .;
+	__bss_start = .;
 	.bss : { *(.bss) }
-	bss_end = .;
-
-	armboot_end = .;
-
+	_end = .;
 }
--- a/board/csb226/flash.c
+++ b/board/csb226/flash.c
@@ -9,6 +9,9 @@
 * (C) Copyright 2002
 * Robert Schwebel, Pengutronix, <r.schwebel@pengutronix.de>
 *
+ * (C) Copyright 2003 (2 x 16 bit Flash bank patches)
+ * Rolf Peukert, IMMS gGmbH, <rolf.peukert@imms.de>
+ *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
@@ -19,7 +22,7 @@
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
@@ -32,9 +35,9 @@
 #include <asm/arch/pxa-regs.h>

 #define FLASH_BANK_SIZE 0x02000000
-#define MAIN_SECT_SIZE  0x40000         /* 2x16 = 256k per sector */
+#define MAIN_SECT_SIZE	0x40000		/* 2x16 = 256k per sector */

-flash_info_t    flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS];


 /**
@@ -51,19 +54,19 @@ ulong flash_init(void)
 	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
 		ulong flashbase = 0;
 		flash_info[i].flash_id =
-	  		(INTEL_MANUFACT & FLASH_VENDMASK) |
-	  		(INTEL_ID_28F128J3 & FLASH_TYPEMASK);
+			(INTEL_MANUFACT & FLASH_VENDMASK) |
+			(INTEL_ID_28F128J3 & FLASH_TYPEMASK);
 		flash_info[i].size = FLASH_BANK_SIZE;
 		flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
 		memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);

 		switch (i) {
-			case 0:
-				flashbase = PHYS_FLASH_1;
-				break;
-			default:
-				panic("configured too many flash banks!\n");
-				break;
+		case 0:
+			flashbase = PHYS_FLASH_1;
+			break;
+		default:
+			panic("configured too many flash banks!\n");
+			break;
 		}
 		for (j = 0; j < flash_info[i].sector_count; j++) {
 			flash_info[i].start[j] = flashbase + j*MAIN_SECT_SIZE;
@@ -88,8 +91,6 @@ ulong flash_init(void)

 /**
 * flash_print_info: - print information about the flash situation
- *
- * @param info:
 */

 void flash_print_info  (flash_info_t *info)
@@ -99,23 +100,21 @@ void flash_print_info  (flash_info_t *info)
 	for (j=0; j<CFG_MAX_FLASH_BANKS; j++) {

 		switch (info->flash_id & FLASH_VENDMASK) {
-
-			case (INTEL_MANUFACT & FLASH_VENDMASK):
-				printf("Intel: ");
-				break;
-			default:
-				printf("Unknown Vendor ");
-				break;
+		case (INTEL_MANUFACT & FLASH_VENDMASK):
+			printf ("Intel: ");
+			break;
+		default:
+			printf ("Unknown Vendor ");
+			break;
 		}

 		switch (info->flash_id & FLASH_TYPEMASK) {
-
-			case (INTEL_ID_28F128J3 & FLASH_TYPEMASK):
-				printf("28F128J3 (128Mbit)\n");
-				break;
-			default:
-				printf("Unknown Chip Type\n");
-				return;
+		case (INTEL_ID_28F128J3 & FLASH_TYPEMASK):
+			printf("28F128J3 (128Mbit)\n");
+			break;
+		default:
+			printf("Unknown Chip Type\n");
+			return;
 		}

 		printf("  Size: %ld MB in %d Sectors\n",
@@ -123,10 +122,10 @@ void flash_print_info  (flash_info_t *info)

 		printf("  Sector Start Addresses:");
 		for (i = 0; i < info->sector_count; i++) {
-			if ((i % 5) == 0) printf ("\n   ");
+			if ((i % 5) == 0) printf ("\n	");

 			printf (" %08lX%s", info->start[i],
-				info->protect[i] ? " (RO)" : "     ");
+				info->protect[i] ? " (RO)" : "	   ");
 		}
 		printf ("\n");
 		info++;
@@ -136,7 +135,6 @@ void flash_print_info  (flash_info_t *info)

 /**
 * flash_erase: - erase flash sectors
- *
 */

 int flash_erase(flash_info_t *info, int s_first, int s_last)
@@ -179,13 +177,13 @@ int flash_erase(flash_info_t *info, int s_first, int s_last)
 		/* arm simple, non interrupt dependent timer */
 		reset_timer_masked();

-		if (info->protect[sect] == 0) {	/* not protected */
+		if (info->protect[sect] == 0) { /* not protected */
 			u32 * volatile addr = (u32 * volatile)(info->start[sect]);

-			/* erase sector:                                    */
+			/* erase sector:				    */
 			/* The strata flashs are aligned side by side on    */
 			/* the data bus, so we have to write the commands   */
-			/* to both chips here:                              */
+			/* to both chips here:				    */

 			*addr = 0x00200020;	/* erase setup */
 			*addr = 0x00D000D0;	/* erase confirm */
@@ -198,19 +196,14 @@ int flash_erase(flash_info_t *info, int s_first, int s_last)
 					goto outahere;
 				}
 			}
-
 			*addr = 0x00500050; /* clear status register cmd.   */
-			*addr = 0x00FF00FF; /* resest to read mode          */
-
+			*addr = 0x00FF00FF; /* reset to read mode	    */
 		}
-
 		printf("ok.\n");
 	}
-
 	if (ctrlc()) printf("User Interrupt!\n");

-	outahere:
-
+outahere:
 	/* allow flash to settle - wait 10 ms */
 	udelay_masked(10000);

@@ -219,22 +212,19 @@ int flash_erase(flash_info_t *info, int s_first, int s_last)
 	return rc;
 }

-
 /**
- * write_word: - copy memory to flash
- *
- * @param info:
- * @param dest:
- * @param data:
- * @return:
+ * write_long: - copy memory to flash, assume a bank of 2 devices with 16bit each
 */

-static int write_word (flash_info_t *info, ulong dest, ushort data)
+static int write_long (flash_info_t *info, ulong dest, ulong data)
 {
 	u32 * volatile addr = (u32 * volatile)dest, val;
 	int rc = ERR_OK;
 	int flag;

+	/* read array command - just for the case... */
+	*addr = 0x00FF00FF;
+
 	/* Check if Flash is (sufficiently) erased */
 	if ((*addr & data) != data) return ERR_NOT_ERASED;

@@ -248,10 +238,10 @@ static int write_word (flash_info_t *info, ulong dest, ushort data)
 	flag = disable_interrupts();

 	/* clear status register command */
-	*addr = 0x50;
+	*addr = 0x00500050;

 	/* program set-up command */
-	*addr = 0x40;
+	*addr = 0x00400040;

 	/* latch address/data */
 	*addr = data;
@@ -260,28 +250,30 @@ static int write_word (flash_info_t *info, ulong dest, ushort data)
 	reset_timer_masked();

 	/* wait while polling the status register */
-	while(((val = *addr) & 0x80) != 0x80) {
+	while(((val = *addr) & 0x00800080) != 0x00800080) {
 		if (get_timer_masked() > CFG_FLASH_WRITE_TOUT) {
 			rc = ERR_TIMOUT;
-			*addr = 0xB0; /* suspend program command */
+			/* suspend program command */
+			*addr = 0x00B000B0;
 			goto outahere;
 		}
 	}

-	if(val & 0x1A) {	/* check for error */
+	/* check for errors */
+	if(val & 0x001A001A) {
 		printf("\nFlash write error %02x at address %08lx\n",
 			(int)val, (unsigned long)dest);
-		if(val & (1<<3)) {
+		if(val & 0x00080008) {
 			printf("Voltage range error.\n");
 			rc = ERR_PROG_ERROR;
 			goto outahere;
 		}
-		if(val & (1<<1)) {
+		if(val & 0x00020002) {
 			printf("Device protect error.\n");
 			rc = ERR_PROTECTED;
 			goto outahere;
 		}
-		if(val & (1<<4)) {
+		if(val & 0x00100010) {
 			printf("Programming error.\n");
 			rc = ERR_PROG_ERROR;
 			goto outahere;
@@ -290,9 +282,9 @@ static int write_word (flash_info_t *info, ulong dest, ushort data)
 		goto outahere;
 	}

-	outahere:
-
-	*addr = 0xFF; /* read array command */
+outahere:
+	/* read array command */
+	*addr = 0x00FF00FF;
 	if (flag) enable_interrupts();

 	return rc;
@@ -304,20 +296,21 @@ static int write_word (flash_info_t *info, ulong dest, ushort data)
 *
 * @param info:
 * @param src:	source of copy transaction
- * @param addr:	where to copy to
- * @param cnt: 	number of bytes to copy
+ * @param addr: where to copy to
+ * @param cnt:	number of bytes to copy
 *
 * @return	error code
 */

+/* "long" version, uses 32bit words */
 int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
 {
 	ulong cp, wp;
-	ushort data;
+	ulong data;
 	int l;
 	int i, rc;

-	wp = (addr & ~1);	/* get lower word aligned address */
+	wp = (addr & ~3);	/* get lower word aligned address */

 	/*
 	 * handle unaligned start bytes
@@ -325,35 +318,34 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
 	if ((l = addr - wp) != 0) {
 		data = 0;
 		for (i=0, cp=wp; i<l; ++i, ++cp) {
-			data = (data >> 8) | (*(uchar *)cp << 8);
+			data = (data >> 8) | (*(uchar *)cp << 24);
 		}
-		for (; i<2 && cnt>0; ++i) {
-			data = (data >> 8) | (*src++ << 8);
+		for (; i<4 && cnt>0; ++i) {
+			data = (data >> 8) | (*src++ << 24);
 			--cnt;
 			++cp;
 		}
-		for (; cnt==0 && i<2; ++i, ++cp) {
-			data = (data >> 8) | (*(uchar *)cp << 8);
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *)cp << 24);
 		}

-		if ((rc = write_word(info, wp, data)) != 0) {
+		if ((rc = write_long(info, wp, data)) != 0) {
 			return (rc);
 		}
-		wp += 2;
+		wp += 4;
 	}

 	/*
 	 * handle word aligned part
 	 */
-	while (cnt >= 2) {
-		/* data = *((vushort*)src); */
-		data = *((ushort*)src);
-		if ((rc = write_word(info, wp, data)) != 0) {
+	while (cnt >= 4) {
+		data = *((ulong*)src);
+		if ((rc = write_long(info, wp, data)) != 0) {
 			return (rc);
 		}
-		src += 2;
-		wp  += 2;
-		cnt -= 2;
+		src += 4;
+		wp  += 4;
+		cnt -= 4;
 	}

 	if (cnt == 0) return ERR_OK;
@@ -362,13 +354,13 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
 	 * handle unaligned tail bytes
 	 */
 	data = 0;
-	for (i=0, cp=wp; i<2 && cnt>0; ++i, ++cp) {
-		data = (data >> 8) | (*src++ << 8);
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data >> 8) | (*src++ << 24);
 		--cnt;
 	}
-	for (; i<2; ++i, ++cp) {
-		data = (data >> 8) | (*(uchar *)cp << 8);
+	for (; i<4; ++i, ++cp) {
+		data = (data >> 8) | (*(uchar *)cp << 24);
 	}

-	return write_word(info, wp, data);
+	return write_long(info, wp, data);
 }
--- a/board/csb226/u-boot.lds
+++ b/board/csb226/u-boot.lds
@@ -44,16 +44,12 @@ SECTIONS
 	. = ALIGN(4);
 	.got : { *(.got) }

-   __u_boot_cmd_start = .;
-   .u_boot_cmd : { *(.u_boot_cmd) }
-   __u_boot_cmd_end = .;
-
-	armboot_end_data = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;

 	. = ALIGN(4);
-	bss_start = .;
+	__bss_start = .;
 	.bss : { *(.bss) }
-	bss_end = .;
-
-	armboot_end = .;
+	_end = .;
 }
--- a/board/dnp1110/u-boot.lds
+++ b/board/dnp1110/u-boot.lds
@@ -44,16 +44,12 @@ SECTIONS
 	. = ALIGN(4);
 	.got : { *(.got) }

-
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
-
-
-	armboot_end_data = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;

 	. = ALIGN(4);
+	__bss_start = .;
 	.bss : { *(.bss) }
-
-	armboot_end = .;
+	_end = .;
 }
--- a/board/eltec/bab7xx/bab7xx.c
+++ b/board/eltec/bab7xx/bab7xx.c
@@ -37,17 +37,18 @@
 */
 ulong bab7xx_get_bus_freq (void)
 {
-    /*
-     * The GPIO Port 1 on BAB7xx reflects the bus speed.
-     */
-    volatile struct GPIO *gpio = (struct GPIO *)(CFG_ISA_IO + CFG_NS87308_GPIO_BASE);
+	/*
+	 * The GPIO Port 1 on BAB7xx reflects the bus speed.
+	 */
+	volatile struct GPIO *gpio =
+		(struct GPIO *) (CFG_ISA_IO + CFG_NS87308_GPIO_BASE);

-    unsigned char data = gpio->dta1;
+	unsigned char data = gpio->dta1;

-    if (data & 0x02)
-	return 66666666;
+	if (data & 0x02)
+		return 66666666;

-    return 83333333;
+	return 83333333;
 }

 /*---------------------------------------------------------------------------*/
@@ -57,24 +58,26 @@ ulong bab7xx_get_bus_freq (void)
 */
 ulong bab7xx_get_gclk_freq (void)
 {
-    static const int pllratio_to_factor[] = {
-	00, 75, 70, 00, 20, 65, 100, 45, 30, 55, 40, 50, 80, 60, 35, 00,
-    };
+	static const int pllratio_to_factor[] = {
+		00, 75, 70, 00, 20, 65, 100, 45, 30, 55, 40, 50, 80, 60, 35,
+			00,
+	};

-    return pllratio_to_factor[get_hid1 () >> 28] * (bab7xx_get_bus_freq() / 10);
+	return pllratio_to_factor[get_hid1 () >> 28] *
+		(bab7xx_get_bus_freq () / 10);
 }

 /*----------------------------------------------------------------------------*/

 int checkcpu (void)
 {
-    uint pvr  = get_pvr();
+	uint pvr = get_pvr ();

-    printf ("MPC7xx V%d.%d",(pvr >> 8) & 0xFF, pvr & 0xFF);
-    printf (" at %ld / %ld MHz\n",  bab7xx_get_gclk_freq()/1000000,
-	    bab7xx_get_bus_freq()/1000000);
+	printf ("MPC7xx V%d.%d", (pvr >> 8) & 0xFF, pvr & 0xFF);
+	printf (" at %ld / %ld MHz\n", bab7xx_get_gclk_freq () / 1000000,
+		bab7xx_get_bus_freq () / 1000000);

-    return (0);
+	return (0);
 }

 /* ------------------------------------------------------------------------- */
@@ -82,20 +85,20 @@ int checkcpu (void)
 int checkboard (void)
 {
 #ifdef CFG_ADDRESS_MAP_A
-    puts ("Board: ELTEC BAB7xx PReP\n");
+	puts ("Board: ELTEC BAB7xx PReP\n");
 #else
-    puts ("Board: ELTEC BAB7xx CHRP\n");
+	puts ("Board: ELTEC BAB7xx CHRP\n");
 #endif
-    return (0);
+	return (0);
 }

 /* ------------------------------------------------------------------------- */

 int checkflash (void)
 {
-    /* TODO: XXX XXX XXX */
-    printf ("2 MB ## Test not implemented yet ##\n");
-    return (0);
+	/* TODO: XXX XXX XXX */
+	printf ("2 MB ## Test not implemented yet ##\n");
+	return (0);
 }

 /* ------------------------------------------------------------------------- */
@@ -103,77 +106,75 @@ int checkflash (void)

 static unsigned int mpc106_read_cfg_dword (unsigned int reg)
 {
-    unsigned int reg_addr = MPC106_REG | (reg & 0xFFFFFFFC);
+	unsigned int reg_addr = MPC106_REG | (reg & 0xFFFFFFFC);

-    out32r(MPC106_REG_ADDR, reg_addr);
+	out32r (MPC106_REG_ADDR, reg_addr);

-    return (in32r(MPC106_REG_DATA | (reg & 0x3)));
+	return (in32r (MPC106_REG_DATA | (reg & 0x3)));
 }

 /* ------------------------------------------------------------------------- */

 long int dram_size (int board_type)
 {
-    /* No actual initialisation to do - done when setting up
-     * PICRs MCCRs ME/SARs etc in ram_init.S.
-     */
+	/* No actual initialisation to do - done when setting up
+	 * PICRs MCCRs ME/SARs etc in ram_init.S.
+	 */

-    register unsigned long i, msar1, mear1, memSize;
+	register unsigned long i, msar1, mear1, memSize;

 #if defined(CFG_MEMTEST)
-    register unsigned long reg;
+	register unsigned long reg;

-    printf("Testing DRAM\n");
+	printf ("Testing DRAM\n");

-    /* write each mem addr with it's address */
-    for (reg = CFG_MEMTEST_START; reg < CFG_MEMTEST_END; reg+=4)
-    *reg = reg;
+	/* write each mem addr with it's address */
+	for (reg = CFG_MEMTEST_START; reg < CFG_MEMTEST_END; reg += 4)
+		*reg = reg;

-    for (reg = CFG_MEMTEST_START; reg < CFG_MEMTEST_END; reg+=4)
-    {
-	if (*reg != reg)
-	    return -1;
-    }
+	for (reg = CFG_MEMTEST_START; reg < CFG_MEMTEST_END; reg += 4) {
+		if (*reg != reg)
+			return -1;
+	}
 #endif

-    /*
-    * Since MPC106 memory controller chip has already been set to
-    * control all memory, just read and interpret its memory boundery register.
-    */
-    memSize = 0;
-    msar1 = mpc106_read_cfg_dword(MPC106_MSAR1);
-    mear1 = mpc106_read_cfg_dword(MPC106_MEAR1);
-    i     = mpc106_read_cfg_dword(MPC106_MBER) & 0xf;
+	/*
+	 * Since MPC106 memory controller chip has already been set to
+	 * control all memory, just read and interpret its memory boundery register.
+	 */
+	memSize = 0;
+	msar1 = mpc106_read_cfg_dword (MPC106_MSAR1);
+	mear1 = mpc106_read_cfg_dword (MPC106_MEAR1);
+	i = mpc106_read_cfg_dword (MPC106_MBER) & 0xf;

-    do
-    {
-	if (i & 0x01)   /* is bank enabled ? */
-	    memSize += (mear1 & 0xff) - (msar1 & 0xff) + 1;
-	msar1 >>= 8;
-	mear1 >>= 8;
-	i     >>= 1;
-    } while (i);
+	do {
+		if (i & 0x01)	/* is bank enabled ? */
+			memSize += (mear1 & 0xff) - (msar1 & 0xff) + 1;
+		msar1 >>= 8;
+		mear1 >>= 8;
+		i >>= 1;
+	} while (i);

-    return (memSize * 0x100000);
+	return (memSize * 0x100000);
 }

 /* ------------------------------------------------------------------------- */

-long int initdram(int board_type)
+long int initdram (int board_type)
 {
-    return dram_size(board_type);
+	return dram_size (board_type);
 }

 /* ------------------------------------------------------------------------- */

 void after_reloc (ulong dest_addr)
 {
-    DECLARE_GLOBAL_DATA_PTR;
+	DECLARE_GLOBAL_DATA_PTR;

-    /*
-     * Jump to the main U-Boot board init code
-     */
-    board_init_r((gd_t *)gd, dest_addr);
+	/*
+	 * Jump to the main U-Boot board init code
+	 */
+	board_init_r ((gd_t *) gd, dest_addr);
 }

 /* ------------------------------------------------------------------------- */
@@ -182,14 +183,13 @@ void after_reloc (ulong dest_addr)
 * do_reset is done here because in this case it is board specific, since the
 * 7xx CPUs can only be reset by external HW (the RTC in this case).
 */
-void
-do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
+void do_reset (cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
 {
 #if defined(CONFIG_RTC_MK48T59)
-    /* trigger watchdog immediately */
-    rtc_set_watchdog(1, RTC_WD_RB_16TH);
+	/* trigger watchdog immediately */
+	rtc_set_watchdog (1, RTC_WD_RB_16TH);
 #else
-    #error "You must define the macro CONFIG_RTC_MK48T59."
+#error "You must define the macro CONFIG_RTC_MK48T59."
 #endif
 }

@@ -200,16 +200,16 @@ do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
 * Since the 7xx CPUs don't have an internal watchdog, this function is
 * board specific.  We use the RTC here.
 */
-void watchdog_reset(void)
+void watchdog_reset (void)
 {
 #if defined(CONFIG_RTC_MK48T59)
-    /* we use a 32 sec watchdog timer */
-    rtc_set_watchdog(8, RTC_WD_RB_4);
+	/* we use a 32 sec watchdog timer */
+	rtc_set_watchdog (8, RTC_WD_RB_4);
 #else
-    #error "You must define the macro CONFIG_RTC_MK48T59."
+#error "You must define the macro CONFIG_RTC_MK48T59."
 #endif
 }
-#endif    /* CONFIG_WATCHDOG */
+#endif /* CONFIG_WATCHDOG */

 /* ------------------------------------------------------------------------- */

@@ -218,29 +218,28 @@ extern GraphicDevice smi;

 void video_get_info_str (int line_number, char *info)
 {
-    /* init video info strings for graphic console */
-    switch (line_number)
-    {
-    case 1:
-	sprintf (info," MPC7xx V%d.%d at %ld / %ld MHz",
-	    (get_pvr() >> 8) & 0xFF,
-	    get_pvr() & 0xFF,
-	    bab7xx_get_gclk_freq()/1000000,
-	    bab7xx_get_bus_freq()/1000000);
-	return;
-    case 2:
-	sprintf (info, " ELTEC BAB7xx with %ld MB DRAM and %ld MB FLASH",
-	    dram_size(0)/0x100000,
-	    flash_init()/0x100000);
-	return;
-    case 3:
-	sprintf (info, " %s", smi.modeIdent);
-	return;
-    }
+	/* init video info strings for graphic console */
+	switch (line_number) {
+	case 1:
+		sprintf (info, " MPC7xx V%d.%d at %ld / %ld MHz",
+			 (get_pvr () >> 8) & 0xFF,
+			 get_pvr () & 0xFF,
+			 bab7xx_get_gclk_freq () / 1000000,
+			 bab7xx_get_bus_freq () / 1000000);
+		return;
+	case 2:
+		sprintf (info,
+			 " ELTEC BAB7xx with %ld MB DRAM and %ld MB FLASH",
+			 dram_size (0) / 0x100000, flash_init () / 0x100000);
+		return;
+	case 3:
+		sprintf (info, " %s", smi.modeIdent);
+		return;
+	}

-    /* no more info lines */
-    *info = 0;
-    return;
+	/* no more info lines */
+	*info = 0;
+	return;
 }
 #endif

--- a/board/eltec/elppc/misc.c
+++ b/board/eltec/elppc/misc.c
@@ -31,32 +31,32 @@
 /* imports  */
 extern char console_buffer[CFG_CBSIZE];
 extern int l2_cache_enable (int l2control);
-extern int eepro100_write_eeprom (struct eth_device* dev, int location,
-		 int addr_len, unsigned short data);
-extern int read_eeprom (struct eth_device* dev, int location, int addr_len);
+extern int eepro100_write_eeprom (struct eth_device *dev, int location,
+				  int addr_len, unsigned short data);
+extern int read_eeprom (struct eth_device *dev, int location, int addr_len);

 /*----------------------------------------------------------------------------*/
 /*
 * read/write to nvram is only byte access
 */
-void *nvram_read(void *dest, const long src, size_t count)
+void *nvram_read (void *dest, const long src, size_t count)
 {
-    uchar *d = (uchar *) dest;
-    uchar *s = (uchar *) (CFG_ENV_MAP_ADRS + src);
+	uchar *d = (uchar *) dest;
+	uchar *s = (uchar *) (CFG_ENV_MAP_ADRS + src);

-    while (count--)
-	*d++ = *s++;
+	while (count--)
+		*d++ = *s++;

-    return dest;
+	return dest;
 }

-void nvram_write(long dest, const void *src, size_t count)
+void nvram_write (long dest, const void *src, size_t count)
 {
-    uchar *d = (uchar *) (CFG_ENV_MAP_ADRS + dest);
-    uchar *s = (uchar *) src;
+	uchar *d = (uchar *) (CFG_ENV_MAP_ADRS + dest);
+	uchar *s = (uchar *) src;

-    while (count--)
-	*d++ = *s++;
+	while (count--)
+		*d++ = *s++;
 }

 /*----------------------------------------------------------------------------*/
@@ -67,192 +67,199 @@ void nvram_write(long dest, const void *src, size_t count)
 */
 int misc_init_r (void)
 {
-    revinfo eerev;
-    u_char *ptr;
-    u_int  i, l, initSrom, copyNv;
-    char buf[256];
-    char hex[23] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 0, 0,
-		     0, 0, 0, 0, 10, 11, 12, 13, 14, 15 };
+	revinfo eerev;
+	u_char *ptr;
+	u_int i, l, initSrom, copyNv;
+	char buf[256];
+	char hex[23] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 0, 0,
+		0, 0, 0, 0, 10, 11, 12, 13, 14, 15
+	};

-    /* Clock setting for MPC107 i2c */
-    mpc107_i2c_init (MPC107_EUMB_ADDR, 0x2b);
+	/* Clock setting for MPC107 i2c */
+	mpc107_i2c_init (MPC107_EUMB_ADDR, 0x2b);

-    /* Reset the EPIC */
-    out32r (MPC107_EUMB_GCR, 0xa0000000);
-    while (in32r (MPC107_EUMB_GCR) & 0x80000000);   /* Wait for reset to complete */
-    out32r (MPC107_EUMB_GCR, 0x20000000);           /* Put into into mixed mode */
-    while (in32r (MPC107_EUMB_IACKR) != 0xff);      /* Clear all pending interrupts */
+	/* Reset the EPIC */
+	out32r (MPC107_EUMB_GCR, 0xa0000000);
+	while (in32r (MPC107_EUMB_GCR) & 0x80000000);	/* Wait for reset to complete */
+	out32r (MPC107_EUMB_GCR, 0x20000000);	/* Put into into mixed mode */
+	while (in32r (MPC107_EUMB_IACKR) != 0xff);	/* Clear all pending interrupts */

-    /*
-     * Check/Remake revision info
-     */
-    initSrom = 0;
-    copyNv   = 0;
+	/*
+	 * Check/Remake revision info
+	 */
+	initSrom = 0;
+	copyNv = 0;

-    /* read out current revision srom contens */
-    mpc107_srom_load (0x0000, (u_char*)&eerev, sizeof(revinfo),
-		SECOND_DEVICE, FIRST_BLOCK);
+	/* read out current revision srom contens */
+	mpc107_srom_load (0x0000, (u_char *) & eerev, sizeof (revinfo),
+			  SECOND_DEVICE, FIRST_BLOCK);

-    /* read out current nvram shadow image */
-    nvram_read (buf, CFG_NV_SROM_COPY_ADDR, CFG_SROM_SIZE);
+	/* read out current nvram shadow image */
+	nvram_read (buf, CFG_NV_SROM_COPY_ADDR, CFG_SROM_SIZE);

-    if (strcmp (eerev.magic, "ELTEC") != 0)
-    {
-	/* srom is not initialized -> create a default revision info */
-	for (i = 0, ptr = (u_char *)&eerev; i < sizeof(revinfo); i++)
-	    *ptr++ = 0x00;
-	strcpy(eerev.magic, "ELTEC");
-	eerev.revrev[0] = 1;
-	eerev.revrev[1] = 0;
-	eerev.size = 0x00E0;
-	eerev.category[0] = 0x01;
+	if (strcmp (eerev.magic, "ELTEC") != 0) {
+		/* srom is not initialized -> create a default revision info */
+		for (i = 0, ptr = (u_char *) & eerev; i < sizeof (revinfo);
+		     i++)
+			*ptr++ = 0x00;
+		strcpy (eerev.magic, "ELTEC");
+		eerev.revrev[0] = 1;
+		eerev.revrev[1] = 0;
+		eerev.size = 0x00E0;
+		eerev.category[0] = 0x01;

-	/* node id from dead e128 as default */
-	eerev.etheraddr[0] = 0x00;
-	eerev.etheraddr[1] = 0x00;
-	eerev.etheraddr[2] = 0x5B;
-	eerev.etheraddr[3] = 0x00;
-	eerev.etheraddr[4] = 0x2E;
-	eerev.etheraddr[5] = 0x4D;
+		/* node id from dead e128 as default */
+		eerev.etheraddr[0] = 0x00;
+		eerev.etheraddr[1] = 0x00;
+		eerev.etheraddr[2] = 0x5B;
+		eerev.etheraddr[3] = 0x00;
+		eerev.etheraddr[4] = 0x2E;
+		eerev.etheraddr[5] = 0x4D;

-	/* cache config word for ELPPC */
-	*(int*)&eerev.res[0] = 0;
+		/* cache config word for ELPPC */
+		*(int *) &eerev.res[0] = 0;

-	initSrom = 1;  /* force dialog */
-	copyNv   = 1;  /* copy to nvram */
-    }
-
-    if ((copyNv == 0) &&   (el_srom_checksum((u_char*)&eerev, CFG_SROM_SIZE) !=
-		el_srom_checksum((u_char*)buf, CFG_SROM_SIZE)))
-    {
-	printf ("Invalid revision info copy in nvram !\n");
-	printf ("Press key:\n  <c> to copy current revision info to nvram.\n");
-	printf ("  <r> to reenter revision info.\n");
-	printf ("=> ");
-	if (0 != readline (NULL))
-	{
-	    switch ((char)toupper(console_buffer[0]))
-	    {
-	    case 'C':
-		copyNv = 1;
-		break;
-	    case 'R':
-		copyNv = 1;
-		initSrom = 1;
-		break;
-	    }
-	}
-    }
-
-    if (initSrom)
-    {
-	memcpy (buf, &eerev.revision[0][0], 14);     /* save all revision info */
-	printf ("Enter revision number (0-9): %c  ", eerev.revision[0][0]);
-	if (0 != readline (NULL))
-	{
-	    eerev.revision[0][0] = (char)toupper(console_buffer[0]);
-	    memcpy (&eerev.revision[1][0], buf, 12); /* shift rest of rev info */
+		initSrom = 1;	/* force dialog */
+		copyNv = 1;	/* copy to nvram */
 	}

-	printf ("Enter revision character (A-Z): %c  ", eerev.revision[0][1]);
-	if (1 == readline (NULL))
-	{
-	    eerev.revision[0][1] = (char)toupper(console_buffer[0]);
+	if ((copyNv == 0)
+	    && (el_srom_checksum ((u_char *) & eerev, CFG_SROM_SIZE) !=
+		el_srom_checksum ((u_char *) buf, CFG_SROM_SIZE))) {
+		printf ("Invalid revision info copy in nvram !\n");
+		printf ("Press key:\n  <c> to copy current revision info to nvram.\n");
+		printf ("  <r> to reenter revision info.\n");
+		printf ("=> ");
+		if (0 != readline (NULL)) {
+			switch ((char) toupper (console_buffer[0])) {
+			case 'C':
+				copyNv = 1;
+				break;
+			case 'R':
+				copyNv = 1;
+				initSrom = 1;
+				break;
+			}
+		}
 	}

-	printf ("Enter board name (V-XXXX-XXXX): %s  ", (char *)&eerev.board);
-	if (11 == readline (NULL))
-	{
-	    for (i=0; i<11; i++)
-		eerev.board[i] =  (char)toupper(console_buffer[i]);
-	    eerev.board[11] = '\0';
+	if (initSrom) {
+		memcpy (buf, &eerev.revision[0][0], 14);	/* save all revision info */
+		printf ("Enter revision number (0-9): %c  ",
+			eerev.revision[0][0]);
+		if (0 != readline (NULL)) {
+			eerev.revision[0][0] =
+				(char) toupper (console_buffer[0]);
+			memcpy (&eerev.revision[1][0], buf, 12);	/* shift rest of rev info */
+		}
+
+		printf ("Enter revision character (A-Z): %c  ",
+			eerev.revision[0][1]);
+		if (1 == readline (NULL)) {
+			eerev.revision[0][1] =
+				(char) toupper (console_buffer[0]);
+		}
+
+		printf ("Enter board name (V-XXXX-XXXX): %s  ",
+			(char *) &eerev.board);
+		if (11 == readline (NULL)) {
+			for (i = 0; i < 11; i++)
+				eerev.board[i] =
+					(char) toupper (console_buffer[i]);
+			eerev.board[11] = '\0';
+		}
+
+		printf ("Enter serial number: %s ", (char *) &eerev.serial);
+		if (6 == readline (NULL)) {
+			for (i = 0; i < 6; i++)
+				eerev.serial[i] = console_buffer[i];
+			eerev.serial[6] = '\0';
+		}
+
+		printf ("Enter ether node ID with leading zero (HEX): %02x%02x%02x%02x%02x%02x  ", eerev.etheraddr[0], eerev.etheraddr[1], eerev.etheraddr[2], eerev.etheraddr[3], eerev.etheraddr[4], eerev.etheraddr[5]);
+		if (12 == readline (NULL)) {
+			for (i = 0; i < 12; i += 2)
+				eerev.etheraddr[i >> 1] =
+					(char) (16 *
+						hex[toupper
+						    (console_buffer[i]) -
+						    '0'] +
+						hex[toupper
+						    (console_buffer[i + 1]) -
+						    '0']);
+		}
+
+		l = strlen ((char *) &eerev.text);
+		printf ("Add to text section (max 64 chr): %s ",
+			(char *) &eerev.text);
+		if (0 != readline (NULL)) {
+			for (i = l; i < 63; i++)
+				eerev.text[i] = console_buffer[i - l];
+			eerev.text[63] = '\0';
+		}
+
+		/* prepare network eeprom */
+		memset (buf, 0, 128);
+
+		buf[0] = eerev.etheraddr[1];
+		buf[1] = eerev.etheraddr[0];
+		buf[2] = eerev.etheraddr[3];
+		buf[3] = eerev.etheraddr[2];
+		buf[4] = eerev.etheraddr[5];
+		buf[5] = eerev.etheraddr[4];
+
+		*(unsigned short *) &buf[20] = 0x48B2;
+		*(unsigned short *) &buf[22] = 0x0004;
+		*(unsigned short *) &buf[24] = 0x1433;
+
+		printf ("\nSRom:  Writing i82559 info ........ ");
+		if (eepro100_srom_store ((unsigned short *) buf) == -1)
+			printf ("FAILED\n");
+		else
+			printf ("OK\n");
+
+		/* update CRC */
+		eerev.crc =
+			el_srom_checksum ((u_char *) eerev.board, eerev.size);
+
+		/* write new values */
+		printf ("\nSRom:  Writing revision info ...... ");
+		if (mpc107_srom_store
+		    ((BLOCK_SIZE - sizeof (revinfo)), (u_char *) & eerev,
+		     sizeof (revinfo), SECOND_DEVICE, FIRST_BLOCK) == -1)
+			printf ("FAILED\n\n");
+		else
+			printf ("OK\n\n");
+
+		/* write new values as shadow image to nvram */
+		nvram_write (CFG_NV_SROM_COPY_ADDR, (void *) &eerev,
+			     CFG_SROM_SIZE);
+
 	}

-	printf ("Enter serial number: %s ", (char *)&eerev.serial );
-	if (6 == readline (NULL))
-	{
-	    for (i=0; i<6; i++)
-		eerev.serial[i] = console_buffer[i];
-	    eerev.serial[6] = '\0';
-	}
+	/*if (initSrom) */
+	/* copy current values as shadow image to nvram */
+	if (initSrom == 0 && copyNv == 1)
+		nvram_write (CFG_NV_SROM_COPY_ADDR, (void *) &eerev,
+			     CFG_SROM_SIZE);

-	printf ("Enter ether node ID with leading zero (HEX): %02x%02x%02x%02x%02x%02x  ",
-	    eerev.etheraddr[0], eerev.etheraddr[1],
-	    eerev.etheraddr[2], eerev.etheraddr[3],
-	    eerev.etheraddr[4], eerev.etheraddr[5]);
-	if (12 == readline (NULL))
-	{
-	    for (i=0; i<12; i+=2)
-	    eerev.etheraddr[i>>1] = (char)(16*hex[toupper(console_buffer[i])-'0'] +
-			       hex[toupper(console_buffer[i+1])-'0']);
-	}
+	/* update environment */
+	sprintf (buf, "%02x:%02x:%02x:%02x:%02x:%02x",
+		 eerev.etheraddr[0], eerev.etheraddr[1],
+		 eerev.etheraddr[2], eerev.etheraddr[3],
+		 eerev.etheraddr[4], eerev.etheraddr[5]);
+	setenv ("ethaddr", buf);

-	l = strlen ((char *)&eerev.text);
-	printf("Add to text section (max 64 chr): %s ", (char *)&eerev.text );
-	if (0 != readline (NULL))
-	{
-	    for (i = l; i<63; i++)
-		eerev.text[i] = console_buffer[i-l];
-	    eerev.text[63] = '\0';
-	}
+	/* set serial console as default */
+	if ((ptr = getenv ("console")) == NULL)
+		setenv ("console", "serial");

-	/* prepare network eeprom */
-	memset (buf, 0, 128);
+	/* print actual board identification */
+	printf ("Ident: %s  Ser %s  Rev %c%c\n",
+		eerev.board, (char *) &eerev.serial,
+		eerev.revision[0][0], eerev.revision[0][1]);

-	buf[0] = eerev.etheraddr[1];
-	buf[1] = eerev.etheraddr[0];
-	buf[2] = eerev.etheraddr[3];
-	buf[3] = eerev.etheraddr[2];
-	buf[4] = eerev.etheraddr[5];
-	buf[5] = eerev.etheraddr[4];
-
-	*(unsigned short *)&buf[20] = 0x48B2;
-	*(unsigned short *)&buf[22] = 0x0004;
-	*(unsigned short *)&buf[24] = 0x1433;
-
-	printf("\nSRom:  Writing i82559 info ........ ");
-	if (eepro100_srom_store ((unsigned short *)buf) == -1)
-	    printf("FAILED\n");
-	else
-	    printf("OK\n");
-
-	/* update CRC */
-	eerev.crc = el_srom_checksum((u_char *)eerev.board, eerev.size);
-
-	/* write new values */
-	printf("\nSRom:  Writing revision info ...... ");
-	if (mpc107_srom_store((BLOCK_SIZE-sizeof(revinfo)), (u_char *)&eerev,
-			    sizeof(revinfo), SECOND_DEVICE, FIRST_BLOCK) == -1)
-	    printf("FAILED\n\n");
-	else
-	    printf("OK\n\n");
-
-	/* write new values as shadow image to nvram */
-	nvram_write (CFG_NV_SROM_COPY_ADDR, (void *)&eerev, CFG_SROM_SIZE);
-
-    } /*if (initSrom) */
-
-    /* copy current values as shadow image to nvram */
-    if (initSrom == 0 && copyNv == 1)
-	nvram_write (CFG_NV_SROM_COPY_ADDR, (void *)&eerev, CFG_SROM_SIZE);
-
-    /* update environment */
-    sprintf (buf, "%02x:%02x:%02x:%02x:%02x:%02x",
-	    eerev.etheraddr[0], eerev.etheraddr[1],
-	    eerev.etheraddr[2], eerev.etheraddr[3],
-	    eerev.etheraddr[4], eerev.etheraddr[5]);
-    setenv ("ethaddr", buf);
-
-    /* set serial console as default */
-    if ((ptr = getenv ("console")) == NULL)
-	setenv ("console", "serial");
-
-    /* print actual board identification */
-    printf("Ident: %s  Ser %s  Rev %c%c\n",
-	    eerev.board, (char *)&eerev.serial,
-	    eerev.revision[0][0], eerev.revision[0][1]);
-
-    return (0);
+	return (0);
 }

 /*----------------------------------------------------------------------------*/
--- a/board/eltec/mhpc/mhpc.c
+++ b/board/eltec/mhpc/mhpc.c
@@ -38,19 +38,19 @@
 /* imports from common/main.c */
 extern char console_buffer[CFG_CBSIZE];

-extern void eeprom_init  (void);
-extern int  eeprom_read  (unsigned dev_addr, unsigned offset,
-			  unsigned char *buffer, unsigned cnt);
-extern int  eeprom_write (unsigned dev_addr, unsigned offset,
-			  unsigned char *buffer, unsigned cnt);
+extern void eeprom_init (void);
+extern int eeprom_read (unsigned dev_addr, unsigned offset,
+			unsigned char *buffer, unsigned cnt);
+extern int eeprom_write (unsigned dev_addr, unsigned offset,
+			 unsigned char *buffer, unsigned cnt);

 /* globals */
-void *video_hw_init(void);
-void video_set_lut (unsigned int index,     /* color number */
-		    unsigned char r,        /* red */
-		    unsigned char g,        /* green */
-		    unsigned char b         /* blue */
-		    );
+void *video_hw_init (void);
+void video_set_lut (unsigned int index,	/* color number */
+		    unsigned char r,	/* red */
+		    unsigned char g,	/* green */
+		    unsigned char b	/* blue */
+	);

 GraphicDevice gdev;

@@ -60,79 +60,78 @@ static void video_test_image (void);
 static void video_default_lut (unsigned int clut_type);

 /* revision info foer MHPC EEPROM offset 480 */
-typedef struct  {
-    char    board[12];      /* 000 - Board Revision information */
-    char    sensor;         /* 012 - Sensor Type information */
-    char    serial[8];      /* 013 - Board serial number */
-    char    etheraddr[6];   /* 021 - Ethernet node addresse */
-    char    revision[2];    /* 027 - Revision code */
-    char    option[3];      /* 029 - resevered for options */
+typedef struct {
+	char board[12];		/* 000 - Board Revision information */
+	char sensor;		/* 012 - Sensor Type information */
+	char serial[8];		/* 013 - Board serial number */
+	char etheraddr[6];	/* 021 - Ethernet node addresse */
+	char revision[2];	/* 027 - Revision code */
+	char option[3];		/* 029 - resevered for options */
 } revinfo;

 /* ------------------------------------------------------------------------- */

-static const unsigned int sdram_table[] =
-{
-    /* read single beat cycle */
-    0xef0efc04, 0x0e2dac04, 0x01ba5c04, 0x1ff5fc00,
-    0xfffffc05, 0xeffafc34, 0x0ff0bc34, 0x1ff57c35,
+static const unsigned int sdram_table[] = {
+	/* read single beat cycle */
+	0xef0efc04, 0x0e2dac04, 0x01ba5c04, 0x1ff5fc00,
+	0xfffffc05, 0xeffafc34, 0x0ff0bc34, 0x1ff57c35,

-    /* read burst cycle */
-    0xef0efc04, 0x0e3dac04, 0x10ff5c04, 0xf0fffc00,
-    0xf0fffc00, 0xf1fffc00, 0xfffffc00, 0xfffffc05,
-    0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
-    0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+	/* read burst cycle */
+	0xef0efc04, 0x0e3dac04, 0x10ff5c04, 0xf0fffc00,
+	0xf0fffc00, 0xf1fffc00, 0xfffffc00, 0xfffffc05,
+	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,

-    /* write single beat cycle */
-    0xef0efc04, 0x0e29ac00, 0x01b25c04, 0x1ff5fc05,
-    0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+	/* write single beat cycle */
+	0xef0efc04, 0x0e29ac00, 0x01b25c04, 0x1ff5fc05,
+	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,

-    /* write burst cycle */
-    0xef0ef804, 0x0e39a000, 0x10f75000, 0xf0fff440,
-    0xf0fffc40, 0xf1fffc04, 0xfffffc05, 0xfffffc04,
-    0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
-    0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+	/* write burst cycle */
+	0xef0ef804, 0x0e39a000, 0x10f75000, 0xf0fff440,
+	0xf0fffc40, 0xf1fffc04, 0xfffffc05, 0xfffffc04,
+	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,

-    /* periodic timer expired */
-    0xeffebc84, 0x1ffd7c04, 0xfffffc04, 0xfffffc84,
-    0xeffebc04, 0x1ffd7c04, 0xfffffc04, 0xfffffc05,
-    0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+	/* periodic timer expired */
+	0xeffebc84, 0x1ffd7c04, 0xfffffc04, 0xfffffc84,
+	0xeffebc04, 0x1ffd7c04, 0xfffffc04, 0xfffffc05,
+	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,

-    /* exception */
-    0xfffffc04, 0xfffffc05, 0xfffffc04, 0xfffffc04
+	/* exception */
+	0xfffffc04, 0xfffffc05, 0xfffffc04, 0xfffffc04
 };

 /* ------------------------------------------------------------------------- */

 int board_early_init_f (void)
 {
-    volatile immap_t  *im = (immap_t *)CFG_IMMR;
-    volatile cpm8xx_t *cp = &(im->im_cpm);
-    volatile iop8xx_t *ip = (iop8xx_t *)&(im->im_ioport);
+	volatile immap_t *im = (immap_t *) CFG_IMMR;
+	volatile cpm8xx_t *cp = &(im->im_cpm);
+	volatile iop8xx_t *ip = (iop8xx_t *) & (im->im_ioport);

-    /* reset the port A s.a. cpm-routines */
-    ip->iop_padat = 0x0000;
-    ip->iop_papar = 0x0000;
-    ip->iop_padir = 0x0800;
-    ip->iop_paodr = 0x0000;
+	/* reset the port A s.a. cpm-routines */
+	ip->iop_padat = 0x0000;
+	ip->iop_papar = 0x0000;
+	ip->iop_padir = 0x0800;
+	ip->iop_paodr = 0x0000;

-    /* reset the port B for digital and LCD output */
-    cp->cp_pbdat  = 0x0300;
-    cp->cp_pbpar  = 0x5001;
-    cp->cp_pbdir  = 0x5301;
-    cp->cp_pbodr  = 0x0000;
+	/* reset the port B for digital and LCD output */
+	cp->cp_pbdat = 0x0300;
+	cp->cp_pbpar = 0x5001;
+	cp->cp_pbdir = 0x5301;
+	cp->cp_pbodr = 0x0000;

-    /* reset the port C configured for SMC1 serial port and aqc. control */
-    ip->iop_pcdat = 0x0800;
-    ip->iop_pcpar = 0x0000;
-    ip->iop_pcdir = 0x0e30;
-    ip->iop_pcso  = 0x0000;
+	/* reset the port C configured for SMC1 serial port and aqc. control */
+	ip->iop_pcdat = 0x0800;
+	ip->iop_pcpar = 0x0000;
+	ip->iop_pcdir = 0x0e30;
+	ip->iop_pcso = 0x0000;

-    /* Config port D for LCD output */
-    ip->iop_pdpar = 0x1fff;
-    ip->iop_pddir = 0x1fff;
+	/* Config port D for LCD output */
+	ip->iop_pdpar = 0x1fff;
+	ip->iop_pddir = 0x1fff;

-    return (0);
+	return (0);
 }

 /* ------------------------------------------------------------------------- */
@@ -142,322 +141,327 @@ int board_early_init_f (void)
 */
 int checkboard (void)
 {
-    puts ("Board: ELTEC miniHiperCam\n");
-    return(0);
+	puts ("Board: ELTEC miniHiperCam\n");
+	return (0);
 }

 /* ------------------------------------------------------------------------- */

-int misc_init_r(void)
+int misc_init_r (void)
 {
-    revinfo  mhpcRevInfo;
-    char     nid[32];
-    char     *mhpcSensorTypes[] = { "OMNIVISON OV7610/7620 color",
-				    "OMNIVISON OV7110 b&w", NULL };
-    char     hex[23] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 0, 0,
-			 0, 0, 0, 0, 10, 11, 12, 13, 14, 15 };
-    int      i;
+	revinfo mhpcRevInfo;
+	char nid[32];
+	char *mhpcSensorTypes[] = { "OMNIVISON OV7610/7620 color",
+		"OMNIVISON OV7110 b&w", NULL
+	};
+	char hex[23] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 0, 0,
+		0, 0, 0, 0, 10, 11, 12, 13, 14, 15
+	};
+	int i;

-    /* check revision data */
-    eeprom_read (CFG_I2C_EEPROM_ADDR, 480, (char*)&mhpcRevInfo, 32);
+	/* check revision data */
+	eeprom_read (CFG_I2C_EEPROM_ADDR, 480, (char *) &mhpcRevInfo, 32);

-    if (strncmp((char *)&mhpcRevInfo.board[2], "MHPC", 4) != 0)
-    {
-    printf ("Enter revision number (0-9): %c  ", mhpcRevInfo.revision[0]);
-    if (0 != readline (NULL))
-    {
-	mhpcRevInfo.revision[0] = (char)toupper(console_buffer[0]);
-    }
+	if (strncmp ((char *) &mhpcRevInfo.board[2], "MHPC", 4) != 0) {
+		printf ("Enter revision number (0-9): %c  ",
+			mhpcRevInfo.revision[0]);
+		if (0 != readline (NULL)) {
+			mhpcRevInfo.revision[0] =
+				(char) toupper (console_buffer[0]);
+		}

-    printf ("Enter revision character (A-Z): %c  ", mhpcRevInfo.revision[1]);
-    if (1 == readline (NULL))
-    {
-	mhpcRevInfo.revision[1] = (char)toupper(console_buffer[0]);
-    }
+		printf ("Enter revision character (A-Z): %c  ",
+			mhpcRevInfo.revision[1]);
+		if (1 == readline (NULL)) {
+			mhpcRevInfo.revision[1] =
+				(char) toupper (console_buffer[0]);
+		}

-    printf("Enter board name (V-XXXX-XXXX): %s  ", (char *)&mhpcRevInfo.board);
-    if (11 == readline (NULL))
-    {
-	for (i=0; i<11; i++)
-	{
-	    mhpcRevInfo.board[i] =  (char)toupper(console_buffer[i]);
-	    mhpcRevInfo.board[11] = '\0';
+		printf ("Enter board name (V-XXXX-XXXX): %s  ",
+			(char *) &mhpcRevInfo.board);
+		if (11 == readline (NULL)) {
+			for (i = 0; i < 11; i++) {
+				mhpcRevInfo.board[i] =
+					(char) toupper (console_buffer[i]);
+				mhpcRevInfo.board[11] = '\0';
+			}
+		}
+
+		printf ("Supported sensor types:\n");
+		i = 0;
+		do {
+			printf ("\n    \'%d\' : %s\n", i, mhpcSensorTypes[i]);
+		} while (mhpcSensorTypes[++i] != NULL);
+
+		do {
+			printf ("\nEnter sensor number (0-255): %d  ",
+				(int) mhpcRevInfo.sensor);
+			if (0 != readline (NULL)) {
+				mhpcRevInfo.sensor =
+					(unsigned char)
+					simple_strtoul (console_buffer, NULL,
+							10);
+			}
+		} while (mhpcRevInfo.sensor >= i);
+
+		printf ("Enter serial number: %s ",
+			(char *) &mhpcRevInfo.serial);
+		if (6 == readline (NULL)) {
+			for (i = 0; i < 6; i++) {
+				mhpcRevInfo.serial[i] = console_buffer[i];
+			}
+			mhpcRevInfo.serial[6] = '\0';
+		}
+
+		printf ("Enter ether node ID with leading zero (HEX): %02x%02x%02x%02x%02x%02x  ", mhpcRevInfo.etheraddr[0], mhpcRevInfo.etheraddr[1], mhpcRevInfo.etheraddr[2], mhpcRevInfo.etheraddr[3], mhpcRevInfo.etheraddr[4], mhpcRevInfo.etheraddr[5]);
+		if (12 == readline (NULL)) {
+			for (i = 0; i < 12; i += 2) {
+				mhpcRevInfo.etheraddr[i >> 1] =
+					(char) (16 *
+						hex[toupper
+						    (console_buffer[i]) -
+						    '0'] +
+						hex[toupper
+						    (console_buffer[i + 1]) -
+						    '0']);
+			}
+		}
+
+		/* setup new revision data */
+		eeprom_write (CFG_I2C_EEPROM_ADDR, 480, (char *) &mhpcRevInfo,
+			      32);
 	}
-    }

-    printf("Supported sensor types:\n");
-    i=0;
-    do
-    {
-	printf("\n    \'%d\' : %s\n", i, mhpcSensorTypes[i]);
-    } while ( mhpcSensorTypes[++i] != NULL );
+	/* set environment */
+	sprintf (nid, "%02x:%02x:%02x:%02x:%02x:%02x",
+		 mhpcRevInfo.etheraddr[0], mhpcRevInfo.etheraddr[1],
+		 mhpcRevInfo.etheraddr[2], mhpcRevInfo.etheraddr[3],
+		 mhpcRevInfo.etheraddr[4], mhpcRevInfo.etheraddr[5]);
+	setenv ("ethaddr", nid);

-    do
-    {
-	printf("\nEnter sensor number (0-255): %d  ", (int)mhpcRevInfo.sensor );
-	if (0 != readline (NULL))
-	{
-	mhpcRevInfo.sensor = (unsigned char)simple_strtoul(console_buffer, NULL, 10);
-	}
-    } while ( mhpcRevInfo.sensor >= i );
+	/* print actual board identification */
+	printf ("Ident: %s %s Ser %s Rev %c%c\n",
+		mhpcRevInfo.board,
+		(mhpcRevInfo.sensor == 0 ? "color" : "b&w"),
+		(char *) &mhpcRevInfo.serial, mhpcRevInfo.revision[0],
+		mhpcRevInfo.revision[1]);

-    printf("Enter serial number: %s ", (char *)&mhpcRevInfo.serial );
-    if (6 == readline (NULL))
-    {
-	for (i=0; i<6; i++)
-	{
-	mhpcRevInfo.serial[i] = console_buffer[i];
-	}
-	mhpcRevInfo.serial[6] = '\0';
-    }
-
-    printf("Enter ether node ID with leading zero (HEX): %02x%02x%02x%02x%02x%02x  ",
-	      mhpcRevInfo.etheraddr[0], mhpcRevInfo.etheraddr[1],
-	      mhpcRevInfo.etheraddr[2], mhpcRevInfo.etheraddr[3],
-	      mhpcRevInfo.etheraddr[4], mhpcRevInfo.etheraddr[5]  );
-    if (12 == readline (NULL))
-    {
-	for (i=0; i<12; i+=2)
-	{
-	mhpcRevInfo.etheraddr[i>>1] = (char)(16*hex[toupper(console_buffer[i])-'0'] +
-			     hex[toupper(console_buffer[i+1])-'0']);
-	}
-    }
-
-    /* setup new revision data */
-    eeprom_write (CFG_I2C_EEPROM_ADDR, 480, (char*)&mhpcRevInfo, 32);
-    }
-
-    /* set environment */
-    sprintf( nid, "%02x:%02x:%02x:%02x:%02x:%02x",
-		  mhpcRevInfo.etheraddr[0], mhpcRevInfo.etheraddr[1],
-		  mhpcRevInfo.etheraddr[2], mhpcRevInfo.etheraddr[3],
-		  mhpcRevInfo.etheraddr[4], mhpcRevInfo.etheraddr[5]);
-    setenv("ethaddr", nid);
-
-    /* print actual board identification */
-    printf("Ident: %s %s Ser %s Rev %c%c\n",
-	    mhpcRevInfo.board, (mhpcRevInfo.sensor==0?"color":"b&w"),
-	    (char *)&mhpcRevInfo.serial,
-	    mhpcRevInfo.revision[0], mhpcRevInfo.revision[1]);
-
-    return (0);
+	return (0);
 }

 /* ------------------------------------------------------------------------- */

 long int initdram (int board_type)
 {
-    volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
-    volatile memctl8xx_t *memctl = &immap->im_memctl;
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;

-    upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
+	upmconfig (UPMA, (uint *) sdram_table,
+		   sizeof (sdram_table) / sizeof (uint));

-    memctl->memc_mamr  = CFG_MAMR & (~(MAMR_PTAE)); /* no refresh yet */
-    memctl->memc_mbmr  = MBMR_GPL_B4DIS;	/* should this be mamr? - NTL */
-    memctl->memc_mptpr = MPTPR_PTP_DIV64;
-    memctl->memc_mar   = 0x00008800;
+	memctl->memc_mamr = CFG_MAMR & (~(MAMR_PTAE));	/* no refresh yet */
+	memctl->memc_mbmr = MBMR_GPL_B4DIS;	/* should this be mamr? - NTL */
+	memctl->memc_mptpr = MPTPR_PTP_DIV64;
+	memctl->memc_mar = 0x00008800;

-    /*
-     * Map controller SDRAM bank 0
-     */
-    memctl->memc_or1 = CFG_OR1_PRELIM;
-    memctl->memc_br1 = CFG_BR1_PRELIM;
-    udelay(200);
+	/*
+	 * Map controller SDRAM bank 0
+	 */
+	memctl->memc_or1 = CFG_OR1_PRELIM;
+	memctl->memc_br1 = CFG_BR1_PRELIM;
+	udelay (200);

-    /*
-     * Map controller SDRAM bank 1
-     */
-    memctl->memc_or2 = CFG_OR2;
-    memctl->memc_br2 = CFG_BR2;
+	/*
+	 * Map controller SDRAM bank 1
+	 */
+	memctl->memc_or2 = CFG_OR2;
+	memctl->memc_br2 = CFG_BR2;

-    /*
-     * Perform SDRAM initializsation sequence
-     */
-    memctl->memc_mcr  = 0x80002105;    /* SDRAM bank 0 */
-    udelay(1);
-    memctl->memc_mcr  = 0x80002730;    /* SDRAM bank 0 - execute twice */
-    udelay(1);
-    memctl->memc_mamr |= MAMR_PTAE;    /* enable refresh */
+	/*
+	 * Perform SDRAM initializsation sequence
+	 */
+	memctl->memc_mcr = 0x80002105;	/* SDRAM bank 0 */
+	udelay (1);
+	memctl->memc_mcr = 0x80002730;	/* SDRAM bank 0 - execute twice */
+	udelay (1);
+	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */

-    udelay(10000);
+	udelay (10000);

-    /* leave place for framebuffers */
-    return (SDRAM_MAX_SIZE-SDRAM_RES_SIZE);
+	/* leave place for framebuffers */
+	return (SDRAM_MAX_SIZE - SDRAM_RES_SIZE);
 }

 /* ------------------------------------------------------------------------- */

 static void video_circle (char *center, int radius, int color, int pitch)
 {
-    int x,y,d,dE,dSE;
+	int x, y, d, dE, dSE;

-    x   = 0;
-    y   = radius;
-    d   = 1-radius;
-    dE  = 3;
-    dSE = -2*radius+5;
+	x = 0;
+	y = radius;
+	d = 1 - radius;
+	dE = 3;
+	dSE = -2 * radius + 5;

-    *(center+x+y*pitch) = color;
-    *(center+y+x*pitch) = color;
-    *(center+y-x*pitch) = color;
-    *(center+x-y*pitch) = color;
-    *(center-x-y*pitch) = color;
-    *(center-y-x*pitch) = color;
-    *(center-y+x*pitch) = color;
-    *(center-x+y*pitch) = color;
-    while(y>x)
-    {
-	if (d<0)
-	{
-	    d   += dE;
-	    dE  += 2;
-	    dSE += 2;
-	    x++;
+	*(center + x + y * pitch) = color;
+	*(center + y + x * pitch) = color;
+	*(center + y - x * pitch) = color;
+	*(center + x - y * pitch) = color;
+	*(center - x - y * pitch) = color;
+	*(center - y - x * pitch) = color;
+	*(center - y + x * pitch) = color;
+	*(center - x + y * pitch) = color;
+	while (y > x) {
+		if (d < 0) {
+			d += dE;
+			dE += 2;
+			dSE += 2;
+			x++;
+		} else {
+			d += dSE;
+			dE += 2;
+			dSE += 4;
+			x++;
+			y--;
+		}
+		*(center + x + y * pitch) = color;
+		*(center + y + x * pitch) = color;
+		*(center + y - x * pitch) = color;
+		*(center + x - y * pitch) = color;
+		*(center - x - y * pitch) = color;
+		*(center - y - x * pitch) = color;
+		*(center - y + x * pitch) = color;
+		*(center - x + y * pitch) = color;
 	}
-	else
-	{
-	    d   += dSE;
-	    dE  += 2;
-	    dSE += 4;
-	    x++;
-	    y--;
-	}
-	*(center+x+y*pitch) = color;
-	*(center+y+x*pitch) = color;
-	*(center+y-x*pitch) = color;
-	*(center+x-y*pitch) = color;
-	*(center-x-y*pitch) = color;
-	*(center-y-x*pitch) = color;
-	*(center-y+x*pitch) = color;
-	*(center-x+y*pitch) = color;
-    }
 }

 /* ------------------------------------------------------------------------- */

-static void video_test_image(void)
+static void video_test_image (void)
 {
-    char *di;
-    int i, n;
+	char *di;
+	int i, n;

-    /* draw raster */
-    for (i=0; i<LCD_VIDEO_ROWS; i+=32)
-    {
-	memset((char*)(LCD_VIDEO_ADDR+i*LCD_VIDEO_COLS), LCD_VIDEO_FG, LCD_VIDEO_COLS);
-	for (n=i+1;n<i+32;n++)
-	    memset((char*)(LCD_VIDEO_ADDR+n*LCD_VIDEO_COLS), LCD_VIDEO_BG, LCD_VIDEO_COLS);
-    }
-
-    for (i=0; i<LCD_VIDEO_COLS; i+=32)
-    {
-	for (n=0; n<LCD_VIDEO_ROWS; n++)
-	    *(char*)(LCD_VIDEO_ADDR+n*LCD_VIDEO_COLS+i) = LCD_VIDEO_FG;
-    }
-
-    /* draw gray bar */
-    di = (char *)(LCD_VIDEO_ADDR + (LCD_VIDEO_COLS-256)/64*32 + 97*LCD_VIDEO_COLS);
-    for (n=0; n<63; n++)
-    {
-	for (i=0; i<256; i++)
-	{
-	    *di++ = (char)i;
-	    *(di+LCD_VIDEO_COLS*64) = (i&1)*255;
+	/* draw raster */
+	for (i = 0; i < LCD_VIDEO_ROWS; i += 32) {
+		memset ((char *) (LCD_VIDEO_ADDR + i * LCD_VIDEO_COLS),
+			LCD_VIDEO_FG, LCD_VIDEO_COLS);
+		for (n = i + 1; n < i + 32; n++)
+			memset ((char *) (LCD_VIDEO_ADDR +
+					  n * LCD_VIDEO_COLS), LCD_VIDEO_BG,
+				LCD_VIDEO_COLS);
 	}
-	di += LCD_VIDEO_COLS-256;
-    }

-    video_circle ((char*)LCD_VIDEO_ADDR+LCD_VIDEO_COLS/2+LCD_VIDEO_ROWS/2*LCD_VIDEO_COLS,
-		  LCD_VIDEO_ROWS/2,LCD_VIDEO_FG, LCD_VIDEO_COLS);
+	for (i = 0; i < LCD_VIDEO_COLS; i += 32) {
+		for (n = 0; n < LCD_VIDEO_ROWS; n++)
+			*(char *) (LCD_VIDEO_ADDR + n * LCD_VIDEO_COLS + i) =
+				LCD_VIDEO_FG;
+	}
+
+	/* draw gray bar */
+	di = (char *) (LCD_VIDEO_ADDR + (LCD_VIDEO_COLS - 256) / 64 * 32 +
+		       97 * LCD_VIDEO_COLS);
+	for (n = 0; n < 63; n++) {
+		for (i = 0; i < 256; i++) {
+			*di++ = (char) i;
+			*(di + LCD_VIDEO_COLS * 64) = (i & 1) * 255;
+		}
+		di += LCD_VIDEO_COLS - 256;
+	}
+
+	video_circle ((char *) LCD_VIDEO_ADDR + LCD_VIDEO_COLS / 2 +
+		      LCD_VIDEO_ROWS / 2 * LCD_VIDEO_COLS, LCD_VIDEO_ROWS / 2,
+		      LCD_VIDEO_FG, LCD_VIDEO_COLS);
 }

 /* ------------------------------------------------------------------------- */

 static void video_default_lut (unsigned int clut_type)
 {
-    unsigned int i;
-    unsigned char RGB[] =
-	{
-	0x00, 0x00, 0x00,   /* black */
-	0x80, 0x80, 0x80,   /* gray */
-	0xff, 0x00, 0x00,   /* red */
-	0x00, 0xff, 0x00,   /* green */
-	0x00, 0x00, 0xff,   /* blue */
-	0x00, 0xff, 0xff,   /* cyan */
-	0xff, 0x00, 0xff,   /* magenta */
-	0xff, 0xff, 0x00,   /* yellow */
-	0x80, 0x00, 0x00,   /* dark red */
-	0x00, 0x80, 0x00,   /* dark green */
-	0x00, 0x00, 0x80,   /* dark blue */
-	0x00, 0x80, 0x80,   /* dark cyan */
-	0x80, 0x00, 0x80,   /* dark magenta */
-	0x80, 0x80, 0x00,   /* dark yellow */
-	0xc0, 0xc0, 0xc0,   /* light gray */
-	0xff, 0xff, 0xff,   /* white */
+	unsigned int i;
+	unsigned char RGB[] = {
+		0x00, 0x00, 0x00,	/* black */
+		0x80, 0x80, 0x80,	/* gray */
+		0xff, 0x00, 0x00,	/* red */
+		0x00, 0xff, 0x00,	/* green */
+		0x00, 0x00, 0xff,	/* blue */
+		0x00, 0xff, 0xff,	/* cyan */
+		0xff, 0x00, 0xff,	/* magenta */
+		0xff, 0xff, 0x00,	/* yellow */
+		0x80, 0x00, 0x00,	/* dark red */
+		0x00, 0x80, 0x00,	/* dark green */
+		0x00, 0x00, 0x80,	/* dark blue */
+		0x00, 0x80, 0x80,	/* dark cyan */
+		0x80, 0x00, 0x80,	/* dark magenta */
+		0x80, 0x80, 0x00,	/* dark yellow */
+		0xc0, 0xc0, 0xc0,	/* light gray */
+		0xff, 0xff, 0xff,	/* white */
 	};

-    switch (clut_type)
-    {
-    case 1:
-	for (i=0; i<240; i++)
-	    video_set_lut (i, i, i, i);
-	for (i=0; i<16; i++)
-	    video_set_lut (i+240, RGB[i*3], RGB[i*3+1], RGB[i*3+2]);
-	break;
-    default:
-	for (i=0; i<256; i++)
-	    video_set_lut (i, i, i, i);
-    }
+	switch (clut_type) {
+	case 1:
+		for (i = 0; i < 240; i++)
+			video_set_lut (i, i, i, i);
+		for (i = 0; i < 16; i++)
+			video_set_lut (i + 240, RGB[i * 3], RGB[i * 3 + 1],
+				       RGB[i * 3 + 2]);
+		break;
+	default:
+		for (i = 0; i < 256; i++)
+			video_set_lut (i, i, i, i);
+	}
 }

 /* ------------------------------------------------------------------------- */

 void *video_hw_init (void)
 {
-    unsigned int clut = 0;
-    unsigned char *penv;
-    immap_t *immr = (immap_t *) CFG_IMMR;
+	unsigned int clut = 0;
+	unsigned char *penv;
+	immap_t *immr = (immap_t *) CFG_IMMR;

-    /* enable video only on CLUT value */
-    if ((penv = getenv ("clut")) != NULL)
-	clut = (u_int)simple_strtoul (penv, NULL, 10);
-    else
-	return NULL;
+	/* enable video only on CLUT value */
+	if ((penv = getenv ("clut")) != NULL)
+		clut = (u_int) simple_strtoul (penv, NULL, 10);
+	else
+		return NULL;

-    /* disable graphic before write LCD regs. */
-    immr->im_lcd.lcd_lccr = 0x96000866;
+	/* disable graphic before write LCD regs. */
+	immr->im_lcd.lcd_lccr = 0x96000866;

-    /* config LCD regs. */
-    immr->im_lcd.lcd_lcfaa = LCD_VIDEO_ADDR;
-    immr->im_lcd.lcd_lchcr = 0x010a0093;
-    immr->im_lcd.lcd_lcvcr = 0x900f0024;
+	/* config LCD regs. */
+	immr->im_lcd.lcd_lcfaa = LCD_VIDEO_ADDR;
+	immr->im_lcd.lcd_lchcr = 0x010a0093;
+	immr->im_lcd.lcd_lcvcr = 0x900f0024;

-    printf ("Video: 640x480 8Bit Index Lut %s\n",
-	    (clut==1?"240/16 (gray/vga)":"256(gray)"));
+	printf ("Video: 640x480 8Bit Index Lut %s\n",
+		(clut == 1 ? "240/16 (gray/vga)" : "256(gray)"));

-    video_default_lut (clut);
+	video_default_lut (clut);

-    /* clear framebuffer */
-    memset ( (char*)(LCD_VIDEO_ADDR), LCD_VIDEO_BG, LCD_VIDEO_ROWS*LCD_VIDEO_COLS );
+	/* clear framebuffer */
+	memset ((char *) (LCD_VIDEO_ADDR), LCD_VIDEO_BG,
+		LCD_VIDEO_ROWS * LCD_VIDEO_COLS);

-    /* enable graphic */
-    immr->im_lcd.lcd_lccr = 0x96000867;
+	/* enable graphic */
+	immr->im_lcd.lcd_lccr = 0x96000867;

-    /* fill in Graphic Device */
-    gdev.frameAdrs = LCD_VIDEO_ADDR;
-    gdev.winSizeX = LCD_VIDEO_COLS;
-    gdev.winSizeY = LCD_VIDEO_ROWS;
-    gdev.gdfBytesPP = 1;
-    gdev.gdfIndex = GDF__8BIT_INDEX;
+	/* fill in Graphic Device */
+	gdev.frameAdrs = LCD_VIDEO_ADDR;
+	gdev.winSizeX = LCD_VIDEO_COLS;
+	gdev.winSizeY = LCD_VIDEO_ROWS;
+	gdev.gdfBytesPP = 1;
+	gdev.gdfIndex = GDF__8BIT_INDEX;

-    if (clut > 1)
-	/* return Graphic Device for console */
-	return (void *)&gdev;
-    else
-	/* just graphic enabled - draw something beautiful */
-	video_test_image();
+	if (clut > 1)
+		/* return Graphic Device for console */
+		return (void *) &gdev;
+	else
+		/* just graphic enabled - draw something beautiful */
+		video_test_image ();

-    return NULL;            /* this disabels cfb - console */
+	return NULL;		/* this disabels cfb - console */
 }

 /* ------------------------------------------------------------------------- */
@@ -465,13 +469,15 @@ void *video_hw_init (void)
 void video_set_lut (unsigned int index,
 		    unsigned char r, unsigned char g, unsigned char b)
 {
-    unsigned int lum;
-    unsigned short *pLut = (unsigned short *)(CFG_IMMR + 0x0e00);
+	unsigned int lum;
+	unsigned short *pLut = (unsigned short *) (CFG_IMMR + 0x0e00);

-    /* 16 bit lut values, 12 bit used, xxxx BBGG RRii iiii */
-    /* y = 0.299*R + 0.587*G + 0.114*B */
-    lum = (2990*r + 5870*g + 1140*b)/10000;
-    pLut[index] = ((b & 0xc0)<<4) | ((g & 0xc0)<<2) | (r & 0xc0) | (lum & 0x3f);
+	/* 16 bit lut values, 12 bit used, xxxx BBGG RRii iiii */
+	/* y = 0.299*R + 0.587*G + 0.114*B */
+	lum = (2990 * r + 5870 * g + 1140 * b) / 10000;
+	pLut[index] =
+		((b & 0xc0) << 4) | ((g & 0xc0) << 2) | (r & 0xc0) | (lum &
+								      0x3f);
 }

 /* ------------------------------------------------------------------------- */
--- a/board/ep7312/u-boot.lds
+++ b/board/ep7312/u-boot.lds
@@ -44,14 +44,12 @@ SECTIONS
 	. = ALIGN(4);
 	.got : { *(.got) }

-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
-
-	armboot_end_data = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;

 	. = ALIGN(4);
+	__bss_start = .;
 	.bss : { *(.bss) }
-
-	armboot_end = .;
+	_end = .;
 }
--- a/board/ep8260/ep8260.c
+++ b/board/ep8260/ep8260.c
@@ -190,21 +190,22 @@ const iop_conf_t iop_conf_tab[4][32] = {
 */
 int board_early_init_f (void)
 {
-    volatile t_ep_regs *regs = (t_ep_regs*)CFG_REGS_BASE;
-    volatile immap_t *immap  = (immap_t *)CFG_IMMR;
-    volatile memctl8260_t *memctl = &immap->im_memctl;
-    memctl->memc_br4 = CFG_BR4_PRELIM;
-    memctl->memc_or4 = CFG_OR4_PRELIM;
-    regs->bcsr1 = 0x62; /* to enable terminal on SMC1 */
-    regs->bcsr2 = 0x30;	/* enable NVRAM and writing FLASH */
-    return 0;
+	volatile t_ep_regs *regs = (t_ep_regs *) CFG_REGS_BASE;
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8260_t *memctl = &immap->im_memctl;
+
+	memctl->memc_br4 = CFG_BR4_PRELIM;
+	memctl->memc_or4 = CFG_OR4_PRELIM;
+	regs->bcsr1 = 0x62;	/* to enable terminal on SMC1 */
+	regs->bcsr2 = 0x30;	/* enable NVRAM and writing FLASH */
+	return 0;
 }

-void
-reset_phy(void)
+void reset_phy (void)
 {
-    volatile t_ep_regs *regs = (t_ep_regs*)CFG_REGS_BASE;
-    regs->bcsr4 = 0xC0;
+	volatile t_ep_regs *regs = (t_ep_regs *) CFG_REGS_BASE;
+
+	regs->bcsr4 = 0xC0;
 }

 /*
@@ -213,15 +214,21 @@ reset_phy(void)
 * Thats why its a static interpretation ...
 */

-int
-checkboard(void)
+int checkboard (void)
 {
-	volatile t_ep_regs *regs = (t_ep_regs*)CFG_REGS_BASE;
-	uint major=0, minor=0;
+	volatile t_ep_regs *regs = (t_ep_regs *) CFG_REGS_BASE;
+	uint major = 0, minor = 0;
+
 	switch (regs->bcsr0) {
-		case 0x02: major = 1; break;
-		case 0x03: major = 1; minor = 1; break;
-		default: break;
+	case 0x02:
+		major = 1;
+		break;
+	case 0x03:
+		major = 1;
+		minor = 1;
+		break;
+	default:
+		break;
 	}
 	printf ("Board: Embedded Planet EP8260, Revision %d.%d\n",
 		major, minor);
@@ -232,13 +239,13 @@ checkboard(void)
 /* ------------------------------------------------------------------------- */


-long int
-initdram(int board_type)
+long int initdram (int board_type)
 {
-	volatile immap_t *immap  = (immap_t *)CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
 	volatile memctl8260_t *memctl = &immap->im_memctl;
 	volatile uchar c = 0;
-	volatile uchar *ramaddr = (uchar *)(CFG_SDRAM_BASE) + 0x110;
+	volatile uchar *ramaddr = (uchar *) (CFG_SDRAM_BASE) + 0x110;
+
 /*
 	ulong psdmr = CFG_PSDMR;
 #ifdef CFG_LSDRAM
@@ -288,7 +295,7 @@ initdram(int board_type)
 #ifndef CFG_RAMBOOT
 #ifdef CFG_LSDRAM
 	size += CFG_SDRAM1_SIZE;
-	ramaddr = (uchar *)(CFG_SDRAM1_BASE) + 0x8c;
+	ramaddr = (uchar *) (CFG_SDRAM1_BASE) + 0x8c;
 	memctl->memc_lsrt = CFG_LSRT;

 	memctl->memc_lsdmr = (ulong) CFG_LSDMR | PSDMR_OP_PREA;
--- a/board/esteem192e/esteem192e.c
+++ b/board/esteem192e/esteem192e.c
@@ -113,7 +113,7 @@ long int initdram (int board_type)

 	memctl->memc_mptpr = 0x0200;	/* divide by 32 */

-	memctl->memc_mamr = 0x18003112;	/*CFG_MAMR_8COL; *//* 0x18005112 TODO: explain here */
+	memctl->memc_mamr = 0x18003112;	/*CFG_MAMR_8COL; */ /* 0x18005112 TODO: explain here */

 	upmconfig (UPMA, (uint *) sdram_table,
 		   sizeof (sdram_table) / sizeof (uint));
--- a/board/evb64260/ecctest.c
+++ b/board/evb64260/ecctest.c
@@ -1,91 +1,111 @@
+indent: Standard input:27: Warning:old style assignment ambiguity in "=*".  Assuming "= *"
+
 #ifdef ECC_TEST
-static inline void ecc_off(void)
+static inline void ecc_off (void)
 {
-	*(volatile int *)(INTERNAL_REG_BASE_ADDR+0x4b4) &= ~0x00200000;
+	*(volatile int *) (INTERNAL_REG_BASE_ADDR + 0x4b4) &= ~0x00200000;
 }

-static inline void ecc_on(void)
+static inline void ecc_on (void)
 {
-	*(volatile int *)(INTERNAL_REG_BASE_ADDR+0x4b4) |= 0x00200000;
+	*(volatile int *) (INTERNAL_REG_BASE_ADDR + 0x4b4) |= 0x00200000;
 }

-static int putshex(const char *buf, int len)
+static int putshex (const char *buf, int len)
 {
-    int i;
-    for (i=0;i<len;i++) {
-	printf("%02x", buf[i]);
-    }
-    return 0;
-}
+	int i;

-static int char_memcpy(void *d, const void *s, int len)
-{
-    int i;
-    char *cd=d;
-    const char *cs=s;
-    for(i=0;i<len;i++) {
-	*(cd++)=*(cs++);
-    }
-    return 0;
-}
-
-static int memory_test(char *buf)
-{
-    const char src[][16]={
-	{   0,   0,   0,   0,   0,   0,   0,   0,   0,   0,   0,   0,   0,   0,   0,   0},
-	{0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01},
-	{0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02},
-	{0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04},
-	{0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08},
-	{0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10},
-	{0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20},
-	{0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40},
-	{0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80},
-	{0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55},
-	{0xaa,0xaa,0xaa,0xaa,0xaa,0xaa,0xaa,0xaa,0xaa,0xaa,0xaa,0xaa,0xaa,0xaa,0xaa,0xaa},
-	{0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff}
-    };
-    const int foo[] = {0};
-    int i,j,a;
-
-    printf("\ntest @ %d %p\n", foo[0], buf);
-    for(i=0;i<12;i++) {
-	for(a=0;a<8;a++) {
-	    const char *s=src[i]+a;
-	    int align=(unsigned)(s)&0x7;
-	    /* ecc_off(); */
-	    memcpy(buf,s,8);
-	    /* ecc_on(); */
-	    putshex(s,8);
-	    if(memcmp(buf,s,8)) {
-		putc('\n');
-		putshex(buf,8);
-		printf(" [FAIL] (%p) align=%d\n", s, align);
-		for(j=0;j<8;j++) {
-		    s[j]==buf[j]?puts("  "):printf("%02x", (s[j])^(buf[j]));
-		}
-		putc('\n');
-	    } else {
-		printf(" [PASS] (%p) align=%d\n", s, align);
-	    }
-	    /* ecc_off(); */
-	    char_memcpy(buf,s,8);
-	    /* ecc_on(); */
-	    putshex(s,8);
-	    if(memcmp(buf,s,8)) {
-		putc('\n');
-		putshex(buf,8);
-		printf(" [FAIL] (%p) align=%d\n", s, align);
-		for(j=0;j<8;j++) {
-		    s[j]==buf[j]?puts("  "):printf("%02x", (s[j])^(buf[j]));
-		}
-		putc('\n');
-	    } else {
-		printf(" [PASS] (%p) align=%d\n", s, align);
-	    }
+	for (i = 0; i < len; i++) {
+		printf ("%02x", buf[i]);
 	}
-    }
+	return 0;
+}

-    return 0;
+static int char_memcpy (void *d, const void *s, int len)
+{
+	int i;
+	char *cd = d;
+	const char *cs = s;
+
+	for (i = 0; i < len; i++) {
+		*(cd++) = *(cs++);
+	}
+	return 0;
+}
+
+static int memory_test (char *buf)
+{
+	const char src[][16] = {
+		{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+		{0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
+		 0x01, 0x01, 0x01, 0x01, 0x01, 0x01},
+		{0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
+		 0x02, 0x02, 0x02, 0x02, 0x02, 0x02},
+		{0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04,
+		 0x04, 0x04, 0x04, 0x04, 0x04, 0x04},
+		{0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08,
+		 0x08, 0x08, 0x08, 0x08, 0x08, 0x08},
+		{0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+		 0x10, 0x10, 0x10, 0x10, 0x10, 0x10},
+		{0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+		 0x20, 0x20, 0x20, 0x20, 0x20, 0x20},
+		{0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40,
+		 0x40, 0x40, 0x40, 0x40, 0x40, 0x40},
+		{0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+		 0x80, 0x80, 0x80, 0x80, 0x80, 0x80},
+		{0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55,
+		 0x55, 0x55, 0x55, 0x55, 0x55, 0x55},
+		{0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
+		 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa},
+		{0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+	};
+	const int foo[] = { 0 };
+	int i, j, a;
+
+	printf ("\ntest @ %d %p\n", foo[0], buf);
+	for (i = 0; i < 12; i++) {
+		for (a = 0; a < 8; a++) {
+			const char *s = src[i] + a;
+			int align = (unsigned) (s) & 0x7;
+
+			/* ecc_off(); */
+			memcpy (buf, s, 8);
+			/* ecc_on(); */
+			putshex (s, 8);
+			if (memcmp (buf, s, 8)) {
+				putc ('\n');
+				putshex (buf, 8);
+				printf (" [FAIL] (%p) align=%d\n", s, align);
+				for (j = 0; j < 8; j++) {
+					s[j] == buf[j] ? puts ("  ") :
+						printf ("%02x",
+							(s[j]) ^ (buf[j]));
+				}
+				putc ('\n');
+			} else {
+				printf (" [PASS] (%p) align=%d\n", s, align);
+			}
+			/* ecc_off(); */
+			char_memcpy (buf, s, 8);
+			/* ecc_on(); */
+			putshex (s, 8);
+			if (memcmp (buf, s, 8)) {
+				putc ('\n');
+				putshex (buf, 8);
+				printf (" [FAIL] (%p) align=%d\n", s, align);
+				for (j = 0; j < 8; j++) {
+					s[j] == buf[j] ? puts ("  ") :
+						printf ("%02x",
+							(s[j]) ^ (buf[j]));
+				}
+				putc ('\n');
+			} else {
+				printf (" [PASS] (%p) align=%d\n", s, align);
+			}
+		}
+	}
+
+	return 0;
 }
 #endif
--- a/board/evb64260/eth_addrtbl.c
+++ b/board/evb64260/eth_addrtbl.c
@@ -13,66 +13,68 @@

 #ifdef CONFIG_GT_USE_MAC_HASH_TABLE

-static u32           addressTableHashMode[ GAL_ETH_DEVS ] = { 0, };
-static u32           addressTableHashSize[ GAL_ETH_DEVS ] = { 0, };
-static addrTblEntry *addressTableBase[     GAL_ETH_DEVS ] = { 0, };
-static void         *realAddrTableBase[    GAL_ETH_DEVS ] = { 0, };
+static u32 addressTableHashMode[GAL_ETH_DEVS] = { 0, };
+static u32 addressTableHashSize[GAL_ETH_DEVS] = { 0, };
+static addrTblEntry *addressTableBase[GAL_ETH_DEVS] = { 0, };
+static void *realAddrTableBase[GAL_ETH_DEVS] = { 0, };

-static const u32 hashLength[ 2 ] = {
-    (0x8000),             /* 8K * 4 entries */
-    (0x8000/16),          /* 512 * 4 entries */
+static const u32 hashLength[2] = {
+	(0x8000),		/* 8K * 4 entries */
+	(0x8000 / 16),		/* 512 * 4 entries */
 };

 /* Initialize the address table for a port, if needed */
-unsigned int initAddressTable( u32 port, u32 hashMode, u32 hashSizeSelector)
+unsigned int initAddressTable (u32 port, u32 hashMode, u32 hashSizeSelector)
 {
-    unsigned int tableBase;
+	unsigned int tableBase;

-    if( port < 0 || port >= GAL_ETH_DEVS ) {
-		printf("%s: Invalid port number %d\n", __FUNCTION__, port );
+	if (port < 0 || port >= GAL_ETH_DEVS) {
+		printf ("%s: Invalid port number %d\n", __FUNCTION__, port);
 		return 0;
 	}

 	if (hashMode > 1) {
-		printf("%s: Invalid Hash Mode %d\n", __FUNCTION__, port );
+		printf ("%s: Invalid Hash Mode %d\n", __FUNCTION__, port);
 		return 0;
 	}

-	if ( realAddrTableBase[port] &&
-		( addressTableHashSize[port] != hashSizeSelector )) {
+	if (realAddrTableBase[port] &&
+	    (addressTableHashSize[port] != hashSizeSelector)) {
 		/* we have been here before,
 		 * but now we want a different sized table
 		 */
-		free( realAddrTableBase[port] );
+		free (realAddrTableBase[port]);
 		realAddrTableBase[port] = 0;
 		addressTableBase[port] = 0;

 	}

-	tableBase = (unsigned int)addressTableBase[port];
+	tableBase = (unsigned int) addressTableBase[port];
 	/* we get called for every probe, so only do this once */
-	if ( !tableBase ) {
-	int bytes = hashLength[hashSizeSelector] * sizeof(addrTblEntry);
+	if (!tableBase) {
+		int bytes =
+			hashLength[hashSizeSelector] * sizeof (addrTblEntry);

-		tableBase = (unsigned int)realAddrTableBase[port] = malloc(bytes+64);
+		tableBase = (unsigned int) realAddrTableBase[port] =
+			malloc (bytes + 64);

-	    if(!tableBase)
-		{
-			printf("%s: alloc memory failed \n", __FUNCTION__);
+		if (!tableBase) {
+			printf ("%s: alloc memory failed \n", __FUNCTION__);
 			return 0;
 		}

-	/* align to octal byte */
-	    if(tableBase&63) tableBase=(tableBase+63) & ~63;
+		/* align to octal byte */
+		if (tableBase & 63)
+			tableBase = (tableBase + 63) & ~63;

-	addressTableHashMode[port] = hashMode;
-	    addressTableHashSize[port] = hashSizeSelector;
-	addressTableBase[port] = (addrTblEntry *)tableBase;
+		addressTableHashMode[port] = hashMode;
+		addressTableHashSize[port] = hashSizeSelector;
+		addressTableBase[port] = (addrTblEntry *) tableBase;

-	    memset((void *)tableBase,0,bytes);
+		memset ((void *) tableBase, 0, bytes);
 	}

-    return tableBase;
+	return tableBase;
 }

 /*
@@ -87,61 +89,61 @@ unsigned int initAddressTable( u32 port, u32 hashMode, u32 hashSizeSelector)
 * Outputs
 * return the calculated entry.
 */
-u32
-hashTableFunction( u32 macH, u32 macL, u32 HashSize, u32 hash_mode)
+u32 hashTableFunction (u32 macH, u32 macL, u32 HashSize, u32 hash_mode)
 {
-    u32 hashResult;
-    u32 addrH;
-    u32 addrL;
-    u32 addr0;
-    u32 addr1;
-    u32 addr2;
-    u32 addr3;
-    u32 addrHSwapped;
-    u32 addrLSwapped;
+	u32 hashResult;
+	u32 addrH;
+	u32 addrL;
+	u32 addr0;
+	u32 addr1;
+	u32 addr2;
+	u32 addr3;
+	u32 addrHSwapped;
+	u32 addrLSwapped;


-    addrH = NIBBLE_SWAPPING_16_BIT( macH );
-    addrL = NIBBLE_SWAPPING_32_BIT( macL );
+	addrH = NIBBLE_SWAPPING_16_BIT (macH);
+	addrL = NIBBLE_SWAPPING_32_BIT (macL);

-    addrHSwapped =   FLIP_4_BITS(  addrH        & 0xf )
-		 + ((FLIP_4_BITS( (addrH >>  4) & 0xf)) <<  4)
-		 + ((FLIP_4_BITS( (addrH >>  8) & 0xf)) <<  8)
-		 + ((FLIP_4_BITS( (addrH >> 12) & 0xf)) << 12);
+	addrHSwapped = FLIP_4_BITS (addrH & 0xf)
+		+ ((FLIP_4_BITS ((addrH >> 4) & 0xf)) << 4)
+		+ ((FLIP_4_BITS ((addrH >> 8) & 0xf)) << 8)
+		+ ((FLIP_4_BITS ((addrH >> 12) & 0xf)) << 12);

-    addrLSwapped =   FLIP_4_BITS(  addrL        & 0xf )
-		 + ((FLIP_4_BITS( (addrL >>  4) & 0xf)) <<  4)
-		 + ((FLIP_4_BITS( (addrL >>  8) & 0xf)) <<  8)
-		 + ((FLIP_4_BITS( (addrL >> 12) & 0xf)) << 12)
-		 + ((FLIP_4_BITS( (addrL >> 16) & 0xf)) << 16)
-		 + ((FLIP_4_BITS( (addrL >> 20) & 0xf)) << 20)
-		 + ((FLIP_4_BITS( (addrL >> 24) & 0xf)) << 24)
-		 + ((FLIP_4_BITS( (addrL >> 28) & 0xf)) << 28);
+	addrLSwapped = FLIP_4_BITS (addrL & 0xf)
+		+ ((FLIP_4_BITS ((addrL >> 4) & 0xf)) << 4)
+		+ ((FLIP_4_BITS ((addrL >> 8) & 0xf)) << 8)
+		+ ((FLIP_4_BITS ((addrL >> 12) & 0xf)) << 12)
+		+ ((FLIP_4_BITS ((addrL >> 16) & 0xf)) << 16)
+		+ ((FLIP_4_BITS ((addrL >> 20) & 0xf)) << 20)
+		+ ((FLIP_4_BITS ((addrL >> 24) & 0xf)) << 24)
+		+ ((FLIP_4_BITS ((addrL >> 28) & 0xf)) << 28);

-    addrH = addrHSwapped;
-    addrL = addrLSwapped;
+	addrH = addrHSwapped;
+	addrL = addrLSwapped;

-    if( hash_mode == 0 )  {
-	addr0 =  (addrL >>  2) & 0x03f;
-	addr1 =  (addrL        & 0x003) | ((addrL >> 8) & 0x7f) << 2;
-	addr2 =  (addrL >> 15) & 0x1ff;
-	addr3 = ((addrL >> 24) & 0x0ff) | ((addrH &  1)         << 8);
-    } else  {
-	addr0 = FLIP_6_BITS(    addrL        & 0x03f );
-	addr1 = FLIP_9_BITS(  ((addrL >>  6) & 0x1ff));
-	addr2 = FLIP_9_BITS(   (addrL >> 15) & 0x1ff);
-	addr3 = FLIP_9_BITS( (((addrL >> 24) & 0x0ff) | ((addrH & 0x1) << 8)));
-    }
+	if (hash_mode == 0) {
+		addr0 = (addrL >> 2) & 0x03f;
+		addr1 = (addrL & 0x003) | ((addrL >> 8) & 0x7f) << 2;
+		addr2 = (addrL >> 15) & 0x1ff;
+		addr3 = ((addrL >> 24) & 0x0ff) | ((addrH & 1) << 8);
+	} else {
+		addr0 = FLIP_6_BITS (addrL & 0x03f);
+		addr1 = FLIP_9_BITS (((addrL >> 6) & 0x1ff));
+		addr2 = FLIP_9_BITS ((addrL >> 15) & 0x1ff);
+		addr3 = FLIP_9_BITS ((((addrL >> 24) & 0x0ff) |
+				      ((addrH & 0x1) << 8)));
+	}

-    hashResult = (addr0 << 9) | (addr1 ^ addr2 ^ addr3);
+	hashResult = (addr0 << 9) | (addr1 ^ addr2 ^ addr3);

-    if( HashSize == _8K_TABLE )  {
-	hashResult = hashResult & 0xffff;
-    } else  {
-	hashResult = hashResult & 0x07ff;
-    }
+	if (HashSize == _8K_TABLE) {
+		hashResult = hashResult & 0xffff;
+	} else {
+		hashResult = hashResult & 0x07ff;
+	}

-    return( hashResult );
+	return (hashResult);
 }


@@ -160,66 +162,59 @@ hashTableFunction( u32 macH, u32 macL, u32 HashSize, u32 hash_mode)
 * TRUE if success.
 * FALSE if table full
 */
-int
-addAddressTableEntry(
-    u32           port,
-    u32           macH,
-    u32           macL,
-    u32           rd,
-    u32           skip         )
+int addAddressTableEntry (u32 port, u32 macH, u32 macL, u32 rd, u32 skip)
 {
-    addrTblEntry *entry;
-    u32           newHi;
-    u32           newLo;
-    u32           i;
+	addrTblEntry *entry;
+	u32 newHi;
+	u32 newLo;
+	u32 i;

-    newLo = (((macH >>  4) & 0xf) << 15)
-	  | (((macH >>  0) & 0xf) << 11)
-	  | (((macH >> 12) & 0xf) <<  7)
-	  | (((macH >>  8) & 0xf) <<  3)
-	  | (((macL >> 20) & 0x1) << 31)
-	  | (((macL >> 16) & 0xf) << 27)
-	  | (((macL >> 28) & 0xf) << 23)
-	  | (((macL >> 24) & 0xf) << 19)
-	  |   (skip << SKIP_BIT)  |  (rd << 2) | VALID;
+	newLo = (((macH >> 4) & 0xf) << 15)
+		| (((macH >> 0) & 0xf) << 11)
+		| (((macH >> 12) & 0xf) << 7)
+		| (((macH >> 8) & 0xf) << 3)
+		| (((macL >> 20) & 0x1) << 31)
+		| (((macL >> 16) & 0xf) << 27)
+		| (((macL >> 28) & 0xf) << 23)
+		| (((macL >> 24) & 0xf) << 19)
+		| (skip << SKIP_BIT) | (rd << 2) | VALID;

-    newHi = (((macL >>  4) & 0xf) << 15)
-	  | (((macL >>  0) & 0xf) << 11)
-	  | (((macL >> 12) & 0xf) <<  7)
-	  | (((macL >>  8) & 0xf) <<  3)
-	  | (((macL >> 21) & 0x7) <<  0);
+	newHi = (((macL >> 4) & 0xf) << 15)
+		| (((macL >> 0) & 0xf) << 11)
+		| (((macL >> 12) & 0xf) << 7)
+		| (((macL >> 8) & 0xf) << 3)
+		| (((macL >> 21) & 0x7) << 0);

-    /*
-     * Pick the appropriate table, start scanning for free/reusable
-     * entries at the index obtained by hashing the specified MAC address
-     */
-    entry  = addressTableBase[port];
-    entry += hashTableFunction( macH, macL, addressTableHashSize[port],
-					    addressTableHashMode[port]  );
-    for( i = 0;  i < HOP_NUMBER;  i++, entry++ )  {
-	if( !(entry->lo & VALID)   /*|| (entry->lo & SKIP)*/   )  {
-	    break;
-	} else  {                    /* if same address put in same position */
-	    if(   ((entry->lo & 0xfffffff8) == (newLo & 0xfffffff8))
-		&& (entry->hi               ==  newHi) )
-	    {
-		    break;
-	    }
+	/*
+	 * Pick the appropriate table, start scanning for free/reusable
+	 * entries at the index obtained by hashing the specified MAC address
+	 */
+	entry = addressTableBase[port];
+	entry += hashTableFunction (macH, macL, addressTableHashSize[port],
+				    addressTableHashMode[port]);
+	for (i = 0; i < HOP_NUMBER; i++, entry++) {
+		if (!(entry->lo & VALID) /*|| (entry->lo & SKIP) */ ) {
+			break;
+		} else {	/* if same address put in same position */
+			if (((entry->lo & 0xfffffff8) == (newLo & 0xfffffff8))
+			    && (entry->hi == newHi)) {
+				break;
+			}
+		}
 	}
-    }

-    if( i == HOP_NUMBER )  {
-	PRINTF( "addGT64260addressTableEntry: table section is full\n" );
-	return( FALSE );
-    }
+	if (i == HOP_NUMBER) {
+		PRINTF ("addGT64260addressTableEntry: table section is full\n");
+		return (FALSE);
+	}

-    /*
-     * Update the selected entry
-     */
-    entry->hi = newHi;
-    entry->lo = newLo;
-    DCACHE_FLUSH_N_SYNC( (u32)entry, MAC_ENTRY_SIZE );
-    return( TRUE );
+	/*
+	 * Update the selected entry
+	 */
+	entry->hi = newHi;
+	entry->lo = newLo;
+	DCACHE_FLUSH_N_SYNC ((u32) entry, MAC_ENTRY_SIZE);
+	return (TRUE);
 }

 #endif /* CONFIG_GT_USE_MAC_HASH_TABLE */
--- a/board/evb64260/pci.c
+++ b/board/evb64260/pci.c
--- a/board/evb64260/sdram_init.c
+++ b/board/evb64260/sdram_init.c
@@ -54,65 +54,64 @@ typedef struct sdram_info {
 	uchar tras_clocks;
 	uchar burst_len;
 	uchar banks, slot;
-	int size;	/* detected size, not from I2C but from dram_size() */
+	int size;		/* detected size, not from I2C but from dram_size() */
 } sdram_info_t;

 #ifdef DEBUG
-void dump_dimm_info(struct sdram_info *d)
+void dump_dimm_info (struct sdram_info *d)
 {
-    static const char *ecc_legend[]={""," Parity"," ECC"};
-    printf("dimm%s %sDRAM: %dMibytes:\n",
-	    ecc_legend[d->ecc],
-	    d->registered?"R":"",
-	    (d->size>>20));
-    printf("  drb=%d tpar=%d tras=%d burstlen=%d banks=%d slot=%d\n",
-	    d->drb_size, d->tpar, d->tras_clocks, d->burst_len,
-	    d->banks, d->slot);
+	static const char *ecc_legend[] = { "", " Parity", " ECC" };
+
+	printf ("dimm%s %sDRAM: %dMibytes:\n",
+		ecc_legend[d->ecc],
+		d->registered ? "R" : "", (d->size >> 20));
+	printf ("  drb=%d tpar=%d tras=%d burstlen=%d banks=%d slot=%d\n",
+		d->drb_size, d->tpar, d->tras_clocks, d->burst_len,
+		d->banks, d->slot);
 }
 #endif

 static int
-memory_map_bank(unsigned int bankNo,
-		unsigned int bankBase,
-		unsigned int bankLength)
+memory_map_bank (unsigned int bankNo,
+		 unsigned int bankBase, unsigned int bankLength)
 {
 #ifdef DEBUG
 	if (bankLength > 0) {
-		printf("mapping bank %d at %08x - %08x\n",
-		       bankNo, bankBase, bankBase + bankLength - 1);
+		printf ("mapping bank %d at %08x - %08x\n",
+			bankNo, bankBase, bankBase + bankLength - 1);
 	} else {
-		printf("unmapping bank %d\n", bankNo);
+		printf ("unmapping bank %d\n", bankNo);
 	}
 #endif

-	memoryMapBank(bankNo, bankBase, bankLength);
+	memoryMapBank (bankNo, bankBase, bankLength);

 	return 0;
 }

 #ifdef MAP_PCI
 static int
-memory_map_bank_pci(unsigned int bankNo,
-		unsigned int bankBase,
-		unsigned int bankLength)
+memory_map_bank_pci (unsigned int bankNo,
+		     unsigned int bankBase, unsigned int bankLength)
 {
 	PCI_HOST host;
-	for (host=PCI_HOST0;host<=PCI_HOST1;host++) {
-		const int features=
+
+	for (host = PCI_HOST0; host <= PCI_HOST1; host++) {
+		const int features =
 			PREFETCH_ENABLE |
 			DELAYED_READ_ENABLE |
 			AGGRESSIVE_PREFETCH |
 			READ_LINE_AGGRESSIVE_PREFETCH |
 			READ_MULTI_AGGRESSIVE_PREFETCH |
-			MAX_BURST_4 |
-			PCI_NO_SWAP;
+			MAX_BURST_4 | PCI_NO_SWAP;

-		pciMapMemoryBank(host, bankNo, bankBase, bankLength);
+		pciMapMemoryBank (host, bankNo, bankBase, bankLength);

-		pciSetRegionSnoopMode(host, bankNo, PCI_SNOOP_WB, bankBase,
-				bankLength);
+		pciSetRegionSnoopMode (host, bankNo, PCI_SNOOP_WB, bankBase,
+				       bankLength);

-		pciSetRegionFeatures(host, bankNo, features, bankBase, bankLength);
+		pciSetRegionFeatures (host, bankNo, features, bankBase,
+				      bankLength);
 	}
 	return 0;
 }
@@ -128,8 +127,7 @@ memory_map_bank_pci(unsigned int bankNo,
 * translate ns.ns/10 coding of SPD timing values
 * into 10 ps unit values
 */
-static inline unsigned short
-NS10to10PS(unsigned char spd_byte)
+static inline unsigned short NS10to10PS (unsigned char spd_byte)
 {
 	unsigned short ns, ns10;

@@ -138,37 +136,35 @@ NS10to10PS(unsigned char spd_byte)
 	/* isolate lower nibble */
 	ns10 = (spd_byte & 0x0F);

-	return(ns*100 + ns10*10);
+	return (ns * 100 + ns10 * 10);
 }

 /*
 * translate ns coding of SPD timing values
 * into 10 ps unit values
 */
-static inline unsigned short
-NSto10PS(unsigned char spd_byte)
+static inline unsigned short NSto10PS (unsigned char spd_byte)
 {
-	return(spd_byte*100);
+	return (spd_byte * 100);
 }

 #ifdef CONFIG_ZUMA_V2
-static int
-check_dimm(uchar slot, sdram_info_t *info)
+static int check_dimm (uchar slot, sdram_info_t * info)
 {
 	/* assume 2 dimms, 2 banks each 256M - we dont have an
 	 * dimm i2c so rely on the detection routines later */

-	memset(info, 0, sizeof(*info));
+	memset (info, 0, sizeof (*info));

 	info->slot = slot;
 	info->banks = 2;	/* Detect later */
-	    info->registered = 0;
+	info->registered = 0;
 	info->drb_size = 32;	/* 16 - 256MBit, 32 - 512MBit
 				   but doesn't matter, both do same
 				   thing in setup_sdram() */
-	    info->tpar = 3;
-	    info->tras_clocks = 5;
-	    info->burst_len = 4;
+	info->tpar = 3;
+	info->tras_clocks = 5;
+	info->burst_len = 4;
 #ifdef CONFIG_ECC
 	info->ecc = 0;		/* Detect later */
 #endif /* CONFIG_ECC */
@@ -177,10 +173,9 @@ check_dimm(uchar slot, sdram_info_t *info)

 #elif defined(CONFIG_P3G4)

-static int
-check_dimm(uchar slot, sdram_info_t *info)
+static int check_dimm (uchar slot, sdram_info_t * info)
 {
-	memset(info, 0, sizeof(*info));
+	memset (info, 0, sizeof (*info));

 	if (slot)
 		return 0;
@@ -198,12 +193,11 @@ check_dimm(uchar slot, sdram_info_t *info)
 	return 0;
 }

-#else /* ! CONFIG_ZUMA_V2 && ! CONFIG_P3G4*/
+#else  /* ! CONFIG_ZUMA_V2 && ! CONFIG_P3G4 */

 /* This code reads the SPD chip on the sdram and populates
 * the array which is passed in with the relevant information */
-static int
-check_dimm(uchar slot, sdram_info_t *info)
+static int check_dimm (uchar slot, sdram_info_t * info)
 {
 	DECLARE_GLOBAL_DATA_PTR;
 	uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR;
@@ -215,32 +209,32 @@ check_dimm(uchar slot, sdram_info_t *info)

 	get_clocks ();

-	tmemclk = 1000000000 / (gd->bus_clk / 100);  /* in 10 ps units */
+	tmemclk = 1000000000 / (gd->bus_clk / 100);	/* in 10 ps units */

 #ifdef CONFIG_EVB64260_750CX
 	if (0 != slot) {
-		printf("check_dimm: The EVB-64260-750CX only has 1 DIMM,");
-		printf("            called with slot=%d insetad!\n", slot);
+		printf ("check_dimm: The EVB-64260-750CX only has 1 DIMM,");
+		printf ("            called with slot=%d insetad!\n", slot);
 		return 0;
 	}
 #endif
-	DP(puts("before i2c read\n"));
+	DP (puts ("before i2c read\n"));

-	ret = i2c_read(addr, 0, 128, data, 0);
+	ret = i2c_read (addr, 0, 128, data, 0);

-	DP(puts("after i2c read\n"));
+	DP (puts ("after i2c read\n"));

 	/* zero all the values */
-	memset(info, 0, sizeof(*info));
+	memset (info, 0, sizeof (*info));

 	if (ret) {
-		DP(printf("No DIMM in slot %d [err = %x]\n", slot, ret));
+		DP (printf ("No DIMM in slot %d [err = %x]\n", slot, ret));
 		return 0;
 	}

 	/* first, do some sanity checks */
 	if (data[2] != 0x4) {
-		printf("Not SDRAM in slot %d\n", slot);
+		printf ("Not SDRAM in slot %d\n", slot);
 		return 0;
 	}

@@ -251,7 +245,8 @@ check_dimm(uchar slot, sdram_info_t *info)
 	sdram_banks = data[17];
 	width = data[13] & 0x7f;

-	DP(printf("sdram_banks: %d, banks: %d\n", sdram_banks, info->banks));
+	DP (printf
+	    ("sdram_banks: %d, banks: %d\n", sdram_banks, info->banks));

 	/* check if the memory is registered */
 	if (data[21] & (BIT1 | BIT4))
@@ -266,31 +261,31 @@ check_dimm(uchar slot, sdram_info_t *info)
 	supp_cal = (data[18] & 0x6) >> 1;

 	/* compute the relevant clock values */
-	trp_clocks = (NSto10PS(data[27])+(tmemclk-1)) / tmemclk;
-	trcd_clocks = (NSto10PS(data[29])+(tmemclk-1)) / tmemclk;
-	info->tras_clocks = (NSto10PS(data[30])+(tmemclk-1)) / tmemclk;
+	trp_clocks = (NSto10PS (data[27]) + (tmemclk - 1)) / tmemclk;
+	trcd_clocks = (NSto10PS (data[29]) + (tmemclk - 1)) / tmemclk;
+	info->tras_clocks = (NSto10PS (data[30]) + (tmemclk - 1)) / tmemclk;

-	DP(printf("trp = %d\ntrcd_clocks = %d\ntras_clocks = %d\n",
-		  trp_clocks, trcd_clocks, info->tras_clocks));
+	DP (printf ("trp = %d\ntrcd_clocks = %d\ntras_clocks = %d\n",
+		    trp_clocks, trcd_clocks, info->tras_clocks));

 	/* try a CAS latency of 3 first... */
 	cal_val = 0;
 	if (supp_cal & 3) {
-		if (NS10to10PS(data[9]) <= tmemclk)
+		if (NS10to10PS (data[9]) <= tmemclk)
 			cal_val = 3;
 	}

 	/* then 2... */
 	if (supp_cal & 2) {
-		if (NS10to10PS(data[23]) <= tmemclk)
+		if (NS10to10PS (data[23]) <= tmemclk)
 			cal_val = 2;
 	}

-	DP(printf("cal_val = %d\n", cal_val));
+	DP (printf ("cal_val = %d\n", cal_val));

 	/* bummer, did't work... */
 	if (cal_val == 0) {
-		DP(printf("Couldn't find a good CAS latency\n"));
+		DP (printf ("Couldn't find a good CAS latency\n"));
 		return 0;
 	}

@@ -302,18 +297,19 @@ check_dimm(uchar slot, sdram_info_t *info)
 	if (trcd_clocks > info->tpar)
 		info->tpar = trcd_clocks;

-	DP(printf("tpar set to: %d\n", info->tpar));
+	DP (printf ("tpar set to: %d\n", info->tpar));

 #ifdef CFG_BROKEN_CL2
-	if (info->tpar == 2){
+	if (info->tpar == 2) {
 		info->tpar = 3;
-		DP(printf("tpar fixed-up to: %d\n", info->tpar));
+		DP (printf ("tpar fixed-up to: %d\n", info->tpar));
 	}
 #endif
 	/* compute the module DRB size */
-	info->drb_size = (((1 << (rows + cols)) * sdram_banks) * width) / _16M;
+	info->drb_size =
+		(((1 << (rows + cols)) * sdram_banks) * width) / _16M;

-	DP(printf("drb_size set to: %d\n", info->drb_size));
+	DP (printf ("drb_size set to: %d\n", info->drb_size));

 	/* find the burst len */
 	info->burst_len = data[16] & 0xf;
@@ -330,40 +326,52 @@ check_dimm(uchar slot, sdram_info_t *info)
 }
 #endif /* ! CONFIG_ZUMA_V2 */

-static int
-setup_sdram_common(sdram_info_t info[2])
+static int setup_sdram_common (sdram_info_t info[2])
 {
 	ulong tmp;
-	int tpar=2, tras_clocks=5, registered=1, ecc=2;
+	int tpar = 2, tras_clocks = 5, registered = 1, ecc = 2;

-	if(!info[0].banks && !info[1].banks) return 0;
+	if (!info[0].banks && !info[1].banks)
+		return 0;

-	if(info[0].banks) {
-	    if(info[0].tpar>tpar) tpar=info[0].tpar;
-	    if(info[0].tras_clocks>tras_clocks) tras_clocks=info[0].tras_clocks;
-	    if(!info[0].registered) registered=0;
-	    if(info[0].ecc!=2) ecc=0;
+	if (info[0].banks) {
+		if (info[0].tpar > tpar)
+			tpar = info[0].tpar;
+		if (info[0].tras_clocks > tras_clocks)
+			tras_clocks = info[0].tras_clocks;
+		if (!info[0].registered)
+			registered = 0;
+		if (info[0].ecc != 2indent: Standard input:491: Warning:old style assignment ambiguity in "=*".  Assuming "= *"
+
+indent: Standard input:492: Warning:old style assignment ambiguity in "=*".  Assuming "= *"
+
+)
+			ecc = 0;
 	}

-	if(info[1].banks) {
-	    if(info[1].tpar>tpar) tpar=info[1].tpar;
-	    if(info[1].tras_clocks>tras_clocks) tras_clocks=info[1].tras_clocks;
-	    if(!info[1].registered) registered=0;
-	    if(info[1].ecc!=2) ecc=0;
+	if (info[1].banks) {
+		if (info[1].tpar > tpar)
+			tpar = info[1].tpar;
+		if (info[1].tras_clocks > tras_clocks)
+			tras_clocks = info[1].tras_clocks;
+		if (!info[1].registered)
+			registered = 0;
+		if (info[1].ecc != 2)
+			ecc = 0;
 	}

 	/* SDRAM configuration */
-	tmp = GTREGREAD(SDRAM_CONFIGURATION);
+	tmp = GTREGREAD (SDRAM_CONFIGURATION);

 	/* Turn on physical interleave if both DIMMs
 	 * have even numbers of banks. */
-	if( (info[0].banks == 0 || info[0].banks == 2) &&
-	    (info[1].banks == 0 || info[1].banks == 2) ) {
-	    /* physical interleave on */
-	    tmp &= ~(1 << 15);
+	if ((info[0].banks == 0 || info[0].banks == 2) &&
+	    (info[1].banks == 0 || info[1].banks == 2)) {
+		/* physical interleave on */
+		tmp &= ~(1 << 15);
 	} else {
-	    /* physical interleave off */
-	    tmp |= (1 << 15);
+		/* physical interleave off */
+		tmp |= (1 << 15);
 	}

 	tmp |= (registered << 17);
@@ -372,52 +380,51 @@ setup_sdram_common(sdram_info_t info[2])
 	 * See Res #12 */
 	tmp |= (1 << 26);

-	GT_REG_WRITE(SDRAM_CONFIGURATION, tmp);
-	DP(printf("SDRAM config: %08x\n",
-		GTREGREAD(SDRAM_CONFIGURATION)));
+	GT_REG_WRITE (SDRAM_CONFIGURATION, tmp);
+	DP (printf ("SDRAM config: %08x\n", GTREGREAD (SDRAM_CONFIGURATION)));

 	/* SDRAM timing */
 	tmp = (((tpar == 3) ? 2 : 1) |
 	       (((tpar == 3) ? 2 : 1) << 2) |
-	       (((tpar == 3) ? 2 : 1) << 4) |
-	       (tras_clocks << 8));
+	       (((tpar == 3) ? 2 : 1) << 4) | (tras_clocks << 8));

 #ifdef CONFIG_ECC
 	/* Setup ECC */
-	if (ecc == 2) tmp |= 1<<13;
+	if (ecc == 2)
+		tmp |= 1 << 13;
 #endif /* CONFIG_ECC */

-	GT_REG_WRITE(SDRAM_TIMING, tmp);
-	DP(printf("SDRAM timing: %08x (%d,%d,%d,%d)\n",
-		GTREGREAD(SDRAM_TIMING), tpar,tpar,tpar,tras_clocks));
+	GT_REG_WRITE (SDRAM_TIMING, tmp);
+	DP (printf ("SDRAM timing: %08x (%d,%d,%d,%d)\n",
+		    GTREGREAD (SDRAM_TIMING), tpar, tpar, tpar, tras_clocks));

 	/* SDRAM address decode register */
 	/* program this with the default value */
-	GT_REG_WRITE(SDRAM_ADDRESS_DECODE, 0x2);
-	DP(printf("SDRAM decode: %08x\n",
-		GTREGREAD(SDRAM_ADDRESS_DECODE)));
+	GT_REG_WRITE (SDRAM_ADDRESS_DECODE, 0x2);
+	DP (printf ("SDRAM decode: %08x\n",
+		    GTREGREAD (SDRAM_ADDRESS_DECODE)));

 	return 0;
 }

 /* sets up the GT properly with information passed in */
-static int
-setup_sdram(sdram_info_t *info)
+static int setup_sdram (sdram_info_t * info)
 {
 	ulong tmp, check;
 	ulong *addr = 0;
 	int i;

 	/* sanity checking */
-	if (! info->banks) return 0;
+	if (!info->banks)
+		return 0;

 	/* ---------------------------- */
 	/* Program the GT with the discovered data */

 	/* bank parameters */
-	tmp = (0xf<<16);	/* leave all virt bank pages open */
+	tmp = (0xf << 16);	/* leave all virt bank pages open */

-	DP(printf("drb_size: %d\n", info->drb_size));
+	DP (printf ("drb_size: %d\n", info->drb_size));
 	switch (info->drb_size) {
 	case 1:
 		tmp |= (1 << 14);
@@ -431,41 +438,42 @@ setup_sdram(sdram_info_t *info)
 		tmp |= (3 << 14);
 		break;
 	default:
-		printf("Error in dram size calculation\n");
+		printf ("Error in dram size calculation\n");
 		return 1;
 	}

 	/* SDRAM bank parameters */
 	/* the param registers for slot 1 (banks 2+3) are offset by 0x8 */
-	GT_REG_WRITE(SDRAM_BANK0PARAMETERS + (info->slot * 0x8), tmp);
-	GT_REG_WRITE(SDRAM_BANK1PARAMETERS + (info->slot * 0x8), tmp);
-	DP(printf("SDRAM bankparam slot %d (bank %d+%d): %08lx\n", info->slot, info->slot*2, (info->slot*2)+1, tmp));
+	GT_REG_WRITE (SDRAM_BANK0PARAMETERS + (info->slot * 0x8), tmp);
+	GT_REG_WRITE (SDRAM_BANK1PARAMETERS + (info->slot * 0x8), tmp);
+	DP (printf
+	    ("SDRAM bankparam slot %d (bank %d+%d): %08lx\n", info->slot,
+	     info->slot * 2, (info->slot * 2) + 1, tmp));

 	/* set the SDRAM configuration for each bank */
 	for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) {
-		DP(printf("*** Running a MRS cycle for bank %d ***\n", i));
+		DP (printf ("*** Running a MRS cycle for bank %d ***\n", i));

 		/* map the bank */
-		memory_map_bank(i, 0, GB/4);
+		memory_map_bank (i, 0, GB / 4);

 		/* set SDRAM mode */
-		GT_REG_WRITE(SDRAM_OPERATION_MODE, 0x3);
-		check = GTREGREAD(SDRAM_OPERATION_MODE);
+		GT_REG_WRITE (SDRAM_OPERATION_MODE, 0x3);
+		check = GTREGREAD (SDRAM_OPERATION_MODE);

 		/* dummy write */
 		*addr = 0;

 		/* wait for the command to complete */
-		while ((GTREGREAD(SDRAM_OPERATION_MODE) & (1 << 31)) == 0)
-			;
+		while ((GTREGREAD (SDRAM_OPERATION_MODE) & (1 << 31)) == 0);

 		/* switch back to normal operation mode */
-		GT_REG_WRITE(SDRAM_OPERATION_MODE, 0);
-		check = GTREGREAD(SDRAM_OPERATION_MODE);
+		GT_REG_WRITE (SDRAM_OPERATION_MODE, 0);
+		check = GTREGREAD (SDRAM_OPERATION_MODE);

 		/* unmap the bank */
-		memory_map_bank(i, 0, 0);
-		DP(printf("*** MRS cycle for bank %d done ***\n", i));
+		memory_map_bank (i, 0, 0);
+		DP (printf ("*** MRS cycle for bank %d done ***\n", i));
 	}

 	return 0;
@@ -478,50 +486,50 @@ setup_sdram(sdram_info_t *info)
 * - short between address lines
 * - short between data lines
 */
-static long int
-dram_size(long int *base, long int maxsize)
+static long int dram_size (long int *base, long int maxsize)
 {
-    volatile long int	 *addr, *b=base;
-    long int	 cnt, val, save1, save2;
+	volatile long int *addr, *b = base;
+	long int cnt, val, save1, save2;

 #define STARTVAL (1<<20)	/* start test at 1M */
-    for (cnt = STARTVAL/sizeof(long); cnt < maxsize/sizeof(long); cnt <<= 1) {
-	    addr = base + cnt;	/* pointer arith! */
+	for (cnt = STARTVAL / sizeof (long); cnt < maxsize / sizeof (long);
+	     cnt <<= 1) {
+		addr = base + cnt;	/* pointer arith! */

-	    save1=*addr;	/* save contents of addr */
-	    save2=*b;		/* save contents of base */
+		save1 = *addr;	/* save contents of addr */
+		save2 = *b;	/* save contents of base */

-	    *addr=cnt;		/* write cnt to addr */
-	    *b=0;		/* put null at base */
+		*addr = cnt;	/* write cnt to addr */
+		*b = 0;		/* put null at base */

-	    /* check at base address */
-	    if ((*b) != 0) {
-		*addr=save1;	/* restore *addr */
-		*b=save2;	/* restore *b */
-		return (0);
-	    }
-	    val = *addr;	/* read *addr */
+		/* check at base address */
+		if ((*b) != 0) {
+			*addr = save1;	/* restore *addr */
+			*b = save2;	/* restore *b */
+			return (0);
+		}
+		val = *addr;	/* read *addr */

-	    *addr=save1;
-	    *b=save2;
+		*addr = save1;
+		*b = save2;

-	    if (val != cnt) {
-		    /* fix boundary condition.. STARTVAL means zero */
-		    if(cnt==STARTVAL/sizeof(long)) cnt=0;
-		    return (cnt * sizeof(long));
-	    }
-    }
-    return maxsize;
+		if (val != cnt) {
+			/* fix boundary condition.. STARTVAL means zero */
+			if (cnt == STARTVAL / sizeof (long))
+				cnt = 0;
+			return (cnt * sizeof (long));
+		}
+	}
+	return maxsize;
 }

 /* ------------------------------------------------------------------------- */

 /* U-Boot interface function to SDRAM init - this is where all the
 * controlling logic happens */
-long int
-initdram(int board_type)
+long int initdram (int board_type)
 {
-	ulong checkbank[4] = { [0 ... 3] = 0 };
+	ulong checkbank[4] = {[0 ... 3] = 0 };
 	int bank_no;
 	ulong total;
 	int nhr;
@@ -531,92 +539,97 @@ initdram(int board_type)
 	/* first, use the SPD to get info about the SDRAM */

 	/* check the NHR bit and skip mem init if it's already done */
-	nhr = get_hid0() & (1 << 16);
+	nhr = get_hid0 () & (1 << 16);

 	if (nhr) {
-		printf("Skipping SDRAM setup due to NHR bit being set\n");
+		printf ("Skipping SDRAM setup due to NHR bit being set\n");
 	} else {
 		/* DIMM0 */
-		check_dimm(0, &dimm_info[0]);
+		check_dimm (0, &dimm_info[0]);

 		/* DIMM1 */
-#ifndef CONFIG_EVB64260_750CX /* EVB64260_750CX has only 1 DIMM */
-		check_dimm(1, &dimm_info[1]);
-#else /* CONFIG_EVB64260_750CX */
-		memset(&dimm_info[1], 0, sizeof(sdram_info_t));
+#ifndef CONFIG_EVB64260_750CX	/* EVB64260_750CX has only 1 DIMM */
+		check_dimm (1, &dimm_info[1]);
+#else  /* CONFIG_EVB64260_750CX */
+		memset (&dimm_info[1], 0, sizeof (sdram_info_t));
 #endif

 		/* unmap all banks */
-		memory_map_bank(0, 0, 0);
-		memory_map_bank(1, 0, 0);
-		memory_map_bank(2, 0, 0);
-		memory_map_bank(3, 0, 0);
+		memory_map_bank (0, 0, 0);
+		memory_map_bank (1, 0, 0);
+		memory_map_bank (2, 0, 0);
+		memory_map_bank (3, 0, 0);

 		/* Now, program the GT with the correct values */
-		if (setup_sdram_common(dimm_info)) {
-			printf("Setup common failed.\n");
+		if (setup_sdram_common (dimm_info)) {
+			printf ("Setup common failed.\n");
 		}

-		if (setup_sdram(&dimm_info[0])) {
-			printf("Setup for DIMM1 failed.\n");
+		if (setup_sdram (&dimm_info[0])) {
+			printf ("Setup for DIMM1 failed.\n");
 		}

-		if (setup_sdram(&dimm_info[1])) {
-			printf("Setup for DIMM2 failed.\n");
+		if (setup_sdram (&dimm_info[1])) {
+			printf ("Setup for DIMM2 failed.\n");
 		}

 		/* set the NHR bit */
-		set_hid0(get_hid0() | (1 << 16));
+		set_hid0 (get_hid0 () | (1 << 16));
 	}
 	/* next, size the SDRAM banks */

 	total = 0;
-	if (dimm_info[0].banks > 0) checkbank[0] = 1;
-	if (dimm_info[0].banks > 1) checkbank[1] = 1;
+	if (dimm_info[0].banks > 0)
+		checkbank[0] = 1;
+	if (dimm_info[0].banks > 1)
+		checkbank[1] = 1;
 	if (dimm_info[0].banks > 2)
-		printf("Error, SPD claims DIMM1 has >2 banks\n");
+		printf ("Error, SPD claims DIMM1 has >2 banks\n");

-	if (dimm_info[1].banks > 0) checkbank[2] = 1;
-	if (dimm_info[1].banks > 1) checkbank[3] = 1;
+	if (dimm_info[1].banks > 0)
+		checkbank[2] = 1;
+	if (dimm_info[1].banks > 1)
+		checkbank[3] = 1;
 	if (dimm_info[1].banks > 2)
-		printf("Error, SPD claims DIMM2 has >2 banks\n");
+		printf ("Error, SPD claims DIMM2 has >2 banks\n");

 	/* Generic dram sizer: works even if we don't have i2c DIMMs,
 	 * as long as the timing settings are more or less correct */

 	/*
 	 * pass 1: size all the banks, using first bat (0-256M)
-	 * 	   limitation: we only support 256M per bank due to
-	 *  	   us only having 1 BAT for all DRAM
+	 *         limitation: we only support 256M per bank due to
+	 *         us only having 1 BAT for all DRAM
 	 */
 	for (bank_no = 0; bank_no < CFG_DRAM_BANKS; bank_no++) {
 		/* skip over banks that are not populated */
-		if (! checkbank[bank_no])
+		if (!checkbank[bank_no])
 			continue;

-		DP(printf("checking bank %d\n", bank_no));
+		DP (printf ("checking bank %d\n", bank_no));

-		memory_map_bank(bank_no, 0, GB/4);
-		checkbank[bank_no] = dram_size(NULL, GB/4);
-		memory_map_bank(bank_no, 0, 0);
+		memory_map_bank (bank_no, 0, GB / 4);
+		checkbank[bank_no] = dram_size (NULL, GB / 4);
+		memory_map_bank (bank_no, 0, 0);

-		DP(printf("bank %d %08lx\n", bank_no, checkbank[bank_no]));
+		DP (printf ("bank %d %08lx\n", bank_no, checkbank[bank_no]));
 	}

 	/*
 	 * pass 2: contiguously map each bank into physical address
-	 * 	   space.
+	 *         space.
 	 */
-	dimm_info[0].banks=dimm_info[1].banks=0;
+	dimm_info[0].banks = dimm_info[1].banks = 0;
 	for (bank_no = 0; bank_no < CFG_DRAM_BANKS; bank_no++) {
-		if(!checkbank[bank_no]) continue;
+		if (!checkbank[bank_no])
+			continue;

-		dimm_info[bank_no/2].banks++;
-		dimm_info[bank_no/2].size+=checkbank[bank_no];
+		dimm_info[bank_no / 2].banks++;
+		dimm_info[bank_no / 2].size += checkbank[bank_no];

-		memory_map_bank(bank_no, total, checkbank[bank_no]);
+		memory_map_bank (bank_no, total, checkbank[bank_no]);
 #ifdef MAP_PCI
-		memory_map_bank_pci(bank_no, total, checkbank[bank_no]);
+		memory_map_bank_pci (bank_no, total, checkbank[bank_no]);
 #endif
 		total += checkbank[bank_no];
 	}
@@ -630,21 +643,22 @@ initdram(int board_type)
 	 * in that configuration, ECC chips are mounted, even for stacked
 	 * chips)
 	 */
-	if (checkbank[2]==0 && checkbank[3]==0) {
-		dimm_info[0].ecc=2;
-		GT_REG_WRITE(SDRAM_TIMING, GTREGREAD(SDRAM_TIMING) | (1 << 13));
+	if (checkbank[2] == 0 && checkbank[3] == 0) {
+		dimm_info[0].ecc = 2;
+		GT_REG_WRITE (SDRAM_TIMING,
+			      GTREGREAD (SDRAM_TIMING) | (1 << 13));
 		/* TODO: do we have to run MRS cycles again? */
 	}
 #endif /* CONFIG_ZUMA_V2 */

-	if (GTREGREAD(SDRAM_TIMING) & (1 << 13)) {
-		puts("[ECC] ");
+	if (GTREGREAD (SDRAM_TIMING) & (1 << 13)) {
+		puts ("[ECC] ");
 	}
 #endif /* CONFIG_ECC */

 #ifdef DEBUG
-	dump_dimm_info(&dimm_info[0]);
-	dump_dimm_info(&dimm_info[1]);
+	dump_dimm_info (&dimm_info[0]);
+	dump_dimm_info (&dimm_info[1]);
 #endif
 	/* TODO: return at MOST 256M? */
 	/* return total > GB/4 ? GB/4 : total; */
--- a/board/evb64260/zuma_pbb_mbox.h
+++ b/board/evb64260/zuma_pbb_mbox.h
@@ -2,33 +2,33 @@
 #define OUT_PENDING 2

 enum {
-    ZUMA_MBOXMSG_DONE,
-    ZUMA_MBOXMSG_MACL,
-    ZUMA_MBOXMSG_MACH,
-    ZUMA_MBOXMSG_IP,
-    ZUMA_MBOXMSG_SLOT,
-    ZUMA_MBOXMSG_RESET,
-    ZUMA_MBOXMSG_BAUD,
-    ZUMA_MBOXMSG_START,
-    ZUMA_MBOXMSG_ENG_PRV_MACL,
-    ZUMA_MBOXMSG_ENG_PRV_MACH,
+	ZUMA_MBOXMSG_DONE,
+	ZUMA_MBOXMSG_MACL,
+	ZUMA_MBOXMSG_MACH,
+	ZUMA_MBOXMSG_IP,
+	ZUMA_MBOXMSG_SLOT,
+	ZUMA_MBOXMSG_RESET,
+	ZUMA_MBOXMSG_BAUD,
+	ZUMA_MBOXMSG_START,
+	ZUMA_MBOXMSG_ENG_PRV_MACL,
+	ZUMA_MBOXMSG_ENG_PRV_MACH,

-    MBOXMSG_LAST
+	MBOXMSG_LAST
 };

 struct zuma_mailbox_info {
-  unsigned char acc_mac[6];
-  unsigned char prv_mac[6];
-  unsigned int ip;
-  unsigned int slot_bac;
-  unsigned int console_baud;
-  unsigned int debug_baud;
+	unsigned char acc_mac[6];
+	unsigned char prv_mac[6];
+	unsigned int ip;
+	unsigned int slot_bac;
+	unsigned int console_baud;
+	unsigned int debug_baud;
 };

 struct _zuma_mbox_dev {
-  pci_dev_t dev;
-  PBB_DMA_REG_MAP *sip;
-  struct zuma_mailbox_info mailbox;
+	pci_dev_t dev;
+	PBB_DMA_REG_MAP *sip;
+	struct zuma_mailbox_info mailbox;
 };

 #define zuma_prv_mac		zuma_mbox_dev.mailbox.prv_mac
@@ -40,4 +40,4 @@ struct _zuma_mbox_dev {


 extern struct _zuma_mbox_dev zuma_mbox_dev;
-extern int zuma_mbox_init(void);
+extern int zuma_mbox_init (void);
--- a/board/fads/flash.c
+++ b/board/fads/flash.c
@@ -24,7 +24,7 @@
 #include <common.h>
 #include <mpc8xx.h>

-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips        */

 #if defined(CFG_ENV_IS_IN_FLASH)
 # ifndef  CFG_ENV_ADDR
@@ -41,43 +41,42 @@ flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 /*-----------------------------------------------------------------------
 * Functions
 */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info);
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-static void flash_get_offsets (ulong base, flash_info_t *info);
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static int write_word (flash_info_t * info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t * info);

 /*-----------------------------------------------------------------------
 */

 unsigned long flash_init (void)
 {
-	volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	unsigned long total_size;
 	unsigned long size_b0, size_b1;
 	int i;

 	/* Init: no FLASHes known */
-	for (i=0; i < CFG_MAX_FLASH_BANKS; ++i)
-	{
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}

 	total_size = 0;
 	size_b0 = 0xffffffff;

-	for (i=0; i < CFG_MAX_FLASH_BANKS; ++i)
-	{
-		size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + total_size), &flash_info[i]);
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+		size_b1 =
+			flash_get_size ((vu_long *) (CFG_FLASH_BASE +
+						     total_size),
+					&flash_info[i]);

-		if (flash_info[i].flash_id == FLASH_UNKNOWN)
-		{
-			printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", i, size_b1, size_b1>>20);
+		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+			printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", i, size_b1, size_b1 >> 20);
 		}

 		/* Is this really needed ? - LP */
 		if (size_b1 > size_b0) {
-			printf ("## ERROR: Bank %d (0x%08lx = %ld MB) > Bank %d (0x%08lx = %ld MB)\n",
-			        i, size_b1, size_b1>>20, i-1, size_b0, size_b0>>20);
+			printf ("## ERROR: Bank %d (0x%08lx = %ld MB) > Bank %d (0x%08lx = %ld MB)\n", i, size_b1, size_b1 >> 20, i - 1, size_b0, size_b0 >> 20);
 			goto out_error;
 		}
 		size_b0 = size_b1;
@@ -85,43 +84,47 @@ unsigned long flash_init (void)
 	}

 	/* Compute the Address Mask */
-	for (i=0; (total_size >> i) != 0; ++i) {};
+	for (i = 0; (total_size >> i) != 0; ++i) {
+	}
 	i--;

 	if (total_size != (1 << i)) {
-		printf ("## WARNING: Total FLASH size (0x%08lx = %ld MB) is not a power of 2\n",
-			total_size, total_size>>20);
+		printf ("## WARNING: Total FLASH size (0x%08lx = %ld MB) is not a power of 2\n", total_size, total_size >> 20);
 	}

 	/* Remap FLASH according to real size */
-	memctl->memc_or0 = ((((unsigned long)~1) << i) & OR_AM_MSK) | CFG_OR_TIMING_FLASH;
+	memctl->memc_or0 =
+		((((unsigned long) ~1) << i) & OR_AM_MSK) |
+		CFG_OR_TIMING_FLASH;
 	memctl->memc_br0 = CFG_BR0_PRELIM;

 	total_size = 0;

-	for (i=0; i < CFG_MAX_FLASH_BANKS && flash_info[i].size != 0; ++i)
-	{
+	for (i = 0; i < CFG_MAX_FLASH_BANKS && flash_info[i].size != 0; ++i) {
 		/* Re-do sizing to get full correct info */
 		/* Why ? - LP */
-		size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + total_size), &flash_info[i]);
+		size_b1 =
+			flash_get_size ((vu_long *) (CFG_FLASH_BASE +
+						     total_size),
+					&flash_info[i]);

 		/* This is done by flash_get_size - LP */
 		/* flash_get_offsets (CFG_FLASH_BASE + total_size, &flash_info[i]); */

 #if CFG_MONITOR_BASE >= CFG_FLASH_BASE
 		/* monitor protection ON by default */
-		flash_protect(FLAG_PROTECT_SET,
-			      CFG_MONITOR_BASE,
-			      CFG_MONITOR_BASE+monitor_flash_len-1,
-			      &flash_info[i]);
+		flash_protect (FLAG_PROTECT_SET,
+			       CFG_MONITOR_BASE,
+			       CFG_MONITOR_BASE + monitor_flash_len - 1,
+			       &flash_info[i]);
 #endif

 #ifdef	CFG_ENV_IS_IN_FLASH
 		/* ENV protection ON by default */
-		flash_protect(FLAG_PROTECT_SET,
-			      CFG_ENV_ADDR,
-			      CFG_ENV_ADDR+CFG_ENV_SIZE-1,
-			      &flash_info[i]);
+		flash_protect (FLAG_PROTECT_SET,
+			       CFG_ENV_ADDR,
+			       CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+			       &flash_info[i]);
 #endif

 		total_size += size_b1;
@@ -129,12 +132,11 @@ unsigned long flash_init (void)

 	return (total_size);

-out_error:
-	for (i=0; i < CFG_MAX_FLASH_BANKS; ++i)
-	{
-		flash_info[i].flash_id		= FLASH_UNKNOWN;
-		flash_info[i].sector_count	= -1;
-		flash_info[i].size		= 0;
+      out_error:
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+		flash_info[i].sector_count = -1;
+		flash_info[i].size = 0;
 	}

 	return (0);
@@ -142,13 +144,14 @@ out_error:

 /*-----------------------------------------------------------------------
 */
-static void flash_get_offsets (ulong base, flash_info_t *info)
+static void flash_get_offsets (ulong base, flash_info_t * info)
 {
 	int i;

 	/* set up sector start address table */
-	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040 || (info->flash_id & FLASH_TYPEMASK) == FLASH_AM080 ) {
-		/* set sector offsets for uniform sector type	*/
+	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040
+	    || (info->flash_id & FLASH_TYPEMASK) == FLASH_AM080) {
+		/* set sector offsets for uniform sector type   */
 		for (i = 0; i < info->sector_count; i++) {
 			info->start[i] = base + (i * 0x00040000);
 		}
@@ -157,64 +160,78 @@ static void flash_get_offsets (ulong base, flash_info_t *info)

 /*-----------------------------------------------------------------------
 */
-void flash_print_info  (flash_info_t *info)
+void flash_print_info (flash_info_t * info)
 {
 	int i;

-	if (info->flash_id == FLASH_UNKNOWN)
-	{
+	if (info->flash_id == FLASH_UNKNOWN) {
 		printf ("missing or unknown FLASH type\n");
 		return;
 	}

-	switch (info->flash_id & FLASH_VENDMASK)
-	{
-		case FLASH_MAN_AMD:	printf ("AMD ");		break;
-		case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
-		case FLASH_MAN_BM:	printf ("BRIGHT MICRO ");	break;
-		default:		printf ("Unknown Vendor ");	break;
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:
+		printf ("AMD ");
+		break;
+	case FLASH_MAN_FUJ:
+		printf ("FUJITSU ");
+		break;
+	case FLASH_MAN_BM:
+		printf ("BRIGHT MICRO ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
 	}

-	switch (info->flash_id & FLASH_TYPEMASK)
-	{
-		case FLASH_AM040:	printf ("29F040 or 29LV040 (4 Mbit, uniform sectors)\n");
-			break;
-		case FLASH_AM080:	printf ("29F080 or 29LV080 (8 Mbit, uniform sectors)\n");
-		                	break;
-		case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
-					break;
-		case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
-					break;
-		case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
-					break;
-		case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
-					break;
-		case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
-					break;
-		case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
-					break;
-		case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
-					break;
-		case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit, top boot sector)\n");
-					break;
-		default:		printf ("Unknown Chip Type\n");
-					break;
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM040:
+		printf ("29F040 or 29LV040 (4 Mbit, uniform sectors)\n");
+		break;
+	case FLASH_AM080:
+		printf ("29F080 or 29LV080 (8 Mbit, uniform sectors)\n");
+		break;
+	case FLASH_AM400B:
+		printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM400T:
+		printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM800B:
+		printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM800T:
+		printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM160B:
+		printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM160T:
+		printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM320B:
+		printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM320T:
+		printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
 	}

-	printf ("  Size: %ld MB in %d Sectors\n",info->size >> 20, info->sector_count);
+	printf ("  Size: %ld MB in %d Sectors\n", info->size >> 20,
+		info->sector_count);

 	printf ("  Sector Start Addresses:");

-	for (i=0; i<info->sector_count; ++i)
-	{
-		if ((i % 5) == 0)
-		{
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0) {
 			printf ("\n   ");
 		}

 		printf (" %08lX%s",
-			info->start[i],
-			info->protect[i] ? " (RO)" : "     ");
+			info->start[i], info->protect[i] ? " (RO)" : "     ");
 	}

 	printf ("\n");
@@ -232,11 +249,12 @@ void flash_print_info  (flash_info_t *info)
 * The following code cannot be run from FLASH!
 */

-static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+static ulong flash_get_size (vu_long * addr, flash_info_t * info)
 {
 	short i;
+
 #if 0
-	ulong base = (ulong)addr;
+	ulong base = (ulong) addr;
 #endif
 	uchar value;

@@ -253,97 +271,95 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)

 	value = addr[0];

-	switch (value + (value << 16))
-	{
-		case AMD_MANUFACT:
-			info->flash_id = FLASH_MAN_AMD;
-			break;
+	switch (value + (value << 16)) {
+	case AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;

-		case FUJ_MANUFACT:
-			info->flash_id = FLASH_MAN_FUJ;
-			break;
+	case FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;

-		default:
-			info->flash_id = FLASH_UNKNOWN;
-			info->sector_count = 0;
-			info->size = 0;
-			break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		break;
 	}

-	value = addr[1];			/* device ID		*/
+	value = addr[1];	/* device ID            */

-	switch (value)
-	{
-		case AMD_ID_F040B:
-			info->flash_id += FLASH_AM040;
-			info->sector_count = 8;
-			info->size = 0x00200000;
-			break;				/* => 2 MB		*/
+	switch (value) {
+	case AMD_ID_F040B:
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x00200000;
+		break;		/* => 2 MB              */

-		case AMD_ID_F080B:
-			info->flash_id += FLASH_AM080;
-			info->sector_count =16;
-			info->size = 0x00400000;
-			break;				/* => 4 MB		*/
+	case AMD_ID_F080B:
+		info->flash_id += FLASH_AM080;
+		info->sector_count = 16;
+		info->size = 0x00400000;
+		break;		/* => 4 MB              */

-		case AMD_ID_LV400T:
-			info->flash_id += FLASH_AM400T;
-			info->sector_count = 11;
-			info->size = 0x00100000;
-			break;				/* => 1 MB		*/
+	case AMD_ID_LV400T:
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;		/* => 1 MB              */

-		case AMD_ID_LV400B:
-			info->flash_id += FLASH_AM400B;
-			info->sector_count = 11;
-			info->size = 0x00100000;
-			break;				/* => 1 MB		*/
+	case AMD_ID_LV400B:
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;		/* => 1 MB              */

-		case AMD_ID_LV800T:
-			info->flash_id += FLASH_AM800T;
-			info->sector_count = 19;
-			info->size = 0x00200000;
-			break;				/* => 2 MB		*/
+	case AMD_ID_LV800T:
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;		/* => 2 MB              */

-		case AMD_ID_LV800B:
-			info->flash_id += FLASH_AM800B;
-			info->sector_count = 19;
-			info->size = 0x00200000;
-			break;				/* => 2 MB		*/
+	case AMD_ID_LV800B:
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;		/* => 2 MB              */

-		case AMD_ID_LV160T:
-			info->flash_id += FLASH_AM160T;
-			info->sector_count = 35;
-			info->size = 0x00400000;
-			break;				/* => 4 MB		*/
+	case AMD_ID_LV160T:
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;		/* => 4 MB              */

-		case AMD_ID_LV160B:
-			info->flash_id += FLASH_AM160B;
-			info->sector_count = 35;
-			info->size = 0x00400000;
-			break;				/* => 4 MB		*/
-#if 0	/* enable when device IDs are available */
-		case AMD_ID_LV320T:
-			info->flash_id += FLASH_AM320T;
-			info->sector_count = 67;
-			info->size = 0x00800000;
-			break;				/* => 8 MB		*/
+	case AMD_ID_LV160B:
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;		/* => 4 MB              */
+#if 0				/* enable when device IDs are available */
+	case AMD_ID_LV320T:
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 67;
+		info->size = 0x00800000;
+		break;		/* => 8 MB              */

-		case AMD_ID_LV320B:
-			info->flash_id += FLASH_AM320B;
-			info->sector_count = 67;
-			info->size = 0x00800000;
-			break;				/* => 8 MB		*/
+	case AMD_ID_LV320B:
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 67;
+		info->size = 0x00800000;
+		break;		/* => 8 MB              */
 #endif
-		default:
-			info->flash_id = FLASH_UNKNOWN;
-			return (0);			/* => no or unknown flash */
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);	/* => no or unknown flash */

 	}

 #if 0
 	/* set up sector start address table */
 	if (info->flash_id & FLASH_BTYPE) {
-		/* set sector offsets for bottom boot block type	*/
+		/* set sector offsets for bottom boot block type        */
 		info->start[0] = base + 0x00000000;
 		info->start[1] = base + 0x00008000;
 		info->start[2] = base + 0x0000C000;
@@ -352,7 +368,7 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 			info->start[i] = base + (i * 0x00020000) - 0x00060000;
 		}
 	} else {
-		/* set sector offsets for top boot block type		*/
+		/* set sector offsets for top boot block type           */
 		i = info->sector_count - 1;
 		info->start[i--] = base + info->size - 0x00008000;
 		info->start[i--] = base + info->size - 0x0000C000;
@@ -362,24 +378,22 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 		}
 	}
 #else
-	flash_get_offsets ((ulong)addr, info);
+	flash_get_offsets ((ulong) addr, info);
 #endif

 	/* check for protected sectors */
-	for (i = 0; i < info->sector_count; i++)
-	{
+	for (i = 0; i < info->sector_count; i++) {
 		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
 		/* D0 = 1 if protected */
-		addr = (volatile unsigned long *)(info->start[i]);
+		addr = (volatile unsigned long *) (info->start[i]);
 		info->protect[i] = addr[2] & 1;
 	}

 	/*
 	 * Prevent writes to uninitialized FLASH.
 	 */
-	if (info->flash_id != FLASH_UNKNOWN)
-	{
-		addr = (volatile unsigned long *)info->start[0];
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr = (volatile unsigned long *) info->start[0];
 #if 0
 		*addr = 0x00F000F0;	/* reset bank */
 #else
@@ -394,9 +408,9 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 /*-----------------------------------------------------------------------
 */

-int	flash_erase (flash_info_t *info, int s_first, int s_last)
+int flash_erase (flash_info_t * info, int s_first, int s_last)
 {
-	vu_long *addr = (vu_long*)(info->start[0]);
+	vu_long *addr = (vu_long *) (info->start[0]);
 	int flag, prot, sect, l_sect;
 	ulong start, now, last;

@@ -416,15 +430,14 @@ int	flash_erase (flash_info_t *info, int s_first, int s_last)
 	}

 	prot = 0;
-	for (sect=s_first; sect<=s_last; ++sect) {
+	for (sect = s_first; sect <= s_last; ++sect) {
 		if (info->protect[sect]) {
 			prot++;
 		}
 	}

 	if (prot) {
-		printf ("- Warning: %d protected sectors will not be erased!\n",
-			prot);
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
 	} else {
 		printf ("\n");
 	}
@@ -432,7 +445,7 @@ int	flash_erase (flash_info_t *info, int s_first, int s_last)
 	l_sect = -1;

 	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
+	flag = disable_interrupts ();

 #if 0
 	addr[0x0555] = 0x00AA00AA;
@@ -449,9 +462,9 @@ int	flash_erase (flash_info_t *info, int s_first, int s_last)
 #endif

 	/* Start erase on unprotected sectors */
-	for (sect = s_first; sect<=s_last; sect++) {
+	for (sect = s_first; sect <= s_last; sect++) {
 		if (info->protect[sect] == 0) {	/* not protected */
-			addr = (vu_long*)(info->start[sect]);
+			addr = (vu_long *) (info->start[sect]);
 #if 0
 			addr[0] = 0x00300030;
 #else
@@ -463,7 +476,7 @@ int	flash_erase (flash_info_t *info, int s_first, int s_last)

 	/* re-enable interrupts if necessary */
 	if (flag)
-		enable_interrupts();
+		enable_interrupts ();

 	/* wait at least 80us - let's wait 1 ms */
 	udelay (1000);
@@ -475,15 +488,15 @@ int	flash_erase (flash_info_t *info, int s_first, int s_last)
 		goto DONE;

 	start = get_timer (0);
-	last  = start;
-	addr = (vu_long*)(info->start[l_sect]);
+	last = start;
+	addr = (vu_long *) (info->start[l_sect]);
 #if 0
 	while ((addr[0] & 0x00800080) != 0x00800080)
 #else
 	while ((addr[0] & 0xFFFFFFFF) != 0xFFFFFFFF)
 #endif
 	{
-		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+		if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
 			printf ("Timeout\n");
 			return 1;
 		}
@@ -494,9 +507,9 @@ int	flash_erase (flash_info_t *info, int s_first, int s_last)
 		}
 	}

-DONE:
+      DONE:
 	/* reset to read mode */
-	addr = (volatile unsigned long *)info->start[0];
+	addr = (volatile unsigned long *) info->start[0];
 #if 0
 	addr[0] = 0x00F000F0;	/* reset bank */
 #else
@@ -514,7 +527,7 @@ DONE:
 * 2 - Flash not erased
 */

-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
 {
 	ulong cp, wp, data;
 	int i, l, rc;
@@ -526,19 +539,19 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
 	 */
 	if ((l = addr - wp) != 0) {
 		data = 0;
-		for (i=0, cp=wp; i<l; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *)cp);
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
 		}
-		for (; i<4 && cnt>0; ++i) {
+		for (; i < 4 && cnt > 0; ++i) {
 			data = (data << 8) | *src++;
 			--cnt;
 			++cp;
 		}
-		for (; cnt==0 && i<4; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *)cp);
+		for (; cnt == 0 && i < 4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
 		}

-		if ((rc = write_word(info, wp, data)) != 0) {
+		if ((rc = write_word (info, wp, data)) != 0) {
 			return (rc);
 		}
 		wp += 4;
@@ -549,13 +562,13 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
 	 */
 	while (cnt >= 4) {
 		data = 0;
-		for (i=0; i<4; ++i) {
+		for (i = 0; i < 4; ++i) {
 			data = (data << 8) | *src++;
 		}
-		if ((rc = write_word(info, wp, data)) != 0) {
+		if ((rc = write_word (info, wp, data)) != 0) {
 			return (rc);
 		}
-		wp  += 4;
+		wp += 4;
 		cnt -= 4;
 	}

@@ -567,15 +580,15 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
 	 * handle unaligned tail bytes
 	 */
 	data = 0;
-	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+	for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
 		data = (data << 8) | *src++;
 		--cnt;
 	}
-	for (; i<4; ++i, ++cp) {
-		data = (data << 8) | (*(uchar *)cp);
+	for (; i < 4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
 	}

-	return (write_word(info, wp, data));
+	return (write_word (info, wp, data));
 }

 /*-----------------------------------------------------------------------
@@ -584,18 +597,18 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
 * 1 - write timeout
 * 2 - Flash not erased
 */
-static int write_word (flash_info_t *info, ulong dest, ulong data)
+static int write_word (flash_info_t * info, ulong dest, ulong data)
 {
-	vu_long *addr = (vu_long*)(info->start[0]);
+	vu_long *addr = (vu_long *) (info->start[0]);
 	ulong start;
 	int flag;

 	/* Check if Flash is (sufficiently) erased */
-	if ((*((vu_long *)dest) & data) != data) {
+	if ((*((vu_long *) dest) & data) != data) {
 		return (2);
 	}
 	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
+	flag = disable_interrupts ();

 #if 0
 	addr[0x0555] = 0x00AA00AA;
@@ -607,21 +620,21 @@ static int write_word (flash_info_t *info, ulong dest, ulong data)
 	addr[0x0555] = 0xA0A0A0A0;
 #endif

-	*((vu_long *)dest) = data;
+	*((vu_long *) dest) = data;

 	/* re-enable interrupts if necessary */
 	if (flag)
-		enable_interrupts();
+		enable_interrupts ();

 	/* data polling for D7 */
 	start = get_timer (0);
 #if 0
-	while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080))
+	while ((*((vu_long *) dest) & 0x00800080) != (data & 0x00800080))
 #else
-	while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080))
+	while ((*((vu_long *) dest) & 0x80808080) != (data & 0x80808080))
 #endif
 	{
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
 			return (1);
 		}
 	}
--- a/board/gen860t/fpga.c
+++ b/board/gen860t/fpga.c
@@ -72,30 +72,27 @@ Xilinx_Virtex2_Slave_SelectMap_fns fpga_fns = {
 };

 Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
-	{ Xilinx_Virtex2,
-	  slave_selectmap,
-	  XILINX_XC2V3000_SIZE,
-	  (void *)&fpga_fns,
-	  0
-	}
+	{Xilinx_Virtex2,
+	 slave_selectmap,
+	 XILINX_XC2V3000_SIZE,
+	 (void *) &fpga_fns,
+	 0}
 };

 /*
 * Display FPGA revision information
 */
-void
-print_fpga_revision(void)
+void print_fpga_revision (void)
 {
-	vu_long *rev_p = (vu_long *)0x60000008;
+	vu_long *rev_p = (vu_long *) 0x60000008;

-	printf("FPGA Revision 0x%.8lx"
-		   " (Date %.2lx/%.2lx/%.2lx, Status \"%.1lx\", Version %.3lu)\n",
-		   *rev_p,
-		   ((*rev_p >> 28) & 0xf),
-		   ((*rev_p >> 20) & 0xff),
-		   ((*rev_p >> 12) & 0xff),
-		   ((*rev_p >> 8) & 0xf),
-		   (*rev_p & 0xff));
+	printf ("FPGA Revision 0x%.8lx"
+		" (Date %.2lx/%.2lx/%.2lx, Status \"%.1lx\", Version %.3lu)\n",
+		*rev_p,
+		((*rev_p >> 28) & 0xf),
+		((*rev_p >> 20) & 0xff),
+		((*rev_p >> 12) & 0xff),
+		((*rev_p >> 8) & 0xf), (*rev_p & 0xff));
 }


@@ -106,10 +103,9 @@ print_fpga_revision(void)
 * problems with bus charging.
 * Return 0 on failure, 1 on success.
 */
-int
-test_fpga_ibtr(void)
+int test_fpga_ibtr (void)
 {
-	vu_long *ibtr_p = (vu_long *)0x60000010;
+	vu_long *ibtr_p = (vu_long *) 0x60000010;
 	vu_long readback;
 	vu_long compare;
 	int i;
@@ -118,40 +114,41 @@ test_fpga_ibtr(void)
 	int pass = 1;

 	static const ulong bitpattern[] = {
-		0xdeadbeef,	/* magic ID pattern for debug	*/
-		0x00000001,	/* single bit					*/
-		0x00000003,	/* two adjacent bits			*/
-		0x00000007,	/* three adjacent bits			*/
-		0x0000000F,	/* four adjacent bits			*/
-		0x00000005,	/* two non-adjacent bits		*/
-		0x00000015,	/* three non-adjacent bits		*/
-		0x00000055,	/* four non-adjacent bits		*/
-		0xaaaaaaaa,	/* alternating 1/0				*/
+		0xdeadbeef,	/* magic ID pattern for debug   */
+		0x00000001,	/* single bit                                   */
+		0x00000003,	/* two adjacent bits                    */
+		0x00000007,	/* three adjacent bits                  */
+		0x0000000F,	/* four adjacent bits                   */
+		0x00000005,	/* two non-adjacent bits                */
+		0x00000015,	/* three non-adjacent bits              */
+		0x00000055,	/* four non-adjacent bits               */
+		0xaaaaaaaa,	/* alternating 1/0                              */
 	};

 	for (i = 0; i < 1024; i++) {
 		for (j = 0; j < 31; j++) {
-			for (k = 0; k < sizeof(bitpattern)/sizeof(bitpattern[0]); k++) {
+			for (k = 0;
+			     k < sizeof (bitpattern) / sizeof (bitpattern[0]);
+			     k++) {
 				*ibtr_p = compare = (bitpattern[k] << j);
 				readback = *ibtr_p;
 				if (readback != ~compare) {
-					printf("%s:%d: FPGA test fail: expected 0x%.8lx"
-						   " actual 0x%.8lx\n",
-						   __FUNCTION__, __LINE__, ~compare, readback);
+					printf ("%s:%d: FPGA test fail: expected 0x%.8lx" " actual 0x%.8lx\n", __FUNCTION__, __LINE__, ~compare, readback);
 					pass = 0;
 					break;
 				}
 			}
-			if (!pass) break;
+			if (!pass)
+				break;
 		}
-		if (!pass) break;
+		if (!pass)
+			break;
 	}
 	if (pass) {
-		printf("FPGA inverting bus test passed\n");
-		print_fpga_revision();
-	}
-	else {
-		printf("** FPGA inverting bus test failed\n");
+		printf ("FPGA inverting bus test passed\n");
+		print_fpga_revision ();
+	} else {
+		printf ("** FPGA inverting bus test failed\n");
 	}
 	return pass;
 }
@@ -160,19 +157,17 @@ test_fpga_ibtr(void)
 /*
 * Set the active-low FPGA reset signal.
 */
-void
-fpga_reset(int assert)
+void fpga_reset (int assert)
 {
-    volatile immap_t *immap  = (immap_t *)CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;

-	PRINTF("%s:%d: RESET ", __FUNCTION__, __LINE__);
+	PRINTF ("%s:%d: RESET ", __FUNCTION__, __LINE__);
 	if (assert) {
 		immap->im_ioport.iop_pcdat &= ~(0x8000 >> FPGA_RESET_BIT_NUM);
-		PRINTF("asserted\n");
-	}
-	else {
+		PRINTF ("asserted\n");
+	} else {
 		immap->im_ioport.iop_pcdat |= (0x8000 >> FPGA_RESET_BIT_NUM);
-		PRINTF("deasserted\n");
+		PRINTF ("deasserted\n");
 	}
 }

@@ -181,54 +176,52 @@ fpga_reset(int assert)
 * Initialize the SelectMap interface.  We assume that the mode and the
 * initial state of all of the port pins have already been set!
 */
-void
-fpga_selectmap_init(void)
+void fpga_selectmap_init (void)
 {
-	PRINTF("%s:%d: Initialize SelectMap interface\n", __FUNCTION__, __LINE__);
-	fpga_pgm_fn(FALSE, FALSE, 0);   /* make sure program pin is inactive */
+	PRINTF ("%s:%d: Initialize SelectMap interface\n", __FUNCTION__,
+		__LINE__);
+	fpga_pgm_fn (FALSE, FALSE, 0);	/* make sure program pin is inactive */
 }


 /*
 * Initialize the fpga.  Return 1 on success, 0 on failure.
 */
-int
-gen860t_init_fpga(void)
+int gen860t_init_fpga (void)
 {
 	DECLARE_GLOBAL_DATA_PTR;

 	int i;

-	PRINTF("%s:%d: Initialize FPGA interface (relocation offset = 0x%.8lx)\n",
-			__FUNCTION__, __LINE__, gd->reloc_off);
-	fpga_init(gd->reloc_off);
-	fpga_selectmap_init();
+	PRINTF ("%s:%d: Initialize FPGA interface (relocation offset = 0x%.8lx)\n", __FUNCTION__, __LINE__, gd->reloc_off);
+	fpga_init (gd->reloc_off);
+	fpga_selectmap_init ();

-	for(i=0; i < CONFIG_FPGA_COUNT; i++) {
-		PRINTF("%s:%d: Adding fpga %d\n", __FUNCTION__, __LINE__, i);
-		fpga_add(fpga_xilinx, &fpga[i]);
+	for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
+		PRINTF ("%s:%d: Adding fpga %d\n", __FUNCTION__, __LINE__, i);
+		fpga_add (fpga_xilinx, &fpga[i]);
 	}
- 	return 1;
+	return 1;
 }


 /*
 * Set the FPGA's active-low SelectMap program line to the specified level
 */
-int
-fpga_pgm_fn(int assert, int flush, int cookie)
+int fpga_pgm_fn (int assert, int flush, int cookie)
 {
-    volatile immap_t *immap  = (immap_t *)CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;

-	PRINTF("%s:%d: FPGA PROGRAM ", __FUNCTION__, __LINE__);
+	PRINTF ("%s:%d: FPGA PROGRAM ", __FUNCTION__, __LINE__);

 	if (assert) {
-		immap->im_ioport.iop_padat &= ~(0x8000 >> FPGA_PROGRAM_BIT_NUM);
-		PRINTF("asserted\n");
-	}
-	else {
-		immap->im_ioport.iop_padat |= (0x8000 >> FPGA_PROGRAM_BIT_NUM);
-		PRINTF("deasserted\n");
+		immap->im_ioport.iop_padat &=
+			~(0x8000 >> FPGA_PROGRAM_BIT_NUM);
+		PRINTF ("asserted\n");
+	} else {
+		immap->im_ioport.iop_padat |=
+			(0x8000 >> FPGA_PROGRAM_BIT_NUM);
+		PRINTF ("deasserted\n");
 	}
 	return assert;
 }
@@ -238,18 +231,16 @@ fpga_pgm_fn(int assert, int flush, int cookie)
 * Test the state of the active-low FPGA INIT line.  Return 1 on INIT
 * asserted (low).
 */
-int
-fpga_init_fn(int cookie)
+int fpga_init_fn (int cookie)
 {
-    volatile immap_t *immap  = (immap_t *)CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;

-	PRINTF("%s:%d: INIT check... ", __FUNCTION__, __LINE__);
-	if(immap->im_cpm.cp_pbdat & (0x80000000 >> FPGA_INIT_BIT_NUM)) {
-		PRINTF("high\n");
+	PRINTF ("%s:%d: INIT check... ", __FUNCTION__, __LINE__);
+	if (immap->im_cpm.cp_pbdat & (0x80000000 >> FPGA_INIT_BIT_NUM)) {
+		PRINTF ("high\n");
 		return 0;
-	}
-	else {
-		PRINTF("low\n");
+	} else {
+		PRINTF ("low\n");
 		return 1;
 	}
 }
@@ -258,18 +249,16 @@ fpga_init_fn(int cookie)
 /*
 * Test the state of the active-high FPGA DONE pin
 */
-int
-fpga_done_fn(int cookie)
+int fpga_done_fn (int cookie)
 {
-    volatile immap_t *immap  = (immap_t *)CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;

-	PRINTF("%s:%d: DONE check... ", __FUNCTION__, __LINE__);
+	PRINTF ("%s:%d: DONE check... ", __FUNCTION__, __LINE__);
 	if (immap->im_cpm.cp_pbdat & (0x80000000 >> FPGA_DONE_BIT_NUM)) {
-		PRINTF("high\n");
+		PRINTF ("high\n");
 		return FPGA_SUCCESS;
-	}
-	else {
-		PRINTF("low\n");
+	} else {
+		PRINTF ("low\n");
 		return FPGA_FAIL;
 	}
 }
@@ -278,43 +267,40 @@ fpga_done_fn(int cookie)
 /*
 * Read FPGA SelectMap data.
 */
-int
-fpga_read_data_fn(unsigned char *data, int cookie)
+int fpga_read_data_fn (unsigned char *data, int cookie)
 {
-	vu_char *p = (vu_char *)SELECTMAP_BASE;
+	vu_char *p = (vu_char *) SELECTMAP_BASE;

 	*data = *p;
 #if 0
-	PRINTF("%s: Read 0x%x into 0x%p\n", __FUNCTION__, (int)data, data);
+	PRINTF ("%s: Read 0x%x into 0x%p\n", __FUNCTION__, (int) data, data);
 #endif
-	return (int)data;
+	return (int) data;
 }


 /*
 * Write data to the FPGA SelectMap port
 */
-int
-fpga_write_data_fn(unsigned char data, int flush, int cookie)
+int fpga_write_data_fn (unsigned char data, int flush, int cookie)
 {
-	vu_char *p = (vu_char *)SELECTMAP_BASE;
+	vu_char *p = (vu_char *) SELECTMAP_BASE;

 #if 0
-	PRINTF("%s: Write Data 0x%x\n", __FUNCTION__, (int)data);
+	PRINTF ("%s: Write Data 0x%x\n", __FUNCTION__, (int) data);
 #endif
 	*p = data;
-	return (int)data;
+	return (int) data;
 }


 /*
 * Abort and FPGA operation
 */
-int
-fpga_abort_fn(int cookie)
+int fpga_abort_fn (int cookie)
 {
-	PRINTF("%s:%d: FPGA program sequence aborted\n",
-		   __FUNCTION__, __LINE__);
+	PRINTF ("%s:%d: FPGA program sequence aborted\n",
+		__FUNCTION__, __LINE__);
 	return FPGA_FAIL;
 }

@@ -324,11 +310,10 @@ fpga_abort_fn(int cookie)
 * FPGA reset is asserted to keep the FPGA from starting up after
 * configuration.
 */
-int
-fpga_pre_config_fn(int cookie)
+int fpga_pre_config_fn (int cookie)
 {
-	PRINTF("%s:%d: FPGA pre-configuration\n", __FUNCTION__, __LINE__);
-	fpga_reset(TRUE);
+	PRINTF ("%s:%d: FPGA pre-configuration\n", __FUNCTION__, __LINE__);
+	fpga_reset (TRUE);
 	return 0;
 }

@@ -337,22 +322,21 @@ fpga_pre_config_fn(int cookie)
 * FPGA post configuration function. Blip the FPGA reset line and then see if
 * the FPGA appears to be running.
 */
-int
-fpga_post_config_fn(int cookie)
+int fpga_post_config_fn (int cookie)
 {
 	int rc;

-	PRINTF("%s:%d: FPGA post configuration\n", __FUNCTION__, __LINE__);
-	fpga_reset(TRUE);
-	udelay(1000);
-	fpga_reset(FALSE);
+	PRINTF ("%s:%d: FPGA post configuration\n", __FUNCTION__, __LINE__);
+	fpga_reset (TRUE);
+	udelay (1000);
+	fpga_reset (FALSE);
 	udelay (1000);

 	/*
 	 * Use the FPGA,s inverting bus test register to do a simple test of the
 	 * processor interface.
 	 */
-	rc = test_fpga_ibtr();
+	rc = test_fpga_ibtr ();
 	return rc;
 }

@@ -367,32 +351,27 @@ fpga_post_config_fn(int cookie)
 * going low during configuration, so there is no need for a separate error
 * function.
 */
-int
-fpga_clk_fn(int assert_clk, int flush, int cookie)
+int fpga_clk_fn (int assert_clk, int flush, int cookie)
 {
 	return assert_clk;
 }

-int
-fpga_cs_fn(int assert_cs, int flush, int cookie)
+int fpga_cs_fn (int assert_cs, int flush, int cookie)
 {
 	return assert_cs;
 }

-int
-fpga_wr_fn(int assert_write, int flush, int cookie)
+int fpga_wr_fn (int assert_write, int flush, int cookie)
 {
 	return assert_write;
 }

-int
-fpga_err_fn(int cookie)
+int fpga_err_fn (int cookie)
 {
 	return 0;
 }

-int
-fpga_busy_fn(int cookie)
+int fpga_busy_fn (int cookie)
 {
 	return 0;
 }
--- a/board/gen860t/gen860t.c
+++ b/board/gen860t/gen860t.c
@@ -94,7 +94,7 @@ const uint sdram_upm_table[] = {
 	0xfffffc05, 0xffffffff, 0xffffffff, 0xffffffff,
 	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
 	/* exception     (offset 0x3C in upm ram) */
-   };
+};

 const uint selectmap_upm_table[] = {
 	/* single read   (offset 0x00 in upm ram) */
@@ -124,63 +124,61 @@ const uint selectmap_upm_table[] = {
 /*
 * Check board identity.  Always successful (gives information only)
 */
-int
-checkboard(void)
+int checkboard (void)
 {
 	DECLARE_GLOBAL_DATA_PTR;

-    unsigned char *s;
-    unsigned char buf[64];
-    int i;
+	unsigned char *s;
+	unsigned char buf[64];
+	int i;

-    i = getenv_r("board_id", buf, sizeof(buf));
-    s = (i>0) ? buf : NULL;
+	i = getenv_r ("board_id", buf, sizeof (buf));
+	s = (i > 0) ? buf : NULL;

 	if (s) {
-		printf("%s ", s);
+		printf ("%s ", s);
 	} else {
-		printf("<unknown> ");
+		printf ("<unknown> ");
 	}

-    i = getenv_r("serial#", buf, sizeof(buf));
-    s = (i>0) ? buf : NULL;
+	i = getenv_r ("serial#", buf, sizeof (buf));
+	s = (i > 0) ? buf : NULL;

 	if (s) {
-		printf("S/N %s\n", s);
+		printf ("S/N %s\n", s);
 	} else {
-		printf("S/N <unknown>\n");
+		printf ("S/N <unknown>\n");
 	}

-    printf("CPU at %s MHz, ",strmhz(buf, gd->cpu_clk));
-	printf("local bus at %s MHz\n", strmhz(buf, gd->bus_clk));
-    return (0);
+	printf ("CPU at %s MHz, ", strmhz (buf, gd->cpu_clk));
+	printf ("local bus at %s MHz\n", strmhz (buf, gd->bus_clk));
+	return (0);
 }

 /*
 * Initialize SDRAM
 */
-long int
-initdram(int board_type)
+long int initdram (int board_type)
 {
-    volatile immap_t     *immr  = (immap_t *)CFG_IMMR;
-    volatile memctl8xx_t *memctl = &immr->im_memctl;
+	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immr->im_memctl;

-    upmconfig(UPMA,
-			  (uint *)sdram_upm_table,
-			  sizeof(sdram_upm_table) / sizeof(uint)
-			 );
+	upmconfig (UPMA,
+		   (uint *) sdram_upm_table,
+		   sizeof (sdram_upm_table) / sizeof (uint)
+		);

-    /*
-     * Setup MAMR register
-     */
-    memctl->memc_mptpr = CFG_MPTPR_1BK_8K;
-    memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
+	/*
+	 * Setup MAMR register
+	 */
+	memctl->memc_mptpr = CFG_MPTPR_1BK_8K;
+	memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */

-    /*
-     * Map CS1* to SDRAM bank
-     */
-    memctl->memc_or1 = CFG_OR1;
-    memctl->memc_br1 = CFG_BR1;
+	/*
+	 * Map CS1* to SDRAM bank
+	 */
+	memctl->memc_or1 = CFG_OR1;
+	memctl->memc_br1 = CFG_BR1;

 	/*
 	 * Perform SDRAM initialization sequence:
@@ -193,31 +191,31 @@ initdram(int board_type)
 	 * Program SDRAM for standard operation, sequential burst, burst length
 	 * of 4, CAS latency of 2.
 	 */
-    memctl->memc_mar = 0x00000000;
+	memctl->memc_mar = 0x00000000;
 	memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 |
-					   MCR_MLCF(0) | UPMA_NOP_ADDR;
-	udelay(200);
-    memctl->memc_mar = 0x00000000;
+		MCR_MLCF (0) | UPMA_NOP_ADDR;
+	udelay (200);
+	memctl->memc_mar = 0x00000000;
 	memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 |
-					   MCR_MLCF(4) | UPMA_PRECHARGE_ADDR;
+		MCR_MLCF (4) | UPMA_PRECHARGE_ADDR;

-    memctl->memc_mar = 0x00000000;
+	memctl->memc_mar = 0x00000000;
 	memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 |
-					   MCR_MLCF(2) | UPM_REFRESH_ADDR;
+		MCR_MLCF (2) | UPM_REFRESH_ADDR;

-    memctl->memc_mar = 0x00000088;
+	memctl->memc_mar = 0x00000088;
 	memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 |
-					   MCR_MLCF(1) | UPMA_MRS_ADDR;
+		MCR_MLCF (1) | UPMA_MRS_ADDR;

-    memctl->memc_mar = 0x00000000;
+	memctl->memc_mar = 0x00000000;
 	memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 |
-					   MCR_MLCF(0) | UPMA_NOP_ADDR;
+		MCR_MLCF (0) | UPMA_NOP_ADDR;
 	/*
 	 * Enable refresh
 	 */
-    memctl->memc_mamr |= MAMR_PTAE;
+	memctl->memc_mamr |= MAMR_PTAE;

-    return (SDRAM_SIZE);
+	return (SDRAM_SIZE);
 }

 /*
@@ -225,42 +223,39 @@ initdram(int board_type)
 * The DOC lives in the CS2* space
 */
 #if (CONFIG_COMMANDS & CFG_CMD_DOC)
-extern void
-doc_probe(ulong physadr);
+extern void doc_probe (ulong physadr);

-void
-doc_init(void)
+void doc_init (void)
 {
-	printf("Probing at 0x%.8x: ", DOC_BASE);
-	doc_probe(DOC_BASE);
+	printf ("Probing at 0x%.8x: ", DOC_BASE);
+	doc_probe (DOC_BASE);
 }
 #endif

 /*
 * Miscellaneous intialization
 */
-int
-misc_init_r (void)
+int misc_init_r (void)
 {
-    volatile immap_t     *immr  = (immap_t *)CFG_IMMR;
-    volatile memctl8xx_t *memctl = &immr->im_memctl;
+	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immr->im_memctl;

 	/*
 	 * Set up UPMB to handle the Virtex FPGA SelectMap interface
 	 */
-	upmconfig(UPMB, (uint *)selectmap_upm_table,
-			  sizeof(selectmap_upm_table) / sizeof(uint));
+	upmconfig (UPMB, (uint *) selectmap_upm_table,
+		   sizeof (selectmap_upm_table) / sizeof (uint));

-    memctl->memc_mbmr = 0x0;
+	memctl->memc_mbmr = 0x0;

-	config_mpc8xx_ioports(immr);
+	config_mpc8xx_ioports (immr);

 #if (CONFIG_COMMANDS & CFG_CMD_MII)
-	mii_init();
+	mii_init ();
 #endif

 #if (CONFIG_FPGA)
-	gen860t_init_fpga();
+	gen860t_init_fpga ();
 #endif
 	return 0;
 }
@@ -268,8 +263,7 @@ misc_init_r (void)
 /*
 * Final init hook before entering command loop.
 */
-int
-last_stage_init(void)
+int last_stage_init (void)
 {
 #if !defined(CONFIG_SC)
 	unsigned char buf[256];
@@ -278,15 +272,15 @@ last_stage_init(void)
 	/*
 	 * Turn the beeper volume all the way down in case this is a warm boot.
 	 */
-	set_beeper_volume(-64);
-	init_beeper();
+	set_beeper_volume (-64);
+	init_beeper ();

 	/*
 	 * Read the environment to see what to do with the beeper
 	 */
-    i = getenv_r("beeper", buf, sizeof(buf));
+	i = getenv_r ("beeper", buf, sizeof (buf));
 	if (i > 0) {
-		do_beeper(buf);
+		do_beeper (buf);
 	}
 #endif
 	return 0;
@@ -295,11 +289,10 @@ last_stage_init(void)
 /*
 * Stub to make POST code happy.  Can't self-poweroff, so just hang.
 */
-void
-board_poweroff(void)
+void board_poweroff (void)
 {
-	puts("### Please power off the board ###\n");
-    while (1);
+	puts ("### Please power off the board ###\n");
+	while (1);
 }

 #ifdef CONFIG_POST
@@ -307,9 +300,9 @@ board_poweroff(void)
 * Returns 1 if keys pressed to start the power-on long-running tests
 * Called from board_init_f().
 */
-int post_hotkeys_pressed(void)
+int post_hotkeys_pressed (void)
 {
-	return 0;	/* No hotkeys supported */
+	return 0;		/* No hotkeys supported */
 }
 #endif

--- a/board/gen860t/ioport.c
+++ b/board/gen860t/ioport.c
@@ -199,16 +199,16 @@ const mpc8xx_iop_conf_t iop_conf_tab[NUM_PORTS][PORT_BITS] = {
 * Configure the MPC8XX I/O ports per the ioport configuration table
 * (taken from ./cpu/mpc8260/cpu_init.c)
 */
-void
-config_mpc8xx_ioports(volatile immap_t *immr)
+void config_mpc8xx_ioports (volatile immap_t * immr)
 {
-    int portnum;
+	int portnum;

-    for (portnum = 0; portnum < NUM_PORTS; portnum++) {
+	for (portnum = 0; portnum < NUM_PORTS; portnum++) {
 		uint pmsk = 0, ppar = 0, psor = 0, pdir = 0;
 		uint podr = 0, pdat = 0, pint = 0;
 		uint msk = 1;
-		mpc8xx_iop_conf_t *iopc = (mpc8xx_iop_conf_t *)&iop_conf_tab[portnum][0];
+		mpc8xx_iop_conf_t *iopc =
+			(mpc8xx_iop_conf_t *) & iop_conf_tab[portnum][0];
 		mpc8xx_iop_conf_t *eiopc = iopc + PORT_BITS;

 		/*
@@ -216,104 +216,132 @@ config_mpc8xx_ioports(volatile immap_t *immr)
 		 * in the configuration tables.
 		 */
 		if (portnum != 1) {
-			iopc = (mpc8xx_iop_conf_t *)&iop_conf_tab[portnum][2];
+			iopc = (mpc8xx_iop_conf_t *) &
+				iop_conf_tab[portnum][2];
 		}

 		/*
 		 * NOTE: index 0 refers to pin 17, index 17 refers to pin 0
 		 */
 		while (iopc < eiopc) {
-	    	if (iopc->conf) {
+			if (iopc->conf) {
 				pmsk |= msk;
-				if (iopc->ppar) ppar |= msk;
-				if (iopc->psor) psor |= msk;
-				if (iopc->pdir) pdir |= msk;
-				if (iopc->podr) podr |= msk;
-				if (iopc->pdat) pdat |= msk;
-				if (iopc->pint) pint |= msk;
-		    }
-		    msk <<= 1;
-	  	  iopc++;
+				if (iopc->ppar)
+					ppar |= msk;
+				if (iopc->psor)
+					psor |= msk;
+				if (iopc->pdir)
+					pdir |= msk;
+				if (iopc->podr)
+					podr |= msk;
+				if (iopc->pdat)
+					pdat |= msk;
+				if (iopc->pint)
+					pint |= msk;
+			}
+			msk <<= 1;
+			iopc++;
 		}

-		PRINTF("%s:%d:\n  portnum=%d ", __FUNCTION__, __LINE__, portnum);
+		PRINTF ("%s:%d:\n  portnum=%d ", __FUNCTION__, __LINE__,
+			portnum);
 #ifdef IOPORT_DEBUG
-		switch(portnum) {
-			case 0: printf("(A)\n"); break;
-			case 1: printf("(B)\n"); break;
-			case 2: printf("(C)\n"); break;
-			case 3: printf("(D)\n"); break;
-			default: printf("(?)\n"); break;
+		switch (portnum) {
+		case 0:
+			printf ("(A)\n");
+			break;
+		case 1:
+			printf ("(B)\n");
+			break;
+		case 2:
+			printf ("(C)\n");
+			break;
+		case 3:
+			printf ("(D)\n");
+			break;
+		default:
+			printf ("(?)\n");
+			break;
 		}
 #endif
-		PRINTF("  ppar=0x%.8x  pdir=0x%.8x  podr=0x%.8x\n"
-			   "  pdat=0x%.8x  psor=0x%.8x  pint=0x%.8x  pmsk=0x%.8x\n",
-			   ppar, pdir, podr, pdat, psor, pint, pmsk);
+		PRINTF ("  ppar=0x%.8x  pdir=0x%.8x  podr=0x%.8x\n"
+			"  pdat=0x%.8x  psor=0x%.8x  pint=0x%.8x  pmsk=0x%.8x\n",
+			ppar, pdir, podr, pdat, psor, pint, pmsk);

 		/*
 		 * Have to handle the ioports on a port-by-port basis since there
 		 * are three different flavors.
 		 */
 		if (pmsk != 0) {
-		    uint tpmsk = ~pmsk;
+			uint tpmsk = ~pmsk;

-			if (0 == portnum) { /* port A */
-		    	immr->im_ioport.iop_papar &= tpmsk;
-		    	immr->im_ioport.iop_padat =
-					(immr->im_ioport.iop_padat & tpmsk) | pdat;
-		    	immr->im_ioport.iop_padir =
-					(immr->im_ioport.iop_padir & tpmsk) | pdir;
-		    	immr->im_ioport.iop_paodr =
-					(immr->im_ioport.iop_paodr & tpmsk) | podr;
-		    	immr->im_ioport.iop_papar |= ppar;
-			}
-			else if (1 == portnum) { /* port B */
-		    	immr->im_cpm.cp_pbpar &= tpmsk;
-		    	immr->im_cpm.cp_pbdat = (immr->im_cpm.cp_pbdat & tpmsk) | pdat;
-		    	immr->im_cpm.cp_pbdir = (immr->im_cpm.cp_pbdir & tpmsk) | pdir;
-		    	immr->im_cpm.cp_pbodr = (immr->im_cpm.cp_pbodr & tpmsk) | podr;
-		    	immr->im_cpm.cp_pbpar |= ppar;
-			}
-			else if (2 == portnum) { /* port C */
-		    	immr->im_ioport.iop_pcpar &= tpmsk;
-		    	immr->im_ioport.iop_pcdat =
-					(immr->im_ioport.iop_pcdat & tpmsk) | pdat;
-		    	immr->im_ioport.iop_pcdir =
-					(immr->im_ioport.iop_pcdir & tpmsk) | pdir;
-		    	immr->im_ioport.iop_pcint =
-					(immr->im_ioport.iop_pcint & tpmsk) | pint;
-		    	immr->im_ioport.iop_pcso =
-					(immr->im_ioport.iop_pcso & tpmsk) | psor;
-		    	immr->im_ioport.iop_pcpar |= ppar;
-			}
-			else if (3 == portnum) { /* port D */
-		    	immr->im_ioport.iop_pdpar &= tpmsk;
-		    	immr->im_ioport.iop_pddat =
-					(immr->im_ioport.iop_pddat & tpmsk) | pdat;
-		    	immr->im_ioport.iop_pddir =
-					(immr->im_ioport.iop_pddir & tpmsk) | pdir;
-		    	immr->im_ioport.iop_pdpar |= ppar;
+			if (0 == portnum) {	/* port A */
+				immr->im_ioport.iop_papar &= tpmsk;
+				immr->im_ioport.iop_padat =
+					(immr->im_ioport.
+					 iop_padat & tpmsk) | pdat;
+				immr->im_ioport.iop_padir =
+					(immr->im_ioport.
+					 iop_padir & tpmsk) | pdir;
+				immr->im_ioport.iop_paodr =
+					(immr->im_ioport.
+					 iop_paodr & tpmsk) | podr;
+				immr->im_ioport.iop_papar |= ppar;
+			} else if (1 == portnum) {	/* port B */
+				immr->im_cpm.cp_pbpar &= tpmsk;
+				immr->im_cpm.cp_pbdat =
+					(immr->im_cpm.
+					 cp_pbdat & tpmsk) | pdat;
+				immr->im_cpm.cp_pbdir =
+					(immr->im_cpm.
+					 cp_pbdir & tpmsk) | pdir;
+				immr->im_cpm.cp_pbodr =
+					(immr->im_cpm.
+					 cp_pbodr & tpmsk) | podr;
+				immr->im_cpm.cp_pbpar |= ppar;
+			} else if (2 == portnum) {	/* port C */
+				immr->im_ioport.iop_pcpar &= tpmsk;
+				immr->im_ioport.iop_pcdat =
+					(immr->im_ioport.
+					 iop_pcdat & tpmsk) | pdat;
+				immr->im_ioport.iop_pcdir =
+					(immr->im_ioport.
+					 iop_pcdir & tpmsk) | pdir;
+				immr->im_ioport.iop_pcint =
+					(immr->im_ioport.
+					 iop_pcint & tpmsk) | pint;
+				immr->im_ioport.iop_pcso =
+					(immr->im_ioport.
+					 iop_pcso & tpmsk) | psor;
+				immr->im_ioport.iop_pcpar |= ppar;
+			} else if (3 == portnum) {	/* port D */
+				immr->im_ioport.iop_pdpar &= tpmsk;
+				immr->im_ioport.iop_pddat =
+					(immr->im_ioport.
+					 iop_pddat & tpmsk) | pdat;
+				immr->im_ioport.iop_pddir =
+					(immr->im_ioport.
+					 iop_pddir & tpmsk) | pdir;
+				immr->im_ioport.iop_pdpar |= ppar;
 			}
 		}
-    }
+	}

-	PRINTF("%s:%d: Port A:\n  papar=0x%.4x  padir=0x%.4x"
-		   "  paodr=0x%.4x\n  padat=0x%.4x\n", __FUNCTION__, __LINE__,
-		   immr->im_ioport.iop_papar, immr->im_ioport.iop_padir,
-		   immr->im_ioport.iop_paodr, immr->im_ioport.iop_padat);
-	PRINTF("%s:%d: Port B:\n  pbpar=0x%.8x  pbdir=0x%.8x"
-		   "  pbodr=0x%.8x\n  pbdat=0x%.8x\n", __FUNCTION__, __LINE__,
-		   immr->im_cpm.cp_pbpar, immr->im_cpm.cp_pbdir,
-		   immr->im_cpm.cp_pbodr, immr->im_cpm.cp_pbdat);
-	PRINTF("%s:%d: Port C:\n  pcpar=0x%.4x  pcdir=0x%.4x"
-		   "  pcdat=0x%.4x\n  pcso=0x%.4x  pcint=0x%.4x\n  ",
-		   __FUNCTION__, __LINE__, immr->im_ioport.iop_pcpar,
-		   immr->im_ioport.iop_pcdir, immr->im_ioport.iop_pcdat,
-		   immr->im_ioport.iop_pcso, immr->im_ioport.iop_pcint);
-	PRINTF("%s:%d: Port D:\n  pdpar=0x%.4x  pddir=0x%.4x"
-		   "  pddat=0x%.4x\n", __FUNCTION__, __LINE__,
-		   immr->im_ioport.iop_pdpar, immr->im_ioport.iop_pddir,
-		   immr->im_ioport.iop_pddat);
+	PRINTF ("%s:%d: Port A:\n  papar=0x%.4x  padir=0x%.4x"
+		"  paodr=0x%.4x\n  padat=0x%.4x\n", __FUNCTION__, __LINE__,
+		immr->im_ioport.iop_papar, immr->im_ioport.iop_padir,
+		immr->im_ioport.iop_paodr, immr->im_ioport.iop_padat);
+	PRINTF ("%s:%d: Port B:\n  pbpar=0x%.8x  pbdir=0x%.8x"
+		"  pbodr=0x%.8x\n  pbdat=0x%.8x\n", __FUNCTION__, __LINE__,
+		immr->im_cpm.cp_pbpar, immr->im_cpm.cp_pbdir,
+		immr->im_cpm.cp_pbodr, immr->im_cpm.cp_pbdat);
+	PRINTF ("%s:%d: Port C:\n  pcpar=0x%.4x  pcdir=0x%.4x"
+		"  pcdat=0x%.4x\n  pcso=0x%.4x  pcint=0x%.4x\n  ",
+		__FUNCTION__, __LINE__, immr->im_ioport.iop_pcpar,
+		immr->im_ioport.iop_pcdir, immr->im_ioport.iop_pcdat,
+		immr->im_ioport.iop_pcso, immr->im_ioport.iop_pcint);
+	PRINTF ("%s:%d: Port D:\n  pdpar=0x%.4x  pddir=0x%.4x"
+		"  pddat=0x%.4x\n", __FUNCTION__, __LINE__,
+		immr->im_ioport.iop_pdpar, immr->im_ioport.iop_pddir,
+		immr->im_ioport.iop_pddat);
 }
-
-/* vim: set ts=4 sw=4 tw=78: */
--- a/board/gw8260/gw8260.c
+++ b/board/gw8260/gw8260.c
@@ -212,16 +212,17 @@ const iop_conf_t iop_conf_tab[4][32] = {
 /*								     */
 /*								     */
 /*********************************************************************/
-int checkboard(void)
+int checkboard (void)
 {
-    char *str;
-    puts ("Board: Advent Networks gw8260\n");
+	char *str;

-    str = getenv("serial#");
-    if (str != NULL) {
-	printf("SN:    %s\n", str);
-    }
-    return 0;
+	puts ("Board: Advent Networks gw8260\n");
+
+	str = getenv ("serial#");
+	if (str != NULL) {
+		printf ("SN:    %s\n", str);
+	}
+	return 0;
 }


@@ -246,30 +247,31 @@ int checkboard(void)
 /*   May cloober fr0.						     */
 /*								     */
 /*********************************************************************/
-static void move64(unsigned long long *src, unsigned long long *dest)
+static void move64 (unsigned long long *src, unsigned long long *dest)
 {
-	asm ("lfd  0, 0(3)\n\t" /* fpr0	  =  *scr	*/
-	 "stfd 0, 0(4)"		/* *dest  =  fpr0	*/
-	 : : : "fr0" );		/* Clobbers fr0		*/
-    return;
+	asm ("lfd  0, 0(3)\n\t"	/* fpr0   =  *scr       */
+	     "stfd 0, 0(4)"	/* *dest  =  fpr0       */
+      : : : "fr0");		/* Clobbers fr0         */
+	return;
 }


 #if defined (CFG_DRAM_TEST_DATA)

-unsigned long long pattern[]= {
-    0xaaaaaaaaaaaaaaaa,
-    0xcccccccccccccccc,
-    0xf0f0f0f0f0f0f0f0,
-    0xff00ff00ff00ff00,
-    0xffff0000ffff0000,
-    0xffffffff00000000,
-    0x00000000ffffffff,
-    0x0000ffff0000ffff,
-    0x00ff00ff00ff00ff,
-    0x0f0f0f0f0f0f0f0f,
-    0x3333333333333333,
-    0x5555555555555555};
+unsigned long long pattern[] = {
+	0xaaaaaaaaaaaaaaaa,
+	0xcccccccccccccccc,
+	0xf0f0f0f0f0f0f0f0,
+	0xff00ff00ff00ff00,
+	0xffff0000ffff0000,
+	0xffffffff00000000,
+	0x00000000ffffffff,
+	0x0000ffff0000ffff,
+	0x00ff00ff00ff00ff,
+	0x0f0f0f0f0f0f0f0f,
+	0x3333333333333333,
+	0x5555555555555555
+};

 /*********************************************************************/
 /* NAME:  mem_test_data() -  test data lines for shorts and opens    */
@@ -315,34 +317,34 @@ unsigned long long pattern[]= {
 /*  Assumes only one one SDRAM bank				     */
 /*								     */
 /*********************************************************************/
-int mem_test_data(void)
+int mem_test_data (void)
 {
-    unsigned long long * pmem =
-	(unsigned long long *)CFG_SDRAM_BASE ;
-    unsigned long long temp64;
-    int num_patterns = sizeof(pattern)/ sizeof(pattern[0]);
-    int i;
-    unsigned int hi, lo;
+	unsigned long long *pmem = (unsigned long long *) CFG_SDRAM_BASE;
+	unsigned long long temp64;
+	int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
+	int i;
+	unsigned int hi, lo;

-    for ( i = 0; i < num_patterns; i++) {
-	move64(&(pattern[i]), pmem);
-	move64(pmem, &temp64);
+	for (i = 0; i < num_patterns; i++) {
+		move64 (&(pattern[i]), pmem);
+		move64 (pmem, &temp64);

-	/* hi = (temp64>>32) & 0xffffffff;	    */
-	/* lo = temp64 & 0xffffffff;		    */
-	/* printf("\ntemp64 = 0x%08x%08x", hi, lo); */
+		/* hi = (temp64>>32) & 0xffffffff;          */
+		/* lo = temp64 & 0xffffffff;                */
+		/* printf("\ntemp64 = 0x%08x%08x", hi, lo); */

-	hi = (pattern[i]>>32) & 0xffffffff;
-	lo = pattern[i] & 0xffffffff;
-	/* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo);  */
+		hi = (pattern[i] >> 32) & 0xffffffff;
+		lo = pattern[i] & 0xffffffff;
+		/* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo);  */

-	if (temp64 != pattern[i]){
-	    printf ("\n   Data Test Failed, pattern 0x%08x%08x", hi, lo);
-	    return 1;
+		if (temp64 != pattern[i]) {
+			printf ("\n   Data Test Failed, pattern 0x%08x%08x",
+				hi, lo);
+			return 1;
+		}
 	}
-    }

-    return 0;
+	return 0;
 }
 #endif /* CFG_DRAM_TEST_DATA */

@@ -368,25 +370,26 @@ int mem_test_data(void)
 /*								     */
 /*								     */
 /*********************************************************************/
-int mem_test_address(void)
+int mem_test_address (void)
 {
-    volatile unsigned int * pmem = (volatile unsigned int *)CFG_SDRAM_BASE ;
-    const unsigned int size = (CFG_SDRAM_SIZE * 1024 * 1024)/4;
-    unsigned int i;
+	volatile unsigned int *pmem =
+		(volatile unsigned int *) CFG_SDRAM_BASE;
+	const unsigned int size = (CFG_SDRAM_SIZE * 1024 * 1024) / 4;
+	unsigned int i;

-    /* write address to each location */
-    for ( i = 0; i < size; i++) {
-	pmem[i] = i;
-    }
-
-    /* verify each loaction */
-    for ( i = 0; i < size; i++) {
-	if (pmem[i] != i) {
-	    printf("\n   Address Test Failed at 0x%x", i);
-	    return 1;
+	/* write address to each location */
+	for (i = 0; i < size; i++) {
+		pmem[i] = i;
 	}
-    }
-    return 0;
+
+	/* verify each loaction */
+	for (i = 0; i < size; i++) {
+		if (pmem[i] != i) {
+			printf ("\n   Address Test Failed at 0x%x", i);
+			return 1;
+		}
+	}
+	return 0;
 }
 #endif /* CFG_DRAM_TEST_ADDRESS */

@@ -418,39 +421,35 @@ int mem_test_address(void)
 /*								     */
 /*								     */
 /*********************************************************************/
-int mem_march(volatile unsigned long long * base,
-	      unsigned int size,
-	      unsigned long long rmask,
-	      unsigned long long wmask,
-	      short read,
-	      short write)
+int mem_march (volatile unsigned long long *base,
+	       unsigned int size,
+	       unsigned long long rmask,
+	       unsigned long long wmask, short read, short write)
 {
-    unsigned int i;
-    unsigned long long temp;
-    unsigned int hitemp, lotemp, himask, lomask;
+	unsigned int i;
+	unsigned long long temp;
+	unsigned int hitemp, lotemp, himask, lomask;

-    for (i = 0 ; i < size ; i++) {
-	if (read != 0) {
-	    /* temp = base[i]; */
-	    move64 ((unsigned long long *)&(base[i]), &temp);
-	    if (rmask != temp) {
-		hitemp = (temp>>32) & 0xffffffff;
-		lotemp = temp & 0xffffffff;
-		himask = (rmask>>32) & 0xffffffff;
-		lomask = rmask & 0xffffffff;
+	for (i = 0; i < size; i++) {
+		if (read != 0) {
+			/* temp = base[i]; */
+			move64 ((unsigned long long *) &(base[i]), &temp);
+			if (rmask != temp) {
+				hitemp = (temp >> 32) & 0xffffffff;
+				lotemp = temp & 0xffffffff;
+				himask = (rmask >> 32) & 0xffffffff;
+				lomask = rmask & 0xffffffff;

-		printf("\n Walking one's test failed: address = 0x%08x,"
-		       "\n\texpected 0x%08x%08x, found 0x%08x%08x",
-		       i<<3, himask, lomask, hitemp, lotemp);
-		return 1;
-	    }
+				printf ("\n Walking one's test failed: address = 0x%08x," "\n\texpected 0x%08x%08x, found 0x%08x%08x", i << 3, himask, lomask, hitemp, lotemp);
+				return 1;
+			}
+		}
+		if (write != 0) {
+			/*  base[i] = wmask; */
+			move64 (&wmask, (unsigned long long *) &(base[i]));
+		}
 	}
-	if ( write != 0 ) {
-	   /*  base[i] = wmask; */
-	    move64 (&wmask, (unsigned long long *)&(base[i]));
-	}
-    }
-    return 0;
+	return 0;
 }
 #endif /* CFG_DRAM_TEST_WALK */

@@ -480,43 +479,44 @@ int mem_march(volatile unsigned long long * base,
 /*								     */
 /*								     */
 /*********************************************************************/
-int mem_test_walk(void)
+int mem_test_walk (void)
 {
-    unsigned long long mask;
-    volatile unsigned long long * pmem =
-	(volatile unsigned long long *)CFG_SDRAM_BASE ;
-    const unsigned long size = (CFG_SDRAM_SIZE * 1024 * 1024)/8;
+	unsigned long long mask;
+	volatile unsigned long long *pmem =
+		(volatile unsigned long long *) CFG_SDRAM_BASE;
+	const unsigned long size = (CFG_SDRAM_SIZE * 1024 * 1024) / 8;

-    unsigned int i;
-    mask = 0x01;
+	unsigned int i;

-    printf("Initial Pass");
-    mem_march(pmem,size,0x0,0x1,0,1);
+	mask = 0x01;

-    printf("\b\b\b\b\b\b\b\b\b\b\b\b");
-    printf("		");
-    printf("\b\b\b\b\b\b\b\b\b\b\b\b");
+	printf ("Initial Pass");
+	mem_march (pmem, size, 0x0, 0x1, 0, 1);

-    for (i = 0 ; i < 63 ; i++) {
-	printf("Pass %2d", i+2);
-	if ( mem_march(pmem,size, mask,mask << 1, 1, 1) != 0 ){
-	    /*printf("mask: 0x%x, pass: %d, ", mask, i);*/
-	    return 1;
+	printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
+	printf ("		");
+	printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
+
+	for (i = 0; i < 63; i++) {
+		printf ("Pass %2d", i + 2);
+		if (mem_march (pmem, size, mask, mask << 1, 1, 1) != 0) {
+			/*printf("mask: 0x%x, pass: %d, ", mask, i); */
+			return 1;
+		}
+		mask = mask << 1;
+		printf ("\b\b\b\b\b\b\b");
 	}
-	mask = mask<<1;
-	printf("\b\b\b\b\b\b\b");
-    }

-    printf("Last Pass");
-    if (mem_march(pmem, size, 0, mask, 0, 1) != 0) {
-	/* printf("mask: 0x%x", mask); */
-	return 1;
-    }
-    printf("\b\b\b\b\b\b\b\b\b");
-    printf("	     ");
-    printf("\b\b\b\b\b\b\b\b\b");
+	printf ("Last Pass");
+	if (mem_march (pmem, size, 0, mask, 0, 1) != 0) {
+		/* printf("mask: 0x%x", mask); */
+		return 1;
+	}
+	printf ("\b\b\b\b\b\b\b\b\b");
+	printf ("	     ");
+	printf ("\b\b\b\b\b\b\b\b\b");

-    return 0;
+	return 0;
 }

 /*********************************************************************/
@@ -542,46 +542,46 @@ int mem_test_walk(void)
 /*								     */
 /*								     */
 /*********************************************************************/
-int testdram(void)
+int testdram (void)
 {
-    char *s;
-    int rundata, runaddress, runwalk;
+	char *s;
+	int rundata, runaddress, runwalk;

-    s = getenv ("testdramdata");
-    rundata = (s && (*s == 'y')) ? 1 : 0;
-    s = getenv ("testdramaddress");
-    runaddress = (s && (*s == 'y')) ? 1 : 0;
-    s = getenv ("testdramwalk");
-    runwalk = (s && (*s == 'y')) ? 1 : 0;
+	s = getenv ("testdramdata");
+	rundata = (s && (*s == 'y')) ? 1 : 0;
+	s = getenv ("testdramaddress");
+	runaddress = (s && (*s == 'y')) ? 1 : 0;
+	s = getenv ("testdramwalk");
+	runwalk = (s && (*s == 'y')) ? 1 : 0;

-    if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
-	printf("Testing RAM ... ");
-    }
-#ifdef CFG_DRAM_TEST_DATA
-    if (rundata == 1) {
-	if (mem_test_data() == 1){
-	    return 1;
+	if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
+		printf ("Testing RAM ... ");
+	}
+#ifdef CFG_DRAM_TEST_DATA
+	if (rundata == 1) {
+		if (mem_test_data () == 1) {
+			return 1;
+		}
 	}
-    }
 #endif
 #ifdef CFG_DRAM_TEST_ADDRESS
-    if (runaddress == 1) {
-	if (mem_test_address() == 1){
-	    return 1;
+	if (runaddress == 1) {
+		if (mem_test_address () == 1) {
+			return 1;
+		}
 	}
-    }
 #endif
 #ifdef CFG_DRAM_TEST_WALK
-    if (runwalk == 1) {
-	if (mem_test_walk() == 1){
-	    return 1;
+	if (runwalk == 1) {
+		if (mem_test_walk () == 1) {
+			return 1;
+		}
 	}
-    }
 #endif
-    if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
-	printf("passed");
-    }
-    return 0;
+	if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
+		printf ("passed");
+	}
+	return 0;

 }
 #endif /* CFG_DRAM_TEST */
@@ -606,52 +606,52 @@ int testdram(void)
 /*								     */
 /*								     */
 /*********************************************************************/
-long int initdram(int board_type)
+long int initdram (int board_type)
 {
-    volatile immap_t *immap  = (immap_t *)CFG_IMMR;
-    volatile memctl8260_t *memctl = &immap->im_memctl;
-    volatile uchar c = 0, *ramaddr = (uchar *)(CFG_SDRAM_BASE + 0x8);
-    ulong psdmr = CFG_PSDMR;
-    int i;
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8260_t *memctl = &immap->im_memctl;
+	volatile uchar c = 0, *ramaddr = (uchar *) (CFG_SDRAM_BASE + 0x8);
+	ulong psdmr = CFG_PSDMR;
+	int i;

-    /*
-     * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
-     *
-     * "At system reset, initialization software must set up the
-     *	programmable parameters in the memory controller banks registers
-     *	(ORx, BRx, P/LSDMR). After all memory parameters are configured,
-     *	system software should execute the following initialization sequence
-     *	for each SDRAM device.
-     *
-     *	1. Issue a PRECHARGE-ALL-BANKS command
-     *	2. Issue eight CBR REFRESH commands
-     *	3. Issue a MODE-SET command to initialize the mode register
-     *
-     *	The initial commands are executed by setting P/LSDMR[OP] and
-     *	accessing the SDRAM with a single-byte transaction."
-     *
-     * The appropriate BRx/ORx registers have already been set when we
-     * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
-     */
+	/*
+	 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
+	 *
+	 * "At system reset, initialization software must set up the
+	 *  programmable parameters in the memory controller banks registers
+	 *  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
+	 *  system software should execute the following initialization sequence
+	 *  for each SDRAM device.
+	 *
+	 *  1. Issue a PRECHARGE-ALL-BANKS command
+	 *  2. Issue eight CBR REFRESH commands
+	 *  3. Issue a MODE-SET command to initialize the mode register
+	 *
+	 *  The initial commands are executed by setting P/LSDMR[OP] and
+	 *  accessing the SDRAM with a single-byte transaction."
+	 *
+	 * The appropriate BRx/ORx registers have already been set when we
+	 * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
+	 */

-    memctl->memc_psrt = CFG_PSRT;
-    memctl->memc_mptpr = CFG_MPTPR;
+	memctl->memc_psrt = CFG_PSRT;
+	memctl->memc_mptpr = CFG_MPTPR;

-    memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
-    *ramaddr = c;
-
-    memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
-    for (i = 0; i < 8; i++){
+	memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
 	*ramaddr = c;
-    }
-    memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
-    *ramaddr = c;

-    memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
-    *ramaddr = c;
+	memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
+	for (i = 0; i < 8; i++) {
+		*ramaddr = c;
+	}
+	memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
+	*ramaddr = c;

-    /* return total ram size */
-    return (CFG_SDRAM0_SIZE * 1024 * 1024);
+	memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
+	*ramaddr = c;
+
+	/* return total ram size */
+	return (CFG_SDRAM0_SIZE * 1024 * 1024);
 }

 /*********************************************************************/
--- a/board/impa7/u-boot.lds
+++ b/board/impa7/u-boot.lds
@@ -44,15 +44,12 @@ SECTIONS
 	. = ALIGN(4);
 	.got : { *(.got) }

-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
-
-	armboot_end_data = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;

 	. = ALIGN(4);
+	__bss_start = .;
 	.bss : { *(.bss) }
-
-	armboot_end = .;
-
+	_end = .;
 }
--- a/board/incaip/memsetup.S
+++ b/board/incaip/memsetup.S
@@ -185,8 +185,10 @@ sdram_init:

 	li	t1, MC_MODUL_BASE

+#if 0
 	/* Disable memory controller before changing any of its registers */
 	sw	zero, MC_CTRLENA(t1)
+#endif

 	li	t2, 100000000
 	beq	a0, t2, 1f
--- a/board/innokom/u-boot.lds
+++ b/board/innokom/u-boot.lds
@@ -44,16 +44,12 @@ SECTIONS
 	. = ALIGN(4);
 	.got : { *(.got) }

-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
-
-	armboot_end_data = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;

 	. = ALIGN(4);
-	bss_start = .;
+	__bss_start = .;
 	.bss : { *(.bss) }
-	bss_end = .;
-
-	armboot_end = .;
+	_end = .;
 }
--- a/board/ixdp425/config.mk
+++ b/board/ixdp425/config.mk
@@ -1,2 +1,2 @@
 #TEXT_BASE = 0x00100000
-TEXT_BASE = 0x00f00000
+TEXT_BASE = 0x00f80000
--- a/board/ixdp425/flash.c
+++ b/board/ixdp425/flash.c
@@ -72,7 +72,7 @@ unsigned long flash_init (void)
 			flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
 			break;
 		default:
-			panic ("configured to many flash banks!\n");
+			panic ("configured too many flash banks!\n");
 			break;
 		}
 		size += flash_info[i].size;
@@ -82,7 +82,7 @@ unsigned long flash_init (void)
 	 */
 	flash_protect (FLAG_PROTECT_SET,
 		       CFG_FLASH_BASE,
-		       CFG_FLASH_BASE + _armboot_end_data - _armboot_start,
+		       CFG_FLASH_BASE + _bss_start - _armboot_start,
 		       &flash_info[0]);

 	flash_protect (FLAG_PROTECT_SET,
--- a/board/ixdp425/u-boot.lds
+++ b/board/ixdp425/u-boot.lds
@@ -48,12 +48,8 @@ SECTIONS
 	.u_boot_cmd : { *(.u_boot_cmd) }
 	__u_boot_cmd_end = .;

-	armboot_end_data = .;
-
 	. = ALIGN(4);
-	bss_start = .;
+	__bss_start = .;
 	.bss : { *(.bss) }
-	bss_end = .;
-
-	armboot_end = .;
+	_end = .;
 }
--- a/board/lart/u-boot.lds
+++ b/board/lart/u-boot.lds
@@ -44,14 +44,12 @@ SECTIONS
 	. = ALIGN(4);
 	.got : { *(.got) }

-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
-
-	armboot_end_data = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;

 	. = ALIGN(4);
+	__bss_start = .;
 	.bss : { *(.bss) }
-
-	armboot_end = .;
+	_end = .;
 }
--- a/board/logodl/flash.c
+++ b/board/logodl/flash.c
@@ -105,7 +105,7 @@ ulong flash_init(void)
     */
    flash_protect(FLAG_PROTECT_SET,
 		  CFG_FLASH_BASE,
-		  CFG_FLASH_BASE + _armboot_end_data - _armboot_start,
+		  CFG_FLASH_BASE + _bss_start - _armboot_start,
 		  &flash_info[0]);

    flash_protect(FLAG_PROTECT_SET,
--- a/board/logodl/u-boot.lds
+++ b/board/logodl/u-boot.lds
@@ -44,12 +44,12 @@ SECTIONS
 	. = ALIGN(4);
 	.got : { *(.got) }

-	armboot_end_data = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;

 	. = ALIGN(4);
-	bss_start = .;
+	__bss_start = .;
 	.bss : { *(.bss) }
-	bss_end = .;
-
-	armboot_end = .;
+	_end = .;
 }
--- a/board/lubbock/config.mk
+++ b/board/lubbock/config.mk
@@ -1,3 +1,3 @@
 #TEXT_BASE = 0xa1700000
-TEXT_BASE = 0xa3000000
+TEXT_BASE = 0xa3080000
 #TEXT_BASE = 0
--- a/board/lubbock/u-boot.lds
+++ b/board/lubbock/u-boot.lds
@@ -44,16 +44,12 @@ SECTIONS
 	. = ALIGN(4);
 	.got : { *(.got) }

-   __u_boot_cmd_start = .;
-   .u_boot_cmd : { *(.u_boot_cmd) }
-   __u_boot_cmd_end = .;
-
-	armboot_end_data = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;

 	. = ALIGN(4);
-	bss_start = .;
+	__bss_start = .;
 	.bss : { *(.bss) }
-	bss_end = .;
-
-	armboot_end = .;
+	_end = .;
 }
--- a/board/m5272c3/Makefile
+++ b/board/m5272c3/Makefile
@@ -28,7 +28,7 @@ LIB	= lib$(BOARD).a
 OBJS	= $(BOARD).o flash.o

 $(LIB):	.depend $(OBJS)
-	$(AR) crv $@ $^
+	$(AR) crv $@ $(OBJS)

 #########################################################################

--- a/board/m5272c3/config.mk
+++ b/board/m5272c3/config.mk
@@ -22,4 +22,4 @@
 # MA 02111-1307 USA
 #

-TEXT_BASE = 0x3e0000
+TEXT_BASE = 0xffe00000
--- a/board/m5272c3/m5272c3.c
+++ b/board/m5272c3/m5272c3.c
@@ -22,14 +22,31 @@
 */

 #include <common.h>
+#include <asm/m5272.h>
+#include <asm/immap_5272.h>

-int checkboard (void)
-{
-	puts ("MOTOROLA MCF5272C3 Evaluation Board\n");
+
+int checkboard (void) {
+	puts ("Board: ");
+	puts("MOTOROLA MCF5272C3 EVB\n");
 	return 0;
-}
+	};

-long int initdram (int board_type)
-{
-	return 0x400000;
+long int initdram (int board_type) {
+	volatile sdramctrl_t * sdp = (sdramctrl_t *)(CFG_MBAR + MCFSIM_SDCR);
+
+	sdp->sdram_sdtr = 0xf539;
+	sdp->sdram_sdcr = 0x4211;
+
+	/* Dummy write to start SDRAM */
+	*((volatile unsigned long *)0) = 0;
+
+	return CFG_SDRAM_SIZE * 1024 * 1024;
+	};
+
+int testdram (void) {
+	/* TODO: XXX XXX XXX */
+	printf ("DRAM test not implemented!\n");
+
+	return (0);
 }
--- a/board/m5272c3/u-boot.lds
+++ b/board/m5272c3/u-boot.lds
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000-2003
+ * (C) Copyright 2000
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
@@ -22,7 +22,7 @@
 */

 OUTPUT_ARCH(m68k)
-SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
 /* Do we need any of these for elf?
   __DYNAMIC = 0;    */
 SECTIONS
@@ -56,15 +56,14 @@ SECTIONS
    /* WARNING - the following is hand-optimized to fit within	*/
    /* the sector layout of our flash chips!	XXX FIXME XXX	*/

-    cpu/coldfire/start.o	(.text)
-    common/dlmalloc.o	(.text)
-    lib_generic/string.o	(.text)
-    lib_generic/vsprintf.o	(.text)
-    lib_generic/crc32.o	(.text)
-    lib_generic/zlib.o	(.text)
+    cpu/mcf52x2/start.o		(.text)
+    lib_m68k/traps.o		(.text)
+    cpu/mcf52x2/interrupts.o	(.text)
+    common/dlmalloc.o		(.text)
+    lib_generic/zlib.o		(.text)

-/*    . = env_offset; */
-    common/environment.o(.text)
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/environment.o	(.text)

    *(.text)
    *(.fixup)
@@ -85,9 +84,12 @@ SECTIONS
  . = (. + 0x00FF) & 0xFFFFFF00;
  _erotext = .;
  PROVIDE (erotext = .);
+
  .reloc   :
  {
+    __got_start = .;
    *(.got)
+    __got_end = .;
    _GOT2_TABLE_ = .;
    *(.got2)
    _FIXUP_TABLE_ = .;
@@ -108,6 +110,11 @@ SECTIONS
  _edata  =  .;
  PROVIDE (edata = .);

+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
  __start___ex_table = .;
  __ex_table : { *(__ex_table) }
  __stop___ex_table = .;
--- a/board/m5282evb/Makefile
+++ b/board/m5282evb/Makefile
@@ -28,7 +28,7 @@ LIB	= lib$(BOARD).a
 OBJS	= $(BOARD).o flash.o

 $(LIB):	.depend $(OBJS)
-	$(AR) crv $@ $^
+	$(AR) crv $@ $(OBJS)

 #########################################################################

--- a/board/m5282evb/config.mk
+++ b/board/m5282evb/config.mk
@@ -22,4 +22,4 @@
 # MA 02111-1307 USA
 #

-TEXT_BASE = 0x3e0000
+TEXT_BASE = 0x20000
--- a/board/m5282evb/u-boot.lds
+++ b/board/m5282evb/u-boot.lds
@@ -22,7 +22,7 @@
 */

 OUTPUT_ARCH(m68k)
-SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
 /* Do we need any of these for elf?
   __DYNAMIC = 0;    */
 SECTIONS
@@ -56,7 +56,7 @@ SECTIONS
    /* WARNING - the following is hand-optimized to fit within	*/
    /* the sector layout of our flash chips!	XXX FIXME XXX	*/

-    cpu/coldfire/start.o	(.text)
+    cpu/mcf52x2/start.o	(.text)
    common/dlmalloc.o	(.text)
    lib_generic/string.o	(.text)
    lib_generic/vsprintf.o	(.text)
@@ -85,9 +85,11 @@ SECTIONS
  . = (. + 0x00FF) & 0xFFFFFF00;
  _erotext = .;
  PROVIDE (erotext = .);
-  .reloc   :
+    .reloc   :
  {
+    __got_start = .;
    *(.got)
+    __got_end = .;
    _GOT2_TABLE_ = .;
    *(.got2)
    _FIXUP_TABLE_ = .;
@@ -108,6 +110,10 @@ SECTIONS
  _edata  =  .;
  PROVIDE (edata = .);

+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
  __start___ex_table = .;
  __ex_table : { *(__ex_table) }
  __stop___ex_table = .;
--- a/board/mpl/vcma9/config.mk
+++ b/board/mpl/vcma9/config.mk
@@ -14,11 +14,11 @@
 # Linux-Kernel is expected to be at 3000'8000, entry 3000'8000
 # optionally with a ramdisk at 3040'0000
 #
-# we load ourself to 30F8'0000
+# we load ourself to 33F8'0000
 #
 # download area is 3080'0000
 #


 #TEXT_BASE = 0x30F80000
-TEXT_BASE = 0x33F00000
+TEXT_BASE = 0x33F80000
--- a/board/mpl/vcma9/u-boot.lds
+++ b/board/mpl/vcma9/u-boot.lds
@@ -45,14 +45,12 @@ SECTIONS
 	. = ALIGN(4);
 	.got : { *(.got) }

-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
-
-	armboot_end_data = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;

 	. = ALIGN(4);
+	__bss_start = .;
 	.bss : { *(.bss) }
-
-	armboot_end = .;
+	_end = .;
 }
--- a/board/omap1510inn/config.mk
+++ b/board/omap1510inn/config.mk
@@ -17,9 +17,9 @@
 #
 # Linux-Kernel is expected to be at 1000'8000, entry 1000'8000  (mem base + reserved)
 #
-# we load ourself to 1100'0000
+# we load ourself to 1108'0000
 #
 #


-TEXT_BASE = 0x11000000
+TEXT_BASE = 0x11080000
--- a/board/omap1510inn/u-boot.lds
+++ b/board/omap1510inn/u-boot.lds
@@ -45,14 +45,12 @@ SECTIONS
 	. = ALIGN(4);
 	.got : { *(.got) }

-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
-
-	armboot_end_data = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;

 	. = ALIGN(4);
+	__bss_start = .;
 	.bss : { *(.bss) }
-
-	armboot_end = .;
+	_end = .;
 }
--- a/board/omap1610inn/config.mk
+++ b/board/omap1610inn/config.mk
@@ -18,9 +18,9 @@
 # Linux-Kernel is expected to be at 1000'8000, entry 1000'8000
 # (mem base + reserved)
 #
-# we load ourself to 1100'0000
+# we load ourself to 1108'0000
 #
 #


-TEXT_BASE = 0x11000000
+TEXT_BASE = 0x11080000
--- a/board/omap1610inn/flash.c
+++ b/board/omap1610inn/flash.c
@@ -2,7 +2,7 @@
 * (C) Copyright 2001
 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
 *
- * (C) Copyright 2001
+ * (C) Copyright 2001-2004
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * (C) Copyright 2003
@@ -19,7 +19,7 @@
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
@@ -32,7 +32,7 @@
 #include <linux/byteorder/swab.h>

 #define PHYS_FLASH_SECT_SIZE	0x00020000	/* 256 KB sectors (x2) */
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips	   */

 /* Board support for 1 or 2 flash devices */
 #undef FLASH_PORT_WIDTH32
@@ -80,6 +80,7 @@ void flash_print_info (flash_info_t * info);
 void flash_unprotect_sectors (FPWV * addr);
 int flash_erase (flash_info_t * info, int s_first, int s_last);
 int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt);
+void flash_unlock(flash_info_t * info);

 /*-----------------------------------------------------------------------
 */
@@ -93,6 +94,8 @@ unsigned long flash_init (void)
 		case 0:
 			flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
 			flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
+			/* to reset the lock bit */
+			flash_unlock(&flash_info[i]);
 			break;
 		default:
 			panic ("configured too many flash banks!\n");
@@ -114,6 +117,19 @@ unsigned long flash_init (void)
 	return size;
 }

+/*-----------------------------------------------------------------------
+ */
+void flash_unlock(flash_info_t * info)
+{
+	int j;
+	for (j=2;j<CFG_MAX_FLASH_SECT;j++){
+	FPWV *addr = (FPWV *) (info->start[j]);
+	flash_unprotect_sectors (addr);
+	*addr = (FPW) 0x00500050;/* clear status register */
+	*addr = (FPW) 0x00FF00FF;/* resest to read mode */
+	}
+}
+
 /*-----------------------------------------------------------------------
 */
 static void flash_get_offsets (ulong base, flash_info_t * info)
@@ -177,7 +193,7 @@ void flash_print_info (flash_info_t * info)
 		if ((i % 5) == 0)
 			printf ("\n   ");
 		printf (" %08lX%s",
-			info->start[i], info->protect[i] ? " (RO)" : "     ");
+			info->start[i], info->protect[i] ? " (RO)" : "	   ");
 	}
 	printf ("\n");
 	return;
@@ -209,18 +225,18 @@ static ulong flash_get_size (FPW * addr, flash_info_t * info)
 		info->sector_count = 0;
 		info->size = 0;
 		addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
-		return (0);		/* no or unknown flash  */
+		return (0);		/* no or unknown flash	*/
 	}

 	mb ();
-	value = addr[1];	/* device ID        */
+	value = addr[1];	/* device ID	    */
 	switch (value) {

 	case (FPW) (INTEL_ID_28F256L18T):
 		info->flash_id += FLASH_28F256L18T;
 		info->sector_count = 259;
 		info->size = 0x02000000;
-		break;			/* => 32 MB     */
+		break;			/* => 32 MB	*/

 	default:
 		info->flash_id = FLASH_UNKNOWN;
@@ -303,7 +319,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)

 	/* Start erase on unprotected sectors */
 	for (sect = s_first; sect <= s_last; sect++) {
-		if (info->protect[sect] == 0) {	/* not protected */
+		if (info->protect[sect] == 0) { /* not protected */
 			FPWV *addr = (FPWV *) (info->start[sect]);
 			FPW status;

@@ -333,7 +349,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
 				}
 			}

-			/* clear status register cmd.   */
+			/* clear status register cmd.	*/
 			*addr = (FPW) 0x00500050;
 			*addr = (FPW) 0x00FF00FF;/* resest to read mode */
 			printf (" done\n");
@@ -447,7 +463,6 @@ static int write_data (flash_info_t * info, ulong dest, FPW data)
 		printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr);
 		return (2);
 	}
-	flash_unprotect_sectors (addr);
 	/* Disable interrupts which might cause a timeout here */
 	flag = disable_interrupts ();
 	*addr = (FPW) 0x00400040;	/* write setup */
--- a/board/omap1610inn/u-boot.lds
+++ b/board/omap1610inn/u-boot.lds
@@ -44,8 +44,8 @@ SECTIONS
 	.u_boot_cmd : { *(.u_boot_cmd) }
 	__u_boot_cmd_end = .;

-	armboot_end_data = .;
 	. = ALIGN(4);
+	__bss_start = .;
 	.bss : { *(.bss) }
-	armboot_end = .;
+	_end = .;
 }
--- a/board/ppmc8260/Makefile
+++ b/board/ppmc8260/Makefile
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk

 LIB	= lib$(BOARD).a

-OBJS	:= ppmc8260.o strataflash.o
+OBJS	:= ppmc8260.o

 $(LIB):	$(OBJS) $(SOBJS)
 	$(AR) crv $@ $(OBJS)
--- a/board/shannon/u-boot.lds
+++ b/board/shannon/u-boot.lds
@@ -44,15 +44,12 @@ SECTIONS
 	. = ALIGN(4);
 	.got : { *(.got) }

-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
-
-	armboot_end_data = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;

 	. = ALIGN(4);
+	__bss_start = .;
 	.bss : { *(.bss) }
-
-	armboot_end = .;
-
+	_end = .;
 }
--- a/board/siemens/IAD210/atm.h
+++ b/board/siemens/IAD210/atm.h
@@ -1,9 +1,9 @@
-typedef unsigned char  uint8;
+typedef unsigned char uint8;
 typedef unsigned short uint16;
-typedef unsigned int   uint32;
-typedef volatile unsigned char  vuint8;
+typedef unsigned int uint32;
+typedef volatile unsigned char vuint8;
 typedef volatile unsigned short vuint16;
-typedef volatile unsigned int   vuint32;
+typedef volatile unsigned int vuint32;


 #define DPRAM_ATM CFG_IMMR + 0x3000
@@ -19,7 +19,7 @@ typedef volatile unsigned int   vuint32;
 #define NUM_AP_ENTRIES           (NUM_CONNECTIONS+1)
 #define NUM_MPHYPT_ENTRIES       1
 #define NUM_APCP_ENTRIES         1
-#define NUM_APCT_PRIO_1_ENTRIES  146 /* Determines minimum rate */
+#define NUM_APCT_PRIO_1_ENTRIES  146	/* Determines minimum rate */
 #define NUM_TQ_ENTRIES           12

 #define SIZE_OF_CT_ENTRY         64
@@ -31,16 +31,16 @@ typedef volatile unsigned int   vuint32;
 #define SIZE_OF_APCT_ENTRY       2
 #define SIZE_OF_TQ_ENTRY         2

-#define CT_BASE           ((ATM_DPRAM_BEGIN + 63) & 0xFFC0) /*64*/
-#define TCTE_BASE         (CT_BASE + NUM_CT_ENTRIES * SIZE_OF_CT_ENTRY) /*32*/
-#define APCP_BASE         (TCTE_BASE + NUM_TCTE_ENTRIES * SIZE_OF_TCTE_ENTRY)  /*32*/
-#define AM_BEGIN          (APCP_BASE + NUM_APCP_ENTRIES * SIZE_OF_APCP_ENTRY) /*4*/
+#define CT_BASE           ((ATM_DPRAM_BEGIN + 63) & 0xFFC0)	/*64 */
+#define TCTE_BASE         (CT_BASE + NUM_CT_ENTRIES * SIZE_OF_CT_ENTRY)	/*32 */
+#define APCP_BASE         (TCTE_BASE + NUM_TCTE_ENTRIES * SIZE_OF_TCTE_ENTRY)	/*32 */
+#define AM_BEGIN          (APCP_BASE + NUM_APCP_ENTRIES * SIZE_OF_APCP_ENTRY)	/*4 */
 #define AM_BASE           (AM_BEGIN + (NUM_AM_ENTRIES - 1) * SIZE_OF_AM_ENTRY)
-#define AP_BEGIN          (AM_BEGIN + NUM_AM_ENTRIES * SIZE_OF_AM_ENTRY) /*2*/
+#define AP_BEGIN          (AM_BEGIN + NUM_AM_ENTRIES * SIZE_OF_AM_ENTRY)	/*2 */
 #define AP_BASE           (AP_BEGIN + (NUM_AP_ENTRIES - 1) * SIZE_OF_AP_ENTRY)
-#define MPHYPT_BASE       (AP_BEGIN + NUM_AP_ENTRIES * SIZE_OF_AP_ENTRY) /*2*/
-#define APCT_PRIO_1_BASE  (MPHYPT_BASE + NUM_MPHYPT_ENTRIES * SIZE_OF_MPHYPT_ENTRY) /*2*/
-#define TQ_BASE           (APCT_PRIO_1_BASE + NUM_APCT_PRIO_1_ENTRIES * SIZE_OF_APCT_ENTRY) /*2*/
+#define MPHYPT_BASE       (AP_BEGIN + NUM_AP_ENTRIES * SIZE_OF_AP_ENTRY)	/*2 */
+#define APCT_PRIO_1_BASE  (MPHYPT_BASE + NUM_MPHYPT_ENTRIES * SIZE_OF_MPHYPT_ENTRY)	/*2 */
+#define TQ_BASE           (APCT_PRIO_1_BASE + NUM_APCT_PRIO_1_ENTRIES * SIZE_OF_APCT_ENTRY)	/*2 */
 #define ATM_DPRAM_SIZE    ((TQ_BASE + NUM_TQ_ENTRIES * SIZE_OF_TQ_ENTRY) - ATM_DPRAM_BEGIN)

 #define CT_PTR(base)      ((struct ct_entry_t *)((char *)(base) + 0x2000 + CT_BASE))
@@ -55,62 +55,62 @@ typedef volatile unsigned int   vuint32;
 #define TQ_PTR(base)      ((uint16 *)((char *)(base) + 0x2000 + TQ_BASE))

 /* SAR registers */
-#define RBDBASE(base)	  ((vuint32 *)(base + 0x3F00)) /* Base address of RxBD-List */
-#define SRFCR(base)	  ((vuint8 *)(base + 0x3F04))  /* DMA Receive function code */
-#define SRSTATE(base)	  ((vuint8 *)(base + 0x3F05))  /* DMA Receive status */
-#define MRBLR(base)	  ((vuint16 *)(base + 0x3F06)) /* Init to 0 for ATM */
-#define RSTATE(base)	  ((vuint32 *)(base + 0x3F08)) /* Do not write to */
-#define R_CNT(base)	  ((vuint16 *)(base + 0x3F10)) /* Do not write to */
-#define STFCR(base)	  ((vuint8 *)(base + 0x3F12))  /* DMA Transmit function code */
-#define STSTATE(base)	  ((vuint8 *)(base + 0x3F13))  /* DMA Transmit status */
-#define TBDBASE(base)	  ((vuint32 *)(base + 0x3F14)) /* Base address of TxBD-List */
-#define TSTATE(base)	  ((vuint32 *)(base + 0x3F18)) /* Do not write to */
-#define COMM_CH(base)	  ((vuint16 *)(base + 0x3F1C)) /* Command channel */
-#define STCHNUM(base)	  ((vuint16 *)(base + 0x3F1E)) /* Do not write to */
-#define T_CNT(base)	  ((vuint16 *)(base + 0x3F20)) /* Do not write to */
-#define CTBASE(base)	  ((vuint16 *)(base + 0x3F22)) /* Base address of Connection-table */
-#define ECTBASE(base)	  ((vuint32 *)(base + 0x3F24)) /* Valid only for external Conn.-table */
-#define INTBASE(base)	  ((vuint32 *)(base + 0x3F28)) /* Base address of Interrupt-table */
-#define INTPTR(base)	  ((vuint32 *)(base + 0x3F2C)) /* Pointer to Interrupt-queue */
-#define C_MASK(base)	  ((vuint32 *)(base + 0x3F30)) /* CRC-mask */
-#define SRCHNUM(base)	  ((vuint16 *)(base + 0x3F34)) /* Do not write to */
-#define INT_CNT(base)	  ((vuint16 *)(base + 0x3F36)) /* Interrupt-Counter */
-#define INT_ICNT(base)	  ((vuint16 *)(base + 0x3F38)) /* Interrupt threshold */
-#define TSTA(base)	  ((vuint16 *)(base + 0x3F3A)) /* Time-stamp-address */
-#define OLDLEN(base)	  ((vuint16 *)(base + 0x3F3C)) /* Do not write to */
-#define SMRBLR(base)	  ((vuint16 *)(base + 0x3F3E)) /* SAR max RXBuffer length */
-#define EHEAD(base)	  ((vuint32 *)(base + 0x3F40)) /* Valid for serial mode */
-#define EPAYLOAD(base)	  ((vuint32 *)(base + 0x3F44)) /* Valid for serial mode */
-#define TQBASE(base)	  ((vuint16 *)(base + 0x3F48)) /* Base address of Tx queue */
-#define TQEND(base)	  ((vuint16 *)(base + 0x3F4A)) /* End address of Tx queue */
-#define TQAPTR(base)	  ((vuint16 *)(base + 0x3F4C)) /* TQ APC pointer */
-#define TQTPTR(base)	  ((vuint16 *)(base + 0x3F4E)) /* TQ Tx pointer */
-#define APCST(base)	  ((vuint16 *)(base + 0x3F50)) /* APC status */
-#define APCPTR(base)	  ((vuint16 *)(base + 0x3F52)) /* APC parameter pointer */
-#define HMASK(base)	  ((vuint32 *)(base + 0x3F54)) /* Header mask */
-#define AMBASE(base)	  ((vuint16 *)(base + 0x3F58)) /* Address match table base */
-#define AMEND(base)	  ((vuint16 *)(base + 0x3F5A)) /* Address match table end */
-#define APBASE(base)	  ((vuint16 *)(base + 0x3F5C)) /* Address match parameter */
-#define FLBASE(base)	  ((vuint32 *)(base + 0x3F54)) /* First-level table base */
-#define SLBASE(base)	  ((vuint32 *)(base + 0x3F58)) /* Second-level table base */
-#define FLMASK(base)	  ((vuint16 *)(base + 0x3F5C)) /* First-level mask */
-#define ECSIZE(base)	  ((vuint16 *)(base + 0x3F5E)) /* Valid for extended mode */
-#define APCT_REAL(base)	  ((vuint32 *)(base + 0x3F60)) /* APC 32 bit counter */
-#define R_PTR(base)	  ((vuint32 *)(base + 0x3F64)) /* Do not write to */
-#define RTEMP(base)	  ((vuint32 *)(base + 0x3F68)) /* Do not write to */
-#define T_PTR(base)	  ((vuint32 *)(base + 0x3F6C)) /* Do not write to */
-#define TTEMP(base)	  ((vuint32 *)(base + 0x3F70)) /* Do not write to */
+#define RBDBASE(base)	  ((vuint32 *)(base + 0x3F00))	/* Base address of RxBD-List */
+#define SRFCR(base)	  ((vuint8 *)(base + 0x3F04))	/* DMA Receive function code */
+#define SRSTATE(base)	  ((vuint8 *)(base + 0x3F05))	/* DMA Receive status */
+#define MRBLR(base)	  ((vuint16 *)(base + 0x3F06))	/* Init to 0 for ATM */
+#define RSTATE(base)	  ((vuint32 *)(base + 0x3F08))	/* Do not write to */
+#define R_CNT(base)	  ((vuint16 *)(base + 0x3F10))	/* Do not write to */
+#define STFCR(base)	  ((vuint8 *)(base + 0x3F12))	/* DMA Transmit function code */
+#define STSTATE(base)	  ((vuint8 *)(base + 0x3F13))	/* DMA Transmit status */
+#define TBDBASE(base)	  ((vuint32 *)(base + 0x3F14))	/* Base address of TxBD-List */
+#define TSTATE(base)	  ((vuint32 *)(base + 0x3F18))	/* Do not write to */
+#define COMM_CH(base)	  ((vuint16 *)(base + 0x3F1C))	/* Command channel */
+#define STCHNUM(base)	  ((vuint16 *)(base + 0x3F1E))	/* Do not write to */
+#define T_CNT(base)	  ((vuint16 *)(base + 0x3F20))	/* Do not write to */
+#define CTBASE(base)	  ((vuint16 *)(base + 0x3F22))	/* Base address of Connection-table */
+#define ECTBASE(base)	  ((vuint32 *)(base + 0x3F24))	/* Valid only for external Conn.-table */
+#define INTBASE(base)	  ((vuint32 *)(base + 0x3F28))	/* Base address of Interrupt-table */
+#define INTPTR(base)	  ((vuint32 *)(base + 0x3F2C))	/* Pointer to Interrupt-queue */
+#define C_MASK(base)	  ((vuint32 *)(base + 0x3F30))	/* CRC-mask */
+#define SRCHNUM(base)	  ((vuint16 *)(base + 0x3F34))	/* Do not write to */
+#define INT_CNT(base)	  ((vuint16 *)(base + 0x3F36))	/* Interrupt-Counter */
+#define INT_ICNT(base)	  ((vuint16 *)(base + 0x3F38))	/* Interrupt threshold */
+#define TSTA(base)	  ((vuint16 *)(base + 0x3F3A))	/* Time-stamp-address */
+#define OLDLEN(base)	  ((vuint16 *)(base + 0x3F3C))	/* Do not write to */
+#define SMRBLR(base)	  ((vuint16 *)(base + 0x3F3E))	/* SAR max RXBuffer length */
+#define EHEAD(base)	  ((vuint32 *)(base + 0x3F40))	/* Valid for serial mode */
+#define EPAYLOAD(base)	  ((vuint32 *)(base + 0x3F44))	/* Valid for serial mode */
+#define TQBASE(base)	  ((vuint16 *)(base + 0x3F48))	/* Base address of Tx queue */
+#define TQEND(base)	  ((vuint16 *)(base + 0x3F4A))	/* End address of Tx queue */
+#define TQAPTR(base)	  ((vuint16 *)(base + 0x3F4C))	/* TQ APC pointer */
+#define TQTPTR(base)	  ((vuint16 *)(base + 0x3F4E))	/* TQ Tx pointer */
+#define APCST(base)	  ((vuint16 *)(base + 0x3F50))	/* APC status */
+#define APCPTR(base)	  ((vuint16 *)(base + 0x3F52))	/* APC parameter pointer */
+#define HMASK(base)	  ((vuint32 *)(base + 0x3F54))	/* Header mask */
+#define AMBASE(base)	  ((vuint16 *)(base + 0x3F58))	/* Address match table base */
+#define AMEND(base)	  ((vuint16 *)(base + 0x3F5A))	/* Address match table end */
+#define APBASE(base)	  ((vuint16 *)(base + 0x3F5C))	/* Address match parameter */
+#define FLBASE(base)	  ((vuint32 *)(base + 0x3F54))	/* First-level table base */
+#define SLBASE(base)	  ((vuint32 *)(base + 0x3F58))	/* Second-level table base */
+#define FLMASK(base)	  ((vuint16 *)(base + 0x3F5C))	/* First-level mask */
+#define ECSIZE(base)	  ((vuint16 *)(base + 0x3F5E))	/* Valid for extended mode */
+#define APCT_REAL(base)	  ((vuint32 *)(base + 0x3F60))	/* APC 32 bit counter */
+#define R_PTR(base)	  ((vuint32 *)(base + 0x3F64))	/* Do not write to */
+#define RTEMP(base)	  ((vuint32 *)(base + 0x3F68))	/* Do not write to */
+#define T_PTR(base)	  ((vuint32 *)(base + 0x3F6C))	/* Do not write to */
+#define TTEMP(base)	  ((vuint32 *)(base + 0x3F70))	/* Do not write to */

 /* ESAR registers */
-#define FMCTIMESTMP(base) ((vuint32 *)(base + 0x3F80)) /* Perf.Mon.Timestamp */
-#define FMCTEMPLATE(base) ((vuint32 *)(base + 0x3F84)) /* Perf.Mon.Template */
-#define PMPTR(base)       ((vuint16 *)(base + 0x3F88)) /* Perf.Mon.Table */
-#define PMCHANNEL(base)	  ((vuint16 *)(base + 0x3F8A)) /* Perf.Mon.Channel */
-#define MPHYST(base)	  ((vuint16 *)(base + 0x3F90)) /* Multi-PHY Status */
-#define TCTEBASE(base)	  ((vuint16 *)(base + 0x3F92)) /* Internal TCT Extension Base */
-#define ETCTEBASE(base)	  ((vuint32 *)(base + 0x3F94)) /* External TCT Extension Base */
-#define COMM_CH2(base)	  ((vuint32 *)(base + 0x3F98)) /* 2nd command channel word */
-#define STATBASE(base)	  ((vuint16 *)(base + 0x3F9C)) /* Statistics table pointer */
+#define FMCTIMESTMP(base) ((vuint32 *)(base + 0x3F80))	/* Perf.Mon.Timestamp */
+#define FMCTEMPLATE(base) ((vuint32 *)(base + 0x3F84))	/* Perf.Mon.Template */
+#define PMPTR(base)       ((vuint16 *)(base + 0x3F88))	/* Perf.Mon.Table */
+#define PMCHANNEL(base)	  ((vuint16 *)(base + 0x3F8A))	/* Perf.Mon.Channel */
+#define MPHYST(base)	  ((vuint16 *)(base + 0x3F90))	/* Multi-PHY Status */
+#define TCTEBASE(base)	  ((vuint16 *)(base + 0x3F92))	/* Internal TCT Extension Base */
+#define ETCTEBASE(base)	  ((vuint32 *)(base + 0x3F94))	/* External TCT Extension Base */
+#define COMM_CH2(base)	  ((vuint32 *)(base + 0x3F98))	/* 2nd command channel word */
+#define STATBASE(base)	  ((vuint16 *)(base + 0x3F9C))	/* Statistics table pointer */

 /* UTOPIA Mode Register */
 #define UTMODE(base)      (CAST(vuint32 *)(base + 0x0978))
@@ -139,108 +139,104 @@ typedef volatile unsigned int   vuint32;
 #define NUM_INT_ENTRIES   80
 #define SIZE_OF_INT_ENTRY 4

-struct apc_params_t
-{
-  vuint16 apct_base1;	/* APC Table - First Priority Base pointer */
-  vuint16 apct_end1;	/* First APC Table - Length */
-  vuint16 apct_ptr1;	/* First APC Table Pointer */
-  vuint16 apct_sptr1;	/* APC Table First Priority Service pointer */
-  vuint16 etqbase;	/* Enhanced Transmit Queue Base pointer */
-  vuint16 etqend;	/* Enhanced Transmit Queue End pointer */
-  vuint16 etqaptr;	/* Enhanced Transmit Queue APC pointer */
-  vuint16 etqtptr;	/* Enhanced Transmit Queue Transmitter pointer */
-  vuint16 apc_mi;	/* APC - Max Iteration */
-  vuint16 ncits;	/* Number of Cells In TimeSlot  */
-  vuint16 apcnt;	/* APC - N Timer */
-  vuint16 reserved1;	/* reserved */
-  vuint16 eapcst;	/* APC status */
-  vuint16 ptp_counter;	/* PTP queue length */
-  vuint16 ptp_txch;	/* PTP channel */
-  vuint16 reserved2;	/* reserved */
+struct apc_params_t {
+	vuint16 apct_base1;	/* APC Table - First Priority Base pointer */
+	vuint16 apct_end1;	/* First APC Table - Length */
+	vuint16 apct_ptr1;	/* First APC Table Pointer */
+	vuint16 apct_sptr1;	/* APC Table First Priority Service pointer */
+	vuint16 etqbase;	/* Enhanced Transmit Queue Base pointer */
+	vuint16 etqend;		/* Enhanced Transmit Queue End pointer */
+	vuint16 etqaptr;	/* Enhanced Transmit Queue APC pointer */
+	vuint16 etqtptr;	/* Enhanced Transmit Queue Transmitter pointer */
+	vuint16 apc_mi;		/* APC - Max Iteration */
+	vuint16 ncits;		/* Number of Cells In TimeSlot  */
+	vuint16 apcnt;		/* APC - N Timer */
+	vuint16 reserved1;	/* reserved */
+	vuint16 eapcst;		/* APC status */
+	vuint16 ptp_counter;	/* PTP queue length */
+	vuint16 ptp_txch;	/* PTP channel */
+	vuint16 reserved2;	/* reserved */
 };

-struct ct_entry_t
-{
-  /* RCT */
-  unsigned fhnt	      : 1;
-  unsigned pm_rct     : 1;
-  unsigned reserved0  : 6;
-  unsigned hec        : 1;
-  unsigned clp	      : 1;
-  unsigned cng_ncrc   : 1;
-  unsigned inf_rct    : 1;
-  unsigned cngi_ptp   : 1;
-  unsigned cdis_rct   : 1;
-  unsigned aal_rct    : 2;
-  uint16 rbalen;
-  uint32 rcrc;
-  uint32 rb_ptr;
-  uint16 rtmlen;
-  uint16 rbd_ptr;
-  uint16 rbase;
-  uint16 tstamp;
-  uint16 imask;
-  unsigned ft	      : 2;
-  unsigned nim	      : 1;
-  unsigned reserved1  : 2;
-  unsigned rpmt	      : 6;
-  unsigned reserved2  : 5;
-  uint8 reserved3[8];
-  /* TCT */
-  unsigned reserved4  : 1;
-  unsigned pm_tct     : 1;
-  unsigned reserved5  : 6;
-  unsigned pc	      : 1;
-  unsigned reserved6  : 2;
-  unsigned inf_tct    : 1;
-  unsigned cr10       : 1;
-  unsigned cdis_tct   : 1;
-  unsigned aal_tct    : 2;
-  uint16 tbalen;
-  uint32 tcrc;
-  uint32 tb_ptr;
-  uint16 ttmlen;
-  uint16 tbd_ptr;
-  uint16 tbase;
-  unsigned reserved7  : 5;
-  unsigned tpmt	      : 6;
-  unsigned reserved8  : 3;
-  unsigned avcf	      : 1;
-  unsigned act	      : 1;
-  uint32 chead;
-  uint16 apcl;
-  uint16 apcpr;
-  unsigned out	      : 1;
-  unsigned bnr        : 1;
-  unsigned tservice   : 2;
-  unsigned apcp	      : 12;
-  uint16 apcpf;
+struct ct_entry_t {
+	/* RCT */
+	unsigned fhnt:1;
+	unsigned pm_rct:1;
+	unsigned reserved0:6;
+	unsigned hec:1;
+	unsigned clp:1;
+	unsigned cng_ncrc:1;
+	unsigned inf_rct:1;
+	unsigned cngi_ptp:1;
+	unsigned cdis_rct:1;
+	unsigned aal_rct:2;
+	uint16 rbalen;
+	uint32 rcrc;
+	uint32 rb_ptr;
+	uint16 rtmlen;
+	uint16 rbd_ptr;
+	uint16 rbase;
+	uint16 tstamp;
+	uint16 imask;
+	unsigned ft:2;
+	unsigned nim:1;
+	unsigned reserved1:2;
+	unsigned rpmt:6;
+	unsigned reserved2:5;
+	uint8 reserved3[8];
+	/* TCT */
+	unsigned reserved4:1;
+	unsigned pm_tct:1;
+	unsigned reserved5:6;
+	unsigned pc:1;
+	unsigned reserved6:2;
+	unsigned inf_tct:1;
+	unsigned cr10:1;
+	unsigned cdis_tct:1;
+	unsigned aal_tct:2;
+	uint16 tbalen;
+	uint32 tcrc;
+	uint32 tb_ptr;
+	uint16 ttmlen;
+	uint16 tbd_ptr;
+	uint16 tbase;
+	unsigned reserved7:5;
+	unsigned tpmt:6;
+	unsigned reserved8:3;
+	unsigned avcf:1;
+	unsigned act:1;
+	uint32 chead;
+	uint16 apcl;
+	uint16 apcpr;
+	unsigned out:1;
+	unsigned bnr:1;
+	unsigned tservice:2;
+	unsigned apcp:12;
+	uint16 apcpf;
 };

-struct tcte_entry_t
-{
-  unsigned res1       : 4;
-  unsigned scr        : 12;
-  uint16 scrf;
-  uint16 bt;
-  uint16 buptrh;
-  uint32 buptrl;
-  unsigned vbr2       : 1;
-  unsigned res2       : 15;
-  uint16 oobr;
-  uint16 res3[8];
+struct tcte_entry_t {
+	unsigned res1:4;
+	unsigned scr:12;
+	uint16 scrf;
+	uint16 bt;
+	uint16 buptrh;
+	uint32 buptrl;
+	unsigned vbr2:1;
+	unsigned res2:15;
+	uint16 oobr;
+	uint16 res3[8];
 };

 #define SIZE_OF_RBD  12
 #define SIZE_OF_TBD  12

-struct atm_bd_t
-{
-  vuint16 flags;
-  vuint16 length;
-  unsigned char * buffer_ptr;
-  vuint16 cpcs_uu_cpi;
-  vuint16 reserved;
+struct atm_bd_t {
+	vuint16 flags;
+	vuint16 length;
+	unsigned char *buffer_ptr;
+	vuint16 cpcs_uu_cpi;
+	vuint16 reserved;
 };

 /* BD flags */
@@ -259,35 +255,33 @@ struct atm_bd_t
 #define LEN_ERROR	0x0002
 #define CRC_ERROR	0x0001

-struct atm_connection_t
-{
-  struct atm_bd_t * rbd_ptr;
-  int num_rbd;
-  struct atm_bd_t * tbd_ptr;
-  int num_tbd;
-  struct ct_entry_t * ct_ptr;
-  struct tcte_entry_t * tcte_ptr;
-  void * drv;
-  void (* notify)(void * drv, int event);
+struct atm_connection_t {
+	struct atm_bd_t *rbd_ptr;
+	int num_rbd;
+	struct atm_bd_t *tbd_ptr;
+	int num_tbd;
+	struct ct_entry_t *ct_ptr;
+	struct tcte_entry_t *tcte_ptr;
+	void *drv;
+	void (*notify) (void *drv, int event);
 };

-struct atm_driver_t
-{
-  int loaded;
-  int started;
-  char * csram;
-  int csram_size;
-  uint32 * am_top;
-  uint16 * ap_top;
-  uint32 * int_reload_ptr;
-  uint32 * int_serv_ptr;
-  struct atm_bd_t * rbd_base_ptr;
-  struct atm_bd_t * tbd_base_ptr;
-  unsigned linerate_in_bps;
+struct atm_driver_t {
+	int loaded;
+	int started;
+	char *csram;
+	int csram_size;
+	uint32 *am_top;
+	uint16 *ap_top;
+	uint32 *int_reload_ptr;
+	uint32 *int_serv_ptr;
+	struct atm_bd_t *rbd_base_ptr;
+	struct atm_bd_t *tbd_base_ptr;
+	unsigned linerate_in_bps;
 };

 extern struct atm_connection_t g_conn[NUM_CONNECTIONS];
 extern struct atm_driver_t g_atm;

-extern int    atmLoad(void);
-extern void   atmUnload(void);
+extern int atmLoad (void);
+extern void atmUnload (void);
--- a/board/siemens/SCM/fpga_scm.c
+++ b/board/siemens/SCM/fpga_scm.c
@@ -28,77 +28,77 @@
 #include "../common/fpga.h"

 fpga_t fpga_list[] = {
-    { "FIOX" , CFG_FIOX_BASE ,
-      CFG_PD_FIOX_INIT , CFG_PD_FIOX_PROG , CFG_PD_FIOX_DONE  },
-    { "FDOHM", CFG_FDOHM_BASE,
-      CFG_PD_FDOHM_INIT, CFG_PD_FDOHM_PROG, CFG_PD_FDOHM_DONE }
+	{"FIOX", CFG_FIOX_BASE,
+	 CFG_PD_FIOX_INIT, CFG_PD_FIOX_PROG, CFG_PD_FIOX_DONE}
+	,
+	{"FDOHM", CFG_FDOHM_BASE,
+	 CFG_PD_FDOHM_INIT, CFG_PD_FDOHM_PROG, CFG_PD_FDOHM_DONE}
 };
-int fpga_count = sizeof(fpga_list) / sizeof(fpga_t);
+int fpga_count = sizeof (fpga_list) / sizeof (fpga_t);


-ulong fpga_control (fpga_t* fpga, int cmd)
+ulong fpga_control (fpga_t * fpga, int cmd)
 {
-    volatile immap_t *immr  = (immap_t *)CFG_IMMR;
+	volatile immap_t *immr = (immap_t *) CFG_IMMR;

-    switch (cmd) {
-    case FPGA_INIT_IS_HIGH:
-	immr->im_ioport.iop_pdird &= ~fpga->init_mask; /* input */
-	return (immr->im_ioport.iop_pdatd & fpga->init_mask) ? 1:0;
+	switch (cmd) {
+	case FPGA_INIT_IS_HIGH:
+		immr->im_ioport.iop_pdird &= ~fpga->init_mask;	/* input */
+		return (immr->im_ioport.iop_pdatd & fpga->init_mask) ? 1 : 0;

-    case FPGA_INIT_SET_LOW:
-	immr->im_ioport.iop_pdird |=  fpga->init_mask; /* output */
-	immr->im_ioport.iop_pdatd &= ~fpga->init_mask;
-	break;
+	case FPGA_INIT_SET_LOW:
+		immr->im_ioport.iop_pdird |= fpga->init_mask;	/* output */
+		immr->im_ioport.iop_pdatd &= ~fpga->init_mask;
+		break;

-    case FPGA_INIT_SET_HIGH:
-	immr->im_ioport.iop_pdird |= fpga->init_mask; /* output */
-	immr->im_ioport.iop_pdatd |= fpga->init_mask;
-	break;
+	case FPGA_INIT_SET_HIGH:
+		immr->im_ioport.iop_pdird |= fpga->init_mask;	/* output */
+		immr->im_ioport.iop_pdatd |= fpga->init_mask;
+		break;

-    case FPGA_PROG_SET_LOW:
-	immr->im_ioport.iop_pdatd &= ~fpga->prog_mask;
-	break;
+	case FPGA_PROG_SET_LOW:
+		immr->im_ioport.iop_pdatd &= ~fpga->prog_mask;
+		break;

-    case FPGA_PROG_SET_HIGH:
-	immr->im_ioport.iop_pdatd |= fpga->prog_mask;
-	break;
+	case FPGA_PROG_SET_HIGH:
+		immr->im_ioport.iop_pdatd |= fpga->prog_mask;
+		break;

-    case FPGA_DONE_IS_HIGH:
-	return (immr->im_ioport.iop_pdatd & fpga->done_mask) ? 1:0;
+	case FPGA_DONE_IS_HIGH:
+		return (immr->im_ioport.iop_pdatd & fpga->done_mask) ? 1 : 0;

-    case FPGA_READ_MODE:
-	break;
+	case FPGA_READ_MODE:
+		break;

-    case FPGA_LOAD_MODE:
-	break;
+	case FPGA_LOAD_MODE:
+		break;
+
+	case FPGA_GET_ID:
+		if (fpga->conf_base == CFG_FIOX_BASE) {
+			ulong ver =
+				*(volatile ulong *) (fpga->conf_base + 0x10);
+			return ((ver >> 10) & 0xf) + ((ver >> 2) & 0xf0);
+		} else if (fpga->conf_base == CFG_FDOHM_BASE) {
+			return (*(volatile ushort *) fpga->conf_base) & 0xff;
+		} else {
+			return *(volatile ulong *) fpga->conf_base;
+		}
+
+	case FPGA_INIT_PORTS:
+		immr->im_ioport.iop_ppard &= ~fpga->init_mask;	/* INIT I/O */
+		immr->im_ioport.iop_psord &= ~fpga->init_mask;
+		immr->im_ioport.iop_pdird &= ~fpga->init_mask;
+
+		immr->im_ioport.iop_ppard &= ~fpga->prog_mask;	/* PROG Output */
+		immr->im_ioport.iop_psord &= ~fpga->prog_mask;
+		immr->im_ioport.iop_pdird |= fpga->prog_mask;
+
+		immr->im_ioport.iop_ppard &= ~fpga->done_mask;	/* DONE Input */
+		immr->im_ioport.iop_psord &= ~fpga->done_mask;
+		immr->im_ioport.iop_pdird &= ~fpga->done_mask;
+
+		break;

-    case FPGA_GET_ID:
-	if (fpga->conf_base == CFG_FIOX_BASE) {
-	    ulong ver = *(volatile ulong *)(fpga->conf_base + 0x10);
-	    return ((ver >> 10) & 0xf) + ((ver >> 2) & 0xf0);
 	}
-	else if (fpga->conf_base == CFG_FDOHM_BASE) {
-	    return (*(volatile ushort *)fpga->conf_base) & 0xff;
-	}
-	else {
-	    return *(volatile ulong *)fpga->conf_base;
-	}
-
-    case FPGA_INIT_PORTS:
-	immr->im_ioport.iop_ppard &= ~fpga->init_mask; /* INIT I/O */
-	immr->im_ioport.iop_psord &= ~fpga->init_mask;
-	immr->im_ioport.iop_pdird &= ~fpga->init_mask;
-
-	immr->im_ioport.iop_ppard &= ~fpga->prog_mask; /* PROG Output */
-	immr->im_ioport.iop_psord &= ~fpga->prog_mask;
-	immr->im_ioport.iop_pdird |=  fpga->prog_mask;
-
-	immr->im_ioport.iop_ppard &= ~fpga->done_mask; /* DONE Input */
-	immr->im_ioport.iop_psord &= ~fpga->done_mask;
-	immr->im_ioport.iop_pdird &= ~fpga->done_mask;
-
-	break;
-
-    }
-    return 0;
+	return 0;
 }
--- a/board/smdk2400/config.mk
+++ b/board/smdk2400/config.mk
@@ -15,11 +15,11 @@
 # Linux-Kernel is expected to be at 0cf0'0000, entry 0cf0'0000
 # optionally with a ramdisk at 0c80'0000
 #
-# we load ourself to 0CF00000 (must be high enough not to be
+# we load ourself to 0CF80000 (must be high enough not to be
 # overwritten by the uncompessing Linux kernel)
 #
 # download area is 0C80'0000
 #


-TEXT_BASE = 0x0CF00000
+TEXT_BASE = 0x0CF80000
--- a/board/smdk2400/u-boot.lds
+++ b/board/smdk2400/u-boot.lds
@@ -45,15 +45,12 @@ SECTIONS
 	. = ALIGN(4);
 	.got : { *(.got) }

-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
-
-	armboot_end_data = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;

 	. = ALIGN(4);
+	__bss_start = .;
 	.bss : { *(.bss) }
-
-	armboot_end = .;
-
+	_end = .;
 }
--- a/board/smdk2410/u-boot.lds
+++ b/board/smdk2410/u-boot.lds
@@ -45,16 +45,12 @@ SECTIONS
 	. = ALIGN(4);
 	.got : { *(.got) }

-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
-
-
-	armboot_end_data = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;

 	. = ALIGN(4);
+	__bss_start = .;
 	.bss : { *(.bss) }
-
-	armboot_end = .;
-
+	_end = .;
 }
--- a/board/tb0229/Makefile
+++ b/board/tb0229/Makefile
@@ -0,0 +1,43 @@
+#
+# (C) Masami Komiya <mkomiya@sonare.it> 2004
+#
+# (C) Copyright 2003-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o vr4131-pci.o
+SOBJS	= memsetup.o
+
+$(LIB):	.depend $(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
--- a/board/tb0229/config.mk
+++ b/board/tb0229/config.mk
@@ -1,5 +1,7 @@
 #
-# (C) Copyright 2000-2003
+# (C) Masami Komiya <mkomiya@sonare.it> 2004
+#
+# (C) Copyright 2003
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # See file CREDITS for list of people who contributed to this
@@ -21,6 +23,8 @@
 # MA 02111-1307 USA
 #

-PLATFORM_RELFLAGS +=
+# ROM version
+TEXT_BASE = 0xBFC00000

-PLATFORM_CPPFLAGS += -m5200
+# RAM version
+#TEXT_BASE = 0x80400000
--- a/board/tb0229/flash.c
+++ b/board/tb0229/flash.c
--- a/board/tb0229/memsetup.S
+++ b/board/tb0229/memsetup.S
@@ -0,0 +1,71 @@
+/*
+ *  Memory sub-system initialization code for TANBAC Evaluation board TB0229.
+ *
+ *  Copyright (c) 2003  Masami Komiya <mkomiya@sonare.it>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2, or (at
+ * your option) any later version.
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/regdef.h>
+
+
+	.globl  memsetup
+memsetup:
+
+	/* BCUCNTREG1 = 0x0040 */
+	la	t0, 0xaf000000
+	li	t1, 0x0040
+	sh	t1, 0(t0)
+
+	/* ROMSIZEREG = 0x3333 */
+	la	t0, 0xaf000004
+	li	t1, 0x3333
+	sh	t1, 0(t0)
+
+	/* ROMSPEEDREG = 0x3003 */
+	la	t0, 0xaf000006
+	li	t1, 0x3003
+	sh	t1, 0(t0)
+
+	/* BCUCNTREG3 = 0 */
+	la	t0, 0xaf000016
+	li	t1, 0x0000
+	sh	t1, 0(t0)
+
+	/* CMUCLKMSK */
+	la	t0, 0xaf000060
+	li	t1, 0x39a2
+	sh	t1, 0(t0)
+
+	/* PMUCNTREG */
+	la	t0, 0xaf0000c2
+	li	t1, 0x0006
+	sh	t1, 0(t0)
+
+	/* SDRAMMODEREG = 0x8029 */
+	la	t0, 0xaf000400
+	li	t1, 0x8029
+	sh	t1, 0(t0)
+
+	/* SDRAMCNTREG = 0x2322 */
+	la	t0, 0xaf000402
+	li	t1, 0x2322
+	sh	t1, 0(t0)
+
+	/* BCURFCNTREG = 0x0106 */
+	la	t0, 0xaf000404
+	li	t1, 0x0106
+	sh	t1, 0(t0)
+
+	/* RAMSZEREG = 0x5555 (64MB Bank) */
+	la	t0, 0xaf000408
+	li	t1, 0x5555
+	sh	t1, 0(t0)
+
+	j       ra
+	nop
--- a/board/tb0229/tb0229.c
+++ b/board/tb0229/tb0229.c
@@ -0,0 +1,42 @@
+/*
+ * Board initialize code for TANBAC Evaluation board TB0229.
+ *
+ * (C) Masami Komiya <mkomiya@sonare.it> 2004
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2, or (at
+ * your option) any later version.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/addrspace.h>
+#include <asm/inca-ip.h>
+#include <pci.h>
+
+unsigned long mips_io_port_base = 0;
+
+#if defined(CONFIG_PCI)
+static struct pci_controller hose;
+
+void pci_init_board (void)
+{
+	init_vr4131_pci(&hose);
+}
+#endif
+
+
+long int initdram(int board_type)
+{
+	return get_ram_size (CFG_SDRAM_BASE, 0x8000000);
+}
+
+
+int checkboard (void)
+{
+	printf("Board: TANBAC TB0229 ");
+	printf("(CPU Speed %d MHz)\n", (int)CPU_CLOCK_RATE/1000000);
+
+	return 0;
+}
--- a/board/tb0229/u-boot.lds
+++ b/board/tb0229/u-boot.lds
@@ -0,0 +1,68 @@
+/*
+ * (C) Masami Komiya <mkomiya@sonare.it> 2004
+ *
+ * (C) Copyright 2003
+ * Wolfgang Denk Engineering, <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips")
+
+OUTPUT_ARCH(mips)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text       :
+	{
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata  : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data  : { *(.data) }
+
+	. = ALIGN(4);
+	.sdata  : { *(.sdata) }
+
+	_gp = ALIGN(16);
+
+	__got_start = .;
+	.got  : { *(.got) }
+	__got_end = .;
+
+	.sdata  : { *(.sdata) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	uboot_end_data = .;
+	num_got_entries = (__got_end - __got_start) >> 2;
+
+	. = ALIGN(4);
+	.sbss  : { *(.sbss) }
+	.bss  : { *(.bss) }
+	uboot_end = .;
+}
--- a/board/tb0229/vr4131-pci.c
+++ b/board/tb0229/vr4131-pci.c
@@ -0,0 +1,254 @@
+/*
+ * VR4131 PCIU support code for TANBAC Evaluation board TB0229.
+ *
+ * (C) Masami Komiya <mkomiya@sonare.it> 2004
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2, or (at
+ * your option) any later version.
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/addrspace.h>
+
+#define VR4131_PCIMMAW1REG	(volatile unsigned int*)(KSEG1 + 0x0f000c00)
+#define VR4131_PCIMMAW2REG	(volatile unsigned int*)(KSEG1 + 0x0f000c04)
+#define VR4131_PCITAW1REG	(volatile unsigned int*)(KSEG1 + 0x0f000c08)
+#define VR4131_PCITAW2REG	(volatile unsigned int*)(KSEG1 + 0x0f000c0c)
+#define VR4131_PCIMIOAWREG	(volatile unsigned int*)(KSEG1 + 0x0f000c10)
+#define VR4131_PCICONFDREG	(volatile unsigned int*)(KSEG1 + 0x0f000c14)
+#define VR4131_PCICONFAREG	(volatile unsigned int*)(KSEG1 + 0x0f000c18)
+#define VR4131_PCIMAILREG	(volatile unsigned int*)(KSEG1 + 0x0f000c1c)
+#define VR4131_BUSERRADREG	(volatile unsigned int*)(KSEG1 + 0x0f000c24)
+#define VR4131_INTCNTSTAREG	(volatile unsigned int*)(KSEG1 + 0x0f000c28)
+#define VR4131_PCIEXACCREG	(volatile unsigned int*)(KSEG1 + 0x0f000c2c)
+#define VR4131_PCIRECONTREG	(volatile unsigned int*)(KSEG1 + 0x0f000c30)
+#define VR4131_PCIENREG		(volatile unsigned int*)(KSEG1 + 0x0f000c34)
+#define VR4131_PCICLKSELREG	(volatile unsigned int*)(KSEG1 + 0x0f000c38)
+#define VR4131_PCITRDYREG	(volatile unsigned int*)(KSEG1 + 0x0f000c3c)
+#define VR4131_PCICLKRUNREG	(volatile unsigned int*)(KSEG1 + 0x0f000c60)
+#define VR4131_PCIHOSTCONFIG	(volatile unsigned int*)(KSEG1 + 0x0f000d00)
+#define VR4131_VENDORIDREG	(volatile unsigned int*)(KSEG1 + 0x0f000d00)
+#define VR4131_DEVICEIDREG	(volatile unsigned int*)(KSEG1 + 0x0f000d00)
+#define VR4131_COMMANDREG	(volatile unsigned int*)(KSEG1 + 0x0f000d04)
+#define VR4131_STATUSREG	(volatile unsigned int*)(KSEG1 + 0x0f000d04)
+#define VR4131_REVREG		(volatile unsigned int*)(KSEG1 + 0x0f000d08)
+#define VR4131_CLASSREG		(volatile unsigned int*)(KSEG1 + 0x0f000d08)
+#define VR4131_CACHELSREG	(volatile unsigned int*)(KSEG1 + 0x0f000d0c)
+#define VR4131_LATTIMERRG	(volatile unsigned int*)(KSEG1 + 0x0f000d0c)
+#define VR4131_MAILBAREG	(volatile unsigned int*)(KSEG1 + 0x0f000d10)
+#define VR4131_PCIMBA1REG	(volatile unsigned int*)(KSEG1 + 0x0f000d14)
+#define VR4131_PCIMBA2REG	(volatile unsigned int*)(KSEG1 + 0x0f000d18)
+
+/*#define VR41XX_PCIIRQ_OFFSET    (VR41XX_IRQ_MAX + 1)	*/
+/*#define VR41XX_PCIIRQ_MAX       (VR41XX_IRQ_MAX + 12)	*/
+/*#define VR4122_PCI_HOST_BASE    0xa0000000		*/
+
+volatile unsigned int *pciconfigaddr;
+volatile unsigned int *pciconfigdata;
+
+#define PCI_ACCESS_READ  0
+#define PCI_ACCESS_WRITE 1
+
+/*
+ *	Access PCI Configuration Register for VR4131
+ */
+
+static int vr4131_pci_config_access (u8 access_type, u32 dev, u32 reg,
+				     u32 * data)
+{
+	u32 bus;
+	u32 device;
+
+	bus = ((dev & 0xff0000) >> 16);
+	device = ((dev & 0xf800) >> 11);
+
+	if (bus == 0) {
+		/* Type 0 Configuration */
+		*VR4131_PCICONFAREG = (u32) (1UL << device | (reg & 0xfc));
+	} else {
+		/* Type 1 Configuration */
+		*VR4131_PCICONFAREG = (u32) (dev | ((reg / 4) << 2) | 1);
+	}
+
+	if (access_type == PCI_ACCESS_WRITE) {
+		*VR4131_PCICONFDREG = *data;
+	} else {
+		*data = *VR4131_PCICONFDREG;
+	}
+
+	return (0);
+}
+
+static int vr4131_pci_read_config_byte (u32 hose, u32 dev, u32 reg, u8 * val)
+{
+	u32 data;
+
+	if (vr4131_pci_config_access (PCI_ACCESS_READ, dev, reg, &data))
+		return -1;
+
+	*val = (data >> ((reg & 3) << 3)) & 0xff;
+
+	return 0;
+}
+
+
+static int vr4131_pci_read_config_word (u32 hose, u32 dev, u32 reg, u16 * val)
+{
+	u32 data;
+
+	if (reg & 1)
+		return -1;
+
+	if (vr4131_pci_config_access (PCI_ACCESS_READ, dev, reg, &data))
+		return -1;
+
+	*val = (data >> ((reg & 3) << 3)) & 0xffff;
+
+	return 0;
+}
+
+
+static int vr4131_pci_read_config_dword (u32 hose, u32 dev, u32 reg,
+					 u32 * val)
+{
+	u32 data = 0;
+
+	if (reg & 3)
+		return -1;
+
+	if (vr4131_pci_config_access (PCI_ACCESS_READ, dev, reg, &data))
+		return -1;
+
+	*val = data;
+
+	return (0);
+}
+
+static int vr4131_pci_write_config_byte (u32 hose, u32 dev, u32 reg, u8 val)
+{
+	u32 data = 0;
+
+	if (vr4131_pci_config_access (PCI_ACCESS_READ, dev, reg, &data))
+		return -1;
+
+	data = (data & ~(0xff << ((reg & 3) << 3))) | (val <<
+						       ((reg & 3) << 3));
+
+	if (vr4131_pci_config_access (PCI_ACCESS_WRITE, dev, reg, &data))
+		return -1;
+
+	return 0;
+}
+
+
+static int vr4131_pci_write_config_word (u32 hose, u32 dev, u32 reg, u16 val)
+{
+	u32 data = 0;
+
+	if (reg & 1)
+		return -1;
+
+	if (vr4131_pci_config_access (PCI_ACCESS_READ, dev, reg, &data))
+		return -1;
+
+	data = (data & ~(0xffff << ((reg & 3) << 3))) | (val <<
+							 ((reg & 3) << 3));
+
+	if (vr4131_pci_config_access (PCI_ACCESS_WRITE, dev, reg, &data))
+		return -1;
+
+	return 0;
+}
+
+static int vr4131_pci_write_config_dword (u32 hose, u32 dev, u32 reg, u32 val)
+{
+	u32 data;
+
+	if (reg & 3) {
+		return -1;
+	}
+
+	data = val;
+
+	if (vr4131_pci_config_access (PCI_ACCESS_WRITE, dev, reg, &data))
+		return -1;
+
+	return (0);
+}
+
+
+/*
+ *	Initialize VR4131 PCIU
+ */
+
+vr4131_pciu_init ()
+{
+	/* PCI clock */
+	*VR4131_PCICLKSELREG = 0x00000002;
+
+	/* PCI memory and I/O space */
+	*VR4131_PCIMMAW1REG = 0x100F9010;
+	*VR4131_PCIMMAW2REG = 0x140FD014;
+	*VR4131_PCIMIOAWREG = 0x160FD000;
+
+	/* Target memory window */
+	*VR4131_PCITAW1REG = 0x00081000;	/* 64MB */
+	*VR4131_PCITAW2REG = 0x00000000;
+
+	*VR4131_MAILBAREG = 0UL;
+	*VR4131_PCIMBA1REG = 0UL;
+
+	*VR4131_PCITRDYREG = 0x00008004;
+
+	*VR4131_PCIENREG = 0x00000004;	/* PCI enable */
+	*VR4131_COMMANDREG = 0x02000007;
+}
+
+/*
+ *	Initialize Module
+ */
+
+void init_vr4131_pci (struct pci_controller *hose)
+{
+	hose->first_busno = 0;
+	hose->last_busno = 0xff;
+
+	vr4131_pciu_init ();	/* Initialize VR4131 PCIU */
+
+	/* PCI memory space #1 */
+	pci_set_region (hose->regions + 0,
+			0x10000000, 0xb0000000, 0x04000000, PCI_REGION_MEM);
+
+	/* PCI memory space #2 */
+	pci_set_region (hose->regions + 1,
+			0x14000000, 0xb4000000, 0x02000000, PCI_REGION_MEM);
+
+
+	/* PCI I/O space */
+	pci_set_region (hose->regions + 2,
+			0x16000000, 0xb6000000, 0x02000000, PCI_REGION_IO);
+
+	/* System memory space */
+	pci_set_region (hose->regions + 3,
+			0x00000000,
+			0x80000000,
+			0x04000000, PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+	hose->region_count = 4;
+
+	hose->read_byte = vr4131_pci_read_config_byte;
+	hose->read_word = vr4131_pci_read_config_word;
+	hose->read_dword = vr4131_pci_read_config_dword;
+	hose->write_byte = vr4131_pci_write_config_byte;
+	hose->write_word = vr4131_pci_write_config_word;
+	hose->write_dword = vr4131_pci_write_config_dword;
+
+	pci_register_hose (hose);
+
+	hose->last_busno = pci_hose_scan (hose);
+
+	return;
+}
--- a/board/trab/u-boot.lds
+++ b/board/trab/u-boot.lds
@@ -39,7 +39,7 @@ SECTIONS
 	  lib_generic/string.o	(.text)

 	. = DEFINED(env_offset) ? env_offset : .;
-	common/environment.o	(.ppcenv)
+	  common/environment.o	(.ppcenv)

 	  *(.text)
 	}
@@ -53,15 +53,12 @@ SECTIONS
 	. = ALIGN(4);
 	.got : { *(.got) }

-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
-
-	armboot_end_data = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;

 	. = ALIGN(4);
+	__bss_start = .;
 	.bss : { *(.bss) }
-
-
-	armboot_end = .;
+	_end = .;
 }
--- a/board/wepep250/u-boot.lds
+++ b/board/wepep250/u-boot.lds
@@ -48,12 +48,8 @@ SECTIONS
 	.u_boot_cmd : { *(.u_boot_cmd) }
 	__u_boot_cmd_end = .;

-	armboot_end_data = .;
-
 	. = ALIGN(4);
-	bss_start = .;
+	__bss_start = .;
 	.bss : { *(.bss) }
-	bss_end = .;
-
-	armboot_end = .;
+	_end = .;
 }
--- a/board/xpedite1k/Makefile
+++ b/board/xpedite1k/Makefile
@@ -0,0 +1,48 @@
+#
+# (C) Copyright 2002-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o
+OBJS +=flash.o
+SOBJS	= init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
--- a/board/xpedite1k/config.mk
+++ b/board/xpedite1k/config.mk
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2002-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# esd ADCIOP boards
+#
+
+#TEXT_BASE = 0xFFFE0000
+
+ifeq ($(ramsym),1)
+TEXT_BASE = 0x07FD0000
+else
+TEXT_BASE = 0xFFF80000
+endif
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+endif
--- a/board/xpedite1k/flash.c
+++ b/board/xpedite1k/flash.c
@@ -0,0 +1,607 @@
+/*
+ * (C) Copyright 2002-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
+ * Add support for Am29F016D and dynamic switch setting.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Modified 4/5/2001
+ * Wait for completion of each sector erase command issued
+ * 4/5/2001
+ * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
+ */
+
+/*
+ * Ported to XPedite1000, 1/2 mb boot flash only
+ * Travis B. Sawyer, <travis.sawyer@sandburst.com>
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+
+#undef DEBUG
+#ifdef DEBUG
+#define DEBUGF(x...) printf(x)
+#else
+#define DEBUGF(x...)
+#endif /* DEBUG */
+
+#define BOOT_SMALL_FLASH	32		/* 00100000 */
+#define FLASH_ONBD_N		2		/* 00000010 */
+#define FLASH_SRAM_SEL		1		/* 00000001 */
+
+#define BOOT_SMALL_FLASH_VAL	4
+#define FLASH_ONBD_N_VAL	2
+#define FLASH_SRAM_SEL_VAL	1
+
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+static unsigned long flash_addr_table[8][CFG_MAX_FLASH_BANKS] = {
+	{0xfff80000},	/* 0:000: configuraton 3 */
+	{0xfff90000},	/* 1:001: configuraton 4 */
+	{0xfffa0000},	/* 2:010: configuraton 7 */
+	{0xfffb0000},	/* 3:011: configuraton 8 */
+	{0xfffc0000},	/* 4:100: configuraton 1 */
+	{0xfffd0000},	/* 5:101: configuraton 2 */
+	{0xfffe0000},	/* 6:110: configuraton 5 */
+	{0xffff0000}	/* 7:111: configuraton 6 */
+};
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+
+
+#ifdef CONFIG_XPEDITE1K
+#define ADDR0		0x5555
+#define ADDR1		0x2aaa
+#define FLASH_WORD_SIZE unsigned char
+#endif
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long total_b = 0;
+	unsigned long size_b[CFG_MAX_FLASH_BANKS];
+	unsigned short index = 0;
+	int i;
+
+
+	DEBUGF("\n");
+	DEBUGF("FLASH: Index: %d\n", index);
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+		flash_info[i].sector_count = -1;
+		flash_info[i].size = 0;
+
+		/* check whether the address is 0 */
+		if (flash_addr_table[index][i] == 0) {
+			continue;
+		}
+
+		/* call flash_get_size() to initialize sector address */
+		size_b[i] = flash_get_size(
+			(vu_long *)flash_addr_table[index][i], &flash_info[i]);
+		flash_info[i].size = size_b[i];
+		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+			printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
+				i, size_b[i], size_b[i]<<20);
+			flash_info[i].sector_count = -1;
+			flash_info[i].size = 0;
+		}
+
+		total_b += flash_info[i].size;
+	}
+
+	return total_b;
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+	int k;
+	int size;
+	int erased;
+	volatile unsigned long *flash;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	case FLASH_MAN_SST:	printf ("SST ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AMD016:	printf ("AM29F016D (16 Mbit, uniform sector size)\n");
+		break;
+	case FLASH_AM040:	printf ("AM29F040 (512 Kbit, uniform sector size)\n");
+		break;
+	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+		break;
+	case FLASH_SST800A:	printf ("SST39LF/VF800 (8 Mbit, uniform sector size)\n");
+		break;
+	case FLASH_SST160A:	printf ("SST39LF/VF160 (16 Mbit, uniform sector size)\n");
+		break;
+	default:		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld KB in %d Sectors\n",
+		info->size >> 10, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		/*
+		 * Check if whole sector is erased
+		 */
+		if (i != (info->sector_count-1))
+			size = info->start[i+1] - info->start[i];
+		else
+			size = info->start[0] + info->size - info->start[i];
+		erased = 1;
+		flash = (volatile unsigned long *)info->start[i];
+		size = size >> 2;	 /* divide by 4 for longword access */
+		for (k=0; k<size; k++)
+		{
+			if (*flash++ != 0xffffffff)
+			{
+				erased = 0;
+				break;
+			}
+		}
+
+		if ((i % 5) == 0)
+			printf ("\n   ");
+			printf (" %08lX%s%s",
+				info->start[i],
+				erased ? " E" : "  ",
+				info->protect[i] ? "RO " : "   "
+				);
+			}
+		printf ("\n");
+		return;
+	}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	short i;
+	FLASH_WORD_SIZE value;
+	ulong base = (ulong)addr;
+	volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr;
+
+	DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr );
+
+	/* Write auto select command: read Manufacturer ID */
+	udelay(10000);
+	addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+	udelay(1000);
+	addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+	udelay(1000);
+	addr2[ADDR0] = (FLASH_WORD_SIZE)0x00900090;
+	udelay(1000);
+
+#ifdef CONFIG_ADCIOP
+	value = addr2[2];
+#else
+	value = addr2[0];
+#endif
+
+	DEBUGF("FLASH MANUFACT: %x\n", value);
+
+	switch (value) {
+	case (FLASH_WORD_SIZE)AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case (FLASH_WORD_SIZE)FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case (FLASH_WORD_SIZE)SST_MANUFACT:
+		info->flash_id = FLASH_MAN_SST;
+		break;
+	case (FLASH_WORD_SIZE)STM_MANUFACT:
+		info->flash_id = FLASH_MAN_STM;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+
+#ifdef CONFIG_ADCIOP
+	value = addr2[0];			/* device ID		*/
+	debug ("\ndev_code=%x\n", value);
+#else
+	value = addr2[1];			/* device ID		*/
+#endif
+
+	DEBUGF("\nFLASH DEVICEID: %x\n", value);
+
+	switch (value) {
+	case (FLASH_WORD_SIZE)AMD_ID_LV040B:
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x00080000; /* => 512 kb */
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+
+	}
+
+	/* set up sector start address table */
+	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+		    (info->flash_id  == FLASH_AM040) ||
+		    (info->flash_id  == FLASH_AMD016)) {
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * 0x00010000);
+	} else {
+		if (info->flash_id & FLASH_BTYPE) {
+			/* set sector offsets for bottom boot block type	*/
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00004000;
+			info->start[2] = base + 0x00006000;
+			info->start[3] = base + 0x00008000;
+			for (i = 4; i < info->sector_count; i++) {
+				info->start[i] = base + (i * 0x00010000) - 0x00030000;
+			}
+		} else {
+			/* set sector offsets for top boot block type		*/
+			i = info->sector_count - 1;
+			info->start[i--] = base + info->size - 0x00004000;
+			info->start[i--] = base + info->size - 0x00006000;
+			info->start[i--] = base + info->size - 0x00008000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00010000;
+			}
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+#ifdef CONFIG_ADCIOP
+		addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]);
+		info->protect[i] = addr2[4] & 1;
+#else
+		addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]);
+		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
+			info->protect[i] = 0;
+		else
+			info->protect[i] = addr2[2] & 1;
+#endif
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+#if 0 /* test-only */
+#ifdef CONFIG_ADCIOP
+		addr2 = (volatile unsigned char *)info->start[0];
+		addr2[ADDR0] = 0xAA;
+		addr2[ADDR1] = 0x55;
+		addr2[ADDR0] = 0xF0;  /* reset bank */
+#else
+		addr2 = (FLASH_WORD_SIZE *)info->start[0];
+		*addr2 = (FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
+#endif
+#else /* test-only */
+		addr2 = (FLASH_WORD_SIZE *)info->start[0];
+		*addr2 = (FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
+#endif /* test-only */
+	}
+
+	return (info->size);
+}
+
+int wait_for_DQ7(flash_info_t *info, int sect)
+{
+	ulong start, now, last;
+	volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[sect]);
+
+	start = get_timer (0);
+	last  = start;
+	while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) {
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return -1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {  /* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]);
+	volatile FLASH_WORD_SIZE *addr2;
+	int flag, prot, sect, l_sect;
+	int i;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) { /* not protected */
+			addr2 = (FLASH_WORD_SIZE *)(info->start[sect]);
+			printf("Erasing sector %p\n", addr2);
+
+			if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+				addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+				addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+				addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
+				addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+				addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+				addr2[0] = (FLASH_WORD_SIZE)0x00500050;	 /* block erase */
+				for (i=0; i<50; i++)
+					udelay(1000);  /* wait 1 ms */
+			} else {
+				addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+				addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+				addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
+				addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+				addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+				addr2[0] = (FLASH_WORD_SIZE)0x00300030;	 /* sector erase */
+			}
+			l_sect = sect;
+			/*
+			 * Wait for each sector to complete, it's more
+			 * reliable.  According to AMD Spec, you must
+			 * issue all erase commands within a specified
+			 * timeout.  This has been seen to fail, especially
+			 * if printf()s are included (for debug)!!
+			 */
+			wait_for_DQ7(info, sect);
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+#if 0
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+	wait_for_DQ7(info, l_sect);
+
+DONE:
+#endif
+	/* reset to read mode */
+	addr = (FLASH_WORD_SIZE *)info->start[0];
+	addr[0] = (FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t * info, ulong dest, ulong data)
+{
+	volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) (info->start[0]);
+	volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest;
+	volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data;
+	ulong start;
+	int i;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((volatile FLASH_WORD_SIZE *) dest) &
+	     (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
+		return (2);
+	}
+
+	for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) {
+		int flag;
+
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts ();
+
+		addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+		addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+		addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0;
+
+		dest2[i] = data2[i];
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts ();
+
+		/* data polling for D7 */
+		start = get_timer (0);
+		while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) !=
+		       (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) {
+
+			if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+				return (1);
+			}
+		}
+	}
+
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
--- a/board/xpedite1k/init.S
+++ b/board/xpedite1k/init.S
@@ -0,0 +1,96 @@
+/*
+*  Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
+*
+* See file CREDITS for list of people who contributed to this
+* project.
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; either version 2 of
+* the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+* MA 02111-1307 USA
+*/
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+
+/* General */
+#define TLB_VALID   0x00000200
+
+/* Supported page sizes */
+
+#define SZ_1K	    0x00000000
+#define SZ_4K	    0x00000010
+#define SZ_16K	    0x00000020
+#define SZ_64K	    0x00000030
+#define SZ_256K	    0x00000040
+#define SZ_1M	    0x00000050
+#define SZ_16M	    0x00000070
+#define SZ_256M	    0x00000090
+
+/* Storage attributes */
+#define SA_W	    0x00000800	    /* Write-through */
+#define SA_I	    0x00000400	    /* Caching inhibited */
+#define SA_M	    0x00000200	    /* Memory coherence */
+#define SA_G	    0x00000100	    /* Guarded */
+#define SA_E	    0x00000080	    /* Endian */
+
+/* Access control */
+#define AC_X	    0x00000024	    /* Execute */
+#define AC_W	    0x00000012	    /* Write */
+#define AC_R	    0x00000009	    /* Read */
+
+/* Some handy macros */
+
+#define EPN(e)		((e) & 0xfffffc00)
+#define TLB0(epn,sz)	( (EPN((epn)) | (sz) | TLB_VALID ) )
+#define TLB1(rpn,erpn)	( ((rpn)&0xfffffc00) | (erpn) )
+#define TLB2(a)		( (a)&0x00000fbf )
+
+#define tlbtab_start\
+	mflr    r1  ;\
+	bl 0f	    ;
+
+#define tlbtab_end\
+	.long 0, 0, 0	;   \
+0:	mflr    r0	;   \
+	mtlr    r1	;   \
+	blr		;
+
+#define tlbentry(epn,sz,rpn,erpn,attr)\
+	.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
+
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ *  Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+
+	.section .bootpg,"ax"
+	.globl tlbtab
+
+tlbtab:
+	tlbtab_start
+	tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+	tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
+	tlbentry( CFG_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
+	tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+	tlbentry( CFG_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+	tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
+	tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I )
+	tlbtab_end
--- a/board/m5282evb/u-boot.lds.debug
+++ b/board/m5282evb/u-boot.lds.debug
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000-2003
+ * (C) Copyright 2002-2004
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
@@ -27,6 +27,16 @@ SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/
   __DYNAMIC = 0;    */
 SECTIONS
 {
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  .bootpg 0xFFFFF000 :
+  {
+    cpu/ppc4xx/start.o	(.bootpg)
+  } = 0xffff
+
  /* Read-only sections, merged into text segment: */
  . = + SIZEOF_HEADERS;
  .interp : { *(.interp) }
@@ -56,13 +66,22 @@ SECTIONS
    /* WARNING - the following is hand-optimized to fit within	*/
    /* the sector layout of our flash chips!	XXX FIXME XXX	*/

-    cpu/mpc8xx/start.o	(.text)
+    cpu/ppc4xx/start.o	(.text)
+    board/xpedite1k/init.o	(.text)
+    cpu/ppc4xx/kgdb.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o	(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o	(.text)
+    cpu/ppc4xx/405gp_enet.o	(.text)
    common/dlmalloc.o	(.text)
-    ppc/vsprintf.o	(.text)
-    ppc/crc32.o		(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+    lib_generic/zlib.o		(.text)

-    . = env_offset;
-    common/environment.o(.text)
+/*    . = env_offset;*/
+/*    common/environment.o(.text)*/

    *(.text)
    *(.fixup)
@@ -74,13 +93,14 @@ SECTIONS
  {
    *(.rodata)
    *(.rodata1)
+    *(.rodata.str1.4)
  }
  .fini      : { *(.fini)    } =0
  .ctors     : { *(.ctors)   }
  .dtors     : { *(.dtors)   }

  /* Read-write section, merged into data segment: */
-  . = (. + 0x0FFF) & 0xFFFFF000;
+  . = (. + 0x00FF) & 0xFFFFFF00;
  _erotext = .;
  PROVIDE (erotext = .);
  .reloc   :
@@ -106,15 +126,20 @@ SECTIONS
  _edata  =  .;
  PROVIDE (edata = .);

+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
  __start___ex_table = .;
  __ex_table : { *(__ex_table) }
  __stop___ex_table = .;

-  . = ALIGN(4096);
+  . = ALIGN(256);
  __init_begin = .;
  .text.init : { *(.text.init) }
  .data.init : { *(.data.init) }
-  . = ALIGN(4096);
+  . = ALIGN(256);
  __init_end = .;

  __bss_start = .;
--- a/board/xpedite1k/u-boot.lds.debug
+++ b/board/xpedite1k/u-boot.lds.debug
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000-2003
+ * (C) Copyright 2002-2004
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
@@ -56,13 +56,21 @@ SECTIONS
    /* WARNING - the following is hand-optimized to fit within	*/
    /* the sector layout of our flash chips!	XXX FIXME XXX	*/

-    cpu/mpc8xx/start.o	(.text)
+    cpu/ppc4xx/start.o	(.text)
+    board/xpedite1k/init.o (.text)
+    cpu/ppc4xx/kgdb.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o	(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o	(.text)
+    cpu/ppc4xx/405gp_enet.o	(.text)
    common/dlmalloc.o	(.text)
-    ppc/vsprintf.o	(.text)
-    ppc/crc32.o		(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+    lib_generic/zlib.o		(.text)

-    . = env_offset;
-    common/environment.o(.text)
+/*    common/environment.o(.text) */

    *(.text)
    *(.fixup)
@@ -74,6 +82,7 @@ SECTIONS
  {
    *(.rodata)
    *(.rodata1)
+    *(.rodata.str1.4)
  }
  .fini      : { *(.fini)    } =0
  .ctors     : { *(.ctors)   }
@@ -106,15 +115,20 @@ SECTIONS
  _edata  =  .;
  PROVIDE (edata = .);

+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
  __start___ex_table = .;
  __ex_table : { *(__ex_table) }
  __stop___ex_table = .;

-  . = ALIGN(4096);
+  . = ALIGN(256);
  __init_begin = .;
  .text.init : { *(.text.init) }
  .data.init : { *(.data.init) }
-  . = ALIGN(4096);
+  . = ALIGN(256);
  __init_end = .;

  __bss_start = .;
--- a/board/xpedite1k/xpedite1k.c
+++ b/board/xpedite1k/xpedite1k.c
@@ -0,0 +1,358 @@
+/*
+ *  Copyright (C) 2003 Travis B. Sawyer	 <travis.sawyer@sandburst.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <asm/processor.h>
+#include <spd_sdram.h>
+#include <i2c.h>
+
+#define BOOT_SMALL_FLASH	32	/* 00100000 */
+#define FLASH_ONBD_N		2	/* 00000010 */
+#define FLASH_SRAM_SEL		1	/* 00000001 */
+
+long int fixed_sdram (void);
+
+int board_pre_init (void)
+{
+	unsigned long sdrreg;
+	/* TBS:	 Setup the GPIO access for the user LEDs */
+	mfsdr(sdr_pfc0, sdrreg);
+	mtsdr(sdr_pfc0, (sdrreg & ~0x00000100) | 0x00000E00);
+	out32(CFG_GPIO_BASE + 0x018, (USR_LED0 | USR_LED1 | USR_LED2 | USR_LED3));
+	LED0_OFF();
+	LED1_OFF();
+	LED2_OFF();
+	LED3_OFF();
+
+	/*--------------------------------------------------------------------
+	 * Setup the external bus controller/chip selects
+	 *-------------------------------------------------------------------*/
+
+	/* set the bus controller */
+	mtebc (pb0ap, 0x04055200);	/* FLASH/SRAM */
+	mtebc (pb0cr, 0xfff18000);	/* BAS=0xfff 1MB R/W 8-bit */
+
+	/*--------------------------------------------------------------------
+	 * Setup the interrupt controller polarities, triggers, etc.
+	 *-------------------------------------------------------------------*/
+	mtdcr (uic0sr, 0xffffffff);	/* clear all */
+	mtdcr (uic0er, 0x00000000);	/* disable all */
+	mtdcr (uic0cr, 0x00000003);	/* SMI & UIC1 crit are critical */
+	mtdcr (uic0pr, 0xfffffe00);	/* per ref-board manual */
+	mtdcr (uic0tr, 0x01c00000);	/* per ref-board manual */
+	mtdcr (uic0vr, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (uic0sr, 0xffffffff);	/* clear all */
+
+	mtdcr (uic1sr, 0xffffffff);	/* clear all */
+	mtdcr (uic1er, 0x00000000);	/* disable all */
+	mtdcr (uic1cr, 0x00000000);	/* all non-critical */
+	mtdcr (uic1pr, 0xffffc0ff);	/* per ref-board manual */
+	mtdcr (uic1tr, 0x00ff8000);	/* per ref-board manual */
+	mtdcr (uic1vr, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (uic1sr, 0xffffffff);	/* clear all */
+
+	mtdcr (uic2sr, 0xffffffff);	/* clear all */
+	mtdcr (uic2er, 0x00000000);	/* disable all */
+	mtdcr (uic2cr, 0x00000000);	/* all non-critical */
+	mtdcr (uic2pr, 0xffffffff);	/* per ref-board manual */
+	mtdcr (uic2tr, 0x00ff8c0f);	/* per ref-board manual */
+	mtdcr (uic2vr, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (uic2sr, 0xffffffff);	/* clear all */
+
+	mtdcr (uicb0sr, 0xfc000000); /* clear all */
+	mtdcr (uicb0er, 0x00000000); /* disable all */
+	mtdcr (uicb0cr, 0x00000000); /* all non-critical */
+	mtdcr (uicb0pr, 0xfc000000); /* */
+	mtdcr (uicb0tr, 0x00000000); /* */
+	mtdcr (uicb0vr, 0x00000001); /* */
+
+	LED0_ON();
+
+
+	return 0;
+}
+
+int checkboard (void)
+{
+	sys_info_t sysinfo;
+	get_sys_info (&sysinfo);
+
+	printf ("Board: XES XPedite1000 440GX\n");
+	printf ("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
+	printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
+	printf ("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
+	printf ("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
+	printf ("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
+
+	return (0);
+}
+
+
+long int initdram (int board_type)
+{
+	long dram_size = 0;
+
+#if defined(CONFIG_SPD_EEPROM)
+	dram_size = spd_sdram (0);
+#else
+	dram_size = fixed_sdram ();
+#endif
+	return dram_size;
+}
+
+
+#if defined(CFG_DRAM_TEST)
+int testdram (void)
+{
+	uint *pstart = (uint *) 0x00000000;
+	uint *pend = (uint *) 0x08000000;
+	uint *p;
+
+	for (p = pstart; p < pend; p++)
+		*p = 0xaaaaaaaa;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0xaaaaaaaa) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	for (p = pstart; p < pend; p++)
+		*p = 0x55555555;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0x55555555) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+	return 0;
+}
+#endif
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*************************************************************************
+ *  fixed sdram init -- doesn't use serial presence detect.
+ *
+ *  Assumes:	128 MB, non-ECC, non-registered
+ *		PLB @ 133 MHz
+ *
+ ************************************************************************/
+long int fixed_sdram (void)
+{
+	uint reg;
+
+	/*--------------------------------------------------------------------
+	 * Setup some default
+	 *------------------------------------------------------------------*/
+	mtsdram (mem_uabba, 0x00000000);	/* ubba=0 (default)		*/
+	mtsdram (mem_slio, 0x00000000);		/* rdre=0 wrre=0 rarw=0		*/
+	mtsdram (mem_devopt, 0x00000000);	/* dll=0 ds=0 (normal)		*/
+	mtsdram (mem_wddctr, 0x00000000);	/* wrcp=0 dcd=0			*/
+	mtsdram (mem_clktr, 0x40000000);	/* clkp=1 (90 deg wr) dcdt=0	*/
+
+	/*--------------------------------------------------------------------
+	 * Setup for board-specific specific mem
+	 *------------------------------------------------------------------*/
+	/*
+	 * Following for CAS Latency = 2.5 @ 133 MHz PLB
+	 */
+	mtsdram (mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
+	mtsdram (mem_tr0, 0x410a4012);	/* WR=2	 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
+	/* RA=10 RD=3			    */
+	mtsdram (mem_tr1, 0x8080082f);	/* SS=T2 SL=STAGE 3 CD=1 CT=0x02f   */
+	mtsdram (mem_rtr, 0x08200000);	/* Rate 15.625 ns @ 133 MHz PLB	    */
+	mtsdram (mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM    */
+	udelay (400);			/* Delay 200 usecs (min)	    */
+
+	/*--------------------------------------------------------------------
+	 * Enable the controller, then wait for DCEN to complete
+	 *------------------------------------------------------------------*/
+	mtsdram (mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit	    */
+	for (;;) {
+		mfsdram (mem_mcsts, reg);
+		if (reg & 0x80000000)
+			break;
+	}
+
+	return (128 * 1024 * 1024);	/* 128 MB			    */
+}
+#endif	/* !defined(CONFIG_SPD_EEPROM) */
+
+
+/*************************************************************************
+ *  pci_pre_init
+ *
+ *  This routine is called just prior to registering the hose and gives
+ *  the board the opportunity to check things. Returning a value of zero
+ *  indicates that things are bad & PCI initialization should be aborted.
+ *
+ *	Different boards may wish to customize the pci controller structure
+ *	(add regions, override default access routines, etc) or perform
+ *	certain pre-initialization actions.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
+int pci_pre_init(struct pci_controller * hose )
+{
+	unsigned long strap;
+
+	/*--------------------------------------------------------------------------+
+	 * TBS:
+	 *	The xpedite1k is a PrPMC board, however for our purposes it is the host
+	 *--------------------------------------------------------------------------*/
+	strap = mfdcr(cpc0_strp1);
+	if( (strap & 0x00100000) == 0 ){
+		printf("PCI: CPC0_STRP1[PAE] not set.\n");
+		return 0;
+	}
+
+	return 1;
+}
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
+
+/*************************************************************************
+ *  pci_target_init
+ *
+ *	The bootstrap configuration provides default settings for the pci
+ *	inbound map (PIM). But the bootstrap config choices are limited and
+ *	may not be sufficient for a given board.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+void pci_target_init(struct pci_controller * hose )
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/*--------------------------------------------------------------------------+
+	 * Disable everything
+	 *--------------------------------------------------------------------------*/
+	out32r( PCIX0_PIM0SA, 0 ); /* disable */
+	out32r( PCIX0_PIM1SA, 0 ); /* disable */
+	out32r( PCIX0_PIM2SA, 0 ); /* disable */
+	out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
+
+	/*--------------------------------------------------------------------------+
+	 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
+	 * options to not support sizes such as 128/256 MB.
+	 *--------------------------------------------------------------------------*/
+	out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
+	out32r( PCIX0_PIM0LAH, 0 );
+	out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
+
+	out32r( PCIX0_BAR0, 0 );
+
+	/*--------------------------------------------------------------------------+
+	 * Program the board's subsystem id/vendor id
+	 *--------------------------------------------------------------------------*/
+	out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
+	out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
+
+	out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
+}
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+
+
+/*************************************************************************
+ *  is_pci_host
+ *
+ *	This routine is called to determine if a pci scan should be
+ *	performed. With various hardware environments (especially cPCI and
+ *	PPMC) it's insufficient to depend on the state of the arbiter enable
+ *	bit in the strap register, or generic host/adapter assumptions.
+ *
+ *	Rather than hard-code a bad assumption in the general 440 code, the
+ *	440 pci code requires the board to decide at runtime.
+ *
+ *	Return 0 for adapter mode, non-zero for host (monarch) mode.
+ *
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI)
+int is_pci_host(struct pci_controller *hose)
+{
+	/* The ebony board is always configured as host. */
+	/* TBS:	 The xpedite1k is not necessarily the host, however for our purposes, it is. */
+	return(1);
+}
+#endif /* defined(CONFIG_PCI) */
+
+#ifdef CONFIG_POST
+/*
+ * Returns 1 if keys pressed to start the power-on long-running tests
+ * Called from board_init_f().
+ */
+int post_hotkeys_pressed(void)
+{
+
+	return (ctrlc());
+}
+
+void post_word_store (ulong a)
+{
+	volatile ulong *save_addr =
+		(volatile ulong *)(CFG_POST_WORD_ADDR);
+
+	*save_addr = a;
+}
+
+ulong post_word_load (void)
+{
+	volatile ulong *save_addr =
+		(volatile ulong *)(CFG_POST_WORD_ADDR);
+
+	return *save_addr;
+}
+#endif
+
+/*-----------------------------------------------------------------------------
+ * board_get_enetaddr -- Read the MAC Addresses in the I2C EEPROM
+ *-----------------------------------------------------------------------------
+ */
+static int enetaddr_num = 0;
+void board_get_enetaddr (uchar * enet)
+{
+	int i;
+	unsigned char buff[0x100], *cp;
+
+	/* Initialize I2C					*/
+	i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+
+	/* Read 256 bytes in EEPROM				*/
+	i2c_read (0x50, 0, 1, buff, 0x100);
+
+	if (enetaddr_num == 0) {
+		cp = &buff[0xF4];
+		enetaddr_num = 1;
+	}
+	else
+		cp = &buff[0xFA];
+
+	for (i = 0; i < 6; i++,cp++)
+		enet[i] = *cp;
+
+	printf ("MAC address = %02x:%02x:%02x:%02x:%02x:%02x\n",
+		enet[0], enet[1], enet[2], enet[3], enet[4], enet[5]);
+
+}
--- a/common/cmd_bootm.c
+++ b/common/cmd_bootm.c
@@ -333,8 +333,14 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 #ifdef CONFIG_BZIP2
 	case IH_COMP_BZIP2:
 		printf ("   Uncompressing %s ... ", name);
+		/*
+		 * If we've got less than 4 MB of malloc() space,
+		 * use slower decompression algorithm which requires
+		 * at most 2300 KB of memory.
+		 */
 		i = BZ2_bzBuffToBuffDecompress ((char*)ntohl(hdr->ih_load),
-						&unc_len, (char *)data, len, 0, 0);
+						&unc_len, (char *)data, len,
+						CFG_MALLOC_LEN < (4096 * 1024), 0);
 		if (i != BZ_OK) {
 			printf ("BUNZIP2 ERROR %d - must RESET board to recover\n", i);
 			SHOW_BOOT_PROGRESS (-6);
--- a/common/cmd_mii.c
+++ b/common/cmd_mii.c
@@ -54,7 +54,7 @@ int do_mii (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 	unsigned short	data;
 	int		rcode = 0;

-#ifdef CONFIG_8xx
+#if defined(CONFIG_8xx) || defined(CONFIG_MCF52x2)
 	mii_init ();
 #endif

--- a/common/cmd_pcmcia.c
+++ b/common/cmd_pcmcia.c
@@ -160,6 +160,9 @@ int pcmcia_on (void)
 }
 #else

+#ifdef CONFIG_BMS2003
+# define  BMS2003_FRAM_TIMING	(PCMCIA_SHT(2) | PCMCIA_SST(2) | PCMCIA_SL(4))
+#endif
 #if defined(CONFIG_LWMON) || defined(CONFIG_NSCU)
 # define  CFG_PCMCIA_TIMING	(PCMCIA_SHT(9) | PCMCIA_SST(3) | PCMCIA_SL(12))
 #else
@@ -197,6 +200,17 @@ int pcmcia_on (void)
 		switch (i) {
 #ifdef CONFIG_IDE_8xx_PCCARD
 		case 4:
+#ifdef CONFIG_BMS2003
+		    {	/* map FRAM area */
+			win->or = (	PCMCIA_BSIZE_256K
+				|	PCMCIA_PPS_8
+				|	PCMCIA_PRS_ATTR
+				|	slotbit
+				|	PCMCIA_PV
+				|	BMS2003_FRAM_TIMING );
+			break;
+		    }
+#endif
 		case 0:	{	/* map attribute memory */
 			win->or = (	PCMCIA_BSIZE_64M
 				|	PCMCIA_PPS_8
--- a/common/console.c
+++ b/common/console.c
@@ -191,6 +191,11 @@ void putc (const char c)
 {
 	DECLARE_GLOBAL_DATA_PTR;

+#ifdef CONFIG_SILENT_CONSOLE
+	if (gd->flags & GD_FLG_SILENT)
+		return;
+#endif
+
 	if (gd->flags & GD_FLG_DEVINIT) {
 		/* Send to the standard output */
 		fputc (stdout, c);
@@ -204,6 +209,11 @@ void puts (const char *s)
 {
 	DECLARE_GLOBAL_DATA_PTR;

+#ifdef CONFIG_SILENT_CONSOLE
+	if (gd->flags & GD_FLG_SILENT)
+		return;
+#endif
+
 	if (gd->flags & GD_FLG_DEVINIT) {
 		/* Send to the standard output */
 		fputs (stdout, s);
--- a/common/miiphyutil.c
+++ b/common/miiphyutil.c
@@ -99,7 +99,9 @@ int miiphy_reset (unsigned char addr)
 #endif
 		return (-1);
 	}
-
+#ifdef CONFIG_PHY_RESET_DELAY
+	udelay (CONFIG_PHY_RESET_DELAY);	/* Intel LXT971A needs this */
+#endif
 	/*
 	 * Poll the control register for the reset bit to go to 0 (it is
 	 * auto-clearing).  This should happen within 0.5 seconds per the
--- a/cpu/arm720t/cpu.c
+++ b/cpu/arm720t/cpu.c
@@ -87,7 +87,7 @@ int cpu_init (void)
 #ifdef CONFIG_USE_IRQ
 	DECLARE_GLOBAL_DATA_PTR;

-	IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_LEN - 4;
+	IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
 	FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
 #endif
 	return 0;
--- a/cpu/arm720t/start.S
+++ b/cpu/arm720t/start.S
@@ -63,7 +63,7 @@ _fiq:			.word fiq
 *
 * Startup Code (reset vector)
 *
- * do important init only if we don't start from memory!
+ * do important init only if we don't start from RAM!
 * relocate armboot to ram
 * setup stack
 * jump to second stage
@@ -79,16 +79,15 @@ _armboot_start:
 	.word _start

 /*
- * Note: _armboot_end_data and _armboot_end are defined
- * by the (board-dependent) linker script.
- * _armboot_end_data is the first usable FLASH address after armboot
+ * These are defined in the board-specific linker script.
 */
-.globl _armboot_end_data
-_armboot_end_data:
-	.word armboot_end_data
-.globl _armboot_end
-_armboot_end:
-	.word armboot_end
+.globl _bss_start
+_bss_start:
+	.word __bss_start
+
+.globl _bss_end
+_bss_end:
+	.word _end

 #ifdef CONFIG_USE_IRQ
 /* IRQ stack memory (calculated at run-time) */
@@ -131,7 +130,7 @@ relocate:				/* relocate U-Boot to RAM	    */
 	beq     stack_setup

 	ldr	r2, _armboot_start
-	ldr	r3, _armboot_end
+	ldr	r3, _bss_start
 	sub	r2, r3, r2		/* r2 <- size of armboot            */
 	add	r2, r0, r2		/* r2 <- source end address         */

@@ -151,6 +150,17 @@ stack_setup:
 #endif
 	sub	sp, r0, #12		/* leave 3 words for abort-stack    */

+clear_bss:
+	ldr	r0, _bss_start		/* find start of bss segment        */
+	add	r0, r0, #4		/* start at first byte of bss       */
+	ldr	r1, _bss_end		/* stop here                        */
+	mov 	r2, #0x00000000		/* clear                            */
+
+clbss_l:str	r2, [r0]		/* clear loop...                    */
+	add	r0, r0, #4
+	cmp	r0, r1
+	bne	clbss_l
+
 	ldr	pc, _start_armboot

 _start_armboot:	.word start_armboot
@@ -225,7 +235,7 @@ cpu_init_crit:

 	/*
 	 * before relocating, we have to setup RAM timing
-	 * because memory timing is board-dependend, you will
+	 * because memory timing is board-dependent, you will
 	 * find a memsetup.S in your board directory.
 	 */
 	mov	ip, lr
@@ -281,9 +291,9 @@ cpu_init_crit:
 	stmia	sp, {r0 - r12}			@ Calling r0-r12
 	add     r8, sp, #S_PC

-	ldr	r2, _armboot_end
-	add	r2, r2, #CONFIG_STACKSIZE
-	sub	r2, r2, #8
+	ldr	r2, _armboot_start
+	sub	r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
+	sub	r2, r2, #(CFG_GBL_DATA_SIZE+8)  @ set base 2 words into abort stack
 	ldmia	r2, {r2 - r4}                   @ get pc, cpsr, old_r0
 	add	r0, sp, #S_FRAME_SIZE		@ restore sp_SVC

@@ -314,9 +324,9 @@ cpu_init_crit:
 	.endm

 	.macro get_bad_stack
-	ldr	r13, _armboot_end		@ setup our mode stack
-	add	r13, r13, #CONFIG_STACKSIZE	@ resides at top of normal stack
-	sub	r13, r13, #8
+	ldr	r13, _armboot_start		@ setup our mode stack
+	sub	r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
+	sub	r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack

 	str	lr, [r13]			@ save caller lr / spsr
 	mrs	lr, spsr
--- a/cpu/arm920t/cpu.c
+++ b/cpu/arm920t/cpu.c
@@ -92,7 +92,7 @@ int cpu_init (void)
 #ifdef CONFIG_USE_IRQ
 	DECLARE_GLOBAL_DATA_PTR;

-	IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_LEN - 4;
+	IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
 	FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
 #endif
 	return 0;
--- a/cpu/arm920t/start.S
+++ b/cpu/arm920t/start.S
@@ -80,16 +80,15 @@ _armboot_start:
 	.word _start

 /*
- * Note: _armboot_end_data and _armboot_end are defined
- * by the (board-dependent) linker script.
- * _armboot_end_data is the first usable FLASH address after armboot
+ * These are defined in the board-specific linker script.
 */
-.globl _armboot_end_data
-_armboot_end_data:
-	.word armboot_end_data
-.globl _armboot_end
-_armboot_end:
-	.word armboot_end
+.globl _bss_start
+_bss_start:
+	.word __bss_start
+
+.globl _bss_end
+_bss_end:
+	.word _end

 #ifdef CONFIG_USE_IRQ
 /* IRQ stack memory (calculated at run-time) */
@@ -170,7 +169,7 @@ relocate:				/* relocate U-Boot to RAM	    */
 	beq     stack_setup

 	ldr	r2, _armboot_start
-	ldr	r3, _armboot_end
+	ldr	r3, _bss_start
 	sub	r2, r3, r2		/* r2 <- size of armboot            */
 	add	r2, r0, r2		/* r2 <- source end address         */

@@ -190,6 +189,17 @@ stack_setup:
 #endif
 	sub	sp, r0, #12		/* leave 3 words for abort-stack    */

+clear_bss:
+	ldr	r0, _bss_start		/* find start of bss segment        */
+	add	r0, r0, #4		/* start at first byte of bss       */
+	ldr	r1, _bss_end		/* stop here                        */
+	mov 	r2, #0x00000000		/* clear                            */
+
+clbss_l:str	r2, [r0]		/* clear loop...                    */
+	add	r0, r0, #4
+	cmp	r0, r1
+	bne	clbss_l
+
 #if 0
 	/* try doing this stuff after the relocation */
 	ldr     r0, =pWTCON
@@ -303,9 +313,9 @@ cpu_init_crit:
 	.macro	bad_save_user_regs
 	sub	sp, sp, #S_FRAME_SIZE
 	stmia	sp, {r0 - r12}			@ Calling r0-r12
-	ldr	r2, _armboot_end
-	add	r2, r2, #CONFIG_STACKSIZE
-	sub	r2, r2, #8
+	ldr	r2, _armboot_start
+	sub	r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
+	sub	r2, r2, #(CFG_GBL_DATA_SIZE+8)  @ set base 2 words into abort stack
 	ldmia	r2, {r2 - r3}			@ get pc, cpsr
 	add	r0, sp, #S_FRAME_SIZE		@ restore sp_SVC

@@ -336,9 +346,9 @@ cpu_init_crit:
 	.endm

 	.macro get_bad_stack
-	ldr	r13, _armboot_end		@ setup our mode stack
-	add	r13, r13, #CONFIG_STACKSIZE	@ resides at top of normal stack
-	sub	r13, r13, #8
+	ldr	r13, _armboot_start		@ setup our mode stack
+	sub	r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
+	sub	r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack

 	str	lr, [r13]			@ save caller lr / spsr
 	mrs	lr, spsr
--- a/cpu/arm925t/cpu.c
+++ b/cpu/arm925t/cpu.c
@@ -93,7 +93,7 @@ int cpu_init (void)
 #ifdef CONFIG_USE_IRQ
 	DECLARE_GLOBAL_DATA_PTR;

-	IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_LEN - 4;
+	IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
 	FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
 #endif
 	return 0;
--- a/cpu/arm925t/start.S
+++ b/cpu/arm925t/start.S
@@ -89,16 +89,15 @@ _armboot_start:
 	.word _start

 /*
- * Note: _armboot_end_data and _armboot_end are defined
- * by the (board-dependent) linker script.
- * _armboot_end_data is the first usable FLASH address after armboot
+ * These are defined in the board-specific linker script.
 */
-.globl _armboot_end_data
-_armboot_end_data:
-	.word armboot_end_data
-.globl _armboot_end
-_armboot_end:
-	.word armboot_end
+.globl _bss_start
+_bss_start:
+	.word __bss_start
+
+.globl _bss_end
+_bss_end:
+	.word _end

 #ifdef CONFIG_USE_IRQ
 /* IRQ stack memory (calculated at run-time) */
@@ -176,7 +175,7 @@ relocate:				/* relocate U-Boot to RAM	    */
 	beq     stack_setup

 	ldr	r2, _armboot_start
-	ldr	r3, _armboot_end
+	ldr	r3, _bss_start
 	sub	r2, r3, r2		/* r2 <- size of armboot            */
 	add	r2, r0, r2		/* r2 <- source end address         */

@@ -196,6 +195,17 @@ stack_setup:
 #endif
 	sub	sp, r0, #12		/* leave 3 words for abort-stack    */

+clear_bss:
+	ldr	r0, _bss_start		/* find start of bss segment        */
+	add	r0, r0, #4		/* start at first byte of bss       */
+	ldr	r1, _bss_end		/* stop here                        */
+	mov 	r2, #0x00000000		/* clear                            */
+
+clbss_l:str	r2, [r0]		/* clear loop...                    */
+	add	r0, r0, #4
+	cmp	r0, r1
+	bne	clbss_l
+
 	ldr	pc, _start_armboot

 _start_armboot:	.word start_armboot
@@ -283,9 +293,9 @@ cpu_init_crit:
 	sub	sp, sp, #S_FRAME_SIZE           @ carve out a frame on current user stack
 	stmia	sp, {r0 - r12}			@ Save user registers (now in svc mode) r0-r12

-	ldr	r2, _armboot_end                @ find top of stack
-	add	r2, r2, #CONFIG_STACKSIZE       @ find base of normal stack
-	sub	r2, r2, #8                      @ set base 2 words into abort stack
+	ldr	r2, _armboot_start
+	sub	r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
+	sub	r2, r2, #(CFG_GBL_DATA_SIZE+8)  @ set base 2 words into abort stack
 	ldmia	r2, {r2 - r3}                   @ get values for "aborted" pc and cpsr (into parm regs)
 	add	r0, sp, #S_FRAME_SIZE		@ grab pointer to old stack

@@ -316,9 +326,9 @@ cpu_init_crit:
 	.endm

 	.macro get_bad_stack
-	ldr	r13, _armboot_end		@ get bottom of stack (into sp by by user stack pointer).
-	add	r13, r13, #CONFIG_STACKSIZE	@ head to reserved words at the top of the stack
-	sub	r13, r13, #8                    @ reserved a couple spots in abort stack
+	ldr	r13, _armboot_start		@ setup our mode stack
+	sub	r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
+	sub	r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack

 	str	lr, [r13]			@ save caller lr in position 0 of saved stack
 	mrs	lr, spsr                        @ get the spsr
--- a/cpu/arm926ejs/cpu.c
+++ b/cpu/arm926ejs/cpu.c
@@ -93,7 +93,7 @@ int cpu_init (void)
 #ifdef CONFIG_USE_IRQ
 	DECLARE_GLOBAL_DATA_PTR;

-	IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_LEN - 4;
+	IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
 	FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
 #endif
 	return 0;
--- a/cpu/arm926ejs/start.S
+++ b/cpu/arm926ejs/start.S
@@ -97,16 +97,15 @@ _armboot_start:
 	.word _start

 /*
- * Note: _armboot_end_data and _armboot_end are defined
- * by the (board-dependent) linker script.
- * _armboot_end_data is the first usable FLASH address after armboot
+ * These are defined in the board-specific linker script.
 */
-.globl _armboot_end_data
-_armboot_end_data:
-	.word armboot_end_data
-.globl _armboot_end
-_armboot_end:
-	.word armboot_end
+.globl _bss_start
+_bss_start:
+	.word __bss_start
+
+.globl _bss_end
+_bss_end:
+	.word _end

 #ifdef CONFIG_USE_IRQ
 /* IRQ stack memory (calculated at run-time) */
@@ -170,7 +169,7 @@ relocate:				/* relocate U-Boot to RAM	    */
 	beq     stack_setup

 	ldr	r2, _armboot_start
-	ldr	r3, _armboot_end
+	ldr	r3, _bss_start
 	sub	r2, r3, r2		/* r2 <- size of armboot            */
 	add	r2, r0, r2		/* r2 <- source end address         */

@@ -190,6 +189,17 @@ stack_setup:
 #endif
 	sub	sp, r0, #12		/* leave 3 words for abort-stack    */

+clear_bss:
+	ldr	r0, _bss_start		/* find start of bss segment        */
+	add	r0, r0, #4		/* start at first byte of bss       */
+	ldr	r1, _bss_end		/* stop here                        */
+	mov 	r2, #0x00000000		/* clear                            */
+
+clbss_l:str	r2, [r0]		/* clear loop...                    */
+	add	r0, r0, #4
+	cmp	r0, r1
+	bne	clbss_l
+
 	ldr	pc, _start_armboot

 _start_armboot:
@@ -278,9 +288,10 @@ cpu_init_crit:
 	@ carve out a frame on current user stack
 	sub	sp, sp, #S_FRAME_SIZE
 	stmia	sp, {r0 - r12}	@ Save user registers (now in svc mode) r0-r12
-	ldr	r2, _armboot_end	@ find top of stack
-	add	r2, r2, #CONFIG_STACKSIZE	@ find base of normal stack
-	sub	r2, r2, #8	@ set base 2 words into abort stack
+
+	ldr	r2, _armboot_start
+	sub	r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
+	sub	r2, r2, #(CFG_GBL_DATA_SIZE+8)  @ set base 2 words into abort stack
 	@ get values for "aborted" pc and cpsr (into parm regs)
 	ldmia	r2, {r2 - r3}
 	add	r0, sp, #S_FRAME_SIZE		@ grab pointer to old stack
@@ -312,11 +323,9 @@ cpu_init_crit:
 	.endm

 	.macro get_bad_stack
-	@ get bottom of stack (into sp by by user stack pointer).
-	ldr	r13, _armboot_end
-	@ head to reserved words at the top of the stack
-	add	r13, r13, #CONFIG_STACKSIZE
-	sub	r13, r13, #8	@ reserved a couple spots in abort stack
+	ldr	r13, _armboot_start		@ setup our mode stack
+	sub	r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
+	sub	r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack

 	str	lr, [r13]	@ save caller lr in position 0 of saved stack
 	mrs	lr, spsr	@ get the spsr
--- a/cpu/at91rm9200/cpu.c
+++ b/cpu/at91rm9200/cpu.c
@@ -87,7 +87,7 @@ int cpu_init(void)
 #ifdef CONFIG_USE_IRQ
 	DECLARE_GLOBAL_DATA_PTR;

-	IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_LEN - 4;
+	IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
 	FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
 #endif
 	return 0;
--- a/cpu/at91rm9200/start.S
+++ b/cpu/at91rm9200/start.S
@@ -79,19 +79,15 @@ _armboot_start:
 	.word _start

 /*
- * Note: _armboot_end_data and _armboot_end are defined
- * by the (board-dependent) linker script.
- * _armboot_end_data is the first usable FLASH address after armboot
+ * These are defined in the board-specific linker script.
 */
-.globl _armboot_end_data
-_armboot_end_data:
-	.word armboot_end_data
-/*
- * Note: armboot_end is defined by the (board-dependent) linker script
- */
-.globl _armboot_end
-_armboot_end:
-	.word armboot_end
+.globl _bss_start
+_bss_start:
+	.word __bss_start
+
+.globl _bss_end
+_bss_end:
+	.word _end

 #ifdef CONFIG_USE_IRQ
 /* IRQ stack memory (calculated at run-time) */
@@ -149,6 +145,17 @@ stack_setup:
 #endif
 	sub	sp, r0, #12		/* leave 3 words for abort-stack    */

+clear_bss:
+	ldr	r0, _bss_start		/* find start of bss segment        */
+	add	r0, r0, #4		/* start at first byte of bss       */
+	ldr	r1, _bss_end		/* stop here                        */
+	mov 	r2, #0x00000000		/* clear                            */
+
+clbss_l:str	r2, [r0]		/* clear loop...                    */
+	add	r0, r0, #4
+	cmp	r0, r1
+	bne	clbss_l
+
 	ldr pc,_start_armboot

 _start_armboot: .word start_armboot
@@ -212,9 +219,9 @@ cpu_init_crit:
 	stmia	sp, {r0 - r12}			@ Calling r0-r12
 	add     r8, sp, #S_PC

-	ldr	r2, _armboot_end
-	add	r2, r2, #CONFIG_STACKSIZE
-	sub	r2, r2, #8
+	ldr	r2, _armboot_start
+	sub	r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
+	sub	r2, r2, #(CFG_GBL_DATA_SIZE+8)  @ set base 2 words into abort stack
 	ldmia	r2, {r2 - r4}                   @ get pc, cpsr, old_r0
 	add	r0, sp, #S_FRAME_SIZE		@ restore sp_SVC

@@ -245,9 +252,9 @@ cpu_init_crit:
 	.endm

 	.macro get_bad_stack
-	ldr	r13, _armboot_end		@ setup our mode stack
-	add	r13, r13, #CONFIG_STACKSIZE	@ resides at top of normal stack
-	sub	r13, r13, #8
+	ldr	r13, _armboot_start		@ setup our mode stack
+	sub	r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
+	sub	r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack

 	str	lr, [r13]			@ save caller lr / spsr
 	mrs	lr, spsr
--- a/cpu/coldfire/cpu.c
+++ b/cpu/coldfire/cpu.c
@@ -1,87 +0,0 @@
-/*
- * (C) Copyright 2000-2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <watchdog.h>
-#include <command.h>
-#ifdef CONFIG_M5272
-#include <asm/m5272.h>
-#endif
-#ifdef CONFIG_M5282
-#include <asm/m5282.h>
-#endif
-#include <asm/cache.h>
-
-int do_reset (cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
-{
-	return 0;
-}
-
-unsigned long get_tbclk (void)
-{
-	return CFG_HZ;
-}
-
-int checkcpu (void)
-{
-#ifdef CONFIG_M5272
-	puts ("MOTOROLA Coldfire MCF5272\n");
-#endif
-#ifdef CONFIG_M5282
-	puts ("MOTOROLA Coldfire MCF5282\n");
-#endif
-	return 0;
-}
-
-void do_exception (void)
-{
-	printf ("\n\n*** Unexpected exception ... Reset Board! ***\n");
-	for (;;);
-}
-
-void do_buserror (void)
-{
-	printf ("\n\n*** Bus error ... Reset Board! ***\n");
-	for (;;);
-}
-
-void do_addresserror (void)
-{
-	printf ("\n\n*** Address error ... Reset Board! ***\n");
-	for (;;);
-}
-
-void trap_init (ulong value)
-{
-	extern void buserror_handler (void);
-	extern void addresserror_handler (void);
-	extern void exception_handler (void);
-	unsigned long *vec = 0;
-	int i;
-
-	vec[2] = buserror_handler;
-	vec[3] = addresserror_handler;
-	for (i = 4; i < 256; i++) {
-		vec[i] = exception_handler;
-	}
-}
--- a/cpu/coldfire/fec.c
+++ b/cpu/coldfire/fec.c
@@ -1,296 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <commproc.h>
-#include <net.h>
-#include <command.h>
-
-
-/**************************************************************
- *
- * FEC Ethernet Initialization Routine
- *
- *************************************************************/
-
-#define FEC_ECNTRL_ETHER_EN	0x00000002
-#define FEC_ECNTRL_RESET	0x00000001
-
-#define FEC_RCNTRL_BC_REJ	0x00000010
-#define FEC_RCNTRL_PROM		0x00000008
-#define FEC_RCNTRL_MII_MODE	0x00000004
-#define FEC_RCNTRL_DRT		0x00000002
-#define FEC_RCNTRL_LOOP		0x00000001
-
-#define FEC_TCNTRL_FDEN		0x00000004
-#define FEC_TCNTRL_HBC		0x00000002
-#define FEC_TCNTRL_GTS		0x00000001
-
-#define	FEC_RESET_DELAY		50000
-
-
-/* Ethernet Transmit and Receive Buffers */
-#define DBUF_LENGTH  1520
-#define TX_BUF_CNT 2
-#define TOUT_LOOP 100
-
-#define PKT_MAXBUF_SIZE		1518
-#define PKT_MINBUF_SIZE		64
-#define PKT_MAXBLR_SIZE		1520
-
-
-#ifdef CONFIG_M5272
-#define FEC_ADDR 0x10000840
-#endif
-#ifdef CONFIG_M5282
-#define FEC_ADDR 0x40001000
-#endif
-
-#undef	ET_DEBUG
-
-#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(FEC_ENET)
-
-
-static char txbuf[DBUF_LENGTH];
-
-static uint rxIdx;		/* index of the current RX buffer */
-static uint txIdx;		/* index of the current TX buffer */
-
-/*
-  * FEC Ethernet Tx and Rx buffer descriptors allocated at the
-  *  immr->udata_bd address on Dual-Port RAM
-  * Provide for Double Buffering
-  */
-
-typedef volatile struct CommonBufferDescriptor {
-	cbd_t rxbd[PKTBUFSRX];	/* Rx BD */
-	cbd_t txbd[TX_BUF_CNT];	/* Tx BD */
-} RTXBD;
-
-static RTXBD *rtx = 0x380000;
-
-
-int eth_send (volatile void *packet, int length)
-{
-	int j, rc;
-	volatile fec_t *fecp = FEC_ADDR;
-
-	/* section 16.9.23.3
-	 * Wait for ready
-	 */
-	j = 0;
-	while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY)
-	       && (j < TOUT_LOOP)) {
-		udelay (1);
-		j++;
-	}
-	if (j >= TOUT_LOOP) {
-		printf ("TX not ready\n");
-	}
-
-	rtx->txbd[txIdx].cbd_bufaddr = (uint) packet;
-	rtx->txbd[txIdx].cbd_datlen = length;
-	rtx->txbd[txIdx].cbd_sc |= BD_ENET_TX_READY | BD_ENET_TX_LAST;
-
-	/* Activate transmit Buffer Descriptor polling */
-	fecp->fec_x_des_active = 0x01000000;	/* Descriptor polling active    */
-
-	j = 0;
-	while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY)
-	       && (j < TOUT_LOOP)) {
-		udelay (1);
-		j++;
-	}
-	if (j >= TOUT_LOOP) {
-		printf ("TX timeout\n");
-	}
-#ifdef ET_DEBUG
-	printf ("%s[%d] %s: cycles: %d    status: %x  retry cnt: %d\n",
-		__FILE__, __LINE__, __FUNCTION__, j, rtx->txbd[txIdx].cbd_sc,
-		(rtx->txbd[txIdx].cbd_sc & 0x003C) >> 2);
-#endif
-	/* return only status bits */ ;
-	rc = (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS);
-
-	txIdx = (txIdx + 1) % TX_BUF_CNT;
-
-	return rc;
-}
-
-int eth_rx (void)
-{
-	int length;
-	volatile fec_t *fecp = FEC_ADDR;
-
-	for (;;) {
-		/* section 16.9.23.2 */
-		if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
-			length = -1;
-			break;	/* nothing received - leave for() loop */
-		}
-
-		length = rtx->rxbd[rxIdx].cbd_datlen;
-
-		if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) {
-#ifdef ET_DEBUG
-			printf ("%s[%d] err: %x\n",
-				__FUNCTION__, __LINE__,
-				rtx->rxbd[rxIdx].cbd_sc);
-#endif
-		} else {
-			/* Pass the packet up to the protocol layers. */
-			NetReceive (NetRxPackets[rxIdx], length - 4);
-		}
-
-		/* Give the buffer back to the FEC. */
-		rtx->rxbd[rxIdx].cbd_datlen = 0;
-
-		/* wrap around buffer index when necessary */
-		if ((rxIdx + 1) >= PKTBUFSRX) {
-			rtx->rxbd[PKTBUFSRX - 1].cbd_sc =
-				(BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
-			rxIdx = 0;
-		} else {
-			rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
-			rxIdx++;
-		}
-
-		/* Try to fill Buffer Descriptors */
-		fecp->fec_r_des_active = 0x01000000;	/* Descriptor polling active    */
-	}
-
-	return length;
-}
-
-
-int eth_init (bd_t * bd)
-{
-
-	int i;
-	volatile fec_t *fecp = FEC_ADDR;
-
-	/* Whack a reset.
-	 * A delay is required between a reset of the FEC block and
-	 * initialization of other FEC registers because the reset takes
-	 * some time to complete. If you don't delay, subsequent writes
-	 * to FEC registers might get killed by the reset routine which is
-	 * still in progress.
-	 */
-
-	fecp->fec_ecntrl = FEC_ECNTRL_RESET;
-	for (i = 0;
-	     (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
-	     ++i) {
-		udelay (1);
-	}
-	if (i == FEC_RESET_DELAY) {
-		printf ("FEC_RESET_DELAY timeout\n");
-		return 0;
-	}
-
-	/* We use strictly polling mode only
-	 */
-	fecp->fec_imask = 0;
-
-	/* Clear any pending interrupt */
-	fecp->fec_ievent = 0xffffffff;
-
-	/* Set station address   */
-#define ea bd->bi_enetaddr
-	fecp->fec_addr_low = (ea[0] << 24) | (ea[1] << 16) |
-		(ea[2] << 8) | (ea[3]);
-	fecp->fec_addr_high = (ea[4] << 24) | (ea[5] << 16);
-#undef ea
-
-	/* Clear multicast address hash table
-	 */
-	fecp->fec_hash_table_high = 0;
-	fecp->fec_hash_table_low = 0;
-
-	/* Set maximum receive buffer size.
-	 */
-	fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
-
-	/*
-	 * Setup Buffers and Buffer Desriptors
-	 */
-	rxIdx = 0;
-	txIdx = 0;
-
-	/*
-	 * Setup Receiver Buffer Descriptors (13.14.24.18)
-	 * Settings:
-	 *     Empty, Wrap
-	 */
-	for (i = 0; i < PKTBUFSRX; i++) {
-		rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
-		rtx->rxbd[i].cbd_datlen = 0;	/* Reset */
-		rtx->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i];
-	}
-	rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
-
-	/*
-	 * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
-	 * Settings:
-	 *    Last, Tx CRC
-	 */
-	for (i = 0; i < TX_BUF_CNT; i++) {
-		rtx->txbd[i].cbd_sc = BD_ENET_TX_LAST | BD_ENET_TX_TC;
-		rtx->txbd[i].cbd_datlen = 0;	/* Reset */
-		rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]);
-	}
-	rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
-
-	/* Set receive and transmit descriptor base
-	 */
-	fecp->fec_r_des_start = (unsigned int) (&rtx->rxbd[0]);
-	fecp->fec_x_des_start = (unsigned int) (&rtx->txbd[0]);
-
-	/* Enable MII mode
-	 */
-
-	/* Half duplex mode */
-	fecp->fec_r_cntrl = (PKT_MAXBUF_SIZE << 16) | FEC_RCNTRL_MII_MODE;
-	fecp->fec_r_cntrl = (PKT_MAXBUF_SIZE << 16) | FEC_RCNTRL_MII_MODE;
-	fecp->fec_x_cntrl = 0;
-
-	fecp->fec_mii_speed = 0;
-
-	/* Now enable the transmit and receive processing
-	 */
-	fecp->fec_ecntrl = FEC_ECNTRL_ETHER_EN;
-
-	/* And last, try to fill Rx Buffer Descriptors */
-	fecp->fec_r_des_active = 0x01000000;	/* Descriptor polling active    */
-
-	return 1;
-}
-
-
-void eth_halt (void)
-{
-	volatile fec_t *fecp = FEC_ADDR;
-
-	fecp->fec_ecntrl = 0;
-}
-#endif
--- a/Show More
+++ b/Show More
Author	SHA1	Message	Date
wdenk	cf56e11019	Add Auto-MDIX support for INCA-IP	2004-02-20 22:02:48 +00:00
wdenk	198ea9e294	Last minute fixes / cleanup.	2004-02-12 15:11:57 +00:00
wdenk	b2daeb8e0f	Fix typo. Release version 1.0.2	2004-02-12 14:09:38 +00:00
wdenk	bf9e3b38f7	* Some code cleanup * Patch by Josef Baumgartner, 10 Feb 2004: Fixes for Coldfire port * Patch by Brad Kemp, 11 Feb 2004: Fix CFI flash driver problems	2004-02-12 00:47:09 +00:00
wdenk	a2d18bb7d3	* Make sure to use a bus clock divider of 2 only when running TQM8xxM modules at CPU clock frequencies above 66 MHz. * Optimize flash programming speed for LWMON (by another 100% :-)	2004-02-11 21:35:18 +00:00
wdenk	cd37d9e6e5	* Patch by Jian Zhang, 3 Feb 2004: - Changed the incorrect FAT12BUFSIZE - data_begin in fsdata can be negative. Changed it to be short. * Code cleanup	2004-02-10 00:03:41 +00:00
wdenk	ec4c544bed	Patches by Stephan Linz, 30 Jan 2004: 1: - board/altera/common/flash.c:flash_erase(): o allow interrupts befor get_timer() call o check-up each erased sector and avoid unexpected timeouts - board/altera/dk1c20/dk1s10.c:board_early_init_f(): o enclose sevenseg_set() in cpp condition - remove the ASMI configuration for DK1S10_standard_32 (never present) - fix some typed in mistakes in the NIOS documentation 2: - split DK1C20 configuration into several header files: o two new files for each NIOS CPU description o U-Boot related part is remaining in DK1C20.h 3: - split DK1S10 configuration into several header files: o two new files for each NIOS CPU description o U-Boot related part is remaining in DK1S10.h 4: - Add support for the Microtronix Linux Development Kit NIOS CPU configuration at the Altera Nios Development Kit, Stratix Edition (DK-1S10) 5: - Add documentation for the Altera Nios Development Kit, Stratix Edition (DK-1S10) 6: - Add support for the Nios Serial Peripharel Interface (SPI) (master only) 7: - Add support for the common U-Boot SPI framework at RTC driver DS1306	2004-02-09 23:12:24 +00:00
wdenk	b98fff1d6a	* Patch by Rahul Shanbhag, 28 Jan 2004: Fix flash protection/locking handling for OMAP1610 innovator board. * Patch by Rolf Peukert, 28 Jan 2004: fix flash write problems on CSB226 board (write with 32 bit bus width) * Patches by Mark Jonas, 16 Jan 2004: - fix rounding error when calculating baudrates for MPC5200 PSCs - make sure CFG_RAMBOOT and CFG_LOWBOOT are not enabled at the same time which is not supported	2004-02-09 20:51:26 +00:00
wdenk	5653fc335a	* Patch by Yuli Barcohen, 26 Jan 2004: Allow bzip2 compression for small memory footprint boards * Patch by Brad Kemp, 21 Jan 2004: Add support for CFI flash driver for both the Intel and the AMD command sets. * Patch by Travis Sawyer, 20 Jan 2004: Fix pci bridge auto enumeration of sibling p2p bridges. * Patch by Tolunay Orkun, 12 Jan 2004: Add some delays as needed for Intel LXT971A PHY support * Patches by Stephan Linz, 09 Jan 2004: - avoid warning: unused variable `piop' in board/altera/common/sevenseg.c - make DK1C20 board configuration related to ASMI conform to documentation	2004-02-08 22:55:38 +00:00
wdenk	f6e20fc6ca	Patch by Anders Larsen, 09 Jan 2004: ARM memory layout fixes: the abort-stack is now set up in the correct RAM area, and the BSS is zeroed out as it should be. Furthermore, the magic variables 'armboot_end' and 'armboot_end_data' of the linker scripts are replaced by '__bss_start' and '_end', resp., which is a further step to eliminate unnecessary differences between the implementation of the CPU architectures.	2004-02-08 19:38:38 +00:00
wdenk	f4863a7aec	* Patch by liang a lei, 9 Jan 2004: Fix Intel 28F128J3 ID in include/flash.h * Patch by Masami Komiya, 09 Jan 2004: add support for TB0229 board (NEC VR4131 MIPS processor) * Patch by Leon Kukovec, 12 Dec 2003: changed extern __inline__ into static __inline__ in include/linux/byteorder/swab.h	2004-02-07 01:27:10 +00:00
wdenk	ba56f62576	Patch by Travis Sawyer, 30 Dec 2003: Add support for IBM PPC440GX. Multiple EMAC Ethernet devices, select MDI port based on enabled EMAC device. Add support for XES Inc <http://www.xes-inc.com> XPedite1000 440GX base PrPMC board.	2004-02-06 23:19:44 +00:00
wdenk	a6cccaea5a	* Patch by Wolter Kamphuis, 15 Dec 2003: made CONFIG_SILENT_CONSOLE usable on all architectures * Disable date command on TQM866M - there is no RTC on MPC866	2004-02-06 21:48:22 +00:00