* Make sure to use a bus clock divider of 2 only when running TQM8xxM

modules at CPU clock frequencies above 66 MHz.

* Optimize flash programming speed for LWMON (by another 100% :-)

CHANGELOG

@@ -2,6 +2,101 @@
 Changes since U-Boot 1.0.1:
 ======================================================================
 
+* Make sure to use a bus clock divider of 2 only when running TQM8xxM
+  modules at CPU clock frequencies above 66 MHz.
+  
+* Optimize flash programming speed for LWMON (by another 100% :-)
+
+* Patch by Jian Zhang, 3 Feb 2004:
+  - Changed the incorrect FAT12BUFSIZE
+  - data_begin in fsdata can be negative. Changed it to be short.
+
+* Patches by Stephan Linz, 30 Jan 2004:
+  1: - board/altera/common/flash.c:flash_erase():
+       o allow interrupts befor get_timer() call
+       o check-up each erased sector and avoid unexpected timeouts
+     - board/altera/dk1c20/dk1s10.c:board_early_init_f():
+       o enclose sevenseg_set() in cpp condition
+     - remove the ASMI configuration for DK1S10_standard_32 (never present)
+     - fix some typed in mistakes in the NIOS documentation
+  2: - split DK1C20 configuration into several header files:
+       o two new files for each NIOS CPU description
+       o U-Boot related part is remaining in DK1C20.h
+  3: - split DK1S10 configuration into several header files:
+       o two new files for each NIOS CPU description
+       o U-Boot related part is remaining in DK1S10.h
+  4: - Add support for the Microtronix Linux Development Kit
+       NIOS CPU configuration at the Altera Nios Development Kit,
+       Stratix Edition (DK-1S10)
+  5: - Add documentation for the Altera Nios Development Kit,
+       Stratix Edition (DK-1S10)
+  6: - Add support for the Nios Serial Peripharel Interface (SPI)
+       (master only)
+  7: - Add support for the common U-Boot SPI framework at
+       RTC driver DS1306
+
+* Patch by Rahul Shanbhag, 28 Jan 2004:
+  Fix flash protection/locking handling for OMAP1610 innovator board.
+
+* Patch by Rolf Peukert, 28 Jan 2004:
+  fix flash write problems on CSB226 board (write with 32 bit bus width)
+
+* Patches by Mark Jonas, 16 Jan 2004:
+  - fix rounding error when calculating baudrates for MPC5200 PSCs
+  - make sure CFG_RAMBOOT and CFG_LOWBOOT are not enabled at the same
+    time which is not supported
+
+* Patch by Yuli Barcohen, 26 Jan 2004:
+  Allow bzip2 compression for small memory footprint boards
+
+* Patch by Brad Kemp, 21 Jan 2004:
+  Add support for CFI flash driver for both the Intel and the AMD
+  command sets.
+
+* Patch by Travis Sawyer, 20 Jan 2004:
+  Fix pci bridge auto enumeration of sibling p2p bridges.
+
+* Patch by Tolunay Orkun, 12 Jan 2004:
+  Add some delays as needed for Intel LXT971A PHY support
+
+* Patches by Stephan Linz, 09 Jan 2004:
+  - avoid warning: unused variable `piop' in board/altera/common/sevenseg.c
+  - make DK1C20 board configuration related to ASMI conform to
+    documentation
+
+* Patch by Anders Larsen, 09 Jan 2004:
+
+  ARM memory layout fixes: the abort-stack is now set up in the
+  correct RAM area, and the BSS is zeroed out as it should be.
+
+  Furthermore, the magic variables 'armboot_end' and 'armboot_end_data'
+  of the linker scripts are replaced by '__bss_start' and '_end',
+  resp., which is a further step to eliminate unnecessary differences
+  between the implementation of the CPU architectures.
+
+* Patch by liang a lei, 9 Jan 2004:
+  Fix Intel 28F128J3 ID in include/flash.h
+
+* Patch by Masami Komiya, 09 Jan 2004:
+  add support for TB0229 board (NEC VR4131 MIPS processor)
+
+* Patch by Leon Kukovec, 12 Dec 2003:
+  changed extern __inline__ into static __inline__ in
+  include/linux/byteorder/swab.h
+
+* Patch by Travis Sawyer, 30 Dec 2003:
+  Add support for IBM PPC440GX. Multiple EMAC Ethernet devices,
+  select MDI port based on enabled EMAC device.
+  Add support for XES Inc <http://www.xes-inc.com> XPedite1000 440GX
+  base PrPMC board.
+
+* Patch by Wolter Kamphuis, 15 Dec 2003:
+  made CONFIG_SILENT_CONSOLE usable on all architectures
+
+* Disable date command on TQM866M - there is no RTC on MPC866
+
+* Fix variable CPU clock for MPC859/866 systems for low CPU clocks
+
 * Implement adaptive SDRAM timing configuration based on actual CPU
   clock frequency for INCA-IP; fix problem with board hanging when
   switching from 150MHz to 100MHz

CREDITS

@@ -276,6 +276,10 @@ N: Neil Russell
 E: caret@c-side.com
 D: Author of LiMon-1.4.2, which contributed some ideas
 
+N: Travis B. Sawyer
+E: travis.sawyer@sandburst.com
+D: Support for IBM PPC440GX, XES XPedite1000 440GX PrPMC board.
+
 N: Paolo Scaffardi
 E: arsenio@tin.it
 D: FADS823 configuration, MPC823 video support, I2C, wireless keyboard, lots more

MAKEALL

@@ -64,6 +64,7 @@ LIST_4xx="	\
 	ML2		OCRTC		ORSG		PCI405		\
 	PIP405		PLU405          PMC405          PPChameleonEVB	\
 	VOH405          W7OLMC		W7OLMG          WALNUT405	\
+	XPEDITE1K							\
 "
 
 #########################################################################
@@ -176,7 +177,7 @@ LIST_x86="${LIST_I486}"
 
 LIST_nios="	\
 	DK1C20 DK1C20_standard_32					\
-	DK1S10 DK1S10_standard_32					\
+	DK1S10 DK1S10_standard_32 DK1S10_mtx_ldk_20			\
 "
 
 #-----------------------------------------------------------------------

Makefile

@@ -635,6 +635,9 @@ W7OLMG_config: unconfig
 WALNUT405_config:unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx walnut405
 
+XPEDITE1K_config:unconfig
+	@./mkconfig $(@:_config=) ppc ppc4xx xpedite1k
+
 #########################################################################
 ## MPC824x Systems
 #########################################################################
@@ -1024,6 +1027,9 @@ incaip_config: unconfig
 		}
 	@./mkconfig -a $(call xtract_incaip,$@) mips mips incaip
 
+tb0229_config: unconfig
+	@./mkconfig $(@:_config=) mips mips tb0229
+
 #########################################################################
 ## MIPS64 5Kc
 #########################################################################
@@ -1058,6 +1064,7 @@ DK1C20_config:	unconfig
 
 DK1S10_safe_32_config		\
 DK1S10_standard_32_config	\
+DK1S10_mtx_ldk_20_config	\
 DK1S10_config:	unconfig
 	@ >include/config.h
 	@[ -z "$(findstring _safe_32,$@)" ] || \
@@ -1068,6 +1075,10 @@ DK1S10_config:	unconfig
 		{ echo "#define CONFIG_NIOS_STANDARD_32 1" >>include/config.h ; \
 		  echo "... NIOS 'standard_32' configuration" ; \
 		}
+	@[ -z "$(findstring _mtx_ldk_20,$@)" ] || \
+		{ echo "#define CONFIG_NIOS_MTX_LDK_20 1" >>include/config.h ; \
+		  echo "... NIOS 'mtx_ldk_20' configuration" ; \
+		}
 	@[ -z "$(findstring DK1S10_config,$@)" ] || \
 		{ echo "#define CONFIG_NIOS_STANDARD_32 1" >>include/config.h ; \
 		  echo "... NIOS 'standard_32' configuration (DEFAULT)" ; \

README

@@ -141,7 +141,7 @@ Directory Hierarchy:
 
 - cpu/74xx_7xx	Files specific to Motorola MPC74xx and 7xx CPUs
 - cpu/arm925t	Files specific to ARM	   925	   CPUs
-- cpu/arm926ejs	Files specific to ARM	926	CPUs
+- cpu/arm926ejs Files specific to ARM	926	CPUs
 - cpu/mpc5xx	Files specific to Motorola MPC5xx  CPUs
 - cpu/mpc8xx	Files specific to Motorola MPC8xx  CPUs
 - cpu/mpc824x	Files specific to Motorola MPC824x CPUs
@@ -150,22 +150,22 @@ Directory Hierarchy:
 - cpu/ppc4xx	Files specific to IBM	   4xx	   CPUs
 
 
-- board/LEOX/   Files specific to boards manufactured by The LEOX team
+- board/LEOX/	Files specific to boards manufactured by The LEOX team
 - board/LEOX/elpt860	Files specific to ELPT860 boards
 - board/RPXClassic
 		Files specific to RPXClassic boards
-- board/RPXlite	Files specific to RPXlite    boards
+- board/RPXlite Files specific to RPXlite    boards
 - board/at91rm9200dk Files specific to AT91RM9200DK boards
 - board/c2mon	Files specific to c2mon	     boards
-- board/cmi	Files specific to cmi        boards
+- board/cmi	Files specific to cmi	     boards
 - board/cogent	Files specific to Cogent     boards
 		(need further configuration)
 		Files specific to CPCIISER4  boards
-- board/cpu86	Files specific to CPU86      boards
+- board/cpu86	Files specific to CPU86	     boards
 - board/cray/	Files specific to boards manufactured by Cray
-- board/cray/L1		Files specific to L1         boards
+- board/cray/L1		Files specific to L1	     boards
 - board/cu824	Files specific to CU824	     boards
-- board/ebony   Files specific to IBM Ebony board
+- board/ebony	Files specific to IBM Ebony board
 - board/eric	Files specific to ERIC	     boards
 - board/esd/	Files specific to boards manufactured by ESD
 - board/esd/adciop	Files specific to ADCIOP     boards
@@ -175,8 +175,8 @@ Directory Hierarchy:
 - board/esd/cpciiser4	Files specific to CPCIISER4  boards
 - board/esd/common	Common files for ESD boards
 - board/esd/dasa_sim	Files specific to DASA_SIM   boards
-- board/esd/du405	Files specific to DU405      boards
-- board/esd/ocrtc	Files specific to OCRTC      boards
+- board/esd/du405	Files specific to DU405	     boards
+- board/esd/ocrtc	Files specific to OCRTC	     boards
 - board/esd/pci405	Files specific to PCI405     boards
 - board/esteem192e
 		Files specific to ESTEEM192E boards
@@ -211,17 +211,17 @@ Directory Hierarchy:
 - board/mpl/common	Common files for MPL boards
 - board/mpl/pip405	Files specific to PIP405     boards
 - board/mpl/mip405	Files specific to MIP405     boards
-- board/mpl/vcma9	Files specific to VCMA9      boards
-- board/musenki	Files specific to MUSEKNI    boards
-- board/mvs1	Files specific to MVS1       boards
-- board/nx823   Files specific to NX823      boards
-- board/oxc	Files specific to OXC        boards
+- board/mpl/vcma9	Files specific to VCMA9	     boards
+- board/musenki Files specific to MUSEKNI    boards
+- board/mvs1	Files specific to MVS1	     boards
+- board/nx823	Files specific to NX823	     boards
+- board/oxc	Files specific to OXC	     boards
 - board/omap1510inn
 		Files specific to OMAP 1510 Innovator boards
 - board/omap1610inn
 		Files specific to OMAP 1610 Innovator boards
-- board/pcippc2	Files specific to PCIPPC2/PCIPPC6 boards
-- board/pm826	Files specific to PM826      boards
+- board/pcippc2 Files specific to PCIPPC2/PCIPPC6 boards
+- board/pm826	Files specific to PM826	     boards
 - board/ppmc8260
 		Files specific to PPMC8260   boards
 - board/snmc/qs850	Files specific to QS850/823  boards
@@ -232,24 +232,24 @@ Directory Hierarchy:
 		Files specific to RSDproto   boards
 - board/sandpoint
 		Files specific to Sandpoint  boards
-- board/sbc8260	Files specific to SBC8260    boards
+- board/sbc8260 Files specific to SBC8260    boards
 - board/sacsng	Files specific to SACSng     boards
 - board/siemens Files specific to boards manufactured by Siemens AG
 - board/siemens/CCM	Files specific to CCM	     boards
 - board/siemens/IAD210	Files specific to IAD210     boards
-- board/siemens/SCM	Files specific to SCM        boards
+- board/siemens/SCM	Files specific to SCM	     boards
 - board/siemens/pcu_e	Files specific to PCU_E	     boards
 - board/sixnet	Files specific to SIXNET     boards
 - board/spd8xx	Files specific to SPD8xxTS   boards
 - board/tqm8260 Files specific to TQM8260    boards
 - board/tqm8xx	Files specific to TQM8xxL    boards
-- board/w7o	Files specific to W7O        boards
+- board/w7o	Files specific to W7O	     boards
 - board/walnut405
 		Files specific to Walnut405  boards
-- board/westel/	Files specific to boards manufactured by Westel Wireless
+- board/westel/ Files specific to boards manufactured by Westel Wireless
 - board/westel/amx860	Files specific to AMX860     boards
-- board/utx8245	Files specific to UTX8245   boards
-- board/zpc1900	Files specific to Zephyr Engineering ZPC.1900 board
+- board/utx8245 Files specific to UTX8245   boards
+- board/zpc1900 Files specific to Zephyr Engineering ZPC.1900 board
 
 Software Configuration:
 =======================
@@ -336,49 +336,49 @@ The following options need to be configured:
 		PowerPC based boards:
 		---------------------
 
-		CONFIG_ADCIOP,     CONFIG_ICU862      CONFIG_RPXsuper,
-		CONFIG_ADS860,     CONFIG_IP860,      CONFIG_SM850,
-		CONFIG_AMX860,     CONFIG_IPHASE4539, CONFIG_SPD823TS,
-		CONFIG_AR405,      CONFIG_IVML24,     CONFIG_SXNI855T,
-		CONFIG_BAB7xx,     CONFIG_IVML24_128, CONFIG_Sandpoint8240,
-		CONFIG_CANBT,      CONFIG_IVML24_256, CONFIG_Sandpoint8245,
-		CONFIG_CCM,        CONFIG_IVMS8,      CONFIG_TQM823L,
-		CONFIG_CPCI405,    CONFIG_IVMS8_128,  CONFIG_TQM850L,
+		CONFIG_ADCIOP,	   CONFIG_ICU862      CONFIG_RPXsuper,
+		CONFIG_ADS860,	   CONFIG_IP860,      CONFIG_SM850,
+		CONFIG_AMX860,	   CONFIG_IPHASE4539, CONFIG_SPD823TS,
+		CONFIG_AR405,	   CONFIG_IVML24,     CONFIG_SXNI855T,
+		CONFIG_BAB7xx,	   CONFIG_IVML24_128, CONFIG_Sandpoint8240,
+		CONFIG_CANBT,	   CONFIG_IVML24_256, CONFIG_Sandpoint8245,
+		CONFIG_CCM,	   CONFIG_IVMS8,      CONFIG_TQM823L,
+		CONFIG_CPCI405,	   CONFIG_IVMS8_128,  CONFIG_TQM850L,
 		CONFIG_CPCI4052,   CONFIG_IVMS8_256,  CONFIG_TQM855L,
 		CONFIG_CPCIISER4,  CONFIG_LANTEC,     CONFIG_TQM860L,
-		CONFIG_CPU86,      CONFIG_MBX,        CONFIG_TQM8260,
-		CONFIG_CRAYL1,     CONFIG_MBX860T,    CONFIG_TTTech,
-		CONFIG_CU824,      CONFIG_MHPC,       CONFIG_UTX8245,
+		CONFIG_CPU86,	   CONFIG_MBX,	      CONFIG_TQM8260,
+		CONFIG_CRAYL1,	   CONFIG_MBX860T,    CONFIG_TTTech,
+		CONFIG_CU824,	   CONFIG_MHPC,	      CONFIG_UTX8245,
 		CONFIG_DASA_SIM,   CONFIG_MIP405,     CONFIG_W7OLMC,
-		CONFIG_DU405,      CONFIG_MOUSSE,     CONFIG_W7OLMG,
-		CONFIG_ELPPC,      CONFIG_MPC8260ADS, CONFIG_WALNUT405,
-		CONFIG_ERIC,       CONFIG_MUSENKI,    CONFIG_ZUMA,
-		CONFIG_ESTEEM192E, CONFIG_MVS1,       CONFIG_c2mon,
-		CONFIG_ETX094,     CONFIG_NX823,      CONFIG_cogent_mpc8260,
+		CONFIG_DU405,	   CONFIG_MOUSSE,     CONFIG_W7OLMG,
+		CONFIG_ELPPC,	   CONFIG_MPC8260ADS, CONFIG_WALNUT405,
+		CONFIG_ERIC,	   CONFIG_MUSENKI,    CONFIG_ZUMA,
+		CONFIG_ESTEEM192E, CONFIG_MVS1,	      CONFIG_c2mon,
+		CONFIG_ETX094,	   CONFIG_NX823,      CONFIG_cogent_mpc8260,
 		CONFIG_EVB64260,   CONFIG_OCRTC,      CONFIG_cogent_mpc8xx,
-		CONFIG_FADS823,    CONFIG_ORSG,       CONFIG_ep8260,
-		CONFIG_FADS850SAR, CONFIG_OXC,        CONFIG_gw8260,
+		CONFIG_FADS823,	   CONFIG_ORSG,	      CONFIG_ep8260,
+		CONFIG_FADS850SAR, CONFIG_OXC,	      CONFIG_gw8260,
 		CONFIG_FADS860T,   CONFIG_PCI405,     CONFIG_hermes,
-		CONFIG_FLAGADM,    CONFIG_PCIPPC2,    CONFIG_hymod,
-		CONFIG_FPS850L,    CONFIG_PCIPPC6,    CONFIG_lwmon,
-		CONFIG_GEN860T,    CONFIG_PIP405,     CONFIG_pcu_e,
-		CONFIG_GENIETV,    CONFIG_PM826,      CONFIG_ppmc8260,
-		CONFIG_GTH,        CONFIG_RPXClassic, CONFIG_rsdproto,
-		CONFIG_IAD210,     CONFIG_RPXlite,    CONFIG_sbc8260,
-		CONFIG_EBONY,      CONFIG_sacsng,     CONFIG_FPS860L,
-		CONFIG_V37,        CONFIG_ELPT860,    CONFIG_CMI,
-		CONFIG_NETVIA,     CONFIG_RBC823,     CONFIG_ZPC1900,
+		CONFIG_FLAGADM,	   CONFIG_PCIPPC2,    CONFIG_hymod,
+		CONFIG_FPS850L,	   CONFIG_PCIPPC6,    CONFIG_lwmon,
+		CONFIG_GEN860T,	   CONFIG_PIP405,     CONFIG_pcu_e,
+		CONFIG_GENIETV,	   CONFIG_PM826,      CONFIG_ppmc8260,
+		CONFIG_GTH,	   CONFIG_RPXClassic, CONFIG_rsdproto,
+		CONFIG_IAD210,	   CONFIG_RPXlite,    CONFIG_sbc8260,
+		CONFIG_EBONY,	   CONFIG_sacsng,     CONFIG_FPS860L,
+		CONFIG_V37,	   CONFIG_ELPT860,    CONFIG_CMI,
+		CONFIG_NETVIA,	   CONFIG_RBC823,     CONFIG_ZPC1900,
 		CONFIG_MPC8540ADS, CONFIG_MPC8560ADS, CONFIG_QS850,
-		CONFIG_QS823,      CONFIG_QS860T,     CONFIG_DB64360,
+		CONFIG_QS823,	   CONFIG_QS860T,     CONFIG_DB64360,
 		CONFIG_DB64460,	   CONFIG_DUET_ADS
 
 		ARM based boards:
 		-----------------
 
 		CONFIG_HHP_CRADLE,  CONFIG_DNP1110,    CONFIG_EP7312,
-		CONFIG_IMPA7,       CONFIG_LART,       CONFIG_LUBBOCK,
+		CONFIG_IMPA7,	    CONFIG_LART,       CONFIG_LUBBOCK,
 		CONFIG_INNOVATOROMAP1510,	CONFIG_INNOVATOROMAP1610
-		CONFIG_SHANNON,     CONFIG_SMDK2400,   CONFIG_SMDK2410,
+		CONFIG_SHANNON,	    CONFIG_SMDK2400,   CONFIG_SMDK2410,
 		CONFIG_TRAB,	    CONFIG_VCMA9,      CONFIG_AT91RM9200DK
 
 
@@ -415,12 +415,28 @@ The following options need to be configured:
 		Define exactly one of
 		CONFIG_MPC8240, CONFIG_MPC8245
 
-- 8xx CPU Options: (if using an 8xx cpu)
+- 8xx CPU Options: (if using an MPC8xx cpu)
 		Define one or more of
 		CONFIG_8xx_GCLK_FREQ	- if get_gclk_freq() cannot work
 					  e.g. if there is no 32KHz
 					  reference PIT/RTC clock
 
+- 859/866 CPU options: (if using a MPC859 or MPC866 CPU):
+		CFG_866_OSCCLK
+		CFG_866_CPUCLK_MIN
+		CFG_866_CPUCLK_MAX
+		CFG_866_CPUCLK_DEFAULT
+			See doc/README.MPC866
+
+		CFG_MEASURE_CPUCLK
+
+		Define this to measure the actual CPU clock instead
+		of relying on the correctness of the configured
+		values. Mostly useful for board bringup to make sure
+		the PLL is locked at the intended frequency. Note
+		that this requires a (stable) reference clock (32 kHz
+		RTC clock),
+
 - Linux Kernel Interface:
 		CONFIG_CLOCKS_IN_MHZ
 
@@ -463,11 +479,11 @@ The following options need to be configured:
 						bit-blit (cf. smiLynxEM)
 			VIDEO_VISIBLE_COLS	visible pixel columns
 						(cols=pitch)
-			VIDEO_VISIBLE_ROWS      visible pixel rows
-			VIDEO_PIXEL_SIZE        bytes per pixel
+			VIDEO_VISIBLE_ROWS	visible pixel rows
+			VIDEO_PIXEL_SIZE	bytes per pixel
 			VIDEO_DATA_FORMAT	graphic data format
 						(0-5, cf. cfb_console.c)
-			VIDEO_FB_ADRS           framebuffer address
+			VIDEO_FB_ADRS		framebuffer address
 			VIDEO_KBD_INIT_FCT	keyboard int fct
 						(i.e. i8042_kbd_init())
 			VIDEO_TSTC_FCT		test char fct
@@ -603,15 +619,15 @@ The following options need to be configured:
 		CFG_CMD_AUTOSCRIPT Autoscript Support
 		CFG_CMD_BDI	  bdinfo
 		CFG_CMD_BEDBUG	  Include BedBug Debugger
-		CFG_CMD_BMP     * BMP support
+		CFG_CMD_BMP	* BMP support
 		CFG_CMD_BOOTD	  bootd
 		CFG_CMD_CACHE	  icache, dcache
 		CFG_CMD_CONSOLE	  coninfo
 		CFG_CMD_DATE	* support for RTC, date/time...
 		CFG_CMD_DHCP	  DHCP support
-		CFG_CMD_DIAG    * Diagnostics
-		CFG_CMD_DOC     * Disk-On-Chip Support
-		CFG_CMD_DTT       Digital Therm and Thermostat
+		CFG_CMD_DIAG	* Diagnostics
+		CFG_CMD_DOC	* Disk-On-Chip Support
+		CFG_CMD_DTT	  Digital Therm and Thermostat
 		CFG_CMD_ECHO	* echo arguments
 		CFG_CMD_EEPROM	* EEPROM read/write support
 		CFG_CMD_ELF	  bootelf, bootvx
@@ -621,37 +637,37 @@ The following options need to be configured:
 		CFG_CMD_FDOS	* Dos diskette Support
 		CFG_CMD_FLASH	  flinfo, erase, protect
 		CFG_CMD_FPGA	  FPGA device initialization support
-		CFG_CMD_HWFLOW  * RTS/CTS hw flow control
+		CFG_CMD_HWFLOW	* RTS/CTS hw flow control
 		CFG_CMD_I2C	* I2C serial bus support
 		CFG_CMD_IDE	* IDE harddisk support
 		CFG_CMD_IMI	  iminfo
-		CFG_CMD_IMLS      List all found images
+		CFG_CMD_IMLS	  List all found images
 		CFG_CMD_IMMAP	* IMMR dump support
 		CFG_CMD_IRQ	* irqinfo
-		CFG_CMD_JFFS2   * JFFS2 Support
+		CFG_CMD_JFFS2	* JFFS2 Support
 		CFG_CMD_KGDB	* kgdb
 		CFG_CMD_LOADB	  loadb
 		CFG_CMD_LOADS	  loads
 		CFG_CMD_MEMORY	  md, mm, nm, mw, cp, cmp, crc, base,
 				  loop, mtest
-		CFG_CMD_MISC      Misc functions like sleep etc
+		CFG_CMD_MISC	  Misc functions like sleep etc
 		CFG_CMD_MMC	  MMC memory mapped support
 		CFG_CMD_MII	  MII utility commands
-		CFG_CMD_NAND    * NAND support
+		CFG_CMD_NAND	* NAND support
 		CFG_CMD_NET	  bootp, tftpboot, rarpboot
 		CFG_CMD_PCI	* pciinfo
 		CFG_CMD_PCMCIA	* PCMCIA support
-		CFG_CMD_PING    * send ICMP ECHO_REQUEST to network host
-		CFG_CMD_PORTIO  * Port I/O
+		CFG_CMD_PING	* send ICMP ECHO_REQUEST to network host
+		CFG_CMD_PORTIO	* Port I/O
 		CFG_CMD_REGINFO * Register dump
 		CFG_CMD_RUN	  run command in env variable
-		CFG_CMD_SAVES     save S record dump
+		CFG_CMD_SAVES	  save S record dump
 		CFG_CMD_SCSI	* SCSI Support
-		CFG_CMD_SDRAM   * print SDRAM configuration information
+		CFG_CMD_SDRAM	* print SDRAM configuration information
 		CFG_CMD_SETGETDCR Support for DCR Register access (4xx only)
 		CFG_CMD_SPI	* SPI serial bus support
 		CFG_CMD_USB	* USB support
-		CFG_CMD_VFD     * VFD support (TRAB)
+		CFG_CMD_VFD	* VFD support (TRAB)
 		CFG_CMD_BSP	* Board SPecific functions
 		-----------------------------------------------
 		CFG_CMD_ALL	all
@@ -834,9 +850,9 @@ The following options need to be configured:
 		Following modes are supported  (* is default):
 
 			    800x600  1024x768  1280x1024
-	      256  (8bit)     303*      305       307
-	    65536 (16bit)     314       317       31a
-	16,7 Mill (24bit)     315       318       31b
+	      256  (8bit)     303*	305	  307
+	    65536 (16bit)     314	317	  31a
+	16,7 Mill (24bit)     315	318	  31b
 		(i.e. setenv videomode 317; saveenv; reset;)
 
 		CONFIG_VIDEO_SED13806
@@ -1015,7 +1031,7 @@ The following options need to be configured:
 		clock chips. See common/cmd_i2c.c for a description of the
 		command line interface.
 
-		CONFIG_HARD_I2C	selects the CPM hardware driver for I2C.
+		CONFIG_HARD_I2C selects the CPM hardware driver for I2C.
 
 		CONFIG_SOFT_I2C configures u-boot to use a software (aka
 		bit-banging) driver instead of CPM or similar hardware
@@ -1045,7 +1061,7 @@ The following options need to be configured:
 		(Optional). Any commands necessary to enable the I2C
 		controller or configure ports.
 
-		eg: #define I2C_INIT (immr->im_cpm.cp_pbdir |=  PB_SCL)
+		eg: #define I2C_INIT (immr->im_cpm.cp_pbdir |=	PB_SCL)
 
 		I2C_PORT
 
@@ -1083,7 +1099,7 @@ The following options need to be configured:
 
 		eg: #define I2C_SDA(bit) \
 			if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
-			else    immr->im_cpm.cp_pbdat &= ~PB_SDA
+			else	immr->im_cpm.cp_pbdat &= ~PB_SDA
 
 		I2C_SCL(bit)
 
@@ -1092,7 +1108,7 @@ The following options need to be configured:
 
 		eg: #define I2C_SCL(bit) \
 			if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
-			else    immr->im_cpm.cp_pbdat &= ~PB_SCL
+			else	immr->im_cpm.cp_pbdat &= ~PB_SCL
 
 		I2C_DELAY
 
@@ -1189,7 +1205,7 @@ The following options need to be configured:
 		Time to wait after FPGA configuration. The default is
 		200 mS.
 
-- FPGA Support:	CONFIG_FPGA_COUNT
+- FPGA Support: CONFIG_FPGA_COUNT
 
 		Specify the number of FPGA devices to support.
 
@@ -1406,11 +1422,11 @@ The following options need to be configured:
 
   Arg	Where			When
     1	common/cmd_bootm.c	before attempting to boot an image
-   -1	common/cmd_bootm.c	Image header has bad     magic number
+   -1	common/cmd_bootm.c	Image header has bad	 magic number
     2	common/cmd_bootm.c	Image header has correct magic number
-   -2	common/cmd_bootm.c	Image header has bad     checksum
+   -2	common/cmd_bootm.c	Image header has bad	 checksum
     3	common/cmd_bootm.c	Image header has correct checksum
-   -3	common/cmd_bootm.c	Image data   has bad     checksum
+   -3	common/cmd_bootm.c	Image data   has bad	 checksum
     4	common/cmd_bootm.c	Image data   has correct checksum
    -4	common/cmd_bootm.c	Image is for unsupported architecture
     5	common/cmd_bootm.c	Architecture check OK
@@ -1423,10 +1439,10 @@ The following options need to be configured:
     8	common/cmd_bootm.c	Image Type check OK
    -9	common/cmd_bootm.c	Unsupported OS (not Linux, BSD, VxWorks, QNX)
     9	common/cmd_bootm.c	Start initial ramdisk verification
-  -10	common/cmd_bootm.c	Ramdisk header has bad     magic number
-  -11	common/cmd_bootm.c	Ramdisk header has bad     checksum
+  -10	common/cmd_bootm.c	Ramdisk header has bad	   magic number
+  -11	common/cmd_bootm.c	Ramdisk header has bad	   checksum
    10	common/cmd_bootm.c	Ramdisk header is OK
-  -12	common/cmd_bootm.c	Ramdisk data   has bad     checksum
+  -12	common/cmd_bootm.c	Ramdisk data   has bad	   checksum
    11	common/cmd_bootm.c	Ramdisk data   has correct checksum
    12	common/cmd_bootm.c	Ramdisk verification complete, start loading
   -13	common/cmd_bootm.c	Wrong Image Type (not PPC Linux Ramdisk)
@@ -1454,7 +1470,7 @@ The following options need to be configured:
    -1	common/cmd_nand.c	Read Error on boot device
    -1	common/cmd_nand.c	Image header has bad magic number
 
-   -1	common/env_common.c     Environment has a bad CRC, using default
+   -1	common/env_common.c	Environment has a bad CRC, using default
 
 
 Modem Support:
@@ -1627,7 +1643,11 @@ Configuration Settings:
 
 - CFG_FLASH_CFI:
 		Define if the flash driver uses extra elements in the
-		common flash structure for storing flash geometry
+		common flash structure for storing flash geometry.
+
+- CFG_FLASH_CFI_DRIVER
+		This option also enables the building of the cfi_flash driver
+		in the drivers directory
 
 - CFG_RX_ETH_BUFFER:
 		Defines the number of ethernet receive buffers. On some
@@ -1758,7 +1778,7 @@ to save the current settings.
 
 	- CFG_EEPROM_PAGE_WRITE_DELAY_MS:
 	  If defined, the number of milliseconds to delay between
-	  page writes.  The default is zero milliseconds.
+	  page writes.	The default is zero milliseconds.
 
 	- CFG_I2C_EEPROM_ADDR_LEN:
 	  The length in bytes of the EEPROM memory array address.  Note
@@ -1976,7 +1996,7 @@ change it to:
 	CROSS_COMPILE = ppc_4xx-
 
 
-U-Boot is intended to be  simple  to  build.  After  installing  the
+U-Boot is intended to be  simple  to  build.  After  installing	 the
 sources	 you must configure U-Boot for one specific board type. This
 is done by typing:
 
@@ -2004,7 +2024,7 @@ configurations; the following names are supported:
     at91rm9200dk_config	  omap1510inn_config	MPC8260ADS_config
     omap1610inn_config	  ZPC1900_config	MPC8540ADS_config
     MPC8560ADS_config	  QS850_config		QS823_config
-    QS860T_config         DUET_ADS_config
+    QS860T_config	  DUET_ADS_config
 
 Note: for some board special configuration names may exist; check  if
       additional  information is available from the board vendor; for
@@ -2120,15 +2140,15 @@ mw	- memory write (fill)
 cp	- memory copy
 cmp	- memory compare
 crc32	- checksum calculation
-imd     - i2c memory display
-imm     - i2c memory modify (auto-incrementing)
-inm     - i2c memory modify (constant address)
-imw     - i2c memory write (fill)
-icrc32  - i2c checksum calculation
-iprobe  - probe to discover valid I2C chip addresses
-iloop   - infinite loop on address range
-isdram  - print SDRAM configuration information
-sspi    - SPI utility commands
+imd	- i2c memory display
+imm	- i2c memory modify (auto-incrementing)
+inm	- i2c memory modify (constant address)
+imw	- i2c memory write (fill)
+icrc32	- i2c checksum calculation
+iprobe	- probe to discover valid I2C chip addresses
+iloop	- infinite loop on address range
+isdram	- print SDRAM configuration information
+sspi	- SPI utility commands
 base	- print or set address offset
 printenv- print environment variables
 setenv	- set environment variables
@@ -2457,7 +2477,7 @@ Example:
 	make uImage
 
 The "uImage" build target uses a special tool (in 'tools/mkimage') to
-encapsulate a compressed Linux kernel image with header  information,
+encapsulate a compressed Linux kernel image with header	 information,
 CRC32 checksum etc. for use with U-Boot. This is what we are doing:
 
 * build a standard "vmlinux" kernel image (in ELF binary format):
@@ -2844,9 +2864,9 @@ use "cu" for S-Record download ("loads" command).
 Nevertheless, if you absolutely want to use it try adding this
 configuration to your "File transfer protocols" section:
 
-	   Name    Program                      Name U/D FullScr IO-Red. Multi
-	X  kermit  /usr/bin/kermit -i -l %l -s   Y    U    Y       N      N
-	Y  kermit  /usr/bin/kermit -i -l %l -r   N    D    Y       N      N
+	   Name	   Program			Name U/D FullScr IO-Red. Multi
+	X  kermit  /usr/bin/kermit -i -l %l -s	 Y    U	   Y	   N	  N
+	Y  kermit  /usr/bin/kermit -i -l %l -r	 N    D	   Y	   N	  N
 
 
 NetBSD Notes:
@@ -2902,7 +2922,7 @@ models provide on-chip memory (like the IMMR area on MPC8xx and
 MPC826x processors), on others (parts of) the data cache can be
 locked as (mis-) used as memory, etc.
 
-	Chris Hallinan posted a good summary of  these  issues  to  the
+	Chris Hallinan posted a good summary of	 these	issues	to  the
 	u-boot-users mailing list:
 
 	Subject: RE: [U-Boot-Users] RE: More On Memory Bank x (nothingness)?
@@ -2971,7 +2991,7 @@ For PowerPC, the following registers have specific use:
 	R1:	stack pointer
 	R2:	TOC pointer
 	R3-R4:	parameter passing and return values
-	R5-R10:	parameter passing
+	R5-R10: parameter passing
 	R13:	small data area pointer
 	R30:	GOT pointer
 	R31:	frame pointer

board/altera/common/flash.c

@@ -71,7 +71,6 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
 	volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
 	volatile CFG_FLASH_WORD_SIZE *addr2;
 	int prot, sect;
-	int any = 0;
 	unsigned oldpri;
 	ulong start;
 
@@ -94,6 +93,12 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
 		printf ("\n");
 	}
 
+#ifdef DEBUG
+	for (sect = s_first; sect <= s_last; sect++) {
+		printf("- Erase: Sect: %i @ 0x%08x\n", sect,  info->start[sect]);
+	}
+#endif
+
 	/* NOTE: disabling interrupts on Nios can be very bad since it
 	 * also disables the LO_LIMIT exception. It's better here to
 	 * set the interrupt priority to 3 & restore it when we're done.
@@ -114,26 +119,25 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
 			*addr = 0xaa;
 			*addr = 0x55;
 			*addr2 = 0x30;
-			any = 1;
+			/* Now just wait for 0xff & provide some user
+			 * feedback while we wait. Here we have to grant
+			 * timer interrupts. Otherwise get_timer() can't
+			 * work right. */
+			ipri(oldpri);
+			start = get_timer (0);
+			while (*addr2 != 0xff) {
+				udelay (1000 * 1000);
+				putc ('.');
+				if (get_timer (start) > CFG_FLASH_ERASE_TOUT) {
+					printf ("timeout\n");
+					return 1;
+				}
+			}
+			oldpri = ipri (3); /* disallow non important irqs again */
 		}
 	}
 
-	/* Now just wait for 0xff & provide some user feedback while
-	 * we wait.
-	 */
-	if (any) {
-		addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
-		start = get_timer (0);
-		while (*addr2 != 0xff) {
-			udelay (1000 * 1000);
-			putc ('.');
-			if (get_timer (start) > CFG_FLASH_ERASE_TOUT) {
-				printf ("timeout\n");
-				return 1;
-			}
-		}
-		printf ("\n");
-	}
+	printf ("\n");
 
 	/* Restore interrupt priority */
 	ipri (oldpri);

board/altera/common/sevenseg.c

@@ -44,7 +44,7 @@ static int sevenseg_init_done = 0;
 
 static inline void __sevenseg_set_masked (unsigned int mask, int value)
 {
-	nios_pio_t *piop = (nios_pio_t*)SEVENSEG_BASE;
+	nios_pio_t *piop __attribute__((unused)) = (nios_pio_t*)SEVENSEG_BASE;
 
 #ifdef	SEVENSEG_WRONLY	/* emulate read access */
 
@@ -97,7 +97,7 @@ static inline void __sevenseg_toggle_masked (unsigned int mask)
 
 static inline void __sevenseg_set (unsigned int value)
 {
-	nios_pio_t *piop = (nios_pio_t*)SEVENSEG_BASE;
+	nios_pio_t *piop __attribute__((unused)) = (nios_pio_t*)SEVENSEG_BASE;
 
 #ifdef	SEVENSEG_WRONLY	/* emulate read access */
 
@@ -126,7 +126,7 @@ static inline void __sevenseg_set (unsigned int value)
 
 static inline void __sevenseg_init (void)
 {
-	nios_pio_t *piop = (nios_pio_t*)SEVENSEG_BASE;
+	nios_pio_t *piop __attribute__((unused)) = (nios_pio_t*)SEVENSEG_BASE;
 
 	__sevenseg_set(0);
 

board/altera/dk1c20/dk1c20.c

@@ -33,8 +33,10 @@ void _default_hdlr (void)
 
 int board_early_init_f (void)
 {
+#if	defined(CONFIG_SEVENSEG)
 	/* init seven segment led display and switch off */
 	sevenseg_set(SEVENSEG_OFF);
+#endif
 	return 0;
 }
 

board/altera/dk1s10/dk1s10.c

@@ -33,14 +33,24 @@ void _default_hdlr (void)
 
 int board_early_init_f (void)
 {
+#if	defined(CONFIG_SEVENSEG)
 	/* init seven segment led display and switch off */
 	sevenseg_set(SEVENSEG_OFF);
+#endif
 	return 0;
 }
 
 int checkboard (void)
 {
 	puts ("Board: Altera Nios 1S10 Development Kit\n");
+#if     defined(CONFIG_NIOS_SAFE_32)
+	puts ("Conf.: Altera Safe 32 (safe_32)\n");
+#elif   defined(CONFIG_NIOS_STANDARD_32)
+	puts ("Conf.: Altera Standard 32 (standard_32)\n");
+#elif   defined(CONFIG_NIOS_MTX_LDK_20)
+	puts ("Conf.: Microtronix LDK 2.0 (LDK2)\n");
+#endif
+
 	return 0;
 }
 

board/altera/dk1s10/vectors.S

@@ -1,6 +1,7 @@
 /*
  * (C) Copyright 2003, Psyent Corporation <www.psyent.com>
  * Scott McNutt <smcnutt@psyent.com>
+ * Stephan Linz <linz@li-pro.net>
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -21,6 +22,8 @@
  * MA 02111-1307 USA
  */
 
+#include <config.h>
+
 
 /*************************************************************************
  * Exception Vector Table
@@ -55,8 +58,14 @@
 	.align	4
 _vectors:
 
-	.long	_def_xhandler@h		/* Vector 0  - NMI */
-	.long	_cwp_lolimit@h		/* Vector 1  -  underflow */
+#if	defined(CFG_NIOS_CPU_OCI_BASE)
+	/* OCI does the reset job */
+	.long	_def_xhandler@h		/* Vector 0  - NMI / Reset */
+#else
+	/* there is no OCI, so we have to do a direct reset jump here */
+	.long	CFG_NIOS_CPU_RST_VECT	/* Vector 0  - Reset to GERMS */
+#endif
+	.long	_cwp_lolimit@h		/* Vector 1  - underflow */
 	.long	_cwp_hilimit@h		/* Vector 2  - overflow	*/
 
 	.long	_def_xhandler@h		/* Vector 3 - GNUPro debug */
@@ -72,7 +81,11 @@ _vectors:
 	.long	_def_xhandler@h		/* Vector 13 - future reserved */
 	.long	_def_xhandler@h		/* Vector 14 - future reserved */
 	.long	_def_xhandler@h		/* Vector 15 - future reserved */
+#if	(CFG_NIOS_TMRIRQ == 16)
+	.long	_timebase_int@h		/* Vector 16 - lopri timer*/
+#else
 	.long	_def_xhandler@h		/* Vector 16 */
+#endif
 	.long	_def_xhandler@h		/* Vector 17 */
 	.long	_def_xhandler@h		/* Vector 18 */
 	.long	_def_xhandler@h		/* Vector 19 */
@@ -106,7 +119,11 @@ _vectors:
 	.long	_def_xhandler@h		/* Vector 47 */
 	.long	_def_xhandler@h		/* Vector 48 */
 	.long	_def_xhandler@h		/* Vector 49 */
+#if	(CFG_NIOS_TMRIRQ == 50)
 	.long	_timebase_int@h		/* Vector 50 - lopri timer*/
+#else
+	.long	_def_xhandler@h		/* Vector 50 */
+#endif
 	.long	_def_xhandler@h		/* Vector 51 */
 	.long	_def_xhandler@h		/* Vector 52 */
 	.long	_def_xhandler@h		/* Vector 53 */

board/at91rm9200dk/u-boot.lds

@@ -45,14 +45,12 @@ SECTIONS
 	. = ALIGN(4);
 	.got : { *(.got) }
 
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
-
-	armboot_end_data = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
 
 	. = ALIGN(4);
+	__bss_start = .;
 	.bss : { *(.bss) }
-
-	armboot_end = .;
+	_end = .;
 }

board/cradle/u-boot.lds

@@ -44,17 +44,12 @@ SECTIONS
 	. = ALIGN(4);
 	.got : { *(.got) }
 
-   __u_boot_cmd_start = .;
-   .u_boot_cmd : { *(.u_boot_cmd) }
-   __u_boot_cmd_end = .;
-
-	armboot_end_data = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
 
 	. = ALIGN(4);
-	bss_start = .;
+	__bss_start = .;
 	.bss : { *(.bss) }
-	bss_end = .;
-
-	armboot_end = .;
-
+	_end = .;
 }

board/csb226/flash.c

@@ -9,6 +9,9 @@
  * (C) Copyright 2002
  * Robert Schwebel, Pengutronix, <r.schwebel@pengutronix.de>
  *
+ * (C) Copyright 2003 (2 x 16 bit Flash bank patches)
+ * Rolf Peukert, IMMS gGmbH, <rolf.peukert@imms.de>
+ *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
@@ -19,7 +22,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -32,9 +35,9 @@
 #include <asm/arch/pxa-regs.h>
 
 #define FLASH_BANK_SIZE 0x02000000
-#define MAIN_SECT_SIZE  0x40000         /* 2x16 = 256k per sector */
+#define MAIN_SECT_SIZE	0x40000		/* 2x16 = 256k per sector */
 
-flash_info_t    flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS];
 
 
 /**
@@ -51,19 +54,19 @@ ulong flash_init(void)
 	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
 		ulong flashbase = 0;
 		flash_info[i].flash_id =
-	  		(INTEL_MANUFACT & FLASH_VENDMASK) |
-	  		(INTEL_ID_28F128J3 & FLASH_TYPEMASK);
+			(INTEL_MANUFACT & FLASH_VENDMASK) |
+			(INTEL_ID_28F128J3 & FLASH_TYPEMASK);
 		flash_info[i].size = FLASH_BANK_SIZE;
 		flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
 		memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
 
 		switch (i) {
-			case 0:
-				flashbase = PHYS_FLASH_1;
-				break;
-			default:
-				panic("configured too many flash banks!\n");
-				break;
+		case 0:
+			flashbase = PHYS_FLASH_1;
+			break;
+		default:
+			panic("configured too many flash banks!\n");
+			break;
 		}
 		for (j = 0; j < flash_info[i].sector_count; j++) {
 			flash_info[i].start[j] = flashbase + j*MAIN_SECT_SIZE;
@@ -88,8 +91,6 @@ ulong flash_init(void)
 
 /**
  * flash_print_info: - print information about the flash situation
- *
- * @param info:
  */
 
 void flash_print_info  (flash_info_t *info)
@@ -99,23 +100,21 @@ void flash_print_info  (flash_info_t *info)
 	for (j=0; j<CFG_MAX_FLASH_BANKS; j++) {
 
 		switch (info->flash_id & FLASH_VENDMASK) {
-
-			case (INTEL_MANUFACT & FLASH_VENDMASK):
-				printf("Intel: ");
-				break;
-			default:
-				printf("Unknown Vendor ");
-				break;
+		case (INTEL_MANUFACT & FLASH_VENDMASK):
+			printf ("Intel: ");
+			break;
+		default:
+			printf ("Unknown Vendor ");
+			break;
 		}
 
 		switch (info->flash_id & FLASH_TYPEMASK) {
-
-			case (INTEL_ID_28F128J3 & FLASH_TYPEMASK):
-				printf("28F128J3 (128Mbit)\n");
-				break;
-			default:
-				printf("Unknown Chip Type\n");
-				return;
+		case (INTEL_ID_28F128J3 & FLASH_TYPEMASK):
+			printf("28F128J3 (128Mbit)\n");
+			break;
+		default:
+			printf("Unknown Chip Type\n");
+			return;
 		}
 
 		printf("  Size: %ld MB in %d Sectors\n",
@@ -123,10 +122,10 @@ void flash_print_info  (flash_info_t *info)
 
 		printf("  Sector Start Addresses:");
 		for (i = 0; i < info->sector_count; i++) {
-			if ((i % 5) == 0) printf ("\n   ");
+			if ((i % 5) == 0) printf ("\n	");
 
 			printf (" %08lX%s", info->start[i],
-				info->protect[i] ? " (RO)" : "     ");
+				info->protect[i] ? " (RO)" : "	   ");
 		}
 		printf ("\n");
 		info++;
@@ -136,7 +135,6 @@ void flash_print_info  (flash_info_t *info)
 
 /**
  * flash_erase: - erase flash sectors
- *
  */
 
 int flash_erase(flash_info_t *info, int s_first, int s_last)
@@ -179,13 +177,13 @@ int flash_erase(flash_info_t *info, int s_first, int s_last)
 		/* arm simple, non interrupt dependent timer */
 		reset_timer_masked();
 
-		if (info->protect[sect] == 0) {	/* not protected */
+		if (info->protect[sect] == 0) { /* not protected */
 			u32 * volatile addr = (u32 * volatile)(info->start[sect]);
 
-			/* erase sector:                                    */
+			/* erase sector:				    */
 			/* The strata flashs are aligned side by side on    */
 			/* the data bus, so we have to write the commands   */
-			/* to both chips here:                              */
+			/* to both chips here:				    */
 
 			*addr = 0x00200020;	/* erase setup */
 			*addr = 0x00D000D0;	/* erase confirm */
@@ -198,19 +196,14 @@ int flash_erase(flash_info_t *info, int s_first, int s_last)
 					goto outahere;
 				}
 			}
-
 			*addr = 0x00500050; /* clear status register cmd.   */
-			*addr = 0x00FF00FF; /* resest to read mode          */
-
+			*addr = 0x00FF00FF; /* reset to read mode	    */
 		}
-
 		printf("ok.\n");
 	}
-
 	if (ctrlc()) printf("User Interrupt!\n");
 
-	outahere:
-
+outahere:
 	/* allow flash to settle - wait 10 ms */
 	udelay_masked(10000);
 
@@ -219,22 +212,19 @@ int flash_erase(flash_info_t *info, int s_first, int s_last)
 	return rc;
 }
 
-
 /**
- * write_word: - copy memory to flash
- *
- * @param info:
- * @param dest:
- * @param data:
- * @return:
+ * write_long: - copy memory to flash, assume a bank of 2 devices with 16bit each
  */
 
-static int write_word (flash_info_t *info, ulong dest, ushort data)
+static int write_long (flash_info_t *info, ulong dest, ulong data)
 {
 	u32 * volatile addr = (u32 * volatile)dest, val;
 	int rc = ERR_OK;
 	int flag;
 
+	/* read array command - just for the case... */
+	*addr = 0x00FF00FF;
+
 	/* Check if Flash is (sufficiently) erased */
 	if ((*addr & data) != data) return ERR_NOT_ERASED;
 
@@ -248,10 +238,10 @@ static int write_word (flash_info_t *info, ulong dest, ushort data)
 	flag = disable_interrupts();
 
 	/* clear status register command */
-	*addr = 0x50;
+	*addr = 0x00500050;
 
 	/* program set-up command */
-	*addr = 0x40;
+	*addr = 0x00400040;
 
 	/* latch address/data */
 	*addr = data;
@@ -260,28 +250,30 @@ static int write_word (flash_info_t *info, ulong dest, ushort data)
 	reset_timer_masked();
 
 	/* wait while polling the status register */
-	while(((val = *addr) & 0x80) != 0x80) {
+	while(((val = *addr) & 0x00800080) != 0x00800080) {
 		if (get_timer_masked() > CFG_FLASH_WRITE_TOUT) {
 			rc = ERR_TIMOUT;
-			*addr = 0xB0; /* suspend program command */
+			/* suspend program command */
+			*addr = 0x00B000B0;
 			goto outahere;
 		}
 	}
 
-	if(val & 0x1A) {	/* check for error */
+	/* check for errors */
+	if(val & 0x001A001A) {
 		printf("\nFlash write error %02x at address %08lx\n",
 			(int)val, (unsigned long)dest);
-		if(val & (1<<3)) {
+		if(val & 0x00080008) {
 			printf("Voltage range error.\n");
 			rc = ERR_PROG_ERROR;
 			goto outahere;
 		}
-		if(val & (1<<1)) {
+		if(val & 0x00020002) {
 			printf("Device protect error.\n");
 			rc = ERR_PROTECTED;
 			goto outahere;
 		}
-		if(val & (1<<4)) {
+		if(val & 0x00100010) {
 			printf("Programming error.\n");
 			rc = ERR_PROG_ERROR;
 			goto outahere;
@@ -290,9 +282,9 @@ static int write_word (flash_info_t *info, ulong dest, ushort data)
 		goto outahere;
 	}
 
-	outahere:
-
-	*addr = 0xFF; /* read array command */
+outahere:
+	/* read array command */
+	*addr = 0x00FF00FF;
 	if (flag) enable_interrupts();
 
 	return rc;
@@ -304,20 +296,21 @@ static int write_word (flash_info_t *info, ulong dest, ushort data)
  *
  * @param info:
  * @param src:	source of copy transaction
- * @param addr:	where to copy to
- * @param cnt: 	number of bytes to copy
+ * @param addr: where to copy to
+ * @param cnt:	number of bytes to copy
  *
  * @return	error code
  */
 
+/* "long" version, uses 32bit words */
 int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
 {
 	ulong cp, wp;
-	ushort data;
+	ulong data;
 	int l;
 	int i, rc;
 
-	wp = (addr & ~1);	/* get lower word aligned address */
+	wp = (addr & ~3);	/* get lower word aligned address */
 
 	/*
 	 * handle unaligned start bytes
@@ -325,35 +318,34 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
 	if ((l = addr - wp) != 0) {
 		data = 0;
 		for (i=0, cp=wp; i<l; ++i, ++cp) {
-			data = (data >> 8) | (*(uchar *)cp << 8);
+			data = (data >> 8) | (*(uchar *)cp << 24);
 		}
-		for (; i<2 && cnt>0; ++i) {
-			data = (data >> 8) | (*src++ << 8);
+		for (; i<4 && cnt>0; ++i) {
+			data = (data >> 8) | (*src++ << 24);
 			--cnt;
 			++cp;
 		}
-		for (; cnt==0 && i<2; ++i, ++cp) {
-			data = (data >> 8) | (*(uchar *)cp << 8);
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *)cp << 24);
 		}
 
-		if ((rc = write_word(info, wp, data)) != 0) {
+		if ((rc = write_long(info, wp, data)) != 0) {
 			return (rc);
 		}
-		wp += 2;
+		wp += 4;
 	}
 
 	/*
 	 * handle word aligned part
 	 */
-	while (cnt >= 2) {
-		/* data = *((vushort*)src); */
-		data = *((ushort*)src);
-		if ((rc = write_word(info, wp, data)) != 0) {
+	while (cnt >= 4) {
+		data = *((ulong*)src);
+		if ((rc = write_long(info, wp, data)) != 0) {
 			return (rc);
 		}
-		src += 2;
-		wp  += 2;
-		cnt -= 2;
+		src += 4;
+		wp  += 4;
+		cnt -= 4;
 	}
 
 	if (cnt == 0) return ERR_OK;
@@ -362,13 +354,13 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
 	 * handle unaligned tail bytes
 	 */
 	data = 0;
-	for (i=0, cp=wp; i<2 && cnt>0; ++i, ++cp) {
-		data = (data >> 8) | (*src++ << 8);
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data >> 8) | (*src++ << 24);
 		--cnt;
 	}
-	for (; i<2; ++i, ++cp) {
-		data = (data >> 8) | (*(uchar *)cp << 8);
+	for (; i<4; ++i, ++cp) {
+		data = (data >> 8) | (*(uchar *)cp << 24);
 	}
 
-	return write_word(info, wp, data);
+	return write_long(info, wp, data);
 }

board/csb226/u-boot.lds

@@ -44,16 +44,12 @@ SECTIONS
 	. = ALIGN(4);
 	.got : { *(.got) }
 
-   __u_boot_cmd_start = .;
-   .u_boot_cmd : { *(.u_boot_cmd) }
-   __u_boot_cmd_end = .;
-
-	armboot_end_data = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
 
 	. = ALIGN(4);
-	bss_start = .;
+	__bss_start = .;
 	.bss : { *(.bss) }
-	bss_end = .;
-
-	armboot_end = .;
+	_end = .;
 }

board/dnp1110/u-boot.lds

@@ -44,16 +44,12 @@ SECTIONS
 	. = ALIGN(4);
 	.got : { *(.got) }
 
-
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
-
-
-	armboot_end_data = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
 
 	. = ALIGN(4);
+	__bss_start = .;
 	.bss : { *(.bss) }
-
-	armboot_end = .;
+	_end = .;
 }

board/ep7312/u-boot.lds

@@ -44,14 +44,12 @@ SECTIONS
 	. = ALIGN(4);
 	.got : { *(.got) }
 
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
-
-	armboot_end_data = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
 
 	. = ALIGN(4);
+	__bss_start = .;
 	.bss : { *(.bss) }
-
-	armboot_end = .;
+	_end = .;
 }

board/esteem192e/esteem192e.c

@@ -113,7 +113,7 @@ long int initdram (int board_type)
 
 	memctl->memc_mptpr = 0x0200;	/* divide by 32 */
 
-	memctl->memc_mamr = 0x18003112;	/*CFG_MAMR_8COL; *//* 0x18005112 TODO: explain here */
+	memctl->memc_mamr = 0x18003112;	/*CFG_MAMR_8COL; */ /* 0x18005112 TODO: explain here */
 
 	upmconfig (UPMA, (uint *) sdram_table,
 		   sizeof (sdram_table) / sizeof (uint));

board/impa7/u-boot.lds

@@ -44,15 +44,12 @@ SECTIONS
 	. = ALIGN(4);
 	.got : { *(.got) }
 
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
-
-	armboot_end_data = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
 
 	. = ALIGN(4);
+	__bss_start = .;
 	.bss : { *(.bss) }
-
-	armboot_end = .;
-
+	_end = .;
 }

board/innokom/u-boot.lds

@@ -44,16 +44,12 @@ SECTIONS
 	. = ALIGN(4);
 	.got : { *(.got) }
 
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
-
-	armboot_end_data = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
 
 	. = ALIGN(4);
-	bss_start = .;
+	__bss_start = .;
 	.bss : { *(.bss) }
-	bss_end = .;
-
-	armboot_end = .;
+	_end = .;
 }

board/ixdp425/config.mk

@@ -1,2 +1,2 @@
 #TEXT_BASE = 0x00100000
-TEXT_BASE = 0x00f00000
+TEXT_BASE = 0x00f80000

board/ixdp425/flash.c

@@ -72,7 +72,7 @@ unsigned long flash_init (void)
 			flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
 			break;
 		default:
-			panic ("configured to many flash banks!\n");
+			panic ("configured too many flash banks!\n");
 			break;
 		}
 		size += flash_info[i].size;
@@ -82,7 +82,7 @@ unsigned long flash_init (void)
 	 */
 	flash_protect (FLAG_PROTECT_SET,
 		       CFG_FLASH_BASE,
-		       CFG_FLASH_BASE + _armboot_end_data - _armboot_start,
+		       CFG_FLASH_BASE + _bss_start - _armboot_start,
 		       &flash_info[0]);
 
 	flash_protect (FLAG_PROTECT_SET,

board/ixdp425/u-boot.lds

@@ -48,12 +48,8 @@ SECTIONS
 	.u_boot_cmd : { *(.u_boot_cmd) }
 	__u_boot_cmd_end = .;
 
-	armboot_end_data = .;
-
 	. = ALIGN(4);
-	bss_start = .;
+	__bss_start = .;
 	.bss : { *(.bss) }
-	bss_end = .;
-
-	armboot_end = .;
+	_end = .;
 }

board/lart/u-boot.lds

@@ -44,14 +44,12 @@ SECTIONS
 	. = ALIGN(4);
 	.got : { *(.got) }
 
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
-
-	armboot_end_data = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
 
 	. = ALIGN(4);
+	__bss_start = .;
 	.bss : { *(.bss) }
-
-	armboot_end = .;
+	_end = .;
 }

board/logodl/flash.c

@@ -105,7 +105,7 @@ ulong flash_init(void)
      */
     flash_protect(FLAG_PROTECT_SET,
 		  CFG_FLASH_BASE,
-		  CFG_FLASH_BASE + _armboot_end_data - _armboot_start,
+		  CFG_FLASH_BASE + _bss_start - _armboot_start,
 		  &flash_info[0]);
 
     flash_protect(FLAG_PROTECT_SET,

board/logodl/u-boot.lds

@@ -44,12 +44,12 @@ SECTIONS
 	. = ALIGN(4);
 	.got : { *(.got) }
 
-	armboot_end_data = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
 
 	. = ALIGN(4);
-	bss_start = .;
+	__bss_start = .;
 	.bss : { *(.bss) }
-	bss_end = .;
-
-	armboot_end = .;
+	_end = .;
 }

board/lubbock/config.mk

@@ -1,3 +1,3 @@
 #TEXT_BASE = 0xa1700000
-TEXT_BASE = 0xa3000000
+TEXT_BASE = 0xa3080000
 #TEXT_BASE = 0

board/lubbock/u-boot.lds

@@ -44,16 +44,12 @@ SECTIONS
 	. = ALIGN(4);
 	.got : { *(.got) }
 
-   __u_boot_cmd_start = .;
-   .u_boot_cmd : { *(.u_boot_cmd) }
-   __u_boot_cmd_end = .;
-
-	armboot_end_data = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
 
 	. = ALIGN(4);
-	bss_start = .;
+	__bss_start = .;
 	.bss : { *(.bss) }
-	bss_end = .;
-
-	armboot_end = .;
+	_end = .;
 }

board/mpl/vcma9/config.mk

@@ -14,11 +14,11 @@
 # Linux-Kernel is expected to be at 3000'8000, entry 3000'8000
 # optionally with a ramdisk at 3040'0000
 #
-# we load ourself to 30F8'0000
+# we load ourself to 33F8'0000
 #
 # download area is 3080'0000
 #
 
 
 #TEXT_BASE = 0x30F80000
-TEXT_BASE = 0x33F00000
+TEXT_BASE = 0x33F80000

board/mpl/vcma9/u-boot.lds

@@ -45,14 +45,12 @@ SECTIONS
 	. = ALIGN(4);
 	.got : { *(.got) }
 
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
-
-	armboot_end_data = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
 
 	. = ALIGN(4);
+	__bss_start = .;
 	.bss : { *(.bss) }
-
-	armboot_end = .;
+	_end = .;
 }

board/omap1510inn/config.mk

@@ -17,9 +17,9 @@
 #
 # Linux-Kernel is expected to be at 1000'8000, entry 1000'8000  (mem base + reserved)
 #
-# we load ourself to 1100'0000
+# we load ourself to 1108'0000
 #
 #
 
 
-TEXT_BASE = 0x11000000
+TEXT_BASE = 0x11080000

board/omap1510inn/u-boot.lds

@@ -45,14 +45,12 @@ SECTIONS
 	. = ALIGN(4);
 	.got : { *(.got) }
 
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
-
-	armboot_end_data = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
 
 	. = ALIGN(4);
+	__bss_start = .;
 	.bss : { *(.bss) }
-
-	armboot_end = .;
+	_end = .;
 }

board/omap1610inn/config.mk

@@ -18,9 +18,9 @@
 # Linux-Kernel is expected to be at 1000'8000, entry 1000'8000
 # (mem base + reserved)
 #
-# we load ourself to 1100'0000
+# we load ourself to 1108'0000
 #
 #
 
 
-TEXT_BASE = 0x11000000
+TEXT_BASE = 0x11080000

board/omap1610inn/flash.c

@@ -19,7 +19,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -32,7 +32,7 @@
 #include <linux/byteorder/swab.h>
 
 #define PHYS_FLASH_SECT_SIZE	0x00020000	/* 256 KB sectors (x2) */
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips	   */
 
 /* Board support for 1 or 2 flash devices */
 #undef FLASH_PORT_WIDTH32
@@ -93,6 +93,8 @@ unsigned long flash_init (void)
 		case 0:
 			flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
 			flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
+			/* to reset the lock bit */
+			flash_unlock(&flash_info[i]);
 			break;
 		default:
 			panic ("configured too many flash banks!\n");
@@ -114,6 +116,19 @@ unsigned long flash_init (void)
 	return size;
 }
 
+/*-----------------------------------------------------------------------
+ */
+flash_unlock(flash_info_t * info)
+{
+	int j;
+	for (j=2;j<CFG_MAX_FLASH_SECT;j++){
+	FPWV *addr = (FPWV *) (info->start[j]);
+	flash_unprotect_sectors (addr);
+	*addr = (FPW) 0x00500050;/* clear status register */
+	*addr = (FPW) 0x00FF00FF;/* resest to read mode */
+	}
+}
+
 /*-----------------------------------------------------------------------
  */
 static void flash_get_offsets (ulong base, flash_info_t * info)
@@ -177,7 +192,7 @@ void flash_print_info (flash_info_t * info)
 		if ((i % 5) == 0)
 			printf ("\n   ");
 		printf (" %08lX%s",
-			info->start[i], info->protect[i] ? " (RO)" : "     ");
+			info->start[i], info->protect[i] ? " (RO)" : "	   ");
 	}
 	printf ("\n");
 	return;
@@ -209,18 +224,18 @@ static ulong flash_get_size (FPW * addr, flash_info_t * info)
 		info->sector_count = 0;
 		info->size = 0;
 		addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
-		return (0);		/* no or unknown flash  */
+		return (0);		/* no or unknown flash	*/
 	}
 
 	mb ();
-	value = addr[1];	/* device ID        */
+	value = addr[1];	/* device ID	    */
 	switch (value) {
 
 	case (FPW) (INTEL_ID_28F256L18T):
 		info->flash_id += FLASH_28F256L18T;
 		info->sector_count = 259;
 		info->size = 0x02000000;
-		break;			/* => 32 MB     */
+		break;			/* => 32 MB	*/
 
 	default:
 		info->flash_id = FLASH_UNKNOWN;
@@ -303,7 +318,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
 
 	/* Start erase on unprotected sectors */
 	for (sect = s_first; sect <= s_last; sect++) {
-		if (info->protect[sect] == 0) {	/* not protected */
+		if (info->protect[sect] == 0) { /* not protected */
 			FPWV *addr = (FPWV *) (info->start[sect]);
 			FPW status;
 
@@ -333,7 +348,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
 				}
 			}
 
-			/* clear status register cmd.   */
+			/* clear status register cmd.	*/
 			*addr = (FPW) 0x00500050;
 			*addr = (FPW) 0x00FF00FF;/* resest to read mode */
 			printf (" done\n");
@@ -447,7 +462,6 @@ static int write_data (flash_info_t * info, ulong dest, FPW data)
 		printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr);
 		return (2);
 	}
-	flash_unprotect_sectors (addr);
 	/* Disable interrupts which might cause a timeout here */
 	flag = disable_interrupts ();
 	*addr = (FPW) 0x00400040;	/* write setup */

board/omap1610inn/u-boot.lds

@@ -44,8 +44,8 @@ SECTIONS
 	.u_boot_cmd : { *(.u_boot_cmd) }
 	__u_boot_cmd_end = .;
 
-	armboot_end_data = .;
 	. = ALIGN(4);
+	__bss_start = .;
 	.bss : { *(.bss) }
-	armboot_end = .;
+	_end = .;
 }

board/shannon/u-boot.lds

@@ -44,15 +44,12 @@ SECTIONS
 	. = ALIGN(4);
 	.got : { *(.got) }
 
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
-
-	armboot_end_data = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
 
 	. = ALIGN(4);
+	__bss_start = .;
 	.bss : { *(.bss) }
-
-	armboot_end = .;
-
+	_end = .;
 }

board/smdk2400/config.mk

@@ -15,11 +15,11 @@
 # Linux-Kernel is expected to be at 0cf0'0000, entry 0cf0'0000
 # optionally with a ramdisk at 0c80'0000
 #
-# we load ourself to 0CF00000 (must be high enough not to be
+# we load ourself to 0CF80000 (must be high enough not to be
 # overwritten by the uncompessing Linux kernel)
 #
 # download area is 0C80'0000
 #
 
 
-TEXT_BASE = 0x0CF00000
+TEXT_BASE = 0x0CF80000

board/smdk2400/u-boot.lds

@@ -45,15 +45,12 @@ SECTIONS
 	. = ALIGN(4);
 	.got : { *(.got) }
 
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
-
-	armboot_end_data = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
 
 	. = ALIGN(4);
+	__bss_start = .;
 	.bss : { *(.bss) }
-
-	armboot_end = .;
-
+	_end = .;
 }

board/smdk2410/u-boot.lds

@@ -45,16 +45,12 @@ SECTIONS
 	. = ALIGN(4);
 	.got : { *(.got) }
 
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
-
-
-	armboot_end_data = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
 
 	. = ALIGN(4);
+	__bss_start = .;
 	.bss : { *(.bss) }
-
-	armboot_end = .;
-
+	_end = .;
 }

board/tb0229/Makefile

@@ -0,0 +1,43 @@
+#
+# (C) Masami Komiya <mkomiya@sonare.it> 2004
+#
+# (C) Copyright 2003-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o vr4131-pci.o
+SOBJS	= memsetup.o
+
+$(LIB):	.depend $(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################

board/tb0229/config.mk

@@ -0,0 +1,30 @@
+#
+# (C) Masami Komiya <mkomiya@sonare.it> 2004
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# ROM version
+TEXT_BASE = 0xBFC00000
+
+# RAM version
+#TEXT_BASE = 0x80400000

board/tb0229/memsetup.S

@@ -0,0 +1,71 @@
+/*
+ *  Memory sub-system initialization code for TANBAC Evaluation board TB0229.
+ *
+ *  Copyright (c) 2003  Masami Komiya <mkomiya@sonare.it>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2, or (at
+ * your option) any later version.
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/regdef.h>
+
+
+	.globl  memsetup
+memsetup:
+
+	/* BCUCNTREG1 = 0x0040 */
+	la	t0, 0xaf000000
+	li	t1, 0x0040
+	sh	t1, 0(t0)
+
+	/* ROMSIZEREG = 0x3333 */
+	la	t0, 0xaf000004
+	li	t1, 0x3333
+	sh	t1, 0(t0)
+
+	/* ROMSPEEDREG = 0x3003 */
+	la	t0, 0xaf000006
+	li	t1, 0x3003
+	sh	t1, 0(t0)
+
+	/* BCUCNTREG3 = 0 */
+	la	t0, 0xaf000016
+	li	t1, 0x0000
+	sh	t1, 0(t0)
+
+	/* CMUCLKMSK */
+	la	t0, 0xaf000060
+	li	t1, 0x39a2
+	sh	t1, 0(t0)
+
+	/* PMUCNTREG */
+	la	t0, 0xaf0000c2
+	li	t1, 0x0006
+	sh	t1, 0(t0)
+
+	/* SDRAMMODEREG = 0x8029 */
+	la	t0, 0xaf000400
+	li	t1, 0x8029
+	sh	t1, 0(t0)
+
+	/* SDRAMCNTREG = 0x2322 */
+	la	t0, 0xaf000402
+	li	t1, 0x2322
+	sh	t1, 0(t0)
+
+	/* BCURFCNTREG = 0x0106 */
+	la	t0, 0xaf000404
+	li	t1, 0x0106
+	sh	t1, 0(t0)
+
+	/* RAMSZEREG = 0x5555 (64MB Bank) */
+	la	t0, 0xaf000408
+	li	t1, 0x5555
+	sh	t1, 0(t0)
+
+	j       ra
+	nop

board/tb0229/tb0229.c

@@ -0,0 +1,42 @@
+/*
+ * Board initialize code for TANBAC Evaluation board TB0229.
+ *
+ * (C) Masami Komiya <mkomiya@sonare.it> 2004
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2, or (at
+ * your option) any later version.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/addrspace.h>
+#include <asm/inca-ip.h>
+#include <pci.h>
+
+unsigned long mips_io_port_base = 0;
+
+#if defined(CONFIG_PCI)
+static struct pci_controller hose;
+
+void pci_init_board (void)
+{
+	init_vr4131_pci(&hose);
+}
+#endif
+
+
+long int initdram(int board_type)
+{
+	return get_ram_size (CFG_SDRAM_BASE, 0x8000000);
+}
+
+
+int checkboard (void)
+{
+	printf("Board: TANBAC TB0229 ");
+	printf("(CPU Speed %d MHz)\n", (int)CPU_CLOCK_RATE/1000000);
+
+	return 0;
+}

board/tb0229/u-boot.lds

@@ -0,0 +1,68 @@
+/*
+ * (C) Masami Komiya <mkomiya@sonare.it> 2004
+ *
+ * (C) Copyright 2003
+ * Wolfgang Denk Engineering, <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips")
+
+OUTPUT_ARCH(mips)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text       :
+	{
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata  : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data  : { *(.data) }
+
+	. = ALIGN(4);
+	.sdata  : { *(.sdata) }
+
+	_gp = ALIGN(16);
+
+	__got_start = .;
+	.got  : { *(.got) }
+	__got_end = .;
+
+	.sdata  : { *(.sdata) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	uboot_end_data = .;
+	num_got_entries = (__got_end - __got_start) >> 2;
+
+	. = ALIGN(4);
+	.sbss  : { *(.sbss) }
+	.bss  : { *(.bss) }
+	uboot_end = .;
+}

board/tb0229/vr4131-pci.c

@@ -0,0 +1,254 @@
+/*
+ * VR4131 PCIU support code for TANBAC Evaluation board TB0229.
+ *
+ * (C) Masami Komiya <mkomiya@sonare.it> 2004
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2, or (at
+ * your option) any later version.
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/addrspace.h>
+
+#define VR4131_PCIMMAW1REG	(volatile unsigned int*)(KSEG1 + 0x0f000c00)
+#define VR4131_PCIMMAW2REG	(volatile unsigned int*)(KSEG1 + 0x0f000c04)
+#define VR4131_PCITAW1REG	(volatile unsigned int*)(KSEG1 + 0x0f000c08)
+#define VR4131_PCITAW2REG	(volatile unsigned int*)(KSEG1 + 0x0f000c0c)
+#define VR4131_PCIMIOAWREG	(volatile unsigned int*)(KSEG1 + 0x0f000c10)
+#define VR4131_PCICONFDREG	(volatile unsigned int*)(KSEG1 + 0x0f000c14)
+#define VR4131_PCICONFAREG	(volatile unsigned int*)(KSEG1 + 0x0f000c18)
+#define VR4131_PCIMAILREG	(volatile unsigned int*)(KSEG1 + 0x0f000c1c)
+#define VR4131_BUSERRADREG	(volatile unsigned int*)(KSEG1 + 0x0f000c24)
+#define VR4131_INTCNTSTAREG	(volatile unsigned int*)(KSEG1 + 0x0f000c28)
+#define VR4131_PCIEXACCREG	(volatile unsigned int*)(KSEG1 + 0x0f000c2c)
+#define VR4131_PCIRECONTREG	(volatile unsigned int*)(KSEG1 + 0x0f000c30)
+#define VR4131_PCIENREG		(volatile unsigned int*)(KSEG1 + 0x0f000c34)
+#define VR4131_PCICLKSELREG	(volatile unsigned int*)(KSEG1 + 0x0f000c38)
+#define VR4131_PCITRDYREG	(volatile unsigned int*)(KSEG1 + 0x0f000c3c)
+#define VR4131_PCICLKRUNREG	(volatile unsigned int*)(KSEG1 + 0x0f000c60)
+#define VR4131_PCIHOSTCONFIG	(volatile unsigned int*)(KSEG1 + 0x0f000d00)
+#define VR4131_VENDORIDREG	(volatile unsigned int*)(KSEG1 + 0x0f000d00)
+#define VR4131_DEVICEIDREG	(volatile unsigned int*)(KSEG1 + 0x0f000d00)
+#define VR4131_COMMANDREG	(volatile unsigned int*)(KSEG1 + 0x0f000d04)
+#define VR4131_STATUSREG	(volatile unsigned int*)(KSEG1 + 0x0f000d04)
+#define VR4131_REVREG		(volatile unsigned int*)(KSEG1 + 0x0f000d08)
+#define VR4131_CLASSREG		(volatile unsigned int*)(KSEG1 + 0x0f000d08)
+#define VR4131_CACHELSREG	(volatile unsigned int*)(KSEG1 + 0x0f000d0c)
+#define VR4131_LATTIMERRG	(volatile unsigned int*)(KSEG1 + 0x0f000d0c)
+#define VR4131_MAILBAREG	(volatile unsigned int*)(KSEG1 + 0x0f000d10)
+#define VR4131_PCIMBA1REG	(volatile unsigned int*)(KSEG1 + 0x0f000d14)
+#define VR4131_PCIMBA2REG	(volatile unsigned int*)(KSEG1 + 0x0f000d18)
+
+/*#define VR41XX_PCIIRQ_OFFSET    (VR41XX_IRQ_MAX + 1)	*/
+/*#define VR41XX_PCIIRQ_MAX       (VR41XX_IRQ_MAX + 12)	*/
+/*#define VR4122_PCI_HOST_BASE    0xa0000000		*/
+
+volatile unsigned int *pciconfigaddr;
+volatile unsigned int *pciconfigdata;
+
+#define PCI_ACCESS_READ  0
+#define PCI_ACCESS_WRITE 1
+
+/*
+ *	Access PCI Configuration Register for VR4131
+ */
+
+static int vr4131_pci_config_access (u8 access_type, u32 dev, u32 reg,
+				     u32 * data)
+{
+	u32 bus;
+	u32 device;
+
+	bus = ((dev & 0xff0000) >> 16);
+	device = ((dev & 0xf800) >> 11);
+
+	if (bus == 0) {
+		/* Type 0 Configuration */
+		*VR4131_PCICONFAREG = (u32) (1UL << device | (reg & 0xfc));
+	} else {
+		/* Type 1 Configuration */
+		*VR4131_PCICONFAREG = (u32) (dev | ((reg / 4) << 2) | 1);
+	}
+
+	if (access_type == PCI_ACCESS_WRITE) {
+		*VR4131_PCICONFDREG = *data;
+	} else {
+		*data = *VR4131_PCICONFDREG;
+	}
+
+	return (0);
+}
+
+static int vr4131_pci_read_config_byte (u32 hose, u32 dev, u32 reg, u8 * val)
+{
+	u32 data;
+
+	if (vr4131_pci_config_access (PCI_ACCESS_READ, dev, reg, &data))
+		return -1;
+
+	*val = (data >> ((reg & 3) << 3)) & 0xff;
+
+	return 0;
+}
+
+
+static int vr4131_pci_read_config_word (u32 hose, u32 dev, u32 reg, u16 * val)
+{
+	u32 data;
+
+	if (reg & 1)
+		return -1;
+
+	if (vr4131_pci_config_access (PCI_ACCESS_READ, dev, reg, &data))
+		return -1;
+
+	*val = (data >> ((reg & 3) << 3)) & 0xffff;
+
+	return 0;
+}
+
+
+static int vr4131_pci_read_config_dword (u32 hose, u32 dev, u32 reg,
+					 u32 * val)
+{
+	u32 data = 0;
+
+	if (reg & 3)
+		return -1;
+
+	if (vr4131_pci_config_access (PCI_ACCESS_READ, dev, reg, &data))
+		return -1;
+
+	*val = data;
+
+	return (0);
+}
+
+static int vr4131_pci_write_config_byte (u32 hose, u32 dev, u32 reg, u8 val)
+{
+	u32 data = 0;
+
+	if (vr4131_pci_config_access (PCI_ACCESS_READ, dev, reg, &data))
+		return -1;
+
+	data = (data & ~(0xff << ((reg & 3) << 3))) | (val <<
+						       ((reg & 3) << 3));
+
+	if (vr4131_pci_config_access (PCI_ACCESS_WRITE, dev, reg, &data))
+		return -1;
+
+	return 0;
+}
+
+
+static int vr4131_pci_write_config_word (u32 hose, u32 dev, u32 reg, u16 val)
+{
+	u32 data = 0;
+
+	if (reg & 1)
+		return -1;
+
+	if (vr4131_pci_config_access (PCI_ACCESS_READ, dev, reg, &data))
+		return -1;
+
+	data = (data & ~(0xffff << ((reg & 3) << 3))) | (val <<
+							 ((reg & 3) << 3));
+
+	if (vr4131_pci_config_access (PCI_ACCESS_WRITE, dev, reg, &data))
+		return -1;
+
+	return 0;
+}
+
+static int vr4131_pci_write_config_dword (u32 hose, u32 dev, u32 reg, u32 val)
+{
+	u32 data;
+
+	if (reg & 3) {
+		return -1;
+	}
+
+	data = val;
+
+	if (vr4131_pci_config_access (PCI_ACCESS_WRITE, dev, reg, &data))
+		return -1;
+
+	return (0);
+}
+
+
+/*
+ *	Initialize VR4131 PCIU
+ */
+
+vr4131_pciu_init ()
+{
+	/* PCI clock */
+	*VR4131_PCICLKSELREG = 0x00000002;
+
+	/* PCI memory and I/O space */
+	*VR4131_PCIMMAW1REG = 0x100F9010;
+	*VR4131_PCIMMAW2REG = 0x140FD014;
+	*VR4131_PCIMIOAWREG = 0x160FD000;
+
+	/* Target memory window */
+	*VR4131_PCITAW1REG = 0x00081000;	/* 64MB */
+	*VR4131_PCITAW2REG = 0x00000000;
+
+	*VR4131_MAILBAREG = 0UL;
+	*VR4131_PCIMBA1REG = 0UL;
+
+	*VR4131_PCITRDYREG = 0x00008004;
+
+	*VR4131_PCIENREG = 0x00000004;	/* PCI enable */
+	*VR4131_COMMANDREG = 0x02000007;
+}
+
+/*
+ *	Initialize Module
+ */
+
+void init_vr4131_pci (struct pci_controller *hose)
+{
+	hose->first_busno = 0;
+	hose->last_busno = 0xff;
+
+	vr4131_pciu_init ();	/* Initialize VR4131 PCIU */
+
+	/* PCI memory space #1 */
+	pci_set_region (hose->regions + 0,
+			0x10000000, 0xb0000000, 0x04000000, PCI_REGION_MEM);
+
+	/* PCI memory space #2 */
+	pci_set_region (hose->regions + 1,
+			0x14000000, 0xb4000000, 0x02000000, PCI_REGION_MEM);
+
+
+	/* PCI I/O space */
+	pci_set_region (hose->regions + 2,
+			0x16000000, 0xb6000000, 0x02000000, PCI_REGION_IO);
+
+	/* System memory space */
+	pci_set_region (hose->regions + 3,
+			0x00000000,
+			0x80000000,
+			0x04000000, PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+	hose->region_count = 4;
+
+	hose->read_byte = vr4131_pci_read_config_byte;
+	hose->read_word = vr4131_pci_read_config_word;
+	hose->read_dword = vr4131_pci_read_config_dword;
+	hose->write_byte = vr4131_pci_write_config_byte;
+	hose->write_word = vr4131_pci_write_config_word;
+	hose->write_dword = vr4131_pci_write_config_dword;
+
+	pci_register_hose (hose);
+
+	hose->last_busno = pci_hose_scan (hose);
+
+	return;
+}

board/tqm8xx/tqm8xx.c

@@ -128,14 +128,6 @@ int checkboard (void)
 			break;
 		putc (*s);
 	}
-#if defined(CFG_866_CPUCLK_MIN) && defined(CFG_866_CPUCLK_MAX)
-	printf ("  [%d.%d...%d.%d MHz]",
-		CFG_866_CPUCLK_MIN / 1000000,
-		((CFG_866_CPUCLK_MIN % 1000000) + 50000) / 100000,
-		CFG_866_CPUCLK_MAX / 1000000,
-		((CFG_866_CPUCLK_MAX % 1000000) + 50000) / 100000
-	);
-#endif
 	putc ('\n');
 
 	return (0);

board/trab/u-boot.lds

@@ -39,7 +39,7 @@ SECTIONS
 	  lib_generic/string.o	(.text)
 
 	. = DEFINED(env_offset) ? env_offset : .;
-	common/environment.o	(.ppcenv)
+	  common/environment.o	(.ppcenv)
 
 	  *(.text)
 	}
@@ -53,15 +53,12 @@ SECTIONS
 	. = ALIGN(4);
 	.got : { *(.got) }
 
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
-
-	armboot_end_data = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
 
 	. = ALIGN(4);
+	__bss_start = .;
 	.bss : { *(.bss) }
-
-
-	armboot_end = .;
+	_end = .;
 }

board/wepep250/u-boot.lds

@@ -48,12 +48,8 @@ SECTIONS
 	.u_boot_cmd : { *(.u_boot_cmd) }
 	__u_boot_cmd_end = .;
 
-	armboot_end_data = .;
-
 	. = ALIGN(4);
-	bss_start = .;
+	__bss_start = .;
 	.bss : { *(.bss) }
-	bss_end = .;
-
-	armboot_end = .;
+	_end = .;
 }

board/xpedite1k/Makefile

@@ -0,0 +1,48 @@
+#
+# (C) Copyright 2002-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o
+OBJS +=flash.o
+SOBJS	= init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################

board/xpedite1k/config.mk

@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2002-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# esd ADCIOP boards
+#
+
+#TEXT_BASE = 0xFFFE0000
+
+ifeq ($(ramsym),1)
+TEXT_BASE = 0x07FD0000
+else
+TEXT_BASE = 0xFFF80000
+endif
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+endif

board/xpedite1k/flash.c

@@ -0,0 +1,607 @@
+/*
+ * (C) Copyright 2002-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
+ * Add support for Am29F016D and dynamic switch setting.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Modified 4/5/2001
+ * Wait for completion of each sector erase command issued
+ * 4/5/2001
+ * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
+ */
+
+/*
+ * Ported to XPedite1000, 1/2 mb boot flash only
+ * Travis B. Sawyer, <travis.sawyer@sandburst.com>
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+
+#undef DEBUG
+#ifdef DEBUG
+#define DEBUGF(x...) printf(x)
+#else
+#define DEBUGF(x...)
+#endif /* DEBUG */
+
+#define BOOT_SMALL_FLASH	32		/* 00100000 */
+#define FLASH_ONBD_N		2		/* 00000010 */
+#define FLASH_SRAM_SEL		1		/* 00000001 */
+
+#define BOOT_SMALL_FLASH_VAL	4
+#define FLASH_ONBD_N_VAL	2
+#define FLASH_SRAM_SEL_VAL	1
+
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+static unsigned long flash_addr_table[8][CFG_MAX_FLASH_BANKS] = {
+	{0xfff80000},	/* 0:000: configuraton 3 */
+	{0xfff90000},	/* 1:001: configuraton 4 */
+	{0xfffa0000},	/* 2:010: configuraton 7 */
+	{0xfffb0000},	/* 3:011: configuraton 8 */
+	{0xfffc0000},	/* 4:100: configuraton 1 */
+	{0xfffd0000},	/* 5:101: configuraton 2 */
+	{0xfffe0000},	/* 6:110: configuraton 5 */
+	{0xffff0000}	/* 7:111: configuraton 6 */
+};
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+
+
+#ifdef CONFIG_XPEDITE1K
+#define ADDR0		0x5555
+#define ADDR1		0x2aaa
+#define FLASH_WORD_SIZE unsigned char
+#endif
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long total_b = 0;
+	unsigned long size_b[CFG_MAX_FLASH_BANKS];
+	unsigned short index = 0;
+	int i;
+
+
+	DEBUGF("\n");
+	DEBUGF("FLASH: Index: %d\n", index);
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+		flash_info[i].sector_count = -1;
+		flash_info[i].size = 0;
+
+		/* check whether the address is 0 */
+		if (flash_addr_table[index][i] == 0) {
+			continue;
+		}
+
+		/* call flash_get_size() to initialize sector address */
+		size_b[i] = flash_get_size(
+			(vu_long *)flash_addr_table[index][i], &flash_info[i]);
+		flash_info[i].size = size_b[i];
+		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+			printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
+				i, size_b[i], size_b[i]<<20);
+			flash_info[i].sector_count = -1;
+			flash_info[i].size = 0;
+		}
+
+		total_b += flash_info[i].size;
+	}
+
+	return total_b;
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+	int k;
+	int size;
+	int erased;
+	volatile unsigned long *flash;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	case FLASH_MAN_SST:	printf ("SST ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AMD016:	printf ("AM29F016D (16 Mbit, uniform sector size)\n");
+		break;
+	case FLASH_AM040:	printf ("AM29F040 (512 Kbit, uniform sector size)\n");
+		break;
+	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+		break;
+	case FLASH_SST800A:	printf ("SST39LF/VF800 (8 Mbit, uniform sector size)\n");
+		break;
+	case FLASH_SST160A:	printf ("SST39LF/VF160 (16 Mbit, uniform sector size)\n");
+		break;
+	default:		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld KB in %d Sectors\n",
+		info->size >> 10, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		/*
+		 * Check if whole sector is erased
+		 */
+		if (i != (info->sector_count-1))
+			size = info->start[i+1] - info->start[i];
+		else
+			size = info->start[0] + info->size - info->start[i];
+		erased = 1;
+		flash = (volatile unsigned long *)info->start[i];
+		size = size >> 2;	 /* divide by 4 for longword access */
+		for (k=0; k<size; k++)
+		{
+			if (*flash++ != 0xffffffff)
+			{
+				erased = 0;
+				break;
+			}
+		}
+
+		if ((i % 5) == 0)
+			printf ("\n   ");
+			printf (" %08lX%s%s",
+				info->start[i],
+				erased ? " E" : "  ",
+				info->protect[i] ? "RO " : "   "
+				);
+			}
+		printf ("\n");
+		return;
+	}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	short i;
+	FLASH_WORD_SIZE value;
+	ulong base = (ulong)addr;
+	volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr;
+
+	DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr );
+
+	/* Write auto select command: read Manufacturer ID */
+	udelay(10000);
+	addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+	udelay(1000);
+	addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+	udelay(1000);
+	addr2[ADDR0] = (FLASH_WORD_SIZE)0x00900090;
+	udelay(1000);
+
+#ifdef CONFIG_ADCIOP
+	value = addr2[2];
+#else
+	value = addr2[0];
+#endif
+
+	DEBUGF("FLASH MANUFACT: %x\n", value);
+
+	switch (value) {
+	case (FLASH_WORD_SIZE)AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case (FLASH_WORD_SIZE)FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case (FLASH_WORD_SIZE)SST_MANUFACT:
+		info->flash_id = FLASH_MAN_SST;
+		break;
+	case (FLASH_WORD_SIZE)STM_MANUFACT:
+		info->flash_id = FLASH_MAN_STM;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+
+#ifdef CONFIG_ADCIOP
+	value = addr2[0];			/* device ID		*/
+	debug ("\ndev_code=%x\n", value);
+#else
+	value = addr2[1];			/* device ID		*/
+#endif
+
+	DEBUGF("\nFLASH DEVICEID: %x\n", value);
+
+	switch (value) {
+	case (FLASH_WORD_SIZE)AMD_ID_LV040B:
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x00080000; /* => 512 kb */
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+
+	}
+
+	/* set up sector start address table */
+	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+		    (info->flash_id  == FLASH_AM040) ||
+		    (info->flash_id  == FLASH_AMD016)) {
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * 0x00010000);
+	} else {
+		if (info->flash_id & FLASH_BTYPE) {
+			/* set sector offsets for bottom boot block type	*/
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00004000;
+			info->start[2] = base + 0x00006000;
+			info->start[3] = base + 0x00008000;
+			for (i = 4; i < info->sector_count; i++) {
+				info->start[i] = base + (i * 0x00010000) - 0x00030000;
+			}
+		} else {
+			/* set sector offsets for top boot block type		*/
+			i = info->sector_count - 1;
+			info->start[i--] = base + info->size - 0x00004000;
+			info->start[i--] = base + info->size - 0x00006000;
+			info->start[i--] = base + info->size - 0x00008000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00010000;
+			}
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+#ifdef CONFIG_ADCIOP
+		addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]);
+		info->protect[i] = addr2[4] & 1;
+#else
+		addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]);
+		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
+			info->protect[i] = 0;
+		else
+			info->protect[i] = addr2[2] & 1;
+#endif
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+#if 0 /* test-only */
+#ifdef CONFIG_ADCIOP
+		addr2 = (volatile unsigned char *)info->start[0];
+		addr2[ADDR0] = 0xAA;
+		addr2[ADDR1] = 0x55;
+		addr2[ADDR0] = 0xF0;  /* reset bank */
+#else
+		addr2 = (FLASH_WORD_SIZE *)info->start[0];
+		*addr2 = (FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
+#endif
+#else /* test-only */
+		addr2 = (FLASH_WORD_SIZE *)info->start[0];
+		*addr2 = (FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
+#endif /* test-only */
+	}
+
+	return (info->size);
+}
+
+int wait_for_DQ7(flash_info_t *info, int sect)
+{
+	ulong start, now, last;
+	volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[sect]);
+
+	start = get_timer (0);
+	last  = start;
+	while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) {
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return -1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {  /* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]);
+	volatile FLASH_WORD_SIZE *addr2;
+	int flag, prot, sect, l_sect;
+	int i;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) { /* not protected */
+			addr2 = (FLASH_WORD_SIZE *)(info->start[sect]);
+			printf("Erasing sector %p\n", addr2);
+
+			if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+				addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+				addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+				addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
+				addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+				addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+				addr2[0] = (FLASH_WORD_SIZE)0x00500050;	 /* block erase */
+				for (i=0; i<50; i++)
+					udelay(1000);  /* wait 1 ms */
+			} else {
+				addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+				addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+				addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
+				addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+				addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+				addr2[0] = (FLASH_WORD_SIZE)0x00300030;	 /* sector erase */
+			}
+			l_sect = sect;
+			/*
+			 * Wait for each sector to complete, it's more
+			 * reliable.  According to AMD Spec, you must
+			 * issue all erase commands within a specified
+			 * timeout.  This has been seen to fail, especially
+			 * if printf()s are included (for debug)!!
+			 */
+			wait_for_DQ7(info, sect);
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+#if 0
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+	wait_for_DQ7(info, l_sect);
+
+DONE:
+#endif
+	/* reset to read mode */
+	addr = (FLASH_WORD_SIZE *)info->start[0];
+	addr[0] = (FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t * info, ulong dest, ulong data)
+{
+	volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) (info->start[0]);
+	volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest;
+	volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data;
+	ulong start;
+	int i;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((volatile FLASH_WORD_SIZE *) dest) &
+	     (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
+		return (2);
+	}
+
+	for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) {
+		int flag;
+
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts ();
+
+		addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+		addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+		addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0;
+
+		dest2[i] = data2[i];
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts ();
+
+		/* data polling for D7 */
+		start = get_timer (0);
+		while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) !=
+		       (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) {
+
+			if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+				return (1);
+			}
+		}
+	}
+
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */

board/xpedite1k/init.S

@@ -0,0 +1,96 @@
+/*
+*  Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
+*
+* See file CREDITS for list of people who contributed to this
+* project.
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; either version 2 of
+* the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+* MA 02111-1307 USA
+*/
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+
+/* General */
+#define TLB_VALID   0x00000200
+
+/* Supported page sizes */
+
+#define SZ_1K	    0x00000000
+#define SZ_4K	    0x00000010
+#define SZ_16K	    0x00000020
+#define SZ_64K	    0x00000030
+#define SZ_256K	    0x00000040
+#define SZ_1M	    0x00000050
+#define SZ_16M	    0x00000070
+#define SZ_256M	    0x00000090
+
+/* Storage attributes */
+#define SA_W	    0x00000800	    /* Write-through */
+#define SA_I	    0x00000400	    /* Caching inhibited */
+#define SA_M	    0x00000200	    /* Memory coherence */
+#define SA_G	    0x00000100	    /* Guarded */
+#define SA_E	    0x00000080	    /* Endian */
+
+/* Access control */
+#define AC_X	    0x00000024	    /* Execute */
+#define AC_W	    0x00000012	    /* Write */
+#define AC_R	    0x00000009	    /* Read */
+
+/* Some handy macros */
+
+#define EPN(e)		((e) & 0xfffffc00)
+#define TLB0(epn,sz)	( (EPN((epn)) | (sz) | TLB_VALID ) )
+#define TLB1(rpn,erpn)	( ((rpn)&0xfffffc00) | (erpn) )
+#define TLB2(a)		( (a)&0x00000fbf )
+
+#define tlbtab_start\
+	mflr    r1  ;\
+	bl 0f	    ;
+
+#define tlbtab_end\
+	.long 0, 0, 0	;   \
+0:	mflr    r0	;   \
+	mtlr    r1	;   \
+	blr		;
+
+#define tlbentry(epn,sz,rpn,erpn,attr)\
+	.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
+
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ *  Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+
+	.section .bootpg,"ax"
+	.globl tlbtab
+
+tlbtab:
+	tlbtab_start
+	tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+	tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
+	tlbentry( CFG_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
+	tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+	tlbentry( CFG_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+	tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
+	tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I )
+	tlbtab_end

board/xpedite1k/u-boot.lds

@@ -0,0 +1,155 @@
+/*
+ * (C) Copyright 2002-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  .bootpg 0xFFFFF000 :
+  {
+    cpu/ppc4xx/start.o	(.bootpg)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+    board/xpedite1k/init.o	(.text)
+    cpu/ppc4xx/kgdb.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o	(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o	(.text)
+    cpu/ppc4xx/405gp_enet.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+    lib_generic/zlib.o		(.text)
+
+/*    . = env_offset;*/
+/*    common/environment.o(.text)*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}

board/xpedite1k/u-boot.lds.debug

@@ -0,0 +1,144 @@
+/*
+ * (C) Copyright 2002-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+    board/xpedite1k/init.o (.text)
+    cpu/ppc4xx/kgdb.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o	(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o	(.text)
+    cpu/ppc4xx/405gp_enet.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+    lib_generic/zlib.o		(.text)
+
+/*    common/environment.o(.text) */
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}

board/xpedite1k/xpedite1k.c

@@ -0,0 +1,358 @@
+/*
+ *  Copyright (C) 2003 Travis B. Sawyer	 <travis.sawyer@sandburst.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <asm/processor.h>
+#include <spd_sdram.h>
+#include <i2c.h>
+
+#define BOOT_SMALL_FLASH	32	/* 00100000 */
+#define FLASH_ONBD_N		2	/* 00000010 */
+#define FLASH_SRAM_SEL		1	/* 00000001 */
+
+long int fixed_sdram (void);
+
+int board_pre_init (void)
+{
+	unsigned long sdrreg;
+	/* TBS:	 Setup the GPIO access for the user LEDs */
+	mfsdr(sdr_pfc0, sdrreg);
+	mtsdr(sdr_pfc0, (sdrreg & ~0x00000100) | 0x00000E00);
+	out32(CFG_GPIO_BASE + 0x018, (USR_LED0 | USR_LED1 | USR_LED2 | USR_LED3));
+	LED0_OFF();
+	LED1_OFF();
+	LED2_OFF();
+	LED3_OFF();
+
+	/*--------------------------------------------------------------------
+	 * Setup the external bus controller/chip selects
+	 *-------------------------------------------------------------------*/
+
+	/* set the bus controller */
+	mtebc (pb0ap, 0x04055200);	/* FLASH/SRAM */
+	mtebc (pb0cr, 0xfff18000);	/* BAS=0xfff 1MB R/W 8-bit */
+
+	/*--------------------------------------------------------------------
+	 * Setup the interrupt controller polarities, triggers, etc.
+	 *-------------------------------------------------------------------*/
+	mtdcr (uic0sr, 0xffffffff);	/* clear all */
+	mtdcr (uic0er, 0x00000000);	/* disable all */
+	mtdcr (uic0cr, 0x00000003);	/* SMI & UIC1 crit are critical */
+	mtdcr (uic0pr, 0xfffffe00);	/* per ref-board manual */
+	mtdcr (uic0tr, 0x01c00000);	/* per ref-board manual */
+	mtdcr (uic0vr, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (uic0sr, 0xffffffff);	/* clear all */
+
+	mtdcr (uic1sr, 0xffffffff);	/* clear all */
+	mtdcr (uic1er, 0x00000000);	/* disable all */
+	mtdcr (uic1cr, 0x00000000);	/* all non-critical */
+	mtdcr (uic1pr, 0xffffc0ff);	/* per ref-board manual */
+	mtdcr (uic1tr, 0x00ff8000);	/* per ref-board manual */
+	mtdcr (uic1vr, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (uic1sr, 0xffffffff);	/* clear all */
+
+	mtdcr (uic2sr, 0xffffffff);	/* clear all */
+	mtdcr (uic2er, 0x00000000);	/* disable all */
+	mtdcr (uic2cr, 0x00000000);	/* all non-critical */
+	mtdcr (uic2pr, 0xffffffff);	/* per ref-board manual */
+	mtdcr (uic2tr, 0x00ff8c0f);	/* per ref-board manual */
+	mtdcr (uic2vr, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (uic2sr, 0xffffffff);	/* clear all */
+
+	mtdcr (uicb0sr, 0xfc000000); /* clear all */
+	mtdcr (uicb0er, 0x00000000); /* disable all */
+	mtdcr (uicb0cr, 0x00000000); /* all non-critical */
+	mtdcr (uicb0pr, 0xfc000000); /* */
+	mtdcr (uicb0tr, 0x00000000); /* */
+	mtdcr (uicb0vr, 0x00000001); /* */
+
+	LED0_ON();
+
+
+	return 0;
+}
+
+int checkboard (void)
+{
+	sys_info_t sysinfo;
+	get_sys_info (&sysinfo);
+
+	printf ("Board: XES XPedite1000 440GX\n");
+	printf ("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
+	printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
+	printf ("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
+	printf ("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
+	printf ("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
+
+	return (0);
+}
+
+
+long int initdram (int board_type)
+{
+	long dram_size = 0;
+
+#if defined(CONFIG_SPD_EEPROM)
+	dram_size = spd_sdram (0);
+#else
+	dram_size = fixed_sdram ();
+#endif
+	return dram_size;
+}
+
+
+#if defined(CFG_DRAM_TEST)
+int testdram (void)
+{
+	uint *pstart = (uint *) 0x00000000;
+	uint *pend = (uint *) 0x08000000;
+	uint *p;
+
+	for (p = pstart; p < pend; p++)
+		*p = 0xaaaaaaaa;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0xaaaaaaaa) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	for (p = pstart; p < pend; p++)
+		*p = 0x55555555;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0x55555555) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+	return 0;
+}
+#endif
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*************************************************************************
+ *  fixed sdram init -- doesn't use serial presence detect.
+ *
+ *  Assumes:	128 MB, non-ECC, non-registered
+ *		PLB @ 133 MHz
+ *
+ ************************************************************************/
+long int fixed_sdram (void)
+{
+	uint reg;
+
+	/*--------------------------------------------------------------------
+	 * Setup some default
+	 *------------------------------------------------------------------*/
+	mtsdram (mem_uabba, 0x00000000);	/* ubba=0 (default)		*/
+	mtsdram (mem_slio, 0x00000000);		/* rdre=0 wrre=0 rarw=0		*/
+	mtsdram (mem_devopt, 0x00000000);	/* dll=0 ds=0 (normal)		*/
+	mtsdram (mem_wddctr, 0x00000000);	/* wrcp=0 dcd=0			*/
+	mtsdram (mem_clktr, 0x40000000);	/* clkp=1 (90 deg wr) dcdt=0	*/
+
+	/*--------------------------------------------------------------------
+	 * Setup for board-specific specific mem
+	 *------------------------------------------------------------------*/
+	/*
+	 * Following for CAS Latency = 2.5 @ 133 MHz PLB
+	 */
+	mtsdram (mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
+	mtsdram (mem_tr0, 0x410a4012);	/* WR=2	 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
+	/* RA=10 RD=3			    */
+	mtsdram (mem_tr1, 0x8080082f);	/* SS=T2 SL=STAGE 3 CD=1 CT=0x02f   */
+	mtsdram (mem_rtr, 0x08200000);	/* Rate 15.625 ns @ 133 MHz PLB	    */
+	mtsdram (mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM    */
+	udelay (400);			/* Delay 200 usecs (min)	    */
+
+	/*--------------------------------------------------------------------
+	 * Enable the controller, then wait for DCEN to complete
+	 *------------------------------------------------------------------*/
+	mtsdram (mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit	    */
+	for (;;) {
+		mfsdram (mem_mcsts, reg);
+		if (reg & 0x80000000)
+			break;
+	}
+
+	return (128 * 1024 * 1024);	/* 128 MB			    */
+}
+#endif	/* !defined(CONFIG_SPD_EEPROM) */
+
+
+/*************************************************************************
+ *  pci_pre_init
+ *
+ *  This routine is called just prior to registering the hose and gives
+ *  the board the opportunity to check things. Returning a value of zero
+ *  indicates that things are bad & PCI initialization should be aborted.
+ *
+ *	Different boards may wish to customize the pci controller structure
+ *	(add regions, override default access routines, etc) or perform
+ *	certain pre-initialization actions.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
+int pci_pre_init(struct pci_controller * hose )
+{
+	unsigned long strap;
+
+	/*--------------------------------------------------------------------------+
+	 * TBS:
+	 *	The xpedite1k is a PrPMC board, however for our purposes it is the host
+	 *--------------------------------------------------------------------------*/
+	strap = mfdcr(cpc0_strp1);
+	if( (strap & 0x00100000) == 0 ){
+		printf("PCI: CPC0_STRP1[PAE] not set.\n");
+		return 0;
+	}
+
+	return 1;
+}
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
+
+/*************************************************************************
+ *  pci_target_init
+ *
+ *	The bootstrap configuration provides default settings for the pci
+ *	inbound map (PIM). But the bootstrap config choices are limited and
+ *	may not be sufficient for a given board.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+void pci_target_init(struct pci_controller * hose )
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/*--------------------------------------------------------------------------+
+	 * Disable everything
+	 *--------------------------------------------------------------------------*/
+	out32r( PCIX0_PIM0SA, 0 ); /* disable */
+	out32r( PCIX0_PIM1SA, 0 ); /* disable */
+	out32r( PCIX0_PIM2SA, 0 ); /* disable */
+	out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
+
+	/*--------------------------------------------------------------------------+
+	 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
+	 * options to not support sizes such as 128/256 MB.
+	 *--------------------------------------------------------------------------*/
+	out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
+	out32r( PCIX0_PIM0LAH, 0 );
+	out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
+
+	out32r( PCIX0_BAR0, 0 );
+
+	/*--------------------------------------------------------------------------+
+	 * Program the board's subsystem id/vendor id
+	 *--------------------------------------------------------------------------*/
+	out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
+	out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
+
+	out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
+}
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+
+
+/*************************************************************************
+ *  is_pci_host
+ *
+ *	This routine is called to determine if a pci scan should be
+ *	performed. With various hardware environments (especially cPCI and
+ *	PPMC) it's insufficient to depend on the state of the arbiter enable
+ *	bit in the strap register, or generic host/adapter assumptions.
+ *
+ *	Rather than hard-code a bad assumption in the general 440 code, the
+ *	440 pci code requires the board to decide at runtime.
+ *
+ *	Return 0 for adapter mode, non-zero for host (monarch) mode.
+ *
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI)
+int is_pci_host(struct pci_controller *hose)
+{
+	/* The ebony board is always configured as host. */
+	/* TBS:	 The xpedite1k is not necessarily the host, however for our purposes, it is. */
+	return(1);
+}
+#endif /* defined(CONFIG_PCI) */
+
+#ifdef CONFIG_POST
+/*
+ * Returns 1 if keys pressed to start the power-on long-running tests
+ * Called from board_init_f().
+ */
+int post_hotkeys_pressed(void)
+{
+
+	return (ctrlc());
+}
+
+void post_word_store (ulong a)
+{
+	volatile ulong *save_addr =
+		(volatile ulong *)(CFG_POST_WORD_ADDR);
+
+	*save_addr = a;
+}
+
+ulong post_word_load (void)
+{
+	volatile ulong *save_addr =
+		(volatile ulong *)(CFG_POST_WORD_ADDR);
+
+	return *save_addr;
+}
+#endif
+
+/*-----------------------------------------------------------------------------
+ * board_get_enetaddr -- Read the MAC Addresses in the I2C EEPROM
+ *-----------------------------------------------------------------------------
+ */
+static int enetaddr_num = 0;
+void board_get_enetaddr (uchar * enet)
+{
+	int i;
+	unsigned char buff[0x100], *cp;
+
+	/* Initialize I2C					*/
+	i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+
+	/* Read 256 bytes in EEPROM				*/
+	i2c_read (0x50, 0, 1, buff, 0x100);
+
+	if (enetaddr_num == 0) {
+		cp = &buff[0xF4];
+		enetaddr_num = 1;
+	}
+	else
+		cp = &buff[0xFA];
+
+	for (i = 0; i < 6; i++,cp++)
+		enet[i] = *cp;
+
+	printf ("MAC address = %02x:%02x:%02x:%02x:%02x:%02x\n",
+		enet[0], enet[1], enet[2], enet[3], enet[4], enet[5]);
+
+}

common/cmd_bootm.c

@@ -333,8 +333,14 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 #ifdef CONFIG_BZIP2
 	case IH_COMP_BZIP2:
 		printf ("   Uncompressing %s ... ", name);
+		/*
+		 * If we've got less than 4 MB of malloc() space,
+		 * use slower decompression algorithm which requires
+		 * at most 2300 KB of memory.
+		 */
 		i = BZ2_bzBuffToBuffDecompress ((char*)ntohl(hdr->ih_load),
-						&unc_len, (char *)data, len, 0, 0);
+						&unc_len, (char *)data, len,
+						CFG_MALLOC_LEN < (4096 * 1024), 0);
 		if (i != BZ_OK) {
 			printf ("BUNZIP2 ERROR %d - must RESET board to recover\n", i);
 			SHOW_BOOT_PROGRESS (-6);

common/cmd_pcmcia.c

@@ -160,6 +160,9 @@ int pcmcia_on (void)
 }
 #else
 
+#ifdef CONFIG_BMS2003
+# define  BMS2003_FRAM_TIMING	(PCMCIA_SHT(2) | PCMCIA_SST(2) | PCMCIA_SL(4))
+#endif
 #if defined(CONFIG_LWMON) || defined(CONFIG_NSCU)
 # define  CFG_PCMCIA_TIMING	(PCMCIA_SHT(9) | PCMCIA_SST(3) | PCMCIA_SL(12))
 #else
@@ -197,6 +200,17 @@ int pcmcia_on (void)
 		switch (i) {
 #ifdef CONFIG_IDE_8xx_PCCARD
 		case 4:
+#ifdef CONFIG_BMS2003
+		    {	/* map FRAM area */
+			win->or = (	PCMCIA_BSIZE_256K
+				|	PCMCIA_PPS_8
+				|	PCMCIA_PRS_ATTR
+				|	slotbit
+				|	PCMCIA_PV
+				|	BMS2003_FRAM_TIMING );
+			break;
+		    }
+#endif
 		case 0:	{	/* map attribute memory */
 			win->or = (	PCMCIA_BSIZE_64M
 				|	PCMCIA_PPS_8

common/console.c

@@ -191,6 +191,11 @@ void putc (const char c)
 {
 	DECLARE_GLOBAL_DATA_PTR;
 
+#ifdef CONFIG_SILENT_CONSOLE
+	if (gd->flags & GD_FLG_SILENT)
+		return;
+#endif
+
 	if (gd->flags & GD_FLG_DEVINIT) {
 		/* Send to the standard output */
 		fputc (stdout, c);
@@ -204,6 +209,11 @@ void puts (const char *s)
 {
 	DECLARE_GLOBAL_DATA_PTR;
 
+#ifdef CONFIG_SILENT_CONSOLE
+	if (gd->flags & GD_FLG_SILENT)
+		return;
+#endif
+
 	if (gd->flags & GD_FLG_DEVINIT) {
 		/* Send to the standard output */
 		fputs (stdout, s);

common/miiphyutil.c

@@ -99,7 +99,9 @@ int miiphy_reset (unsigned char addr)
 #endif
 		return (-1);
 	}
-
+#ifdef CONFIG_PHY_RESET_DELAY
+	udelay (CONFIG_PHY_RESET_DELAY);	/* Intel LXT971A needs this */
+#endif
 	/*
 	 * Poll the control register for the reset bit to go to 0 (it is
 	 * auto-clearing).  This should happen within 0.5 seconds per the

cpu/arm720t/cpu.c

@@ -87,7 +87,7 @@ int cpu_init (void)
 #ifdef CONFIG_USE_IRQ
 	DECLARE_GLOBAL_DATA_PTR;
 
-	IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_LEN - 4;
+	IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
 	FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
 #endif
 	return 0;

cpu/arm720t/start.S

@@ -63,7 +63,7 @@ _fiq:			.word fiq
  *
  * Startup Code (reset vector)
  *
- * do important init only if we don't start from memory!
+ * do important init only if we don't start from RAM!
  * relocate armboot to ram
  * setup stack
  * jump to second stage
@@ -79,16 +79,15 @@ _armboot_start:
 	.word _start
 
 /*
- * Note: _armboot_end_data and _armboot_end are defined
- * by the (board-dependent) linker script.
- * _armboot_end_data is the first usable FLASH address after armboot
+ * These are defined in the board-specific linker script.
  */
-.globl _armboot_end_data
-_armboot_end_data:
-	.word armboot_end_data
-.globl _armboot_end
-_armboot_end:
-	.word armboot_end
+.globl _bss_start
+_bss_start:
+	.word __bss_start
+
+.globl _bss_end
+_bss_end:
+	.word _end
 
 #ifdef CONFIG_USE_IRQ
 /* IRQ stack memory (calculated at run-time) */
@@ -131,7 +130,7 @@ relocate:				/* relocate U-Boot to RAM	    */
 	beq     stack_setup
 
 	ldr	r2, _armboot_start
-	ldr	r3, _armboot_end
+	ldr	r3, _bss_start
 	sub	r2, r3, r2		/* r2 <- size of armboot            */
 	add	r2, r0, r2		/* r2 <- source end address         */
 
@@ -151,6 +150,17 @@ stack_setup:
 #endif
 	sub	sp, r0, #12		/* leave 3 words for abort-stack    */
 
+clear_bss:
+	ldr	r0, _bss_start		/* find start of bss segment        */
+	add	r0, r0, #4		/* start at first byte of bss       */
+	ldr	r1, _bss_end		/* stop here                        */
+	mov 	r2, #0x00000000		/* clear                            */
+
+clbss_l:str	r2, [r0]		/* clear loop...                    */
+	add	r0, r0, #4
+	cmp	r0, r1
+	bne	clbss_l
+
 	ldr	pc, _start_armboot
 
 _start_armboot:	.word start_armboot
@@ -225,7 +235,7 @@ cpu_init_crit:
 
 	/*
 	 * before relocating, we have to setup RAM timing
-	 * because memory timing is board-dependend, you will
+	 * because memory timing is board-dependent, you will
 	 * find a memsetup.S in your board directory.
 	 */
 	mov	ip, lr
@@ -281,9 +291,9 @@ cpu_init_crit:
 	stmia	sp, {r0 - r12}			@ Calling r0-r12
 	add     r8, sp, #S_PC
 
-	ldr	r2, _armboot_end
-	add	r2, r2, #CONFIG_STACKSIZE
-	sub	r2, r2, #8
+	ldr	r2, _armboot_start
+	sub	r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
+	sub	r2, r2, #(CFG_GBL_DATA_SIZE+8)  @ set base 2 words into abort stack
 	ldmia	r2, {r2 - r4}                   @ get pc, cpsr, old_r0
 	add	r0, sp, #S_FRAME_SIZE		@ restore sp_SVC
 
@@ -314,9 +324,9 @@ cpu_init_crit:
 	.endm
 
 	.macro get_bad_stack
-	ldr	r13, _armboot_end		@ setup our mode stack
-	add	r13, r13, #CONFIG_STACKSIZE	@ resides at top of normal stack
-	sub	r13, r13, #8
+	ldr	r13, _armboot_start		@ setup our mode stack
+	sub	r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
+	sub	r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
 
 	str	lr, [r13]			@ save caller lr / spsr
 	mrs	lr, spsr

cpu/arm920t/cpu.c

@@ -92,7 +92,7 @@ int cpu_init (void)
 #ifdef CONFIG_USE_IRQ
 	DECLARE_GLOBAL_DATA_PTR;
 
-	IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_LEN - 4;
+	IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
 	FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
 #endif
 	return 0;

cpu/arm920t/start.S

@@ -80,16 +80,15 @@ _armboot_start:
 	.word _start
 
 /*
- * Note: _armboot_end_data and _armboot_end are defined
- * by the (board-dependent) linker script.
- * _armboot_end_data is the first usable FLASH address after armboot
+ * These are defined in the board-specific linker script.
  */
-.globl _armboot_end_data
-_armboot_end_data:
-	.word armboot_end_data
-.globl _armboot_end
-_armboot_end:
-	.word armboot_end
+.globl _bss_start
+_bss_start:
+	.word __bss_start
+
+.globl _bss_end
+_bss_end:
+	.word _end
 
 #ifdef CONFIG_USE_IRQ
 /* IRQ stack memory (calculated at run-time) */
@@ -170,7 +169,7 @@ relocate:				/* relocate U-Boot to RAM	    */
 	beq     stack_setup
 
 	ldr	r2, _armboot_start
-	ldr	r3, _armboot_end
+	ldr	r3, _bss_start
 	sub	r2, r3, r2		/* r2 <- size of armboot            */
 	add	r2, r0, r2		/* r2 <- source end address         */
 
@@ -190,6 +189,17 @@ stack_setup:
 #endif
 	sub	sp, r0, #12		/* leave 3 words for abort-stack    */
 
+clear_bss:
+	ldr	r0, _bss_start		/* find start of bss segment        */
+	add	r0, r0, #4		/* start at first byte of bss       */
+	ldr	r1, _bss_end		/* stop here                        */
+	mov 	r2, #0x00000000		/* clear                            */
+
+clbss_l:str	r2, [r0]		/* clear loop...                    */
+	add	r0, r0, #4
+	cmp	r0, r1
+	bne	clbss_l
+
 #if 0
 	/* try doing this stuff after the relocation */
 	ldr     r0, =pWTCON
@@ -303,9 +313,9 @@ cpu_init_crit:
 	.macro	bad_save_user_regs
 	sub	sp, sp, #S_FRAME_SIZE
 	stmia	sp, {r0 - r12}			@ Calling r0-r12
-	ldr	r2, _armboot_end
-	add	r2, r2, #CONFIG_STACKSIZE
-	sub	r2, r2, #8
+	ldr	r2, _armboot_start
+	sub	r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
+	sub	r2, r2, #(CFG_GBL_DATA_SIZE+8)  @ set base 2 words into abort stack
 	ldmia	r2, {r2 - r3}			@ get pc, cpsr
 	add	r0, sp, #S_FRAME_SIZE		@ restore sp_SVC
 
@@ -336,9 +346,9 @@ cpu_init_crit:
 	.endm
 
 	.macro get_bad_stack
-	ldr	r13, _armboot_end		@ setup our mode stack
-	add	r13, r13, #CONFIG_STACKSIZE	@ resides at top of normal stack
-	sub	r13, r13, #8
+	ldr	r13, _armboot_start		@ setup our mode stack
+	sub	r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
+	sub	r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
 
 	str	lr, [r13]			@ save caller lr / spsr
 	mrs	lr, spsr

cpu/arm925t/cpu.c

@@ -93,7 +93,7 @@ int cpu_init (void)
 #ifdef CONFIG_USE_IRQ
 	DECLARE_GLOBAL_DATA_PTR;
 
-	IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_LEN - 4;
+	IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
 	FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
 #endif
 	return 0;

cpu/arm925t/start.S

@@ -89,16 +89,15 @@ _armboot_start:
 	.word _start
 
 /*
- * Note: _armboot_end_data and _armboot_end are defined
- * by the (board-dependent) linker script.
- * _armboot_end_data is the first usable FLASH address after armboot
+ * These are defined in the board-specific linker script.
  */
-.globl _armboot_end_data
-_armboot_end_data:
-	.word armboot_end_data
-.globl _armboot_end
-_armboot_end:
-	.word armboot_end
+.globl _bss_start
+_bss_start:
+	.word __bss_start
+
+.globl _bss_end
+_bss_end:
+	.word _end
 
 #ifdef CONFIG_USE_IRQ
 /* IRQ stack memory (calculated at run-time) */
@@ -176,7 +175,7 @@ relocate:				/* relocate U-Boot to RAM	    */
 	beq     stack_setup
 
 	ldr	r2, _armboot_start
-	ldr	r3, _armboot_end
+	ldr	r3, _bss_start
 	sub	r2, r3, r2		/* r2 <- size of armboot            */
 	add	r2, r0, r2		/* r2 <- source end address         */
 
@@ -196,6 +195,17 @@ stack_setup:
 #endif
 	sub	sp, r0, #12		/* leave 3 words for abort-stack    */
 
+clear_bss:
+	ldr	r0, _bss_start		/* find start of bss segment        */
+	add	r0, r0, #4		/* start at first byte of bss       */
+	ldr	r1, _bss_end		/* stop here                        */
+	mov 	r2, #0x00000000		/* clear                            */
+
+clbss_l:str	r2, [r0]		/* clear loop...                    */
+	add	r0, r0, #4
+	cmp	r0, r1
+	bne	clbss_l
+
 	ldr	pc, _start_armboot
 
 _start_armboot:	.word start_armboot
@@ -283,9 +293,9 @@ cpu_init_crit:
 	sub	sp, sp, #S_FRAME_SIZE           @ carve out a frame on current user stack
 	stmia	sp, {r0 - r12}			@ Save user registers (now in svc mode) r0-r12
 
-	ldr	r2, _armboot_end                @ find top of stack
-	add	r2, r2, #CONFIG_STACKSIZE       @ find base of normal stack
-	sub	r2, r2, #8                      @ set base 2 words into abort stack
+	ldr	r2, _armboot_start
+	sub	r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
+	sub	r2, r2, #(CFG_GBL_DATA_SIZE+8)  @ set base 2 words into abort stack
 	ldmia	r2, {r2 - r3}                   @ get values for "aborted" pc and cpsr (into parm regs)
 	add	r0, sp, #S_FRAME_SIZE		@ grab pointer to old stack
 
@@ -316,9 +326,9 @@ cpu_init_crit:
 	.endm
 
 	.macro get_bad_stack
-	ldr	r13, _armboot_end		@ get bottom of stack (into sp by by user stack pointer).
-	add	r13, r13, #CONFIG_STACKSIZE	@ head to reserved words at the top of the stack
-	sub	r13, r13, #8                    @ reserved a couple spots in abort stack
+	ldr	r13, _armboot_start		@ setup our mode stack
+	sub	r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
+	sub	r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
 
 	str	lr, [r13]			@ save caller lr in position 0 of saved stack
 	mrs	lr, spsr                        @ get the spsr

cpu/arm926ejs/cpu.c

@@ -93,7 +93,7 @@ int cpu_init (void)
 #ifdef CONFIG_USE_IRQ
 	DECLARE_GLOBAL_DATA_PTR;
 
-	IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_LEN - 4;
+	IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
 	FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
 #endif
 	return 0;

cpu/arm926ejs/start.S

@@ -97,16 +97,15 @@ _armboot_start:
 	.word _start
 
 /*
- * Note: _armboot_end_data and _armboot_end are defined
- * by the (board-dependent) linker script.
- * _armboot_end_data is the first usable FLASH address after armboot
+ * These are defined in the board-specific linker script.
  */
-.globl _armboot_end_data
-_armboot_end_data:
-	.word armboot_end_data
-.globl _armboot_end
-_armboot_end:
-	.word armboot_end
+.globl _bss_start
+_bss_start:
+	.word __bss_start
+
+.globl _bss_end
+_bss_end:
+	.word _end
 
 #ifdef CONFIG_USE_IRQ
 /* IRQ stack memory (calculated at run-time) */
@@ -170,7 +169,7 @@ relocate:				/* relocate U-Boot to RAM	    */
 	beq     stack_setup
 
 	ldr	r2, _armboot_start
-	ldr	r3, _armboot_end
+	ldr	r3, _bss_start
 	sub	r2, r3, r2		/* r2 <- size of armboot            */
 	add	r2, r0, r2		/* r2 <- source end address         */
 
@@ -190,6 +189,17 @@ stack_setup:
 #endif
 	sub	sp, r0, #12		/* leave 3 words for abort-stack    */
 
+clear_bss:
+	ldr	r0, _bss_start		/* find start of bss segment        */
+	add	r0, r0, #4		/* start at first byte of bss       */
+	ldr	r1, _bss_end		/* stop here                        */
+	mov 	r2, #0x00000000		/* clear                            */
+
+clbss_l:str	r2, [r0]		/* clear loop...                    */
+	add	r0, r0, #4
+	cmp	r0, r1
+	bne	clbss_l
+
 	ldr	pc, _start_armboot
 
 _start_armboot:
@@ -278,9 +288,10 @@ cpu_init_crit:
 	@ carve out a frame on current user stack
 	sub	sp, sp, #S_FRAME_SIZE
 	stmia	sp, {r0 - r12}	@ Save user registers (now in svc mode) r0-r12
-	ldr	r2, _armboot_end	@ find top of stack
-	add	r2, r2, #CONFIG_STACKSIZE	@ find base of normal stack
-	sub	r2, r2, #8	@ set base 2 words into abort stack
+
+	ldr	r2, _armboot_start
+	sub	r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
+	sub	r2, r2, #(CFG_GBL_DATA_SIZE+8)  @ set base 2 words into abort stack
 	@ get values for "aborted" pc and cpsr (into parm regs)
 	ldmia	r2, {r2 - r3}
 	add	r0, sp, #S_FRAME_SIZE		@ grab pointer to old stack
@@ -312,11 +323,9 @@ cpu_init_crit:
 	.endm
 
 	.macro get_bad_stack
-	@ get bottom of stack (into sp by by user stack pointer).
-	ldr	r13, _armboot_end
-	@ head to reserved words at the top of the stack
-	add	r13, r13, #CONFIG_STACKSIZE
-	sub	r13, r13, #8	@ reserved a couple spots in abort stack
+	ldr	r13, _armboot_start		@ setup our mode stack
+	sub	r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
+	sub	r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
 
 	str	lr, [r13]	@ save caller lr in position 0 of saved stack
 	mrs	lr, spsr	@ get the spsr

cpu/at91rm9200/cpu.c

@@ -87,7 +87,7 @@ int cpu_init(void)
 #ifdef CONFIG_USE_IRQ
 	DECLARE_GLOBAL_DATA_PTR;
 
-	IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_LEN - 4;
+	IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
 	FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
 #endif
 	return 0;

cpu/at91rm9200/start.S

@@ -79,19 +79,15 @@ _armboot_start:
 	.word _start
 
 /*
- * Note: _armboot_end_data and _armboot_end are defined
- * by the (board-dependent) linker script.
- * _armboot_end_data is the first usable FLASH address after armboot
+ * These are defined in the board-specific linker script.
  */
-.globl _armboot_end_data
-_armboot_end_data:
-	.word armboot_end_data
-/*
- * Note: armboot_end is defined by the (board-dependent) linker script
- */
-.globl _armboot_end
-_armboot_end:
-	.word armboot_end
+.globl _bss_start
+_bss_start:
+	.word __bss_start
+
+.globl _bss_end
+_bss_end:
+	.word _end
 
 #ifdef CONFIG_USE_IRQ
 /* IRQ stack memory (calculated at run-time) */
@@ -149,6 +145,17 @@ stack_setup:
 #endif
 	sub	sp, r0, #12		/* leave 3 words for abort-stack    */
 
+clear_bss:
+	ldr	r0, _bss_start		/* find start of bss segment        */
+	add	r0, r0, #4		/* start at first byte of bss       */
+	ldr	r1, _bss_end		/* stop here                        */
+	mov 	r2, #0x00000000		/* clear                            */
+
+clbss_l:str	r2, [r0]		/* clear loop...                    */
+	add	r0, r0, #4
+	cmp	r0, r1
+	bne	clbss_l
+
 	ldr pc,_start_armboot
 
 _start_armboot: .word start_armboot
@@ -212,9 +219,9 @@ cpu_init_crit:
 	stmia	sp, {r0 - r12}			@ Calling r0-r12
 	add     r8, sp, #S_PC
 
-	ldr	r2, _armboot_end
-	add	r2, r2, #CONFIG_STACKSIZE
-	sub	r2, r2, #8
+	ldr	r2, _armboot_start
+	sub	r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
+	sub	r2, r2, #(CFG_GBL_DATA_SIZE+8)  @ set base 2 words into abort stack
 	ldmia	r2, {r2 - r4}                   @ get pc, cpsr, old_r0
 	add	r0, sp, #S_FRAME_SIZE		@ restore sp_SVC
 
@@ -245,9 +252,9 @@ cpu_init_crit:
 	.endm
 
 	.macro get_bad_stack
-	ldr	r13, _armboot_end		@ setup our mode stack
-	add	r13, r13, #CONFIG_STACKSIZE	@ resides at top of normal stack
-	sub	r13, r13, #8
+	ldr	r13, _armboot_start		@ setup our mode stack
+	sub	r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
+	sub	r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
 
 	str	lr, [r13]			@ save caller lr / spsr
 	mrs	lr, spsr

cpu/ixp/cpu.c

@@ -37,22 +37,16 @@
 int cpu_init (void)
 {
 	/*
-	 * setup up stack if necessary
+	 * setup up stacks if necessary
 	 */
-/*
-
-  FIXME: the stack is _below_ the uboot code!!
-
 #ifdef CONFIG_USE_IRQ
-	IRQ_STACK_START = _armboot_end +
-			CONFIG_STACKSIZE + CONFIG_STACKSIZE_IRQ - 4;
-	FIQ_STACK_START = IRQ_STACK_START + CONFIG_STACKSIZE_FIQ;
-	_armboot_real_end = FIQ_STACK_START + 4;
-#else
-	_armboot_real_end = _armboot_end + CONFIG_STACKSIZE;
+	DECLARE_GLOBAL_DATA_PTR;
+
+	IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
+	FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
 #endif
-*/
-   pci_init();
+
+	pci_init();
 	return 0;
 }
 
@@ -84,7 +78,7 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
 	extern void reset_cpu (ulong addr);
 
-	printf ("reseting ...\n");
+	printf ("resetting ...\n");
 
 	udelay (50000);				/* wait 50 ms */
 	disable_interrupts ();

cpu/ixp/start.S

@@ -101,42 +101,15 @@ _armboot_start:
 	.word _start
 
 /*
- * Note: _armboot_end_data and _armboot_end are defined
- * by the (board-dependent) linker script.
- * _armboot_end_data is the first usable FLASH address after armboot
- */
-.globl _armboot_end_data
-_armboot_end_data:
-	.word armboot_end_data
-.globl _armboot_end
-_armboot_end:
-	.word armboot_end
-
-/*
- * This is defined in the board specific linker script
+ * These are defined in the board-specific linker script.
  */
 .globl _bss_start
 _bss_start:
-	.word bss_start
+	.word __bss_start
 
 .globl _bss_end
 _bss_end:
-	.word bss_end
-
-/*
- * _armboot_real_end is the first usable RAM address behind armboot
- * and the various stacks
- */
-.globl _armboot_real_end
-_armboot_real_end:
-	.word 0x0badc0de
-
-/*
- * We relocate uboot to this address (end of RAM - 128 KiB)
- */
-.globl _uboot_reloc
-_uboot_reloc:
-	.word TEXT_BASE
+	.word _end
 
 #ifdef CONFIG_USE_IRQ
 /* IRQ stack memory (calculated at run-time) */
@@ -294,7 +267,7 @@ relocate:				/* relocate U-Boot to RAM	    */
 	beq     stack_setup
 
 	ldr	r2, _armboot_start
-	ldr	r3, _armboot_end
+	ldr	r3, _bss_start
 	sub	r2, r3, r2		/* r2 <- size of armboot            */
 	add	r2, r0, r2		/* r2 <- source end address         */
 
@@ -305,16 +278,16 @@ copy_loop:
 	ble	copy_loop
 
 	/* Set up the stack						    */
-
 stack_setup:
-
-	ldr	r0, _uboot_reloc	/* upper 128 KiB: relocated uboot   */
-	sub	r0, r0, #CFG_MALLOC_LEN /* malloc area			    */
-					/* FIXME: bdinfo should be here	    */
+	ldr	r0, _TEXT_BASE		/* upper 128 KiB: relocated uboot   */
+	sub	r0, r0, #CFG_MALLOC_LEN	/* malloc area                      */
+	sub	r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo                        */
+#ifdef CONFIG_USE_IRQ
+	sub	r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
+#endif
 	sub	sp, r0, #12		/* leave 3 words for abort-stack    */
 
 clear_bss:
-
 	ldr	r0, _bss_start		/* find start of bss segment        */
 	add	r0, r0, #4		/* start at first byte of bss       */
 	ldr	r1, _bss_end		/* stop here                        */
@@ -325,7 +298,6 @@ clbss_l:str	r2, [r0]		/* clear loop...                    */
 	cmp	r0, r1
 	bne	clbss_l
 
-
 	ldr	pc, _start_armboot
 
 _start_armboot: .word start_armboot
@@ -370,9 +342,9 @@ _start_armboot: .word start_armboot
 	stmia	sp, {r0 - r12}			/* Calling r0-r12	    */
 	add	r8, sp, #S_PC
 
-	ldr	r2, _armboot_end
-	add	r2, r2, #CONFIG_STACKSIZE
-	sub	r2, r2, #8
+	ldr	r2, _armboot_start
+	sub	r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
+	sub	r2, r2, #(CFG_GBL_DATA_SIZE+8)  @ set base 2 words into abort stack
 	ldmia	r2, {r2 - r4}			/* get pc, cpsr, old_r0	    */
 	add	r0, sp, #S_FRAME_SIZE		/* restore sp_SVC	    */
 
@@ -407,9 +379,9 @@ _start_armboot: .word start_armboot
 	.endm
 
 	.macro get_bad_stack
-	ldr	r13, _armboot_end		@ setup our mode stack
-	add	r13, r13, #CONFIG_STACKSIZE	@ resides at top of normal stack
-	sub	r13, r13, #8
+	ldr	r13, _armboot_start		@ setup our mode stack
+	sub	r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
+	sub	r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
 
 	str	lr, [r13]			@ save caller lr / spsr
 	mrs	lr, spsr

cpu/mips/cpu.c

@@ -30,7 +30,7 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
 #if defined(CONFIG_INCA_IP)
 	*INCA_IP_WDT_RST_REQ = 0x3f;
-#elif defined(CONFIG_PURPLE)
+#elif defined(CONFIG_PURPLE) || defined(CONFIG_TB0229)
 	void (*f)(void) = (void *) 0xbfc00000;
 
 	f();

cpu/mips/start.S

@@ -214,7 +214,11 @@ reset:
 	mtc0	zero, CP0_WATCHHI
 
 	/* STATUS register */
+#ifdef  CONFIG_TB0229
+	li	k0, ST0_CU0
+#else
 	mfc0	k0, CP0_STATUS
+#endif
 	li	k1, ~ST0_IE
 	and	k0, k1
 	mtc0	k0, CP0_STATUS

cpu/mpc5xxx/serial.c

@@ -67,10 +67,10 @@ int serial_init (void)
 	/* select clock sources */
 #if defined(CONFIG_MGT5100)
 	psc->psc_clock_select = 0xdd00;
-	baseclk = CFG_MPC5XXX_CLKIN / 32;
+	baseclk = (CFG_MPC5XXX_CLKIN + 16) / 32;
 #elif defined(CONFIG_MPC5200)
 	psc->psc_clock_select = 0;
-	baseclk = gd->ipb_clk / 32;
+	baseclk = (gd->ipb_clk + 16) / 32;
 #endif
 
 	/* switch to UART mode */
@@ -85,8 +85,8 @@ int serial_init (void)
 	psc->mode = PSC_MODE_ONE_STOP;
 
 	/* set up UART divisor */
-	div = baseclk / gd->baudrate;
-	psc->ctur = div >> 8;
+	div = (baseclk + (gd->baudrate/2)) / gd->baudrate;
+	psc->ctur = (div >> 8) & 0xff;
 	psc->ctlr = div & 0xff;
 
 	/* disable all interrupts */

cpu/mpc5xxx/start.S

@@ -104,6 +104,9 @@ boot_warm:
 	mfmsr	r5			/* save msr contents		*/
 
 #if defined(CFG_LOWBOOT)
+#if defined(CFG_RAMBOOT)
+#error CFG_LOWBOOT is incompatible with CFG_RAMBOOT
+#endif /* CFG_RAMBOOT */
 	lis	r4, CFG_DEFAULT_MBAR@h
 	lis	r3,     0x0000FF00@h
 	ori	r3, r3, 0x0000FF00@l

cpu/mpc8xx/cpu.c

@@ -123,10 +123,22 @@ static int check_CPU (long clock, uint pvr, uint immr)
 	else
 		printf ("unknown M%s (0x%08x)", id_str, k);
 
-	printf (" at %s MHz:", strmhz (buf, clock));
 
-	printf (" %u kB I-Cache", checkicache () >> 10);
-	printf (" %u kB D-Cache", checkdcache () >> 10);
+#if defined(CFG_866_CPUCLK_MIN) && defined(CFG_866_CPUCLK_MAX)
+	printf (" at %s MHz [%d.%d...%d.%d MHz]\n       ",
+		strmhz (buf, clock),
+		CFG_866_CPUCLK_MIN / 1000000,
+		((CFG_866_CPUCLK_MIN % 1000000) + 50000) / 100000,
+		CFG_866_CPUCLK_MAX / 1000000,
+		((CFG_866_CPUCLK_MAX % 1000000) + 50000) / 100000
+	);
+#else
+	printf (" at %s MHz: ", strmhz (buf, clock));
+#endif
+	printf ("%u kB I-Cache %u kB D-Cache",
+		checkicache () >> 10,
+		checkdcache () >> 10
+	);
 
 	/* do we have a FEC (860T/P or 852/859/866)? */
 

cpu/mpc8xx/plprcr_write.S

@@ -122,23 +122,13 @@ plprcr_wait:
 
 plprcr_wait_end:
 
-	/* turn instruction cache off
+	/* unlock instruction cache but leave it enabled
 	 */
 	lis	r4, CACHE_CMD_UNLOCK_ALL@h
 	ori	r4, r4, CACHE_CMD_UNLOCK_ALL@l
 	mtspr	IC_CST, r4
 	isync
 
-	lis	r4, CACHE_CMD_INVALIDATE@h
-	ori	r4, r4, CACHE_CMD_INVALIDATE@l
-	mtspr	IC_CST, r4
-	isync
-
-	lis	r4, CACHE_CMD_DISABLE@h
-	ori	r4, r4, CACHE_CMD_DISABLE@l
-	mtspr	IC_CST, r4
-	isync
-
 	mtspr	LR, r10		/* restore original Link Register value */
 	blr
 

cpu/mpc8xx/serial.c

@@ -71,11 +71,11 @@
 static void serial_setdivisor(volatile cpm8xx_t *cp)
 {
 	DECLARE_GLOBAL_DATA_PTR;
-	int divisor=gd->cpu_clk/16/gd->baudrate;
+	int divisor=(gd->cpu_clk + 8*gd->baudrate)/16/gd->baudrate;
 
 	if(divisor/16>0x1000) {
 		/* bad divisor, assume 50Mhz clock and 9600 baud */
-		divisor=(50*1000*1000)/16/9600;
+		divisor=(50*1000*1000 + 8*9600)/16/9600;
 	}
 
 #ifdef CFG_BRGCLK_PRESCALE

cpu/mpc8xx/speed.c

@@ -25,7 +25,7 @@
 #include <mpc8xx.h>
 #include <asm/processor.h>
 
-#ifndef CONFIG_TQM866M
+#if !defined(CONFIG_TQM866M) || defined(CFG_MEASURE_CPUCLK)
 
 #define PITC_SHIFT 16
 #define PITR_SHIFT 16
@@ -64,18 +64,18 @@ static __inline__ void set_msr(unsigned long msr)
  * These strange values for the timing interval and prescaling are used
  * because the formula for the CPU clock is:
  *
- *   CPU clock = count * (177 * (8192 / 58))
+ *    CPU clock = count * (177 * (8192 / 58))
  *
- *             = count * 24999.7241
+ *		= count * 24999.7241
  *
- *   which is very close to
+ *    which is very close to
  *
- *             = count * 25000
+ *		= count * 25000
  *
  * Since the count gives the CPU clock divided by 25000, we can get
  * the CPU clock rounded to the nearest 0.1 MHz by
  *
- *   CPU clock = ((count + 2) / 4) * 100000;
+ *    CPU clock = ((count + 2) / 4) * 100000;
  *
  * The rounding is important since the measurement is sometimes going
  * to be high or low by 0.025 MHz, depending on exactly how the clocks
@@ -112,8 +112,8 @@ unsigned long measure_gclk(void)
 	 */
 	timerp->cpmt_tmr2 = ((177 - 1) << TMR_PS_SHIFT) | TMR_ICLK_IN_GEN;
 
-	timerp->cpmt_tcn2 = 0;		/* reset state      */
-	timerp->cpmt_tgcr |= TGCR_RST2;	/* enable timer 2   */
+	timerp->cpmt_tcn2 = 0;		/* reset state		*/
+	timerp->cpmt_tgcr |= TGCR_RST2;	/* enable timer 2	*/
 
 	/*
 	 * PIT setup:
@@ -148,9 +148,9 @@ unsigned long measure_gclk(void)
 	/* spin until get exact count when we want to start */
 	while (immr->im_sit.sit_pitr > SPEED_PITC);
 
-	timerp->cpmt_tgcr &= ~TGCR_STP2;	/* Start Timer 2    */
+	timerp->cpmt_tgcr &= ~TGCR_STP2;	/* Start Timer 2	*/
 	while ((immr->im_sit.sit_piscr & PISCR_PS) == 0);
-	timerp->cpmt_tgcr |= TGCR_STP2;		/* Stop  Timer 2    */
+	timerp->cpmt_tgcr |= TGCR_STP2;		/* Stop  Timer 2	*/
 
 	/* re-enable external interrupts if they were on */
 	set_msr (msr_val);
@@ -166,10 +166,14 @@ unsigned long measure_gclk(void)
 	/* not using OSCM, using XIN, so scale appropriately */
 	return (((timer2_val + 2) / 4) * (CFG_8XX_XIN/512))/8192 * 100000L;
 #else
-	return ((timer2_val + 2) / 4) * 100000L;	/* convert to Hz    */
+	return ((timer2_val + 2) / 4) * 100000L;	/* convert to Hz	*/
 #endif
 }
 
+#endif
+
+#if !defined(CONFIG_TQM866M)
+
 /*
  * get_clocks() fills in gd->cpu_clock depending on CONFIG_8xx_GCLK_FREQ
  * or (if it is not defined) measure_gclk() (which uses the ref clock)
@@ -220,8 +224,9 @@ int get_clocks_866 (void)
 	DECLARE_GLOBAL_DATA_PTR;
 
 	volatile immap_t *immr = (immap_t *) CFG_IMMR;
-	char              tmp[64];
-	long              cpuclk = 0;
+	char		  tmp[64];
+	long		  cpuclk = 0;
+	long		  sccr_reg;
 
 	if (getenv_r ("cpuclk", tmp, sizeof (tmp)) > 0)
 		cpuclk = simple_strtoul (tmp, NULL, 10) * 1000000;
@@ -230,11 +235,23 @@ int get_clocks_866 (void)
 		cpuclk = CFG_866_CPUCLK_DEFAULT;
 
 	gd->cpu_clk = init_pll_866 (cpuclk);
+#if defined(CFG_MEASURE_CPUCLK)
+	gd->cpu_clk = measure_gclk ();
+#endif
 
-	if ((immr->im_clkrst.car_sccr & SCCR_EBDF11) == 0)
+	/* if cpu clock <= 66 MHz then set bus division factor to 1,
+	 * otherwise set it to 2
+	 */
+	sccr_reg = immr->im_clkrst.car_sccr;
+	sccr_reg &= ~SCCR_EBDF11;
+	if (gd->cpu_clk <= 66000000) {
+		sccr_reg |= SCCR_EBDF00;	/* bus division factor = 1 */
 		gd->bus_clk = gd->cpu_clk;
-	else
+	} else {
+		sccr_reg |= SCCR_EBDF01;	/* bus division factor = 2 */
 		gd->bus_clk = gd->cpu_clk / 2;
+	}
+	immr->im_clkrst.car_sccr = sccr_reg;
 
 	return (0);
 }
@@ -246,7 +263,7 @@ int sdram_adjust_866 (void)
 	DECLARE_GLOBAL_DATA_PTR;
 
 	volatile immap_t *immr = (immap_t *) CFG_IMMR;
-	long              mamr;
+	long		  mamr;
 
 	mamr = immr->im_memctl.memc_mamr;
 	mamr &= ~MAMR_PTA_MSK;
@@ -265,12 +282,23 @@ static long init_pll_866 (long clk)
 	extern void plprcr_write_866 (long);
 
 	volatile immap_t *immr = (immap_t *) CFG_IMMR;
-	long              n, plprcr;
-	char              mfi, mfn, mfd, s, pdf;
-	long              step_mfi, step_mfn;
+	long		  n, plprcr;
+	char		  mfi, mfn, mfd, s, pdf;
+	long		  step_mfi, step_mfn;
 
-	pdf = 0;
-	if (clk < 80000000) {
+	if (clk < 20000000) {
+		clk *= 2;
+		pdf = 1;
+	} else {
+		pdf = 0;
+	}
+
+	if (clk < 40000000) {
+		s = 2;
+		step_mfi = CFG_866_OSCCLK / 4;
+		mfd = 7;
+		step_mfn = CFG_866_OSCCLK / 30;
+	} else if (clk < 80000000) {
 		s = 1;
 		step_mfi = CFG_866_OSCCLK / 2;
 		mfd = 14;
@@ -294,13 +322,14 @@ static long init_pll_866 (long clk)
 
 	/* Calculate effective clk
 	 */
-	n = (mfi * step_mfi) + (mfn * step_mfn);
+	n = ((mfi * step_mfi) + (mfn * step_mfn)) / (pdf + 1);
 
 	immr->im_clkrstk.cark_plprcrk = KAPWR_KEY;
 
 	plprcr = (immr->im_clkrst.car_plprcr & ~(PLPRCR_MFN_MSK
 			| PLPRCR_MFD_MSK | PLPRCR_S_MSK
-			| PLPRCR_MFI_MSK | PLPRCR_DBRMO))
+			| PLPRCR_MFI_MSK | PLPRCR_DBRMO
+			| PLPRCR_PDF_MSK))
 			| (mfn << PLPRCR_MFN_SHIFT)
 			| (mfd << PLPRCR_MFD_SHIFT)
 			| (s << PLPRCR_S_SHIFT)

cpu/nios/Makefile

@@ -27,7 +27,7 @@ LIB	= lib$(CPU).a
 
 START	= start.o
 AOBJS	= traps.o
-OBJS	= cpu.o interrupts.o serial.o asmi.o
+OBJS	= cpu.o interrupts.o serial.o asmi.o spi.o
 
 all:	.depend $(START) $(LIB)
 

cpu/nios/spi.c

@@ -0,0 +1,158 @@
+/*
+ * (C) Copyright 2004, Li-Pro.Net <www.li-pro.net>
+ * Stephan Linz <linz@li-pro.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/ctype.h>
+
+#if defined(CONFIG_NIOS_SPI)
+#include <nios-io.h>
+#include <spi.h>
+
+#if !defined(CFG_NIOS_SPIBASE)
+#error "*** CFG_NIOS_SPIBASE not defined ***"
+#endif
+
+#if !defined(CFG_NIOS_SPIBITS)
+#error "*** CFG_NIOS_SPIBITS not defined ***"
+#endif
+
+#if (CFG_NIOS_SPIBITS != 8) && (CFG_NIOS_SPIBITS != 16)
+#error "*** CFG_NIOS_SPIBITS should be either 8 or 16 ***"
+#endif
+
+static nios_spi_t	*spi	= (nios_spi_t *)CFG_NIOS_SPIBASE;
+
+/* Warning:
+ * You cannot enable DEBUG for early system initalization, i. e. when
+ * this driver is used to read environment parameters like "baudrate"
+ * from EEPROM which are used to initialize the serial port which is
+ * needed to print the debug messages...
+ */
+#undef	DEBUG
+
+#ifdef  DEBUG
+
+#define	DPRINT(a)	printf a;
+/* -----------------------------------------------
+ * Helper functions to peek into tx and rx buffers
+ * ----------------------------------------------- */
+static const char * const hex_digit = "0123456789ABCDEF";
+
+static char quickhex (int i)
+{
+	return hex_digit[i];
+}
+
+static void memdump (void *pv, int num)
+{
+	int i;
+	unsigned char *pc = (unsigned char *) pv;
+
+	for (i = 0; i < num; i++)
+		printf ("%c%c ", quickhex (pc[i] >> 4), quickhex (pc[i] & 0x0f));
+	printf ("\t");
+	for (i = 0; i < num; i++)
+		printf ("%c", isprint (pc[i]) ? pc[i] : '.');
+	printf ("\n");
+}
+#else   /* !DEBUG */
+
+#define	DPRINT(a)
+#define	memdump(p,n)
+
+#endif  /* DEBUG */
+
+
+/*
+ * SPI transfer:
+ *
+ * See include/spi.h and http://www.altera.com/literature/ds/ds_nios_spi.pdf
+ * for more informations.
+ */
+int spi_xfer(spi_chipsel_type chipsel, int bitlen, uchar *dout, uchar *din)
+{
+	int j;
+
+	DPRINT(("spi_xfer: chipsel %08X dout %08X din %08X bitlen %d\n",
+		(int)chipsel, *(uint *)dout, *(uint *)din, bitlen));
+
+	memdump((void*)dout, (bitlen + 7) / 8);
+
+	if(chipsel != NULL) {
+		chipsel(1);	/* select the target chip */
+	}
+
+	if (bitlen > CFG_NIOS_SPIBITS) {	/* leave chip select active */
+		spi->control |= NIOS_SPI_SSO;
+	}
+
+	for (	j = 0;				/* count each byte in */
+		j < ((bitlen + 7) / 8);		/* dout[] and din[] */
+
+#if	(CFG_NIOS_SPIBITS == 8)
+		j++) {
+
+		while ((spi->status & NIOS_SPI_TRDY) == 0)
+			;
+		spi->txdata = (unsigned)(dout[j]);
+
+		while ((spi->status & NIOS_SPI_RRDY) == 0)
+			;
+		din[j] = (unsigned char)(spi->rxdata & 0xff);
+
+#elif	(CFG_NIOS_SPIBITS == 16)
+		j++, j++) {
+
+		while ((spi->status & NIOS_SPI_TRDY) == 0)
+			;
+		if ((j+1) < ((bitlen + 7) / 8))
+			spi->txdata = (unsigned)((dout[j] << 8) | dout[j+1]);
+		else
+			spi->txdata = (unsigned)(dout[j] << 8);
+
+		while ((spi->status & NIOS_SPI_RRDY) == 0)
+			;
+		din[j] = (unsigned char)((spi->rxdata >> 8) & 0xff);
+		if ((j+1) < ((bitlen + 7) / 8))
+			din[j+1] = (unsigned char)(spi->rxdata & 0xff);
+
+#else
+#error "*** unsupported value of CFG_NIOS_SPIBITS ***"
+#endif
+
+	}
+
+	if (bitlen > CFG_NIOS_SPIBITS) {
+		spi->control &= ~NIOS_SPI_SSO;
+	}
+
+	if(chipsel != NULL) {
+		chipsel(0);	/* deselect the target chip */
+	}
+
+	memdump((void*)din, (bitlen + 7) / 8);
+
+	return 0;
+}
+
+#endif /* CONFIG_NIOS_SPI */

cpu/ppc4xx/405gp_enet.c

@@ -83,7 +83,8 @@
 #include <malloc.h>
 #include "vecnum.h"
 
-#if defined(CONFIG_405GP) || defined(CONFIG_440) || defined(CONFIG_405EP)
+#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \
+  ( defined(CONFIG_440)   && !defined(CONFIG_NET_MULTI))
 
 #define EMAC_RESET_TIMEOUT 1000	/* 1000 ms reset timeout */
 #define PHY_AUTONEGOTIATE_TIMEOUT 4000	/* 4000 ms autonegotiate timeout */

cpu/ppc4xx/Makefile

@@ -27,9 +27,12 @@ LIB	= lib$(CPU).a
 
 START	= start.o resetvec.o kgdb.o
 AOBJS	= dcr.o
-COBJS	= traps.o serial.o cpu.o cpu_init.o speed.o interrupts.o \
-	  405gp_pci.o 405gp_enet.o miiphy.o i2c.o bedbug_405.o \
-	  spd_sdram.o sdram.o
+COBJS	= 405gp_enet.o 405gp_pci.o 440gx_enet.o \
+	  bedbug_405.o \
+	  cpu.o cpu_init.o i2c.o interrupts.o \
+	  miiphy.o miiphy_440.o sdram.o serial.o \
+	  spd_sdram.o speed.o traps.o
+
 OBJS	= $(AOBJS) $(COBJS)
 
 all:	.depend $(START) $(LIB)

cpu/ppc4xx/cpu.c

@@ -152,10 +152,10 @@ int checkcpu (void)
 #endif
 
 #if defined(CONFIG_440)
-	puts ("IBM PowerPC 440 Rev. ");
+	puts ("IBM PowerPC 440 G");
 	switch(pvr) {
 	case PVR_440GP_RB:
-		putc('B');
+		puts("P Rev. B");
 		/* See errata 1.12: CHIP_4 */
 		if ((mfdcr(cpc0_sys0) != mfdcr(cpc0_strp0)) ||
 		    (mfdcr(cpc0_sys1) != mfdcr(cpc0_strp1)) ){
@@ -167,7 +167,13 @@ int checkcpu (void)
 		}
 		break;
 	case PVR_440GP_RC:
-		putc('C');
+		puts("P Rev. C");
+		break;
+	case PVR_440GX_RA:
+		puts("X Rev. A");
+		break;
+	case PVR_440GX_RB:
+		puts("X Rev. B");
 		break;
 	default:
 		printf ("UNKNOWN (PVR=%08x)", pvr);

cpu/ppc4xx/interrupts.c

@@ -5,6 +5,9 @@
  * (C) Copyright 2002 (440 port)
  * Scott McNutt, Artesyn Communication Producs, smcnutt@artsyncp.com
  *
+ * (C) Copyright 2003 (440GX port)
+ * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
+ *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
@@ -50,7 +53,15 @@ static struct irq_action irq_vecs[32];
 static struct irq_action irq_vecs1[32]; /* For UIC1 */
 
 void uic1_interrupt( void * parms); /* UIC1 handler */
-#endif
+
+#if defined(CONFIG_440_GX)
+static struct irq_action irq_vecs2[32]; /* For UIC2 */
+
+void uic0_interrupt( void * parms); /* UIC0 handler */
+void uic2_interrupt( void * parms); /* UIC2 handler */
+#endif /* CONFIG_440_GX */
+
+#endif /* CONFIG_440 */
 
 /****************************************************************************/
 #if defined(CONFIG_440)
@@ -104,6 +115,11 @@ int interrupt_init_cpu (unsigned *decrementer_count)
 		irq_vecs1[vec].handler = NULL;
 		irq_vecs1[vec].arg = NULL;
 		irq_vecs1[vec].count = 0;
+#if defined(CONFIG_440_GX)
+		irq_vecs2[vec].handler = NULL;
+		irq_vecs2[vec].arg = NULL;
+		irq_vecs2[vec].count = 0;
+#endif /* CONFIG_440_GX */
 #endif
 	}
 
@@ -146,10 +162,18 @@ int interrupt_init_cpu (unsigned *decrementer_count)
 	set_evpr(0x00000000);
 
 #if defined(CONFIG_440)
+#if !defined(CONFIG_440_GX)
 	/* Install the UIC1 handlers */
 	irq_install_handler(VECNUM_UIC1NC, uic1_interrupt, 0);
 	irq_install_handler(VECNUM_UIC1C, uic1_interrupt, 0);
 #endif
+#endif
+
+#if defined(CONFIG_440_GX)
+	/* Enable UIC interrupts via UIC Base Enable Register */
+	mtdcr(uicb0er, UICB0_ALL);
+	mtdcr(uicb0cr, UICB0_ALL);
+#endif
 
 	return (0);
 }
@@ -159,6 +183,29 @@ int interrupt_init_cpu (unsigned *decrementer_count)
 /*
  * Handle external interrupts
  */
+#if defined(CONFIG_440_GX)
+void external_interrupt(struct pt_regs *regs)
+{
+	ulong uic_msr;
+
+	/*
+	 * Read masked interrupt status register to determine interrupt source
+	 */
+	/* 440 GX uses base uic register */
+	uic_msr = mfdcr(uicb0msr);
+
+	uic0_interrupt(0);
+	uic1_interrupt(0);
+	uic2_interrupt(0);
+
+	mtdcr(uicb0sr, UICB0_ALL);
+
+	return;
+
+} /* external_interrupt CONFIG_440_GX */
+
+#else
+
 void external_interrupt(struct pt_regs *regs)
 {
 	ulong uic_msr;
@@ -200,6 +247,53 @@ void external_interrupt(struct pt_regs *regs)
 		vec++;
 	}
 }
+#endif
+
+#if defined(CONFIG_440_GX)
+/* Handler for UIC0 interrupt */
+void uic0_interrupt( void * parms)
+{
+	ulong uic_msr;
+	ulong msr_shift;
+	int vec;
+
+	/*
+	 * Read masked interrupt status register to determine interrupt source
+	 */
+	uic_msr = mfdcr(uicmsr);
+	msr_shift = uic_msr;
+	vec = 0;
+
+	while (msr_shift != 0) {
+		if (msr_shift & 0x80000000) {
+			/*
+			 * Increment irq counter (for debug purpose only)
+			 */
+			irq_vecs[vec].count++;
+
+			if (irq_vecs[vec].handler != NULL) {
+				/* call isr */
+				(*irq_vecs[vec].handler)(irq_vecs[vec].arg);
+			} else {
+				mtdcr(uicer, mfdcr(uicer) & ~(0x80000000 >> vec));
+				printf ("Masking bogus interrupt vector (uic0) 0x%x\n", vec);
+			}
+
+			/*
+			 * After servicing the interrupt, we have to remove the status indicator.
+			 */
+			mtdcr(uicsr, (0x80000000 >> vec));
+		}
+
+		/*
+		 * Shift msr to next position and increment vector
+		 */
+		msr_shift <<= 1;
+		vec++;
+	}
+}
+
+#endif /* CONFIG_440_GX */
 
 #if defined(CONFIG_440)
 /* Handler for UIC1 interrupt */
@@ -246,50 +340,119 @@ void uic1_interrupt( void * parms)
 }
 #endif /* defined(CONFIG_440) */
 
+#if defined(CONFIG_440_GX)
+/* Handler for UIC1 interrupt */
+void uic2_interrupt( void * parms)
+{
+	ulong uic2_msr;
+	ulong msr_shift;
+	int vec;
+
+	/*
+	 * Read masked interrupt status register to determine interrupt source
+	 */
+	uic2_msr = mfdcr(uic2msr);
+	msr_shift = uic2_msr;
+	vec = 0;
+
+	while (msr_shift != 0) {
+		if (msr_shift & 0x80000000) {
+			/*
+			 * Increment irq counter (for debug purpose only)
+			 */
+			irq_vecs2[vec].count++;
+
+			if (irq_vecs2[vec].handler != NULL) {
+				/* call isr */
+				(*irq_vecs2[vec].handler)(irq_vecs2[vec].arg);
+			} else {
+				mtdcr(uic2er, mfdcr(uic2er) & ~(0x80000000 >> vec));
+				printf ("Masking bogus interrupt vector (uic1) 0x%x\n", vec);
+			}
+
+			/*
+			 * After servicing the interrupt, we have to remove the status indicator.
+			 */
+			mtdcr(uic2sr, (0x80000000 >> vec));
+		}
+
+		/*
+		 * Shift msr to next position and increment vector
+		 */
+		msr_shift <<= 1;
+		vec++;
+	}
+}
+#endif /* defined(CONFIG_440_GX) */
+
 /****************************************************************************/
 
 /*
  * Install and free a interrupt handler.
  */
 
-void
-irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)
+void irq_install_handler (int vec, interrupt_handler_t * handler, void *arg)
 {
 	struct irq_action *irqa = irq_vecs;
-	int   i = vec;
+	int i = vec;
 
 #if defined(CONFIG_440)
+#if defined(CONFIG_440_GX)
+	if ((vec > 31) && (vec < 64)) {
+		i = vec - 32;
+		irqa = irq_vecs1;
+	} else if (vec > 63) {
+		i = vec - 64;
+		irqa = irq_vecs2;
+	}
+#else  /* CONFIG_440_GX */
 	if (vec > 31) {
 		i = vec - 32;
 		irqa = irq_vecs1;
 	}
-#endif
+#endif /* CONFIG_440_GX */
+#endif /* CONFIG_440 */
 
 	if (irqa[i].handler != NULL) {
 		printf ("Interrupt vector %d: handler 0x%x replacing 0x%x\n",
-			vec, (uint)handler, (uint)irqa[i].handler);
+			vec, (uint) handler, (uint) irqa[i].handler);
 	}
 	irqa[i].handler = handler;
-	irqa[i].arg     = arg;
+	irqa[i].arg = arg;
 
 #if defined(CONFIG_440)
-	if( vec > 31 )
-		mtdcr(uic1er, mfdcr(uic1er) | (0x80000000 >> i));
+#if defined(CONFIG_440_GX)
+	if ((vec > 31) && (vec < 64))
+		mtdcr (uic1er, mfdcr (uic1er) | (0x80000000 >> i));
+	else if (vec > 63)
+		mtdcr (uic2er, mfdcr (uic2er) | (0x80000000 >> i));
+	else
+#endif /* CONFIG_440_GX */
+	if (vec > 31)
+		mtdcr (uic1er, mfdcr (uic1er) | (0x80000000 >> i));
 	else
 #endif
-		mtdcr(uicer, mfdcr(uicer) | (0x80000000 >> i));
+		mtdcr (uicer, mfdcr (uicer) | (0x80000000 >> i));
 #if 0
 	printf ("Install interrupt for vector %d ==> %p\n", vec, handler);
 #endif
 }
 
-void
-irq_free_handler(int vec)
+void irq_free_handler (int vec)
 {
 	struct irq_action *irqa = irq_vecs;
-	int   i = vec;
+	int i = vec;
 
 #if defined(CONFIG_440)
+#if defined(CONFIG_440_GX)
+	if ((vec > 31) && (vec < 64)) {
+		irqa = irq_vecs1;
+		i = vec - 32;
+	} else if (vec > 63) {
+		irqa = irq_vecs2;
+		i = vec - 64;
+	}
+#endif /* CONFIG_440_GX */
 	if (vec > 31) {
 		irqa = irq_vecs1;
 		i = vec - 32;
@@ -302,14 +465,21 @@ irq_free_handler(int vec)
 #endif
 
 #if defined(CONFIG_440)
+#if defined(CONFIG_440_GX)
+	if ((vec > 31) && (vec < 64))
+		mtdcr (uic1er, mfdcr (uic1er) & ~(0x80000000 >> i));
+	else if (vec > 63)
+		mtdcr (uic2er, mfdcr (uic2er) & ~(0x80000000 >> i));
+	else
+#endif /* CONFIG_440_GX */
 	if (vec > 31)
-		mtdcr(uic1er, mfdcr(uic1er) & ~(0x80000000 >> i));
+		mtdcr (uic1er, mfdcr (uic1er) & ~(0x80000000 >> i));
 	else
 #endif
-		mtdcr(uicer, mfdcr(uicer) & ~(0x80000000 >> i));
+		mtdcr (uicer, mfdcr (uicer) & ~(0x80000000 >> i));
 
 	irqa[i].handler = NULL;
-	irqa[i].arg     = NULL;
+	irqa[i].arg = NULL;
 }
 
 /****************************************************************************/
@@ -354,8 +524,7 @@ do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	printf ("\nUIC 1\n");
 	printf ("Nr  Routine   Arg       Count\n");
 
-	for (vec=0; vec<32; vec++)
-	{
+	for (vec=0; vec<32; vec++) {
 		if (irq_vecs1[vec].handler != NULL)
 			printf ("%02d  %08lx  %08lx  %d\n",
 				vec+31, (ulong)irq_vecs1[vec].handler,
@@ -363,8 +532,20 @@ do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	}
 	printf("\n");
 #endif
+
+#if defined(CONFIG_440_GX)
+	printf ("\nUIC 2\n");
+	printf ("Nr  Routine   Arg       Count\n");
+
+	for (vec=0; vec<32; vec++) {
+		if (irq_vecs2[vec].handler != NULL)
+			printf ("%02d  %08lx  %08lx  %d\n",
+				vec+63, (ulong)irq_vecs2[vec].handler,
+				(ulong)irq_vecs2[vec].arg, irq_vecs2[vec].count);
+	}
+	printf("\n");
+#endif
+
 	return 0;
 }
-
-
 #endif  /* CONFIG_COMMANDS & CFG_CMD_IRQ */

cpu/ppc4xx/miiphy.c

@@ -48,8 +48,8 @@
 #include <405_mal.h>
 #include <miiphy.h>
 
-#if defined(CONFIG_405GP) || defined(CONFIG_440) || defined(CONFIG_405EP)
-
+#if (defined(CONFIG_405GP) || defined(CONFIG_405EP) || defined(CONFIG_440)) \
+   && !defined (CONFIG_NET_MULTI)
 
 /***********************************************************/
 /* Dump out to the screen PHY regs                         */
@@ -113,6 +113,9 @@ int miiphy_read (unsigned char addr, unsigned char reg,
 	printf ("a2: write: EMAC_STACR=0x%0x\n", sta_reg);	/* test-only */
 #endif
 
+#ifdef CONFIG_PHY_CMD_DELAY
+	udelay (CONFIG_PHY_CMD_DELAY);		/* Intel LXT971A needs this */
+#endif
 	sta_reg = in32 (EMAC_STACR);
 	i = 0;
 	while ((sta_reg & EMAC_STACR_OC) == 0) {
@@ -173,6 +176,9 @@ int miiphy_write (unsigned char addr, unsigned char reg,
 
 	out32 (EMAC_STACR, sta_reg);
 
+#ifdef CONFIG_PHY_CMD_DELAY
+	udelay (CONFIG_PHY_CMD_DELAY);		/* Intel LXT971A needs this */
+#endif
 	/* wait for completion */
 	i = 0;
 	sta_reg = in32 (EMAC_STACR);

cpu/ppc4xx/miiphy_440.c

@@ -0,0 +1,259 @@
+/*-----------------------------------------------------------------------------+
+  |
+  |	  This source code has been made available to you by IBM on an AS-IS
+  |	  basis.  Anyone receiving this source is licensed under IBM
+  |	  copyrights to use it in any way he or she deems fit, including
+  |	  copying it, modifying it, compiling it, and redistributing it either
+  |	  with or without modifications.  No license under IBM patents or
+  |	  patent applications is to be implied by the copyright license.
+  |
+  |	  Any user of this software should understand that IBM cannot provide
+  |	  technical support for this software and will not be responsible for
+  |	  any consequences resulting from the use of this software.
+  |
+  |	  Any person who transfers this source code or any derivative work
+  |	  must include the IBM copyright notice, this paragraph, and the
+  |	  preceding two paragraphs in the transferred software.
+  |
+  |	  COPYRIGHT   I B M   CORPORATION 1995
+  |	  LICENSED MATERIAL  -	PROGRAM PROPERTY OF I B M
+  +-----------------------------------------------------------------------------*/
+/*-----------------------------------------------------------------------------+
+  |
+  |  File Name:	 miiphy.c
+  |
+  |  Function:	 This module has utilities for accessing the MII PHY through
+  |	       the EMAC3 macro.
+  |
+  |  Author:	 Mark Wisner
+  |
+  |  Change Activity-
+  |
+  |  Date	 Description of Change					     BY
+  |  ---------	 ---------------------					     ---
+  |  05-May-99	 Created						     MKW
+  |  01-Jul-99	 Changed clock setting of sta_reg from 66Mhz to 50Mhz to
+  |		 better match OPB speed. Also modified delay times.	     JWB
+  |  29-Jul-99	 Added Full duplex support				     MKW
+  |  24-Aug-99	 Removed printf from dp83843_duplex()			     JWB
+  |  19-Jul-00	 Ported to esd cpci405					     sr
+  |  23-Dec-03	 Ported from miiphy.c to 440GX Travis Sawyer		     TBS
+  |		 <travis.sawyer@sandburst.com>
+  |
+  +-----------------------------------------------------------------------------*/
+
+#include <common.h>
+#include <asm/processor.h>
+#include <ppc_asm.tmpl>
+#include <commproc.h>
+#include <440gx_enet.h>
+#include <405_mal.h>
+#include <miiphy.h>
+
+#if defined(CONFIG_440) && defined(CONFIG_NET_MULTI)
+
+
+/***********************************************************/
+/* Dump out to the screen PHY regs			   */
+/***********************************************************/
+
+void miiphy_dump (unsigned char addr)
+{
+	unsigned long i;
+	unsigned short data;
+
+
+	for (i = 0; i < 0x1A; i++) {
+		if (miiphy_read (addr, i, &data)) {
+			printf ("read error for reg %lx\n", i);
+			return;
+		}
+		printf ("Phy reg %lx ==> %4x\n", i, data);
+
+		/* jump to the next set of regs */
+		if (i == 0x07)
+			i = 0x0f;
+
+	}			/* end for loop */
+}				/* end dump */
+
+
+/***********************************************************/
+/* (Re)start autonegotiation				   */
+/***********************************************************/
+int phy_setup_aneg (unsigned char addr)
+{
+	unsigned short ctl, adv;
+
+	/* Setup standard advertise */
+	miiphy_read (addr, PHY_ANAR, &adv);
+	adv |= (PHY_ANLPAR_ACK | PHY_ANLPAR_RF | PHY_ANLPAR_T4 |
+		PHY_ANLPAR_TXFD | PHY_ANLPAR_TX | PHY_ANLPAR_10FD |
+		PHY_ANLPAR_10);
+	miiphy_write (addr, PHY_ANAR, adv);
+
+	/* Start/Restart aneg */
+	miiphy_read (addr, PHY_BMCR, &ctl);
+	ctl |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
+	miiphy_write (addr, PHY_BMCR, ctl);
+
+	return 0;
+}
+
+
+/***********************************************************/
+/* read a phy reg and return the value with a rc	   */
+/***********************************************************/
+unsigned int miiphy_getemac_offset (void)
+{
+	unsigned long zmii;
+	unsigned long eoffset;
+
+	/* Need to find out which mdi port we're using */
+	zmii = in32 (ZMII_FER);
+
+	if (zmii & (ZMII_FER_MDI << ZMII_FER_V (0))) {
+		/* using port 0 */
+		eoffset = 0;
+	} else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (1))) {
+		/* using port 1 */
+		eoffset = 0x100;
+	} else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (2))) {
+		/* using port 2 */
+		eoffset = 0x400;
+	} else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (3))) {
+		/* using port 3 */
+		eoffset = 0x600;
+	} else {
+		/* None of the mdi ports are enabled! */
+		/* enable port 0 */
+		zmii |= ZMII_FER_MDI << ZMII_FER_V (0);
+		out32 (ZMII_FER, zmii);
+		eoffset = 0;
+		/* need to soft reset port 0 */
+		zmii = in32 (EMAC_M0);
+		zmii |= EMAC_M0_SRST;
+		out32 (EMAC_M0, zmii);
+	}
+
+	return (eoffset);
+
+}
+
+
+int miiphy_read (unsigned char addr, unsigned char reg, unsigned short *value)
+{
+	unsigned long sta_reg;	/* STA scratch area */
+	unsigned long i;
+	unsigned long emac_reg;
+
+
+	emac_reg = miiphy_getemac_offset ();
+	/* see if it is ready for 1000 nsec */
+	i = 0;
+
+	/* see if it is ready for  sec */
+	while ((in32 (EMAC_STACR + emac_reg) & EMAC_STACR_OC) == 0) {
+		udelay (7);
+		if (i > 5) {
+#if 0
+			printf ("read err 1\n");
+#endif
+			return -1;
+		}
+		i++;
+	}
+	sta_reg = reg;		/* reg address */
+	/* set clock (50Mhz) and read flags */
+#if defined(CONFIG_440_GX)
+	sta_reg |= EMAC_STACR_READ;
+#else
+	sta_reg = (sta_reg | EMAC_STACR_READ) & ~EMAC_STACR_CLK_100MHZ;
+#endif
+
+#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440_GX)
+	sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ;
+#endif
+	sta_reg = sta_reg | (addr << 5);	/* Phy address */
+
+	out32 (EMAC_STACR + emac_reg, sta_reg);
+#if 0				/* test-only */
+	printf ("a2: write: EMAC_STACR=0x%0x\n", sta_reg);	/* test-only */
+#endif
+
+	sta_reg = in32 (EMAC_STACR + emac_reg);
+	i = 0;
+	while ((sta_reg & EMAC_STACR_OC) == 0) {
+		udelay (7);
+		if (i > 5) {
+			return -1;
+		}
+		i++;
+		sta_reg = in32 (EMAC_STACR + emac_reg);
+	}
+	if ((sta_reg & EMAC_STACR_PHYE) != 0) {
+		return -1;
+	}
+
+	*value = *(short *) (&sta_reg);
+	return 0;
+
+
+}				/* phy_read */
+
+
+/***********************************************************/
+/* write a phy reg and return the value with a rc	    */
+/***********************************************************/
+
+int miiphy_write (unsigned char addr, unsigned char reg, unsigned short value)
+{
+	unsigned long sta_reg;	/* STA scratch area */
+	unsigned long i;
+	unsigned long emac_reg;
+
+	emac_reg = miiphy_getemac_offset ();
+	/* see if it is ready for 1000 nsec */
+	i = 0;
+
+	while ((in32 (EMAC_STACR + emac_reg) & EMAC_STACR_OC) == 0) {
+		if (i > 5)
+			return -1;
+		udelay (7);
+		i++;
+	}
+	sta_reg = 0;
+	sta_reg = reg;		/* reg address */
+	/* set clock (50Mhz) and read flags */
+#if defined(CONFIG_440_GX)
+	sta_reg |= EMAC_STACR_WRITE;
+#else
+	sta_reg = (sta_reg | EMAC_STACR_WRITE) & ~EMAC_STACR_CLK_100MHZ;
+#endif
+
+#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440_GX)
+	sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ;	/* Set clock frequency (PLB freq. dependend) */
+#endif
+	sta_reg = sta_reg | ((unsigned long) addr << 5);	/* Phy address */
+	memcpy (&sta_reg, &value, 2);	/* put in data */
+
+	out32 (EMAC_STACR + emac_reg, sta_reg);
+
+	/* wait for completion */
+	i = 0;
+	sta_reg = in32 (EMAC_STACR + emac_reg);
+	while ((sta_reg & EMAC_STACR_OC) == 0) {
+		udelay (7);
+		if (i > 5)
+			return -1;
+		i++;
+		sta_reg = in32 (EMAC_STACR + emac_reg);
+	}
+
+	if ((sta_reg & EMAC_STACR_PHYE) != 0)
+		return -1;
+	return 0;
+
+}				/* phy_write */
+
+#endif /* CONFIG_405GP */

cpu/ppc4xx/serial.c

@@ -271,9 +271,15 @@ int serial_tstc ()
 #if defined(CONFIG_440)
 #define UART0_BASE  CFG_PERIPHERAL_BASE + 0x00000200
 #define UART1_BASE  CFG_PERIPHERAL_BASE + 0x00000300
+#if defined(CONFIG_440_GX)
+#define CR0_MASK        0xdfffffff
+#define CR0_EXTCLK_ENA  0x00800000
+#define CR0_UDIV_POS    0
+#else
 #define CR0_MASK        0x3fff0000
 #define CR0_EXTCLK_ENA  0x00600000
 #define CR0_UDIV_POS    16
+#endif /* CONFIG_440_GX */
 #elif defined(CONFIG_405EP)
 #define UART0_BASE      0xef600300
 #define UART1_BASE      0xef600400
@@ -295,9 +301,17 @@ int serial_tstc ()
 #if defined(CONFIG_UART1_CONSOLE)
 #define ACTING_UART0_BASE	UART1_BASE
 #define ACTING_UART1_BASE	UART0_BASE
+#if defined(CONFIG_440_GX)
+#define UART0_SDR           sdr_uart1
+#define UART1_SDR           sdr_uart0
+#endif /* CONFIG_440_GX */
 #else
 #define ACTING_UART0_BASE	UART0_BASE
 #define ACTING_UART1_BASE	UART1_BASE
+#if defined(CONFIG_440_GX)
+#define UART0_SDR           sdr_uart0
+#define UART1_SDR           sdr_uart1
+#endif /* CONFIG_440_GX */
 #endif
 
 #if defined(CONFIG_405EP) && defined(CFG_EXT_SERIAL_CLOCK)
@@ -416,7 +430,12 @@ int serial_init (void)
 	unsigned long tmp;
 #endif
 
+#if defined(CONFIG_440_GX)
+	mfsdr(UART0_SDR,reg);
+	reg &= ~CR0_MASK;
+#else
 	reg = mfdcr(cntrl0) & ~CR0_MASK;
+#endif /* CONFIG_440_GX */
 #ifdef CFG_EXT_SERIAL_CLOCK
 	reg |= CR0_EXTCLK_ENA;
 	udiv = 1;
@@ -430,9 +449,13 @@ int serial_init (void)
 	serial_divs (gd->baudrate, &udiv, &bdiv);
 #endif
 
+#if defined(CONFIG_440_GX)
+	reg |= udiv << CR0_UDIV_POS;	/* set the UART divisor */
+	mtsdr (UART0_SDR,reg);
+#else
 	reg |= (udiv - 1) << CR0_UDIV_POS;	/* set the UART divisor */
 	mtdcr (cntrl0, reg);
-
+#endif
 	out8 (ACTING_UART0_BASE + UART_LCR, 0x80);	/* set DLAB bit */
 	out8 (ACTING_UART0_BASE + UART_DLL, bdiv);	/* set baudrate divisor */
 	out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */

cpu/ppc4xx/speed.c

@@ -206,6 +206,7 @@ ulong get_PCI_freq (void)
 
 
 #elif defined(CONFIG_440)
+#if !defined(CONFIG_440_GX)
 void get_sys_info (sys_info_t * sysInfo)
 {
 	unsigned long strp0;
@@ -237,6 +238,58 @@ void get_sys_info (sys_info_t * sysInfo)
 	sysInfo->freqEPB = sysInfo->freqOPB/sysInfo->pllExtBusDiv;
 
 }
+#else
+void get_sys_info (sys_info_t * sysInfo)
+{
+	unsigned long strp0;
+	unsigned long strp1;
+	unsigned long temp;
+	unsigned long temp1;
+	unsigned long lfdiv;
+	unsigned long m;
+
+
+	/* Extract configured divisors */
+	mfsdr( sdr_sdstp0,strp0 );
+	mfsdr( sdr_sdstp1,strp1 );
+
+	temp = ((strp0 & PLLSYS0_FWD_DIV_A_MASK) >> 8);
+	sysInfo->pllFwdDivA = temp ? temp : 16 ;
+	temp = ((strp0 & PLLSYS0_FWD_DIV_B_MASK) >> 5);
+	sysInfo->pllFwdDivB = temp ? temp: 8 ;
+	temp = (strp0 & PLLSYS0_FB_DIV_MASK) >> 12;
+	sysInfo->pllFbkDiv = temp ? temp : 32;
+	temp = (strp0 & PLLSYS0_OPB_DIV_MASK);
+	sysInfo->pllOpbDiv = temp ? temp : 4;
+	temp = (strp1 & PLLSYS1_PERCLK_DIV_MASK) >> 24;
+	sysInfo->pllExtBusDiv = temp ? temp : 4;
+
+	/* Calculate 'M' based on feedback source */
+	temp = (strp0 & PLLSYS0_SEL_MASK) >> 27;
+	temp1 = (strp1 & PLLSYS1_LF_DIV_MASK) >> 26;
+	lfdiv = temp1 ? temp1 : 64;
+	if (temp == 0) { /* PLL output */
+		/* Figure which pll to use */
+		temp = (strp0 & PLLSYS0_SRC_MASK) >> 30;
+		if (!temp)
+			m = sysInfo->pllFbkDiv * lfdiv * sysInfo->pllFwdDivA;
+		else
+			m = sysInfo->pllFbkDiv * lfdiv * sysInfo->pllFwdDivB;
+	}
+	else if (temp == 1) /* CPU output */
+		m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivA;
+	else /* PerClk */
+		m = sysInfo->pllExtBusDiv * sysInfo->pllOpbDiv * sysInfo->pllFwdDivB;
+
+	/* Now calculate the individual clocks */
+	sysInfo->freqVCOMhz = (m * CONFIG_SYS_CLK_FREQ) + (m>>1);
+	sysInfo->freqProcessor = sysInfo->freqVCOMhz/sysInfo->pllFwdDivA;
+	sysInfo->freqPLB = sysInfo->freqVCOMhz/sysInfo->pllFwdDivB;
+	sysInfo->freqOPB = sysInfo->freqPLB/sysInfo->pllOpbDiv;
+	sysInfo->freqEPB = sysInfo->freqOPB/sysInfo->pllExtBusDiv;
+
+}
+#endif
 
 ulong get_OPB_freq (void)
 {

cpu/ppc4xx/start.S

@@ -166,7 +166,12 @@ _start_440:
 	mtspr	srr1,r0
 	mtspr	csrr0,r0
 	mtspr	csrr1,r0
-
+#if defined (CONFIG_440_GX) /* NOTE: 440GX adds machine check status regs */
+	mtspr   mcsrr0,r0
+	mtspr   mcsrr1,r0
+	mfspr   r1, mcsr
+	mtspr   mcsr,r1
+#endif
 	/*----------------------------------------------------------------*/
 	/* Initialize debug */
 	/*----------------------------------------------------------------*/
@@ -335,9 +340,23 @@ _start:
 	mtspr	tcr,r0			/* disable all */
 	mtspr	esr,r0			/* clear exception syndrome register */
 	mtxer	r0			/* clear integer exception register */
+#if !defined(CONFIG_440_GX)
 	lis	r1,0x0002		/* set CE bit (Critical Exceptions) */
 	ori	r1,r1,0x1000		/* set ME bit (Machine Exceptions) */
 	mtmsr	r1			/* change MSR */
+#else
+	bl	__440gx_msr_set
+	b	__440gx_msr_continue
+
+__440gx_msr_set:
+	lis 	r1, 0x0002		/* set CE bit (Critical Exceptions) */
+	ori 	r1,r1,0x1000	/* set ME bit (Machine Exceptions) */
+	mtspr	srr1,r1
+	mflr	r1
+	mtspr	srr0,r1
+	rfi
+__440gx_msr_continue:
+#endif
 
 	/*----------------------------------------------------------------*/
 	/* Debug setup -- some (not very good) ice's need an event*/
@@ -358,6 +377,9 @@ _start:
 	/* Setup the internal SRAM */
 	/*----------------------------------------------------------------*/
 	li	r0,0
+#if defined (CONFIG_440_GX)
+	mtdcr   l2_cache_cfg,r0		/* Ensure L2 Cache is off */
+#endif
 	mtdcr	isram0_sb1cr,r0		/* Disable bank 1 */
 
 	li	r2,0x7fff
@@ -370,8 +392,22 @@ _start:
 	mtdcr	isram0_pmeg,r1
 
 	lis	r1,0x8000		/* BAS = 8000_0000 */
+#if defined(CONFIG_440_GX)
+	ori	r1,r1,0x0980		/* first 64k */
+	mtdcr   isram0_sb0cr,r1
+	lis	r1,0x8001
+	ori	r1,r1,0x0980		/* second 64k */
+	mtdcr   isram0_sb1cr,r1
+	lis	r1, 0x8002
+	ori	r1,r1, 0x0980		/* third 64k */
+	mtdcr   isram0_sb2cr,r1
+	lis	r1, 0x8003
+	ori	r1,r1, 0x0980		/* fourth 64k */
+	mtdcr   isram0_sb3cr,r1
+#else
 	ori	r1,r1,0x0380		/* 8k rw */
 	mtdcr	isram0_sb0cr,r1
+#endif
 
 	/*----------------------------------------------------------------*/
 	/* Setup the stack in internal SRAM */
@@ -921,7 +957,12 @@ invalidate_icache:
 invalidate_dcache:
 	addi	r6,0,0x0000		/* clear GPR 6 */
 	/* Do loop for # of dcache congruence classes. */
+#if defined(CONFIG_440_GX)
+	lis     r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha	/* TBS for large sized cache */
+	ori     r7, r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l
+#else
 	addi	r7,r0, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)
+#endif
 					/* NOTE: dccci invalidates both */
 	mtctr	r7			/* ways in the D cache */
 ..dcloop:
@@ -942,8 +983,15 @@ flush_dcache:
 	mtdccr	r10
 
 	/* do loop for # of congruence classes. */
+#if defined(CONFIG_440_GX)
+	lis     r10,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha	/* TBS: for large cache sizes */
+	ori     r10,r10,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l
+	lis     r11,(CFG_DCACHE_SIZE / 2)@ha /* D cache set size - 2 way sets */
+	ori     r11,r11,(CFG_DCACHE_SIZE / 2)@l /* D cache set size - 2 way sets */
+#else
 	addi	r10,r0,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)
 	addi	r11,r0,(CFG_DCACHE_SIZE / 2) /* D cache set size - 2 way sets */
+#endif
 	mtctr	r10
 	addi	r10,r0,(0xE000-0x10000)	/* start at 0xFFFFE000 */
 	add	r11,r10,r11		/* add to get to other side of cache line */

cpu/pxa/cpu.c

@@ -42,7 +42,7 @@ int cpu_init (void)
 #ifdef CONFIG_USE_IRQ
 	DECLARE_GLOBAL_DATA_PTR;
 
-	IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_LEN - 4;
+	IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
 	FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
 #endif
 	return 0;

cpu/pxa/start.S

@@ -69,27 +69,15 @@ _armboot_start:
 	.word _start
 
 /*
- * Note: _armboot_end_data and _armboot_end are defined
- * by the (board-dependent) linker script.
- * _armboot_end_data is the first usable FLASH address after armboot
- */
-.globl _armboot_end_data
-_armboot_end_data:
-	.word armboot_end_data
-.globl _armboot_end
-_armboot_end:
-	.word armboot_end
-
-/*
- * This is defined in the board specific linker script
+ * These are defined in the board-specific linker script.
  */
 .globl _bss_start
 _bss_start:
-	.word bss_start
+	.word __bss_start
 
 .globl _bss_end
 _bss_end:
-	.word bss_end
+	.word _end
 
 #ifdef CONFIG_USE_IRQ
 /* IRQ stack memory (calculated at run-time) */
@@ -131,7 +119,7 @@ relocate:				/* relocate U-Boot to RAM	    */
 	beq     stack_setup
 
 	ldr	r2, _armboot_start
-	ldr	r3, _armboot_end
+	ldr	r3, _bss_start
 	sub	r2, r3, r2		/* r2 <- size of armboot            */
 	add	r2, r0, r2		/* r2 <- source end address         */
 
@@ -152,7 +140,6 @@ stack_setup:
 	sub	sp, r0, #12		/* leave 3 words for abort-stack    */
 
 clear_bss:
-
 	ldr	r0, _bss_start		/* find start of bss segment        */
 	add	r0, r0, #4		/* start at first byte of bss       */
 	ldr	r1, _bss_end		/* stop here                        */
@@ -163,7 +150,6 @@ clbss_l:str	r2, [r0]		/* clear loop...                    */
 	cmp	r0, r1
 	bne	clbss_l
 
-
 	ldr	pc, _start_armboot
 
 _start_armboot: .word start_armboot
@@ -303,9 +289,9 @@ setspeed_done:
 	stmia	sp, {r0 - r12}			/* Calling r0-r12	    */
 	add	r8, sp, #S_PC
 
-	ldr	r2, _armboot_end
-	add	r2, r2, #CONFIG_STACKSIZE
-	sub	r2, r2, #8
+	ldr	r2, _armboot_start
+	sub	r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
+	sub	r2, r2, #(CFG_GBL_DATA_SIZE+8)  @ set base 2 words into abort stack
 	ldmia	r2, {r2 - r4}			/* get pc, cpsr, old_r0	    */
 	add	r0, sp, #S_FRAME_SIZE		/* restore sp_SVC	    */
 
@@ -340,9 +326,9 @@ setspeed_done:
 	.endm
 
 	.macro get_bad_stack
-	ldr	r13, _armboot_end		@ setup our mode stack
-	add	r13, r13, #CONFIG_STACKSIZE	@ resides at top of normal stack
-	sub	r13, r13, #8
+	ldr	r13, _armboot_start		@ setup our mode stack
+	sub	r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
+	sub	r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
 
 	str	lr, [r13]			@ save caller lr / spsr
 	mrs	lr, spsr

cpu/sa1100/cpu.c

@@ -41,7 +41,7 @@ int cpu_init (void)
 #ifdef CONFIG_USE_IRQ
 	DECLARE_GLOBAL_DATA_PTR;
 
-	IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_LEN - 4;
+	IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
 	FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
 #endif
 	return 0;

cpu/sa1100/start.S

@@ -81,16 +81,15 @@ _armboot_start:
 	.word _start
 
 /*
- * Note: _armboot_end_data and _armboot_end are defined
- * by the (board-dependent) linker script.
- * _armboot_end_data is the first usable FLASH address after armboot
+ * These are defined in the board-specific linker script.
  */
-.globl _armboot_end_data
-_armboot_end_data:
-	.word armboot_end_data
-.globl _armboot_end
-_armboot_end:
-	.word armboot_end
+.globl _bss_start
+_bss_start:
+	.word __bss_start
+
+.globl _bss_end
+_bss_end:
+	.word _end
 
 #ifdef CONFIG_USE_IRQ
 /* IRQ stack memory (calculated at run-time) */
@@ -133,7 +132,7 @@ relocate:				/* relocate U-Boot to RAM	    */
 	beq     stack_setup
 
 	ldr	r2, _armboot_start
-	ldr	r3, _armboot_end
+	ldr	r3, _bss_start
 	sub	r2, r3, r2		/* r2 <- size of armboot            */
 	add	r2, r0, r2		/* r2 <- source end address         */
 
@@ -153,6 +152,17 @@ stack_setup:
 #endif
 	sub	sp, r0, #12		/* leave 3 words for abort-stack    */
 
+clear_bss:
+	ldr	r0, _bss_start		/* find start of bss segment        */
+	add	r0, r0, #4		/* start at first byte of bss       */
+	ldr	r1, _bss_end		/* stop here                        */
+	mov 	r2, #0x00000000		/* clear                            */
+
+clbss_l:str	r2, [r0]		/* clear loop...                    */
+	add	r0, r0, #4
+	cmp	r0, r1
+	bne	clbss_l
+
 	ldr	pc, _start_armboot
 
 _start_armboot:	.word start_armboot
@@ -276,9 +286,9 @@ cpu_init_crit:
 	stmia	sp, {r0 - r12}			@ Calling r0-r12
 	add     r8, sp, #S_PC
 
-	ldr	r2, _armboot_end
-	add	r2, r2, #CONFIG_STACKSIZE
-	sub	r2, r2, #8
+	ldr	r2, _armboot_start
+	sub	r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
+	sub	r2, r2, #(CFG_GBL_DATA_SIZE+8)  @ set base 2 words into abort stack
 	ldmia	r2, {r2 - r4}                   @ get pc, cpsr, old_r0
 	add	r0, sp, #S_FRAME_SIZE		@ restore sp_SVC
 
@@ -309,9 +319,9 @@ cpu_init_crit:
 	.endm
 
 	.macro get_bad_stack
-	ldr	r13, _armboot_end		@ setup our mode stack
-	add	r13, r13, #CONFIG_STACKSIZE	@ resides at top of normal stack
-	sub	r13, r13, #8
+	ldr	r13, _armboot_start		@ setup our mode stack
+	sub	r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
+	sub	r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
 
 	str	lr, [r13]			@ save caller lr / spsr
 	mrs	lr, spsr

doc/README.ARM-memory-map

@@ -15,13 +15,3 @@ different parts of the (ARM) code.
 Furthermore, the startup code (cpu/<arm>/start.S) internally uses
 another variable (_TEXT_BASE) with the same content as _armboot_start.
 I agree that this mess should be cleaned up.
-
-_armboot_end_data is the end address of the initialized data section,
-and is only used in one place (board/logodl/flash.c - the reference in
-lib_arm/board.c is purely informational).
-
-_armboot_end is the end address of the BSS and is used to determine
-the address of the VFD buffer.
-
-Eliminating those should be doable, and at least the patch already
-eliminates _armboot_real_end.

doc/README.MPC866

@@ -12,6 +12,10 @@ If the "cpuclk" environment variable value is within the CPUCLK_MIN /
 CPUCLK_MAX limits, the specified value is used. Otherwise, the
 default CPU clock value is set.
 
+Please make sure you understand what you are doing, and understand
+the restrictions of your hardware (board, processor). For example,
+ethernet will stop working for CPU clock frequencies below 25 MHz.
+
 Please note that for now the new clock-handling code has been enabled
 for the TQM866M board only, even though it should be pretty much
 common for other MPC859 / MPC866 based boards also. Our intention

doc/README.dk1c20

@@ -24,7 +24,7 @@ Contents:
 
 1. Files
 =========
-	board/dk1c20/*
+	board/altera/dk1c20/*
 	include/configs/DK1C20.h
 
 2. Memory Organization
@@ -73,11 +73,7 @@ see the following:
 2. Quit nios-run and start your terminal application (e.g. start
 Hyperterminal or minicom).
 
-3. From the U-Boot command prompt, erase flash 0x40000 to 0x 5ffff:
-
-    ==> erase 1:4-5
-
-4. Download the u-boot code to RAM. When using Hyperterminal, do the
+3. Download the u-boot code to RAM. When using Hyperterminal, do the
 following:
 
    a.  From the u-boot command prompt start a binary download to SRAM:
@@ -86,6 +82,10 @@ following:
 
     b. Download u-boot.bin using kermit.
 
+4. From the U-Boot command prompt, erase flash 0x40000 to 0x5ffff:
+
+    ==> erase 1:4-5
+
 5. Copy the binary image from SRAM to flash:
 
     ==> cp.b 800000 40000 10000

doc/README.dk1c20_std32

@@ -91,10 +91,10 @@ IDE:	(TODO)
   0x02000000 ---32-----------16|15------------0-
 	       |	       :	       | \
 	       |	       :	       | |
-  SDRAM	       |	       :	       |  > CFG_NIOS_CPU_SRAM_SIZE
+  SDRAM	       |	       :	       |  > CFG_NIOS_CPU_SDRAM_SIZE
 	       |	       :	       | |   = 0x01000000
 	       |	       :	       | /
-  0x01000000 ---32-----------16|15------------0-    CFG_NIOS_CPU_SRAM_BASE
+  0x01000000 ---32-----------16|15------------0-    CFG_NIOS_CPU_SDRAM_BASE
 	       |			       |
 	       :	      gap	       :
 	       :			       :
@@ -345,6 +345,7 @@ IDE:	(TODO)
 	       |	       :	       | |
   0x00040000 --+- - - - - - - -:- - - - - - - -+-|- u-boot _start()
 	       |	       :	       | /
+  0x00000000   |- - - - - - - -:- - - - - - - -+- - u-boot environment
   0x00000000 ---8-------------4|3-------------0-
 
 

doc/README.dk1s10

@@ -0,0 +1,131 @@
+
+			 Nios Development Kit
+			   Startix Editions
+
+		    Last Update: January 28, 2004
+====================================================================
+
+This file contains information regarding U-Boot and the Altera
+Nios Development Kit, Startix Edition (DK-1S10). For general Nios
+information see doc/README.nios.
+
+Most stuff of this file was borrowed and based on README.dk1c20,
+the DK-1C20 related information file.
+
+For those interested in contributing ... see HELP WANTED section
+in doc/README.nios.
+
+Contents:
+
+	1. Files
+	2. Memory Organization
+	3. CPU Variations
+	4. Examples
+	5. Programming U-Boot into FLASH with GERMS
+
+====================================================================
+
+1. Files
+=========
+	board/altera/dk1s10/*
+	include/configs/DK1S10.h
+
+2. Memory Organization
+=======================
+
+	-The heap is placed below the monitor (U-Boot code).
+	-Global data is placed below the heap.
+	-The stack is placed below global data (&grows down).
+
+3. CPU Variations
+=================
+
+There are more than one NIOS CPU variation for the DK-1S10. U-Boot
+supports the following CPU configurations:
+
+	- Altera Standard 32 (make DK1S10_standard_32_config)
+	- Microtronix LDK 2.0 (make DK1S10_mtx_ldk_20_config)
+
+4. Examples
+============
+
+The hello_world example was never tested on DK-1S10. Neverthelse
+it should work as far as possible, because the DK-1S10 port is
+more than ninetieth percents equal to the DK-1C20 port and at
+this platform the hello_world example was already tested
+successfully (see README.dk1c20).
+
+
+5. Programming U-Boot into FLASH with GERMS
+============================================
+The current version of the DK-1S10 port with the default
+configuration settings occupies about 78 KBytes of flash.
+A minimal configuration occupies less than 60 KByte
+(network support disabled).
+
+To program U-Boot into the DK-1S10 flash using GERMS do the
+following:
+
+1. From the command line, download U-Boot using the nios-run:
+
+	$ nios-run -r u-boot.srec
+
+This takes about 45 seconds (GERMS is not very speedy here).
+After u-boot is downloaded it will be executed. You should
+see the following:
+
+    U-Boot 1.0.2 (Jan 28 2004 - 19:02:30)
+
+    CPU: Nios-32 Rev. 3.3 (0x3038)
+    Reg file size: 256 LO_LIMIT/HI_LIMIT: 2/14
+    Board: Altera Nios 1S10 Development Kit
+    In:    serial
+    Out:   serial
+    Err:   serial
+    DK1S10 >
+
+
+2. Quit nios-run and start your terminal application (e.g. start
+   Hyperterminal or minicom).
+
+3. Download the u-boot code to RAM. When using Hyperterminal, do the
+   following:
+
+   a. From the u-boot command prompt start a binary download to
+      SRAM / SDRAM:
+
+      at the Altera Standard 32 to SRAM:
+
+	==> loadb 800000
+
+      at the Microtronix LDK 2.0 to SDRAM:
+
+	==> loadb 1010000
+
+   b. Download u-boot.bin using kermit.
+
+4. From the U-Boot command prompt, erase flash:
+
+   at the Altera Standard 32 from 0x40000 to 0x5ffff:
+
+	==> erase 1:4-5
+
+   at the Microtronix LDK 2.0 from 0x8000000 to 0x81ffff:
+
+	==> erase 1:0-1
+
+5. Copy the binary image from SRAM / SDRAM to flash:
+
+   at the Altera Standard 32 to SRAM:
+
+	==> cp.b 800000 40000 $(filesize)
+
+   at the Microtronix LDK 2.0 to SDRAM:
+
+	==> cp.b 1010000 8000000 $(filesize)
+
+U-Boot will now automatically start when the board is powered on or
+reset using the Standard-32 configuration. To start U-Boot with the
+Safe-32 configuration, enter the following GERMS command:
+
+    + g 40000