* Configure PPChameleon board to use redundand environment in flash

* Configure PPChameleon board to use JFFS2 NAND support.

* Added support for JFFS2 filesystem (read-only) on top of NAND flash

CHANGELOG

@@ -1,6 +1,176 @@
 ======================================================================
-Changes for U-Boot 1.0.2:
+Changes for U-Boot 1.1.1:
 ======================================================================
+ 
+* Configure PPChameleon board to use redundand environment in flash
+
+* Configure PPChameleon board to use JFFS2 NAND support.
+
+* Added support for JFFS2 filesystem (read-only) on top of NAND flash
+
+* Patch by Rune Torgersen, 16 Apr 2004:
+  LBA48 fixes
+
+* Patches by Pantelis Antoniou, 16 Apr 2004:
+  - add support for a new version of an Intracom board and fix
+    various other things on others.
+  - add verify support to the crc32 command (define
+    CONFIG_CRC32_VERIFY to enable it)
+  - fix FEC driver for MPC8xx systems:
+    1. fix compilation problems for boards that use dynamic
+       allocation of DPRAM
+    2. shut down FEC after network transfers
+  - HUSH parser fixes:
+    1. A new test command was added. This is a simplified version of
+       the one in the bourne shell.
+    2. A new exit command was added which terminates the current
+       executing script.
+    3. Fixed handing of $? (exit code of last executed command)
+  - Fix some compile problems;
+    add "once" functionality for the netretry variable
+
+* Patch by George G. Davis, 02 Apr 2004:
+  add support for Intel Assabet board
+
+* Patch by Stephen Williams, 01 Apr 2004:
+  Add support for Picture Elements JSE board
+
+* Patch by Christian Pell, 01 Apr 2004:
+  Add CompactFlash support for PXA systems.
+
+* Patches by Pantelis Antoniou, 30 Mar 2004:
+  - add auto-complete support to the U-Boot CLI
+  - add support for NETTA and NETPHONE boards; fix NETVIA board
+  - add support for the Epson 156x series of graphical displays
+    (These displays are serial and not suitable for using a normal
+    framebuffer console on them)
+  - add infrastructure needed in order to POST any DSPs in a board
+  - improve and fix various things in the MPC8xx FEC driver:
+    1. The new 87x and 88x series of processors have two FECs,
+       and the new driver supports them both.
+    2. Another change in the 87x/88x series is support for
+       the RMII (Reduced MII) interface. However numerous
+       changes are needed to make it work since the PHYs
+       are connected to the same lines. That means that
+       you have to address them correctly over the MII
+       interface.
+    3. We now correctly match the MII/RMII interface
+       configuration to what the PHY reports.
+  - Fix problem when readingthe MII status register. Due to the
+    internal design of many PHYs you have to read the register
+    twice. The problem is more apparent in 10Mbit mode.
+  - add new mode ".jffs2s" for reading from a NAND device: it just
+    skips over bad blocks.
+  - add networking support for VLANs (802.1q), and CDP (Cisco
+    Discovery Protocol)
+  - some minor patches / cleanup
+
+* Patch by Yuli Barcohen, 28 Mar 2004:
+  - Add support for MPC8272 family including MPC8247/8248/8271/8272
+  - Add support for MPC8272ADS evaluation board (another flavour of MPC8260ADS)
+  - Change configuration method for MPC8260ADS family
+
+* add startup code to clear the BSS of standalone applications
+
+* Fix if / elif handling bug in HUSH shell
+
+======================================================================
+Changes for U-Boot 1.1.0:
+======================================================================
+
+* Patch by Mark Jonas: Remove config.tmp files only when
+  unconfiguring the board
+
+* Adapt RMU board for bigger flash memory
+
+* Patch by Klaus Heydeck, 13 Mar 2003:
+  Add support for KUP4X Board
+
+* Patch by Pavel Bartusek, 21 Mar 2004
+  Add Reiserfs support
+
+* Patch by Hinko Kocevar, 20 Mar 2004
+  - Add auto-release for SMSC LAN91c111 driver
+  - Add save/restore of PTR and PNR regs as suggested in datasheet
+
+* Patch by Stephen Williams, 19 March 2004
+  Increase speed of sector reads from SystemACE,
+  shorten poll timeout and remove a useless reset
+
+* Patch by Tolunay Orkun, 19 Mar 2004:
+  Make GigE PHY 1000Mbps Speed/Duplex detection conditional
+  (CONFIG_PHY_GIGE)
+
+* Patch by Brad Kemp, 18 Mar 2004:
+  prevent machine checks during a PCI scan
+
+* Patch by Pierre Aubert, 18 Mar 2004:
+  Fix string cleaning in IDE identification
+
+* Patch by Pierre Aubert, 18 Mar 2004:
+  - Unify video mode handling for Chips & Technologies 69000 Video
+    chip and Silicon Motion SMI 712/710/810 Video chip
+  - Add selection of the video output (CRT or LCD) via 'videoout'
+    environment variable for the Silicon Motion
+  - README update
+
+* Patch by Pierre Aubert, 18 Mar 2004:
+  include/common.h typo fix
+
+* Patches by Tolunay Orkun, 17 Mar 2004:
+  - Add support for bd->bi_iic_fast[] initialization via environment
+    variable "i2cfast" (CONFIG_I2CFAST)
+  - Add "i2cfast" u-boot environment variable support for csb272
+
+* Patch by Carl Riechers, 17 Mar 2004:
+  Ignore '\0' characters in console input for use with telnet and
+  telco pads.
+
+* Patch by Leon Kukovec, 17 Mar 2004:
+  typo fix for strswab prototype #ifdef
+
+* Patches by Thomas Viehweger, 16 Mar 2004:
+  - show PCI clock frequency on MPC8260 systems
+  - add FCC_PSMR_RMII flag for HiP7 processors
+  - in do_jffs2_fsload(), take load address from load_addr if not set
+    explicit, update load_addr otherwise
+  - replaced printf by putc/puts when no formatting is needed
+    (smaller code size, faster execution)
+
+* Patch by Phillippe Robin, 16 Mar 2004:
+  avoid dereferencing NULL pointer in lib_arm/armlinux.c
+
+* Patch by Stephen Williams, 15 Mar 2004:
+  Fix CONFIG_SERIAL_SOFTWARE_FIFO documentation
+
+* Patch by Tolunay Orkun, 15 Mar 2004:
+  Initialize bi_opbfreq to real OPB frequency via get_OPB_freq()
+
+* Patch by Travis Sawyer, 15 Mar 2004:
+  Update CREDITS & MAINTAINERS files for PPC440GX & Ocotea port
+
+* Add start-up delay to make sure power has stabilized before
+  attempting to switch on USB on SX1 board.
+
+* Patch by Josef Wagner, 18 Mar 2004:
+  - Add support for MicroSys XM250 board (PXA255)
+  - Add support for MicroSys PM828 board (MPC8280)
+  - Add support for 32 MB Flash on PM825/826
+  - new SDRAM refresh rate for PM825/PM826
+  - added support for MicroSys PM520 (MPC5200)
+  - replaced Query by Identify command in CPU86/flash.c
+    to support 28F160F3B
+
+* Fix wrap around problem with udelay() on ARM920T
+
+* Add support for Macronix flash on TRAB board
+
+* Patch by Pierre Aubert, 15 Mar 2004:
+  Fix buffer overflow in IDE identification
+
+* Fix power-off of LCD for out-of-band temperatures on LWMON board
+
+* Remove redundand #define in IceCube.h
 
 * Patch by Steven Scholz, 27 Feb 2004:
   - Adding get_ticks() and get_tbclk() for AT91RM9200
@@ -29,7 +199,7 @@ Changes for U-Boot 1.0.2:
 * Patch by George G. Davis, 11 Mar 2004:
   add support for ADS GraphicsClient+ board.
 
-* Patch by  Pierre Aubert, 11 Mar 2004:
+* Patch by Pierre Aubert, 11 Mar 2004:
   - add bitmap command and splash screen support in cfb console
   - add [optional] origin in the bitmap display command
 
@@ -57,7 +227,7 @@ Changes for U-Boot 1.0.2:
   Don't overwrite server IP address or boot file name
   when the boot server does not return values
 
-* Patch by listmember@orkun.us, 5 Mar 2004:
+* Patch by Tolunay Orkun, 5 Mar 2004:
   Removed compile time restriction on CFG_I2C_SPEED for DS1338 RTC
 
 * Patch by Tolunay Orkun, 5 Mar 2004:

CREDITS

@@ -28,16 +28,27 @@ D: ERIC Support
 
 N: Pantelis Antoniou
 E: panto@intracom.gr
-D: NETVIA board support, ARTOS support.
+D: NETVIA & NETPHONE board support, ARTOS support.
 
 N: Pierre Aubert
 E: <p.aubert@staubli.com>
 D: Support for RPXClassic board
 
+N: Yuli Barcohen
+E: yuli@arabellasw.com
+D: Unified support for Motorola MPC826xADS/MPC8272ADS/PQ2FADS boards.
+D: Support for Zephyr Engineering ZPC.1900 board.
+W: http://www.arabellasw.com
+
 N: Jerry van Baren
 E: <vanbaren@cideas.com>
 D: BedBug port to 603e core (MPC82xx). Code for enhanced memory test.
 
+N: Pavel Bartusek
+E: <pba@sysgo.com>
+D: Reiserfs support
+W: http://www.elinos.com
+
 N: Andre Beaudin
 E: <andre.beaudin@colubris.com>
 D: PCMCIA, Ethernet, TFTP
@@ -78,6 +89,10 @@ N: Magnus Damm
 E: damm@opensource.se
 D: 8xxrom
 
+N: George G. Davis
+E: gdavis@mvista.com
+D: Board ports for ADS GraphicsClient+ and Intel Assabet
+
 N: Arun Dharankar
 E: ADharankar@ATTBI.Com
 D: threads / scheduler example code
@@ -252,6 +267,10 @@ E: rof@sysgo.de
 D: Initial support for SSV-DNP1110, SMC91111 driver
 W: www.elinos.com
 
+N: Tolunay Orkun
+E: torkun@nextio.com
+D: Support for Cogent CSB272 board
+
 N: Keith Outwater
 E: keith_outwater@mvis.com
 D: Support for generic/custom MPC860T boards (GEN860T, GEN860T_SC)
@@ -284,7 +303,7 @@ D: Author of LiMon-1.4.2, which contributed some ideas
 
 N: Travis B. Sawyer
 E: travis.sawyer@sandburst.com
-D: Support for IBM PPC440GX, XES XPedite1000 440GX PrPMC board.
+D: Support for IBM PPC440GX, XES XPedite1000 440GX PrPMC board.  IBM 440gx Ref Platform (Ocotea)
 
 N: Paolo Scaffardi
 E: arsenio@tin.it

MAINTAINERS

@@ -27,6 +27,7 @@ Pantelis Antoniou <panto@intracom.gr>
 
 Yuli Barcohen <yuli@arabellasw.com>
 
+	MPC8260ADS		MPC826x/MPC827x/MPC8280
 	ZPC1900			MPC8265
 
 Jerry Van Baren <gerald.vanbaren@smiths-aerospace.com>
@@ -146,6 +147,7 @@ Bill Hargen <Bill_Hargen@Jabil.com>
 Klaus Heydeck <heydeck@kieback-peter.de>
 
 	KUP4K			MPC855
+	KUP4X			MPC859
 
 Murray Jensen <Murray.Jensen@cmst.csiro.au>
 
@@ -230,6 +232,11 @@ Stefan Roese <stefan.roese@esd-electronics.com>
 	PMC405			PPC405GP
 	VOH405			PPC405EP
 
+Travis Sawyer (travis.sawyer@sandburst.com>
+
+	XPEDITE1K		PPC440GX
+	OCOTEA			PPC440GX
+
 Peter De Schrijver <p2@mind.be>
 
 	ML2			PPC4xx
@@ -279,7 +286,6 @@ Unknown / orphaned boards:
 
 	MOUSSE			MPC824x
 
-	MPC8260ADS		MPC8260
 	RPXsuper		MPC8260
 	rsdproto		MPC8260
 
@@ -293,6 +299,11 @@ Unknown / orphaned boards:
 #	Board			CPU					#
 #########################################################################
 
+George G. Davis <gdavis@mvista.com>
+
+	assabet			SA1100
+	gcplus			SA1100
+
 Thomas Elste <info@elste.org>
 
 	modnet50		ARM720T (NET+50)

MAKEALL

@@ -25,7 +25,7 @@ LIST_5xx="	\
 #########################################################################
 
 LIST_5xxx="	\
-	IceCube_5100	IceCube_5200	EVAL5200	\
+	IceCube_5100	IceCube_5200	EVAL5200	PM520		\
 "
 
 #########################################################################
@@ -40,15 +40,15 @@ LIST_8xx="	\
 	GEN860T_SC	GENIETV		GTH		hermes		\
 	IAD210		ICU862_100MHz	IP860		IVML24		\
 	IVML24_128	IVML24_256	IVMS8		IVMS8_128	\
-	IVMS8_256	KUP4K		LANTEC		lwmon		\
-	MBX		MBX860T		MHPC		MPC86xADS	\
-	MVS1		NETVIA		NETVIA_V2	NX823		\
-	pcu_e		QS823		QS850		QS860T		\
-	R360MPI		RBC823		rmu		RPXClassic	\
-	RPXlite		RRvision	SM850		SPD823TS	\
-	svm_sc8xx	SXNI855T	TOP860		TQM823L		\
-	TQM823L_LCD	TQM850L		TQM855L		TQM860L		\
-	v37								\
+	IVMS8_256	KUP4K		KUP4X		LANTEC		\
+	lwmon		MBX		MBX860T		MHPC		\
+	MPC86xADS	MVS1		NETVIA		NETVIA_V2	\
+	NX823		pcu_e		QS823		QS850		\
+	QS860T		R360MPI		RBC823		rmu		\
+	RPXClassic	RPXlite		RRvision	SM850		\
+	SPD823TS	svm_sc8xx	SXNI855T	TOP860		\
+	TQM823L		TQM823L_LCD	TQM850L		TQM855L		\
+	TQM860L		v37		NETTA		NETPHONE	\
 "
 
 #########################################################################
@@ -60,11 +60,12 @@ LIST_4xx="	\
 	CANBT		CPCI405		CPCI4052	CPCI405AB	\
 	CPCI440		CPCIISER4	CRAYL1		csb272		\
 	DASA_SIM	DP405		DU405		EBONY		\
-	ERIC		EXBITGEN	HUB405		MIP405		\
-	MIP405T		ML2		ml300		OCOTEA		\
-	OCRTC		ORSG		PCI405		PIP405		\
-	PLU405		PMC405		PPChameleonEVB	VOH405		\
-	W7OLMC		W7OLMG		WALNUT405	XPEDITE1K	\
+	ERIC		EXBITGEN	HUB405		JSE		\
+	MIP405		MIP405T		ML2		ml300		\
+	OCOTEA		OCRTC		ORSG		PCI405		\
+	PIP405		PLU405		PMC405		PPChameleonEVB	\
+	VOH405		W7OLMC		W7OLMG		WALNUT405	\
+	XPEDITE1K							\
 "
 
 #########################################################################
@@ -85,9 +86,10 @@ LIST_824x="	\
 LIST_8260="	\
 	atc		cogent_mpc8260	CPU86		ep8260		\
 	gw8260		hymod		IPHASE4539	MPC8260ADS	\
-	MPC8266ADS	PM826		ppmc8260	RPXsuper	\
-	rsdproto	sacsng		sbc8260		SCM		\
-	TQM8260_AC	TQM8260_AD	TQM8260_AE	ZPC1900		\
+	MPC8266ADS	MPC8272ADS	PM826		PM828		\
+	ppmc8260	PQ2FADS		RPXsuper	rsdproto	\
+	sacsng		sbc8260		SCM		TQM8260_AC	\
+	TQM8260_AD	TQM8260_AE	ZPC1900				\
 "
 
 #########################################################################
@@ -122,7 +124,7 @@ LIST_ppc="${LIST_5xx}  ${LIST_5xxx} \
 ## StrongARM Systems
 #########################################################################
 
-LIST_SA="dnp1110 gcplus lart shannon"
+LIST_SA="assabet dnp1110 gcplus lart shannon"
 
 #########################################################################
 ## ARM7 Systems
@@ -145,7 +147,7 @@ LIST_ARM9="	\
 ## Xscale Systems
 #########################################################################
 
-LIST_pxa="cradle csb226 innokom lubbock wepep250"
+LIST_pxa="cradle csb226 innokom lubbock wepep250 xm250"
 
 LIST_ixp="ixdp425"
 

Makefile

@@ -99,7 +99,8 @@ LIBS  = lib_generic/libgeneric.a
 LIBS += board/$(BOARDDIR)/lib$(BOARD).a
 LIBS += cpu/$(CPU)/lib$(CPU).a
 LIBS += lib_$(ARCH)/lib$(ARCH).a
-LIBS += fs/cramfs/libcramfs.a fs/fat/libfat.a fs/fdos/libfdos.a fs/jffs2/libjffs2.a
+LIBS += fs/cramfs/libcramfs.a fs/fat/libfat.a fs/fdos/libfdos.a fs/jffs2/libjffs2.a \
+	fs/reiserfs/libreiserfs.a
 LIBS += net/libnet.a
 LIBS += disk/libdisk.a
 LIBS += rtc/librtc.a
@@ -165,6 +166,9 @@ depend dep:
 
 tags:
 		ctags -w `find $(SUBDIRS) include \
+				lib_generic board/$(BOARDDIR) cpu/$(CPU) lib_$(ARCH) \
+				fs/cramfs fs/fat fs/fdos fs/jffs2 \
+				net disk rtc dtt drivers drivers/sk98lin common \
 			\( -name CVS -prune \) -o \( -name '*.[ch]' -print \)`
 
 etags:
@@ -186,7 +190,7 @@ endif
 #########################################################################
 
 unconfig:
-	rm -f include/config.h include/config.mk
+	@rm -f include/config.h include/config.mk board/*/config.tmp
 
 #========================================================================
 # PowerPC
@@ -199,7 +203,7 @@ unconfig:
 cmi_mpc5xx_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc5xx cmi
 
-PATI_config:unconfig
+PATI_config:		unconfig
 	@./mkconfig $(@:_config=) ppc mpc5xx pati mpl
 
 #########################################################################
@@ -216,13 +220,17 @@ icecube_5200_config		\
 IceCube_5200_config		\
 IceCube_5100_config:		unconfig
 	@ >include/config.h
-	@[ -z "$(findstring LOWBOOT,$@)" ] || \
-		{ echo "TEXT_BASE = 0xFF000000" >board/icecube/config.tmp ; \
+	@[ -z "$(findstring LOWBOOT_,$@)" ] || \
+		{ if [ "$(findstring DDR,$@)" ] ; \
+			then echo "TEXT_BASE = 0xFF800000" >board/icecube/config.tmp ; \
+			else echo "TEXT_BASE = 0xFF000000" >board/icecube/config.tmp ; \
+		  fi ; \
 		  echo "... with LOWBOOT configuration" ; \
 		}
 	@[ -z "$(findstring LOWBOOT08,$@)" ] || \
 		{ echo "TEXT_BASE = 0xFF800000" >board/icecube/config.tmp ; \
 		  echo "... with 8 MB flash only" ; \
+		  echo "... with LOWBOOT configuration" ; \
 		}
 	@[ -z "$(findstring DDR,$@)" ] || \
 		{ echo "#define CONFIG_MPC5200_DDR"	>>include/config.h ; \
@@ -244,6 +252,9 @@ TOP5200_config:	unconfig
 	@ echo "#define CONFIG_$(@:_config=) 1"	>include/config.h
 	@./mkconfig -a TOP5200 ppc mpc5xxx top5200 emk
 
+PM520_config:	unconfig
+	@./mkconfig $(@:_config=) ppc mpc5xxx pm520
+
 #########################################################################
 ## MPC8xx Systems
 #########################################################################
@@ -354,7 +365,10 @@ IVMS8_config:	unconfig
 	@./mkconfig -a IVMS8 ppc mpc8xx ivm
 
 KUP4K_config	:	unconfig
-	@./mkconfig $(@:_config=) ppc mpc8xx kup4k
+	@./mkconfig $(@:_config=) ppc mpc8xx kup4k kup
+
+KUP4X_config    :       unconfig
+	@./mkconfig $(@:_config=) ppc mpc8xx kup4x kup
 
 LANTEC_config	:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx lantec
@@ -387,6 +401,32 @@ NETVIA_config:		unconfig
 		 }
 	@./mkconfig -a $(call xtract_NETVIA,$@) ppc mpc8xx netvia
 
+xtract_NETPHONE = $(subst _V2,,$(subst _config,,$1))
+
+NETPHONE_V2_config \
+NETPHONE_config:	unconfig
+	@ >include/config.h
+	@[ -z "$(findstring NETPHONE_config,$@)" ] || \
+		 { echo "#define CONFIG_NETPHONE_VERSION 1" >>include/config.h ; \
+		 }
+	@[ -z "$(findstring NETPHONE_V2_config,$@)" ] || \
+		 { echo "#define CONFIG_NETPHONE_VERSION 2" >>include/config.h ; \
+		 }
+	@./mkconfig -a $(call xtract_NETPHONE,$@) ppc mpc8xx netphone
+
+xtract_NETTA = $(subst _ISDN,,$(subst _config,,$1))
+
+NETTA_ISDN_config \
+NETTA_config:		unconfig
+	@ >include/config.h
+	@[ -z "$(findstring NETTA_config,$@)" ] || \
+		 { echo "#undef CONFIG_NETTA_ISDN" >>include/config.h ; \
+		 }
+	@[ -z "$(findstring NETTA_ISDN_config,$@)" ] || \
+		 { echo "#define CONFIG_NETTA_ISDN 1" >>include/config.h ; \
+		 }
+	@./mkconfig -a $(call xtract_NETTA,$@) ppc mpc8xx netta
+
 NX823_config:		unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx nx823
 
@@ -539,7 +579,7 @@ AR405_config:	unconfig
 ASH405_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx ash405 esd
 
-BUBINGA405EP_config:unconfig
+BUBINGA405EP_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx bubinga405ep
 
 CANBT_config:	unconfig
@@ -557,7 +597,7 @@ CPCI440_config:	unconfig
 CPCIISER4_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx cpciiser4 esd
 
-CRAYL1_config:unconfig
+CRAYL1_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx L1 cray
 
 csb272_config:	unconfig
@@ -572,33 +612,36 @@ DP405_config:	unconfig
 DU405_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx du405 esd
 
-EBONY_config:unconfig
+EBONY_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx ebony
 
-ERIC_config:unconfig
+ERIC_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx eric
 
-EXBITGEN_config:unconfig
+EXBITGEN_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx exbitgen
 
 HUB405_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx hub405 esd
 
-MIP405_config:unconfig
+JSE_config:	unconfig
+	@./mkconfig $(@:_config=) ppc ppc4xx jse
+
+MIP405_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx mip405 mpl
 
-MIP405T_config:unconfig
+MIP405T_config:	unconfig
 	@echo "#define CONFIG_MIP405T" >include/config.h
 	@echo "Enable subset config for MIP405T"
 	@./mkconfig -a MIP405 ppc ppc4xx mip405 mpl
 
-ML2_config:unconfig
+ML2_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx ml2
 
-ml300_config:unconfig
+ml300_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx ml300 xilinx
 
-OCOTEA_config:unconfig
+OCOTEA_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx ocotea
 
 OCRTC_config		\
@@ -608,7 +651,7 @@ ORSG_config:	unconfig
 PCI405_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx pci405 esd
 
-PIP405_config:unconfig
+PIP405_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx pip405 mpl
 
 PLU405_config:	unconfig
@@ -643,16 +686,16 @@ W7OLMC_config	\
 W7OLMG_config: unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx w7o
 
-WALNUT405_config:unconfig
+WALNUT405_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx walnut405
 
-XPEDITE1K_config:unconfig
+XPEDITE1K_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx xpedite1k
 
 #########################################################################
 ## MPC824x Systems
 #########################################################################
-xtract_82xx = $(subst _ROMBOOT,,$(subst _L2,,$(subst _266MHz,,$(subst _300MHz,,$(subst _config,,$1)))))
+xtract_82xx = $(subst _BIGFLASH,,$(subst _ROMBOOT,,$(subst _L2,,$(subst _266MHz,,$(subst _300MHz,,$(subst _config,,$1))))))
 
 A3000_config: unconfig
 	@./mkconfig $(@:_config=) ppc mpc824x a3000
@@ -741,38 +784,77 @@ hymod_config:	unconfig
 IPHASE4539_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8260 iphase4539
 
-MPC8260ADS_config:	unconfig
-	@./mkconfig $(@:_config=) ppc mpc8260 mpc8260ads
+MPC8260ADS_config	\
+MPC8260ADS_33MHz_config	\
+MPC8260ADS_40MHz_config	\
+MPC8272ADS_config	\
+PQ2FADS_config		\
+PQ2FADS-VR_config	\
+PQ2FADS-ZU_config	\
+PQ2FADS-ZU_66MHz_config	\
+	:		unconfig
+	$(if $(findstring PQ2FADS,$@), \
+	@echo "#define CONFIG_ADSTYPE CFG_PQ2FADS" > include/config.h, \
+	@echo "#define CONFIG_ADSTYPE CFG_"$(subst MPC,,$(word 1,$(subst _, ,$@))) > include/config.h)
+	$(if $(findstring MHz,$@), \
+	@echo "#define CONFIG_8260_CLKIN" $(subst MHz,,$(word 2,$(subst _, ,$@)))"000000" >> include/config.h, \
+	$(if $(findstring VR,$@), \
+	@echo "#define CONFIG_8260_CLKIN 66000000" >> include/config.h))
+	@./mkconfig -a MPC8260ADS ppc mpc8260 mpc8260ads
 
 MPC8266ADS_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8260 mpc8266ads
 
+# PM825/PM826 default configuration:  small (= 8 MB) Flash / boot from 64-bit flash
 PM825_config	\
-PM825_ROMBOOT_config: unconfig
-	@echo "#define CONFIG_PCI"	>include/config.h
-	@./mkconfig -a PM826 ppc mpc8260 pm826
-	@cd ./include ;				\
-	if [ "$(findstring _ROMBOOT_,$@)" ] ; then \
-		echo "CONFIG_BOOT_ROM = y" >> config.mk ; \
-		echo "... booting from 8-bit flash" ; \
-	else \
-		echo "CONFIG_BOOT_ROM = n" >> config.mk ; \
-		echo "... booting from 64-bit flash" ; \
-	fi; \
-	echo "export CONFIG_BOOT_ROM" >> config.mk; \
-
+PM825_ROMBOOT_config	\
+PM825_BIGFLASH_config	\
+PM825_ROMBOOT_BIGFLASH_config	\
 PM826_config	\
-PM826_ROMBOOT_config: unconfig
-	@./mkconfig $(call xtract_82xx,$@) ppc mpc8260 pm826
-	@cd ./include ;				\
-	if [ "$(findstring _ROMBOOT_,$@)" ] ; then \
-		echo "CONFIG_BOOT_ROM = y" >> config.mk ; \
-		echo "... booting from 8-bit flash" ; \
+PM826_ROMBOOT_config	\
+PM826_BIGFLASH_config	\
+PM826_ROMBOOT_BIGFLASH_config:	unconfig
+	@if [ "$(findstring PM825_,$@)" ] ; then \
+		echo "#define CONFIG_PCI"	>include/config.h ; \
+	else \
+		>include/config.h ; \
+	fi
+	@if [ "$(findstring _ROMBOOT_,$@)" ] ; then \
+		echo "... booting from 8-bit flash" ; \
+		echo "#define CONFIG_BOOT_ROM" >>include/config.h ; \
+		echo "TEXT_BASE = 0xFF800000" >board/pm826/config.tmp ; \
+		if [ "$(findstring _BIGFLASH_,$@)" ] ; then \
+			echo "... with 32 MB Flash" ; \
+			echo "#define CONFIG_FLASH_32MB" >>include/config.h ; \
+		fi; \
 	else \
-		echo "CONFIG_BOOT_ROM = n" >> config.mk ; \
 		echo "... booting from 64-bit flash" ; \
-	fi; \
-	echo "export CONFIG_BOOT_ROM" >> config.mk; \
+		if [ "$(findstring _BIGFLASH_,$@)" ] ; then \
+			echo "... with 32 MB Flash" ; \
+			echo "#define CONFIG_FLASH_32MB" >>include/config.h ; \
+			echo "TEXT_BASE = 0x40000000" >board/pm826/config.tmp ; \
+		else \
+			echo "TEXT_BASE = 0xFF000000" >board/pm826/config.tmp ; \
+		fi; \
+	fi
+	@./mkconfig -a PM826 ppc mpc8260 pm826
+
+PM828_config	\
+PM828_PCI_config	\
+PM828_ROMBOOT_config	\
+PM828_ROMBOOT_PCI_config:	unconfig
+	@if [ -z "$(findstring _PCI_,$@)" ] ; then \
+		echo "#define CONFIG_PCI"  >>include/config.h ; \
+		echo "... with PCI enabled" ; \
+	else \
+		>include/config.h ; \
+	fi
+	@if [ "$(findstring _ROMBOOT_,$@)" ] ; then \
+		echo "... booting from 8-bit flash" ; \
+		echo "#define CONFIG_BOOT_ROM" >>include/config.h ; \
+		echo "TEXT_BASE = 0xFF800000" >board/pm826/config.tmp ; \
+	fi
+	@./mkconfig -a PM828 ppc mpc8260 pm828
 
 ppmc8260_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8260 ppmc8260
@@ -905,6 +987,9 @@ ZUMA_config:	unconfig
 ## StrongARM Systems
 #########################################################################
 
+assabet_config	:	unconfig
+	@./mkconfig $(@:_config=) arm sa1100 assabet
+
 dnp1110_config	:	unconfig
 	@./mkconfig $(@:_config=) arm sa1100 dnp1110
 
@@ -948,10 +1033,10 @@ omap1610h2_cs0boot_config \
 omap1610h2_cs3boot_config :	unconfig
 	@if [ "$(findstring _cs0boot_, $@)" ] ; then \
 		echo "#define CONFIG_CS0_BOOT" >> ./include/config.h ; \
-		echo "Configured for CS0 boot"; \
+		echo "... configured for CS0 boot"; \
 	else \
 		echo "#define CONFIG_CS3_BOOT" >> ./include/config.h ; \
-		echo "Configured for CS3 boot"; \
+		echo "... configured for CS3 boot"; \
 	fi;
 	@./mkconfig -a $(call xtract_omap1610xxx,$@) arm arm926ejs omap1610inn
 
@@ -1042,6 +1127,9 @@ logodl_config	:	unconfig
 wepep250_config	:	unconfig
 	@./mkconfig $(@:_config=) arm pxa wepep250
 
+xm250_config	:	unconfig
+	@./mkconfig $(@:_config=) arm pxa xm250
+
 #========================================================================
 # i386
 #========================================================================
@@ -1191,13 +1279,13 @@ clean:
 	rm -f examples/hello_world examples/timer \
 	      examples/eepro100_eeprom examples/sched \
 	      examples/mem_to_mem_idma2intr examples/82559_eeprom
-
 	rm -f tools/img2srec tools/mkimage tools/envcrc tools/gen_eth_addr
+	rm -f tools/mpc86x_clk
 	rm -f tools/easylogo/easylogo tools/bmp_logo
 	rm -f tools/gdb/astest tools/gdb/gdbcont tools/gdb/gdbsend
 	rm -f tools/env/fw_printenv tools/env/fw_setenv
 	rm -f board/cray/L1/bootscript.c board/cray/L1/bootscript.image
-	rm -f board/trab/trab_fkt board/*/config.tmp
+	rm -f board/trab/trab_fkt
 
 clobber:	clean
 	find . -type f \

board/assabet/Makefile

@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# 2004 (c) MontaVista Software, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= assabet.o
+SOBJS	:= setup.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################

board/assabet/assabet.c

@@ -0,0 +1,121 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * 2004 (c) MontaVista Software, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <SA-1100.h>
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Board dependent initialisation
+ */
+
+#define ECOR			0x8000
+#define ECOR_RESET		0x80
+#define ECOR_LEVEL_IRQ		0x40
+#define ECOR_WR_ATTRIB		0x04
+#define ECOR_ENABLE		0x01
+
+#define ECSR			0x8002
+#define ECSR_IOIS8		0x20
+#define ECSR_PWRDWN		0x04
+#define ECSR_INT		0x02
+#define SMC_IO_SHIFT		2
+#define NCR_0           	(*((volatile u_char *)(0x100000a0)))
+#define NCR_ENET_OSC_EN		(1<<3)
+
+static inline u8
+readb(volatile u8 * p)
+{
+	return *p;
+}
+
+static inline void
+writeb(u8 v, volatile u8 * p)
+{
+	*p = v;
+}
+
+static void
+smc_init(void)
+{
+	u8 ecor;
+	u8 ecsr;
+	volatile u8 *addr = (volatile u8 *)(0x18000000 + (1 << 25));
+
+	NCR_0 |= NCR_ENET_OSC_EN;
+	udelay(100);
+
+	ecor = readb(addr + (ECOR << SMC_IO_SHIFT)) & ~ECOR_RESET;
+	writeb(ecor | ECOR_RESET, addr + (ECOR << SMC_IO_SHIFT));
+	udelay(100);
+
+	/*
+	 * The device will ignore all writes to the enable bit while
+	 * reset is asserted, even if the reset bit is cleared in the
+	 * same write.  Must clear reset first, then enable the device.
+	 */
+	writeb(ecor, addr + (ECOR << SMC_IO_SHIFT));
+	writeb(ecor | ECOR_ENABLE, addr + (ECOR << SMC_IO_SHIFT));
+
+	/*
+	 * Set the appropriate byte/word mode.
+	 */
+	ecsr = readb(addr + (ECSR << SMC_IO_SHIFT)) & ~ECSR_IOIS8;
+	ecsr |= ECSR_IOIS8;
+	writeb(ecsr, addr + (ECSR << SMC_IO_SHIFT));
+	udelay(100);
+}
+
+static void
+neponset_init(void)
+{
+	smc_init();
+}
+
+int
+board_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_arch_number = 25;	/* Intel Assabet Board */
+	gd->bd->bi_boot_params = 0xc0000100;
+
+	neponset_init();
+
+	return 0;
+}
+
+int
+dram_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return (0);
+}

board/assabet/config.mk

@@ -0,0 +1,7 @@
+#
+# SA-1110 based Intel Assabet board
+#
+# The Intel Assabet 1 bank of 32 MiB SDRAM
+#
+
+TEXT_BASE = 0xc1f00000

board/assabet/setup.S

@@ -0,0 +1,136 @@
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
+ *		       Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
+ * 2004 (c) MontaVista Software, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include "config.h"
+#include "version.h"
+
+
+/*-----------------------------------------------------------------------
+ * Board defines:
+ */
+
+#define MDCNFG		0x00
+#define MDCAS00		0x04
+#define MDCAS01		0x08
+#define MDCAS02		0x0C
+#define MSC0		0x10
+#define MSC1		0x14
+#define MECR		0x18
+#define MDREFR		0x1C
+#define MDCAS20		0x20
+#define MDCAS21		0x24
+#define MDCAS22		0x28
+#define MSC2		0x2C
+#define SMCNFG		0x30
+
+#define ASSABET_BCR		(0x12000000)
+#define ASSABET_BCR_DB1110	(0x00a07490 | (0<<16) | (0<<17))
+#define ASSABET_SCR_nNEPONSET	(1 << 9)
+#define NEPONSET_LEDS		(0x10000010)
+
+
+/*-----------------------------------------------------------------------
+ * Setup parameters for the board:
+ */
+
+
+MEM_BASE:	.long	0xa0000000
+MEM_START:	.long	0xc0000000
+
+mdcnfg:		.long	0x72547254
+mdcas00:	.long	0xaaaaaa7f
+mdcas01:	.long	0xaaaaaaaa
+mdcas02:	.long	0xaaaaaaaa
+msc0:		.long	0x4b384370
+msc1:		.long	0x22212419
+mecr:		.long	0x994a994a
+mdrefr:		.long	0x04340327
+mdcas20:	.long	0xaaaaaa7f
+mdcas21:	.long	0xaaaaaaaa
+mdcas22:	.long	0xaaaaaaaa
+msc2:		.long	0x42196669
+smcnfg:		.long	0x00000000
+
+BCR:		.long	ASSABET_BCR
+BCR_DB1110:	.long	ASSABET_BCR_DB1110
+LEDS:		.long	NEPONSET_LEDS
+
+
+	.globl memsetup
+memsetup:
+
+	/* Setting up the memory and stuff */
+
+	ldr	r0, MEM_BASE
+	ldr	r1, mdcas00
+	str	r1, [r0, #MDCAS00]
+	ldr	r1, mdcas01
+	str	r1, [r0, #MDCAS01]
+	ldr	r1, mdcas02
+	str	r1, [r0, #MDCAS02]
+	ldr	r1, mdcas20
+	str	r1, [r0, #MDCAS20]
+	ldr	r1, mdcas21
+	str	r1, [r0, #MDCAS21]
+	ldr	r1, mdcas22
+	str	r1, [r0, #MDCAS22]
+	ldr	r1, mdrefr
+	str	r1, [r0, #MDREFR]
+	ldr	r1, mecr
+	str	r1, [r0, #MECR]
+	ldr	r1, msc0
+	str	r1, [r0, #MSC0]
+	ldr	r1, msc1
+	str	r1, [r0, #MSC1]
+	ldr	r1, msc2
+	str	r1, [r0, #MSC2]
+	ldr	r1, smcnfg
+	str	r1, [r0, #SMCNFG]
+
+	ldr	r1, mdcnfg
+	str	r1, [r0, #MDCNFG]
+
+	/* Load something to activate bank */
+	ldr	r2, MEM_START
+.rept	8
+	ldr	r3, [r2]
+.endr
+
+	/* Enable SDRAM */
+	orr	r1, r1, #0x00000001
+	str	r1, [r0, #MDCNFG]
+
+	ldr	r1, BCR
+	ldr	r2, BCR_DB1110
+	str	r2, [r1]
+
+	ldr	r1, LEDS
+	mov	r0, #0x3
+	str	r0, [r1]
+
+	/* All done... */
+	mov	pc, lr

board/assabet/u-boot.lds

@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * 2004 (c) MontaVista Software, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+		cpu/sa1100/start.o	(.text)
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}

board/cpu86/flash.c

@@ -41,10 +41,10 @@ ulong flash_int_get_size (volatile unsigned long *baseaddr,
 	info->sector_count = info->size = 0;
 	info->flash_id = FLASH_UNKNOWN;
 
-	/* Write query command sequence and test FLASH answer
+	/* Write identify command sequence and test FLASH answer
 	 */
-	baseaddr[0] = 0x00980098;
-	baseaddr[1] = 0x00980098;
+	baseaddr[0] = 0x00900090;
+	baseaddr[1] = 0x00900090;
 
 	flashtest_h = baseaddr[0];	/* manufacturer ID	*/
 	flashtest_l = baseaddr[1];

board/dave/PPChameleonEVB/u-boot.lds

@@ -73,9 +73,6 @@ SECTIONS
     lib_ppc/extable.o	(.text)
     lib_generic/zlib.o		(.text)
 
-/*    . = env_offset;*/
-/*    common/environment.o(.text)*/
-
     *(.text)
     *(.fixup)
     *(.got1)
@@ -142,6 +139,13 @@ SECTIONS
    *(.bss)
    *(COMMON)
   }
+
+  . = 0xFFFF8000;
+  .ppcenv : 
+  {
+    common/environment.o(.ppcenv);
+  }
+
   _end = . ;
   PROVIDE (end = .);
 }

board/dave/common/flash.c

@@ -669,8 +669,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data)
 	int i;
 
 	/* Check if Flash is (sufficiently) erased */
-	if ((*((volatile CFG_FLASH_WORD_SIZE *)dest) &
-	     (CFG_FLASH_WORD_SIZE)data) != (CFG_FLASH_WORD_SIZE)data) {
+	if ((*((volatile ulong *)dest) & data) != data) {
 		return (2);
 	}
 	/* Disable interrupts which might cause a timeout here */

board/eXalion/Makefile

@@ -29,7 +29,7 @@ OBJS	= $(BOARD).o
 SOBJS	=
 
 $(LIB):	.depend $(OBJS) $(SOBJS)
-	$(AR) crv $@ $^
+	$(AR) crv $@ $(OBJS) $(SOBJS)
 
 #########################################################################
 

board/jse/Makefile

@@ -0,0 +1,44 @@
+#
+# Copyright 2004 Picture Elements, Inc.
+# Stephen Williams <steve@icarus.com>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o sdram.o flash.o host_bridge.o
+SOBJS	= init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################

board/jse/README.txt

@@ -0,0 +1,48 @@
+JSE Configuration Details
+
+Memory Bank 0 -- Flash chip
+---------------------------
+
+0xfff00000 - 0xffffffff
+
+The flash chip is really only 512Kbytes, but the high address bit of
+the 1Meg region is ignored, so the flash is replicated through the
+region. Thus, this is consistent with a flash base address 0xfff80000.
+
+The placement at the end is to be consistent with reset behavior,
+where the processor itself initially uses this bus to load the branch
+vector and start running.
+
+On-Chip Memory
+--------------
+
+0xf4000000 - 0xf4000fff
+
+The 405GPr includes a 4K on-chip memory that can be placed however
+software chooses. I choose to place the memory at this address, to
+keep it out of the cachable areas.
+
+
+Memory Bank 1 -- SystemACE Controller
+-------------------------------------
+
+0xf0000000 - 0xf00fffff
+
+The SystemACE chip is along on peripheral bank CS#1. We don't need
+much space, but 1Meg is the smallest we can configure the chip to
+allocate. We need it far away from the flash region, because this
+region is set to be non-cached.
+
+
+Internal Peripherals
+--------------------
+
+0xef600300 - 0xef6008ff
+
+These are scattered various peripherals internal to the PPC405GPr
+chip.
+
+SDRAM
+-----
+
+0x00000000 - 0x07ffffff  (128 MBytes)

board/jse/config.mk

@@ -0,0 +1,24 @@
+#
+# (C) Copyright 2003 Picture Elements, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Picture Elements, Inc. JSE boards
+#
+
+TEXT_BASE = 0xFFF80000

board/jse/flash.c

@@ -0,0 +1,671 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Modified 4/5/2001
+ * Wait for completion of each sector erase command issued
+ * 4/5/2001
+ * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+#if CFG_MAX_FLASH_BANKS != 1
+#error "CFG_MAX_FLASH_BANKS must be 1"
+#endif
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips        */
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static int write_word (flash_info_t * info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+#define ADDR0           0x5555
+#define ADDR1           0x2aaa
+#define FLASH_WORD_SIZE unsigned char
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0;
+	unsigned long base_b0;
+
+	/* Init: no FLASHes known */
+	flash_info[0].flash_id = FLASH_UNKNOWN;
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 =
+		flash_get_size ((vu_long *) FLASH_BASE0_PRELIM,
+				&flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", size_b0, size_b0 << 20);
+	}
+
+	/* Only one bank */
+	/* Setup offsets */
+	flash_get_offsets (FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	/* Monitor protection ON by default */
+	(void) flash_protect (FLAG_PROTECT_SET,
+			      FLASH_BASE0_PRELIM,
+			      FLASH_BASE0_PRELIM + monitor_flash_len - 1,
+			      &flash_info[0]);
+	flash_info[0].size = size_b0;
+
+	return size_b0;
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t * info)
+{
+	int i;
+
+	/* set up sector start address table */
+	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+	    (info->flash_id == FLASH_AM040)) {
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * 0x00010000);
+	} else {
+		if (info->flash_id & FLASH_BTYPE) {
+			/* set sector offsets for bottom boot block type        */
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00004000;
+			info->start[2] = base + 0x00006000;
+			info->start[3] = base + 0x00008000;
+			for (i = 4; i < info->sector_count; i++) {
+				info->start[i] =
+					base + (i * 0x00010000) - 0x00030000;
+			}
+		} else {
+			/* set sector offsets for top boot block type           */
+			i = info->sector_count - 1;
+			info->start[i--] = base + info->size - 0x00004000;
+			info->start[i--] = base + info->size - 0x00006000;
+			info->start[i--] = base + info->size - 0x00008000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00010000;
+			}
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+	int k;
+	int size;
+	int erased;
+	volatile unsigned long *flash;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:
+		printf ("AMD ");
+		break;
+	case FLASH_MAN_FUJ:
+		printf ("FUJITSU ");
+		break;
+	case FLASH_MAN_SST:
+		printf ("SST ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM040:
+		printf ("AM29F040 (512 Kbit, uniform sector size)\n");
+		break;
+	case FLASH_AM400B:
+		printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM400T:
+		printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM800B:
+		printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM800T:
+		printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM160B:
+		printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM160T:
+		printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM320B:
+		printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM320T:
+		printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+		break;
+	case FLASH_SST800A:
+		printf ("SST39LF/VF800 (8 Mbit, uniform sector size)\n");
+		break;
+	case FLASH_SST160A:
+		printf ("SST39LF/VF160 (16 Mbit, uniform sector size)\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld KB in %d Sectors\n",
+		info->size >> 10, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		/*
+		 * Check if whole sector is erased
+		 */
+		if (i != (info->sector_count - 1))
+			size = info->start[i + 1] - info->start[i];
+		else
+			size = info->start[0] + info->size - info->start[i];
+		erased = 1;
+		flash = (volatile unsigned long *) info->start[i];
+		size = size >> 2;	/* divide by 4 for longword access */
+		for (k = 0; k < size; k++) {
+			if (*flash++ != 0xffffffff) {
+				erased = 0;
+				break;
+			}
+		}
+
+		if ((i % 5) == 0)
+			printf ("\n   ");
+#if 0				/* test-only */
+		printf (" %08lX%s",
+			info->start[i], info->protect[i] ? " (RO)" : "     "
+#else
+		printf (" %08lX%s%s",
+			info->start[i],
+			erased ? " E" : "  ", info->protect[i] ? "RO " : "   "
+#endif
+			);
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info)
+{
+	short i;
+	FLASH_WORD_SIZE value;
+	ulong base = (ulong) addr;
+	volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) addr;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+	addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+	addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00900090;
+
+#ifdef CONFIG_ADCIOP
+	value = addr2[2];
+#else
+	value = addr2[0];
+#endif
+
+	switch (value) {
+	case (FLASH_WORD_SIZE) AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case (FLASH_WORD_SIZE) FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case (FLASH_WORD_SIZE) SST_MANUFACT:
+		info->flash_id = FLASH_MAN_SST;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);	/* no or unknown flash  */
+	}
+
+#ifdef CONFIG_ADCIOP
+	value = addr2[0];	/* device ID            */
+	/*        printf("\ndev_code=%x\n", value); */
+#else
+	value = addr2[1];	/* device ID            */
+#endif
+
+	switch (value) {
+	case (FLASH_WORD_SIZE) AMD_ID_F040B:
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x0080000;	/* => 512 ko */
+		break;
+	case (FLASH_WORD_SIZE) AMD_ID_LV040B:
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x0080000;	/* => 512 ko */
+		break;
+	case (FLASH_WORD_SIZE) AMD_ID_LV400T:
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;		/* => 0.5 MB            */
+
+	case (FLASH_WORD_SIZE) AMD_ID_LV400B:
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;		/* => 0.5 MB            */
+
+	case (FLASH_WORD_SIZE) AMD_ID_LV800T:
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;		/* => 1 MB              */
+
+	case (FLASH_WORD_SIZE) AMD_ID_LV800B:
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;		/* => 1 MB              */
+
+	case (FLASH_WORD_SIZE) AMD_ID_LV160T:
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;		/* => 2 MB              */
+
+	case (FLASH_WORD_SIZE) AMD_ID_LV160B:
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;		/* => 2 MB              */
+#if 0				/* enable when device IDs are available */
+	case (FLASH_WORD_SIZE) AMD_ID_LV320T:
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 67;
+		info->size = 0x00400000;
+		break;		/* => 4 MB              */
+
+	case (FLASH_WORD_SIZE) AMD_ID_LV320B:
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 67;
+		info->size = 0x00400000;
+		break;		/* => 4 MB              */
+#endif
+	case (FLASH_WORD_SIZE) SST_ID_xF800A:
+		info->flash_id += FLASH_SST800A;
+		info->sector_count = 16;
+		info->size = 0x00100000;
+		break;		/* => 1 MB              */
+
+	case (FLASH_WORD_SIZE) SST_ID_xF160A:
+		info->flash_id += FLASH_SST160A;
+		info->sector_count = 32;
+		info->size = 0x00200000;
+		break;		/* => 2 MB              */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);	/* => no or unknown flash */
+
+	}
+
+	/* set up sector start address table */
+	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+	    (info->flash_id == FLASH_AM040)) {
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * 0x00010000);
+	} else {
+		if (info->flash_id & FLASH_BTYPE) {
+			/* set sector offsets for bottom boot block type        */
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00004000;
+			info->start[2] = base + 0x00006000;
+			info->start[3] = base + 0x00008000;
+			for (i = 4; i < info->sector_count; i++) {
+				info->start[i] =
+					base + (i * 0x00010000) - 0x00030000;
+			}
+		} else {
+			/* set sector offsets for top boot block type           */
+			i = info->sector_count - 1;
+			info->start[i--] = base + info->size - 0x00004000;
+			info->start[i--] = base + info->size - 0x00006000;
+			info->start[i--] = base + info->size - 0x00008000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00010000;
+			}
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+#ifdef CONFIG_ADCIOP
+		addr2 = (volatile FLASH_WORD_SIZE *) (info->start[i]);
+		info->protect[i] = addr2[4] & 1;
+#else
+		addr2 = (volatile FLASH_WORD_SIZE *) (info->start[i]);
+		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
+			info->protect[i] = 0;
+		else
+			info->protect[i] = addr2[2] & 1;
+#endif
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+#if 0				/* test-only */
+#ifdef CONFIG_ADCIOP
+		addr2 = (volatile unsigned char *) info->start[0];
+		addr2[ADDR0] = 0xAA;
+		addr2[ADDR1] = 0x55;
+		addr2[ADDR0] = 0xF0;	/* reset bank */
+#else
+		addr2 = (FLASH_WORD_SIZE *) info->start[0];
+		*addr2 = (FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
+#endif
+#else  /* test-only */
+		addr2 = (FLASH_WORD_SIZE *) info->start[0];
+		*addr2 = (FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
+#endif /* test-only */
+	}
+
+	return (info->size);
+}
+
+int wait_for_DQ7 (flash_info_t * info, int sect)
+{
+	ulong start, now, last;
+	volatile FLASH_WORD_SIZE *addr =
+		(FLASH_WORD_SIZE *) (info->start[sect]);
+
+	start = get_timer (0);
+	last = start;
+	while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) !=
+	       (FLASH_WORD_SIZE) 0x00800080) {
+		if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return -1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]);
+	volatile FLASH_WORD_SIZE *addr2;
+	int flag, prot, sect, l_sect;
+	int i;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr2 = (FLASH_WORD_SIZE *) (info->start[sect]);
+			printf ("Erasing sector %p\n", addr2);	/* CLH */
+
+			if ((info->flash_id & FLASH_VENDMASK) ==
+			    FLASH_MAN_SST) {
+				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080;
+				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+				addr2[0] = (FLASH_WORD_SIZE) 0x00500050;	/* block erase */
+				for (i = 0; i < 50; i++)
+					udelay (1000);	/* wait 1 ms */
+			} else {
+				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080;
+				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+				addr2[0] = (FLASH_WORD_SIZE) 0x00300030;	/* sector erase */
+			}
+			l_sect = sect;
+			/*
+			 * Wait for each sector to complete, it's more
+			 * reliable.  According to AMD Spec, you must
+			 * issue all erase commands within a specified
+			 * timeout.  This has been seen to fail, especially
+			 * if printf()s are included (for debug)!!
+			 */
+			wait_for_DQ7 (info, sect);
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+#if 0
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+	wait_for_DQ7 (info, l_sect);
+
+      DONE:
+#endif
+	/* reset to read mode */
+	addr = (FLASH_WORD_SIZE *) info->start[0];
+	addr[0] = (FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < 4 && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < 4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i = 0; i < 4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < 4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_word (info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t * info, ulong dest, ulong data)
+{
+	volatile FLASH_WORD_SIZE *addr2 =
+		(FLASH_WORD_SIZE *) (info->start[0]);
+	volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest;
+	volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data;
+	ulong start;
+	int i;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((volatile FLASH_WORD_SIZE *) dest) &
+	     (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
+		return (2);
+	}
+
+	for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) {
+		int flag;
+
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts ();
+
+		addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+		addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+		addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0;
+
+		dest2[i] = data2[i];
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts ();
+
+		/* data polling for D7 */
+		start = get_timer (0);
+		while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) !=
+		       (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) {
+
+			if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+				return (1);
+			}
+		}
+	}
+
+	return (0);
+}

board/jse/host_bridge.c

@@ -0,0 +1,89 @@
+/*
+ * Copyright (c) 2004 Picture Elements, Inc.
+ *    Stephen Williams (steve@icarus.com)
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+#ident "$Id:$"
+
+# include  <common.h>
+# include  <pci.h>
+# include  "jse_priv.h"
+
+/*
+ * The JSE board has an Intel 21555 non-transparent bridge for
+ * communication with the host. We need to render it harmless on the
+ * JSE side, but leave it alone on the host (primary) side. Normally,
+ * this will all be done before the host BIOS can gain access to the
+ * board, due to the Primary Access Lockout bit.
+ *
+ * The host_bridge_init function is called as a late initialization
+ * function, after most of the board is set up, including a PCI scan.
+ */
+
+void host_bridge_init (void)
+{
+	/* The bridge chip is at a fixed location. */
+	pci_dev_t dev = PCI_BDF (0, 10, 0);
+
+	int rc;
+	u32 val32;
+
+	rc = pci_read_config_dword (dev, 0, &val32);
+
+	/* Set subsystem ID --
+	   The primary side sees this value at 0x2c. We set it here so
+	   that the host can tell what sort of device this is:
+	   We are a Picture Elements [0x12c5] JSE [0x008a]. */
+	pci_write_config_dword (dev, 0x6c, 0x008a12c5);
+
+	/* Downstream (Primary-to-Secondary) BARs are set up mostly
+	   off. We need only the Memory-0 Bar so that the host can get
+	   at the CSR region to set up tables and the lot. */
+
+	/* Downstream Memory 0 setup (4K for CSR) */
+	pci_write_config_dword (dev, 0xac, 0xfffff000);
+	/* Downstream Memory 1 setup (off) */
+	pci_write_config_dword (dev, 0xb0, 0x00000000);
+	/* Downstream Memory 2 setup (off) */
+	pci_write_config_dword (dev, 0xb4, 0x00000000);
+	/* Downstream Memory 3 setup (off) */
+	pci_write_config_dword (dev, 0xb8, 0x00000000);
+
+	/* Upstream (Secondary-to-Primary) BARs are used to get at
+	   host memory from the JSE card. Create two regions: a small
+	   one to manage individual word reads/writes, and a larger
+	   one for doing bulk frame moves. */
+
+	/* Upstream Memory 0 Setup -- (BAR2) 4K non-prefetchable */
+	pci_write_config_dword (dev, 0xc4, 0xfffff000);
+	/* Upstream Memory 1 setup -- (BAR3) 4K non-prefetchable */
+	pci_write_config_dword (dev, 0xc8, 0xfffff000);
+
+	/* Upstream Memory 2 (BAR4) uses page translation, and is set
+	   up in CCR1. Configure for 4K pages. */
+
+	/* Set CCR1,0 reigsters. This clears the Primary PCI Lockout
+	   bit as well, so we are done configuring after this
+	   point. Therefore, this must be the last step.
+
+	   CC1[15:12]= 0  (disable I2O message unit)
+	   CC1[11:8] = 0x5 (4K page size)
+	   CC0[11]   = 1  (Secondary Clock Disable: disable clock)
+	   CC0[10]   = 0  (Primary Access Lockout: allow primary access)
+	 */
+	pci_write_config_dword (dev, 0xcc, 0x05000800);
+}

board/jse/init.S

@@ -0,0 +1,105 @@
+/*------------------------------------------------------------------------+ */
+/* */
+/*       This source code has been made available to you by IBM on an AS-IS */
+/*       basis.  Anyone receiving this source is licensed under IBM */
+/*       copyrights to use it in any way he or she deems fit, including */
+/*       copying it, modifying it, compiling it, and redistributing it either */
+/*       with or without modifications.  No license under IBM patents or */
+/*       patent applications is to be implied by the copyright license. */
+/* */
+/*       Any user of this software should understand that IBM cannot provide */
+/*       technical support for this software and will not be responsible for */
+/*       any consequences resulting from the use of this software. */
+/* */
+/*       Any person who transfers this source code or any derivative work */
+/*       must include the IBM copyright notice, this paragraph, and the */
+/*       preceding two paragraphs in the transferred software. */
+/* */
+/*       COPYRIGHT   I B M   CORPORATION 1995 */
+/*       LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M */
+/*------------------------------------------------------------------------- */
+
+/*------------------------------------------------------------------------- */
+/* Function:     ext_bus_cntlr_init */
+/* Description:  Initializes the External Bus Controller for the external */
+/*		peripherals. IMPORTANT: For pass1 this code must run from */
+/*		cache since you can not reliably change a peripheral banks */
+/*		timing register (pbxap) while running code from that bank. */
+/*		For ex., since we are running from ROM on bank 0, we can NOT */
+/*		execute the code that modifies bank 0 timings from ROM, so */
+/*		we run it from cache. */
+/*                                    */
+/*                                    */
+/* The layout for the PEI JSE board:  */
+/*	Bank 0 - Flash and SRAM       */
+/*	Bank 1 - SystemACE            */
+/*	Bank 2 - not used             */
+/*	Bank 3 - not used             */
+/*	Bank 4 - not used             */
+/*	Bank 5 - not used             */
+/*	Bank 6 - not used             */
+/*	Bank 7 - not used             */
+/*------------------------------------------------------------------------- */
+#include <ppc4xx.h>
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+
+#define cpc0_cr0 0xB1
+
+	.globl	ext_bus_cntlr_init
+ext_bus_cntlr_init:
+	mflr    r4                      /* save link register */
+	bl      ..getAddr
+..getAddr:
+	mflr    r3                      /* get address of ..getAddr */
+	mtlr    r4                      /* restore link register */
+	addi    r4,0,14                 /* set ctr to 10; used to prefetch */
+	mtctr   r4                      /* 10 cache lines to fit this function */
+					/* in cache (gives us 8x10=80 instrctns) */
+..ebcloop:
+	icbt    r0,r3                   /* prefetch cache line for addr in r3 */
+	addi    r3,r3,32		/* move to next cache line */
+	bdnz    ..ebcloop               /* continue for 10 cache lines */
+
+	/*----------------------------------------------------------------- */
+	/* Delay to ensure all accesses to ROM are complete before changing */
+	/* bank 0 timings. 200usec should be enough. */
+	/*   200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */
+	/*----------------------------------------------------------------- */
+	addis	r3,0,0x0
+	ori     r3,r3,0xA000          /* ensure 200usec have passed since reset */
+	mtctr   r3
+..spinlp:
+	bdnz    ..spinlp                /* spin loop */
+
+	/*----------------------------------------------------------------- */
+	/* Memory Bank 0 (Flash) initialization */
+	/*----------------------------------------------------------------- */
+
+	addi    r4,0,pb0ap
+	mtdcr   ebccfga,r4
+	addis   r4,0,0x9B01
+	ori     r4,r4,0x5480
+	mtdcr   ebccfgd,r4
+
+	addi    r4,0,pb0cr
+	mtdcr   ebccfga,r4
+	addis   r4,0,0xFFF1           /* BAS=0xFFF,BS=0x0(1MB),BU=0x3(R/W), */
+	ori     r4,r4,0x8000          /* BW=0x0( 8 bits) */
+	mtdcr   ebccfgd,r4
+
+	blr
+
+
+/*----------------------------------------------------------------------- */
+/* Function:     sdram_init                                               */
+/* Description:  This function is called by cpu/ppc4xx/start.S code       */
+/*               to get the SDRAM initialized.                            */
+/*----------------------------------------------------------------------- */
+	.globl  sdram_init
+sdram_init:
+	blr

board/jse/jse.c

@@ -0,0 +1,160 @@
+/*
+ * Copyright (c) 2004 Picture Elements, Inc.
+ *    Stephen Williams (steve@icarus.com)
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+
+# include  <common.h>
+# include  <ppc4xx.h>
+# include  <asm/processor.h>
+# include  <asm/io.h>
+# include  "jse_priv.h"
+
+/*
+ * This function is run very early, out of flash, and before devices are
+ * initialized. It is called by lib_ppc/board.c:board_init_f by virtue
+ * of being in the init_sequence array.
+ *
+ * The SDRAM has been initialized already -- start.S:start called
+ * init.S:init_sdram early on -- but it is not yet being used for
+ * anything, not even stack. So be careful.
+ */
+int board_early_init_f (void)
+{
+   /*-------------------------------------------------------------------------+
+   | Interrupt controller setup for the JSE board.
+   | Note: IRQ 0-15  405GP internally generated; active high; level sensitive
+   |       IRQ 16    405GP internally generated; active low; level sensitive
+   |       IRQ 17-24 RESERVED/UNUSED
+   |       IRQ 25 (EXT IRQ 0) PCI SLOT 0; active low; level sensitive
+   |       IRQ 26 (EXT IRQ 1) PCI SLOT 1; active low; level sensitive
+   |       IRQ 27 (EXT IRQ 2) JP2C CHIP ; active low; level sensitive
+   |       IRQ 28 (EXT IRQ 3) PCI bridge; active low; level sensitive
+   |       IRQ 29 (EXT IRQ 4) SystemACE IRQ; active high
+   |       IRQ 30 (EXT IRQ 5) SystemACE BRdy (unused)
+   |       IRQ 31 (EXT IRQ 6) (unused)
+   +-------------------------------------------------------------------------*/
+	mtdcr (uicsr, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr (uicer, 0x00000000);	/* disable all ints */
+	mtdcr (uiccr, 0x00000000);	/* set all to be non-critical */
+	mtdcr (uicpr, 0xFFFFFF87);	/* set int polarities */
+	mtdcr (uictr, 0x10000000);	/* set int trigger levels */
+	mtdcr (uicsr, 0xFFFFFFFF);	/* clear all ints */
+
+	/* Configure the interface to the SystemACE MCU port.
+	   The SystemACE is fast, but there is no reason to have
+	   excessivly tight timings. So the settings are slightly
+	   generous. */
+
+	/* EBC0_B1AP: BME=1, TWT=2, CSN=0, OEN=1,
+	   WBN=0, WBF=1, TH=0,  RE=0,  SOR=0, BEM=0, PEN=0 */
+	mtdcr (ebccfga, pb1ap);
+	mtdcr (ebccfgd, 0x01011000);
+
+	/* EBC0_B1CR: BAS=x, BS=0(1MB), BU=3(R/W), BW=0(8bits) */
+	mtdcr (ebccfga, pb1cr);
+	mtdcr (ebccfgd, CFG_SYSTEMACE_BASE | 0x00018000);
+
+	/* Enable the /PerWE output as /PerWE, instead of /PCIINT. */
+	/* CPC0_CR1 |= PCIPW */
+	mtdcr (0xb2, mfdcr (0xb2) | 0x00004000);
+
+	return 0;
+}
+
+#ifdef CONFIG_BOARD_PRE_INIT
+int board_pre_init (void)
+{
+	return board_early_init_f ();
+}
+
+#endif
+
+/*
+ * This function is also called by lib_ppc/board.c:board_init_f (it is
+ * also in the init_sequence array) but later. Many more things are
+ * configured, but we are still running from flash.
+ */
+int checkboard (void)
+{
+	unsigned vers, status;
+
+	/* check that the SystemACE chip is alive. */
+	printf ("ACE:   ");
+	vers = readw (CFG_SYSTEMACE_BASE + 0x16);
+	printf ("SystemACE %u.%u (build %u)",
+		(vers >> 12) & 0x0f, (vers >> 8) & 0x0f, vers & 0xff);
+
+	status = readl (CFG_SYSTEMACE_BASE + 0x04);
+#ifdef DEBUG
+	printf (" STATUS=0x%08x", status);
+#endif
+	/* If the flash card is present and there is an initial error,
+	   then force a restart of the program. */
+	if (status & 0x00000010) {
+		printf (" CFDETECT");
+
+		if (status & 0x04) {
+			/* CONTROLREG = CFGPROG */
+			writew (0x1000, CFG_SYSTEMACE_BASE + 0x18);
+			udelay (500);
+			/* CONTROLREG = CFGRESET */
+			writew (0x0080, CFG_SYSTEMACE_BASE + 0x18);
+			udelay (500);
+			writew (0x0000, CFG_SYSTEMACE_BASE + 0x18);
+			/* CONTROLREG = CFGSTART */
+			writew (0x0020, CFG_SYSTEMACE_BASE + 0x18);
+
+			status = readl (CFG_SYSTEMACE_BASE + 0x04);
+		}
+	}
+
+	/* Wait for the SystemACE to program its chain of devices. */
+	while ((status & 0x84) == 0x00) {
+		udelay (500);
+		status = readl (CFG_SYSTEMACE_BASE + 0x04);
+	}
+
+	if (status & 0x04)
+		printf (" CFG-ERROR");
+	if (status & 0x80)
+		printf (" CFGDONE");
+
+	printf ("\n");
+
+	/* Force /RTS to active. The board it not wired quite
+	   correctly to use cts/rtc flow control, so just force the
+	   /RST active and forget about it. */
+	writeb (readb (0xef600404) | 0x03, 0xef600404);
+
+	printf ("JSE:   ready\n");
+
+	return 0;
+}
+
+/* **** No more functions called by board_init_f. **** */
+
+/*
+ * This function is called by lib_ppc/board.c:board_init_r. At this
+ * point, basic setup is done, U-Boot has been moved into SDRAM and
+ * PCI has been set up. From here we done late setup.
+ */
+int misc_init_r (void)
+{
+	host_bridge_init ();
+	return 0;
+}

board/jse/jse_priv.h

@@ -0,0 +1,25 @@
+#ifndef __jse_priv_H
+#define __jse_prov_H
+/*
+ * Copyright (c) 2004 Picture Elements, Inc.
+ *    Stephen Williams (steve@icarus.com)
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+
+extern void host_bridge_init(void);
+
+#endif

board/jse/sdram.c

@@ -0,0 +1,182 @@
+/*
+ * Copyright (c) 2004 Picture Elements, Inc.
+ *    Stephen Williams (steve@icarus.com)
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+# define SDRAM_LEN 0x08000000
+
+/*
+ * this is even after checkboard. It returns the size of the SDRAM
+ * that we have installed. This function is called by board_init_f
+ * in lib_ppc/board.c to initialize the memory and return what I
+ * found.
+ */
+long int initdram (int board_type)
+{
+	/* Configure the SDRAMS */
+
+	/* disable memory controller */
+	mtdcr (memcfga, mem_mcopt1);
+	mtdcr (memcfgd, 0x00000000);
+
+	udelay (500);
+
+	/* Clear SDRAM0_BESR0 (Bus Error Syndrome Register) */
+	mtdcr (memcfga, mem_besra);
+	mtdcr (memcfgd, 0xffffffff);
+
+	/* Clear SDRAM0_BESR1 (Bus Error Syndrome Register) */
+	mtdcr (memcfga, mem_besrb);
+	mtdcr (memcfgd, 0xffffffff);
+
+	/* Clear SDRAM0_ECCCFG (disable ECC) */
+	mtdcr (memcfga, mem_ecccf);
+	mtdcr (memcfgd, 0x00000000);
+
+	/* Clear SDRAM0_ECCESR (ECC Error Syndrome Register) */
+	mtdcr (memcfga, mem_eccerr);
+	mtdcr (memcfgd, 0xffffffff);
+
+	/* Timing register: CASL=2, PTA=2, CTP=2, LDF=1, RFTA=5, RCD=2 */
+	mtdcr (memcfga, mem_sdtr1);
+	mtdcr (memcfgd, 0x010a4016);
+
+	/* Memory Bank 0 Config == BA=0x00000000, SZ=64M, AM=3, BE=1 */
+	mtdcr (memcfga, mem_mb0cf);
+	mtdcr (memcfgd, 0x00084001);
+
+	/* Memory Bank 1 Config == BA=0x04000000, SZ=64M, AM=3, BE=1 */
+	mtdcr (memcfga, mem_mb1cf);
+	mtdcr (memcfgd, 0x04084001);
+
+	/* Memory Bank 2 Config ==  BE=0 */
+	mtdcr (memcfga, mem_mb2cf);
+	mtdcr (memcfgd, 0x00000000);
+
+	/* Memory Bank 3 Config ==  BE=0 */
+	mtdcr (memcfga, mem_mb3cf);
+	mtdcr (memcfgd, 0x00000000);
+
+	/* refresh timer = 0x400  */
+	mtdcr (memcfga, mem_rtr);
+	mtdcr (memcfgd, 0x04000000);
+
+	/* Power management idle timer set to the default. */
+	mtdcr (memcfga, mem_pmit);
+	mtdcr (memcfgd, 0x07c00000);
+
+	udelay (500);
+
+	/* Enable banks (DCE=1, BPRF=1, ECCDD=1, EMDUL=1) */
+	mtdcr (memcfga, mem_mcopt1);
+	mtdcr (memcfgd, 0x80e00000);
+
+	return SDRAM_LEN;
+}
+
+/*
+ * The U-Boot core, as part of the initialization to prepare for
+ * loading the monitor into SDRAM, requests of this function that the
+ * memory be tested. Return 0 if the memory tests OK.
+ */
+int testdram (void)
+{
+	unsigned long idx;
+	unsigned val;
+	unsigned errors;
+	volatile unsigned long *sdram;
+
+#ifdef DEBUG
+	printf ("SDRAM Controller Registers --\n");
+
+	mtdcr (memcfga, mem_mcopt1);
+	val = mfdcr (memcfgd);
+	printf ("    SDRAM0_CFG   : 0x%08x\n", val);
+
+	mtdcr (memcfga, 0x24);
+	val = mfdcr (memcfgd);
+	printf ("    SDRAM0_STATUS: 0x%08x\n", val);
+
+	mtdcr (memcfga, mem_mb0cf);
+	val = mfdcr (memcfgd);
+	printf ("    SDRAM0_B0CR  : 0x%08x\n", val);
+
+	mtdcr (memcfga, mem_mb1cf);
+	val = mfdcr (memcfgd);
+	printf ("    SDRAM0_B1CR  : 0x%08x\n", val);
+
+	mtdcr (memcfga, mem_sdtr1);
+	val = mfdcr (memcfgd);
+	printf ("    SDRAM0_TR    : 0x%08x\n", val);
+
+	mtdcr (memcfga, mem_rtr);
+	val = mfdcr (memcfgd);
+	printf ("    SDRAM0_RTR   : 0x%08x\n", val);
+#endif
+
+	/* Wait for memory to be ready by testing MRSCMPbit
+	   bit. Really, there should already have been plenty of time,
+	   given it was started long ago. But, best to check. */
+	for (idx = 0; idx < 1000000; idx += 1) {
+		mtdcr (memcfga, 0x24);
+		val = mfdcr (memcfgd);
+		if (val & 0x80000000)
+			break;
+	}
+
+	if (!(val & 0x80000000)) {
+		printf ("SDRAM ERROR: SDRAM0_STATUS never set!\n");
+		return 1;
+	}
+
+	/* Start memory test. */
+	printf ("test: %u MB - ", SDRAM_LEN / 1048576);
+
+	sdram = (unsigned long *) CFG_SDRAM_BASE;
+
+	printf ("write - ");
+	for (idx = 2; idx < SDRAM_LEN / 4; idx += 2) {
+		sdram[idx + 0] = idx;
+		sdram[idx + 1] = ~idx;
+	}
+
+	printf ("read - ");
+	errors = 0;
+	for (idx = 2; idx < SDRAM_LEN / 4; idx += 2) {
+		if (sdram[idx + 0] != idx)
+			errors += 1;
+		if (sdram[idx + 1] != ~idx)
+			errors += 1;
+		if (errors > 0)
+			break;
+	}
+
+	if (errors > 0) {
+		printf ("NOT OK\n");
+		printf ("FIRST ERROR at %p: 0x%08lx:0x%08lx != 0x%08lx:0x%08lx\n",
+			sdram + idx, sdram[idx + 0], sdram[idx + 1], idx, ~idx);
+		return 1;
+	}
+
+	printf ("ok\n");
+	return 0;
+}

board/jse/u-boot.lds

@@ -0,0 +1,140 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text          : {
+    /* The start.o file includes the initial jump vector that
+       must be located in the beginning. It is the basic run-
+       time function that calls all other functions. */
+    cpu/ppc4xx/start.o	(.text)
+
+    board/jse/init.o	(.text)
+    cpu/ppc4xx/kgdb.o	(.text)
+
+/*    . = env_offset;*/
+/*    common/environment.o(.text)*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}

board/kup/Makefile

@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o kup.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################

board/kup/common/flash.c

@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000-2002
+ * (C) Copyright 2000-2004
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -197,13 +197,13 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 	case AMD_ID_LV800T:
 		info->flash_id += FLASH_AM800T;
 		info->sector_count = 19;
-		info->size = 0x00200000;
-		break;				/* => 2 MB		*/
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
 	case AMD_ID_LV800B:
 		info->flash_id += FLASH_AM800B;
 		info->sector_count = 19;
-		info->size = 0x00200000;
-		break;				/* => 2 MB		*/
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
 	default:
 		info->flash_id = FLASH_UNKNOWN;
 		return (0);			/* => no or unknown flash */

board/kup/common/kup.c

@@ -0,0 +1,72 @@
+/*
+ * (C) Copyright 2004
+ * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+#include "kup.h"
+
+int misc_init_f (void)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile sysconf8xx_t *siu = &immap->im_siu_conf;
+
+	while (siu->sc_sipend & 0x20000000) {
+		/* printf("waiting for 5V VCC\n"); */
+		;
+	}
+
+	/* RS232 / RS485 default is RS232 */
+	immap->im_ioport.iop_padat &= ~(PA_RS485);
+	immap->im_ioport.iop_papar &= ~(PA_RS485);
+	immap->im_ioport.iop_paodr &= ~(PA_RS485);
+	immap->im_ioport.iop_padir |= (PA_RS485);
+	return (0);
+}
+
+
+#ifdef CONFIG_IDE_LED
+void ide_led (uchar led, uchar status)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+
+	/* We have one led for both pcmcia slots */
+	if (status) {		/* led on */
+		immap->im_ioport.iop_padat &= ~(PA_LED_YELLOW);
+	} else {
+		immap->im_ioport.iop_padat |= (PA_LED_YELLOW);
+	}
+}
+#endif
+
+void poweron_key (void)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+
+	immap->im_ioport.iop_pcpar &= ~(PC_SWITCH1);
+	immap->im_ioport.iop_pcdir &= ~(PC_SWITCH1);
+
+	if (immap->im_ioport.iop_pcdat & (PC_SWITCH1))
+		setenv ("key1", "off");
+	else
+		setenv ("key1", "on");
+}

board/kup/common/kup.h

@@ -0,0 +1,44 @@
+/*
+ * (C) Copyright 2004
+ * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __KUP_H
+#define __KUP_H
+
+#define PA_8       0x0080
+#define PA_11      0x0010
+#define PA_12      0x0008
+
+#define PB_14      0x00020000
+#define PB_17      0x00004000
+
+#define PC_9       0x0040
+
+#define PA_RS485                 PA_11   /* SCC1: 0=RS232 1=RS485 */
+#define PA_LED_YELLOW            PA_8
+#define BP_USB_VCC               PB_14   /* VCC for USB devices 0=vcc on, 1=vcc off*/
+#define PB_LCD_PWM	         PB_17	 /* PB 17 */
+#define PC_SWITCH1               PC_9    /* Reboot switch */
+
+extern void poweron_key (void);
+
+#endif	/* __KUP_H */

board/kup/kup4k/Makefile

@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o ../common/flash.o ../common/kup.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################

board/kup/kup4k/config.mk

@@ -1,5 +1,5 @@
 #
-# (C) Copyright 2000-2002
+# (C) Copyright 2000-2004
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # See file CREDITS for list of people who contributed to this

board/kup/kup4k/kup4k.c

@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000, 2001, 2002
+ * (C) Copyright 2000-2004
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de
  *
@@ -24,16 +24,23 @@
 
 #include <common.h>
 #include <mpc8xx.h>
+#include "../common/kup.h"
 #ifdef CONFIG_KUP4K_LOGO
    #include "s1d13706.h"
 #endif
 
+#undef DEBUG
+#ifdef  DEBUG
+# define debugk(fmt,args...)    printf(fmt ,##args)
+#else
+# define debugk(fmt,args...)
+#endif
+
+typedef struct {
+	volatile unsigned char *VmemAddr;
+	volatile unsigned char *RegAddr;
+} FB_INFO_S1D13xxx;
 
-typedef struct
-{
-    volatile unsigned char *VmemAddr;
-    volatile unsigned char *RegAddr;
-}FB_INFO_S1D13xxx;
 
 /* ------------------------------------------------------------------------- */
 
@@ -42,15 +49,15 @@ static long int dram_size (long int, long int *, long int);
 #endif
 
 #ifdef CONFIG_KUP4K_LOGO
-   void lcd_logo(bd_t *bd);
+void lcd_logo(bd_t *bd);
 #endif
 
+
 /* ------------------------------------------------------------------------- */
 
 #define	_NOT_USED_	0xFFFFFFFF
 
-const uint sdram_table[] =
-{
+const uint sdram_table[] = {
 	/*
 	 * Single Read. (Offset 0 in UPMA RAM)
 	 */
@@ -114,8 +121,19 @@ const uint sdram_table[] =
 
 int checkboard (void)
 {
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	uchar *latch,rev,mod;
 
-	printf ("### No HW ID - assuming KUP4K-Color\n");
+	/*
+	 * Init ChipSelect #4 (CAN + HW-Latch)
+	 */
+	immap->im_memctl.memc_or4 = 0xFFFF8926;
+	immap->im_memctl.memc_br4 = 0x90000401;
+
+	latch=(uchar *)0x90000200;
+	rev = (*latch & 0xF8) >> 3;
+	mod=(*latch & 0x03);
+	printf ("Board: KUP4K Rev %d.%d SN: %s\n",rev,mod,getenv("ethaddr"));
 	return (0);
 }
 
@@ -230,10 +248,42 @@ static long int dram_size (long int mamr_value, long int *base,
 {
 	volatile immap_t *immap = (immap_t *) CFG_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	volatile long int *addr;
+	ulong cnt, val;
+	ulong save[32];				/* to make test non-destructive */
+	unsigned char i = 0;
 
 	memctl->memc_mamr = mamr_value;
 
-	return(get_ram_size(base, maxsize));
+	for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
+		addr = base + cnt;		/* pointer arith! */
+
+		save[i++] = *addr;
+		*addr = ~cnt;
+	}
+
+	/* write 0 to base address */
+	addr = base;
+	save[i] = *addr;
+	*addr = 0;
+
+	/* check at base address */
+	if ((val = *addr) != 0) {
+		*addr = save[i];
+		return (0);
+	}
+
+	for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
+		addr = base + cnt;		/* pointer arith! */
+
+		val = *addr;
+		*addr = save[--i];
+
+		if (val != (~cnt)) {
+			return (cnt * sizeof (long));
+		}
+	}
+	return (maxsize);
 }
 #endif
 
@@ -247,7 +297,6 @@ int misc_init_r (void)
 #ifdef CONFIG_KUP4K_LOGO
 	bd_t *bd = gd->bd;
 
-
 	lcd_logo (bd);
 #endif							/* CONFIG_KUP4K_LOGO */
 #ifdef CONFIG_IDE_LED
@@ -257,14 +306,14 @@ int misc_init_r (void)
 	immap->im_ioport.iop_papar &= ~0x80;
 	immap->im_ioport.iop_padat |= 0x80;	/* turn it off */
 #endif
+	setenv("hw","4k");
+	poweron_key();
 	return (0);
 }
 
 #ifdef CONFIG_KUP4K_LOGO
 
 
-#define PB_LCD_PWM	((uint)0x00004000)	/* PB 17 */
-
 void lcd_logo (bd_t * bd)
 {
 	FB_INFO_S1D13xxx fb_info;
@@ -277,104 +326,117 @@ void lcd_logo (bd_t * bd)
 	int rs, gs, bs;
 	int r = 8, g = 8, b = 4;
 	int r1, g1, b1;
+	int n;
+	uchar tmp[64];		/* long enough for environment variables */
+	int tft = 0;
 
-	immr->im_cpm.cp_pbpar &= ~PB_LCD_PWM;
-	immr->im_cpm.cp_pbodr &= ~PB_LCD_PWM;
-	immr->im_cpm.cp_pbdat &= ~PB_LCD_PWM;	/* set to 0 = enabled */
-	immr->im_cpm.cp_pbdir |= PB_LCD_PWM;
-
+	immr->im_cpm.cp_pbpar &= ~(PB_LCD_PWM);
+	immr->im_cpm.cp_pbodr &= ~(PB_LCD_PWM);
+	immr->im_cpm.cp_pbdat &= ~(PB_LCD_PWM);	/* set to 0 = enabled */
+	immr->im_cpm.cp_pbdir |= (PB_LCD_PWM);
 
 /*----------------------------------------------------------------------------- */
-	 /**/
 /* Initialize the chip and the frame buffer driver. */
-			 /**/
 /*----------------------------------------------------------------------------- */
-			memctl = &immr->im_memctl;
-/*	memctl->memc_or5 = 0xFFC007F0;    / * 4 MB  17 WS or externel TA */
-/*	memctl->memc_br5 = 0x80000801;    / * Start at 0x80000000 */
+	memctl = &immr->im_memctl;
 
-	memctl->memc_or5 = 0xFFC00708;	/* 4 MB  17 WS or externel TA */
+
+	/*
+	 * Init ChipSelect #5 (S1D13768)
+	 */
+	memctl->memc_or5 = 0xFFC007F0;	/* 4 MB  17 WS or externel TA */
 	memctl->memc_br5 = 0x80080801;	/* Start at 0x80080000 */
 
-
 	fb_info.VmemAddr = (unsigned char *) (S1D_PHYSICAL_VMEM_ADDR);
 	fb_info.RegAddr = (unsigned char *) (S1D_PHYSICAL_REG_ADDR);
 
 	if ((((S1D_VALUE *) fb_info.RegAddr)[0] != 0x28)
-		|| (((S1D_VALUE *) fb_info.RegAddr)[1] != 0x14)) {
+	    || (((S1D_VALUE *) fb_info.RegAddr)[1] != 0x14)) {
 		printf ("Warning:LCD Controller S1D13706 not found\n");
+		setenv ("lcd", "none");
 		return;
 	}
 
-	/* init controller */
-	for (i = 0; i < sizeof (aS1DRegs) / sizeof (aS1DRegs[0]); i++) {
-		s1dReg = aS1DRegs[i].Index;
-		s1dValue = aS1DRegs[i].Value;
-/*      printf("sid1 Index: %02x Register: %02x Wert: %02x\n",i, aS1DRegs[i].Index, aS1DRegs[i].Value); */
+
+	for (i = 0; i < sizeof(aS1DRegs_prelimn) / sizeof(aS1DRegs_prelimn[0]); i++) {
+		s1dReg = aS1DRegs_prelimn[i].Index;
+		s1dValue = aS1DRegs_prelimn[i].Value;
+		debugk ("s13768 reg: %02x value: %02x\n",
+			aS1DRegs_prelimn[i].Index, aS1DRegs_prelimn[i].Value);
 		((S1D_VALUE *) fb_info.RegAddr)[s1dReg / sizeof (S1D_VALUE)] =
+			s1dValue;
+	}
+
+
+	n = getenv_r ("lcd", tmp, sizeof (tmp));
+	if (n > 0) {
+		if (!strcmp ("tft", tmp))
+			tft = 1;
+		else
+			tft = 0;
+	}
+#if 0
+	if (((S1D_VALUE *) fb_info.RegAddr)[0xAC] & 0x04)
+		tft = 0;
+	else
+		tft = 1;
+#endif
+
+	debugk ("Port=0x%02x -> TFT=%d\n", tft,
+		((S1D_VALUE *) fb_info.RegAddr)[0xAC]);
+
+	/* init controller */
+	if (!tft) {
+		for (i = 0; i < sizeof(aS1DRegs_stn) / sizeof(aS1DRegs_stn[0]); i++) {
+			s1dReg = aS1DRegs_stn[i].Index;
+			s1dValue = aS1DRegs_stn[i].Value;
+			debugk ("s13768 reg: %02x value: %02x\n",
+				aS1DRegs_stn[i].Index,
+				aS1DRegs_stn[i].Value);
+			((S1D_VALUE *) fb_info.RegAddr)[s1dReg / sizeof(S1D_VALUE)] =
 				s1dValue;
-	}
+		}
+		n = getenv_r ("contrast", tmp, sizeof (tmp));
+		((S1D_VALUE *) fb_info.RegAddr)[0xB3] =
+			(n > 0) ? (uchar) simple_strtoul (tmp, NULL, 10) * 255 / 100 : 0xA0;
+		switch (bd->bi_busfreq) {
+		case 40000000:
+			((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32;
+			((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x41;
+			break;
+		case 48000000:
+			((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x22;
+			((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x34;
+			break;
+		default:
+			printf ("KUP4K S1D1: unknown busfrequency: %ld assuming 64 MHz\n", bd->bi_busfreq);
+		case 64000000:
+			((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32;
+			((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x66;
+			break;
+		}
+		/*   setenv("lcd","stn"); */
+	} else {
+		for (i = 0; i < sizeof(aS1DRegs_tft) / sizeof(aS1DRegs_tft[0]); i++) {
+			s1dReg = aS1DRegs_tft[i].Index;
+			s1dValue = aS1DRegs_tft[i].Value;
+			debugk ("s13768 reg: %02x value: %02x\n",
+				aS1DRegs_tft[i].Index,
+				aS1DRegs_tft[i].Value);
+			((S1D_VALUE *) fb_info.RegAddr)[s1dReg / sizeof (S1D_VALUE)] =
+				s1dValue;
+		}
 
-#undef MONOCHROME
-#ifdef MONOCHROME
-	switch (bd->bi_busfreq) {
-#if 0
-	case 24000000:
-		((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32;
-		((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x28;
-		break;
-	case 32000000:
-		((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32;
-		((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x33;
-		break;
-#endif
-	case 40000000:
-		((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32;
-		((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x40;
-		break;
-	case 48000000:
-		((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32;
-		((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x4C;
-		break;
-	default:
-		printf ("KUP4K S1D1: unknown busfrequency: %ld assuming 64 MHz\n",
-				bd->bi_busfreq);
-	case 64000000:
-		((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32;
-		((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x69;
-		break;
+		switch (bd->bi_busfreq) {
+		default:
+			printf ("KUP4K S1D1: unknown busfrequency: %ld assuming 64 MHz\n", bd->bi_busfreq);
+		case 40000000:
+			((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x42;
+			((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x30;
+			break;
+		}
+		/* setenv("lcd","tft"); */
 	}
-	((S1D_VALUE *) fb_info.RegAddr)[0x10] = 0x00;
-#else
-	switch (bd->bi_busfreq) {
-#if 0
-	case 24000000:
-		((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x22;
-		((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x34;
-		break;
-	case 32000000:
-		((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32;
-		((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x34;
-		break;
-#endif
-	case 40000000:
-		((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32;
-		((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x41;
-		break;
-	case 48000000:
-		((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x22;
-		((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x34;
-		break;
-	default:
-		printf ("KUP4K S1D1: unknown busfrequency: %ld assuming 64 MHz\n",
-				bd->bi_busfreq);
-	case 64000000:
-		((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32;
-		((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x66;
-		break;
-	}
-#endif
-
 
 	/* create and set colormap */
 	rs = 256 / (r - 1);
@@ -384,27 +446,13 @@ void lcd_logo (bd_t * bd)
 		r1 = (rs * ((i / (g * b)) % r)) * 255;
 		g1 = (gs * ((i / b) % g)) * 255;
 		b1 = (bs * ((i) % b)) * 255;
-/*     printf("%d %04x %04x %04x\n",i,r1>>4,g1>>4,b1>>4); */
+		debugk ("%d %04x %04x %04x\n", i, r1 >> 4, g1 >> 4, b1 >> 4);
 		S1D_WRITE_PALETTE (fb_info.RegAddr, i, (r1 >> 4), (g1 >> 4),
-						   (b1 >> 4));
+				   (b1 >> 4));
 	}
 
 	/* copy bitmap */
 	fb = (char *) (fb_info.VmemAddr);
 	memcpy (fb, (uchar *) CONFIG_KUP4K_LOGO, 320 * 240);
 }
-#endif							/* CONFIG_KUP4K_LOGO */
-
-#ifdef CONFIG_IDE_LED
-void ide_led (uchar led, uchar status)
-{
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
-
-	/* We have one led for both pcmcia slots */
-	if (status) {				/* led on */
-		immap->im_ioport.iop_padat &= ~0x80;
-	} else {
-		immap->im_ioport.iop_padat |= 0x80;
-	}
-}
-#endif
+#endif	/* CONFIG_KUP4K_LOGO */

board/kup/kup4k/s1d13706.h

@@ -0,0 +1,174 @@
+/*---------------------------------------------------------------------------- */
+/* */
+/*  File generated by S1D13706CFG.EXE */
+/* */
+/*  Copyright (c) 2000,2001 Epson Research and Development, Inc. */
+/*  All rights reserved. */
+/* */
+/*---------------------------------------------------------------------------- */
+
+/* Panel: 320x240x8bpp 70Hz Color Single STN 8-bit (PCLK=6.250MHz) (Format 2) */
+
+#define S1D_DISPLAY_WIDTH           320
+#define S1D_DISPLAY_HEIGHT          240
+#define S1D_DISPLAY_BPP             8
+#define S1D_DISPLAY_SCANLINE_BYTES  320
+#define S1D_PHYSICAL_VMEM_ADDR      0x800A0000L
+#define S1D_PHYSICAL_VMEM_SIZE      0x14000L
+#define S1D_PHYSICAL_REG_ADDR       0x80080000L
+#define S1D_PHYSICAL_REG_SIZE       0x100
+#define S1D_DISPLAY_PCLK            6250
+#define S1D_PALETTE_SIZE            256
+#define S1D_REGDELAYOFF             0xFFFE
+#define S1D_REGDELAYON              0xFFFF
+
+#define S1D_WRITE_PALETTE(p,i,r,g,b)  \
+{  \
+    ((volatile S1D_VALUE*)(p))[0x0A/sizeof(S1D_VALUE)] = (S1D_VALUE)((r)>>4);  \
+    ((volatile S1D_VALUE*)(p))[0x09/sizeof(S1D_VALUE)] = (S1D_VALUE)((g)>>4);  \
+    ((volatile S1D_VALUE*)(p))[0x08/sizeof(S1D_VALUE)] = (S1D_VALUE)((b)>>4);  \
+    ((volatile S1D_VALUE*)(p))[0x0B/sizeof(S1D_VALUE)] = (S1D_VALUE)(i);  \
+}
+
+#define S1D_READ_PALETTE(p,i,r,g,b)  \
+{  \
+    ((volatile S1D_VALUE*)(p))[0x0F/sizeof(S1D_VALUE)] = (S1D_VALUE)(i);  \
+    r = ((volatile S1D_VALUE*)(p))[0x0E/sizeof(S1D_VALUE)];  \
+    g = ((volatile S1D_VALUE*)(p))[0x0D/sizeof(S1D_VALUE)];  \
+    b = ((volatile S1D_VALUE*)(p))[0x0C/sizeof(S1D_VALUE)];  \
+}
+
+typedef unsigned short S1D_INDEX;
+typedef unsigned char  S1D_VALUE;
+
+
+typedef struct
+{
+    S1D_INDEX Index;
+    S1D_VALUE Value;
+} S1D_REGS;
+
+
+static S1D_REGS aS1DRegs_prelimn[] =
+{
+    {0x10,0x00},   /* PANEL Type Register */
+    {0xA8,0x00},   /* GPIO Config Register 0 */
+    {0xA9,0x80},   /* GPIO Config Register 1 */
+
+};
+
+static S1D_REGS aS1DRegs_stn[] =
+{
+    {0x04,0x10},   /* BUSCLK MEMCLK Config Register */
+    {0x10,0xD0},   /* PANEL Type Register */
+    {0x11,0x00},   /* MOD Rate Register */
+    {0x14,0x27},   /* Horizontal Display Period Register */
+    {0x16,0x00},   /* Horizontal Display Period Start Pos Register 0 */
+    {0x17,0x00},   /* Horizontal Display Period Start Pos Register 1 */
+    {0x18,0xF0},   /* Vertical Total Register 0 */
+    {0x19,0x00},   /* Vertical Total Register 1 */
+    {0x1C,0xEF},   /* Vertical Display Period Register 0 */
+    {0x1D,0x00},   /* Vertical Display Period Register 1 */
+    {0x1E,0x00},   /* Vertical Display Period Start Pos Register 0 */
+    {0x1F,0x00},   /* Vertical Display Period Start Pos Register 1 */
+    {0x20,0x87},   /* Horizontal Sync Pulse Width Register */
+    {0x22,0x00},   /* Horizontal Sync Pulse Start Pos Register 0 */
+    {0x23,0x00},   /* Horizontal Sync Pulse Start Pos Register 1 */
+    {0x24,0x80},   /* Vertical Sync Pulse Width Register */
+    {0x26,0x01},   /* Vertical Sync Pulse Start Pos Register 0 */
+    {0x27,0x00},   /* Vertical Sync Pulse Start Pos Register 1 */
+    {0x70,0x83},   /* Display Mode Register */
+    {0x71,0x00},   /* Special Effects Register */
+    {0x74,0x00},   /* Main Window Display Start Address Register 0 */
+    {0x75,0x00},   /* Main Window Display Start Address Register 1 */
+    {0x76,0x00},   /* Main Window Display Start Address Register 2 */
+    {0x78,0x50},   /* Main Window Address Offset Register 0 */
+    {0x79,0x00},   /* Main Window Address Offset Register 1 */
+    {0x7C,0x00},   /* Sub Window Display Start Address Register 0 */
+    {0x7D,0x00},   /* Sub Window Display Start Address Register 1 */
+    {0x7E,0x00},   /* Sub Window Display Start Address Register 2 */
+    {0x80,0x50},   /* Sub Window Address Offset Register 0 */
+    {0x81,0x00},   /* Sub Window Address Offset Register 1 */
+    {0x84,0x00},   /* Sub Window X Start Pos Register 0 */
+    {0x85,0x00},   /* Sub Window X Start Pos Register 1 */
+    {0x88,0x00},   /* Sub Window Y Start Pos Register 0 */
+    {0x89,0x00},   /* Sub Window Y Start Pos Register 1 */
+    {0x8C,0x4F},   /* Sub Window X End Pos Register 0 */
+    {0x8D,0x00},   /* Sub Window X End Pos Register 1 */
+    {0x90,0xEF},   /* Sub Window Y End Pos Register 0 */
+    {0x91,0x00},   /* Sub Window Y End Pos Register 1 */
+    {0xA0,0x00},   /* Power Save Config Register */
+    {0xA1,0x00},   /* CPU Access Control Register */
+    {0xA2,0x00},   /* Software Reset Register */
+    {0xA3,0x00},   /* BIG Endian Support Register */
+    {0xA4,0x00},   /* Scratch Pad Register 0 */
+    {0xA5,0x00},   /* Scratch Pad Register 1 */
+    {0xA8,0x01},   /* GPIO Config Register 0 */
+    {0xA9,0x80},   /* GPIO Config Register 1 */
+    {0xAC,0x01},   /* GPIO Status Control Register 0 */
+    {0xAD,0x00},   /* GPIO Status Control Register 1 */
+    {0xB0,0x10},   /* PWM CV Clock Control Register */
+    {0xB1,0x80},   /* PWM CV Clock Config Register */
+    {0xB2,0x00},   /* CV Clock Burst Length Register */
+    {0xAD,0x80},   /* reset seq */
+    {0x70,0x03},
+};
+
+static S1D_REGS aS1DRegs_tft[] =
+{
+    {0x04,0x10},   /* BUSCLK MEMCLK Config Register */
+    {0x05,0x42},   /* PCLK Config  Register */
+    {0x10,0x61},   /* PANEL Type Register */
+    {0x11,0x00},   /* MOD Rate Register */
+    {0x12,0x30},   /* Horizontal Total Register */
+    {0x14,0x27},   /* Horizontal Display Period Register */
+    {0x16,0x11},   /* Horizontal Display Period Start Pos Register 0 */
+    {0x17,0x00},   /* Horizontal Display Period Start Pos Register 1 */
+    {0x18,0xFA},   /* Vertical Total Register 0 */
+    {0x19,0x00},   /* Vertical Total Register 1 */
+    {0x1C,0xEF},   /* Vertical Display Period Register 0 */
+    {0x1D,0x00},   /* Vertical Display Period Register 1 */
+    {0x1E,0x00},   /* Vertical Display Period Start Pos Register 0 */
+    {0x1F,0x00},   /* Vertical Display Period Start Pos Register 1 */
+    {0x20,0x07},   /* Horizontal Sync Pulse Width Register */
+    {0x22,0x00},   /* Horizontal Sync Pulse Start Pos Register 0 */
+    {0x23,0x00},   /* Horizontal Sync Pulse Start Pos Register 1 */
+    {0x24,0x00},   /* Vertical Sync Pulse Width Register */
+    {0x26,0x00},   /* Vertical Sync Pulse Start Pos Register 0 */
+    {0x27,0x00},   /* Vertical Sync Pulse Start Pos Register 1 */
+    {0x70,0x03},   /* Display Mode Register */
+    {0x71,0x00},   /* Special Effects Register */
+    {0x74,0x00},   /* Main Window Display Start Address Register 0 */
+    {0x75,0x00},   /* Main Window Display Start Address Register 1 */
+    {0x76,0x00},   /* Main Window Display Start Address Register 2 */
+    {0x78,0x50},   /* Main Window Address Offset Register 0 */
+    {0x79,0x00},   /* Main Window Address Offset Register 1 */
+    {0x7C,0x00},   /* Sub Window Display Start Address Register 0 */
+    {0x7D,0x00},   /* Sub Window Display Start Address Register 1 */
+    {0x7E,0x00},   /* Sub Window Display Start Address Register 2 */
+    {0x80,0x50},   /* Sub Window Address Offset Register 0 */
+    {0x81,0x00},   /* Sub Window Address Offset Register 1 */
+    {0x84,0x00},   /* Sub Window X Start Pos Register 0 */
+    {0x85,0x00},   /* Sub Window X Start Pos Register 1 */
+    {0x88,0x00},   /* Sub Window Y Start Pos Register 0 */
+    {0x89,0x00},   /* Sub Window Y Start Pos Register 1 */
+    {0x8C,0x4F},   /* Sub Window X End Pos Register 0 */
+    {0x8D,0x00},   /* Sub Window X End Pos Register 1 */
+    {0x90,0xEF},   /* Sub Window Y End Pos Register 0 */
+    {0x91,0x00},   /* Sub Window Y End Pos Register 1 */
+    {0xA0,0x00},   /* Power Save Config Register */
+    {0xA1,0x00},   /* CPU Access Control Register */
+    {0xA2,0x00},   /* Software Reset Register */
+    {0xA3,0x00},   /* BIG Endian Support Register */
+    {0xA4,0x00},   /* Scratch Pad Register 0 */
+    {0xA5,0x00},   /* Scratch Pad Register 1 */
+    {0xA8,0x01},   /* GPIO Config Register 0 */
+    {0xA9,0x80},   /* GPIO Config Register 1 */
+    {0xAC,0x01},   /* GPIO Status Control Register 0 */
+    {0xAD,0x00},   /* GPIO Status Control Register 1 */
+    {0xB0,0x10},   /* PWM CV Clock Control Register */
+    {0xB1,0x80},   /* PWM CV Clock Config Register */
+    {0xB2,0x00},   /* CV Clock Burst Length Register */
+    {0xAD,0x80},   /* reset seq */
+    {0x70,0x03},
+};

board/kup/kup4k/u-boot.lds

@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000-2002
+ * (C) Copyright 2000-2004
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -57,17 +57,17 @@ SECTIONS
     /* the sector layout of our flash chips!	XXX FIXME XXX	*/
 
     cpu/mpc8xx/start.o		(.text)
-    cpu/mpc8xx/traps.o		(.text)
-    common/dlmalloc.o		(.text)
-    lib_ppc/ppcstring.o		(.text)
+/*
+    cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_ppc/ppcstring.o	(.text)
     lib_generic/vsprintf.o	(.text)
     lib_generic/crc32.o		(.text)
     lib_generic/zlib.o		(.text)
-    lib_ppc/cache.o		(.text)
-    lib_ppc/time.o		(.text)
 
     . = env_offset;
-    common/environment.o	(.ppcenv)
+    common/environment.o(.text)
+*/
 
     *(.text)
     *(.fixup)

board/kup/kup4k/u-boot.lds.debug

@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000-2002
+ * (C) Copyright 2000-2004
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this

board/kup/kup4x/Makefile

@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o ../common/flash.o ../common/kup.o usb.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################

board/kup/kup4x/config.mk

@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# KUP4X board
+#
+
+TEXT_BASE = 0x40000000

board/kup/kup4x/kup4x.c

@@ -0,0 +1,311 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+#include "../common/kup.h"
+#ifdef CONFIG_KUP4K_LOGO
+/* #include "s1d13706.h" */
+#endif
+
+#define KUP4X_USB
+
+
+typedef struct {
+	volatile unsigned char *VmemAddr;
+	volatile unsigned char *RegAddr;
+} FB_INFO_S1D13xxx;
+
+/* ------------------------------------------------------------------------- */
+
+int usb_init_kup4x (void);
+
+
+#ifdef CONFIG_KUP4K_LOGO
+void lcd_logo (bd_t * bd);
+#endif
+
+/* ------------------------------------------------------------------------- */
+
+#define	_NOT_USED_	0xFFFFFFFF
+
+const uint sdram_table[] = {
+	/*
+	 * Single Read. (Offset 0 in UPMA RAM)
+	 */
+	0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
+	0x1FF77C47,		/* last */
+
+	/*
+	 * SDRAM Initialization (offset 5 in UPMA RAM)
+	 *
+	 * This is no UPM entry point. The following definition uses
+	 * the remaining space to establish an initialization
+	 * sequence, which is executed by a RUN command.
+	 *
+	 */
+	0x1FF77C35, 0xEFEABC34, 0x1FB57C35,	/* last */
+
+	/*
+	 * Burst Read. (Offset 8 in UPMA RAM)
+	 */
+	0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
+	0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47,	/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Single Write. (Offset 18 in UPMA RAM)
+	 */
+	0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47,	/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Burst Write. (Offset 20 in UPMA RAM)
+	 */
+	0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
+	0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47,	/* last */
+	_NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Refresh  (Offset 30 in UPMA RAM)
+	 */
+	0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
+	0xFFFFFC84, 0xFFFFFC07,	/* last */
+	_NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Exception. (Offset 3c in UPMA RAM)
+	 */
+	0x7FFFFC07,		/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+};
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	uchar *latch, rev, mod;
+
+	/*
+	 * Init ChipSelect #4 (CAN + HW-Latch)
+	 */
+	memctl->memc_or4 = 0xFFFF8926;
+	memctl->memc_br4 = 0x90000401;
+
+	latch = (uchar *) 0x90000200;
+	rev = (*latch & 0xF8) >> 3;
+	mod = (*latch & 0x03);
+	printf ("Board: KUP4X Rev %d.%d SN: %s\n", rev, mod,
+		getenv ("ethaddr"));
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size_b0 = 0;
+	long int size_b1 = 0;
+	long int size_b2 = 0;
+	long int size_b3 = 0;
+
+	upmconfig (UPMA, (uint *) sdram_table,
+		   sizeof (sdram_table) / sizeof (uint));
+	/*
+	 * Preliminary prescaler for refresh (depends on number of
+	 * banks): This value is selected for four cycles every 62.4 us
+	 * with two SDRAM banks or four cycles every 31.2 us with one
+	 * bank. It will be adjusted after memory sizing.
+	 */
+	memctl->memc_mptpr = CFG_MPTPR;
+
+	memctl->memc_mar = 0x00000088;
+
+	/*
+	 * Map controller banks 1 and 2 to the SDRAM banks 2 and 3 at
+	 * preliminary addresses - these have to be modified after the
+	 * SDRAM size has been determined.
+	 */
+/*	memctl->memc_or1 = CFG_OR1_PRELIM;	*/
+/*	memctl->memc_br1 = CFG_BR1_PRELIM;	*/
+
+/*	memctl->memc_or2 = CFG_OR2_PRELIM;	*/
+/*	memctl->memc_br2 = CFG_BR2_PRELIM;	*/
+
+	memctl->memc_mamr = CFG_MAMR & (~(MAMR_PTAE));	/* no refresh yet */
+
+	udelay (200);
+
+	/* perform SDRAM initializsation sequence */
+
+	memctl->memc_mcr = 0x80002105;	/* SDRAM bank 0 */
+	udelay (1);
+	memctl->memc_mcr = 0x80002830;	/* SDRAM bank 0 - execute twice */
+	udelay (1);
+	memctl->memc_mcr = 0x80002106;	/* SDRAM bank 0 - RUN MRS Pattern from loc 6 */
+	udelay (1);
+
+	memctl->memc_mcr = 0x80004105;	/* SDRAM bank 1 */
+	udelay (1);
+	memctl->memc_mcr = 0x80004830;	/* SDRAM bank 1 - execute twice */
+	udelay (1);
+	memctl->memc_mcr = 0x80004106;	/* SDRAM bank 1 - RUN MRS Pattern from loc 6 */
+	udelay (1);
+
+	memctl->memc_mcr = 0x80006105;	/* SDRAM bank 2 */
+	udelay (1);
+	memctl->memc_mcr = 0x80006830;	/* SDRAM bank 2 - execute twice */
+	udelay (1);
+	memctl->memc_mcr = 0x80006106;	/* SDRAM bank 2 - RUN MRS Pattern from loc 6 */
+	udelay (1);
+
+	memctl->memc_mcr = 0x8000C105;	/* SDRAM bank 2 */
+	udelay (1);
+	memctl->memc_mcr = 0x8000C830;	/* SDRAM bank 2 - execute twice */
+	udelay (1);
+	memctl->memc_mcr = 0x8000C106;	/* SDRAM bank 2 - RUN MRS Pattern from loc 6 */
+	udelay (1);
+
+	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
+	udelay (1000);
+#if 0				/* 4 x 8MB */
+	size_b0 = 0x00800000;
+	size_b1 = 0x00800000;
+	size_b2 = 0x00800000;
+	size_b3 = 0x00800000;
+	memctl->memc_mptpr = CFG_MPTPR;
+	udelay (1000);
+	memctl->memc_or1 = 0xFF800A00;
+	memctl->memc_br1 = 0x00000081;
+	memctl->memc_or2 = 0xFF000A00;
+	memctl->memc_br2 = 0x00800081;
+	memctl->memc_or3 = 0xFE000A00;
+	memctl->memc_br3 = 0x01000081;
+	memctl->memc_or6 = 0xFE000A00;
+	memctl->memc_br6 = 0x01800081;
+#else  /* 4 x 16 MB */
+	size_b0 = 0x01000000;
+	size_b1 = 0x01000000;
+	size_b2 = 0x01000000;
+	size_b3 = 0x01000000;
+	memctl->memc_mptpr = CFG_MPTPR;
+	udelay (1000);
+	memctl->memc_or1 = 0xFF000A00;
+	memctl->memc_br1 = 0x00000081;
+	memctl->memc_or2 = 0xFE000A00;
+	memctl->memc_br2 = 0x01000081;
+	memctl->memc_or3 = 0xFD000A00;
+	memctl->memc_br3 = 0x02000081;
+	memctl->memc_or6 = 0xFC000A00;
+	memctl->memc_br6 = 0x03000081;
+#endif
+	udelay (10000);
+
+	return (size_b0 + size_b1 + size_b2 + size_b3);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+#if 0
+static long int dram_size (long int mamr_value, long int *base,
+			   long int maxsize)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	volatile long int *addr;
+	ulong cnt, val;
+	ulong save[32];		/* to make test non-destructive */
+	unsigned char i = 0;
+
+	memctl->memc_mamr = mamr_value;
+
+	for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
+		addr = base + cnt;	/* pointer arith! */
+
+		save[i++] = *addr;
+		*addr = ~cnt;
+	}
+
+	/* write 0 to base address */
+	addr = base;
+	save[i] = *addr;
+	*addr = 0;
+
+	/* check at base address */
+	if ((val = *addr) != 0) {
+		*addr = save[i];
+		return (0);
+	}
+
+	for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
+		addr = base + cnt;	/* pointer arith! */
+
+		val = *addr;
+		*addr = save[--i];
+
+		if (val != (~cnt)) {
+			return (cnt * sizeof (long));
+		}
+	}
+	return (maxsize);
+}
+#endif
+
+int misc_init_r (void)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+
+#ifdef CONFIG_IDE_LED
+	/* Configure PA8 as output port */
+	immap->im_ioport.iop_padir |= 0x80;
+	immap->im_ioport.iop_paodr |= 0x80;
+	immap->im_ioport.iop_papar &= ~0x80;
+	immap->im_ioport.iop_padat |= 0x80;	/* turn it off */
+#endif
+#ifdef KUP4X_USB
+	usb_init_kup4x ();
+#endif
+	setenv ("hw", "4x");
+	poweron_key ();
+	return (0);
+}

board/kup/kup4x/u-boot.lds

@@ -0,0 +1,141 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)	}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)	}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)	}
+  .rela.got      : { *(.rela.got)	}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)	}
+  .rela.bss      : { *(.rela.bss)	}
+  .rel.plt       : { *(.rel.plt)	}
+  .rela.plt      : { *(.rela.plt)	}
+  .init          : { *(.init)		}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o		(.text)
+/*
+    cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_ppc/ppcstring.o	(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_generic/zlib.o		(.text)
+
+    . = env_offset;
+    common/environment.o(.text)
+*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}

board/kup/kup4x/u-boot.lds.debug

@@ -0,0 +1,135 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+
+    . = env_offset;
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}

board/kup/kup4x/usb.c

@@ -0,0 +1,81 @@
+/*
+ * (C) Copyright 2004
+ * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+#include "../common/kup.h"
+
+
+#define  SL811_ADR (0x50000000)
+#define  SL811_DAT (0x50000001)
+
+
+static void sl811_write_index_data (__u8 index, __u8 data)
+{
+	*(volatile unsigned char *) (SL811_ADR) = index;
+	__asm__ ("eieio");
+	*(volatile unsigned char *) (SL811_DAT) = data;
+	__asm__ ("eieio");
+}
+
+static __u8 sl811_read_index_data (__u8 index)
+{
+	__u8 data;
+
+	*(volatile unsigned char *) (SL811_ADR) = index;
+	__asm__ ("eieio");
+	data = *(volatile unsigned char *) (SL811_DAT);
+	__asm__ ("eieio");
+	return (data);
+}
+
+int usb_init_kup4x (void)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	int i;
+	unsigned char tmp;
+
+	memctl = &immap->im_memctl;
+	memctl->memc_or7 = 0xFFFF8726;
+	memctl->memc_br7 = 0x50000401;	/* start at 0x50000000 */
+	/* BP 14 low = USB ON */
+	immap->im_cpm.cp_pbdat &= ~(BP_USB_VCC);
+	/* PB 14 nomal port */
+	immap->im_cpm.cp_pbpar &= ~(BP_USB_VCC);
+	/* output */
+	immap->im_cpm.cp_pbdir |= (BP_USB_VCC);
+
+	puts ("USB:   ");
+
+	for (i = 0x10; i < 0xff; i++) {
+		sl811_write_index_data (i, i);
+		tmp = (sl811_read_index_data (i));
+		if (tmp != i) {
+			printf ("SL811 compare error index=0x%02x read=0x%02x\n", i, tmp);
+			return (-1);
+		}
+	}
+	printf ("SL811 ready\n");
+	return (0);
+}

board/kup4k/s1d13706.h

@@ -1,113 +0,0 @@
-/*---------------------------------------------------------------------------- */
-/* */
-/*  File generated by S1D13706CFG.EXE */
-/* */
-/*  Copyright (c) 2000,2001 Epson Research and Development, Inc. */
-/*  All rights reserved. */
-/* */
-/*---------------------------------------------------------------------------- */
-
-/* Panel: 320x240x8bpp 70Hz Color Single STN 8-bit (PCLK=6.250MHz) (Format 2) */
-
-#define S1D_DISPLAY_WIDTH           320
-#define S1D_DISPLAY_HEIGHT          240
-#define S1D_DISPLAY_BPP             8
-#define S1D_DISPLAY_SCANLINE_BYTES  320
-#define S1D_PHYSICAL_VMEM_ADDR      0x800A0000L
-#define S1D_PHYSICAL_VMEM_SIZE      0x14000L
-#define S1D_PHYSICAL_REG_ADDR       0x80080000L
-#define S1D_PHYSICAL_REG_SIZE       0x100
-#define S1D_DISPLAY_PCLK            6250
-#define S1D_PALETTE_SIZE            256
-#define S1D_REGDELAYOFF             0xFFFE
-#define S1D_REGDELAYON              0xFFFF
-
-#define S1D_WRITE_PALETTE(p,i,r,g,b)  \
-{  \
-    ((volatile S1D_VALUE*)(p))[0x0A/sizeof(S1D_VALUE)] = (S1D_VALUE)((r)>>4);  \
-    ((volatile S1D_VALUE*)(p))[0x09/sizeof(S1D_VALUE)] = (S1D_VALUE)((g)>>4);  \
-    ((volatile S1D_VALUE*)(p))[0x08/sizeof(S1D_VALUE)] = (S1D_VALUE)((b)>>4);  \
-    ((volatile S1D_VALUE*)(p))[0x0B/sizeof(S1D_VALUE)] = (S1D_VALUE)(i);  \
-}
-
-#define S1D_READ_PALETTE(p,i,r,g,b)  \
-{  \
-    ((volatile S1D_VALUE*)(p))[0x0F/sizeof(S1D_VALUE)] = (S1D_VALUE)(i);  \
-    r = ((volatile S1D_VALUE*)(p))[0x0E/sizeof(S1D_VALUE)];  \
-    g = ((volatile S1D_VALUE*)(p))[0x0D/sizeof(S1D_VALUE)];  \
-    b = ((volatile S1D_VALUE*)(p))[0x0C/sizeof(S1D_VALUE)];  \
-}
-
-typedef unsigned short S1D_INDEX;
-typedef unsigned char  S1D_VALUE;
-
-
-typedef struct
-{
-    S1D_INDEX Index;
-    S1D_VALUE Value;
-} S1D_REGS;
-
-static S1D_REGS aS1DRegs[] =
-{
-	{0x04,0x10},	/* BUSCLK MEMCLK Config Register */
-#if 0
-	{0x05,0x32},	/* PCLK Config  Register  */
-#endif
-	{0x10,0xD0},	/* PANEL Type Register */
-	{0x11,0x00},	/* MOD Rate Register */
-#if 0
-	{0x12,0x34},	/* Horizontal Total Register */
-#endif
-	{0x14,0x27},	/* Horizontal Display Period Register */
-	{0x16,0x00},	/* Horizontal Display Period Start Pos Register 0 */
-	{0x17,0x00},	/* Horizontal Display Period Start Pos Register 1 */
-	{0x18,0xF0},	/* Vertical Total Register 0  */
-	{0x19,0x00},	/* Vertical Total Register 1 */
-	{0x1C,0xEF},	/* Vertical Display Period Register 0 */
-	{0x1D,0x00},	/* Vertical Display Period Register 1 */
-	{0x1E,0x00},	/* Vertical Display Period Start Pos Register 0 */
-	{0x1F,0x00},	/* Vertical Display Period Start Pos Register 1 */
-	{0x20,0x87},	/* Horizontal Sync Pulse Width Register */
-	{0x22,0x00},	/* Horizontal Sync Pulse Start Pos Register 0 */
-	{0x23,0x00},	/* Horizontal Sync Pulse Start Pos Register 1 */
-	{0x24,0x80},	/* Vertical Sync Pulse Width Register */
-	{0x26,0x01},	/* Vertical Sync Pulse Start Pos Register 0 */
-	{0x27,0x00},	/* Vertical Sync Pulse Start Pos Register 1 */
-	{0x70,0x83},	/* Display Mode Register */
-	{0x71,0x00},	/* Special Effects Register */
-	{0x74,0x00},	/* Main Window Display Start Address Register 0 */
-	{0x75,0x00},	/* Main Window Display Start Address Register 1 */
-	{0x76,0x00},	/* Main Window Display Start Address Register 2 */
-	{0x78,0x50},	/* Main Window Address Offset Register 0 */
-	{0x79,0x00},	/* Main Window Address Offset Register 1 */
-	{0x7C,0x00},	/* Sub Window Display Start Address Register 0 */
-	{0x7D,0x00},	/* Sub Window Display Start Address Register 1 */
-	{0x7E,0x00},	/* Sub Window Display Start Address Register 2 */
-	{0x80,0x50},	/* Sub Window Address Offset Register 0 */
-	{0x81,0x00},	/* Sub Window Address Offset Register 1 */
-	{0x84,0x00},	/* Sub Window X Start Pos Register 0 */
-	{0x85,0x00},	/* Sub Window X Start Pos Register 1 */
-	{0x88,0x00},	/* Sub Window Y Start Pos Register 0 */
-	{0x89,0x00},	/* Sub Window Y Start Pos Register 1 */
-	{0x8C,0x4F},	/* Sub Window X End Pos Register 0 */
-	{0x8D,0x00},	/* Sub Window X End Pos Register 1 */
-	{0x90,0xEF},	/* Sub Window Y End Pos Register 0 */
-	{0x91,0x00},	/* Sub Window Y End Pos Register 1 */
-	{0xA0,0x00},	/* Power Save Config Register */
-	{0xA1,0x00},	/* CPU Access Control Register */
-	{0xA2,0x00},	/* Software Reset Register */
-	{0xA3,0x00},	/* BIG Endian Support Register */
-	{0xA4,0x00},	/* Scratch Pad Register 0 */
-	{0xA5,0x00},	/* Scratch Pad Register 1 */
-	{0xA8,0x01},	/* GPIO Config Register 0 */
-	{0xA9,0x80},	/* GPIO Config Register 1 */
-	{0xAC,0x01},	/* GPIO Status Control Register 0 */
-	{0xAD,0x00},	/* GPIO Status Control Register 1 */
-	{0xB0,0x10},	/* PWM CV Clock Control Register */
-	{0xB1,0x80},	/* PWM CV Clock Config Register */
-	{0xB2,0x00},	/* CV Clock Burst Length Register */
-	{0xB3,0xA0},	/* PWM Clock Duty Cycle Register */
-	{0xAD,0x80},	/* reset seq */
-	{0x70,0x03},	/*  */
-};

board/mpc8260ads/mpc8260ads.c

@@ -9,7 +9,7 @@
  * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
  * Added support for the 16M dram simm on the 8260ads boards
  *
- * (C) Copyright 2003 Arabella Software Ltd.
+ * (C) Copyright 2003-2004 Arabella Software Ltd.
  * Yuli Barcohen <yuli@arabellasw.com>
  * Added support for SDRAM DIMMs SPD EEPROM, MII, Ethernet PHY init.
  *
@@ -47,121 +47,137 @@
  * according to the five values podr/pdir/ppar/psor/pdat for that entry
  */
 
+#define CFG_FCC1 (CONFIG_ETHER_INDEX == 1)
+#define CFG_FCC2 (CONFIG_ETHER_INDEX == 2)
+#define CFG_FCC3 (CONFIG_ETHER_INDEX == 3)
+
 const iop_conf_t iop_conf_tab[4][32] = {
 
     /* Port A configuration */
-    {	/*	      conf ppar psor pdir podr pdat */
-	/* PA31 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxENB */
-	/* PA30 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 TxClav   */
-	/* PA29 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxSOC  */
-	/* PA28 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 RxENB */
-	/* PA27 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxSOC */
-	/* PA26 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxClav */
-	/* PA25 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[0] */
-	/* PA24 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[1] */
-	/* PA23 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[2] */
-	/* PA22 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[3] */
-	/* PA21 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[4] */
-	/* PA20 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[5] */
-	/* PA19 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[6] */
-	/* PA18 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[7] */
-	/* PA17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[7] */
-	/* PA16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[6] */
-	/* PA15 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[5] */
-	/* PA14 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[4] */
-	/* PA13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[3] */
-	/* PA12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[2] */
-	/* PA11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[1] */
-	/* PA10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[0] */
-	/* PA9  */ {   0,   1,   1,   1,   0,   0   }, /* FCC1 L1TXD */
-	/* PA8  */ {   0,   1,   1,   0,   0,   0   }, /* FCC1 L1RXD */
-	/* PA7  */ {   0,   0,   0,   1,   0,   0   }, /* PA7 */
-	/* PA6  */ {   1,   1,   1,   1,   0,   0   }, /* TDM A1 L1RSYNC */
-	/* PA5  */ {   0,   0,   0,   1,   0,   0   }, /* PA5 */
-	/* PA4  */ {   0,   0,   0,   1,   0,   0   }, /* PA4 */
-	/* PA3  */ {   0,   0,   0,   1,   0,   0   }, /* PA3 */
-	/* PA2  */ {   0,   0,   0,   1,   0,   0   }, /* PA2 */
-	/* PA1  */ {   1,   0,   0,   0,   0,   0   }, /* FREERUN */
-	/* PA0  */ {   0,   0,   0,   1,   0,   0   }  /* PA0 */
+    {	/*	      conf      ppar psor pdir podr pdat */
+	/* PA31 */ { CFG_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII COL   */
+	/* PA30 */ { CFG_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII CRS   */
+	/* PA29 */ { CFG_FCC1,   1,   1,   1,   0,   0 }, /* FCC1 MII TX_ER */
+	/* PA28 */ { CFG_FCC1,   1,   1,   1,   0,   0 }, /* FCC1 MII TX_EN */
+	/* PA27 */ { CFG_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII RX_DV */
+	/* PA26 */ { CFG_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII RX_ER */
+	/* PA25 */ { 0,          0,   0,   0,   0,   0 }, /* PA25 */
+	/* PA24 */ { 0,          0,   0,   0,   0,   0 }, /* PA24 */
+	/* PA23 */ { 0,          0,   0,   0,   0,   0 }, /* PA23 */
+	/* PA22 */ { 0,          0,   0,   0,   0,   0 }, /* PA22 */
+	/* PA21 */ { CFG_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[3] */
+	/* PA20 */ { CFG_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[2] */
+	/* PA19 */ { CFG_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[1] */
+	/* PA18 */ { CFG_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[0] */
+	/* PA17 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[0] */
+	/* PA16 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[1] */
+	/* PA15 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[2] */
+	/* PA14 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[3] */
+	/* PA13 */ { 0,          0,   0,   0,   0,   0 }, /* PA13 */
+	/* PA12 */ { 0,          0,   0,   0,   0,   0 }, /* PA12 */
+	/* PA11 */ { 0,          0,   0,   0,   0,   0 }, /* PA11 */
+	/* PA10 */ { 0,          0,   0,   0,   0,   0 }, /* PA10 */
+	/* PA9  */ { 0,          0,   0,   0,   0,   0 }, /* PA9 */
+	/* PA8  */ { 0,          0,   0,   0,   0,   0 }, /* PA8 */
+	/* PA7  */ { 0,          0,   0,   1,   0,   0 }, /* PA7 */
+	/* PA6  */ { 0,          0,   0,   0,   0,   0 }, /* PA6 */
+	/* PA5  */ { 0,          0,   0,   1,   0,   0 }, /* PA5 */
+	/* PA4  */ { 0,          0,   0,   1,   0,   0 }, /* PA4 */
+	/* PA3  */ { 0,          0,   0,   1,   0,   0 }, /* PA3 */
+	/* PA2  */ { 0,          0,   0,   1,   0,   0 }, /* PA2 */
+	/* PA1  */ { 0,          0,   0,   0,   0,   0 }, /* PA1 */
+	/* PA0  */ { 0,          0,   0,   1,   0,   0 }  /* PA0 */
     },
 
     /* Port B configuration */
-    {   /*	      conf ppar psor pdir podr pdat */
-	/* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
-	/* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
-	/* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
-	/* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
-	/* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
-	/* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
-	/* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
-	/* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
-	/* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
-	/* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
-	/* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
-	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
-	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
-	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
-	/* PB17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_DIV */
-	/* PB16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_ERR */
-	/* PB15 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_ERR */
-	/* PB14 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_EN */
-	/* PB13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:COL */
-	/* PB12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:CRS */
-	/* PB11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
-	/* PB10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
-	/* PB9  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
-	/* PB8  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
-	/* PB7  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
-	/* PB6  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
-	/* PB5  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
-	/* PB4  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
-	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    {   /*	      conf      ppar psor pdir podr pdat */
+	/* PB31 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TX_ER */
+	/* PB30 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RX_DV */
+	/* PB29 */ { CFG_FCC2,   1,   1,   1,   0,   0 }, /* FCC2 MII TX_EN */
+	/* PB28 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RX_ER */
+	/* PB27 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII COL */
+	/* PB26 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII CRS */
+	/* PB25 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[3] */
+	/* PB24 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[2] */
+	/* PB23 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[1] */
+	/* PB22 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[0] */
+	/* PB21 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[0] */
+	/* PB20 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[1] */
+	/* PB19 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[2] */
+	/* PB18 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[3] */
+	/* PB17 */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:RX_DIV */
+	/* PB16 */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:RX_ERR */
+	/* PB15 */ { CFG_FCC3,   1,   0,   1,   0,   0 }, /* FCC3:TX_ERR */
+	/* PB14 */ { CFG_FCC3,   1,   0,   1,   0,   0 }, /* FCC3:TX_EN */
+	/* PB13 */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:COL */
+	/* PB12 */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:CRS */
+	/* PB11 */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:RXD */
+	/* PB10 */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:RXD */
+	/* PB9  */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:RXD */
+	/* PB8  */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:RXD */
+	/* PB7  */ { CFG_FCC3,   1,   0,   1,   0,   0 }, /* FCC3:TXD */
+	/* PB6  */ { CFG_FCC3,   1,   0,   1,   0,   0 }, /* FCC3:TXD */
+	/* PB5  */ { CFG_FCC3,   1,   0,   1,   0,   0 }, /* FCC3:TXD */
+	/* PB4  */ { CFG_FCC3,   1,   0,   1,   0,   0 }, /* FCC3:TXD */
+	/* PB3  */ { 0,          0,   0,   0,   0,   0 }, /* pin doesn't exist */
+	/* PB2  */ { 0,          0,   0,   0,   0,   0 }, /* pin doesn't exist */
+	/* PB1  */ { 0,          0,   0,   0,   0,   0 }, /* pin doesn't exist */
+	/* PB0  */ { 0,          0,   0,   0,   0,   0 }  /* pin doesn't exist */
     },
 
     /* Port C */
-    {   /*	      conf ppar psor pdir podr pdat */
-	/* PC31 */ {   0,   0,   0,   1,   0,   0   }, /* PC31 */
-	/* PC30 */ {   0,   0,   0,   1,   0,   0   }, /* PC30 */
-	/* PC29 */ {   0,   1,   1,   0,   0,   0   }, /* SCC1 EN *CLSN */
-	/* PC28 */ {   0,   0,   0,   1,   0,   0   }, /* PC28 */
-	/* PC27 */ {   0,   0,   0,   1,   0,   0   }, /* UART Clock in */
-	/* PC26 */ {   0,   0,   0,   1,   0,   0   }, /* PC26 */
-	/* PC25 */ {   0,   0,   0,   1,   0,   0   }, /* PC25 */
-	/* PC24 */ {   0,   0,   0,   1,   0,   0   }, /* PC24 */
-	/* PC23 */ {   0,   1,   0,   1,   0,   0   }, /* ATMTFCLK */
-	/* PC22 */ {   0,   1,   0,   0,   0,   0   }, /* ATMRFCLK */
-	/* PC21 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN RXCLK */
-	/* PC20 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN TXCLK */
-	/* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII Rx Clock (CLK13) */
-	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII Tx Clock (CLK14) */
-	/* PC17 */ {   0,   0,   0,   1,   0,   0   }, /* PC17 */
-	/* PC16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK16) */
-	/* PC15 */ {   0,   0,   0,   1,   0,   0   }, /* PC15 */
-	/* PC14 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN *CD */
-	/* PC13 */ {   0,   0,   0,   1,   0,   0   }, /* PC13 */
-	/* PC12 */ {   0,   1,   0,   1,   0,   0   }, /* PC12 */
-	/* PC11 */ {   0,   0,   0,   1,   0,   0   }, /* LXT971 transmit control */
-	/* PC10 */ {   1,   0,   0,   1,   0,   0   }, /* LXT970 FETHMDC */
-	/* PC9  */ {   1,   0,   0,   0,   0,   0   }, /* LXT970 FETHMDIO */
-	/* PC8  */ {   0,   0,   0,   1,   0,   0   }, /* PC8 */
-	/* PC7  */ {   0,   0,   0,   1,   0,   0   }, /* PC7 */
-	/* PC6  */ {   0,   0,   0,   1,   0,   0   }, /* PC6 */
-	/* PC5  */ {   0,   0,   0,   1,   0,   0   }, /* PC5 */
-	/* PC4  */ {   0,   0,   0,   1,   0,   0   }, /* PC4 */
-	/* PC3  */ {   0,   0,   0,   1,   0,   0   }, /* PC3 */
-	/* PC2  */ {   0,   0,   0,   1,   0,   1   }, /* ENET FDE */
-	/* PC1  */ {   0,   0,   0,   1,   0,   0   }, /* ENET DSQE */
-	/* PC0  */ {   0,   0,   0,   1,   0,   0   }, /* ENET LBK */
+    {   /*	      conf      ppar psor pdir podr pdat */
+	/* PC31 */ { 0,          0,   0,   0,   0,   0 }, /* PC31 */
+	/* PC30 */ { 0,          0,   0,   0,   0,   0 }, /* PC30 */
+	/* PC29 */ { 0,          0,   0,   0,   0,   0 }, /* PC29 */
+	/* PC28 */ { 0,          0,   0,   0,   0,   0 }, /* PC28 */
+	/* PC27 */ { 0,          0,   0,   0,   0,   0 }, /* PC27 */
+	/* PC26 */ { 0,          0,   0,   0,   0,   0 }, /* PC26 */
+	/* PC25 */ { 0,          0,   0,   0,   0,   0 }, /* PC25 */
+	/* PC24 */ { 0,          0,   0,   0,   0,   0 }, /* PC24 */
+	/* PC23 */ { 0,          0,   0,   0,   0,   0 }, /* PC23 */
+	/* PC22 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII Tx Clock (CLK10) */
+	/* PC21 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII Rx Clock (CLK11) */
+	/* PC20 */ { 0,          0,   0,   0,   0,   0 }, /* PC20 */
+#if CONFIG_ADSTYPE == CFG_8272ADS
+	/* PC19 */ { 1,          0,   0,   1,   0,   0 }, /* FETHMDC  */
+	/* PC18 */ { 1,          0,   0,   0,   0,   0 }, /* FETHMDIO */
+	/* PC17 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII Rx Clock (CLK15) */
+	/* PC16 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII Tx Clock (CLK16) */
+#else
+	/* PC19 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII Rx Clock (CLK13) */
+	/* PC18 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII Tx Clock (CLK14) */
+	/* PC17 */ { 0,          0,   0,   0,   0,   0 }, /* PC17 */
+	/* PC16 */ { 0,          0,   0,   0,   0,   0 }, /* PC16 */
+#endif /* CONFIG_ADSTYPE == CFG_8272ADS */
+	/* PC15 */ { 0,          0,   0,   0,   0,   0 }, /* PC15 */
+	/* PC14 */ { 0,          0,   0,   0,   0,   0 }, /* PC14 */
+	/* PC13 */ { 0,          0,   0,   0,   0,   0 }, /* PC13 */
+	/* PC12 */ { 0,          0,   0,   0,   0,   0 }, /* PC12 */
+	/* PC11 */ { 0,          0,   0,   0,   0,   0 }, /* PC11 */
+#if CONFIG_ADSTYPE == CFG_8272ADS
+	/* PC10 */ { 0,          0,   0,   0,   0,   0 }, /* PC10 */
+	/* PC9  */ { 0,          0,   0,   0,   0,   0 }, /* PC9  */
+#else
+	/* PC10 */ { 1,          0,   0,   1,   0,   0 }, /* FETHMDC  */
+	/* PC9  */ { 1,          0,   0,   0,   0,   0 }, /* FETHMDIO */
+#endif /* CONFIG_ADSTYPE == CFG_8272ADS */
+	/* PC8  */ { 0,          0,   0,   0,   0,   0 }, /* PC8 */
+	/* PC7  */ { 0,          0,   0,   0,   0,   0 }, /* PC7 */
+	/* PC6  */ { 0,          0,   0,   0,   0,   0 }, /* PC6 */
+	/* PC5  */ { 0,          0,   0,   0,   0,   0 }, /* PC5 */
+	/* PC4  */ { 0,          0,   0,   0,   0,   0 }, /* PC4 */
+	/* PC3  */ { 0,          0,   0,   0,   0,   0 }, /* PC3 */
+	/* PC2  */ { 0,          0,   0,   0,   0,   0 }, /* PC2 */
+	/* PC1  */ { 0,          0,   0,   0,   0,   0 }, /* PC1 */
+	/* PC0  */ { 0,          0,   0,   0,   0,   0 }, /* PC0 */
     },
 
     /* Port D */
     {   /*	      conf ppar psor pdir podr pdat */
 	/* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 UART RxD */
 	/* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 UART TxD */
-	/* PD29 */ {   0,   1,   0,   1,   0,   0   }, /* SCC1 EN TENA */
+	/* PD29 */ {   0,   0,   0,   0,   0,   0   }, /* PD29 */
 	/* PD28 */ {   0,   1,   0,   0,   0,   0   }, /* PD28 */
 	/* PD27 */ {   0,   1,   1,   1,   0,   0   }, /* PD27 */
 	/* PD26 */ {   0,   0,   0,   1,   0,   0   }, /* PD26 */
@@ -198,19 +214,25 @@ void reset_phy (void)
 {
 	vu_long *bcsr = (vu_long *)CFG_BCSR;
 
-	/* reset the FEC port */
-	bcsr[1] &= ~FETH1_RST;
+	/* Reset the PHY */
+#if CFG_PHY_ADDR == 0
+	bcsr[1] &= ~(FETHIEN1 | FETH1_RST);
 	udelay(2);
 	bcsr[1] |=  FETH1_RST;
+#else
+	bcsr[3] &= ~(FETHIEN2 | FETH2_RST);
+	udelay(2);
+	bcsr[3] |=  FETH2_RST;
+#endif /* CFG_PHY_ADDR == 0 */
 	udelay(1000);
 #ifdef CONFIG_MII
-#if CONFIG_ADSTYPE == CFG_PQ2FADS
+#if CONFIG_ADSTYPE >= CFG_PQ2FADS
 	/*
 	 * Do not bypass Rx/Tx (de)scrambler (fix configuration error)
 	 * Enable autonegotiation.
 	 */
-	miiphy_write(0, 16, 0x610);
-	miiphy_write(0, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
+	miiphy_write(CFG_PHY_ADDR, 16, 0x610);
+	miiphy_write(CFG_PHY_ADDR, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
 #else
 	/*
 	 * Ethernet PHY is configured (by means of configuration pins)
@@ -218,9 +240,9 @@ void reset_phy (void)
 	 * to advertise all capabilities, including 100Mb/s, and
 	 * restart autonegotiation.
 	 */
-	miiphy_write(0, PHY_ANAR, 0x01E1); /* Advertise all capabilities */
-	miiphy_write(0, PHY_DCR,  0x0000); /* Do not bypass Rx/Tx (de)scrambler */
-	miiphy_write(0, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
+	miiphy_write(CFG_PHY_ADDR, PHY_ANAR, 0x01E1); /* Advertise all capabilities */
+	miiphy_write(CFG_PHY_ADDR, PHY_DCR,  0x0000); /* Do not bypass Rx/Tx (de)scrambler */
+	miiphy_write(CFG_PHY_ADDR, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
 #endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
 #endif /* CONFIG_MII */
 }
@@ -229,7 +251,12 @@ int board_early_init_f (void)
 {
 	vu_long *bcsr = (vu_long *)CFG_BCSR;
 
-	bcsr[1] = ~FETHIEN1 & ~RS232EN_1;
+#if (CONFIG_CONS_INDEX == 1) || (CONFIG_KGDB_INDEX == 1)
+	bcsr[1] &= ~RS232EN_1;
+#endif
+#if (CONFIG_CONS_INDEX > 1) || (CONFIG_KGDB_INDEX > 1)
+	bcsr[1] &= ~RS232EN_2;
+#endif
 
 #if CONFIG_ADSTYPE != CFG_8260ADS /* PCI mode can be selected */
 #if CONFIG_ADSTYPE == CFG_PQ2FADS
@@ -252,8 +279,10 @@ int board_early_init_f (void)
 
 long int initdram (int board_type)
 {
-#if CONFIG_ADSTYPE == CFG_PQ2FADS
+#if   CONFIG_ADSTYPE == CFG_PQ2FADS
 	long int msize = 32;
+#elif CONFIG_ADSTYPE == CFG_8272ADS
+	long int msize = 64;
 #else
 	long int msize = 16;
 #endif
@@ -470,6 +499,8 @@ int checkboard (void)
 	puts ("Board: Motorola MPC8266ADS\n");
 #elif CONFIG_ADSTYPE == CFG_PQ2FADS
 	puts ("Board: Motorola PQ2FADS-ZU\n");
+#elif CONFIG_ADSTYPE == CFG_8272ADS
+	puts ("Board: Motorola MPC8272ADS\n");
 #else
 	puts ("Board: unknown\n");
 #endif

board/netphone/Makefile

@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o phone_console.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################

board/netphone/config.mk

@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# netVia Boards
+#
+
+TEXT_BASE = 0x40000000

board/netphone/flash.c

@@ -0,0 +1,528 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(vu_long * addr, flash_info_t * info);
+static int write_byte(flash_info_t * info, ulong dest, uchar data);
+static void flash_get_offsets(ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init(void)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	unsigned long size;
+#if CONFIG_NETPHONE_VERSION == 2
+	unsigned long size1;
+#endif
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i)
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+
+	size = flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size, size << 20);
+	}
+
+	/* Remap FLASH according to real size */
+	memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size & 0xFFFF8000);
+	memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | (memctl->memc_br0 & ~(BR_BA_MSK));
+
+	/* Re-do sizing to get full correct info */
+	size = flash_get_size((vu_long *) CFG_FLASH_BASE, &flash_info[0]);
+
+	flash_get_offsets(CFG_FLASH_BASE, &flash_info[0]);
+
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+			CFG_FLASH_BASE, CFG_FLASH_BASE + monitor_flash_len - 1,
+			&flash_info[0]);
+
+	flash_protect ( FLAG_PROTECT_SET,
+			CFG_ENV_ADDR,
+			CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+			&flash_info[0]);
+
+#ifdef CFG_ENV_ADDR_REDUND
+	flash_protect ( FLAG_PROTECT_SET,
+			CFG_ENV_ADDR_REDUND,
+			CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1,
+			&flash_info[0]);
+#endif
+
+	flash_info[0].size = size;
+
+#if CONFIG_NETPHONE_VERSION == 2
+	size1 = flash_get_size((vu_long *) FLASH_BASE4_PRELIM, &flash_info[1]);
+
+	if (flash_info[1].flash_id == FLASH_UNKNOWN && size1 > 0) {
+		printf("## Unknown FLASH on Bank 1 - Size = 0x%08lx = %ld MB\n", size1, size1 << 20);
+	}
+
+	/* Remap FLASH according to real size */
+	memctl->memc_or4 = CFG_OR_TIMING_FLASH | (-size1 & 0xFFFF8000);
+	memctl->memc_br4 = (CFG_FLASH_BASE4 & BR_BA_MSK) | (memctl->memc_br4 & ~(BR_BA_MSK));
+
+	/* Re-do sizing to get full correct info */
+	size1 = flash_get_size((vu_long *) CFG_FLASH_BASE4, &flash_info[1]);
+
+	flash_get_offsets(CFG_FLASH_BASE4, &flash_info[1]);
+
+	size += size1;
+#endif
+
+	return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets(ulong base, flash_info_t * info)
+{
+	int i;
+
+	/* set up sector start address table */
+	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000);
+		}
+	} else if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type    */
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00004000;
+		info->start[2] = base + 0x00006000;
+		info->start[3] = base + 0x00008000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000) - 0x00030000;
+		}
+	} else {
+		/* set sector offsets for top boot block type       */
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00004000;
+		info->start[i--] = base + info->size - 0x00006000;
+		info->start[i--] = base + info->size - 0x00008000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00010000;
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info(flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:
+		printf("AMD ");
+		break;
+	case FLASH_MAN_FUJ:
+		printf("FUJITSU ");
+		break;
+	case FLASH_MAN_MX:
+		printf("MXIC ");
+		break;
+	default:
+		printf("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM040:
+		printf("AM29LV040B (4 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM400B:
+		printf("AM29LV400B (4 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM400T:
+		printf("AM29LV400T (4 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM800B:
+		printf("AM29LV800B (8 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM800T:
+		printf("AM29LV800T (8 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM160B:
+		printf("AM29LV160B (16 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM160T:
+		printf("AM29LV160T (16 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM320B:
+		printf("AM29LV320B (32 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM320T:
+		printf("AM29LV320T (32 Mbit, top boot sector)\n");
+		break;
+	default:
+		printf("Unknown Chip Type\n");
+		break;
+	}
+
+	printf("  Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count);
+
+	printf("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf("\n   ");
+		printf(" %08lX%s", info->start[i], info->protect[i] ? " (RO)" : "     ");
+	}
+	printf("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size(vu_long * addr, flash_info_t * info)
+{
+	short i;
+	uchar mid;
+	uchar pid;
+	vu_char *caddr = (vu_char *) addr;
+	ulong base = (ulong) addr;
+
+	/* Write auto select command: read Manufacturer ID */
+	caddr[0x0555] = 0xAA;
+	caddr[0x02AA] = 0x55;
+	caddr[0x0555] = 0x90;
+
+	mid = caddr[0];
+	switch (mid) {
+	case (AMD_MANUFACT & 0xFF):
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case (FUJ_MANUFACT & 0xFF):
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case (MX_MANUFACT & 0xFF):
+		info->flash_id = FLASH_MAN_MX;
+		break;
+	case (STM_MANUFACT & 0xFF):
+		info->flash_id = FLASH_MAN_STM;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);				/* no or unknown flash  */
+	}
+
+	pid = caddr[1];				/* device ID        */
+	switch (pid) {
+	case (AMD_ID_LV400T & 0xFF):
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;					/* => 512 kB        */
+
+	case (AMD_ID_LV400B & 0xFF):
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;					/* => 512 kB        */
+
+	case (AMD_ID_LV800T & 0xFF):
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;					/* => 1 MB      */
+
+	case (AMD_ID_LV800B & 0xFF):
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;					/* => 1 MB      */
+
+	case (AMD_ID_LV160T & 0xFF):
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;					/* => 2 MB      */
+
+	case (AMD_ID_LV160B & 0xFF):
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;					/* => 2 MB      */
+
+	case (AMD_ID_LV040B & 0xFF):
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x00080000;
+		break;
+
+	case (STM_ID_M29W040B & 0xFF):
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x00080000;
+		break;
+
+#if 0							/* enable when device IDs are available */
+	case (AMD_ID_LV320T & 0xFF):
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 67;
+		info->size = 0x00400000;
+		break;					/* => 4 MB      */
+
+	case (AMD_ID_LV320B & 0xFF):
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 67;
+		info->size = 0x00400000;
+		break;					/* => 4 MB      */
+#endif
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);				/* => no or unknown flash */
+
+	}
+
+	printf(" ");
+	/* set up sector start address table */
+	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000);
+		}
+	} else if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type    */
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00004000;
+		info->start[2] = base + 0x00006000;
+		info->start[3] = base + 0x00008000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000) - 0x00030000;
+		}
+	} else {
+		/* set sector offsets for top boot block type       */
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00004000;
+		info->start[i--] = base + info->size - 0x00006000;
+		info->start[i--] = base + info->size - 0x00008000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00010000;
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection: D0 = 1 if protected */
+		caddr = (volatile unsigned char *)(info->start[i]);
+		info->protect[i] = caddr[2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		caddr = (vu_char *) info->start[0];
+
+		caddr[0x0555] = 0xAA;
+		caddr[0x02AA] = 0x55;
+		caddr[0x0555] = 0xF0;
+
+		udelay(20000);
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+{
+	vu_char *addr = (vu_char *) (info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf("- missing\n");
+		} else {
+			printf("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    (info->flash_id > FLASH_AMD_COMP)) {
+		printf("Can't erase unknown flash type %08lx - aborted\n", info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf("- Warning: %d protected sectors will not be erased!\n", prot);
+	} else {
+		printf("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x0555] = 0xAA;
+	addr[0x02AA] = 0x55;
+	addr[0x0555] = 0x80;
+	addr[0x0555] = 0xAA;
+	addr[0x02AA] = 0x55;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (vu_char *) (info->start[sect]);
+			addr[0] = 0x30;
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay(1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer(0);
+	last = start;
+	addr = (vu_char *) (info->start[l_sect]);
+	while ((addr[0] & 0x80) != 0x80) {
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc('.');
+			last = now;
+		}
+	}
+
+DONE:
+	/* reset to read mode */
+	addr = (vu_char *) info->start[0];
+	addr[0] = 0xF0;				/* reset bank */
+
+	printf(" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	int rc;
+
+	while (cnt > 0) {
+		if ((rc = write_byte(info, addr++, *src++)) != 0) {
+			return (rc);
+		}
+		--cnt;
+	}
+
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_byte(flash_info_t * info, ulong dest, uchar data)
+{
+	vu_char *addr = (vu_char *) (info->start[0]);
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_char *) dest) & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x0555] = 0xAA;
+	addr[0x02AA] = 0x55;
+	addr[0x0555] = 0xA0;
+
+	*((vu_char *) dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer(0);
+	while ((*((vu_char *) dest) & 0x80) != (data & 0x80)) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+	return (0);
+}

board/netphone/netphone.c

@@ -0,0 +1,708 @@
+/*
+ * (C) Copyright 2000-2004
+ * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
+ * U-Boot port on NetTA4 board
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <sed156x.h>
+
+#include "mpc8xx.h"
+
+#ifdef CONFIG_HW_WATCHDOG
+#include <watchdog.h>
+#endif
+
+/****************************************************************/
+
+/* some sane bit macros */
+#define _BD(_b)				(1U << (31-(_b)))
+#define _BDR(_l, _h)			(((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1))
+
+#define _BW(_b)				(1U << (15-(_b)))
+#define _BWR(_l, _h)			(((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1))
+
+#define _BB(_b)				(1U << (7-(_b)))
+#define _BBR(_l, _h)			(((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1))
+
+#define _B(_b)				_BD(_b)
+#define _BR(_l, _h)			_BDR(_l, _h)
+
+/****************************************************************/
+
+/*
+ * Check Board Identity:
+ *
+ * Return 1 always.
+ */
+
+int checkboard(void)
+{
+	printf ("Intracom NetPhone V%d\n", CONFIG_NETPHONE_VERSION);
+	return (0);
+}
+
+/****************************************************************/
+
+#define _NOT_USED_	0xFFFFFFFF
+
+/****************************************************************/
+
+#define CS_0000		0x00000000
+#define CS_0001		0x10000000
+#define CS_0010		0x20000000
+#define CS_0011		0x30000000
+#define CS_0100		0x40000000
+#define CS_0101		0x50000000
+#define CS_0110		0x60000000
+#define CS_0111		0x70000000
+#define CS_1000		0x80000000
+#define CS_1001		0x90000000
+#define CS_1010		0xA0000000
+#define CS_1011		0xB0000000
+#define CS_1100		0xC0000000
+#define CS_1101		0xD0000000
+#define CS_1110		0xE0000000
+#define CS_1111		0xF0000000
+
+#define BS_0000		0x00000000
+#define BS_0001		0x01000000
+#define BS_0010		0x02000000
+#define BS_0011		0x03000000
+#define BS_0100		0x04000000
+#define BS_0101		0x05000000
+#define BS_0110		0x06000000
+#define BS_0111		0x07000000
+#define BS_1000		0x08000000
+#define BS_1001		0x09000000
+#define BS_1010		0x0A000000
+#define BS_1011		0x0B000000
+#define BS_1100		0x0C000000
+#define BS_1101		0x0D000000
+#define BS_1110		0x0E000000
+#define BS_1111		0x0F000000
+
+#define GPL0_AAAA	0x00000000
+#define GPL0_AAA0	0x00200000
+#define GPL0_AAA1	0x00300000
+#define GPL0_000A	0x00800000
+#define GPL0_0000	0x00A00000
+#define GPL0_0001	0x00B00000
+#define GPL0_111A	0x00C00000
+#define GPL0_1110	0x00E00000
+#define GPL0_1111	0x00F00000
+
+#define GPL1_0000	0x00000000
+#define GPL1_0001	0x00040000
+#define GPL1_1110	0x00080000
+#define GPL1_1111	0x000C0000
+
+#define GPL2_0000	0x00000000
+#define GPL2_0001	0x00010000
+#define GPL2_1110	0x00020000
+#define GPL2_1111	0x00030000
+
+#define GPL3_0000	0x00000000
+#define GPL3_0001	0x00004000
+#define GPL3_1110	0x00008000
+#define GPL3_1111	0x0000C000
+
+#define GPL4_0000	0x00000000
+#define GPL4_0001	0x00001000
+#define GPL4_1110	0x00002000
+#define GPL4_1111	0x00003000
+
+#define GPL5_0000	0x00000000
+#define GPL5_0001	0x00000400
+#define GPL5_1110	0x00000800
+#define GPL5_1111	0x00000C00
+#define LOOP		0x00000080
+
+#define EXEN		0x00000040
+
+#define AMX_COL		0x00000000
+#define AMX_ROW		0x00000020
+#define AMX_MAR		0x00000030
+
+#define NA		0x00000008
+
+#define UTA		0x00000004
+
+#define TODT		0x00000002
+
+#define LAST		0x00000001
+
+#define A10_AAAA	GPL0_AAAA
+#define A10_AAA0	GPL0_AAA0
+#define A10_AAA1	GPL0_AAA1
+#define A10_000A	GPL0_000A
+#define A10_0000	GPL0_0000
+#define A10_0001	GPL0_0001
+#define A10_111A	GPL0_111A
+#define A10_1110	GPL0_1110
+#define A10_1111	GPL0_1111
+
+#define RAS_0000	GPL1_0000
+#define RAS_0001	GPL1_0001
+#define RAS_1110	GPL1_1110
+#define RAS_1111	GPL1_1111
+
+#define CAS_0000	GPL2_0000
+#define CAS_0001	GPL2_0001
+#define CAS_1110	GPL2_1110
+#define CAS_1111	GPL2_1111
+
+#define WE_0000		GPL3_0000
+#define WE_0001		GPL3_0001
+#define WE_1110		GPL3_1110
+#define WE_1111		GPL3_1111
+
+/* #define CAS_LATENCY	3  */
+#define CAS_LATENCY	2
+
+const uint sdram_table[0x40] = {
+
+#if CAS_LATENCY == 3
+	/* RSS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,			/* READ  */
+	CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA,			/* PALL  */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,	/* NOP   */
+	_NOT_USED_, _NOT_USED_,
+
+	/* RBS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,			/* READ  */
+	CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP	 */
+	CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP	 */
+	CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL,				/* PALL  */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST,		/* NOP	 */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* WSS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP	 */
+	CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA,			/* WRITE */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA,			/* PALL  */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,	/* NOP   */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* WBS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL,				/* WRITE */
+	CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA,			/* PALL  */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,	/* NOP   */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+#endif
+
+#if CAS_LATENCY == 2
+	/* RSS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_0001 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,			/* READ  */
+	CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL,				/* NOP   */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,	/* PALL  */
+	_NOT_USED_,
+	_NOT_USED_, _NOT_USED_,
+
+	/* RBS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,			/* READ  */
+	CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1111 | BS_0001 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL,				/* NOP   */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,	/* PALL  */
+	_NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* WSS */
+	CS_0001 | BS_1111 | A10_AAA0 | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL,				/* NOP   */
+	CS_0000 | BS_0001 | A10_0001 | RAS_1110 | CAS_0001 | WE_0000 | AMX_COL | UTA,			/* WRITE */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,	/* PALL  */
+	_NOT_USED_,
+	_NOT_USED_, _NOT_USED_,
+	_NOT_USED_,
+
+	/* WBS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL,				/* NOP   */
+	CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0001 | AMX_COL,				/* WRITE */
+	CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1110 | BS_0001 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL | UTA,			/* NOP   */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,	/* PALL  */
+	_NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_,
+
+#endif
+
+	/* UPT */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | UTA | LOOP,		/* ATRFR */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | LOOP,		/* NOP   */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,	/* NOP   */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_,
+
+	/* EXC */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | LAST,
+	_NOT_USED_,
+
+	/* REG */
+	CS_1110 | BS_1111 | A10_1110 | RAS_1110 | CAS_1110 | WE_1110 | AMX_MAR | UTA,
+	CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | UTA | LAST,
+};
+
+#if CONFIG_NETPHONE_VERSION == 2
+static const uint nandcs_table[0x40] = {
+	/* RSS */
+	CS_1000 | GPL4_1111 | GPL5_1111 | UTA,
+	CS_0000 | GPL4_1110 | GPL5_1111 | UTA,
+	CS_0000 | GPL4_0000 | GPL5_1111 | UTA,
+	CS_0000 | GPL4_0000 | GPL5_1111 | UTA,
+	CS_0000 | GPL4_0000 | GPL5_1111,
+	CS_0000 | GPL4_0001 | GPL5_1111 | UTA,
+	CS_0000 | GPL4_1111 | GPL5_1111 | UTA,
+	CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST,	/* NOP   */
+
+	/* RBS */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* WSS */
+	CS_1000 | GPL4_1111 | GPL5_1110 | UTA,
+	CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
+	CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
+	CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
+	CS_0000 | GPL4_1111 | GPL5_0001 | UTA,
+	CS_0000 | GPL4_1111 | GPL5_1111 | UTA,
+	CS_0000 | GPL4_1111 | GPL5_1111,
+	CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST,
+
+	/* WBS */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* UPT */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_,	_NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_,	_NOT_USED_, _NOT_USED_,
+
+	/* EXC */
+	CS_0001 | LAST,
+	_NOT_USED_,
+
+	/* REG */
+	CS_1110 ,
+	CS_0001 | LAST,
+};
+#endif
+
+/* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */
+/* 0x88 = 0b10001000 , CAS2, >> 2 = 0b00 10 0 010 */
+#define MAR_SDRAM_INIT		((CAS_LATENCY << 6) | 0x00000008LU)
+
+/* 8 */
+#define CFG_MAMR	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+void check_ram(unsigned int addr, unsigned int size)
+{
+	unsigned int i, j, v, vv;
+	volatile unsigned int *p;
+	unsigned int pv;
+
+	p = (unsigned int *)addr;
+	pv = (unsigned int)p;
+	for (i = 0; i < size / sizeof(unsigned int); i++, pv += sizeof(unsigned int))
+		*p++ = pv;
+
+	p = (unsigned int *)addr;
+	for (i = 0; i < size / sizeof(unsigned int); i++) {
+		v = (unsigned int)p;
+		vv = *p;
+		if (vv != v) {
+			printf("%p: read %08x instead of %08x\n", p, vv, v);
+			hang();
+		}
+		p++;
+	}
+
+	for (j = 0; j < 5; j++) {
+		switch (j) {
+			case 0: v = 0x00000000; break;
+			case 1: v = 0xffffffff; break;
+			case 2: v = 0x55555555; break;
+			case 3: v = 0xaaaaaaaa; break;
+			default:v = 0xdeadbeef; break;
+		}
+		p = (unsigned int *)addr;
+		for (i = 0; i < size / sizeof(unsigned int); i++) {
+			*p = v;
+			vv = *p;
+			if (vv != v) {
+				printf("%p: read %08x instead of %08x\n", p, vv, v);
+				hang();
+			}
+			*p = ~v;
+			p++;
+		}
+	}
+}
+
+long int initdram(int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size;
+
+	upmconfig(UPMB, (uint *) sdram_table, sizeof(sdram_table) / sizeof(sdram_table[0]));
+
+	/*
+	 * Preliminary prescaler for refresh
+	 */
+	memctl->memc_mptpr = MPTPR_PTP_DIV8;
+
+	memctl->memc_mar = MAR_SDRAM_INIT;	/* 32-bit address to be output on the address bus if AMX = 0b11 */
+
+	/*
+	 * Map controller bank 3 to the SDRAM bank at preliminary address.
+	 */
+	memctl->memc_or3 = CFG_OR3_PRELIM;
+	memctl->memc_br3 = CFG_BR3_PRELIM;
+
+	memctl->memc_mbmr = CFG_MAMR & ~MAMR_PTAE;	/* no refresh yet */
+
+	udelay(200);
+
+	/* perform SDRAM initialisation sequence */
+	memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3C);	/* precharge all		*/
+	udelay(1);
+
+	memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(2) | MCR_MAD(0x30);	/* refresh 2 times(0)		*/
+	udelay(1);
+
+	memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3E);	/* exception program (write mar)*/
+	udelay(1);
+
+	memctl->memc_mbmr |= MAMR_PTAE;	/* enable refresh */
+
+	udelay(10000);
+
+	{
+		u32 d1, d2;
+
+		d1 = 0xAA55AA55;
+		*(volatile u32 *)0 = d1;
+		d2 = *(volatile u32 *)0;
+		if (d1 != d2) {
+			printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
+			hang();
+		}
+
+		d1 = 0x55AA55AA;
+		*(volatile u32 *)0 = d1;
+		d2 = *(volatile u32 *)0;
+		if (d1 != d2) {
+			printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
+			hang();
+		}
+	}
+
+	size = get_ram_size((long *)0, SDRAM_MAX_SIZE);
+
+	if (size == 0) {
+		printf("SIZE is zero: LOOP on 0\n");
+		for (;;) {
+			*(volatile u32 *)0 = 0;
+			(void)*(volatile u32 *)0;
+		}
+	}
+
+	return size;
+}
+
+/* ------------------------------------------------------------------------- */
+
+void reset_phys(void)
+{
+	int phyno;
+	unsigned short v;
+
+	udelay(10000);
+	/* reset the damn phys */
+	mii_init();
+
+	for (phyno = 0; phyno < 32; ++phyno) {
+		miiphy_read(phyno, PHY_PHYIDR1, &v);
+		if (v == 0xFFFF)
+			continue;
+		miiphy_write(phyno, PHY_BMCR, PHY_BMCR_POWD);
+		udelay(10000);
+		miiphy_write(phyno, PHY_BMCR, PHY_BMCR_RESET | PHY_BMCR_AUTON);
+		udelay(10000);
+	}
+}
+
+/* ------------------------------------------------------------------------- */
+
+/* GP = general purpose, SP = special purpose (on chip peripheral) */
+
+/* bits that can have a special purpose or can be configured as inputs/outputs */
+#define PA_GP_INMASK	0
+#define PA_GP_OUTMASK	(_BW(3) | _BW(7) | _BW(10) | _BW(14) | _BW(15))
+#define PA_SP_MASK	0
+#define PA_ODR_VAL	0
+#define PA_GP_OUTVAL	(_BW(3) | _BW(14) | _BW(15))
+#define PA_SP_DIRVAL	0
+
+#define PB_GP_INMASK	_B(28)
+#define PB_GP_OUTMASK	(_B(19) | _B(23) | _B(26) | _B(27) | _B(29) | _B(30))
+#define PB_SP_MASK	(_BR(22, 25))
+#define PB_ODR_VAL	0
+#define PB_GP_OUTVAL	(_B(26) | _B(27) | _B(29) | _B(30))
+#define PB_SP_DIRVAL	0
+
+#if CONFIG_NETPHONE_VERSION == 1
+#define PC_GP_INMASK	_BW(12)
+#define PC_GP_OUTMASK	(_BW(10) | _BW(11) | _BW(13) | _BW(15))
+#elif CONFIG_NETPHONE_VERSION == 2
+#define PC_GP_INMASK	(_BW(13) | _BW(15))
+#define PC_GP_OUTMASK	(_BW(10) | _BW(11) | _BW(12))
+#endif
+#define PC_SP_MASK	0
+#define PC_SOVAL	0
+#define PC_INTVAL	0
+#define PC_GP_OUTVAL	(_BW(10) | _BW(11))
+#define PC_SP_DIRVAL	0
+
+#if CONFIG_NETPHONE_VERSION == 1
+#define PE_GP_INMASK	_B(31)
+#define PE_GP_OUTMASK	(_B(17) | _B(18) |_B(20) | _B(24) | _B(27) | _B(28) | _B(29) | _B(30))
+#define PE_GP_OUTVAL	(_B(20) | _B(24) | _B(27) | _B(28))
+#elif CONFIG_NETPHONE_VERSION == 2
+#define PE_GP_INMASK	_BR(28, 31)
+#define PE_GP_OUTMASK	(_B(17) | _B(18) |_B(20) | _B(24) | _B(27))
+#define PE_GP_OUTVAL	(_B(20) | _B(24) | _B(27))
+#endif
+#define PE_SP_MASK	0
+#define PE_ODR_VAL	0
+#define PE_SP_DIRVAL	0
+
+int board_early_init_f(void)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile iop8xx_t *ioport = &immap->im_ioport;
+	volatile cpm8xx_t *cpm = &immap->im_cpm;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	/* NAND chip select */
+#if CONFIG_NETPHONE_VERSION == 1
+	memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_8_CLK | OR_EHTR | OR_TRLX);
+	memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
+#elif CONFIG_NETPHONE_VERSION == 2
+	upmconfig(UPMA, (uint *) nandcs_table, sizeof(nandcs_table) / sizeof(nandcs_table[0]));
+	memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_BI | OR_G5LS);
+	memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V | BR_MS_UPMA);
+	memctl->memc_mamr = 0;	/* all clear */
+#endif
+
+	/* DSP chip select */
+	memctl->memc_or2 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_ACS_DIV2 | OR_SETA | OR_TRLX);
+	memctl->memc_br2 = ((DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_V);
+
+#if CONFIG_NETPHONE_VERSION == 1
+	memctl->memc_br4 &= ~BR_V;
+#endif
+	memctl->memc_br5 &= ~BR_V;
+	memctl->memc_br6 &= ~BR_V;
+	memctl->memc_br7 &= ~BR_V;
+
+	ioport->iop_padat	= PA_GP_OUTVAL;
+	ioport->iop_paodr	= PA_ODR_VAL;
+	ioport->iop_padir	= PA_GP_OUTMASK | PA_SP_DIRVAL;
+	ioport->iop_papar	= PA_SP_MASK;
+
+	cpm->cp_pbdat		= PB_GP_OUTVAL;
+	cpm->cp_pbodr		= PB_ODR_VAL;
+	cpm->cp_pbdir		= PB_GP_OUTMASK | PB_SP_DIRVAL;
+	cpm->cp_pbpar		= PB_SP_MASK;
+
+	ioport->iop_pcdat	= PC_GP_OUTVAL;
+	ioport->iop_pcdir	= PC_GP_OUTMASK | PC_SP_DIRVAL;
+	ioport->iop_pcso	= PC_SOVAL;
+	ioport->iop_pcint	= PC_INTVAL;
+	ioport->iop_pcpar	= PC_SP_MASK;
+
+	cpm->cp_pedat		= PE_GP_OUTVAL;
+	cpm->cp_peodr		= PE_ODR_VAL;
+	cpm->cp_pedir		= PE_GP_OUTMASK | PE_SP_DIRVAL;
+	cpm->cp_pepar		= PE_SP_MASK;
+
+	return 0;
+}
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+
+#include <linux/mtd/nand.h>
+
+extern ulong nand_probe(ulong physadr);
+extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
+
+void nand_init(void)
+{
+	unsigned long totlen;
+
+	totlen = nand_probe(CFG_NAND_BASE);
+	printf ("%4lu MB\n", totlen >> 20);
+}
+#endif
+
+#ifdef CONFIG_HW_WATCHDOG
+
+void hw_watchdog_reset(void)
+{
+	/* XXX add here the really funky stuff */
+}
+
+#endif
+
+#ifdef CONFIG_SHOW_ACTIVITY
+
+static volatile int left_to_poll = PHONE_CONSOLE_POLL_HZ;	/* poll */
+
+/* called from timer interrupt every 1/CFG_HZ sec */
+void board_show_activity(ulong timestamp)
+{
+	if (left_to_poll > -PHONE_CONSOLE_POLL_HZ)
+		--left_to_poll;
+}
+
+extern void phone_console_do_poll(void);
+
+static void do_poll(void)
+{
+	unsigned int base;
+
+	while (left_to_poll <= 0) {
+		phone_console_do_poll();
+		base = left_to_poll + PHONE_CONSOLE_POLL_HZ;
+		do {
+			left_to_poll = base;
+		} while (base != left_to_poll);
+	}
+}
+
+/* called when looping */
+void show_activity(int arg)
+{
+	do_poll();
+}
+
+#endif
+
+#if defined(CFG_CONSOLE_IS_IN_ENV) && defined(CFG_CONSOLE_OVERWRITE_ROUTINE)
+int overwrite_console(void)
+{
+	/* printf("overwrite_console called\n"); */
+	return 0;
+}
+#endif
+
+extern int drv_phone_init(void);
+extern int drv_phone_use_me(void);
+
+int misc_init_r(void)
+{
+	return drv_phone_init();
+}
+
+int last_stage_init(void)
+{
+	int i;
+
+#if CONFIG_NETPHONE_VERSION == 2
+	/* assert peripheral reset */
+	((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat &= ~_BW(12);
+	for (i = 0; i < 10; i++)
+		udelay(1000);
+	((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat |=  _BW(12);
+#endif
+	reset_phys();
+
+	/* check in order to enable the local console */
+	left_to_poll = PHONE_CONSOLE_POLL_HZ;
+	i = CFG_HZ * 2;
+	while (i > 0) {
+
+	       	if (tstc()) {
+			getc();
+			break;
+		}
+
+		do_poll();
+
+		if (drv_phone_use_me()) {
+			console_assign(stdin, "phone");
+			console_assign(stdout, "phone");
+			console_assign(stderr, "phone");
+			setenv("bootdelay", "-1");
+			break;
+		}
+
+		udelay(1000000 / CFG_HZ);
+		i--;
+		left_to_poll--;
+	}
+	left_to_poll = PHONE_CONSOLE_POLL_HZ;
+
+	return 0;
+}

board/netphone/u-boot.lds

@@ -0,0 +1,138 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp		: { *(.interp)		}
+  .hash         : { *(.hash)		}
+  .dynsym       : { *(.dynsym)		}
+  .dynstr       : { *(.dynstr)		}
+  .rel.text     : { *(.rel.text)	}
+  .rela.text    : { *(.rela.text) 	}
+  .rel.data     : { *(.rel.data)	}
+  .rela.data    : { *(.rela.data) 	}
+  .rel.rodata   : { *(.rel.rodata) 	}
+  .rela.rodata  : { *(.rela.rodata)	}
+  .rel.got      : { *(.rel.got)		}
+  .rela.got     : { *(.rela.got)	}
+  .rel.ctors    : { *(.rel.ctors)	}
+  .rela.ctors   : { *(.rela.ctors)	}
+  .rel.dtors    : { *(.rel.dtors)	}
+  .rela.dtors   : { *(.rela.dtors)	}
+  .rel.bss      : { *(.rel.bss)		}
+  .rela.bss     : { *(.rela.bss)	}
+  .rel.plt      : { *(.rel.plt)		}
+  .rela.plt     : { *(.rela.plt)	}
+  .init         : { *(.init)		}
+  .plt			: { *(.plt) 		}
+  .text      	:
+  {
+    cpu/mpc8xx/start.o		(.text)
+    cpu/mpc8xx/traps.o		(.text)
+    common/dlmalloc.o		(.text)
+    lib_ppc/ppcstring.o		(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_generic/zlib.o		(.text)
+    lib_ppc/cache.o		(.text)
+    lib_ppc/time.o		(.text)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/environment.o	(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}

board/netphone/u-boot.lds.debug

@@ -0,0 +1,135 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o		(.text)
+    common/dlmalloc.o		(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+
+    . = env_offset;
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}

board/netta/Makefile

@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o dsp.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################

board/netta/config.mk

@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# netVia Boards
+#
+
+TEXT_BASE = 0x40000000

board/netta/flash.c

@@ -0,0 +1,508 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(vu_long * addr, flash_info_t * info);
+static int write_byte(flash_info_t * info, ulong dest, uchar data);
+static void flash_get_offsets(ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init(void)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	unsigned long size;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i)
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+
+	size = flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", size, size << 20);
+	}
+
+	/* Remap FLASH according to real size */
+	memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size & 0xFFFF8000);
+	memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | (memctl->memc_br0 & ~(BR_BA_MSK));
+
+	/* Re-do sizing to get full correct info */
+	size = flash_get_size((vu_long *) CFG_FLASH_BASE, &flash_info[0]);
+
+	flash_get_offsets(CFG_FLASH_BASE, &flash_info[0]);
+
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+			CFG_FLASH_BASE, CFG_FLASH_BASE + monitor_flash_len - 1,
+			&flash_info[0]);
+
+	flash_protect ( FLAG_PROTECT_SET,
+			CFG_ENV_ADDR,
+			CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+			&flash_info[0]);
+
+#ifdef CFG_ENV_ADDR_REDUND
+	flash_protect ( FLAG_PROTECT_SET,
+			CFG_ENV_ADDR_REDUND,
+			CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1,
+			&flash_info[0]);
+#endif
+
+
+	flash_info[0].size = size;
+
+	return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets(ulong base, flash_info_t * info)
+{
+	int i;
+
+	/* set up sector start address table */
+	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000);
+		}
+	} else if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type    */
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00004000;
+		info->start[2] = base + 0x00006000;
+		info->start[3] = base + 0x00008000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000) - 0x00030000;
+		}
+	} else {
+		/* set sector offsets for top boot block type       */
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00004000;
+		info->start[i--] = base + info->size - 0x00006000;
+		info->start[i--] = base + info->size - 0x00008000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00010000;
+		}
+	}
+
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info(flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:
+		printf("AMD ");
+		break;
+	case FLASH_MAN_FUJ:
+		printf("FUJITSU ");
+		break;
+	case FLASH_MAN_MX:
+		printf("MXIC ");
+		break;
+	default:
+		printf("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM040:
+		printf("AM29LV040B (4 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM400B:
+		printf("AM29LV400B (4 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM400T:
+		printf("AM29LV400T (4 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM800B:
+		printf("AM29LV800B (8 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM800T:
+		printf("AM29LV800T (8 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM160B:
+		printf("AM29LV160B (16 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM160T:
+		printf("AM29LV160T (16 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM320B:
+		printf("AM29LV320B (32 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM320T:
+		printf("AM29LV320T (32 Mbit, top boot sector)\n");
+		break;
+	default:
+		printf("Unknown Chip Type\n");
+		break;
+	}
+
+	printf("  Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count);
+
+	printf("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf("\n   ");
+		printf(" %08lX%s", info->start[i], info->protect[i] ? " (RO)" : "     ");
+	}
+	printf("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size(vu_long * addr, flash_info_t * info)
+{
+	short i;
+	uchar mid;
+	uchar pid;
+	vu_char *caddr = (vu_char *) addr;
+	ulong base = (ulong) addr;
+
+
+	/* Write auto select command: read Manufacturer ID */
+	caddr[0x0555] = 0xAA;
+	caddr[0x02AA] = 0x55;
+	caddr[0x0555] = 0x90;
+
+	mid = caddr[0];
+	switch (mid) {
+	case (AMD_MANUFACT & 0xFF):
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case (FUJ_MANUFACT & 0xFF):
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case (MX_MANUFACT & 0xFF):
+		info->flash_id = FLASH_MAN_MX;
+		break;
+	case (STM_MANUFACT & 0xFF):
+		info->flash_id = FLASH_MAN_STM;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);				/* no or unknown flash  */
+	}
+
+	pid = caddr[1];				/* device ID        */
+	switch (pid) {
+	case (AMD_ID_LV400T & 0xFF):
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;					/* => 512 kB        */
+
+	case (AMD_ID_LV400B & 0xFF):
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;					/* => 512 kB        */
+
+	case (AMD_ID_LV800T & 0xFF):
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;					/* => 1 MB      */
+
+	case (AMD_ID_LV800B & 0xFF):
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;					/* => 1 MB      */
+
+	case (AMD_ID_LV160T & 0xFF):
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;					/* => 2 MB      */
+
+	case (AMD_ID_LV160B & 0xFF):
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;					/* => 2 MB      */
+
+	case (AMD_ID_LV040B & 0xFF):
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x00080000;
+		break;
+
+	case (STM_ID_M29W040B & 0xFF):
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x00080000;
+		break;
+
+#if 0							/* enable when device IDs are available */
+	case (AMD_ID_LV320T & 0xFF):
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 67;
+		info->size = 0x00400000;
+		break;					/* => 4 MB      */
+
+	case (AMD_ID_LV320B & 0xFF):
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 67;
+		info->size = 0x00400000;
+		break;					/* => 4 MB      */
+#endif
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);				/* => no or unknown flash */
+
+	}
+
+	printf(" ");
+	/* set up sector start address table */
+	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000);
+		}
+	} else if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type    */
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00004000;
+		info->start[2] = base + 0x00006000;
+		info->start[3] = base + 0x00008000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000) - 0x00030000;
+		}
+	} else {
+		/* set sector offsets for top boot block type       */
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00004000;
+		info->start[i--] = base + info->size - 0x00006000;
+		info->start[i--] = base + info->size - 0x00008000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00010000;
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection: D0 = 1 if protected */
+		caddr = (volatile unsigned char *)(info->start[i]);
+		info->protect[i] = caddr[2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		caddr = (vu_char *) info->start[0];
+
+		caddr[0x0555] = 0xAA;
+		caddr[0x02AA] = 0x55;
+		caddr[0x0555] = 0xF0;
+
+		udelay(20000);
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+{
+	vu_char *addr = (vu_char *) (info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf("- missing\n");
+		} else {
+			printf("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    (info->flash_id > FLASH_AMD_COMP)) {
+		printf("Can't erase unknown flash type %08lx - aborted\n", info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf("- Warning: %d protected sectors will not be erased!\n", prot);
+	} else {
+		printf("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x0555] = 0xAA;
+	addr[0x02AA] = 0x55;
+	addr[0x0555] = 0x80;
+	addr[0x0555] = 0xAA;
+	addr[0x02AA] = 0x55;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (vu_char *) (info->start[sect]);
+			addr[0] = 0x30;
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay(1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer(0);
+	last = start;
+	addr = (vu_char *) (info->start[l_sect]);
+	while ((addr[0] & 0x80) != 0x80) {
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc('.');
+			last = now;
+		}
+	}
+
+  DONE:
+	/* reset to read mode */
+	addr = (vu_char *) info->start[0];
+	addr[0] = 0xF0;				/* reset bank */
+
+	printf(" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	int rc;
+
+	while (cnt > 0) {
+		if ((rc = write_byte(info, addr++, *src++)) != 0) {
+			return (rc);
+		}
+		--cnt;
+	}
+
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_byte(flash_info_t * info, ulong dest, uchar data)
+{
+	vu_char *addr = (vu_char *) (info->start[0]);
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_char *) dest) & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x0555] = 0xAA;
+	addr[0x02AA] = 0x55;
+	addr[0x0555] = 0xA0;
+
+	*((vu_char *) dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer(0);
+	while ((*((vu_char *) dest) & 0x80) != (data & 0x80)) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+	return (0);
+}

board/netta/netta.c

@@ -0,0 +1,575 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
+ * U-Boot port on NetTA4 board
+ */
+
+#include <common.h>
+#include <miiphy.h>
+
+#include "mpc8xx.h"
+
+#ifdef CONFIG_HW_WATCHDOG
+#include <watchdog.h>
+#endif
+
+/****************************************************************/
+
+/* some sane bit macros */
+#define _BD(_b)				(1U << (31-(_b)))
+#define _BDR(_l, _h)			(((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1))
+
+#define _BW(_b)				(1U << (15-(_b)))
+#define _BWR(_l, _h)			(((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1))
+
+#define _BB(_b)				(1U << (7-(_b)))
+#define _BBR(_l, _h)			(((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1))
+
+#define _B(_b)				_BD(_b)
+#define _BR(_l, _h)			_BDR(_l, _h)
+
+/****************************************************************/
+
+/*
+ * Check Board Identity:
+ *
+ * Return 1 always.
+ */
+
+int checkboard(void)
+{
+	printf ("Intracom NETTA"
+#if defined(CONFIG_NETTA_ISDN)
+			" with ISDN support"
+#endif
+			"\n"
+			);
+	return (0);
+}
+
+/****************************************************************/
+
+#define _NOT_USED_	0xFFFFFFFF
+
+/****************************************************************/
+
+#define CS_0000		0x00000000
+#define CS_0001		0x10000000
+#define CS_0010		0x20000000
+#define CS_0011		0x30000000
+#define CS_0100		0x40000000
+#define CS_0101		0x50000000
+#define CS_0110		0x60000000
+#define CS_0111		0x70000000
+#define CS_1000		0x80000000
+#define CS_1001		0x90000000
+#define CS_1010		0xA0000000
+#define CS_1011		0xB0000000
+#define CS_1100		0xC0000000
+#define CS_1101		0xD0000000
+#define CS_1110		0xE0000000
+#define CS_1111		0xF0000000
+
+#define BS_0000		0x00000000
+#define BS_0001		0x01000000
+#define BS_0010		0x02000000
+#define BS_0011		0x03000000
+#define BS_0100		0x04000000
+#define BS_0101		0x05000000
+#define BS_0110		0x06000000
+#define BS_0111		0x07000000
+#define BS_1000		0x08000000
+#define BS_1001		0x09000000
+#define BS_1010		0x0A000000
+#define BS_1011		0x0B000000
+#define BS_1100		0x0C000000
+#define BS_1101		0x0D000000
+#define BS_1110		0x0E000000
+#define BS_1111		0x0F000000
+
+#define A10_AAAA	0x00000000
+#define A10_AAA0	0x00200000
+#define A10_AAA1	0x00300000
+#define A10_000A	0x00800000
+#define A10_0000	0x00A00000
+#define A10_0001	0x00B00000
+#define A10_111A	0x00C00000
+#define A10_1110	0x00E00000
+#define A10_1111	0x00F00000
+
+#define RAS_0000	0x00000000
+#define RAS_0001	0x00040000
+#define RAS_1110	0x00080000
+#define RAS_1111	0x000C0000
+
+#define CAS_0000	0x00000000
+#define CAS_0001	0x00010000
+#define CAS_1110	0x00020000
+#define CAS_1111	0x00030000
+
+#define WE_0000		0x00000000
+#define WE_0001		0x00004000
+#define WE_1110		0x00008000
+#define WE_1111		0x0000C000
+
+#define GPL4_0000	0x00000000
+#define GPL4_0001	0x00001000
+#define GPL4_1110	0x00002000
+#define GPL4_1111	0x00003000
+
+#define GPL5_0000	0x00000000
+#define GPL5_0001	0x00000400
+#define GPL5_1110	0x00000800
+#define GPL5_1111	0x00000C00
+#define LOOP		0x00000080
+
+#define EXEN		0x00000040
+
+#define AMX_COL		0x00000000
+#define AMX_ROW		0x00000020
+#define AMX_MAR		0x00000030
+
+#define NA		0x00000008
+
+#define UTA		0x00000004
+
+#define TODT		0x00000002
+
+#define LAST		0x00000001
+
+/* #define CAS_LATENCY	3 */
+#define CAS_LATENCY	2
+
+const uint sdram_table[0x40] = {
+
+#if CAS_LATENCY == 3
+	/* RSS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,			/* READ  */
+	CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA,			/* PALL  */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,	/* NOP   */
+	_NOT_USED_, _NOT_USED_,
+
+	/* RBS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,			/* READ  */
+	CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP	 */
+	CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP	 */
+	CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL,				/* PALL  */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST,		/* NOP	 */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* WSS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP	 */
+	CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA,			/* WRITE */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA,			/* PALL  */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,	/* NOP   */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* WBS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL,				/* WRITE */
+	CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA,			/* PALL  */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,	/* NOP   */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+#endif
+
+#if CAS_LATENCY == 2
+	/* RSS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_0001 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,			/* READ  */
+	CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL,				/* NOP   */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,	/* PALL  */
+	_NOT_USED_,
+	_NOT_USED_, _NOT_USED_,
+
+	/* RBS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,			/* READ  */
+	CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1111 | BS_0001 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL,				/* NOP   */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,	/* PALL  */
+	_NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* WSS */
+	CS_0001 | BS_1111 | A10_AAA0 | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL,				/* NOP   */
+	CS_0000 | BS_0001 | A10_0001 | RAS_1110 | CAS_0001 | WE_0000 | AMX_COL | UTA,			/* WRITE */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,	/* PALL  */
+	_NOT_USED_,
+	_NOT_USED_, _NOT_USED_,
+	_NOT_USED_,
+
+	/* WBS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL,				/* NOP   */
+	CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0001 | AMX_COL,				/* WRITE */
+	CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1110 | BS_0001 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL | UTA,			/* NOP   */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,	/* PALL  */
+	_NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_,
+
+#endif
+
+	/* UPT */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | UTA | LOOP,		/* ATRFR */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | LOOP,		/* NOP   */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,	/* NOP   */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_,
+
+	/* EXC */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | LAST,
+	_NOT_USED_,
+
+	/* REG */
+	CS_1110 | BS_1111 | A10_1110 | RAS_1110 | CAS_1110 | WE_1110 | AMX_MAR | UTA,
+	CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | UTA | LAST,
+};
+
+/* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */
+/* 0x88 = 0b10001000 , CAS2, >> 2 = 0b00 10 0 010 */
+#define MAR_SDRAM_INIT		((CAS_LATENCY << 6) | 0x00000008LU)
+
+/* 8 */
+#define CFG_MAMR	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+void check_ram(unsigned int addr, unsigned int size)
+{
+	unsigned int i, j, v, vv;
+	volatile unsigned int *p;
+	unsigned int pv;
+
+	p = (unsigned int *)addr;
+	pv = (unsigned int)p;
+	for (i = 0; i < size / sizeof(unsigned int); i++, pv += sizeof(unsigned int))
+		*p++ = pv;
+
+	p = (unsigned int *)addr;
+	for (i = 0; i < size / sizeof(unsigned int); i++) {
+		v = (unsigned int)p;
+		vv = *p;
+		if (vv != v) {
+			printf("%p: read %08x instead of %08x\n", p, vv, v);
+			hang();
+		}
+		p++;
+	}
+
+	for (j = 0; j < 5; j++) {
+		switch (j) {
+			case 0: v = 0x00000000; break;
+			case 1: v = 0xffffffff; break;
+			case 2: v = 0x55555555; break;
+			case 3: v = 0xaaaaaaaa; break;
+			default:v = 0xdeadbeef; break;
+		}
+		p = (unsigned int *)addr;
+		for (i = 0; i < size / sizeof(unsigned int); i++) {
+			*p = v;
+			vv = *p;
+			if (vv != v) {
+				printf("%p: read %08x instead of %08x\n", p, vv, v);
+				hang();
+			}
+			*p = ~v;
+			p++;
+		}
+	}
+}
+
+long int initdram(int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size;
+
+	upmconfig(UPMB, (uint *) sdram_table, sizeof(sdram_table) / sizeof(uint));
+
+	/*
+	 * Preliminary prescaler for refresh
+	 */
+	memctl->memc_mptpr = MPTPR_PTP_DIV8;
+
+	memctl->memc_mar = MAR_SDRAM_INIT;	/* 32-bit address to be output on the address bus if AMX = 0b11 */
+
+	/*
+	 * Map controller bank 3 to the SDRAM bank at preliminary address.
+	 */
+	memctl->memc_or3 = CFG_OR3_PRELIM;
+	memctl->memc_br3 = CFG_BR3_PRELIM;
+
+	memctl->memc_mbmr = CFG_MAMR & ~MAMR_PTAE;	/* no refresh yet */
+
+	udelay(200);
+
+	/* perform SDRAM initialisation sequence */
+	memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3C);	/* precharge all		*/
+	udelay(1);
+
+	memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(2) | MCR_MAD(0x30);	/* refresh 2 times(0)		*/
+	udelay(1);
+
+	memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3E);	/* exception program (write mar)*/
+	udelay(1);
+
+	memctl->memc_mbmr |= MAMR_PTAE;	/* enable refresh */
+
+	udelay(10000);
+
+	{
+		u32 d1, d2;
+
+		d1 = 0xAA55AA55;
+		*(volatile u32 *)0 = d1;
+		d2 = *(volatile u32 *)0;
+		if (d1 != d2) {
+			printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
+			hang();
+		}
+
+		d1 = 0x55AA55AA;
+		*(volatile u32 *)0 = d1;
+		d2 = *(volatile u32 *)0;
+		if (d1 != d2) {
+			printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
+			hang();
+		}
+	}
+
+	size = get_ram_size((long *)0, SDRAM_MAX_SIZE);
+
+#if 0
+	printf("check 0\n");
+	check_ram(( 0 << 20), (2 << 20));
+	printf("check 16\n");
+	check_ram((16 << 20), (2 << 20));
+	printf("check 32\n");
+	check_ram((32 << 20), (2 << 20));
+	printf("check 48\n");
+	check_ram((48 << 20), (2 << 20));
+#endif
+
+	if (size == 0) {
+		printf("SIZE is zero: LOOP on 0\n");
+		for (;;) {
+			*(volatile u32 *)0 = 0;
+			(void)*(volatile u32 *)0;
+		}
+	}
+
+	return size;
+}
+
+/* ------------------------------------------------------------------------- */
+
+int misc_init_r(void)
+{
+	return(0);
+}
+
+void reset_phys(void)
+{
+	int phyno;
+	unsigned short v;
+
+	/* reset the damn phys */
+	mii_init();
+
+	for (phyno = 0; phyno < 32; ++phyno) {
+		miiphy_read(phyno, PHY_PHYIDR1, &v);
+		if (v == 0xFFFF)
+			continue;
+		miiphy_write(phyno, PHY_BMCR, PHY_BMCR_POWD);
+		udelay(10000);
+		miiphy_write(phyno, PHY_BMCR, PHY_BMCR_RESET | PHY_BMCR_AUTON);
+		udelay(10000);
+	}
+}
+
+extern int board_dsp_reset(void);
+
+int last_stage_init(void)
+{
+	int r;
+
+	reset_phys();
+	r = board_dsp_reset();
+	if (r < 0)
+		printf("*** WARNING *** DSP reset failed (run diagnostics)\n");
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+/* GP = general purpose, SP = special purpose (on chip peripheral) */
+
+/* bits that can have a special purpose or can be configured as inputs/outputs */
+#define PA_GP_INMASK	(_BWR(3) | _BWR(7, 9) | _BW(11))
+#define PA_GP_OUTMASK	(_BW(6) | _BW(10) | _BWR(12, 15))
+#define PA_SP_MASK	(_BWR(0, 2) | _BWR(4, 5))
+#define PA_ODR_VAL	0
+#define PA_GP_OUTVAL	(_BW(13) | _BWR(14, 15))
+#define PA_SP_DIRVAL	0
+
+#define PB_GP_INMASK	(_B(28) | _B(31))
+#define PB_GP_OUTMASK	(_BR(16, 19) | _BR(26, 27) | _BR(29, 30))
+#define PB_SP_MASK	(_BR(22, 25))
+#define PB_ODR_VAL	0
+#define PB_GP_OUTVAL	(_BR(16, 19) | _BR(26, 27) | _BR(29, 31))
+#define PB_SP_DIRVAL	0
+
+#define PC_GP_INMASK	(_BW(5) | _BW(7) | _BW(8) | _BWR(9, 11) | _BWR(13, 15))
+#define PC_GP_OUTMASK	(_BW(6) | _BW(12))
+#define PC_SP_MASK	(_BW(4) | _BW(8))
+#define PC_SOVAL	0
+#define PC_INTVAL	_BW(7)
+#define PC_GP_OUTVAL	(_BW(6) | _BW(12))
+#define PC_SP_DIRVAL	0
+
+#define PD_GP_INMASK	0
+#define PD_GP_OUTMASK	_BWR(3, 15)
+#define PD_SP_MASK	0
+#define PD_GP_OUTVAL	(_BWR(5, 7) | _BW(9) | _BW(11))
+#define PD_SP_DIRVAL	0
+
+int board_early_init_f(void)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile iop8xx_t *ioport = &immap->im_ioport;
+	volatile cpm8xx_t *cpm = &immap->im_cpm;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	/* CS1: NAND chip select */
+	memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_BI | OR_SCY_2_CLK | OR_TRLX | OR_ACS_DIV2) ;
+	memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
+
+	/* CS2: DSP */
+	memctl->memc_or2 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_7_CLK | OR_ACS_DIV2);
+	memctl->memc_br2 = ((DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_V);
+
+	/* CS4: External register chip select */
+	memctl->memc_or4 = ((0xFFFFFFFFLU & ~(ER_SIZE - 1)) | OR_BI | OR_SCY_4_CLK);
+	memctl->memc_br4 = ((ER_BASE & BR_BA_MSK) | BR_PS_32 | BR_V);
+
+	/* CS5: dummy for accurate delay */
+	memctl->memc_or5 = ((0xFFFFFFFFLU & ~(DUMMY_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_0_CLK | OR_ACS_DIV2);
+	memctl->memc_br5 = ((DUMMY_BASE & BR_BA_MSK) | BR_PS_32 | BR_V);
+
+	ioport->iop_padat	= PA_GP_OUTVAL;
+	ioport->iop_paodr	= PA_ODR_VAL;
+	ioport->iop_padir	= PA_GP_OUTMASK | PA_SP_DIRVAL;
+	ioport->iop_papar	= PA_SP_MASK;
+
+	cpm->cp_pbdat		= PB_GP_OUTVAL;
+	cpm->cp_pbodr		= PB_ODR_VAL;
+	cpm->cp_pbdir		= PB_GP_OUTMASK | PB_SP_DIRVAL;
+	cpm->cp_pbpar		= PB_SP_MASK;
+
+	ioport->iop_pcdat	= PC_GP_OUTVAL;
+	ioport->iop_pcdir	= PC_GP_OUTMASK | PC_SP_DIRVAL;
+	ioport->iop_pcso	= PC_SOVAL;
+	ioport->iop_pcint	= PC_INTVAL;
+	ioport->iop_pcpar	= PC_SP_MASK;
+
+	ioport->iop_pddat	= PD_GP_OUTVAL;
+	ioport->iop_pddir	= PD_GP_OUTMASK | PD_SP_DIRVAL;
+	ioport->iop_pdpar	= PD_SP_MASK;
+
+	ioport->iop_pddat |=  (1 << (15 - 6)) | (1 << (15 - 7));
+
+	return 0;
+}
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+
+#include <linux/mtd/nand.h>
+
+extern ulong nand_probe(ulong physadr);
+extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
+
+void nand_init(void)
+{
+	unsigned long totlen = nand_probe(CFG_NAND_BASE);
+
+	printf ("%4lu MB\n", totlen >> 20);
+}
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
+
+int pcmcia_init(void)
+{
+	return 0;
+}
+
+#endif
+
+#ifdef CONFIG_POST
+/*
+ * Returns 1 if keys pressed to start the power-on long-running tests
+ * Called from board_init_f().
+ */
+int post_hotkeys_pressed(void)
+{
+	return 0;	/* No hotkeys supported */
+}
+#endif
+
+#ifdef CONFIG_HW_WATCHDOG
+
+void hw_watchdog_reset(void)
+{
+	/* XXX add here the really funky stuff */
+}
+
+#endif

board/netta/u-boot.lds

@@ -0,0 +1,138 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp		: { *(.interp)		}
+  .hash         : { *(.hash)		}
+  .dynsym       : { *(.dynsym)		}
+  .dynstr       : { *(.dynstr)		}
+  .rel.text     : { *(.rel.text)	}
+  .rela.text    : { *(.rela.text) 	}
+  .rel.data     : { *(.rel.data)	}
+  .rela.data    : { *(.rela.data) 	}
+  .rel.rodata   : { *(.rel.rodata) 	}
+  .rela.rodata  : { *(.rela.rodata)	}
+  .rel.got      : { *(.rel.got)		}
+  .rela.got     : { *(.rela.got)	}
+  .rel.ctors    : { *(.rel.ctors)	}
+  .rela.ctors   : { *(.rela.ctors)	}
+  .rel.dtors    : { *(.rel.dtors)	}
+  .rela.dtors   : { *(.rela.dtors)	}
+  .rel.bss      : { *(.rel.bss)		}
+  .rela.bss     : { *(.rela.bss)	}
+  .rel.plt      : { *(.rel.plt)		}
+  .rela.plt     : { *(.rela.plt)	}
+  .init         : { *(.init)		}
+  .plt			: { *(.plt) 		}
+  .text      	:
+  {
+    cpu/mpc8xx/start.o		(.text)
+    cpu/mpc8xx/traps.o		(.text)
+    common/dlmalloc.o		(.text)
+    lib_ppc/ppcstring.o		(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_generic/zlib.o		(.text)
+    lib_ppc/cache.o		(.text)
+    lib_ppc/time.o		(.text)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/environment.o	(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}

board/netta/u-boot.lds.debug

@@ -0,0 +1,135 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o		(.text)
+    common/dlmalloc.o		(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+
+    . = env_offset;
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}

board/pm520/Makefile

@@ -0,0 +1,47 @@
+
+#
+# (C) Copyright 2003-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o flash.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################

board/pm520/config.mk

@@ -0,0 +1,31 @@
+#
+# (C) Copyright 2003-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# PM520 board
+#
+
+TEXT_BASE = 0xfff00000
+# TEXT_BASE = 0x00100000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board

board/pm520/flash.c

@@ -0,0 +1,545 @@
+/*
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+
+/* Board support for 1 or 2 flash devices */
+#define FLASH_PORT_WIDTH32
+#undef FLASH_PORT_WIDTH16
+
+#ifdef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH		ushort
+#define FLASH_PORT_WIDTHV		vu_short
+#define SWAP(x)               		(x)
+#else
+#define FLASH_PORT_WIDTH		ulong
+#define FLASH_PORT_WIDTHV		vu_long
+#define SWAP(x)               		(x)
+#endif
+
+/* Intel-compatible flash ID */
+#define INTEL_COMPAT  0x00890089
+#define INTEL_ALT     0x00B000B0
+
+/* Intel-compatible flash commands */
+#define INTEL_PROGRAM 0x00100010
+#define INTEL_ERASE   0x00200020
+#define INTEL_CLEAR   0x00500050
+#define INTEL_LOCKBIT 0x00600060
+#define INTEL_PROTECT 0x00010001
+#define INTEL_STATUS  0x00700070
+#define INTEL_READID  0x00900090
+#define INTEL_CONFIRM 0x00D000D0
+#define INTEL_RESET   0xFFFFFFFF
+
+/* Intel-compatible flash status bits */
+#define INTEL_FINISHED 0x00800080
+#define INTEL_OK       0x00800080
+
+#define FPW	   FLASH_PORT_WIDTH
+#define FPWV   FLASH_PORT_WIDTHV
+
+#define mb() __asm__ __volatile__ ("" : : : "memory")
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (FPW *addr, flash_info_t *info);
+static int write_data (flash_info_t *info, ulong dest, FPW data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+void inline spin_wheel (void);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	int i;
+	ulong size = 0;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		switch (i) {
+		case 0:
+			flash_get_size ((FPW *) CFG_FLASH_BASE, &flash_info[i]);
+			flash_get_offsets (CFG_FLASH_BASE, &flash_info[i]);
+			break;
+		default:
+			panic ("configured to many flash banks!\n");
+			break;
+		}
+		size += flash_info[i].size;
+	}
+
+	/* Protect monitor and environment sectors
+	 */
+	flash_protect ( FLAG_PROTECT_SET,
+			CFG_MONITOR_BASE,
+			CFG_MONITOR_BASE + monitor_flash_len - 1,
+			&flash_info[0] );
+
+	flash_protect ( FLAG_PROTECT_SET,
+			CFG_ENV_ADDR,
+			CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0] );
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
+			info->protect[i] = 0;
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F128J3A:
+		printf ("28F128J3A\n");
+		break;
+
+	case FLASH_28F640J3A:
+		printf ("28F640J3A\n");
+		break;
+
+	case FLASH_28F320J3A:
+		printf ("28F320J3A\n");
+		break;
+
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (FPW *addr, flash_info_t *info)
+{
+	volatile FPW value;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x5555] = (FPW) 0x00AA00AA;
+	addr[0x2AAA] = (FPW) 0x00550055;
+	addr[0x5555] = (FPW) 0x00900090;
+
+	mb ();
+	value = addr[0];
+
+	switch (value) {
+
+	case (FPW) INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+		return (0);			/* no or unknown flash  */
+	}
+
+	mb ();
+	value = addr[1];			/* device ID        */
+
+	switch (value) {
+
+	case (FPW) INTEL_ID_28F128J3A:
+		info->flash_id += FLASH_28F128J3A;
+		info->sector_count = 128;
+		info->size = 0x02000000;
+		break;				/* => 32 MB     */
+
+	case (FPW) INTEL_ID_28F640J3A:
+		info->flash_id += FLASH_28F640J3A;
+		info->sector_count = 64;
+		info->size = 0x01000000;
+		break;				/* => 16 MB     */
+
+	case (FPW) INTEL_ID_28F320J3A:
+		info->flash_id += FLASH_28F320J3A;
+		info->sector_count = 32;
+		info->size = 0x00800000;
+		break;				/* => 8 MB     */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+			info->sector_count, CFG_MAX_FLASH_SECT);
+		info->sector_count = CFG_MAX_FLASH_SECT;
+	}
+
+	addr[0] = (FPW) 0x00FF00FF;		/* restore read mode */
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong type, start, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	start = get_timer (0);
+	last = start;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			FPWV *addr = (FPWV *) (info->start[sect]);
+			FPW status;
+
+			printf ("Erasing sector %2d ... ", sect);
+
+			/* arm simple, non interrupt dependent timer */
+			start = get_timer(0);
+
+			*addr = (FPW) 0x00500050;	/* clear status register */
+			*addr = (FPW) 0x00200020;	/* erase setup */
+			*addr = (FPW) 0x00D000D0;	/* erase confirm */
+
+			while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+				if (get_timer(start) > CFG_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					*addr = (FPW) 0x00B000B0;	/* suspend erase     */
+					*addr = (FPW) 0x00FF00FF;	/* reset to read mode */
+					rcode = 1;
+					break;
+				}
+			}
+
+			*addr = 0x00500050;	/* clear status register cmd.   */
+			*addr = 0x00FF00FF;	/* resest to read mode          */
+
+			printf (" done\n");
+		}
+	}
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	FPW data;
+	int count, i, l, rc, port_width;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+/* get lower word aligned address */
+#ifdef FLASH_PORT_WIDTH16
+	wp = (addr & ~1);
+	port_width = 2;
+#else
+	wp = (addr & ~3);
+	port_width = 4;
+#endif
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < port_width && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < port_width; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	count = 0;
+	while (cnt >= port_width) {
+		data = 0;
+		for (i = 0; i < port_width; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+		cnt -= port_width;
+		if (count++ > 0x800) {
+			spin_wheel ();
+			count = 0;
+		}
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < port_width; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_data (info, wp, SWAP (data)));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t *info, ulong dest, FPW data)
+{
+	FPWV *addr = (FPWV *) dest;
+	ulong status;
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr);
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	*addr = (FPW) 0x00400040;	/* write setup */
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	start = get_timer(0);
+
+	/* wait while polling the status register */
+	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+			return (1);
+		}
+	}
+
+	*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (0);
+}
+
+void inline spin_wheel (void)
+{
+	static int p = 0;
+	static char w[] = "\\/-";
+
+	printf ("\010%c", w[p]);
+	(++p == 3) ? (p = 0) : 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Set/Clear sector's lock bit, returns:
+ * 0 - OK
+ * 1 - Error (timeout, voltage problems, etc.)
+ */
+int flash_real_protect(flash_info_t *info, long sector, int prot)
+{
+	ulong start;
+	int i;
+	int rc = 0;
+	vu_long *addr = (vu_long *)(info->start[sector]);
+	int flag = disable_interrupts();
+
+	*addr = INTEL_CLEAR;	/* Clear status register */
+	if (prot) {			/* Set sector lock bit */
+		*addr = INTEL_LOCKBIT;	/* Sector lock bit */
+		*addr = INTEL_PROTECT;	/* set */
+	}
+	else {				/* Clear sector lock bit */
+		*addr = INTEL_LOCKBIT;	/* All sectors lock bits */
+		*addr = INTEL_CONFIRM;	/* clear */
+	}
+
+	start = get_timer(0);
+
+	while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
+		if (get_timer(start) > CFG_FLASH_UNLOCK_TOUT) {
+			printf("Flash lock bit operation timed out\n");
+			rc = 1;
+			break;
+		}
+	}
+
+	if (*addr != INTEL_OK) {
+		printf("Flash lock bit operation failed at %08X, CSR=%08X\n",
+		       (uint)addr, (uint)*addr);
+		rc = 1;
+	}
+
+	if (!rc)
+		info->protect[sector] = prot;
+
+	/*
+	 * Clear lock bit command clears all sectors lock bits, so
+	 * we have to restore lock bits of protected sectors.
+	 */
+	if (!prot)
+	{
+		for (i = 0; i < info->sector_count; i++)
+		{
+			if (info->protect[i])
+			{
+				start = get_timer(0);
+				addr = (vu_long *)(info->start[i]);
+				*addr = INTEL_LOCKBIT;	/* Sector lock bit */
+				*addr = INTEL_PROTECT;	/* set */
+				while ((*addr & INTEL_FINISHED) != INTEL_FINISHED)
+				{
+					if (get_timer(start) > CFG_FLASH_UNLOCK_TOUT)
+					{
+						printf("Flash lock bit operation timed out\n");
+						rc = 1;
+						break;
+					}
+				}
+			}
+		}
+	}
+
+	if (flag)
+		enable_interrupts();
+
+	*addr = INTEL_RESET;		/* Reset to read array mode */
+
+	return rc;
+}

board/pm520/pm520.c

@@ -0,0 +1,193 @@
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+
+#ifndef CFG_RAMBOOT
+static long int dram_size(long int *base, long int maxsize)
+{
+	volatile long int *addr;
+	ulong cnt, val;
+	ulong save[32];			/* to make test non-destructive */
+	unsigned char i = 0;
+
+	for (cnt = (maxsize / sizeof (long)) >> 1; cnt > 0; cnt >>= 1) {
+		addr = base + cnt;		/* pointer arith! */
+
+		save[i++] = *addr;
+		*addr = ~cnt;
+	}
+
+	/* write 0 to base address */
+	addr = base;
+	save[i] = *addr;
+	*addr = 0;
+
+	/* check at base address */
+	if ((val = *addr) != 0) {
+		*addr = save[i];
+		return (0);
+	}
+
+	for (cnt = 1; cnt < maxsize / sizeof (long); cnt <<= 1) {
+		addr = base + cnt;		/* pointer arith! */
+
+		val = *addr;
+		*addr = save[--i];
+
+		if (val != (~cnt)) {
+			return (cnt * sizeof (long));
+		}
+	}
+	return (maxsize);
+}
+
+static void sdram_start (int hi_addr)
+{
+	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+	/* unlock mode register */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0000 | hi_addr_bit;
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0002 | hi_addr_bit;
+	/* set mode register */
+#if defined(CONFIG_MPC5200)
+	*(vu_long *)MPC5XXX_SDRAM_MODE = 0x408d0000;
+#elif defined(CONFIG_MGT5100)
+	*(vu_long *)MPC5XXX_SDRAM_MODE = 0x008d0000;
+#endif
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0002 | hi_addr_bit;
+	/* auto refresh */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0004 | hi_addr_bit;
+	/* set mode register */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = 0x008d0000;
+	/* normal operation */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = 0x504f0000 | hi_addr_bit;
+}
+#endif
+
+long int initdram (int board_type)
+{
+	ulong dramsize = 0;
+#ifndef CFG_RAMBOOT
+	ulong test1, test2;
+
+	/* configure SDRAM start/end */
+#if defined(CONFIG_MPC5200)
+	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
+
+	/* setup config registers */
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = 0xc2233a00;
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = 0x88b70004;
+
+#elif defined(CONFIG_MGT5100)
+	*(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
+	*(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
+	*(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
+
+	/* setup config registers */
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = 0xc2222600;
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = 0x88b70004;
+
+	/* address select register */
+	*(vu_long *)MPC5XXX_SDRAM_XLBSEL = 0x03000000;
+#endif
+	sdram_start(0);
+	test1 = dram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+	sdram_start(1);
+	test2 = dram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+#if defined(CONFIG_MPC5200)
+	*(vu_long *)MPC5XXX_SDRAM_CS0CFG =
+		(0x13 + __builtin_ffs(dramsize >> 20) - 1);
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
+#elif defined(CONFIG_MGT5100)
+	*(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
+#endif
+
+#else
+#ifdef CONFIG_MGT5100
+	*(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
+	dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
+#else
+	dramsize = ((1 << (*(vu_long *)MPC5XXX_SDRAM_CS0CFG - 0x13)) << 20);
+#endif
+#endif /* CFG_RAMBOOT */
+	/* return total ram size */
+	return dramsize;
+}
+
+int checkboard (void)
+{
+#if defined(CONFIG_MPC5200)
+	puts ("Board: MicroSys PM520 \n");
+#elif defined(CONFIG_MGT5100)
+	puts ("Board: MicroSys PM510 \n");
+#endif
+	return 0;
+}
+
+void flash_preinit(void)
+{
+	/*
+	 * Now, when we are in RAM, enable flash write
+	 * access for detection process.
+	 * Note that CS_BOOT cannot be cleared when
+	 * executing in flash.
+	 */
+#if defined(CONFIG_MGT5100)
+	*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
+	*(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
+#endif
+	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
+}
+
+void flash_afterinit(ulong size)
+{
+	if (size == 0x800000) { /* adjust mapping */
+		*(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
+			START_REG(CFG_BOOTCS_START | size);
+		*(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
+			STOP_REG(CFG_BOOTCS_START | size, size);
+	}
+}
+
+#ifdef	CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+	pci_mpc5xxx_init(&hose);
+}
+#endif

board/pm520/u-boot.lds

@@ -0,0 +1,122 @@
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc5xxx/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}

board/pm826/config.mk

@@ -1,5 +1,5 @@
 #
-# (C) Copyright 2001, 2002
+# (C) Copyright 2001-2004
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # See file CREDITS for list of people who contributed to this
@@ -22,21 +22,16 @@
 #
 
 #
-# PM826 boards
+# MicroSys PM826 board:
 #
 
-# This should be equal to the CFG_FLASH_BASE or
-# CFG_BOOTROM_BASE define in config_PM826.h
-# for the "final" configuration, with U-Boot
-# in flash, or the address in RAM where
-# U-Boot is loaded at for debugging.
-#
 
-ifeq ($(CONFIG_BOOT_ROM),y)
-	TEXT_BASE := 0xFF800000
-	PLATFORM_CPPFLAGS += -DCONFIG_BOOT_ROM
-else
-	TEXT_BASE := 0xFF000000
+sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp
+
+ifndef TEXT_BASE
+## Standard: boot 64-bit flash
+TEXT_BASE = 0xFF000000
+
 endif
 
 PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)

board/pm826/flash.c

@@ -69,6 +69,11 @@ ulong flash_get_size (volatile unsigned long *baseaddr,
 		info->sector_count = 39;
 		info->size = 0x00800000;	/* 4 * 2 MB = 8 MB      */
 		break;
+	case INTEL_ID_28F640C3B:
+		info->flash_id = FLASH_28F640C3B;
+		info->sector_count = 135;
+		info->size = 0x02000000;	/* 16 * 2 MB = 32 MB	*/
+		break;
 	default:
 		return (0);			/* no or unknown flash	*/
 	}
@@ -79,10 +84,11 @@ ulong flash_get_size (volatile unsigned long *baseaddr,
 		volatile unsigned long *tmp = baseaddr;
 
 		/* set up sector start adress table (bottom sector type)
-		 * AND unlock the sectors (if our chip is 160C3)
+		 * AND unlock the sectors (if our chip is 160C3 or 640C3)
 		 */
 		for (i = 0; i < info->sector_count; i++) {
-			if ((info->flash_id & FLASH_TYPEMASK) == FLASH_28F160C3B) {
+			if (((info->flash_id & FLASH_TYPEMASK) == FLASH_28F160C3B) ||
+			    ((info->flash_id & FLASH_TYPEMASK) == FLASH_28F640C3B)) {
 				tmp[0] = 0x00600060;
 				tmp[1] = 0x00600060;
 				tmp[0] = 0x00D000D0;
@@ -177,6 +183,9 @@ void flash_print_info (flash_info_t * info)
 	case FLASH_28F160F3B:
 		printf ("28F160F3B (16 M, bottom sector)\n");
 		break;
+	case FLASH_28F640C3B:
+		printf ("28F640C3B (64 M, bottom sector)\n");
+		break;
 	default:
 		printf ("Unknown Chip Type\n");
 		break;

board/pm828/Makefile

@@ -1,5 +1,5 @@
 #
-# (C) Copyright 2000-2002
+# (C) Copyright 2001-2004
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # See file CREDITS for list of people who contributed to this

board/pm828/config.mk

@@ -0,0 +1,37 @@
+#
+# (C) Copyright 2003-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# MicroSys PM828 board:
+#
+
+
+sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp
+
+ifndef TEXT_BASE
+## Standard: boot 64-bit flash
+TEXT_BASE = 0x40000000
+
+endif
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)

board/pm828/flash.c

@@ -0,0 +1,386 @@
+/*
+ * (C) Copyright 2001-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Flash Routines for Intel devices
+ *
+ *--------------------------------------------------------------------
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+/*-----------------------------------------------------------------------
+ */
+ulong flash_get_size (volatile unsigned long *baseaddr,
+					  flash_info_t * info)
+{
+	short i;
+	unsigned long flashtest_h, flashtest_l;
+
+	info->sector_count = info->size = 0;
+	info->flash_id = FLASH_UNKNOWN;
+
+	/* Write query command sequence and test FLASH answer
+	 */
+	baseaddr[0] = 0x00980098;
+	baseaddr[1] = 0x00980098;
+
+	flashtest_h = baseaddr[0];	/* manufacturer ID	*/
+	flashtest_l = baseaddr[1];
+
+	if (flashtest_h != INTEL_MANUFACT || flashtest_l != INTEL_MANUFACT)
+		return (0);		/* no or unknown flash	*/
+
+	flashtest_h = baseaddr[2];	/* device ID	        */
+	flashtest_l = baseaddr[3];
+
+	if (flashtest_h != flashtest_l)
+		return (0);
+
+	switch (flashtest_h) {
+	case INTEL_ID_28F160C3B:
+		info->flash_id = FLASH_28F160C3B;
+		info->sector_count = 39;
+		info->size = 0x00800000;	/* 4 * 2 MB = 8 MB	*/
+		break;
+	case INTEL_ID_28F160F3B:
+		info->flash_id = FLASH_28F160F3B;
+		info->sector_count = 39;
+		info->size = 0x00800000;	/* 4 * 2 MB = 8 MB      */
+		break;
+	case INTEL_ID_28F640C3B:
+		info->flash_id = FLASH_28F640C3B;
+		info->sector_count = 135;
+		info->size = 0x02000000;	/* 16 * 2 MB = 32 MB	*/
+		break;
+	default:
+		return (0);			/* no or unknown flash	*/
+	}
+
+	info->flash_id |= INTEL_MANUFACT << 16; /* set manufacturer offset */
+
+	if (info->flash_id & FLASH_BTYPE) {
+		volatile unsigned long *tmp = baseaddr;
+
+		/* set up sector start adress table (bottom sector type)
+		 * AND unlock the sectors (if our chip is 160C3 or 640c3)
+		 */
+		for (i = 0; i < info->sector_count; i++) {
+			if (((info->flash_id & FLASH_TYPEMASK) == FLASH_28F160C3B) ||
+			    ((info->flash_id & FLASH_TYPEMASK) == FLASH_28F640C3B)) {
+				tmp[0] = 0x00600060;
+				tmp[1] = 0x00600060;
+				tmp[0] = 0x00D000D0;
+				tmp[1] = 0x00D000D0;
+			}
+			info->start[i] = (uint) tmp;
+			tmp += i < 8 ? 0x2000 : 0x10000; /* pointer arith       */
+		}
+	}
+
+	memset (info->protect, 0, info->sector_count);
+
+	baseaddr[0] = 0x00FF00FF;
+	baseaddr[1] = 0x00FF00FF;
+
+	return (info->size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+unsigned long flash_init (void)
+{
+	unsigned long size_b0 = 0;
+	int i;
+
+	/* Init: no FLASHes known
+	 */
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here (only one bank) */
+
+	size_b0 = flash_get_size ((ulong *) CFG_FLASH0_BASE, &flash_info[0]);
+	if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+				size_b0, size_b0 >> 20);
+	}
+
+	/* protect monitor and environment sectors
+	 */
+
+#ifndef CONFIG_BOOT_ROM
+	/* If U-Boot is  booted from ROM the CFG_MONITOR_BASE > CFG_FLASH0_BASE
+	 * but we shouldn't protect it.
+	 */
+
+# if CFG_MONITOR_BASE >= CFG_FLASH0_BASE
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_MONITOR_BASE,
+		       CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]
+	);
+# endif
+#endif	/* CONFIG_BOOT_ROM */
+
+#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR)
+# ifndef  CFG_ENV_SIZE
+#  define CFG_ENV_SIZE	CFG_ENV_SECT_SIZE
+# endif
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_ENV_ADDR,
+		       CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
+#endif
+
+	return (size_b0);
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch ((info->flash_id >> 16) & 0xff) {
+	case 0x89:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F160C3B:
+		printf ("28F160C3B (16 M, bottom sector)\n");
+		break;
+	case FLASH_28F160F3B:
+		printf ("28F160F3B (16 M, bottom sector)\n");
+		break;
+	case FLASH_28F640C3B:
+		printf ("28F640C3B (64 M, bottom sector)\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect])
+			prot++;
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+				prot);
+	} else {
+		printf ("\n");
+	}
+
+	/* Start erase on unprotected sectors
+	 */
+	for (sect = s_first; sect <= s_last; sect++) {
+		volatile ulong *addr =
+				(volatile unsigned long *) info->start[sect];
+
+		start = get_timer (0);
+		last = start;
+		if (info->protect[sect] == 0) {
+			/* Disable interrupts which might cause a timeout here
+			 */
+			flag = disable_interrupts ();
+
+			/* Erase the block
+			 */
+			addr[0] = 0x00200020;
+			addr[1] = 0x00200020;
+			addr[0] = 0x00D000D0;
+			addr[1] = 0x00D000D0;
+
+			/* re-enable interrupts if necessary
+			 */
+			if (flag)
+				enable_interrupts ();
+
+			/* wait at least 80us - let's wait 1 ms
+			 */
+			udelay (1000);
+
+			last = start;
+			while ((addr[0] & 0x00800080) != 0x00800080 ||
+				   (addr[1] & 0x00800080) != 0x00800080) {
+				if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
+					printf ("Timeout (erase suspended!)\n");
+					/* Suspend erase
+					 */
+					addr[0] = 0x00B000B0;
+					addr[1] = 0x00B000B0;
+					goto DONE;
+				}
+				/* show that we're waiting
+				 */
+				if ((now - last) > 1000) {	/* every second */
+					serial_putc ('.');
+					last = now;
+				}
+			}
+			if (addr[0] & 0x00220022 || addr[1] & 0x00220022) {
+				printf ("*** ERROR: erase failed!\n");
+				goto DONE;
+			}
+		}
+		/* Clear status register and reset to read mode
+		 */
+		addr[0] = 0x00500050;
+		addr[1] = 0x00500050;
+		addr[0] = 0x00FF00FF;
+		addr[1] = 0x00FF00FF;
+	}
+
+	printf (" done\n");
+
+DONE:
+	return 0;
+}
+
+static int write_word (flash_info_t *, volatile unsigned long *, ulong);
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong v;
+	int i, l, cc = cnt, res = 0;
+
+
+	for (v=0; cc > 0; addr += 4, cc -= 4 - l) {
+		l = (addr & 3);
+		addr &= ~3;
+
+		for (i = 0; i < 4; i++) {
+			v = (v << 8) + (i < l || i - l >= cc ?
+				*((unsigned char *) addr + i) : *src++);
+		}
+
+		if ((res = write_word (info, (volatile unsigned long *) addr, v)) != 0)
+			break;
+	}
+
+	return (res);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t * info, volatile unsigned long *addr,
+					   ulong data)
+{
+	int flag, res = 0;
+	ulong start;
+
+	/* Check if Flash is (sufficiently) erased
+	 */
+	if ((*addr & data) != data)
+		return (2);
+
+	/* Disable interrupts which might cause a timeout here
+	 */
+	flag = disable_interrupts ();
+
+	*addr = 0x00400040;
+	*addr = data;
+
+	/* re-enable interrupts if necessary
+	 */
+	if (flag)
+		enable_interrupts ();
+
+	start = get_timer (0);
+	while ((*addr & 0x00800080) != 0x00800080) {
+		if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+			/* Suspend program
+			 */
+			*addr = 0x00B000B0;
+			res = 1;
+			goto OUT;
+		}
+	}
+
+	if (*addr & 0x00220022) {
+		printf ("*** ERROR: program failed!\n");
+		res = 1;
+	}
+
+OUT:
+	/* Clear status register and reset to read mode
+	 */
+	*addr = 0x00500050;
+	*addr = 0x00FF00FF;
+
+	return (res);
+}

board/pm828/pm828.c

@@ -0,0 +1,363 @@
+/*
+ * (C) Copyright 2001-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc8260.h>
+#include <pci.h>
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A configuration */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PA31 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 COL */
+	/* PA30 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 CRS */
+	/* PA29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC1 TXER */
+	/* PA28 */ {   1,   1,   1,   1,   0,   0   }, /* FCC1 TXEN */
+	/* PA27 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 RXDV */
+	/* PA26 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 RXER */
+	/* PA25 */ {   0,   0,   0,   1,   0,   0   }, /* PA25 */
+	/* PA24 */ {   0,   0,   0,   1,   0,   0   }, /* PA24 */
+	/* PA23 */ {   0,   0,   0,   1,   0,   0   }, /* PA23 */
+	/* PA22 */ {   0,   0,   0,   1,   0,   0   }, /* PA22 */
+	/* PA21 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 TXD3 */
+	/* PA20 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 TXD2 */
+	/* PA19 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 TXD1 */
+	/* PA18 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 TXD0 */
+	/* PA17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 RXD0 */
+	/* PA16 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 RXD1*/
+	/* PA15 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 RXD2 */
+	/* PA14 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 RXD3 */
+	/* PA13 */ {   0,   0,   0,   1,   0,   0   }, /* PA13 */
+	/* PA12 */ {   0,   0,   0,   1,   0,   0   }, /* PA12 */
+	/* PA11 */ {   0,   0,   0,   1,   0,   0   }, /* PA11 */
+	/* PA10 */ {   0,   0,   0,   1,   0,   0   }, /* PA10 */
+	/* PA9  */ {   0,   1,   0,   1,   0,   0   }, /* PA9 */
+	/* PA8  */ {   0,   1,   0,   0,   0,   0   }, /* PA8 */
+	/* PA7  */ {   0,   0,   0,   1,   0,   0   }, /* PA7 */
+	/* PA6  */ {   0,   0,   0,   1,   0,   0   }, /* PA6 */
+	/* PA5  */ {   0,   0,   0,   1,   0,   0   }, /* PA5 */
+	/* PA4  */ {   0,   0,   0,   1,   0,   0   }, /* PA4 */
+	/* PA3  */ {   0,   0,   0,   1,   0,   0   }, /* PA3 */
+	/* PA2  */ {   0,   0,   0,   1,   0,   0   }, /* PA2 */
+	/* PA1  */ {   0,   0,   0,   1,   0,   0   }, /* PA1 */
+	/* PA0  */ {   0,   0,   0,   1,   0,   0   }  /* PA0 */
+    },
+
+    /* Port B configuration */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 TX_ER */
+	/* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 RX_DV  */
+	/* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 TX_EN  */
+#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
+#ifdef CONFIG_ETHER_ON_FCC2
+#error "SCC1 conflicts with FCC2"
+#endif
+	/* PB28 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 TXD */
+#else
+	/* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 RX_ER */
+#endif
+	/* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 COL */
+	/* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 CRS */
+	/* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 TxD[3] */
+	/* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 TxD[2] */
+	/* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 TxD[1] */
+	/* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 TxD[0] */
+	/* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 RxD[0] */
+	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 RxD[1] */
+	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 RxD[2] */
+	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 RxD[3] */
+	/* PB17 */ {   0,   0,   0,   0,   0,   0   }, /* PB17 */
+	/* PB16 */ {   0,   0,   0,   0,   0,   0   }, /* PB16 */
+	/* PB15 */ {   1,   1,   0,   0,   0,   0   }, /* SCC2 RXD */
+	/* PB14 */ {   1,   1,   0,   0,   0,   0   }, /* SCC3 RXD */
+	/* PB13 */ {   0,   0,   0,   0,   0,   0   }, /* PB13 */
+	/* PB12 */ {   0,   0,   0,   0,   0,   0   }, /* PB12 */
+	/* PB11 */ {   0,   0,   0,   0,   0,   0   }, /* PB11 */
+	/* PB10 */ {   0,   0,   0,   0,   0,   0   }, /* PB10 */
+	/* PB9  */ {   0,   0,   0,   0,   0,   0   }, /* PB9 */
+	/* PB8  */ {   1,   1,   1,   1,   0,   0   }, /* SCC3 TXD */
+	/* PB7  */ {   0,   0,   0,   0,   0,   0   }, /* PB7 */
+	/* PB6  */ {   0,   0,   0,   0,   0,   0   }, /* PB6 */
+	/* PB5  */ {   0,   0,   0,   0,   0,   0   }, /* PB5 */
+	/* PB4  */ {   0,   0,   0,   0,   0,   0   }, /* PB4 */
+	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    },
+
+    /* Port C */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PC31 */ {   0,   0,   0,   1,   0,   0   }, /* PC31 */
+	/* PC30 */ {   0,   0,   0,   1,   0,   0   }, /* PC30 */
+	/* PC29 */ {   0,   1,   1,   0,   0,   0   }, /* SCC1 CTS */
+	/* PC28 */ {   0,   0,   0,   1,   0,   0   }, /* SCC2 CTS */
+	/* PC27 */ {   0,   0,   0,   1,   0,   0   }, /* PC27 */
+	/* PC26 */ {   0,   0,   0,   1,   0,   0   }, /* PC26 */
+	/* PC25 */ {   0,   0,   0,   1,   0,   0   }, /* PC25 */
+	/* PC24 */ {   0,   0,   0,   1,   0,   0   }, /* PC24 */
+	/* PC23 */ {   0,   1,   0,   1,   0,   0   }, /* PC23 */
+	/* PC22 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 TXCK */
+	/* PC21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 RXCK */
+	/* PC20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 TXCK(2) */
+	/* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 RXCK */
+	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 TXCK */
+	/* PC17 */ {   0,   0,   0,   1,   0,   0   }, /* PC17 */
+	/* PC16 */ {   0,   0,   0,   1,   0,   0   }, /* PC16 */
+	/* PC15 */ {   1,   1,   0,   1,   0,   0   }, /* SMC2 TXD */
+	/* PC14 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 DCD */
+	/* PC13 */ {   0,   0,   0,   1,   0,   0   }, /* PC13 */
+	/* PC12 */ {   0,   0,   0,   1,   0,   0   }, /* SCC2 DCD */
+	/* PC11 */ {   0,   0,   0,   1,   0,   0   }, /* SCC3 CTS */
+	/* PC10 */ {   0,   0,   0,   1,   0,   0   }, /* SCC3 DCD */
+	/* PC9  */ {   0,   0,   0,   1,   0,   0   }, /* SCC4 CTS */
+	/* PC8  */ {   0,   0,   0,   1,   0,   0   }, /* SCC4 DCD */
+	/* PC7  */ {   0,   0,   0,   1,   0,   0   }, /* PC7 */
+	/* PC6  */ {   0,   0,   0,   1,   0,   0   }, /* PC6 */
+	/* PC5  */ {   0,   0,   0,   1,   0,   0   }, /* PC5 */
+	/* PC4  */ {   0,   0,   0,   1,   0,   0   }, /* PC4 */
+	/* PC3  */ {   0,   0,   0,   1,   0,   0   }, /* PC3 */
+	/* PC2  */ {   0,   0,   0,   1,   0,   1   }, /* PC2 */
+	/* PC1  */ {   0,   0,   0,   1,   0,   0   }, /* PC1 */
+	/* PC0  */ {   0,   0,   0,   1,   0,   0   }, /* PC0 */
+    },
+
+    /* Port D */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 RXD */
+	/* PD30 */ {   0,   1,   1,   1,   0,   0   }, /* PD30 */
+	/* PD29 */ {   0,   1,   0,   1,   0,   0   }, /* SCC1 RTS */
+	/* PD28 */ {   0,   0,   0,   1,   0,   0   }, /* PD28 */
+	/* PD27 */ {   0,   1,   0,   1,   0,   0   }, /* SCC2 RTS */
+	/* PD26 */ {   0,   0,   0,   1,   0,   0   }, /* PD26 */
+	/* PD25 */ {   0,   0,   0,   1,   0,   0   }, /* PD25 */
+	/* PD24 */ {   0,   0,   0,   1,   0,   0   }, /* PD24 */
+	/* PD23 */ {   0,   0,   0,   1,   0,   0   }, /* SCC3 RTS */
+	/* PD22 */ {   1,   1,   0,   0,   0,   0   }, /* SCC4 RXD */
+	/* PD21 */ {   1,   1,   0,   1,   0,   0   }, /* SCC4 TXD */
+	/* PD20 */ {   0,   0,   1,   1,   0,   0   }, /* SCC4 RTS */
+	/* PD19 */ {   0,   0,   0,   1,   0,   0   }, /* PD19 */
+	/* PD18 */ {   0,   0,   0,   1,   0,   0   }, /* PD18 */
+	/* PD17 */ {   0,   1,   0,   0,   0,   0   }, /* PD17 */
+	/* PD16 */ {   0,   1,   0,   1,   0,   0   }, /* PD16 */
+#if defined(CONFIG_SOFT_I2C)
+	/* PD15 */ {   1,   0,   0,   1,   1,   1   }, /* I2C SDA */
+	/* PD14 */ {   1,   0,   0,   1,   1,   1   }, /* I2C SCL */
+#else
+#if defined(CONFIG_HARD_I2C)
+	/* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
+#else /* normal I/O port pins */
+	/* PD15 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SCL */
+#endif
+#endif
+	/* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
+	/* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
+	/* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
+	/* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
+	/* PD9  */ {   0,   1,   0,   1,   0,   0   }, /* PD9 */
+	/* PD8  */ {   0,   1,   0,   0,   0,   0   }, /* PD8 */
+	/* PD7  */ {   0,   0,   0,   1,   0,   1   }, /* PD7 */
+	/* PD6  */ {   0,   0,   0,   1,   0,   1   }, /* PD6 */
+	/* PD5  */ {   0,   0,   0,   1,   0,   1   }, /* PD5 */
+	/* PD4  */ {   1,   1,   1,   0,   0,   0   }, /* SMC2 RXD */
+	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    }
+};
+
+/* ------------------------------------------------------------------------- */
+
+/* Check Board Identity:
+ */
+int checkboard (void)
+{
+	puts ("Board: PM828\n");
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+
+/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
+ *
+ * This routine performs standard 8260 initialization sequence
+ * and calculates the available memory size. It may be called
+ * several times to try different SDRAM configurations on both
+ * 60x and local buses.
+ */
+static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
+						  ulong orx, volatile uchar * base)
+{
+	volatile uchar c = 0xff;
+	volatile ulong cnt, val;
+	volatile ulong *addr;
+	volatile uint *sdmr_ptr;
+	volatile uint *orx_ptr;
+	int i;
+	ulong save[32];				/* to make test non-destructive */
+	ulong maxsize;
+
+	/* We must be able to test a location outsize the maximum legal size
+	 * to find out THAT we are outside; but this address still has to be
+	 * mapped by the controller. That means, that the initial mapping has
+	 * to be (at least) twice as large as the maximum expected size.
+	 */
+	maxsize = (1 + (~orx | 0x7fff)) / 2;
+
+	sdmr_ptr = &memctl->memc_psdmr;
+	orx_ptr = &memctl->memc_or2;
+
+	*orx_ptr = orx;
+
+	/*
+	 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
+	 *
+	 * "At system reset, initialization software must set up the
+	 *  programmable parameters in the memory controller banks registers
+	 *  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
+	 *  system software should execute the following initialization sequence
+	 *  for each SDRAM device.
+	 *
+	 *  1. Issue a PRECHARGE-ALL-BANKS command
+	 *  2. Issue eight CBR REFRESH commands
+	 *  3. Issue a MODE-SET command to initialize the mode register
+	 *
+	 *  The initial commands are executed by setting P/LSDMR[OP] and
+	 *  accessing the SDRAM with a single-byte transaction."
+	 *
+	 * The appropriate BRx/ORx registers have already been set when we
+	 * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
+	 */
+
+	*sdmr_ptr = sdmr | PSDMR_OP_PREA;
+	*base = c;
+
+	*sdmr_ptr = sdmr | PSDMR_OP_CBRR;
+	for (i = 0; i < 8; i++)
+		*base = c;
+
+	*sdmr_ptr = sdmr | PSDMR_OP_MRW;
+	*(base + CFG_MRS_OFFS) = c;	/* setting MR on address lines */
+
+	*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
+	*base = c;
+
+	/*
+	 * Check memory range for valid RAM. A simple memory test determines
+	 * the actually available RAM size between addresses `base' and
+	 * `base + maxsize'. Some (not all) hardware errors are detected:
+	 * - short between address lines
+	 * - short between data lines
+	 */
+	i = 0;
+	for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
+		addr = (volatile ulong *) base + cnt;	/* pointer arith! */
+		save[i++] = *addr;
+		*addr = ~cnt;
+	}
+
+	addr = (volatile ulong *) base;
+	save[i] = *addr;
+	*addr = 0;
+
+	if ((val = *addr) != 0) {
+		*addr = save[i];
+		return (0);
+	}
+
+	for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
+		addr = (volatile ulong *) base + cnt;	/* pointer arith! */
+		val = *addr;
+		*addr = save[--i];
+		if (val != ~cnt) {
+			/* Write the actual size to ORx
+			 */
+			*orx_ptr = orx | ~(cnt * sizeof (long) - 1);
+			return (cnt * sizeof (long));
+		}
+	}
+	return (maxsize);
+}
+
+
+long int initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8260_t *memctl = &immap->im_memctl;
+
+#ifndef CFG_RAMBOOT
+	ulong size8, size9;
+#endif
+	ulong psize = 32 * 1024 * 1024;
+
+	memctl->memc_psrt = CFG_PSRT;
+	memctl->memc_mptpr = CFG_MPTPR;
+
+#ifndef CFG_RAMBOOT
+	size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL,
+					  (uchar *) CFG_SDRAM_BASE);
+	size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR2_9COL,
+					  (uchar *) CFG_SDRAM_BASE);
+
+	if (size8 < size9) {
+		psize = size9;
+		printf ("(60x:9COL) ");
+	} else {
+		psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL,
+						  (uchar *) CFG_SDRAM_BASE);
+		printf ("(60x:8COL) ");
+	}
+#endif
+	return (psize);
+}
+
+#if (CONFIG_COMMANDS & CFG_CMD_DOC)
+extern void doc_probe (ulong physadr);
+void doc_init (void)
+{
+	doc_probe (CFG_DOC_BASE);
+}
+#endif
+
+#ifdef	CONFIG_PCI
+struct pci_controller hose;
+
+extern void pci_mpc8250_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+	pci_mpc8250_init(&hose);
+}
+#endif

board/pm828/u-boot.lds

@@ -0,0 +1,123 @@
+/*
+ * (C) Copyright 2001-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc8260/start.o	(.text)
+    *(.text)
+    common/environment.o(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}

board/rmu/flash.c

@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000
+ * (C) Copyright 2000-2004
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -21,6 +21,8 @@
  * MA 02111-1307 USA
  */
 
+/* #define DEBUG */
+
 #include <common.h>
 #include <mpc8xx.h>
 
@@ -49,28 +51,35 @@ unsigned long flash_init (void)
 	}
 
 	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	debug ("\n## Get flash bank size @ 0x%08x\n", FLASH_BASE_PRELIM);
+
 	size_b0 = flash_get_size((vu_long *)FLASH_BASE_PRELIM, &flash_info[0]);
 	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
 		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
 			size_b0, size_b0<<20);
 	}
 
+	debug  ("## Before remap:  BR0: 0x%08x    OR0: 0x%08x\n",
+		memctl->memc_br0, memctl->memc_or0);
+
 	/* Remap FLASH according to real size */
 	memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
 	memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
 
+	debug ("## BR0: 0x%08x    OR0: 0x%08x\n",
+		memctl->memc_br0, memctl->memc_or0);
+
 	/* Re-do sizing to get full correct info */
 
 	size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
 	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
 		      CFG_MONITOR_BASE,
 		      CFG_MONITOR_BASE+monitor_flash_len-1,
 		      &flash_info[0]);
-#endif
 
 #ifdef	CFG_ENV_IS_IN_FLASH
 	/* ENV protection ON by default */
@@ -80,8 +89,21 @@ unsigned long flash_init (void)
 		      &flash_info[0]);
 #endif
 
+#if defined(CFG_ENV_ADDR_REDUND) || defined(CFG_ENV_OFFSET_REDUND)
+	debug ("Protect redundand environment: %08lx ... %08lx\n",
+		(ulong)CFG_ENV_ADDR_REDUND,
+		(ulong)CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE - 1);
+
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_ENV_ADDR_REDUND,
+		      CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1,
+		      &flash_info[0]);
+#endif
+
 	flash_info[0].size = size_b0;
 
+	debug ("## Final Flash bank size: %08lx\n", size_b0);
+
 	return (size_b0);
 }
 
@@ -192,6 +214,8 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 
 	value = addr[0] ;
 
+	debug ("Manuf. ID @ 0x%08lx: 0x%08lx\n", (ulong)addr, value);
+
 	switch (value & 0x00FF00FF) {
 	case AMD_MANUFACT:
 		info->flash_id = FLASH_MAN_AMD;
@@ -208,6 +232,8 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 
 	value = addr[2] ;		/* device ID		*/
 
+	debug ("Device ID @ 0x%08lx: 0x%08lx\n", (ulong)(&addr[1]), value);
+
 	switch (value & 0x00FF00FF) {
 	case (AMD_ID_LV400T & 0x00FF00FF):
 		info->flash_id += FLASH_AM400T;
@@ -244,25 +270,22 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 		info->sector_count = 35;
 		info->size = 0x00800000;
 		break;				/* => 8 MB		*/
-#if 0	/* enable when device IDs are available */
-	case AMD_ID_LV320T:
+	case (AMD_ID_LV320T & 0x00FF00FF):
 		info->flash_id += FLASH_AM320T;
 		info->sector_count = 67;
 		info->size = 0x00800000;
 		break;				/* => 8 MB		*/
 
-	case AMD_ID_LV320B:
+	case (AMD_ID_LV320B & 0x00FF00FF):
 		info->flash_id += FLASH_AM320B;
 		info->sector_count = 67;
 		info->size = 0x01000000;
 		break;				/* => 16 MB		*/
-#endif
 	default:
 		info->flash_id = FLASH_UNKNOWN;
 		return (0);			/* => no or unknown flash */
 
 	}
-	/*%%% sector start address modified */
 	/* set up sector start address table */
 	if (info->flash_id & FLASH_BTYPE) {
 		/* set sector offsets for bottom boot block type	*/
@@ -314,6 +337,8 @@ int	flash_erase (flash_info_t *info, int s_first, int s_last)
 	int flag, prot, sect, l_sect;
 	ulong start, now, last;
 
+	debug ("flash_erase: first: %d last: %d\n", s_first, s_last);
+
 	if ((s_first < 0) || (s_first > s_last)) {
 		if (info->flash_id == FLASH_UNKNOWN) {
 			printf ("- missing\n");

board/sx1/platform.S

@@ -118,30 +118,21 @@ platformsetup:
 	str r1, [r0]	    /* EMIFS GlB Configuration. (value 0x12 most likely) */
 
 	ldr r0, _GPIO_PIN_CONTROL_REG
-	ldrh r1,[r0]
+	mov r1,#0
 	orr r1, r1, #0x0001 /* M_PCM_SYNC */
 	orr r1, r1, #0x4000 /* IPC_ACTIVE */
-	orr r1, r1, #0x0002 /* A_IRDA_OFF */
-	orr r1, r1, #0x0800 /* A_SWITCH	  */
-	orr r1, r1, #0x8000 /* A_USB_ON	  */
 	strh r1,[r0]
 
 	ldr r0, _GPIO_DIR_CONTROL_REG
-	ldrh r1,[r0]
+	mov r1,#0
 	bic r1, r1, #0x0001 /* M_PCM_SYNC */
 	bic r1, r1, #0x4000 /* IPC_ACTIVE */
-	bic r1, r1, #0x0002 /* A_IRDA_OFF */
-	bic r1, r1, #0x0800 /* A_SWITCH	  */
-	bic r1, r1, #0x8000 /* A_USB_ON	  */
 	strh r1,[r0]
 
 	ldr r0, _GPIO_DATA_OUTPUT_REG
-	ldrh r1,[r0]
+	mov r1,#0
 	bic r1, r1, #0x0001 /* M_PCM_SYNC */
 	orr r1, r1, #0x4000 /* IPC_ACTIVE */
-	orr r1, r1, #0x0002 /* A_IRDA_OFF */
-	bic r1, r1, #0x0800 /* A_SWITCH	  */
-	bic r1, r1, #0x8000 /* A_USB_ON	  */
 	strh r1,[r0]
 
 	/* Setup some clock domains */

board/trab/flash.c

@@ -83,6 +83,7 @@ ulong flash_init (void)
 
 			switch (info->flash_id & FLASH_TYPEMASK) {
 			case (FLASH_AM320B & FLASH_TYPEMASK):
+			case (FLASH_MXLV320B & FLASH_TYPEMASK):
 				/* Boot sector type: 8 x 8 + N x 128 kB */
 				flashbase += (j < 8) ? 0x4000 : 0x20000;
 				break;
@@ -130,6 +131,8 @@ void flash_print_info (flash_info_t * info)
 			printf ("AMD ");		break;
 	case (FLASH_MAN_FUJ & FLASH_VENDMASK):
 			printf ("FUJITSU ");		break;
+	case (FLASH_MAN_MX  & FLASH_VENDMASK):
+			printf ("MACRONIX ");		break;
 	default:	printf ("Unknown Vendor ");	break;
 	}
 
@@ -137,6 +140,9 @@ void flash_print_info (flash_info_t * info)
 	case (FLASH_AM320B & FLASH_TYPEMASK):
 		printf ("2x Am29LV320DB (32Mbit)\n");
 		break;
+	case (FLASH_MXLV320B & FLASH_TYPEMASK):
+		printf ("2x MX29LV320DB (32Mbit)\n");
+		break;
 	case (FLASH_AM640U & FLASH_TYPEMASK):
 		printf ("2x Am29LV640D (64Mbit)\n");
 		break;
@@ -191,6 +197,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
 	switch (info->flash_id & FLASH_VENDMASK) {
 	case (FLASH_MAN_AMD & FLASH_VENDMASK):	break;	/* OK */
 	case (FLASH_MAN_FUJ & FLASH_VENDMASK):	break;	/* OK */
+	case (FLASH_MAN_MX  & FLASH_VENDMASK):	break;	/* OK */
 	default:
 		debug ("## flash_erase: unknown manufacturer\n");
 		return (ERR_UNKNOWN_FLASH_VENDOR);
@@ -502,6 +509,9 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 	case FUJ_MANUFACT:
 		info->flash_id = FLASH_MAN_FUJ;
 		break;
+	case MX_MANUFACT:
+		info->flash_id = FLASH_MAN_MX;
+		break;
 	default:
 		info->flash_id = FLASH_UNKNOWN;
 		info->sector_count = 0;
@@ -532,6 +542,14 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 		addr[0] = 0x00F000F0;		/* restore read mode */
 		break;				/* => 16 MB		*/
 
+	case MX_ID_LV320B:
+		info->flash_id += FLASH_MXLV320B;
+		info->sector_count = 71;
+		info->size = 0x00800000;
+
+		addr[0] = 0x00FF00FF;		/* restore read mode */
+		break;				/* =>  8 MB		*/
+
 	default:
 		debug ("## flash_init: unknown flash chip\n");
 		info->flash_id = FLASH_UNKNOWN;

board/xm250/Makefile

@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= xm250.o flash.o
+SOBJS	:= memsetup.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################

board/xm250/config.mk

@@ -0,0 +1,35 @@
+#
+# (C) Copyright 2003-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# MicroSys XM250 board:
+#
+
+
+# This is the address where U-Boot lives in flash:
+#TEXT_BASE = 0
+
+# FIXME: armboot does only work correctly when being compiled
+# for the addresses _after_ relocation to RAM!! Otherwhise the
+# .bss segment is assumed in flash...
+TEXT_BASE = 0xA3F80000

board/xm250/flash.c

@@ -0,0 +1,536 @@
+/*
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+
+/* Board support for 1 or 2 flash devices */
+#define FLASH_PORT_WIDTH32
+#undef FLASH_PORT_WIDTH16
+
+#ifdef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH		ushort
+#define FLASH_PORT_WIDTHV		vu_short
+#define SWAP(x)               __swab16(x)
+#else
+#define FLASH_PORT_WIDTH		ulong
+#define FLASH_PORT_WIDTHV		vu_long
+#define SWAP(x)               __swab32(x)
+#endif
+
+/* Intel-compatible flash ID */
+#define INTEL_COMPAT  0x00890089
+#define INTEL_ALT     0x00B000B0
+
+/* Intel-compatible flash commands */
+#define INTEL_PROGRAM 0x00100010
+#define INTEL_ERASE   0x00200020
+#define INTEL_CLEAR   0x00500050
+#define INTEL_LOCKBIT 0x00600060
+#define INTEL_PROTECT 0x00010001
+#define INTEL_STATUS  0x00700070
+#define INTEL_READID  0x00900090
+#define INTEL_CONFIRM 0x00D000D0
+#define INTEL_RESET   0xFFFFFFFF
+
+/* Intel-compatible flash status bits */
+#define INTEL_FINISHED 0x00800080
+#define INTEL_OK       0x00800080
+
+#define FPW	   FLASH_PORT_WIDTH
+#define FPWV   FLASH_PORT_WIDTHV
+
+#define mb() __asm__ __volatile__ ("" : : : "memory")
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (FPW *addr, flash_info_t *info);
+static int write_data (flash_info_t *info, ulong dest, FPW data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+void inline spin_wheel (void);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	int i;
+	ulong size = 0;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		switch (i) {
+		case 0:
+			flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
+			flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
+			break;
+		case 1:
+			flash_get_size ((FPW *) PHYS_FLASH_2, &flash_info[i]);
+			flash_get_offsets (PHYS_FLASH_2, &flash_info[i]);
+			break;
+		default:
+			panic ("configured to many flash banks!\n");
+			break;
+		}
+		size += flash_info[i].size;
+	}
+
+	/* Protect monitor and environment sectors
+	 */
+	flash_protect ( FLAG_PROTECT_SET,
+			CFG_FLASH_BASE,
+			CFG_FLASH_BASE + monitor_flash_len - 1,
+			&flash_info[0] );
+
+	flash_protect ( FLAG_PROTECT_SET,
+			CFG_ENV_ADDR,
+			CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0] );
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
+			info->protect[i] = 0;
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F128J3A:
+		printf ("28F128J3A\n");
+		break;
+
+	case FLASH_28F640J3A:
+		printf ("28F640J3A\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (FPW *addr, flash_info_t *info)
+{
+	volatile FPW value;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x5555] = (FPW) 0x00AA00AA;
+	addr[0x2AAA] = (FPW) 0x00550055;
+	addr[0x5555] = (FPW) 0x00900090;
+
+	mb ();
+	value = addr[0];
+
+	switch (value) {
+
+	case (FPW) INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+		return (0);			/* no or unknown flash  */
+	}
+
+	mb ();
+	value = addr[1];			/* device ID        */
+
+	switch (value) {
+
+	case (FPW) INTEL_ID_28F128J3A:
+		info->flash_id += FLASH_28F128J3A;
+		info->sector_count = 128;
+		info->size = 0x02000000;
+		break;				/* => 32 MB     */
+
+	case (FPW) INTEL_ID_28F640J3A:
+		info->flash_id += FLASH_28F640J3A;
+		info->sector_count = 64;
+		info->size = 0x01000000;
+		break;				/* => 16 MB     */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+			info->sector_count, CFG_MAX_FLASH_SECT);
+		info->sector_count = CFG_MAX_FLASH_SECT;
+	}
+
+	addr[0] = (FPW) 0x00FF00FF;		/* restore read mode */
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong type, start, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	start = get_timer (0);
+	last = start;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			FPWV *addr = (FPWV *) (info->start[sect]);
+			FPW status;
+
+			printf ("Erasing sector %2d ... ", sect);
+
+			/* arm simple, non interrupt dependent timer */
+			reset_timer_masked ();
+
+			*addr = (FPW) 0x00500050;	/* clear status register */
+			*addr = (FPW) 0x00200020;	/* erase setup */
+			*addr = (FPW) 0x00D000D0;	/* erase confirm */
+
+			while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+				if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					*addr = (FPW) 0x00B000B0;	/* suspend erase     */
+					*addr = (FPW) 0x00FF00FF;	/* reset to read mode */
+					rcode = 1;
+					break;
+				}
+			}
+
+			*addr = 0x00500050;	/* clear status register cmd.   */
+			*addr = 0x00FF00FF;	/* resest to read mode          */
+
+			printf (" done\n");
+		}
+	}
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	FPW data;
+	int count, i, l, rc, port_width;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+/* get lower word aligned address */
+#ifdef FLASH_PORT_WIDTH16
+	wp = (addr & ~1);
+	port_width = 2;
+#else
+	wp = (addr & ~3);
+	port_width = 4;
+#endif
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < port_width && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < port_width; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	count = 0;
+	while (cnt >= port_width) {
+		data = 0;
+		for (i = 0; i < port_width; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+		cnt -= port_width;
+		if (count++ > 0x800) {
+			spin_wheel ();
+			count = 0;
+		}
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < port_width; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_data (info, wp, SWAP (data)));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t *info, ulong dest, FPW data)
+{
+	FPWV *addr = (FPWV *) dest;
+	ulong status;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr);
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	*addr = (FPW) 0x00400040;	/* write setup */
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();
+
+	/* wait while polling the status register */
+	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+		if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+			return (1);
+		}
+	}
+
+	*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (0);
+}
+
+void inline spin_wheel (void)
+{
+	static int p = 0;
+	static char w[] = "\\/-";
+
+	printf ("\010%c", w[p]);
+	(++p == 3) ? (p = 0) : 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Set/Clear sector's lock bit, returns:
+ * 0 - OK
+ * 1 - Error (timeout, voltage problems, etc.)
+ */
+int flash_real_protect(flash_info_t *info, long sector, int prot)
+{
+	int i;
+	int rc = 0;
+	vu_long *addr = (vu_long *)(info->start[sector]);
+	int flag = disable_interrupts();
+
+	*addr = INTEL_CLEAR;	/* Clear status register */
+	if (prot) {			/* Set sector lock bit */
+		*addr = INTEL_LOCKBIT;	/* Sector lock bit */
+		*addr = INTEL_PROTECT;	/* set */
+	}
+	else {				/* Clear sector lock bit */
+		*addr = INTEL_LOCKBIT;	/* All sectors lock bits */
+		*addr = INTEL_CONFIRM;	/* clear */
+	}
+
+	reset_timer_masked ();
+
+	while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
+		if (get_timer_masked () > CFG_FLASH_UNLOCK_TOUT) {
+			printf("Flash lock bit operation timed out\n");
+			rc = 1;
+			break;
+		}
+	}
+
+	if (*addr != INTEL_OK) {
+		printf("Flash lock bit operation failed at %08X, CSR=%08X\n",
+		       (uint)addr, (uint)*addr);
+		rc = 1;
+	}
+
+	if (!rc)
+		info->protect[sector] = prot;
+
+	/*
+	 * Clear lock bit command clears all sectors lock bits, so
+	 * we have to restore lock bits of protected sectors.
+	 */
+	if (!prot)
+	{
+		for (i = 0; i < info->sector_count; i++)
+		{
+			if (info->protect[i])
+			{
+				reset_timer_masked ();
+				addr = (vu_long *)(info->start[i]);
+				*addr = INTEL_LOCKBIT;	/* Sector lock bit */
+				*addr = INTEL_PROTECT;	/* set */
+				while ((*addr & INTEL_FINISHED) != INTEL_FINISHED)
+				{
+					if (get_timer_masked () > CFG_FLASH_UNLOCK_TOUT)
+					{
+						printf("Flash lock bit operation timed out\n");
+						rc = 1;
+						break;
+					}
+				}
+			}
+		}
+	}
+
+	if (flag)
+		enable_interrupts();
+
+	*addr = INTEL_RESET;		/* Reset to read array mode */
+
+	return rc;
+}

board/xm250/memsetup.S

@@ -0,0 +1,519 @@
+/*
+ * Most of this taken from Redboot hal_platform_setup.h with cleanup
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/pxa-regs.h>
+
+DRAM_SIZE:  .long   CFG_DRAM_SIZE
+
+/* wait for coprocessor write complete */
+	.macro CPWAIT reg
+	mrc	p15,0,\reg,c2,c0,0
+	mov	\reg,\reg
+	sub	pc,pc,#4
+	.endm
+/*
+	.macro SET_LED val
+	ldr	r6, =CRADLE_LED_CLR_REG
+	ldr	r7, =0
+	str	r7, [r6]
+	ldr	r6, =CRADLE_LED_SET_REG
+	ldr	r7, =\val
+	str	r7, [r6]
+	.endm
+*/
+
+.globl memsetup
+memsetup:
+
+	mov	r10, lr
+
+	/* Set up GPIO pins first */
+
+	ldr	r0,   =GPSR0
+	ldr	r1,   =CFG_GPSR0_VAL
+	str	r1,   [r0]
+
+	ldr	r0,   =GPSR1
+	ldr	r1,   =CFG_GPSR1_VAL
+	str	r1,   [r0]
+
+	ldr	r0,   =GPSR2
+	ldr	r1,   =CFG_GPSR2_VAL
+	str	r1,   [r0]
+
+	ldr	r0,   =GPCR0
+	ldr	r1,   =CFG_GPCR0_VAL
+	str	r1,   [r0]
+
+	ldr	r0,   =GPCR1
+	ldr	r1,   =CFG_GPCR1_VAL
+	str	r1,   [r0]
+
+	ldr	r0,   =GPCR2
+	ldr	r1,   =CFG_GPCR2_VAL
+	str	r1,   [r0]
+
+	ldr	r0,   =GRER0
+	ldr	r1,   =CFG_GRER0_VAL
+	str	r1,   [r0]
+
+	ldr	r0,   =GRER1
+	ldr	r1,   =CFG_GRER1_VAL
+	str	r1,   [r0]
+
+	ldr	r0,   =GRER2
+	ldr	r1,   =CFG_GRER2_VAL
+	str	r1,   [r0]
+
+	ldr	r0,   =GFER0
+	ldr	r1,   =CFG_GFER0_VAL
+	str	r1,   [r0]
+
+	ldr	r0,   =GFER1
+	ldr	r1,   =CFG_GFER1_VAL
+	str	r1,   [r0]
+
+	ldr	r0,   =GFER2
+	ldr	r1,   =CFG_GFER2_VAL
+	str	r1,   [r0]
+
+	ldr	r0,   =GPDR0
+	ldr	r1,   =CFG_GPDR0_VAL
+	str	r1,   [r0]
+
+	ldr	r0,   =GPDR1
+	ldr	r1,   =CFG_GPDR1_VAL
+	str	r1,   [r0]
+
+	ldr	r0,   =GPDR2
+	ldr	r1,   =CFG_GPDR2_VAL
+	str	r1,   [r0]
+
+	ldr	r0,   =GAFR0_L
+	ldr	r1,   =CFG_GAFR0_L_VAL
+	str	r1,   [r0]
+
+	ldr	r0,   =GAFR0_U
+	ldr	r1,   =CFG_GAFR0_U_VAL
+	str	r1,   [r0]
+
+	ldr	r0,   =GAFR1_L
+	ldr	r1,   =CFG_GAFR1_L_VAL
+	str	r1,   [r0]
+
+	ldr	r0,   =GAFR1_U
+	ldr	r1,   =CFG_GAFR1_U_VAL
+	str	r1,   [r0]
+
+	ldr	r0,   =GAFR2_L
+	ldr	r1,   =CFG_GAFR2_L_VAL
+	str	r1,   [r0]
+
+	ldr	r0,   =GAFR2_U
+	ldr	r1,   =CFG_GAFR2_U_VAL
+	str	r1,   [r0]
+
+	/* enable GPIO pins */
+	ldr	r0,   =PSSR
+	ldr	r1,   =CFG_PSSR_VAL
+	str	r1,   [r0]
+
+	/* SET_LED 1 */
+
+	ldr	r3, =MSC1		/* low - bank 2 Lubbock Registers / SRAM */
+	ldr	r2, =CFG_MSC1_VAL	/* high - bank 3 Ethernet Controller */
+	str	r2, [r3]		/* need to set MSC1 before trying to write to the HEX LEDs */
+	ldr	r2, [r3]		/* need to read it back to make sure the value latches (see MSC section of manual) */
+
+
+/*********************************************************************
+ *  Initlialize Memory Controller
+ *
+ *  See PXA250 Operating System Developer's Guide
+ *
+ *  pause for 200 uSecs- allow internal clocks to settle
+ *  *Note: only need this if hard reset... doing it anyway for now
+ */
+
+	@ Step 1
+	@ ---- Wait 200 usec
+	ldr	r3, =OSCR	@ reset the OS Timer Count to zero
+	mov	r2, #0
+	str	r2, [r3]
+	ldr	r4, =0x300	@ really 0x2E1 is about 200usec, so 0x300 should be plenty
+1:
+	ldr	r2, [r3]
+	cmp	r4, r2
+	bgt	1b
+
+	/* SET_LED 2 */
+
+mem_init:
+	@ get memory controller base address
+	ldr	r1,  =MEMC_BASE
+
+
+@****************************************************************************
+@  Step 2
+@
+
+	@ Step 2a
+	@ write msc0, read back to ensure data latches
+	@
+	ldr	r2,   =CFG_MSC0_VAL
+	str	r2,   [r1, #MSC0_OFFSET]
+	ldr	r2,   [r1, #MSC0_OFFSET]
+
+	@ write msc1
+	ldr	r2,  =CFG_MSC1_VAL
+	str	r2,  [r1, #MSC1_OFFSET]
+	ldr	r2,  [r1, #MSC1_OFFSET]
+
+	@ write msc2
+	ldr	r2,  =CFG_MSC2_VAL
+	str	r2,  [r1, #MSC2_OFFSET]
+	ldr	r2,  [r1, #MSC2_OFFSET]
+
+	@ Step 2b
+	@ write mecr
+	ldr	r2,  =CFG_MECR_VAL
+	str	r2,  [r1, #MECR_OFFSET]
+
+	@ write mcmem0
+	ldr	r2,  =CFG_MCMEM0_VAL
+	str	r2,  [r1, #MCMEM0_OFFSET]
+
+	@ write mcmem1
+	ldr	r2,  =CFG_MCMEM1_VAL
+	str	r2,  [r1, #MCMEM1_OFFSET]
+
+	@ write mcatt0
+	ldr	r2,  =CFG_MCATT0_VAL
+	str	r2,  [r1, #MCATT0_OFFSET]
+
+	@ write mcatt1
+	ldr	r2,  =CFG_MCATT1_VAL
+	str	r2,  [r1, #MCATT1_OFFSET]
+
+	@ write mcio0
+	ldr	r2,  =CFG_MCIO0_VAL
+	str	r2,  [r1, #MCIO0_OFFSET]
+
+	@ write mcio1
+	ldr	r2,  =CFG_MCIO1_VAL
+	str	r2,  [r1, #MCIO1_OFFSET]
+
+	/*SET_LED 3 */
+
+	@ Step 2c
+	@ fly-by-dma is defeatured on this part
+	@ write flycnfg
+	@ldr	r2,  =CFG_FLYCNFG_VAL
+	@str	r2,  [r1, #FLYCNFG_OFFSET]
+
+/* FIXME Does this sequence really make sense */
+#ifdef REDBOOT_WAY
+	@ Step 2d
+	@ get the mdrefr settings
+	ldr	r3,  =CFG_MDREFR_VAL
+
+	@ extract DRI field (we need a valid DRI field)
+	@
+	ldr	r2,  =0xFFF
+
+	@ valid DRI field in r3
+	@
+	and	r3,  r3,  r2
+
+	@ get the reset state of MDREFR
+	@
+	ldr	r4,  [r1, #MDREFR_OFFSET]
+
+	@ clear the DRI field
+	@
+	bic	r4,  r4,  r2
+
+	@ insert the valid DRI field loaded above
+	@
+	orr	r4,  r4,  r3
+
+	@ write back mdrefr
+	@
+	str	r4,  [r1, #MDREFR_OFFSET]
+
+	@ *Note: preserve the mdrefr value in r4 *
+
+	/*SET_LED 4 */
+
+@****************************************************************************
+@  Step 3
+@
+@ NO SRAM
+
+	mov   pc, r10
+
+
+@****************************************************************************
+@  Step 4
+@
+
+	@ Assumes previous mdrefr value in r4, if not then read current mdrefr
+
+	@ clear the free-running clock bits
+	@ (clear K0Free, K1Free, K2Free
+	@
+	bic	r4,  r4,  #(0x00800000 | 0x01000000 | 0x02000000)
+
+	@ set K0RUN for CPLD clock
+	@
+	orr	r4,  r4, #0x00002000
+
+	@ set K1RUN if bank 0 installed
+	@
+	orr	r4,  r4, #0x00010000
+
+	@ write back mdrefr
+	@
+	str	r4,  [r1, #MDREFR_OFFSET]
+	ldr	r4,  [r1, #MDREFR_OFFSET]
+
+	@ deassert SLFRSH
+	@
+	bic	r4,  r4,  #0x00400000
+
+	@ write back mdrefr
+	@
+	str	r4,  [r1, #MDREFR_OFFSET]
+
+	@ assert E1PIN
+	@
+	orr	r4,  r4,  #0x00008000
+
+	@ write back mdrefr
+	@
+	str	r4,  [r1, #MDREFR_OFFSET]
+	ldr	r4,  [r1, #MDREFR_OFFSET]
+	nop
+	nop
+#else
+	@ Step 2d
+	@ get the mdrefr settings
+	ldr	r4,  =CFG_MDREFR_VAL
+
+	@ write back mdrefr
+	@
+	str	r4,  [r1, #MDREFR_OFFSET]
+
+	@  Step 4
+
+	@ set K0RUN for FLASH clock
+	@
+	orr	r4,  r4, #0x00002000
+
+	@ set K1RUN for bank DRAM 0
+	@
+	orr	r4,  r4, #0x00010000
+
+	@ set K2RUN for bank PLD
+	@
+	orr	r4,  r4, #0x00040000
+
+	@ write back mdrefr
+	@
+	str	r4,  [r1, #MDREFR_OFFSET]
+	ldr	r4,  [r1, #MDREFR_OFFSET]
+
+	@ deassert SLFRSH
+	@
+	bic	r4,  r4,  #0x00400000
+
+	@ write back mdrefr
+	@
+	str	r4,  [r1, #MDREFR_OFFSET]
+
+	@ assert E1PIN
+	@
+	orr	r4,  r4,  #0x00008000
+
+	@ write back mdrefr
+	@
+	str	r4,  [r1, #MDREFR_OFFSET]
+	ldr	r4,  [r1, #MDREFR_OFFSET]
+	nop
+	nop
+#endif
+
+	@ Step 4d
+	@ fetch platform value of mdcnfg
+	@
+	ldr	r2,  =CFG_MDCNFG_VAL
+
+	@ disable all sdram banks
+	@
+	bic	r2,  r2,  #(MDCNFG_DE0 | MDCNFG_DE1)
+	bic	r2,  r2,  #(MDCNFG_DE2 | MDCNFG_DE3)
+
+	@ program banks 0/1 for bus width
+	@
+	bic	r2,  r2,  #MDCNFG_DWID0		@0=32-bit
+
+	@ write initial value of mdcnfg, w/o enabling sdram banks
+	@
+	str	r2,  [r1, #MDCNFG_OFFSET]
+
+	@ Step 4e
+	@ pause for 200 uSecs
+	@
+	ldr	r3, =OSCR	@ reset the OS Timer Count to zero
+	mov	r2, #0
+	str	r2, [r3]
+	ldr	r4, =0x300	@ really 0x2E1 is about 200usec, so 0x300 should be plenty
+1:
+	ldr	r2, [r3]
+	cmp	r4, r2
+	bgt	1b
+
+	/*SET_LED 5 */
+
+	/* Why is this here??? */
+	mov	r0, #0x78		@turn everything off
+	mcr	p15, 0, r0, c1, c0, 0	@(caches off, MMU off, etc.)
+
+	@ Step 4f
+	@ Access memory *not yet enabled* for CBR refresh cycles (8)
+	@ - CBR is generated for all banks
+
+	ldr	r2, =CFG_DRAM_BASE
+	str	r2, [r2]
+	str	r2, [r2]
+	str	r2, [r2]
+	str	r2, [r2]
+	str	r2, [r2]
+	str	r2, [r2]
+	str	r2, [r2]
+	str	r2, [r2]
+
+	@ Step 4g
+	@get memory controller base address
+	@
+	ldr	r1,  =MEMC_BASE
+
+	@fetch current mdcnfg value
+	@
+	ldr	r3,  [r1, #MDCNFG_OFFSET]
+
+	@enable sdram bank 0 if installed (must do for any populated bank)
+	@
+	orr	r3,  r3,  #MDCNFG_DE0
+
+	@write back mdcnfg, enabling the sdram bank(s)
+	@
+	str	r3,  [r1, #MDCNFG_OFFSET]
+
+	@ Step 4h
+	@ write mdmrs
+	@
+	ldr	r2,  =CFG_MDMRS_VAL
+	str	r2,  [r1, #MDMRS_OFFSET]
+
+	@ Done Memory Init
+
+	/*SET_LED 6 */
+
+	@********************************************************************
+	@ Disable (mask) all interrupts at the interrupt controller
+	@
+
+	@ clear the interrupt level register (use IRQ, not FIQ)
+	@
+	mov	r1, #0
+	ldr	r2,  =ICLR
+	str	r1,  [r2]
+
+	@ Set interrupt mask register
+	@
+	ldr	r1,  =CFG_ICMR_VAL
+	ldr	r2,  =ICMR
+	str	r1,  [r2]
+
+	@ ********************************************************************
+	@ Disable the peripheral clocks, and set the core clock
+	@
+
+	@ Turn Off ALL on-chip peripheral clocks for re-configuration
+	@
+	ldr	r1,  =CKEN
+	mov	r2,  #0
+	str	r2,  [r1]
+
+	@ set core clocks
+	@
+	ldr	r2,  =CFG_CCCR_VAL
+	ldr	r1,  =CCCR
+	str	r2,  [r1]
+
+#ifdef ENABLE32KHZ
+	@ enable the 32Khz oscillator for RTC and PowerManager
+	@
+	ldr	r1,  =OSCC
+	mov	r2,  #OSCC_OON
+	str	r2,  [r1]
+
+	@ NOTE:	 spin here until OSCC.OOK get set,
+	@	 meaning the PLL has settled.
+	@
+60:
+	ldr	r2, [r1]
+	ands	r2, r2, #1
+	beq	60b
+#endif
+
+	@ Turn on needed clocks
+	@
+	ldr	r1,  =CKEN
+	ldr	r2,  =CFG_CKEN_VAL
+	str	r2,  [r1]
+
+	/*SET_LED 7 */
+
+/* Is this needed???? */
+#define NODEBUG
+#ifdef NODEBUG
+	/*Disable software and data breakpoints */
+	mov	r0,#0
+	mcr	p15,0,r0,c14,c8,0	/* ibcr0 */
+	mcr	p15,0,r0,c14,c9,0	/* ibcr1 */
+	mcr	p15,0,r0,c14,c4,0	/* dbcon */
+
+	/*Enable all debug functionality */
+	mov	r0,#0x80000000
+	mcr	p14,0,r0,c10,c0,0	/* dcsr */
+
+#endif
+
+	/*SET_LED 8 */
+
+	mov	pc, r10
+
+@ End memsetup

board/xm250/u-boot.lds

@@ -0,0 +1,55 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/pxa/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}

board/xm250/xm250.c

@@ -0,0 +1,91 @@
+/*
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch/pxa-regs.h>
+#include <common.h>
+
+/* ------------------------------------------------------------------------- */
+
+/* local prototypes */
+
+inline void sleep (int i);
+
+inline void
+/**********************************************************/
+sleep (int i)
+/**********************************************************/
+{
+	while (i--) {
+		udelay (1000000);
+	}
+}
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int
+/**********************************************************/
+board_post_init (void)
+/**********************************************************/
+{
+	return (0);
+}
+
+int
+/**********************************************************/
+board_init (void)
+/**********************************************************/
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	/* arch number of MicroSys XM250 */
+	gd->bd->bi_arch_number = 444;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0xa0000100;
+
+	return 0;
+}
+
+int
+/**********************************************************/
+dram_init (void)
+/**********************************************************/
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size  = PHYS_SDRAM_1_SIZE;
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size  = PHYS_SDRAM_2_SIZE;
+	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
+	gd->bd->bi_dram[2].size  = PHYS_SDRAM_3_SIZE;
+	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
+	gd->bd->bi_dram[3].size  = PHYS_SDRAM_4_SIZE;
+
+	return (0);
+}

common/Makefile

@@ -39,7 +39,7 @@ COBJS	= main.o ACEX1K.o altera.o bedbug.o \
 	  cmd_mem.o cmd_mii.o cmd_misc.o cmd_mmc.o \
 	  cmd_nand.o cmd_net.o cmd_nvedit.o \
 	  cmd_pci.o cmd_pcmcia.o cmd_portio.o \
-	  cmd_reginfo.o cmd_scsi.o cmd_spi.o cmd_usb.o cmd_vfd.o \
+	  cmd_reginfo.o cmd_reiser.o cmd_scsi.o cmd_spi.o cmd_usb.o cmd_vfd.o \
 	  command.o console.o devices.o dlmalloc.o docecc.o \
 	  environment.o env_common.o \
 	  env_dataflash.o env_flash.o env_eeprom.o env_nvram.o env_nowhere.o exports.o \

common/cmd_ace.c

@@ -190,16 +190,13 @@ static unsigned long systemace_read(int dev,
 	      /* Write sector count | ReadMemCardData. */
 	    ace_writew((trans&0xff) | 0x0300, 0x14);
 
-	      /* CONTROLREG = CFGRESET|LOCKREQ */
-	    ace_writew(0x0082, 0x18);
-
 	    retry = trans * 16;
 	    while (retry > 0) {
 		  int idx;
 
 		    /* Wait for buffer to become ready. */
 		  while (! (ace_readw(0x04) & 0x0020)) {
-			udelay(1000);
+			udelay(100);
 		  }
 
 		    /* Read 16 words of 2bytes from the sector buffer. */

common/cmd_autoscript.c

@@ -68,7 +68,7 @@ autoscript (ulong addr)
 	memmove (hdr, (char *)addr, sizeof(image_header_t));
 
 	if (ntohl(hdr->ih_magic) != IH_MAGIC) {
-		printf ("Bad magic number\n");
+		puts ("Bad magic number\n");
 		return 1;
 	}
 
@@ -77,7 +77,7 @@ autoscript (ulong addr)
 	len = sizeof (image_header_t);
 	data = (ulong)hdr;
 	if (crc32(0, (char *)data, len) != crc) {
-		printf ("Bad header crc\n");
+		puts ("Bad header crc\n");
 		return 1;
 	}
 
@@ -86,13 +86,13 @@ autoscript (ulong addr)
 
 	if (verify) {
 		if (crc32(0, (char *)data, len) != ntohl(hdr->ih_dcrc)) {
-			printf ("Bad data crc\n");
+			puts ("Bad data crc\n");
 			return 1;
 		}
 	}
 
 	if (hdr->ih_type != IH_TYPE_SCRIPT) {
-		printf ("Bad image type\n");
+		puts ("Bad image type\n");
 		return 1;
 	}
 
@@ -100,7 +100,7 @@ autoscript (ulong addr)
 	len_ptr = (ulong *)data;
 
 	if ((len = ntohl(*len_ptr)) == 0) {
-		printf ("Empty Script\n");
+		puts ("Empty Script\n");
 		return 1;
 	}
 

common/cmd_bdinfo.c

@@ -77,19 +77,19 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 #endif
 	print_str ("busfreq",	    strmhz(buf, bd->bi_busfreq));
 #endif /* CONFIG_405GP, CONFIG_405CR, CONFIG_405EP, CONFIG_XILINX_ML300 */
-	printf ("ethaddr     =");
+	puts ("ethaddr     =");
 	for (i=0; i<6; ++i) {
 		printf ("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]);
 	}
 #if (defined CONFIG_PN62) || (defined CONFIG_PPCHAMELEONEVB) \
     || (defined CONFIG_MPC8540ADS) || (defined CONFIG_MPC8560ADS)
-	printf ("\neth1addr    =");
+	puts ("\neth1addr    =");
 	for (i=0; i<6; ++i) {
 		printf ("%c%02X", i ? ':' : ' ', bd->bi_enet1addr[i]);
 	}
 #endif /* CONFIG_PN62 */
 #if defined(CONFIG_MPC8540ADS) || defined(CONFIG_MPC8560ADS)
-       printf ("\neth2addr    =");
+       puts ("\neth2addr    =");
        for (i=0; i<6; ++i) {
 		printf ("%c%02X", i ? ':' : ' ', bd->bi_enet2addr[i]);
 	}
@@ -97,7 +97,7 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 #ifdef CONFIG_HERMES
 	print_str ("ethspeed",	    strmhz(buf, bd->bi_ethspeed));
 #endif
-	printf ("\nIP addr     = ");	print_IPaddr (bd->bi_ip_addr);
+	puts ("\nIP addr     = ");	print_IPaddr (bd->bi_ip_addr);
 	printf ("\nbaudrate    = %6ld bps\n", bd->bi_baudrate   );
 	return 0;
 }
@@ -117,11 +117,11 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	print_num ("flashsize",		(ulong)bd->bi_flashsize);
 	print_num ("flashoffset",	(ulong)bd->bi_flashoffset);
 
-	printf ("ethaddr     =");
+	puts ("ethaddr     =");
 	for (i=0; i<6; ++i) {
 		printf ("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]);
 	}
-	printf ("\nip_addr     = ");
+	puts ("\nip_addr     = ");
 	print_IPaddr (bd->bi_ip_addr);
 	printf ("\nbaudrate    = %ld bps\n", bd->bi_baudrate);
 
@@ -145,11 +145,11 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	print_num ("flashsize",		(ulong)bd->bi_flashsize);
 	print_num ("flashoffset",	(ulong)bd->bi_flashoffset);
 
-	printf ("ethaddr     =");
+	puts ("ethaddr     =");
 	for (i=0; i<6; ++i) {
 		printf ("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]);
 	}
-	printf ("\nip_addr     = ");
+	puts ("\nip_addr     = ");
 	print_IPaddr (bd->bi_ip_addr);
 	printf ("\nbaudrate    = %d bps\n", bd->bi_baudrate);
 
@@ -176,11 +176,11 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 		print_num("-> size",	bd->bi_dram[i].size);
 	}
 
-	printf ("ethaddr     =");
+	puts ("ethaddr     =");
 	for (i=0; i<6; ++i) {
 		printf ("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]);
 	}
-	printf ("\n"
+	puts  ( "\n"
 		"ip_addr     = ");
 	print_IPaddr (bd->bi_ip_addr);
 	printf ("\n"

common/cmd_bootm.c

@@ -184,7 +184,7 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 		} else
 #endif	/* __I386__ */
 	    {
-		printf ("Bad Magic Number\n");
+		puts ("Bad Magic Number\n");
 		SHOW_BOOT_PROGRESS (-1);
 		return 1;
 	    }
@@ -198,7 +198,7 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	hdr->ih_hcrc = 0;
 
 	if (crc32 (0, (char *)data, len) != checksum) {
-		printf ("Bad Header Checksum\n");
+		puts ("Bad Header Checksum\n");
 		SHOW_BOOT_PROGRESS (-2);
 		return 1;
 	}
@@ -218,13 +218,13 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 #endif
 
 	if (verify) {
-		printf ("   Verifying Checksum ... ");
+		puts ("   Verifying Checksum ... ");
 		if (crc32 (0, (char *)data, len) != ntohl(hdr->ih_dcrc)) {
 			printf ("Bad Data CRC\n");
 			SHOW_BOOT_PROGRESS (-3);
 			return 1;
 		}
-		printf ("OK\n");
+		puts ("OK\n");
 	}
 	SHOW_BOOT_PROGRESS (4);
 
@@ -325,7 +325,7 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 		printf ("   Uncompressing %s ... ", name);
 		if (gunzip ((void *)ntohl(hdr->ih_load), unc_len,
 			    (uchar *)data, (int *)&len) != 0) {
-			printf ("GUNZIP ERROR - must RESET board to recover\n");
+			puts ("GUNZIP ERROR - must RESET board to recover\n");
 			SHOW_BOOT_PROGRESS (-6);
 			do_reset (cmdtp, flag, argc, argv);
 		}
@@ -356,7 +356,7 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 		SHOW_BOOT_PROGRESS (-7);
 		return 1;
 	}
-	printf ("OK\n");
+	puts ("OK\n");
 	SHOW_BOOT_PROGRESS (7);
 
 	switch (hdr->ih_type) {
@@ -435,7 +435,7 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 	SHOW_BOOT_PROGRESS (-9);
 #ifdef DEBUG
-	printf ("\n## Control returned to monitor - resetting...\n");
+	puts ("\n## Control returned to monitor - resetting...\n");
 	do_reset (cmdtp, flag, argc, argv);
 #endif
 	return 1;
@@ -597,7 +597,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
 		memmove (&header, (char *)addr, sizeof(image_header_t));
 
 		if (hdr->ih_magic  != IH_MAGIC) {
-			printf ("Bad Magic Number\n");
+			puts ("Bad Magic Number\n");
 			SHOW_BOOT_PROGRESS (-10);
 			do_reset (cmdtp, flag, argc, argv);
 		}
@@ -609,7 +609,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
 		hdr->ih_hcrc = 0;
 
 		if (crc32 (0, (char *)data, len) != checksum) {
-			printf ("Bad Header Checksum\n");
+			puts ("Bad Header Checksum\n");
 			SHOW_BOOT_PROGRESS (-11);
 			do_reset (cmdtp, flag, argc, argv);
 		}
@@ -627,7 +627,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
 			ulong cdata = data, edata = cdata + len;
 #endif	/* CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG */
 
-			printf ("   Verifying Checksum ... ");
+			puts ("   Verifying Checksum ... ");
 
 #if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
 
@@ -646,11 +646,11 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
 #endif	/* CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG */
 
 			if (csum != hdr->ih_dcrc) {
-				printf ("Bad Data CRC\n");
+				puts ("Bad Data CRC\n");
 				SHOW_BOOT_PROGRESS (-12);
 				do_reset (cmdtp, flag, argc, argv);
 			}
-			printf ("OK\n");
+			puts ("OK\n");
 		}
 
 		SHOW_BOOT_PROGRESS (11);
@@ -658,7 +658,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
 		if ((hdr->ih_os   != IH_OS_LINUX)	||
 		    (hdr->ih_arch != IH_CPU_PPC)	||
 		    (hdr->ih_type != IH_TYPE_RAMDISK)	) {
-			printf ("No Linux PPC Ramdisk Image\n");
+			puts ("No Linux PPC Ramdisk Image\n");
 			SHOW_BOOT_PROGRESS (-13);
 			do_reset (cmdtp, flag, argc, argv);
 		}
@@ -756,7 +756,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
 #else	/* !(CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG) */
 		memmove ((void *)initrd_start, (void *)data, len);
 #endif	/* CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG */
-		printf ("OK\n");
+		puts ("OK\n");
 	    }
 	} else {
 		initrd_start = 0;
@@ -1014,7 +1014,7 @@ static int image_info (ulong addr)
 	memmove (&header, (char *)addr, sizeof(image_header_t));
 
 	if (ntohl(hdr->ih_magic) != IH_MAGIC) {
-		printf ("   Bad Magic Number\n");
+		puts ("   Bad Magic Number\n");
 		return 1;
 	}
 
@@ -1025,7 +1025,7 @@ static int image_info (ulong addr)
 	hdr->ih_hcrc = 0;
 
 	if (crc32 (0, (char *)data, len) != checksum) {
-		printf ("   Bad Header Checksum\n");
+		puts ("   Bad Header Checksum\n");
 		return 1;
 	}
 
@@ -1035,12 +1035,12 @@ static int image_info (ulong addr)
 	data = addr + sizeof(image_header_t);
 	len  = ntohl(hdr->ih_size);
 
-	printf ("   Verifying Checksum ... ");
+	puts ("   Verifying Checksum ... ");
 	if (crc32 (0, (char *)data, len) != ntohl(hdr->ih_dcrc)) {
-		printf ("   Bad Data CRC\n");
+		puts ("   Bad Data CRC\n");
 		return 1;
 	}
-	printf ("OK\n");
+	puts ("OK\n");
 	return 0;
 }
 
@@ -1091,11 +1091,11 @@ int do_imls (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 			data = (ulong)hdr + sizeof(image_header_t);
 			len  = ntohl(hdr->ih_size);
 
-			printf ("   Verifying Checksum ... ");
+			puts ("   Verifying Checksum ... ");
 			if (crc32 (0, (char *)data, len) != ntohl(hdr->ih_dcrc)) {
-				printf ("   Bad Data CRC\n");
+				puts ("   Bad Data CRC\n");
 			}
-			printf ("OK\n");
+			puts ("OK\n");
 next_sector:		;
 		}
 next_bank:	;
@@ -1128,18 +1128,19 @@ print_image_hdr (image_header_t *hdr)
 		tm.tm_year, tm.tm_mon, tm.tm_mday,
 		tm.tm_hour, tm.tm_min, tm.tm_sec);
 #endif	/* CFG_CMD_DATE, CONFIG_TIMESTAMP */
-	printf ("   Image Type:   "); print_type(hdr); printf ("\n");
-	printf ("   Data Size:    %d Bytes = ", ntohl(hdr->ih_size));
+	puts ("   Image Type:   "); print_type(hdr);
+	printf ("\n   Data Size:    %d Bytes = ", ntohl(hdr->ih_size));
 	print_size (ntohl(hdr->ih_size), "\n");
-	printf ("   Load Address: %08x\n", ntohl(hdr->ih_load));
-	printf ("   Entry Point:  %08x\n", ntohl(hdr->ih_ep));
+	printf ("   Load Address: %08x\n"
+		"   Entry Point:  %08x\n",
+		 ntohl(hdr->ih_load), ntohl(hdr->ih_ep));
 
 	if (hdr->ih_type == IH_TYPE_MULTI) {
 		int i;
 		ulong len;
 		ulong *len_ptr = (ulong *)((ulong)hdr + sizeof(image_header_t));
 
-		printf ("   Contents:\n");
+		puts ("   Contents:\n");
 		for (i=0; (len = ntohl(*len_ptr)); ++i, ++len_ptr) {
 			printf ("   Image %d: %8ld Bytes = ", i, len);
 			print_size (len, "\n");
@@ -1244,7 +1245,7 @@ int gunzip(void *dst, int dstlen, unsigned char *src, int *lenp)
 	i = 10;
 	flags = src[3];
 	if (src[2] != DEFLATED || (flags & RESERVED) != 0) {
-		printf ("Error: Bad gzipped data\n");
+		puts ("Error: Bad gzipped data\n");
 		return (-1);
 	}
 	if ((flags & EXTRA_FIELD) != 0)
@@ -1258,7 +1259,7 @@ int gunzip(void *dst, int dstlen, unsigned char *src, int *lenp)
 	if ((flags & HEAD_CRC) != 0)
 		i += 2;
 	if (i >= *lenp) {
-		printf ("Error: gunzip out of data in header\n");
+		puts ("Error: gunzip out of data in header\n");
 		return (-1);
 	}
 

common/cmd_date.c

@@ -47,14 +47,14 @@ int do_date (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	switch (argc) {
 	case 2:			/* set date & time */
 		if (strcmp(argv[1],"reset") == 0) {
-			printf ("Reset RTC...\n");
+			puts ("Reset RTC...\n");
 			rtc_reset ();
 		} else {
 			/* initialize tm with current time */
 			rtc_get (&tm);
 			/* insert new date & time */
 			if (mk_date (argv[1], &tm) != 0) {
-				printf ("## Bad date format\n");
+				puts ("## Bad date format\n");
 				return 1;
 			}
 			/* and write to RTC */

common/cmd_diag.c

@@ -37,11 +37,11 @@ int do_diag (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 	if (argc == 1 || strcmp (argv[1], "run") != 0) {
 		/* List test info */
 		if (argc == 1) {
-			printf ("Available hardware tests:\n");
+			puts ("Available hardware tests:\n");
 			post_info (NULL);
-			printf ("Use 'diag [<test1> [<test2> ...]]'"
+			puts ("Use 'diag [<test1> [<test2> ...]]'"
 					" to get more info.\n");
-			printf ("Use 'diag run [<test1> [<test2> ...]]'"
+			puts ("Use 'diag run [<test1> [<test2> ...]]'"
 					" to run tests.\n");
 		} else {
 			for (i = 1; i < argc; i++) {

common/cmd_eeprom.c

@@ -75,7 +75,7 @@ int do_eeprom ( cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 
 			rcode = eeprom_read (dev_addr, off, (uchar *) addr, cnt);
 
-			printf ("done\n");
+			puts ("done\n");
 			return rcode;
 		} else if (strcmp (argv[1], "write") == 0) {
 			int rcode;
@@ -84,7 +84,7 @@ int do_eeprom ( cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 
 			rcode = eeprom_write (dev_addr, off, (uchar *) addr, cnt);
 
-			printf ("done\n");
+			puts ("done\n");
 			return rcode;
 		}
 	}
@@ -295,7 +295,7 @@ int eeprom_write (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cn
 #endif
 			}
 			if (i == MAX_ACKNOWLEDGE_POLLS) {
-				printf("EEPROM poll acknowledge failed\n");
+				puts ("EEPROM poll acknowledge failed\n");
 				rcode = 1;
 			}
 		}

common/cmd_elf.c

@@ -103,7 +103,7 @@ int do_bootvx ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	if ((tmp = getenv ("loadaddr")) != NULL) {
 		addr = simple_strtoul (tmp, NULL, 16);
 	} else {
-		printf ("No load address provided\n");
+		puts ("No load address provided\n");
 		return 1;
 	}
 
@@ -133,7 +133,7 @@ int do_bootvx ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	tmp = (char *) CFG_ETHERNET_MAC_ADDR;
 	memcpy ((char *) tmp, (char *) &gd->bd->bi_enetaddr[0], 6);
 #else
-	printf ("## Ethernet MAC address not copied to NV RAM\n");
+	puts ("## Ethernet MAC address not copied to NV RAM\n");
 #endif
 
 	/*
@@ -200,7 +200,7 @@ int do_bootvx ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 		 * to just copy
 		 */
 
-		printf ("No bootargs defined\n");
+		puts ("No bootargs defined\n");
 		return 1;
 #endif
 	}
@@ -214,7 +214,7 @@ int do_bootvx ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	if (valid_elf_image (addr)) {
 		addr = load_elf_image (addr);
 	} else {
-		printf ("## Not an ELF image, assuming binary\n");
+		puts ("## Not an ELF image, assuming binary\n");
 		/* leave addr as load_addr */
 	}
 
@@ -224,7 +224,7 @@ int do_bootvx ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 	((void (*)(void)) addr) ();
 
-	printf ("## vxWorks terminated\n");
+	puts ("## vxWorks terminated\n");
 	return 1;
 }
 

common/cmd_flash.c

@@ -149,14 +149,14 @@ flash_fill_sect_ranges (ulong addr_first, ulong addr_last,
 				if (addr_last > b_end) {
 					s_last[bank] = s_end;
 				} else {
-					printf ("Error: end address"
+					puts ("Error: end address"
 						" not on sector boundary\n");
 					rcode = 1;
 					break;
 				}
 			}
 			if (s_last[bank] < s_first[bank]) {
-				printf ("Error: end sector"
+				puts ("Error: end sector"
 					" precedes start sector\n");
 				rcode = 1;
 				break;
@@ -165,7 +165,7 @@ flash_fill_sect_ranges (ulong addr_first, ulong addr_last,
 			addr_first = (sect == s_end) ? b_end + 1: info->start[sect + 1];
 			(*s_count) += s_last[bank] - s_first[bank] + 1;
 		} else if (s_last[bank] >= 0) {
-			printf("Error: cannot span across banks when they are"
+			puts ("Error: cannot span across banks when they are"
 			       " mapped in reverse order\n");
 			rcode = 1;
 			break;
@@ -225,7 +225,7 @@ int do_flerase (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 	if ((n = abbrev_spec(argv[1], &info, &sect_first, &sect_last)) != 0) {
 		if (n < 0) {
-			printf("Bad sector specification\n");
+			puts ("Bad sector specification\n");
 			return 1;
 		}
 		printf ("Erase Flash Sectors %d-%d in Bank # %d ",
@@ -294,7 +294,7 @@ int flash_sect_erase (ulong addr_first, ulong addr_last)
 		}
 		printf ("Erased %d sectors\n", erased);
 	} else if (rcode == 0) {
-		printf ("Error: start and/or end address"
+		puts ("Error: start and/or end address"
 			" not on sector boundary\n");
 		rcode = 1;
 	}
@@ -332,7 +332,7 @@ int do_protect (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 		if (addr_dataflash(addr_first) && addr_dataflash(addr_last)) {
 			status = dataflash_real_protect(p,addr_first,addr_last);
 			if (status < 0){
-				printf("Bad DataFlash sector specification\n");
+				puts ("Bad DataFlash sector specification\n");
 				return 1;
 			}
 			printf("%sProtect %d DataFlash Sectors\n",
@@ -371,7 +371,7 @@ int do_protect (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 	if ((n = abbrev_spec(argv[2], &info, &sect_first, &sect_last)) != 0) {
 		if (n < 0) {
-			printf("Bad sector specification\n");
+			puts ("Bad sector specification\n");
 			return 1;
 		}
 		printf("%sProtect Flash Sectors %d-%d in Bank # %d\n",
@@ -411,7 +411,7 @@ int do_protect (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 		info = &flash_info[bank-1];
 
 		if (info->flash_id == FLASH_UNKNOWN) {
-			printf ("missing or unknown FLASH type\n");
+			puts ("missing or unknown FLASH type\n");
 			return 1;
 		}
 		for (i=0; i<info->sector_count; ++i) {
@@ -485,7 +485,7 @@ int flash_sect_protect (int p, ulong addr_first, ulong addr_last)
 		printf ("%sProtected %d sectors\n",
 			p ? "" : "Un-", protected);
 	} else if (rcode == 0) {
-		printf ("Error: start and/or end address"
+		puts ("Error: start and/or end address"
 			" not on sector boundary\n");
 		rcode = 1;
 	}

common/cmd_i2c.c

@@ -186,7 +186,7 @@ int do_i2c_md ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 		linebytes = (nbytes > DISP_LINE_LEN) ? DISP_LINE_LEN : nbytes;
 
 		if(i2c_read(chip, addr, alen, linebuf, linebytes) != 0) {
-			printf("Error reading the chip.\n");
+			puts ("Error reading the chip.\n");
 		} else {
 			printf("%04x:", addr);
 			cp = linebuf;
@@ -194,16 +194,16 @@ int do_i2c_md ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 				printf(" %02x", *cp++);
 				addr++;
 			}
-			printf("    ");
+			puts ("    ");
 			cp = linebuf;
 			for (j=0; j<linebytes; j++) {
 				if ((*cp < 0x20) || (*cp > 0x7e))
-					printf(".");
+					puts (".");
 				else
 					printf("%c", *cp);
 				cp++;
 			}
-			printf("\n");
+			putc ('\n');
 		}
 		nbytes -= linebytes;
 	} while (nbytes > 0);
@@ -285,7 +285,7 @@ int do_i2c_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 	while (count-- > 0) {
 		if(i2c_write(chip, addr++, alen, &byte, 1) != 0) {
-			printf("Error writing the chip.\n");
+			puts ("Error writing the chip.\n");
 		}
 		/*
 		 * Wait for the write to complete.  The write can take
@@ -374,7 +374,7 @@ int do_i2c_crc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	}
 	if(err > 0)
 	{
-		printf("Error reading the chip,\n");
+		puts ("Error reading the chip,\n");
 	} else {
 		printf ("%08lx\n", crc);
 	}
@@ -456,7 +456,7 @@ mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char *argv[])
 	do {
 		printf("%08lx:", addr);
 		if(i2c_read(chip, addr, alen, (char *)&data, size) != 0) {
-			printf("\nError reading the chip,\n");
+			puts ("\nError reading the chip,\n");
 		} else {
 			data = cpu_to_be32(data);
 			if(size == 1) {
@@ -505,7 +505,7 @@ mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char *argv[])
 				reset_cmd_timeout();
 #endif
 				if(i2c_write(chip, addr, alen, (char *)&data, size) != 0) {
-					printf("Error writing the chip.\n");
+					puts ("Error writing the chip.\n");
 				}
 #ifdef CFG_EEPROM_PAGE_WRITE_DELAY_MS
 				udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
@@ -534,7 +534,7 @@ int do_i2c_probe (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	int k, skip;
 #endif
 
-	printf("Valid chip addresses:");
+	puts ("Valid chip addresses:");
 	for(j = 0; j < 128; j++) {
 #if defined(CFG_I2C_NOPROBES)
 		skip = 0;
@@ -551,13 +551,13 @@ int do_i2c_probe (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 			printf(" %02X", j);
 		}
 	}
-	printf("\n");
+	putc ('\n');
 
 #if defined(CFG_I2C_NOPROBES)
 	puts ("Excluded chip addresses:");
 	for( k = 0; k < sizeof(i2c_no_probes); k++ )
 		printf(" %02X", i2c_no_probes[k] );
-	puts ("\n");
+	putc ('\n');
 #endif
 
 	return 0;
@@ -629,7 +629,7 @@ int do_i2c_loop(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	 */
 	while(1) {
 		if(i2c_read(chip, addr, alen, bytes, length) != 0) {
-			printf("Error reading the chip.\n");
+			puts ("Error reading the chip.\n");
 		}
 		udelay(delay);
 	}
@@ -666,7 +666,7 @@ int do_sdram  ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	chip = simple_strtoul(argv[1], NULL, 16);
 
 	if(i2c_read(chip, 0, 1, data, sizeof(data)) != 0) {
-		printf("No SDRAM Serial Presence Detect found.\n");
+		puts ("No SDRAM Serial Presence Detect found.\n");
 		return 1;
 	}
 
@@ -683,19 +683,19 @@ int do_sdram  ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 		(data[62] >> 4) & 0x0F, data[62] & 0x0F);
 	printf("Bytes used                   0x%02X\n", data[0]);
 	printf("Serial memory size           0x%02X\n", 1 << data[1]);
-	printf("Memory type                  ");
+	puts ("Memory type                  ");
 	switch(data[2]) {
-		case 2:  printf("EDO\n");	break;
-		case 4:  printf("SDRAM\n");	break;
-		default: printf("unknown\n");	break;
+		case 2:  puts ("EDO\n");	break;
+		case 4:  puts ("SDRAM\n");	break;
+		default: puts ("unknown\n");	break;
 	}
-	printf("Row address bits             ");
+	puts ("Row address bits             ");
 	if((data[3] & 0x00F0) == 0) {
 		printf("%d\n", data[3] & 0x0F);
 	} else {
 		printf("%d/%d\n", data[3] & 0x0F, (data[3] >> 4) & 0x0F);
 	}
-	printf("Column address bits          ");
+	puts ("Column address bits          ");
 	if((data[4] & 0x00F0) == 0) {
 		printf("%d\n", data[4] & 0x0F);
 	} else {
@@ -703,39 +703,39 @@ int do_sdram  ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	}
 	printf("Module rows                  %d\n", data[5]);
 	printf("Module data width            %d bits\n", (data[7] << 8) | data[6]);
-	printf("Interface signal levels      ");
+	puts ("Interface signal levels      ");
 	switch(data[8]) {
-		case 0:  printf("5.0v/TTL\n");	break;
-		case 1:  printf("LVTTL\n");	break;
-		case 2:  printf("HSTL 1.5\n");	break;
-		case 3:  printf("SSTL 3.3\n");	break;
-		case 4:  printf("SSTL 2.5\n");	break;
-		default: printf("unknown\n");	break;
+		case 0:  puts ("5.0v/TTL\n");	break;
+		case 1:  puts ("LVTTL\n");	break;
+		case 2:  puts ("HSTL 1.5\n");	break;
+		case 3:  puts ("SSTL 3.3\n");	break;
+		case 4:  puts ("SSTL 2.5\n");	break;
+		default: puts ("unknown\n");	break;
 	}
 	printf("SDRAM cycle time             %d.%d nS\n",
 		(data[9] >> 4) & 0x0F, data[9] & 0x0F);
 	printf("SDRAM access time            %d.%d nS\n",
 		(data[10] >> 4) & 0x0F, data[10] & 0x0F);
-	printf("EDC configuration            ");
+	puts ("EDC configuration            ");
 	switch(data[11]) {
-		case 0:  printf("None\n");	break;
-		case 1:  printf("Parity\n");	break;
-		case 2:  printf("ECC\n");	break;
-		default: printf("unknown\n");	break;
+		case 0:  puts ("None\n");	break;
+		case 1:  puts ("Parity\n");	break;
+		case 2:  puts ("ECC\n");	break;
+		default: puts ("unknown\n");	break;
 	}
 	if((data[12] & 0x80) == 0) {
-		printf("No self refresh, rate        ");
+		puts ("No self refresh, rate        ");
 	} else {
-		printf("Self refresh, rate           ");
+		puts ("Self refresh, rate           ");
 	}
 	switch(data[12] & 0x7F) {
-		case 0:  printf("15.625uS\n");	break;
-		case 1:  printf("3.9uS\n");	break;
-		case 2:  printf("7.8uS\n");	break;
-		case 3:  printf("31.3uS\n");	break;
-		case 4:  printf("62.5uS\n");	break;
-		case 5:  printf("125uS\n");	break;
-		default: printf("unknown\n");	break;
+		case 0:  puts ("15.625uS\n");	break;
+		case 1:  puts ("3.9uS\n");	break;
+		case 2:  puts ("7.8uS\n");	break;
+		case 3:  puts ("31.3uS\n");	break;
+		case 4:  puts ("62.5uS\n");	break;
+		case 5:  puts ("125uS\n");	break;
+		default: puts ("unknown\n");	break;
 	}
 	printf("SDRAM width (primary)        %d\n", data[13] & 0x7F);
 	if((data[13] & 0x80) != 0) {
@@ -752,65 +752,65 @@ int do_sdram  ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	}
 	printf("Min clock delay, back-to-back random column addresses %d\n",
 		data[15]);
-	printf("Burst length(s)             ");
-	if(data[16] & 0x80) printf(" Page");
-	if(data[16] & 0x08) printf(" 8");
-	if(data[16] & 0x04) printf(" 4");
-	if(data[16] & 0x02) printf(" 2");
-	if(data[16] & 0x01) printf(" 1");
-	printf("\n");
+	puts ("Burst length(s)             ");
+	if (data[16] & 0x80) puts (" Page");
+	if (data[16] & 0x08) puts (" 8");
+	if (data[16] & 0x04) puts (" 4");
+	if (data[16] & 0x02) puts (" 2");
+	if (data[16] & 0x01) puts (" 1");
+	putc ('\n');
 	printf("Number of banks              %d\n", data[17]);
-	printf("CAS latency(s)              ");
-	if(data[18] & 0x80) printf(" TBD");
-	if(data[18] & 0x40) printf(" 7");
-	if(data[18] & 0x20) printf(" 6");
-	if(data[18] & 0x10) printf(" 5");
-	if(data[18] & 0x08) printf(" 4");
-	if(data[18] & 0x04) printf(" 3");
-	if(data[18] & 0x02) printf(" 2");
-	if(data[18] & 0x01) printf(" 1");
-	printf("\n");
-	printf("CS latency(s)               ");
-	if(data[19] & 0x80) printf(" TBD");
-	if(data[19] & 0x40) printf(" 6");
-	if(data[19] & 0x20) printf(" 5");
-	if(data[19] & 0x10) printf(" 4");
-	if(data[19] & 0x08) printf(" 3");
-	if(data[19] & 0x04) printf(" 2");
-	if(data[19] & 0x02) printf(" 1");
-	if(data[19] & 0x01) printf(" 0");
-	printf("\n");
-	printf("WE latency(s)               ");
-	if(data[20] & 0x80) printf(" TBD");
-	if(data[20] & 0x40) printf(" 6");
-	if(data[20] & 0x20) printf(" 5");
-	if(data[20] & 0x10) printf(" 4");
-	if(data[20] & 0x08) printf(" 3");
-	if(data[20] & 0x04) printf(" 2");
-	if(data[20] & 0x02) printf(" 1");
-	if(data[20] & 0x01) printf(" 0");
-	printf("\n");
-	printf("Module attributes:\n");
-	if(!data[21])       printf("  (none)\n");
-	if(data[21] & 0x80) printf("  TBD (bit 7)\n");
-	if(data[21] & 0x40) printf("  Redundant row address\n");
-	if(data[21] & 0x20) printf("  Differential clock input\n");
-	if(data[21] & 0x10) printf("  Registerd DQMB inputs\n");
-	if(data[21] & 0x08) printf("  Buffered DQMB inputs\n");
-	if(data[21] & 0x04) printf("  On-card PLL\n");
-	if(data[21] & 0x02) printf("  Registered address/control lines\n");
-	if(data[21] & 0x01) printf("  Buffered address/control lines\n");
-	printf("Device attributes:\n");
-	if(data[22] & 0x80) printf("  TBD (bit 7)\n");
-	if(data[22] & 0x40) printf("  TBD (bit 6)\n");
-	if(data[22] & 0x20) printf("  Upper Vcc tolerance 5%%\n");
-	else                printf("  Upper Vcc tolerance 10%%\n");
-	if(data[22] & 0x10) printf("  Lower Vcc tolerance 5%%\n");
-	else                printf("  Lower Vcc tolerance 10%%\n");
-	if(data[22] & 0x08) printf("  Supports write1/read burst\n");
-	if(data[22] & 0x04) printf("  Supports precharge all\n");
-	if(data[22] & 0x02) printf("  Supports auto precharge\n");
-	if(data[22] & 0x01) printf("  Supports early RAS# precharge\n");
+	puts ("CAS latency(s)              ");
+	if (data[18] & 0x80) puts (" TBD");
+	if (data[18] & 0x40) puts (" 7");
+	if (data[18] & 0x20) puts (" 6");
+	if (data[18] & 0x10) puts (" 5");
+	if (data[18] & 0x08) puts (" 4");
+	if (data[18] & 0x04) puts (" 3");
+	if (data[18] & 0x02) puts (" 2");
+	if (data[18] & 0x01) puts (" 1");
+	putc ('\n');
+	puts ("CS latency(s)               ");
+	if (data[19] & 0x80) puts (" TBD");
+	if (data[19] & 0x40) puts (" 6");
+	if (data[19] & 0x20) puts (" 5");
+	if (data[19] & 0x10) puts (" 4");
+	if (data[19] & 0x08) puts (" 3");
+	if (data[19] & 0x04) puts (" 2");
+	if (data[19] & 0x02) puts (" 1");
+	if (data[19] & 0x01) puts (" 0");
+	putc ('\n');
+	puts ("WE latency(s)               ");
+	if (data[20] & 0x80) puts (" TBD");
+	if (data[20] & 0x40) puts (" 6");
+	if (data[20] & 0x20) puts (" 5");
+	if (data[20] & 0x10) puts (" 4");
+	if (data[20] & 0x08) puts (" 3");
+	if (data[20] & 0x04) puts (" 2");
+	if (data[20] & 0x02) puts (" 1");
+	if (data[20] & 0x01) puts (" 0");
+	putc ('\n');
+	puts ("Module attributes:\n");
+	if (!data[21])       puts ("  (none)\n");
+	if (data[21] & 0x80) puts ("  TBD (bit 7)\n");
+	if (data[21] & 0x40) puts ("  Redundant row address\n");
+	if (data[21] & 0x20) puts ("  Differential clock input\n");
+	if (data[21] & 0x10) puts ("  Registerd DQMB inputs\n");
+	if (data[21] & 0x08) puts ("  Buffered DQMB inputs\n");
+	if (data[21] & 0x04) puts ("  On-card PLL\n");
+	if (data[21] & 0x02) puts ("  Registered address/control lines\n");
+	if (data[21] & 0x01) puts ("  Buffered address/control lines\n");
+	puts ("Device attributes:\n");
+	if (data[22] & 0x80) puts ("  TBD (bit 7)\n");
+	if (data[22] & 0x40) puts ("  TBD (bit 6)\n");
+	if (data[22] & 0x20) puts ("  Upper Vcc tolerance 5%\n");
+	else                 puts ("  Upper Vcc tolerance 10%\n");
+	if (data[22] & 0x10) puts ("  Lower Vcc tolerance 5%\n");
+	else                 puts ("  Lower Vcc tolerance 10%\n");
+	if (data[22] & 0x08) puts ("  Supports write1/read burst\n");
+	if (data[22] & 0x04) puts ("  Supports precharge all\n");
+	if (data[22] & 0x02) puts ("  Supports auto precharge\n");
+	if (data[22] & 0x01) puts ("  Supports early RAS# precharge\n");
 	printf("SDRAM cycle time (2nd highest CAS latency)        %d.%d nS\n",
 		(data[23] >> 4) & 0x0F, data[23] & 0x0F);
 	printf("SDRAM access from clock (2nd highest CAS latency) %d.%d nS\n",
@@ -823,16 +823,16 @@ int do_sdram  ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	printf("Row active to row active min %d nS\n", data[28]);
 	printf("RAS to CAS delay min         %d nS\n", data[29]);
 	printf("Minimum RAS pulse width      %d nS\n", data[30]);
-	printf("Density of each row         ");
-	if(data[31] & 0x80) printf(" 512MByte");
-	if(data[31] & 0x40) printf(" 256MByte");
-	if(data[31] & 0x20) printf(" 128MByte");
-	if(data[31] & 0x10) printf(" 64MByte");
-	if(data[31] & 0x08) printf(" 32MByte");
-	if(data[31] & 0x04) printf(" 16MByte");
-	if(data[31] & 0x02) printf(" 8MByte");
-	if(data[31] & 0x01) printf(" 4MByte");
-	printf("\n");
+	puts ("Density of each row         ");
+	if (data[31] & 0x80) puts (" 512");
+	if (data[31] & 0x40) puts (" 256");
+	if (data[31] & 0x20) puts (" 128");
+	if (data[31] & 0x10) puts (" 64");
+	if (data[31] & 0x08) puts (" 32");
+	if (data[31] & 0x04) puts (" 16");
+	if (data[31] & 0x02) puts (" 8");
+	if (data[31] & 0x01) puts (" 4");
+	puts ("MByte\n");
 	printf("Command and Address setup    %c%d.%d nS\n",
 		(data[32] & 0x80) ? '-' : '+',
 		(data[32] >> 4) & 0x07, data[32] & 0x0F);
@@ -845,21 +845,21 @@ int do_sdram  ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	printf("Data signal input hold       %c%d.%d nS\n",
 		(data[35] & 0x80) ? '-' : '+',
 		(data[35] >> 4) & 0x07, data[35] & 0x0F);
-	printf("Manufacturer's JEDEC ID      ");
+	puts ("Manufacturer's JEDEC ID      ");
 	for(j = 64; j <= 71; j++)
 		printf("%02X ", data[j]);
-	printf("\n");
+	putc ('\n');
 	printf("Manufacturing Location       %02X\n", data[72]);
-	printf("Manufacturer's Part Number   ");
+	puts ("Manufacturer's Part Number   ");
 	for(j = 73; j <= 90; j++)
 		printf("%02X ", data[j]);
-	printf("\n");
+	putc ('\n');
 	printf("Revision Code                %02X %02X\n", data[91], data[92]);
 	printf("Manufacturing Date           %02X %02X\n", data[93], data[94]);
-	printf("Assembly Serial Number       ");
+	puts ("Assembly Serial Number       ");
 	for(j = 95; j <= 98; j++)
 		printf("%02X ", data[j]);
-	printf("\n");
+	putc ('\n');
 	printf("Speed rating                 PC%d\n",
 		data[126] == 0x66 ? 66 : data[126]);
 

common/cmd_ide.c

@@ -139,7 +139,7 @@ static  block_dev_desc_t ide_dev_desc[CFG_IDE_MAXDEVICE];
 /* ------------------------------------------------------------------------- */
 
 #ifdef CONFIG_IDE_LED
-#if !defined(CONFIG_KUP4K) && !defined(CONFIG_HMI10)
+#if !defined(CONFIG_KUP4K) &&  !defined(CONFIG_KUP4X) &&!defined(CONFIG_BMS2003)
 static void  ide_led   (uchar led, uchar status);
 #else
 extern void  ide_led   (uchar led, uchar status);
@@ -782,15 +782,17 @@ set_pcmcia_timing (int pmode)
 
 /* ------------------------------------------------------------------------- */
 
-#ifdef __PPC__
+#if defined(__PPC__) || defined(CONFIG_PXA_PCMCIA)
 static void __inline__
 ide_outb(int dev, int port, unsigned char val)
 {
-	PRINTF ("ide_outb (dev= %d, port= %d, val= 0x%02x) : @ 0x%08lx\n",
+	PRINTF ("ide_outb (dev= %d, port= 0x%x, val= 0x%02x) : @ 0x%08lx\n",
 		dev, port, val, (ATA_CURR_BASE(dev)+port));
 
 	/* Ensure I/O operations complete */
+#ifdef __PPC__
 	__asm__ volatile("eieio");
+#endif
 	*((uchar *)(ATA_CURR_BASE(dev)+port)) = val;
 }
 #else	/* ! __PPC__ */
@@ -802,15 +804,17 @@ ide_outb(int dev, int port, unsigned char val)
 #endif	/* __PPC__ */
 
 
-#ifdef __PPC__
+#if defined(__PPC__) || defined(CONFIG_PXA_PCMCIA)
 static unsigned char __inline__
 ide_inb(int dev, int port)
 {
 	uchar val;
 	/* Ensure I/O operations complete */
+#ifdef __PPC__
 	__asm__ volatile("eieio");
+#endif
 	val = *((uchar *)(ATA_CURR_BASE(dev)+port));
-	PRINTF ("ide_inb (dev= %d, port= %d) : @ 0x%08lx -> 0x%02x\n",
+	PRINTF ("ide_inb (dev= %d, port= 0x%x) : @ 0x%08lx -> 0x%02x\n",
 		dev, port, (ATA_CURR_BASE(dev)+port), val);
 	return (val);
 }
@@ -856,6 +860,8 @@ input_swap_data(int dev, ulong *sect_buf, int words)
 	volatile ushort	*pbuf = (ushort *)(ATA_CURR_BASE(dev)+ATA_DATA_REG);
 	ushort	*dbuf = (ushort *)sect_buf;
 
+	PRINTF("in input swap data base for read is %lx\n", (unsigned long) pbuf);
+
 	while (words--) {
 		*dbuf++ = ld_le16(pbuf);
 		*dbuf++ = ld_le16(pbuf);
@@ -878,7 +884,7 @@ input_swap_data(int dev, ulong *sect_buf, int words)
 #endif	/* __LITTLE_ENDIAN || CONFIG_AU1X00 */
 
 
-#ifdef __PPC__
+#if defined(__PPC__) || defined(CONFIG_PXA_PCMCIA)
 static void
 output_data(int dev, ulong *sect_buf, int words)
 {
@@ -889,9 +895,13 @@ output_data(int dev, ulong *sect_buf, int words)
 	pbuf = (ushort *)(ATA_CURR_BASE(dev)+ATA_DATA_REG);
 	dbuf = (ushort *)sect_buf;
 	while (words--) {
+#ifdef __PPC__
 		__asm__ volatile ("eieio");
+#endif
 		*pbuf = *dbuf++;
+#ifdef __PPC__
 		__asm__ volatile ("eieio");
+#endif
 		*pbuf = *dbuf++;
 	}
 #else	/* CONFIG_HMI10 */
@@ -922,7 +932,7 @@ output_data(int dev, ulong *sect_buf, int words)
 }
 #endif	/* __PPC__ */
 
-#ifdef __PPC__
+#if defined(__PPC__) || defined(CONFIG_PXA_PCMCIA)
 static void
 input_data(int dev, ulong *sect_buf, int words)
 {
@@ -932,10 +942,17 @@ input_data(int dev, ulong *sect_buf, int words)
 
 	pbuf = (ushort *)(ATA_CURR_BASE(dev)+ATA_DATA_REG);
 	dbuf = (ushort *)sect_buf;
+
+	PRINTF("in input data base for read is %lx\n", (unsigned long) pbuf);
+
 	while (words--) {
+#ifdef __PPC__
 		__asm__ volatile ("eieio");
+#endif
 		*dbuf++ = *pbuf;
+#ifdef __PPC__
 		__asm__ volatile ("eieio");
+#endif
 		*dbuf++ = *pbuf;
 	}
 #else	/* CONFIG_HMI10 */
@@ -1169,13 +1186,12 @@ static void ide_ident (block_dev_desc_t *dev_desc)
 
 #ifdef CONFIG_LBA48
 	if (iop->command_set_2 & 0x0400) { /* LBA 48 support */
-		dev_desc->lba48support = 1;
-		dev_desc->lba48 = (unsigned long long)iop->lba48_capacity[0] |
+		dev_desc->lba48 = 1;
+		dev_desc->lba = (unsigned long long)iop->lba48_capacity[0] |
 						  ((unsigned long long)iop->lba48_capacity[1] << 16) |
 						  ((unsigned long long)iop->lba48_capacity[2] << 32) |
 						  ((unsigned long long)iop->lba48_capacity[3] << 48);
 	} else {
-		dev_desc->lba48support = 0;
 		dev_desc->lba48 = 0;
 	}
 #endif /* CONFIG_LBA48 */
@@ -1410,27 +1426,31 @@ WR_OUT:
 /*
  * copy src to dest, skipping leading and trailing blanks and null
  * terminate the string
+ * "len" is the size of available memory including the terminating '\0'
  */
-static void ident_cpy (unsigned char *dest, unsigned char *src, unsigned int len)
+static void ident_cpy (unsigned char *dst, unsigned char *src, unsigned int len)
 {
-	int start,end;
+	unsigned char *end, *last;
 
-	start=0;
-	while (start<len) {
-		if (src[start]!=' ')
-			break;
-		start++;
+	last = dst;
+	end  = src + len - 1;
+
+	/* reserve space for '\0' */
+	if (len < 2)
+		goto OUT;
+
+	/* skip leading white space */
+	while ((*src) && (src<end) && (*src==' '))
+		++src;
+
+	/* copy string, omitting trailing white space */
+	while ((*src) && (src<end)) {
+		*dst++ = *src;
+		if (*src++ != ' ')
+			last = dst;
 	}
-	end=len-1;
-	while (end>start) {
-		if (src[end]!=' ')
-			break;
-		end--;
-	}
-	for ( ; start<=end; start++) {
-		*dest++=src[start];
-	}
-	*dest='\0';
+OUT:
+	*last = '\0';
 }
 
 /* ------------------------------------------------------------------------- */
@@ -1533,7 +1553,11 @@ static void ide_reset (void)
 
 /* ------------------------------------------------------------------------- */
 
-#if defined(CONFIG_IDE_LED) && !defined(CONFIG_AMIGAONEG3SE) && !defined(CONFIG_KUP4K) && !defined(CONFIG_HMI10)
+#if defined(CONFIG_IDE_LED) && \
+   !defined(CONFIG_AMIGAONEG3SE) && \
+   !defined(CONFIG_KUP4K) && \
+   !defined(CONFIG_KUP4X) && \
+   !defined(CONFIG_HMI10)
 
 static	uchar	led_buffer = 0;		/* Buffer for current LED status	*/
 
@@ -1568,7 +1592,7 @@ static void ide_led (uchar led, uchar status)
 #define AT_PRINTF(fmt,args...)
 #endif
 
-#ifdef __PPC__
+#if defined(__PPC__) || defined(CONFIG_PXA_PCMCIA)
 /* since ATAPI may use commands with not 4 bytes alligned length
  * we have our own transfer functions, 2 bytes alligned */
 static void
@@ -1580,8 +1604,13 @@ output_data_shorts(int dev, ushort *sect_buf, int shorts)
 
 	pbuf = (ushort *)(ATA_CURR_BASE(dev)+ATA_DATA_REG);
 	dbuf = (ushort *)sect_buf;
+
+	PRINTF("in output data shorts base for read is %lx\n", (unsigned long) pbuf);
+
 	while (shorts--) {
+#ifdef __PPC__
 		__asm__ volatile ("eieio");
+#endif
 		*pbuf = *dbuf++;
 	}
 #else	/* CONFIG_HMI10 */
@@ -1609,8 +1638,13 @@ input_data_shorts(int dev, ushort *sect_buf, int shorts)
 
 	pbuf = (ushort *)(ATA_CURR_BASE(dev)+ATA_DATA_REG);
 	dbuf = (ushort *)sect_buf;
+
+	PRINTF("in input data shorts base for read is %lx\n", (unsigned long) pbuf);
+
 	while (shorts--) {
+#ifdef __PPC__
 		__asm__ volatile ("eieio");
+#endif
 		*dbuf++ = *pbuf;
 	}
 #else	/* CONFIG_HMI10 */

common/cmd_immap.c

@@ -107,7 +107,7 @@ do_memcinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 #if defined(CONFIG_8xx)
 	printf (" MCR   = %08x\n", memctl->memc_mcr);
 #elif defined(CONFIG_8260)
-	printf ("\n");
+	putc ('\n');
 #endif
 	printf ("MAMR  = %08x MBMR  = %08x",
 		memctl->memc_mamr, memctl->memc_mbmr);
@@ -325,7 +325,7 @@ do_iopset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	iopin_t iopin;
 
 	if (argc != 5) {
-		printf ("iopset PORT PIN CMD VALUE\n");
+		puts ("iopset PORT PIN CMD VALUE\n");
 		return 1;
 	}
 	port = argv[1][0] - 'A';
@@ -529,7 +529,7 @@ do_i2cinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	printf ("I2CER = %02x I2CMR = %02x\n", i2c->i2c_i2cer, i2c->i2c_i2cmr);
 
 	if (iip == NULL)
-		printf ("i2c parameter ram not allocated\n");
+		puts ("i2c parameter ram not allocated\n");
 	else {
 		printf ("RBASE = %08x TBASE = %08x\n",
 			iip->iic_rbase, iip->iic_tbase);

common/cmd_jffs2.c

@@ -49,6 +49,8 @@ static int part_num=0;
 
 static struct part_info part;
 
+#ifndef CONFIG_JFFS2_NAND
+
 struct part_info*
 jffs2_part_info(int part_num)
 {
@@ -88,6 +90,33 @@ jffs2_part_info(int part_num)
 	}
 	return 0;
 }
+
+#else /* CONFIG_JFFS2_NAND */
+
+struct part_info*
+jffs2_part_info(int part_num)
+{
+	if(part_num==0){
+
+		if(part.usr_priv==(void*)1)
+			return ∂
+
+		memset(&part, 0, sizeof(part));
+
+		part.offset = CONFIG_JFFS2_NAND_OFF;
+		part.size = CONFIG_JFFS2_NAND_SIZE; /* the bigger size the slower jffs2 */
+
+#ifndef CONFIG_JFFS2_NAND_DEV
+#define CONFIG_JFFS2_NAND_DEV 0
+#endif
+		/* nand device with the JFFS2 parition plus 1 */
+		part.usr_priv = (void*)(CONFIG_JFFS2_NAND_DEV+1);
+		return ∂
+	}
+	return 0;
+}
+
+#endif /* CONFIG_JFFS2_NAND */
 #endif /* ifndef CFG_JFFS_CUSTOM_PART */
 
 int
@@ -98,7 +127,7 @@ do_jffs2_fsload(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
     char *fsname;
 
 	char *filename = "uImage";
-	ulong offset = CFG_LOAD_ADDR;
+	ulong offset = load_addr;
 	int size;
 	struct part_info *part;
 
@@ -107,6 +136,7 @@ do_jffs2_fsload(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	}
 	if (argc == 3) {
 		offset = simple_strtoul(argv[1], NULL, 16);
+		load_addr = offset;
 		filename = argv[2];
 	}
 
@@ -135,7 +165,7 @@ do_jffs2_fsload(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 		return !(size > 0);
 	}
-	printf("Active partition not valid\n");
+	puts ("Active partition not valid\n");
 	return 0;
 }
 
@@ -164,7 +194,7 @@ do_jffs2_ls(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 		return (ret == 1);
 	}
-	printf("Active partition not valid\n");
+	puts ("Active partition not valid\n");
 	return 0;
 }
 
@@ -192,7 +222,7 @@ do_jffs2_fsinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 		return (ret == 1);
 	}
-	printf("Active partition not valid\n");
+	puts ("Active partition not valid\n");
 	return 0;
 }
 
@@ -206,7 +236,7 @@ do_jffs2_chpart(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
    if (argc >= 2) {
 		tmp_part = simple_strtoul(argv[1], NULL, 16);
 	}else{
-		printf("Need partition number in argument list\n");
+		puts ("Need partition number in argument list\n");
 		return 0;
 
 	}

common/cmd_mem.c

@@ -178,16 +178,16 @@ int do_mem_md ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 #ifdef CONFIG_HAS_DATAFLASH
 		}
 #endif
-		printf("    ");
+		puts ("    ");
 		cp = linebuf;
 		for (i=0; i<linebytes; i++) {
 			if ((*cp < 0x20) || (*cp > 0x7e))
-				printf(".");
+				putc ('.');
 			else
 				printf("%c", *cp);
 			cp++;
 		}
-		printf("\n");
+		putc ('\n');
 		nbytes -= linebytes;
 		if (ctrlc()) {
 			rc = 1;
@@ -279,7 +279,7 @@ int do_mem_cmp (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 #ifdef CONFIG_HAS_DATAFLASH
 	if (addr_dataflash(addr1) | addr_dataflash(addr2)){
-		printf("Comparison with DataFlash space not supported.\n\r");
+		puts ("Comparison with DataFlash space not supported.\n\r");
 		return 0;
 	}
 #endif
@@ -368,7 +368,7 @@ int do_mem_cp ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	   ) {
 		int rc;
 
-		printf ("Copy to Flash... ");
+		puts ("Copy to Flash... ");
 
 		rc = flash_write ((uchar *)addr, dest, count*size);
 		if (rc != 0) {
@@ -384,13 +384,13 @@ int do_mem_cp ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	if (mmc2info(dest)) {
 		int rc;
 
-		printf ("Copy to MMC... ");
+		puts ("Copy to MMC... ");
 		switch (rc = mmc_write ((uchar *)addr, dest, count*size)) {
 		case 0:
-			printf ("\n");
+			putc ('\n');
 			return 1;
 		case -1:
-			printf("failed\n");
+			puts ("failed\n");
 			return 1;
 		default:
 			printf ("%s[%d] FIXME: rc=%d\n",__FILE__,__LINE__,rc);
@@ -403,13 +403,13 @@ int do_mem_cp ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	if (mmc2info(addr)) {
 		int rc;
 
-		printf ("Copy from MMC... ");
+		puts ("Copy from MMC... ");
 		switch (rc = mmc_read (addr, (uchar *)dest, count*size)) {
 		case 0:
-			printf ("\n");
+			putc ('\n');
 			return 1;
 		case -1:
-			printf("failed\n");
+			puts ("failed\n");
 			return 1;
 		default:
 			printf ("%s[%d] FIXME: rc=%d\n",__FILE__,__LINE__,rc);
@@ -425,7 +425,7 @@ int do_mem_cp ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	if (addr_dataflash(dest) && !addr_dataflash(addr)){
 		int rc;
 
-		printf ("Copy to DataFlash... ");
+		puts ("Copy to DataFlash... ");
 
 		rc = write_dataflash (dest, addr, count*size);
 
@@ -449,7 +449,7 @@ int do_mem_cp ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	}
 
 	if (addr_dataflash(addr) && addr_dataflash(dest)){
-		printf("Unsupported combination of source/destination.\n\r");
+		puts ("Unsupported combination of source/destination.\n\r");
 		return 1;
 	}
 #endif
@@ -828,7 +828,7 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 			val  += incr;
 		}
 
-		printf("Reading...");
+		puts ("Reading...");
 
 		for (addr=start,val=pattern; addr<end; addr++) {
 			readback = *addr;
@@ -902,7 +902,7 @@ mod_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char *argv[])
 
 #ifdef CONFIG_HAS_DATAFLASH
 	if (addr_dataflash(addr)){
-		printf("Can't modify DataFlash in place. Use cp instead.\n\r");
+		puts ("Can't modify DataFlash in place. Use cp instead.\n\r");
 		return 0;
 	}
 #endif
@@ -963,6 +963,8 @@ mod_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char *argv[])
 	return 0;
 }
 
+#ifndef CONFIG_CRC32_VERIFY
+
 int do_mem_crc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
 	ulong addr, length;
@@ -992,6 +994,62 @@ int do_mem_crc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	return 0;
 }
 
+#else	/* CONFIG_CRC32_VERIFY */
+
+int do_mem_crc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	ulong addr, length;
+	ulong crc;
+	ulong *ptr;
+	ulong vcrc;
+	int verify;
+	int ac;
+	char **av;
+
+	if (argc < 3) {
+  usage:
+		printf ("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+	}
+
+	av = argv + 1;
+	ac = argc - 1;
+	if (strcmp(*av, "-v") == 0) {
+		verify = 1;
+		av++;
+		ac--;
+		if (ac < 3)
+			goto usage;
+	} else
+		verify = 0;
+
+	addr = simple_strtoul(*av++, NULL, 16);
+	addr += base_address;
+	length = simple_strtoul(*av++, NULL, 16);
+
+	crc = crc32(0, (const uchar *) addr, length);
+
+	if (!verify) {
+		printf ("CRC32 for %08lx ... %08lx ==> %08lx\n",
+				addr, addr + length - 1, crc);
+		if (ac > 2) {
+			ptr = (ulong *) simple_strtoul (*av++, NULL, 16);
+			*ptr = crc;
+		}
+	} else {
+		vcrc = simple_strtoul(*av++, NULL, 16);
+		if (vcrc != crc) {
+			printf ("CRC32 for %08lx ... %08lx ==> %08lx != %08lx ** ERROR **\n",
+					addr, addr + length - 1, crc, vcrc);
+			return 1;
+		}
+	}
+
+	return 0;
+
+}
+#endif	/* CONFIG_CRC32_VERIFY */
+
 /**************************************************/
 #if (CONFIG_COMMANDS & CFG_CMD_MEMORY)
 U_BOOT_CMD(
@@ -1032,12 +1090,25 @@ U_BOOT_CMD(
 	"[.b, .w, .l] addr1 addr2 count\n    - compare memory\n"
 );
 
+#ifndef CONFIG_CRC32_VERIFY
+
 U_BOOT_CMD(
 	crc32,    4,    1,     do_mem_crc,
 	"crc32   - checksum calculation\n",
 	"address count [addr]\n    - compute CRC32 checksum [save at addr]\n"
 );
 
+#else	/* CONFIG_CRC32_VERIFY */
+
+U_BOOT_CMD(
+	crc32,    5,    1,     do_mem_crc,
+	"crc32   - checksum calculation\n",
+	"address count [addr]\n    - compute CRC32 checksum [save at addr]\n"
+	"-v address count crc\n    - verify crc of memory area\n"
+);
+
+#endif	/* CONFIG_CRC32_VERIFY */
+
 U_BOOT_CMD(
 	base,    2,    1,     do_mem_base,
 	"base    - print or set address offset\n",

common/cmd_mii.c

@@ -109,13 +109,13 @@ int do_mii (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 		}
 	} else if (op == 'r') {
 		if (miiphy_read (addr, reg, &data) != 0) {
-			printf ("Error reading from the PHY\n");
+			puts ("Error reading from the PHY\n");
 			rcode = 1;
 		}
 		printf ("%04X\n", data & 0x0000FFFF);
 	} else if (op == 'w') {
 		if (miiphy_write (addr, reg, data) != 0) {
-			printf ("Error writing to the PHY\n");
+			puts ("Error writing to the PHY\n");
 			rcode = 1;
 		}
 	} else {

common/cmd_nand.c

@@ -9,6 +9,7 @@
 #include <command.h>
 #include <malloc.h>
 #include <asm/io.h>
+#include <watchdog.h>
 
 #ifdef CONFIG_SHOW_BOOT_PROGRESS
 # include <status_led.h>
@@ -63,6 +64,7 @@ struct nand_oob_config {
 #define NANDRW_READ	0x01
 #define NANDRW_WRITE	0x00
 #define NANDRW_JFFS2	0x02
+#define NANDRW_JFFS2_SKIP	0x04
 
 /*
  * Function Prototypes
@@ -207,6 +209,11 @@ int do_nand (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 		}
 		else if (cmdtail && !strncmp(cmdtail, ".jffs2", 2))
 			cmd |= NANDRW_JFFS2;	/* skip bad blocks */
+		else if (cmdtail && !strncmp(cmdtail, ".jffs2s", 2)) {
+			cmd |= NANDRW_JFFS2;	/* skip bad blocks (on read too) */
+			if (cmd & NANDRW_READ)
+				cmd |= NANDRW_JFFS2_SKIP;	/* skip bad blocks (on read too) */
+		}
 #ifdef SXNI855T
 		/* need ".e" same as ".j" for compatibility with older units */
 		else if (cmdtail && !strcmp(cmdtail, ".e"))
@@ -225,7 +232,7 @@ int do_nand (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 			     &total, (u_char*)addr);
 
 		printf (" %d bytes %s: %s\n", total,
-			(cmd & NANDRW_READ) ? "read" : "write",
+			(cmd & NANDRW_READ) ? "read" : "written",
 			ret ? "ERROR" : "OK");
 
 		return ret;
@@ -258,7 +265,7 @@ U_BOOT_CMD(
 	"nand    - NAND sub-system\n",
 	"info  - show available NAND devices\n"
 	"nand device [dev] - show or set current device\n"
-	"nand read[.jffs2]  addr off size\n"
+	"nand read[.jffs2[s]]  addr off size\n"
 	"nand write[.jffs2] addr off size - read/write `size' bytes starting\n"
 	"    at offset `off' to/from memory address `addr'\n"
 	"nand erase [clean] [off size] - erase `size' bytes from\n"
@@ -420,6 +427,7 @@ static void nand_print_bad(struct nand_chip* nand)
  *	1: NANDRW_READ			read, fail on bad block
  *	2: NANDRW_WRITE | NANDRW_JFFS2	write, skip bad blocks
  *	3: NANDRW_READ | NANDRW_JFFS2	read, data all 0xff for bad blocks
+ *      7: NANDRW_READ | NANDRW_JFFS2 | NANDRW_JFFS2_SKIP read, skip bad blocks
  */
 static int nand_rw (struct nand_chip* nand, int cmd,
 	    size_t start, size_t len,
@@ -450,6 +458,10 @@ static int nand_rw (struct nand_chip* nand, int cmd,
 					}
 					continue;
 				}
+				else if (cmd == (NANDRW_READ | NANDRW_JFFS2 | NANDRW_JFFS2_SKIP)) {
+					start += erasesize;
+					continue;
+				}
 				else if (cmd == (NANDRW_WRITE | NANDRW_JFFS2)) {
 					/* skip bad block */
 					start += erasesize;
@@ -1657,4 +1669,17 @@ static int nand_correct_data (u_char *dat, u_char *read_ecc, u_char *calc_ecc)
 }
 
 #endif
+
+#ifdef CONFIG_JFFS2_NAND
+
+int read_jffs2_nand(size_t start, size_t len,
+		    size_t * retlen, u_char * buf, int nanddev)
+{
+	return nand_rw(nand_dev_desc + nanddev, NANDRW_READ | NANDRW_JFFS2,
+		       start, len, retlen, buf);
+}
+
+#endif /* CONFIG_JFFS2_NAND */
+
+
 #endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */

common/cmd_net.c

@@ -94,52 +94,50 @@ U_BOOT_CMD(
 );
 #endif	/* CFG_CMD_NFS */
 
-static void netboot_update_env(void)
+static void netboot_update_env (void)
 {
-    char tmp[16] ;
+	char tmp[22];
 
-    if (NetOurGatewayIP) {
-	ip_to_string (NetOurGatewayIP, tmp);
-	setenv("gatewayip", tmp);
-    }
+	if (NetOurGatewayIP) {
+		ip_to_string (NetOurGatewayIP, tmp);
+		setenv ("gatewayip", tmp);
+	}
 
-    if (NetOurSubnetMask) {
-	ip_to_string (NetOurSubnetMask, tmp);
-	setenv("netmask", tmp);
-    }
+	if (NetOurSubnetMask) {
+		ip_to_string (NetOurSubnetMask, tmp);
+		setenv ("netmask", tmp);
+	}
 
-    if (NetOurHostName[0])
-	setenv("hostname", NetOurHostName);
+	if (NetOurHostName[0])
+		setenv ("hostname", NetOurHostName);
 
-    if (NetOurRootPath[0])
-	setenv("rootpath", NetOurRootPath);
+	if (NetOurRootPath[0])
+		setenv ("rootpath", NetOurRootPath);
 
-    if (NetOurIP) {
-	ip_to_string (NetOurIP, tmp);
-	setenv("ipaddr", tmp);
-    }
+	if (NetOurIP) {
+		ip_to_string (NetOurIP, tmp);
+		setenv ("ipaddr", tmp);
+	}
 
-    if (NetServerIP) {
-	ip_to_string (NetServerIP, tmp);
-	setenv("serverip", tmp);
-    }
-
-    if (NetOurDNSIP) {
-	ip_to_string (NetOurDNSIP, tmp);
-	setenv("dnsip", tmp);
-    }
+	if (NetServerIP) {
+		ip_to_string (NetServerIP, tmp);
+		setenv ("serverip", tmp);
+	}
 
+	if (NetOurDNSIP) {
+		ip_to_string (NetOurDNSIP, tmp);
+		setenv ("dnsip", tmp);
+	}
 #if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_DNS2)
-    if (NetOurDNS2IP) {
-	    ip_to_string (NetOurDNS2IP, tmp);
-	    setenv("dnsip2", tmp);
-    }
+	if (NetOurDNS2IP) {
+		ip_to_string (NetOurDNS2IP, tmp);
+		setenv ("dnsip2", tmp);
+	}
 #endif
-
-    if (NetOurNISDomain[0])
-	setenv("domain", NetOurNISDomain);
-
+	if (NetOurNISDomain[0])
+		setenv ("domain", NetOurNISDomain);
 }
+
 static int
 netboot_common (int proto, cmd_tbl_t *cmdtp, int argc, char *argv[])
 {
@@ -238,4 +236,47 @@ U_BOOT_CMD(
 );
 #endif	/* CFG_CMD_PING */
 
+#if (CONFIG_COMMANDS & CFG_CMD_CDP)
+
+static void cdp_update_env(void)
+{
+	char tmp[16];
+
+	if (CDPApplianceVLAN != htons(-1)) {
+		printf("CDP offered appliance VLAN %d\n", ntohs(CDPApplianceVLAN));
+		VLAN_to_string(CDPApplianceVLAN, tmp);
+		setenv("vlan", tmp);
+		NetOurVLAN = CDPApplianceVLAN;
+	}
+
+	if (CDPNativeVLAN != htons(-1)) {
+		printf("CDP offered native VLAN %d\n", ntohs(CDPNativeVLAN));
+		VLAN_to_string(CDPNativeVLAN, tmp);
+		setenv("nvlan", tmp);
+		NetOurNativeVLAN = CDPNativeVLAN;
+	}
+
+}
+
+int do_cdp (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	int r;
+
+	r = NetLoop(CDP);
+	if (r < 0) {
+		printf("cdp failed; perhaps not a CISCO switch?\n");
+		return 1;
+	}
+
+	cdp_update_env();
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	cdp,	1,	1,	do_cdp,
+	"cdp     - Perform CDP network configuration\n",
+);
+#endif	/* CFG_CMD_CDP */
+
 #endif	/* CFG_CMD_NET */

common/cmd_pcmcia.c

@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000-2002
+ * (C) Copyright 2000-2004
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -63,6 +63,9 @@
 #if defined(CONFIG_LWMON)
 #include <i2c.h>
 #endif
+#ifdef CONFIG_PXA_PCMCIA
+#include <asm/arch/pxa-regs.h>
+#endif
 
 #if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) || \
     ((CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD))
@@ -86,32 +89,35 @@ static int  hardware_disable(int slot);
 static int  hardware_enable (int slot);
 static int  voltage_set(int slot, int vcc, int vpp);
 
-#ifndef	CONFIG_I82365
+#if (! defined(CONFIG_I82365)) && (! defined(CONFIG_PXA_PCMCIA))
 static u_int m8xx_get_graycode(u_int size);
-#endif	/* CONFIG_I82365 */
+#endif	/* !CONFIG_I82365, !CONFIG_PXA_PCMCIA */
 #if 0
 static u_int m8xx_get_speed(u_int ns, u_int is_io);
 #endif
 
 /* -------------------------------------------------------------------- */
 
+#ifndef CONFIG_PXA_PCMCIA
+
 /* look up table for pgcrx registers */
 
 static u_int *pcmcia_pgcrx[2] = {
 	&((immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pgcra,
 	&((immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pgcrb,
 };
-
 #define PCMCIA_PGCRX(slot)	(*pcmcia_pgcrx[slot])
 
+#endif	/* CONFIG_PXA_PCMCIA */
+
 #endif /* CONFIG_I82365 */
 
-#ifdef CONFIG_IDE_8xx_PCCARD
+#if defined(CONFIG_IDE_8xx_PCCARD)  || defined(CONFIG_PXA_PCMCIA)
 static void print_funcid (int func);
 static void print_fixed  (volatile uchar *p);
 static int  identify     (volatile uchar *p);
 static int  check_ide_device (int slot);
-#endif	/* CONFIG_IDE_8xx_PCCARD */
+#endif	/* CONFIG_IDE_8xx_PCCARD, CONFIG_PXA_PCMCIA */
 
 const char *indent = "\t   ";
 
@@ -151,8 +157,7 @@ int pcmcia_on (void)
 
 	rc = i82365_init();
 
-	if (rc == 0)
-	{
+	if (rc == 0) {
 		rc = check_ide_device(0);
 	}
 
@@ -160,6 +165,8 @@ int pcmcia_on (void)
 }
 #else
 
+#ifndef CONFIG_PXA_PCMCIA
+
 #ifdef CONFIG_HMI10
 # define  HMI10_FRAM_TIMING	(PCMCIA_SHT(2) | PCMCIA_SST(2) | PCMCIA_SL(4))
 #endif
@@ -280,8 +287,108 @@ int pcmcia_on (void)
 	}
 	return (rc);
 }
+
+#endif /* CONFIG_PXA_PCMCIA */
+
 #endif /* CONFIG_I82365 */
 
+#ifdef CONFIG_PXA_PCMCIA
+
+static int hardware_enable (int slot)
+{
+	return 0;	/* No hardware to enable */
+}
+
+static int hardware_disable(int slot)
+{
+	return 0;	/* No hardware to disable */
+}
+
+static int voltage_set(int slot, int vcc, int vpp)
+{
+	return 0;
+}
+
+void msWait(unsigned msVal)
+{
+	udelay(msVal*1000);
+}
+
+int pcmcia_on (void)
+{
+	unsigned int reg_arr[] = {
+		0x48000028, CFG_MCMEM0_VAL,
+		0x4800002c, CFG_MCMEM1_VAL,
+		0x48000030, CFG_MCATT0_VAL,
+		0x48000034, CFG_MCATT1_VAL,
+		0x48000038, CFG_MCIO0_VAL,
+		0x4800003c, CFG_MCIO1_VAL,
+
+		0, 0
+	};
+	int i, rc;
+
+#ifdef CONFIG_EXADRON1
+	int cardDetect;
+	volatile unsigned int *v_pBCRReg =
+		(volatile unsigned int *) 0x08000000;
+#endif
+
+	debug ("%s\n", __FUNCTION__);
+
+	i = 0;
+	while (reg_arr[i])
+		*((volatile unsigned int *) reg_arr[i++]) |= reg_arr[i++];
+	udelay (1000);
+
+	debug ("%s: programmed mem controller \n", __FUNCTION__);
+
+#ifdef CONFIG_EXADRON1
+
+/*define useful BCR masks */
+#define BCR_CF_INIT_VAL  		    0x00007230
+#define BCR_CF_PWRON_BUSOFF_RESETOFF_VAL    0x00007231
+#define BCR_CF_PWRON_BUSOFF_RESETON_VAL     0x00007233
+#define BCR_CF_PWRON_BUSON_RESETON_VAL      0x00007213
+#define BCR_CF_PWRON_BUSON_RESETOFF_VAL     0x00007211
+
+	/* we see from the GPIO bit if the card is present */
+	cardDetect = !(GPLR0 & GPIO_bit (14));
+
+	if (cardDetect) {
+		printf ("No PCMCIA card found!\n");
+	}
+
+	/* reset the card via the BCR line */
+	*v_pBCRReg = (unsigned) BCR_CF_INIT_VAL;
+	msWait (500);
+
+	*v_pBCRReg = (unsigned) BCR_CF_PWRON_BUSOFF_RESETOFF_VAL;
+	msWait (500);
+
+	*v_pBCRReg = (unsigned) BCR_CF_PWRON_BUSOFF_RESETON_VAL;
+	msWait (500);
+
+	*v_pBCRReg = (unsigned) BCR_CF_PWRON_BUSON_RESETON_VAL;
+	msWait (500);
+
+	*v_pBCRReg = (unsigned) BCR_CF_PWRON_BUSON_RESETOFF_VAL;
+	msWait (1500);
+
+	/* enable address bus */
+	GPCR1 = 0x01;
+	/* and the first CF slot */
+	MECR = 0x00000002;
+
+#endif /* EXADRON 1 */
+
+	rc = check_ide_device (0);	/* use just slot 0 */
+
+	return rc;
+}
+
+#endif /* CONFIG_PXA_PCMCIA */
+
 /* -------------------------------------------------------------------- */
 
 #if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
@@ -296,6 +403,9 @@ static int pcmcia_off (void)
 	return 0;
 }
 #else
+
+#ifndef CONFIG_PXA_PCMCIA
+
 static int pcmcia_off (void)
 {
 	int i;
@@ -327,13 +437,23 @@ static int pcmcia_off (void)
 	hardware_disable(_slot_);
 	return 0;
 }
+
+#endif /* CONFIG_PXA_PCMCIA */
+
 #endif /* CONFIG_I82365 */
 
+#ifdef CONFIG_PXA_PCMCIA
+static int pcmcia_off (void)
+{
+	return 0;
+}
+#endif
+
 #endif	/* CFG_CMD_PCMCIA */
 
 /* -------------------------------------------------------------------- */
 
-#ifdef CONFIG_IDE_8xx_PCCARD
+#if defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_PXA_PCMCIA)
 
 #define	MAX_TUPEL_SZ	512
 #define MAX_FEATURES	4
@@ -2125,11 +2245,11 @@ done:
 #endif	/* R360MPI */
 
 /* -------------------------------------------------------------------- */
-/* KUP4K Board								*/
+/* KUP4K and KUP4X Boards								*/
 /* -------------------------------------------------------------------- */
-#if defined(CONFIG_KUP4K)
+#if defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X)
 
-#define PCMCIA_BOARD_MSG "KUP4K"
+#define PCMCIA_BOARD_MSG "KUP"
 
 #define KUP4K_PCMCIA_B_3V3 (0x00020000)
 
@@ -2337,7 +2457,7 @@ static int voltage_set(int slot, int vcc, int vpp)
 	return (0);
 }
 
-#endif	/* KUP4K */
+#endif	/* KUP4K || KUP4X */
 
 
 /* -------------------------------------------------------------------- */
@@ -2370,7 +2490,7 @@ static const u_int m8xx_size_to_gray[M8XX_SIZES_NO] =
 
 /* -------------------------------------------------------------------- */
 
-#ifndef	CONFIG_I82365
+#if ( ! defined(CONFIG_I82365) && ! defined(CONFIG_PXA_PCMCIA) )
 
 static u_int m8xx_get_graycode(u_int size)
 {
@@ -2444,7 +2564,7 @@ static u_int m8xx_get_speed(u_int ns, u_int is_io)
 
 /* -------------------------------------------------------------------- */
 
-#ifdef CONFIG_IDE_8xx_PCCARD
+#if defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_PXA_PCMCIA)
 static void print_funcid (int func)
 {
 	puts (indent);
@@ -2486,7 +2606,7 @@ static void print_funcid (int func)
 
 /* -------------------------------------------------------------------- */
 
-#ifdef CONFIG_IDE_8xx_PCCARD
+#if defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_PXA_PCMCIA)
 static void print_fixed (volatile uchar *p)
 {
 	if (p == NULL)
@@ -2544,7 +2664,7 @@ static void print_fixed (volatile uchar *p)
 
 /* -------------------------------------------------------------------- */
 
-#ifdef CONFIG_IDE_8xx_PCCARD
+#if defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_PXA_PCMCIA)
 
 #define MAX_IDENT_CHARS		64
 #define	MAX_IDENT_FIELDS	4
@@ -2606,6 +2726,370 @@ static int identify  (volatile uchar *p)
 }
 #endif	/* CONFIG_IDE_8xx_PCCARD */
 
+/* -------------------------------------------------------------------- */
+/* NETTA board by Intracom S.A.						*/
+/* -------------------------------------------------------------------- */
+
+#if defined(CONFIG_NETTA)
+
+/* some sane bit macros */
+#define _BD(_b)				(1U << (31-(_b)))
+#define _BDR(_l, _h)			(((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1))
+
+#define _BW(_b)				(1U << (15-(_b)))
+#define _BWR(_l, _h)			(((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1))
+
+#define _BB(_b)				(1U << (7-(_b)))
+#define _BBR(_l, _h)			(((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1))
+
+#define _B(_b)				_BD(_b)
+#define _BR(_l, _h)			_BDR(_l, _h)
+
+#define PCMCIA_BOARD_MSG "NETTA"
+
+static const unsigned short vppd_masks[2] = { _BW(14), _BW(15) };
+
+static void cfg_vppd(int no)
+{
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	unsigned short mask;
+
+	if ((unsigned int)no >= sizeof(vppd_masks)/sizeof(vppd_masks[0]))
+		return;
+
+	mask = vppd_masks[no];
+
+	immap->im_ioport.iop_papar &= ~mask;
+	immap->im_ioport.iop_paodr &= ~mask;
+	immap->im_ioport.iop_padir |=  mask;
+}
+
+static void set_vppd(int no, int what)
+{
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	unsigned short mask;
+
+	if ((unsigned int)no >= sizeof(vppd_masks)/sizeof(vppd_masks[0]))
+		return;
+
+	mask = vppd_masks[no];
+
+	if (what)
+		immap->im_ioport.iop_padat |= mask;
+	else
+		immap->im_ioport.iop_padat &= ~mask;
+}
+
+static const unsigned short vccd_masks[2] = { _BW(10), _BW(6) };
+
+static void cfg_vccd(int no)
+{
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	unsigned short mask;
+
+	if ((unsigned int)no >= sizeof(vccd_masks)/sizeof(vccd_masks[0]))
+		return;
+
+	mask = vccd_masks[no];
+
+	immap->im_ioport.iop_papar &= ~mask;
+	immap->im_ioport.iop_paodr &= ~mask;
+	immap->im_ioport.iop_padir |=  mask;
+}
+
+static void set_vccd(int no, int what)
+{
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	unsigned short mask;
+
+	if ((unsigned int)no >= sizeof(vccd_masks)/sizeof(vccd_masks[0]))
+		return;
+
+	mask = vccd_masks[no];
+
+	if (what)
+		immap->im_ioport.iop_padat |= mask;
+	else
+		immap->im_ioport.iop_padat &= ~mask;
+}
+
+static const unsigned short oc_mask = _BW(8);
+
+static void cfg_oc(void)
+{
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	unsigned short mask = oc_mask;
+
+	immap->im_ioport.iop_pcdir &= ~mask;
+	immap->im_ioport.iop_pcso  &= ~mask;
+	immap->im_ioport.iop_pcint &= ~mask;
+	immap->im_ioport.iop_pcpar &= ~mask;
+}
+
+static int get_oc(void)
+{
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	unsigned short mask = oc_mask;
+	int what;
+
+	what = !!(immap->im_ioport.iop_pcdat & mask);;
+	return what;
+}
+
+static const unsigned short shdn_mask = _BW(12);
+
+static void cfg_shdn(void)
+{
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	unsigned short mask;
+
+	mask = shdn_mask;
+
+	immap->im_ioport.iop_papar &= ~mask;
+	immap->im_ioport.iop_paodr &= ~mask;
+	immap->im_ioport.iop_padir |=  mask;
+}
+
+static void set_shdn(int what)
+{
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	unsigned short mask;
+
+	mask = shdn_mask;
+
+	if (what)
+		immap->im_ioport.iop_padat |= mask;
+	else
+		immap->im_ioport.iop_padat &= ~mask;
+}
+
+static void cfg_ports (void);
+
+static int hardware_enable(int slot)
+{
+	volatile immap_t	*immap;
+	volatile cpm8xx_t	*cp;
+	volatile pcmconf8xx_t	*pcmp;
+	volatile sysconf8xx_t	*sysp;
+	uint reg, pipr, mask;
+	int i;
+
+	debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
+
+	udelay(10000);
+
+	immap = (immap_t *)CFG_IMMR;
+	sysp  = (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf));
+	pcmp  = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
+	cp    = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
+
+	/* Configure Ports for TPS2211A PC-Card Power-Interface Switch */
+	cfg_ports ();
+
+	/* clear interrupt state, and disable interrupts */
+	pcmp->pcmc_pscr =  PCMCIA_MASK(_slot_);
+	pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_);
+
+	/*
+	 * Disable interrupts, DMA, and PCMCIA buffers
+	 * (isolate the interface) and assert RESET signal
+	 */
+	debug ("Disable PCMCIA buffers and assert RESET\n");
+	reg  = 0;
+	reg |= __MY_PCMCIA_GCRX_CXRESET;	/* active high */
+	reg |= __MY_PCMCIA_GCRX_CXOE;		/* active low  */
+	PCMCIA_PGCRX(_slot_) = reg;
+
+	udelay(500);
+
+	/*
+	 * Make sure there is a card in the slot, then configure the interface.
+	 */
+	udelay(10000);
+	debug ("[%d] %s: PIPR(%p)=0x%x\n",
+		__LINE__,__FUNCTION__,
+		&(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
+	if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
+		printf ("   No Card found\n");
+		return (1);
+	}
+
+	/*
+	 * Power On: Set VAVCC to 3.3V or 5V, set VAVPP to Hi-Z
+	 */
+	mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot);
+	pipr = pcmp->pcmc_pipr;
+	debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n",
+		pipr,
+		(reg&PCMCIA_VS1(slot))?"n":"ff",
+		(reg&PCMCIA_VS2(slot))?"n":"ff");
+
+	if ((pipr & mask) == mask) {
+		set_vppd(0, 1); set_vppd(1, 1); 		/* VAVPP => Hi-Z */
+		set_vccd(0, 0); set_vccd(1, 1); 		/* 5V on, 3V off */
+		puts (" 5.0V card found: ");
+	} else {
+		set_vppd(0, 1); set_vppd(1, 1); 		/* VAVPP => Hi-Z */
+		set_vccd(0, 1); set_vccd(1, 0); 		/* 5V off, 3V on */
+		puts (" 3.3V card found: ");
+	}
+
+	/*  Wait 500 ms; use this to check for over-current */
+	for (i=0; i<5000; ++i) {
+		if (!get_oc()) {
+			printf ("   *** Overcurrent - Safety shutdown ***\n");
+			set_vccd(0, 0); set_vccd(1, 0); 		/* VAVPP => Hi-Z */
+			return (1);
+		}
+		udelay (100);
+	}
+
+	debug ("Enable PCMCIA buffers and stop RESET\n");
+	reg  =  PCMCIA_PGCRX(_slot_);
+	reg &= ~__MY_PCMCIA_GCRX_CXRESET;	/* active high */
+	reg &= ~__MY_PCMCIA_GCRX_CXOE;		/* active low  */
+	PCMCIA_PGCRX(_slot_) = reg;
+
+	udelay(250000);	/* some cards need >150 ms to come up :-( */
+
+	debug ("# hardware_enable done\n");
+
+	return (0);
+}
+
+
+#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
+static int hardware_disable(int slot)
+{
+	volatile immap_t	*immap;
+	volatile pcmconf8xx_t	*pcmp;
+	u_long reg;
+
+	debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
+
+	immap = (immap_t *)CFG_IMMR;
+	pcmp  = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
+
+	/* Configure PCMCIA General Control Register */
+	debug ("Disable PCMCIA buffers and assert RESET\n");
+	reg  = 0;
+	reg |= __MY_PCMCIA_GCRX_CXRESET;	/* active high */
+	reg |= __MY_PCMCIA_GCRX_CXOE;		/* active low  */
+	PCMCIA_PGCRX(_slot_) = reg;
+
+	/* All voltages off / Hi-Z */
+			set_vppd(0, 1); set_vppd(1, 1);
+	set_vccd(0, 1); set_vccd(1, 1);
+
+	udelay(10000);
+
+	return (0);
+}
+#endif	/* CFG_CMD_PCMCIA */
+
+
+static int voltage_set(int slot, int vcc, int vpp)
+{
+	volatile immap_t	*immap;
+	volatile cpm8xx_t	*cp;
+	volatile pcmconf8xx_t	*pcmp;
+	u_long reg;
+	ushort sreg;
+
+	debug ("voltage_set: "
+		PCMCIA_BOARD_MSG
+		" Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
+		'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
+
+	immap = (immap_t *)CFG_IMMR;
+	cp    = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
+	pcmp  = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
+	/*
+	 * Disable PCMCIA buffers (isolate the interface)
+	 * and assert RESET signal
+	 */
+	debug ("Disable PCMCIA buffers and assert RESET\n");
+	reg  = PCMCIA_PGCRX(_slot_);
+	reg |= __MY_PCMCIA_GCRX_CXRESET;	/* active high */
+	reg |= __MY_PCMCIA_GCRX_CXOE;		/* active low  */
+	PCMCIA_PGCRX(_slot_) = reg;
+	udelay(500);
+
+	/*
+	 * Configure Port C pins for
+	 * 5 Volts Enable and 3 Volts enable,
+	 * Turn all power pins to Hi-Z
+	 */
+	debug ("PCMCIA power OFF\n");
+	cfg_ports ();	/* Enables switch, but all in Hi-Z */
+
+	sreg  = immap->im_ioport.iop_pcdat;
+	set_vppd(0, 1); set_vppd(1, 1);
+
+	switch(vcc) {
+	case  0:
+		break;	/* Switch off		*/
+
+	case 33:
+		set_vccd(0, 1); set_vccd(1, 0);
+		break;
+
+	case 50:
+		set_vccd(0, 0); set_vccd(1, 1);
+		break;
+
+	default:
+		goto done;
+	}
+
+	/* Checking supported voltages */
+
+	debug ("PIPR: 0x%x --> %s\n",
+		pcmp->pcmc_pipr,
+		(pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V");
+
+done:
+	debug ("Enable PCMCIA buffers and stop RESET\n");
+	reg  =  PCMCIA_PGCRX(_slot_);
+	reg &= ~__MY_PCMCIA_GCRX_CXRESET;	/* active high */
+	reg &= ~__MY_PCMCIA_GCRX_CXOE;		/* active low  */
+	PCMCIA_PGCRX(_slot_) = reg;
+	udelay(500);
+
+	debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n",
+		slot+'A');
+	return (0);
+}
+
+static void cfg_ports (void)
+{
+	volatile immap_t	*immap;
+	volatile cpm8xx_t	*cp;
+
+	immap = (immap_t *)CFG_IMMR;
+	cp    = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
+
+
+	cfg_vppd(0); cfg_vppd(1);	/* VPPD0,VPPD1 VAVPP => Hi-Z */
+	cfg_vccd(0); cfg_vccd(1);	/* 3V and 5V off */
+	cfg_shdn();
+	cfg_oc();
+
+	/*
+	 * Configure Port A for TPS2211 PC-Card Power-Interface Switch
+	 *
+	 * Switch off all voltages, assert shutdown
+	 */
+	set_vppd(0, 1); set_vppd(1, 1);
+	set_vccd(0, 0); set_vccd(1, 0);
+	set_shdn(1);
+
+	udelay(100000);
+}
+
+#endif	/* NETTA */
+
+
 /* -------------------------------------------------------------------- */
 
 #endif /* CFG_CMD_PCMCIA || (CFG_CMD_IDE && CONFIG_IDE_8xx_PCCARD) */

common/cmd_reginfo.c

@@ -44,9 +44,9 @@ int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	 * other useful registers
 	 */
 
-	printf("\nSystem Configuration registers\n");
+	printf ("\nSystem Configuration registers\n"
 
-	printf("\tIMMR\t0x%08X\n", get_immr(0));
+		"\tIMMR\t0x%08X\n", get_immr(0));
 
 	printf("\tSIUMCR\t0x%08X", sysconf->sc_siumcr);
 	printf("\tSYPCR\t0x%08X\n",sysconf->sc_sypcr);
@@ -61,9 +61,9 @@ int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	printf("\tTESR\t0x%08X\tSDCR\t0x%08X\n",
 		sysconf->sc_tesr, sysconf->sc_sdcr);
 
-	printf("Memory Controller Registers\n");
+	printf ("Memory Controller Registers\n"
 
-	printf("\tBR0\t0x%08X\tOR0\t0x%08X \n", memctl->memc_br0, memctl->memc_or0);
+		"\tBR0\t0x%08X\tOR0\t0x%08X \n", memctl->memc_br0, memctl->memc_or0);
 	printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", memctl->memc_br1, memctl->memc_or1);
 	printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", memctl->memc_br2, memctl->memc_or2);
 	printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", memctl->memc_br3, memctl->memc_or3);
@@ -71,16 +71,15 @@ int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	printf("\tBR5\t0x%08X\tOR5\t0x%08X \n", memctl->memc_br5, memctl->memc_or5);
 	printf("\tBR6\t0x%08X\tOR6\t0x%08X \n", memctl->memc_br6, memctl->memc_or6);
 	printf("\tBR7\t0x%08X\tOR7\t0x%08X \n", memctl->memc_br7, memctl->memc_or7);
-	printf("\n");
-
-	printf("\tmamr\t0x%08X\tmbmr\t0x%08X \n",
+	printf ("\n"
+		"\tmamr\t0x%08X\tmbmr\t0x%08X \n",
 		memctl->memc_mamr, memctl->memc_mbmr );
 	printf("\tmstat\t0x%08X\tmptpr\t0x%08X \n",
 		memctl->memc_mstat, memctl->memc_mptpr );
 	printf("\tmdr\t0x%08X \n", memctl->memc_mdr);
 
-	printf("\nSystem Integration Timers\n");
-	printf("\tTBSCR\t0x%08X\tRTCSC\t0x%08X \n",
+	printf ("\nSystem Integration Timers\n"
+		"\tTBSCR\t0x%08X\tRTCSC\t0x%08X \n",
 		timers->sit_tbscr, timers->sit_rtcsc);
 	printf("\tPISCR\t0x%08X \n", timers->sit_piscr);
 
@@ -105,7 +104,7 @@ int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	mfdcr(uicvr),
 	mfdcr(uicvcr));
 
-	printf ("\nMemory (SDRAM) Configuration\n"
+	puts ("\nMemory (SDRAM) Configuration\n"
 	    "besra    besrsa   besrb    besrsb   bear     mcopt1   rtr      pmit\n");
 
 	mtdcr(memcfga,mem_besra); 	printf ("%08x ", mfdcr(memcfgd));
@@ -117,7 +116,7 @@ int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	mtdcr(memcfga,mem_rtr); 	printf ("%08x ", mfdcr(memcfgd));
 	mtdcr(memcfga,mem_pmit); 	printf ("%08x ", mfdcr(memcfgd));
 
-	printf ("\n"
+	puts ("\n"
 	    "mb0cf    mb1cf    mb2cf    mb3cf    sdtr1    ecccf    eccerr\n");
 	mtdcr(memcfga,mem_mb0cf); 	printf ("%08x ", mfdcr(memcfgd));
 	mtdcr(memcfga,mem_mb1cf); 	printf ("%08x ", mfdcr(memcfgd));
@@ -145,7 +144,7 @@ int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	mfdcr(dmacr2), mfdcr(dmact2),mfdcr(dmada2), mfdcr(dmasa2), mfdcr(dmasb2),
 	mfdcr(dmacr3), mfdcr(dmact3),mfdcr(dmada3), mfdcr(dmasa3), mfdcr(dmasb3) );
 
-	printf ("\n"
+	puts ("\n"
 	    "External Bus\n"
 	    "pbear    pbesr0   pbesr1   epcr\n");
 	mtdcr(ebccfga,pbear); 	printf ("%08x ", mfdcr(ebccfgd));
@@ -153,7 +152,7 @@ int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	mtdcr(ebccfga,pbesr1); 	printf ("%08x ", mfdcr(ebccfgd));
 	mtdcr(ebccfga,epcr); 	printf ("%08x ", mfdcr(ebccfgd));
 
-	printf ("\n"
+	puts ("\n"
 	    "pb0cr    pb0ap    pb1cr    pb1ap    pb2cr    pb2ap    pb3cr    pb3ap\n");
 	mtdcr(ebccfga,pb0cr); 	printf ("%08x ", mfdcr(ebccfgd));
 	mtdcr(ebccfga,pb0ap); 	printf ("%08x ", mfdcr(ebccfgd));
@@ -164,7 +163,7 @@ int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	mtdcr(ebccfga,pb3cr); 	printf ("%08x ", mfdcr(ebccfgd));
 	mtdcr(ebccfga,pb3ap); 	printf ("%08x ", mfdcr(ebccfgd));
 
-	printf ("\n"
+	puts ("\n"
 	    "pb4cr    pb4ap    pb5cr    bp5ap    pb6cr    pb6ap    pb7cr    pb7ap\n");
 	mtdcr(ebccfga,pb4cr); 	printf ("%08x ", mfdcr(ebccfgd));
 	mtdcr(ebccfga,pb4ap); 	printf ("%08x ", mfdcr(ebccfgd));
@@ -175,7 +174,7 @@ int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	mtdcr(ebccfga,pb7cr); 	printf ("%08x ", mfdcr(ebccfgd));
 	mtdcr(ebccfga,pb7ap); 	printf ("%08x ", mfdcr(ebccfgd));
 
-	printf ("\n\n");
+	puts ("\n\n");
 /* For the BUBINGA (IBM 405EP eval) but should be generically 405ep */
 #elif defined(CONFIG_405EP)
 	printf ("\n405EP registers; MSR=%08x\n",mfmsr());
@@ -192,7 +191,7 @@ int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	mfdcr(uicvr),
 	mfdcr(uicvcr));
 
-	printf ("\nMemory (SDRAM) Configuration\n"
+	puts ("\nMemory (SDRAM) Configuration\n"
 	    "mcopt1   rtr      pmit     mb0cf    mb1cf    sdtr1\n");
 
 	mtdcr(memcfga,mem_mcopt1); 	printf ("%08x ", mfdcr(memcfgd));
@@ -217,7 +216,7 @@ int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	mfdcr(dmacr2), mfdcr(dmact2),mfdcr(dmada2), mfdcr(dmasa2), mfdcr(dmasb2),
 	mfdcr(dmacr3), mfdcr(dmact3),mfdcr(dmada3), mfdcr(dmasa3), mfdcr(dmasb3) );
 
-	printf ("\n"
+	puts ("\n"
 	    "External Bus\n"
 	    "pbear    pbesr0   pbesr1   epcr\n");
 	mtdcr(ebccfga,pbear); 	printf ("%08x ", mfdcr(ebccfgd));
@@ -225,7 +224,7 @@ int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	mtdcr(ebccfga,pbesr1); 	printf ("%08x ", mfdcr(ebccfgd));
 	mtdcr(ebccfga,epcr); 	printf ("%08x ", mfdcr(ebccfgd));
 
-	printf ("\n"
+	puts ("\n"
 	    "pb0cr    pb0ap    pb1cr    pb1ap    pb2cr    pb2ap    pb3cr    pb3ap\n");
 	mtdcr(ebccfga,pb0cr); 	printf ("%08x ", mfdcr(ebccfgd));
 	mtdcr(ebccfga,pb0ap); 	printf ("%08x ", mfdcr(ebccfgd));
@@ -236,12 +235,12 @@ int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	mtdcr(ebccfga,pb3cr); 	printf ("%08x ", mfdcr(ebccfgd));
 	mtdcr(ebccfga,pb3ap); 	printf ("%08x ", mfdcr(ebccfgd));
 
-	printf ("\n"
+	puts ("\n"
 	    "pb4cr    pb4ap\n");
 	mtdcr(ebccfga,pb4cr); 	printf ("%08x ", mfdcr(ebccfgd));
 	mtdcr(ebccfga,pb4ap); 	printf ("%08x ", mfdcr(ebccfgd));
 
-	printf ("\n\n");
+	puts ("\n\n");
 #elif defined(CONFIG_5xx)
 
 	volatile immap_t     	*immap  = (immap_t *)CFG_IMMR;
@@ -251,14 +250,14 @@ int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	volatile car5xx_t	*car = &immap->im_clkrst;
 	volatile uimb5xx_t	*uimb = &immap->im_uimb;
 
-	printf("\nSystem Configuration registers\n");
+	puts ("\nSystem Configuration registers\n");
 	printf("\tIMMR\t0x%08X\tSIUMCR\t0x%08X \n", get_immr(0), sysconf->sc_siumcr);
 	printf("\tSYPCR\t0x%08X\tSWSR\t0x%04X \n" ,sysconf->sc_sypcr, sysconf->sc_swsr);
 	printf("\tSIPEND\t0x%08X\tSIMASK\t0x%08X \n", sysconf->sc_sipend, sysconf->sc_simask);
 	printf("\tSIEL\t0x%08X\tSIVEC\t0x%08X \n", sysconf->sc_siel, sysconf->sc_sivec);
 	printf("\tTESR\t0x%08X\n", sysconf->sc_tesr);
 
-	printf("\nMemory Controller Registers\n");
+	puts ("\nMemory Controller Registers\n");
 	printf("\tBR0\t0x%08X\tOR0\t0x%08X \n", memctl->memc_br0, memctl->memc_or0);
 	printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", memctl->memc_br1, memctl->memc_or1);
 	printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", memctl->memc_br2, memctl->memc_or2);
@@ -266,16 +265,16 @@ int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	printf("\tDMBR\t0x%08X\tDMOR\t0x%08X \n", memctl->memc_dmbr, memctl->memc_dmor );
 	printf("\tMSTAT\t0x%08X\n", memctl->memc_mstat);
 
-	printf("\nSystem Integration Timers\n");
+	puts ("\nSystem Integration Timers\n");
 	printf("\tTBSCR\t0x%08X\tRTCSC\t0x%08X \n", timers->sit_tbscr, timers->sit_rtcsc);
 	printf("\tPISCR\t0x%08X \n", timers->sit_piscr);
 
-	printf("\nClocks and Reset\n");
+	puts ("\nClocks and Reset\n");
 	printf("\tSCCR\t0x%08X\tPLPRCR\t0x%08X \n", car->car_sccr, car->car_plprcr);
 
-	printf("\nU-Bus to IMB3 Bus Interface\n");
+	puts ("\nU-Bus to IMB3 Bus Interface\n");
 	printf("\tUMCR\t0x%08X\tUIPEND\t0x%08X \n", uimb->uimb_umcr, uimb->uimb_uipend);
-	printf ("\n\n");
+	puts ("\n\n");
 #endif /* CONFIG_5xx */
 	return 0;
 }

common/cmd_reiser.c

@@ -0,0 +1,277 @@
+/*
+ * (C) Copyright 2003 - 2004
+ * Sysgo Real-Time Solutions, AG <www.elinos.com>
+ * Pavel Bartusek <pba@sysgo.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+/*
+ * Reiserfs support
+ */
+#include <common.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_REISER)
+#include <config.h>
+#include <command.h>
+#include <image.h>
+#include <linux/ctype.h>
+#include <asm/byteorder.h>
+#include <reiserfs.h>
+
+#ifndef CONFIG_DOS_PARTITION
+#error DOS partition support must be selected
+#endif
+
+/* #define	REISER_DEBUG */
+
+#ifdef	REISER_DEBUG
+#define	PRINTF(fmt,args...)	printf (fmt ,##args)
+#else
+#define PRINTF(fmt,args...)
+#endif
+
+static block_dev_desc_t *get_dev (char* ifname, int dev)
+{
+#if (CONFIG_COMMANDS & CFG_CMD_IDE)
+	if (strncmp(ifname,"ide",3)==0) {
+		extern block_dev_desc_t * ide_get_dev(int dev);
+		return((dev >= CFG_IDE_MAXDEVICE) ? NULL : ide_get_dev(dev));
+	}
+#endif
+#if (CONFIG_COMMANDS & CFG_CMD_SCSI)
+	if (strncmp(ifname,"scsi",4)==0) {
+		extern block_dev_desc_t * scsi_get_dev(int dev);
+		return((dev >= CFG_SCSI_MAXDEVICE) ? NULL : scsi_get_dev(dev));
+	}
+#endif
+#if ((CONFIG_COMMANDS & CFG_CMD_USB) && defined(CONFIG_USB_STORAGE))
+	if (strncmp(ifname,"usb",3)==0) {
+		extern block_dev_desc_t * usb_stor_get_dev(int dev);
+		return((dev >= USB_MAX_STOR_DEV) ? NULL : usb_stor_get_dev(dev));
+	}
+#endif
+#if defined(CONFIG_MMC)
+	if (strncmp(ifname,"mmc",3)==0) {
+		extern block_dev_desc_t *  mmc_get_dev(int dev);
+		return((dev >= 1) ? NULL : mmc_get_dev(dev));
+	}
+#endif
+#if defined(CONFIG_SYSTEMACE)
+	if (strcmp(ifname,"ace")==0) {
+		extern block_dev_desc_t *  systemace_get_dev(int dev);
+		return((dev >= 1) ? NULL : systemace_get_dev(dev));
+	}
+#endif
+	return NULL;
+}
+
+int do_reiserls (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	char *filename = "/";
+	int dev=0;
+	int part=1;
+	char *ep;
+	block_dev_desc_t *dev_desc=NULL;
+	int part_length;
+
+	if (argc < 3) {
+		printf ("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+	}
+	dev = (int)simple_strtoul (argv[2], &ep, 16);
+	dev_desc=get_dev(argv[1],dev);
+
+	if (dev_desc == NULL) {
+		printf ("\n** Block device %s %d not supported\n", argv[1], dev);
+		return 1;
+	}
+
+	if (*ep) {
+		if (*ep != ':') {
+			puts ("\n** Invalid boot device, use `dev[:part]' **\n");
+			return 1;
+		}
+		part = (int)simple_strtoul(++ep, NULL, 16);
+	}
+
+	if (argc == 4) {
+	    filename = argv[3];
+	}
+
+	PRINTF("Using device %s %d:%d, directory: %s\n", argv[1], dev, part, filename);
+
+	if ((part_length = reiserfs_set_blk_dev(dev_desc, part)) == 0) {
+		printf ("** Bad partition - %s %d:%d **\n",  argv[1], dev, part);
+		return 1;
+	}
+
+	if (!reiserfs_mount(part_length)) {
+		printf ("** Bad Reisefs partition or disk - %s %d:%d **\n",  argv[1], dev, part);
+		return 1;
+	}
+
+	if (reiserfs_ls (filename)) {
+		printf ("** Error reiserfs_ls() **\n");
+		return 1;
+	};
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	reiserls,	4,	1,	do_reiserls,
+	"reiserls- list files in a directory (default /)\n",
+	"<interface> <dev[:part]> [directory]\n"
+	"    - list files from 'dev' on 'interface' in a 'directory'\n"
+);
+
+/******************************************************************************
+ * Reiserfs boot command intepreter. Derived from diskboot
+ */
+int do_reiserload (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	char *filename = NULL;
+	char *ep;
+	int dev, part = 0;
+	ulong addr = 0, part_length, filelen;
+	disk_partition_t info;
+	block_dev_desc_t *dev_desc = NULL;
+	char buf [12];
+	unsigned long count;
+	char *addr_str;
+
+	switch (argc) {
+	case 3:
+		addr_str = getenv("loadaddr");
+		if (addr_str != NULL) {
+			addr = simple_strtoul (addr_str, NULL, 16);
+		} else {
+			addr = CFG_LOAD_ADDR;
+		}
+		filename = getenv ("bootfile");
+		count = 0;
+		break;
+	case 4:
+		addr = simple_strtoul (argv[3], NULL, 16);
+		filename = getenv ("bootfile");
+		count = 0;
+		break;
+	case 5:
+		addr = simple_strtoul (argv[3], NULL, 16);
+		filename = argv[4];
+		count = 0;
+		break;
+	case 6:
+		addr = simple_strtoul (argv[3], NULL, 16);
+		filename = argv[4];
+		count = simple_strtoul (argv[5], NULL, 16);
+		break;
+
+	default:
+		printf ("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+	}
+
+	if (!filename) {
+		puts ("\n** No boot file defined **\n");
+		return 1;
+	}
+
+	dev = (int)simple_strtoul (argv[2], &ep, 16);
+	dev_desc=get_dev(argv[1],dev);
+	if (dev_desc==NULL) {
+		printf ("\n** Block device %s %d not supported\n", argv[1], dev);
+		return 1;
+	}
+	if (*ep) {
+		if (*ep != ':') {
+			puts ("\n** Invalid boot device, use `dev[:part]' **\n");
+			return 1;
+		}
+		part = (int)simple_strtoul(++ep, NULL, 16);
+	}
+
+	PRINTF("Using device %s%d, partition %d\n", argv[1], dev, part);
+
+	if (part != 0) {
+		if (get_partition_info (&dev_desc[dev], part, &info)) {
+			printf ("** Bad partition %d **\n", part);
+			return 1;
+		}
+
+		if (strncmp(info.type, BOOT_PART_TYPE, sizeof(info.type)) != 0) {
+			printf ("\n** Invalid partition type \"%.32s\""
+				" (expect \"" BOOT_PART_TYPE "\")\n",
+				info.type);
+			return 1;
+		}
+		PRINTF ("\nLoading from block device %s device %d, partition %d: "
+			"Name: %.32s  Type: %.32s  File:%s\n",
+			argv[1], dev, part, info.name, info.type, filename);
+	} else {
+		PRINTF ("\nLoading from block device %s device %d, File:%s\n",
+			argv[1], dev, filename);
+	}
+
+
+	if ((part_length = reiserfs_set_blk_dev(dev_desc, part)) == 0) {
+		printf ("** Bad partition - %s %d:%d **\n",  argv[1], dev, part);
+		return 1;
+	}
+
+	if (!reiserfs_mount(part_length)) {
+		printf ("** Bad Reisefs partition or disk - %s %d:%d **\n",  argv[1], dev, part);
+		return 1;
+	}
+
+	filelen = reiserfs_open(filename);
+	if (filelen < 0) {
+		printf("** File not found %s\n", filename);
+		return 1;
+	}
+	if ((count < filelen) && (count != 0)) {
+	    filelen = count;
+	}
+
+	if (reiserfs_read((char *)addr, filelen) != filelen) {
+		printf("\n** Unable to read \"%s\" from %s %d:%d **\n", filename, argv[1], dev, part);
+		return 1;
+	}
+
+	/* Loading ok, update default load address */
+	load_addr = addr;
+
+	printf ("\n%ld bytes read\n", filelen);
+	sprintf(buf, "%lX", filelen);
+	setenv("filesize", buf);
+
+	return filelen;
+}
+
+U_BOOT_CMD(
+	reiserload,	6,	0,	do_reiserload,
+	"reiserload- load binary file from a Reiser filesystem\n",
+	"<interface> <dev[:part]> [addr] [filename] [bytes]\n"
+	"    - load binary file 'filename' from 'dev' on 'interface'\n"
+	"      to address 'addr' from dos filesystem\n"
+);
+
+#endif	/* CONFIG_COMMANDS & CFG_CMD_REISER */

common/command.c

@@ -74,6 +74,159 @@ U_BOOT_CMD(
 	"    - echo args to console; \\c suppresses newline\n"
 );
 
+#ifdef CFG_HUSH_PARSER
+
+int
+do_test (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	char **ap;
+	int left, adv, expr, last_expr, neg, last_cmp;
+
+	/* args? */
+	if (argc < 3)
+		return 1;
+
+#if 0
+	{
+		printf("test:");
+		left = 1;
+		while (argv[left])
+			printf(" %s", argv[left++]);
+	}
+#endif
+
+	last_expr = 0;
+	left = argc - 1; ap = argv + 1;
+	if (left > 0 && strcmp(ap[0], "!") == 0) {
+		neg = 1;
+		ap++;
+		left--;
+	} else
+		neg = 0;
+
+	expr = -1;
+	last_cmp = -1;
+	last_expr = -1;
+	while (left > 0) {
+
+		if (strcmp(ap[0], "-o") == 0 || strcmp(ap[0], "-a") == 0)
+			adv = 1;
+		else if (strcmp(ap[0], "-z") == 0 || strcmp(ap[0], "-n") == 0)
+			adv = 2;
+		else
+			adv = 3;
+
+		if (left < adv) {
+			expr = 1;
+			break;
+		}
+
+		if (adv == 1) {
+			if (strcmp(ap[0], "-o") == 0) {
+				last_expr = expr;
+				last_cmp = 0;
+			} else if (strcmp(ap[0], "-a") == 0) {
+				last_expr = expr;
+				last_cmp = 1;
+			} else {
+				expr = 1;
+				break;
+			}
+		}
+
+		if (adv == 2) {
+			if (strcmp(ap[0], "-z") == 0)
+				expr = strlen(ap[1]) == 0 ? 0 : 1;
+			else if (strcmp(ap[0], "-n") == 0)
+				expr = strlen(ap[1]) == 0 ? 1 : 0;
+			else {
+				expr = 1;
+				break;
+			}
+
+			if (last_cmp == 0)
+				expr = last_expr || expr;
+			else if (last_cmp == 1)
+				expr = last_expr && expr;
+			last_cmp = -1;
+		}
+
+		if (adv == 3) {
+			if (strcmp(ap[1], "=") == 0)
+				expr = strcmp(ap[0], ap[2]) == 0;
+			else if (strcmp(ap[1], "!=") == 0)
+				expr = strcmp(ap[0], ap[2]) != 0;
+			else if (strcmp(ap[1], ">") == 0)
+				expr = strcmp(ap[0], ap[2]) > 0;
+			else if (strcmp(ap[1], "<") == 0)
+				expr = strcmp(ap[0], ap[2]) < 0;
+			else if (strcmp(ap[1], "-eq") == 0)
+				expr = simple_strtol(ap[0], NULL, 10) == simple_strtol(ap[2], NULL, 10);
+			else if (strcmp(ap[1], "-ne") == 0)
+				expr = simple_strtol(ap[0], NULL, 10) != simple_strtol(ap[2], NULL, 10);
+			else if (strcmp(ap[1], "-lt") == 0)
+				expr = simple_strtol(ap[0], NULL, 10) < simple_strtol(ap[2], NULL, 10);
+			else if (strcmp(ap[1], "-le") == 0)
+				expr = simple_strtol(ap[0], NULL, 10) <= simple_strtol(ap[2], NULL, 10);
+			else if (strcmp(ap[1], "-gt") == 0)
+				expr = simple_strtol(ap[0], NULL, 10) > simple_strtol(ap[2], NULL, 10);
+			else if (strcmp(ap[1], "-ge") == 0)
+				expr = simple_strtol(ap[0], NULL, 10) >= simple_strtol(ap[2], NULL, 10);
+			else {
+				expr = 1;
+				break;
+			}
+
+			if (last_cmp == 0)
+				expr = last_expr || expr;
+			else if (last_cmp == 1)
+				expr = last_expr && expr;
+			last_cmp = -1;
+		}
+
+		ap += adv; left -= adv;
+	}
+
+	if (neg)
+		expr = !expr;
+
+	expr = !expr;
+
+#if 0
+	printf(": returns %d\n", expr);
+#endif
+
+	return expr;
+}
+
+U_BOOT_CMD(
+	test,	CFG_MAXARGS,	1,	do_test,
+ 	"test    - minimal test like /bin/sh\n",
+ 	"[args..]\n"
+	"    - test functionality\n"
+);
+
+int
+do_exit (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	int r;
+
+	r = 0;
+	if (argc > 1)
+		r = simple_strtoul(argv[1], NULL, 10);
+
+	return -r - 2;
+}
+
+U_BOOT_CMD(
+	exit,	2,	1,	do_exit,
+ 	"exit    - exit script\n",
+	"    - exit functionality\n"
+);
+
+
+#endif
+
 /*
  * Use puts() instead of printf() to avoid printf buffer overflow
  * for long help messages
@@ -217,3 +370,285 @@ cmd_tbl_t *find_cmd (const char *cmd)
 
 	return NULL;	/* not found or ambiguous command */
 }
+
+#ifdef CONFIG_AUTO_COMPLETE
+
+int var_complete(int argc, char *argv[], char last_char, int maxv, char *cmdv[])
+{
+	static char tmp_buf[512];
+	int space;
+
+	space = last_char == '\0' || last_char == ' ' || last_char == '\t';
+
+	if (space && argc == 1)
+		return env_complete("", maxv, cmdv, sizeof(tmp_buf), tmp_buf);
+
+	if (!space && argc == 2)
+		return env_complete(argv[1], maxv, cmdv, sizeof(tmp_buf), tmp_buf);
+
+	return 0;
+}
+
+static void install_auto_complete_handler(const char *cmd,
+		int (*complete)(int argc, char *argv[], char last_char, int maxv, char *cmdv[]))
+{
+	cmd_tbl_t *cmdtp;
+
+	cmdtp = find_cmd(cmd);
+	if (cmdtp == NULL)
+		return;
+
+	cmdtp->complete = complete;
+}
+
+void install_auto_complete(void)
+{
+	install_auto_complete_handler("printenv", var_complete);
+	install_auto_complete_handler("setenv", var_complete);
+#if (CONFIG_COMMANDS & CFG_CMD_RUN)
+	install_auto_complete_handler("run", var_complete);
+#endif
+}
+
+/*************************************************************************************/
+
+static int complete_cmdv(int argc, char *argv[], char last_char, int maxv, char *cmdv[])
+{
+	cmd_tbl_t *cmdtp;
+	const char *p;
+	int len, clen;
+	int n_found = 0;
+	const char *cmd;
+
+	/* sanity? */
+	if (maxv < 2)
+		return -2;
+
+	cmdv[0] = NULL;
+
+	if (argc == 0) {
+		/* output full list of commands */
+		for (cmdtp = &__u_boot_cmd_start; cmdtp != &__u_boot_cmd_end; cmdtp++) {
+			if (n_found >= maxv - 2) {
+				cmdv[n_found++] = "...";
+				break;
+			}
+			cmdv[n_found++] = cmdtp->name;
+		}
+		cmdv[n_found] = NULL;
+		return n_found;
+	}
+
+	/* more than one arg or one but the start of the next */
+	if (argc > 1 || (last_char == '\0' || last_char == ' ' || last_char == '\t')) {
+		cmdtp = find_cmd(argv[0]);
+		if (cmdtp == NULL || cmdtp->complete == NULL) {
+			cmdv[0] = NULL;
+			return 0;
+		}
+		return (*cmdtp->complete)(argc, argv, last_char, maxv, cmdv);
+	}
+
+	cmd = argv[0];
+	/*
+	 * Some commands allow length modifiers (like "cp.b");
+	 * compare command name only until first dot.
+	 */
+	p = strchr(cmd, '.');
+	if (p == NULL)
+		len = strlen(cmd);
+	else
+		len = p - cmd;
+
+	/* return the partial matches */
+	for (cmdtp = &__u_boot_cmd_start; cmdtp != &__u_boot_cmd_end; cmdtp++) {
+
+		clen = strlen(cmdtp->name);
+		if (clen < len)
+			continue;
+
+		if (memcmp(cmd, cmdtp->name, len) != 0)
+			continue;
+
+		/* too many! */
+		if (n_found >= maxv - 2) {
+			cmdv[n_found++] = "...";
+			break;
+		}
+
+		cmdv[n_found++] = cmdtp->name;
+	}
+
+	cmdv[n_found] = NULL;
+	return n_found;
+}
+
+static int make_argv(char *s, int argvsz, char *argv[])
+{
+	int argc = 0;
+
+	/* split into argv */
+	while (argc < argvsz - 1) {
+
+		/* skip any white space */
+		while ((*s == ' ') || (*s == '\t'))
+			++s;
+
+		if (*s == '\0') 	/* end of s, no more args	*/
+			break;
+
+		argv[argc++] = s;	/* begin of argument string	*/
+
+		/* find end of string */
+		while (*s && (*s != ' ') && (*s != '\t'))
+			++s;
+
+		if (*s == '\0')		/* end of s, no more args	*/
+			break;
+
+		*s++ = '\0';		/* terminate current arg	 */
+	}
+	argv[argc] = NULL;
+
+	return argc;
+}
+
+static void print_argv(const char *banner, const char *leader, const char *sep, int linemax, char *argv[])
+{
+	int ll = leader != NULL ? strlen(leader) : 0;
+	int sl = sep != NULL ? strlen(sep) : 0;
+	int len, i;
+
+	if (banner) {
+		puts("\n");
+		puts(banner);
+	}
+
+	i = linemax;	/* force leader and newline */
+	while (*argv != NULL) {
+		len = strlen(*argv) + sl;
+		if (i + len >= linemax) {
+			puts("\n");
+			if (leader)
+				puts(leader);
+			i = ll - sl;
+		} else if (sep)
+			puts(sep);
+		puts(*argv++);
+		i += len;
+	}
+	printf("\n");
+}
+
+static int find_common_prefix(char *argv[])
+{
+	int i, len;
+	char *anchor, *s, *t;
+
+	if (*argv == NULL)
+		return 0;
+
+	/* begin with max */
+	anchor = *argv++;
+	len = strlen(anchor);
+	while ((t = *argv++) != NULL) {
+		s = anchor;
+		for (i = 0; i < len; i++, t++, s++) {
+			if (*t != *s)
+				break;
+		}
+		len = s - anchor;
+	}
+	return len;
+}
+
+static char tmp_buf[CFG_CBSIZE];	/* copy of console I/O buffer	*/
+
+int cmd_auto_complete(const char *const prompt, char *buf, int *np, int *colp)
+{
+	int n = *np, col = *colp;
+	char *argv[CFG_MAXARGS + 1];		/* NULL terminated	*/
+	char *cmdv[20];
+	char *s, *t;
+	const char *sep;
+	int i, j, k, len, seplen, argc;
+	int cnt;
+	char last_char;
+
+	if (strcmp(prompt, CFG_PROMPT) != 0)
+		return 0;	/* not in normal console */
+
+	cnt = strlen(buf);
+	if (cnt >= 1)
+		last_char = buf[cnt - 1];
+	else
+		last_char = '\0';
+
+	/* copy to secondary buffer which will be affected */
+	strcpy(tmp_buf, buf);
+
+	/* separate into argv */
+	argc = make_argv(tmp_buf, sizeof(argv)/sizeof(argv[0]), argv);
+
+	/* do the completion and return the possible completions */
+	i = complete_cmdv(argc, argv, last_char, sizeof(cmdv)/sizeof(cmdv[0]), cmdv);
+
+	/* no match; bell and out */
+	if (i == 0) {
+		if (argc > 1)	/* allow tab for non command */
+			return 0;
+		putc('\a');
+		return 1;
+	}
+
+	s = NULL;
+	len = 0;
+	sep = NULL;
+	seplen = 0;
+	if (i == 1) { /* one match; perfect */
+		k = strlen(argv[argc - 1]);
+		s = cmdv[0] + k;
+		len = strlen(s);
+		sep = " ";
+		seplen = 1;
+	} else if (i > 1 && (j = find_common_prefix(cmdv)) != 0) {	/* more */
+		k = strlen(argv[argc - 1]);
+		j -= k;
+		if (j > 0) {
+			s = cmdv[0] + k;
+			len = j;
+		}
+	}
+
+	if (s != NULL) {
+		k = len + seplen;
+		/* make sure it fits */
+		if (n + k >= CFG_CBSIZE - 2) {
+			putc('\a');
+			return 1;
+		}
+
+		t = buf + cnt;
+		for (i = 0; i < len; i++)
+			*t++ = *s++;
+		if (sep != NULL)
+			for (i = 0; i < seplen; i++)
+				*t++ = sep[i];
+		*t = '\0';
+		n += k;
+		col += k;
+		puts(t - k);
+		if (sep == NULL)
+			putc('\a');
+		*np = n;
+		*colp = col;
+	} else {
+		print_argv(NULL, "  ", " ", 78, cmdv);
+
+		puts(prompt);
+		puts(buf);
+	}
+	return 1;
+}
+
+#endif