Fix CONFIG_ETH*ADDR for Ocotea board.

Sort Makefile. Update docs.
Patch by Scott McNutt, 25 Apr 2004:
2026-06-07 12:16:44 +03:00 · 2004-05-29 16:53:29 +00:00 · 2004-05-19 21:33:14 +00:00 · 2004-05-13 13:23:58 +00:00 · 2004-05-12 22:54:36 +00:00 · 2004-05-12 22:18:31 +00:00
66 changed files with 3657 additions and 2126 deletions
--- a/76
+++ b/76
@@ -1,7 +1,83 @@
+======================================================================
+Changes since U-Boot 1.1.1:
+======================================================================
+
+* Patch by Scott McNutt, 25 Apr 2004:
+  Add Nios GDB/JTAG Console support:
+  - Add stubs to support gdb via JTAG.
+  - Add support for console over JTAG.
+  - Minor cleanup.
+
+* Add support for CATcenter board (based on PPChameleon ME module)
+
+* Patch by Klaus Heydeck, 12 May 2004:
+  Using external watchdog for KUP4 boards in mpc8xx/cpu.c;
+  load_sernum_ethaddr() for KUP4 boards in lib_ppc/board.c;
+  various changes to KUP4 board specific files
+
+* Fix minor network problem on MPC5200: need some delay between
+  resetting the PHY and sending the first packet. Implemented in a
+  "natural" way by invoking the PHY reset and initialization code
+  only once after power on vs. each time the interface is brought up.
+
+* Add some limited support for low-speed devices to SL811 USB controller
+  (at least "usb reset" now passes successfully and "usb info" displays
+  correct information)
+
+* Change init sequence for multiple network interfaces: initialize
+  on-chip interfaces before external cards.
+
+* Fix memory leak in the NAND-specific JFFS2 code
+
+* Fix SL811 USB controller when attached to a USB hub
+
+* Fix config option spelling in PM520 config file
+
+* Fix PHY discovery problem in cpu/mpc8xx/fec.c (introduced by
+  patches by Pantelis Antoniou, 30 Mar 2004)
+
+* Fix minor NAND JFFS2 related issue
+
+* Fixes for SL811 USB controller:
+  - implement workaround for broken memory stick
+  - improve error handling
+
+* Increase packet send timeout to 1 ms in cpu/mpc8xx/scc.c to better
+  cope with congested networks.
+
 ======================================================================
 Changes for U-Boot 1.1.1:
 ======================================================================

+* Patch by Travis Sawyer, 23 Apr 2004:
+  Fix VSC/CIS 8201 phy descrambler interoperability timing due to
+  errata from Vitesse Semiconductor.
+
+* Patch by Philippe Robin, 22 Apr 2004:
+  Fix ethernet configuration for "versatile" board
+
+* Patch by Kshitij Gupta, 21 Apr 2004:
+  Remove busy loop and use MPU timer fr usleep() on OMAP1510/1610 boards
+
+* Patch by Steven Scholz, 24 Feb 2004:
+  Fix a bug in AT91RM9200 ethernet driver:
+  The MII interface is now initialized before accessing the PHY.
+
+* Patch by John Kerl, 19 Apr 2004:
+  Use U-boot's miiphy.h for PHY register names, rather than
+  introducing a new header file.
+
+* Update pci_ids.h from linux-2.4.26
+
+* Patch by Masami Komiya, 19 Apr 2004:
+  Fix problem cause by VLAN function on little endian architecture
+  without VLAN environment
+
+* Clean up the TQM8xx_YYMHz configurations; allow to use the same
+  binary image for all clock frequencies. Implement run-time
+  optimization of flash access timing based on the actual bus
+  frequency.
+
 * Modify KUP4X board configuration to use SL811 driver for USB memory
  sticks (including FAT / VFAT filesystem support)

--- a/1
+++ b/1
@@ -98,7 +98,6 @@ Wolfgang Denk <wd@denx.de>
 	TQM8255			MPC8255

 	CPU86			MPC8260
-	PM825			MPC8250
 	PM826			MPC8260
 	TQM8260			MPC8260

--- a/87
+++ b/87
@@ -486,66 +486,26 @@ TOP860_config:		unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx top860 emk

 # Play some tricks for configuration selection
-# All boards can come with 50 MHz (default), 66MHz, 80MHz or 100 MHz clock,
-# but only 855 and 860 boards may come with FEC
-# and 823 boards may have LCD support
-xtract_8xx = $(subst _66MHz,,$(subst _80MHz,,$(subst _100MHz,,$(subst _133MHz,,$(subst _LCD,,$(subst _config,,$1))))))
+# Only 855 and 860 boards may come with FEC
+# and only 823 boards may have LCD support
+xtract_8xx = $(subst _LCD,,$(subst _config,,$1))

 FPS850L_config		\
 FPS860L_config		\
 NSCU_config		\
 TQM823L_config		\
-TQM823L_66MHz_config	\
-TQM823L_80MHz_config	\
 TQM823L_LCD_config	\
-TQM823L_LCD_66MHz_config \
-TQM823L_LCD_80MHz_config \
 TQM850L_config		\
-TQM850L_66MHz_config	\
-TQM850L_80MHz_config	\
 TQM855L_config		\
-TQM855L_66MHz_config	\
-TQM855L_80MHz_config	\
 TQM860L_config		\
-TQM860L_66MHz_config	\
-TQM860L_80MHz_config	\
 TQM862L_config		\
-TQM862L_66MHz_config	\
-TQM862L_80MHz_config	\
 TQM823M_config		\
-TQM823M_66MHz_config	\
-TQM823M_80MHz_config	\
 TQM850M_config		\
-TQM850M_66MHz_config	\
-TQM850M_80MHz_config	\
 TQM855M_config		\
-TQM855M_66MHz_config	\
-TQM855M_80MHz_config	\
 TQM860M_config		\
-TQM860M_66MHz_config	\
-TQM860M_80MHz_config	\
 TQM862M_config		\
-TQM862M_66MHz_config	\
-TQM862M_80MHz_config	\
-TQM862M_100MHz_config	\
 TQM866M_config:		unconfig
 	@ >include/config.h
-	@[ -z "$(findstring _66MHz,$@)" ] || \
-		{ echo "#define CONFIG_66MHz"		>>include/config.h ; \
-		  echo "... with 66MHz system clock" ; \
-		}
-	@[ -z "$(findstring _80MHz,$@)" ] || \
-		{ echo "#define CONFIG_80MHz"		>>include/config.h ; \
-		  echo "... with 80MHz system clock" ; \
-		}
-	@[ -z "$(findstring _100MHz,$@)" ] || \
-		{ echo "#define CONFIG_100MHz"		>>include/config.h ; \
-		  echo "... with 100MHz system clock" ; \
-		}
-	@[ -z "$(findstring _133MHz,$@)" ] || \
-		{ echo "#define CONFIG_133MHz"		>>include/config.h ; \
-		  echo "... with 133MHz system clock" ; \
-		}
 	@[ -z "$(findstring _LCD,$@)" ] || \
 		{ echo "#define CONFIG_LCD"		>>include/config.h ; \
 		  echo "#define CONFIG_NEC_NL6448BC20"	>>include/config.h ; \
@@ -588,6 +548,11 @@ BUBINGA405EP_config:	unconfig
 CANBT_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx canbt esd

+CATcenter_config:	unconfig
+	@ echo "/* CATcenter uses PPChameleon Model ME */"  > include/config.h
+	@ echo "#define CONFIG_PPCHAMELEON_MODULE_MODEL 1" >> include/config.h
+	@./mkconfig -a $(call xtract_4xx,$@) ppc ppc4xx PPChameleonEVB dave
+
 CPCI405_config	\
 CPCI4052_config	\
 CPCI405AB_config:	unconfig
@@ -1182,6 +1147,24 @@ incaip_config: unconfig
 tb0229_config: unconfig
 	@./mkconfig $(@:_config=) mips mips tb0229

+#########################################################################
+## MIPS32 AU1X00
+#########################################################################
+dbau1000_config		: 	unconfig
+	@ >include/config.h
+	@echo "#define CONFIG_DBAU1000 1" >>include/config.h
+	@./mkconfig -a dbau1x00 mips mips dbau1x00
+
+dbau1100_config		: 	unconfig
+	@ >include/config.h
+	@echo "#define CONFIG_DBAU1100 1" >>include/config.h
+	@./mkconfig -a dbau1x00 mips mips dbau1x00
+
+dbau1500_config		: 	unconfig
+	@ >include/config.h
+	@echo "#define CONFIG_DBAU1500 1" >>include/config.h
+	@./mkconfig -a dbau1x00 mips mips dbau1x00
+
 #########################################################################
 ## MIPS64 5Kc
 #########################################################################
@@ -1267,24 +1250,6 @@ suzaku_config:	unconfig
 	@echo "#define CONFIG_SUZAKU 1" >> include/config.h
 	@./mkconfig -a $(@:_config=) microblaze microblaze suzaku AtmarkTechno

-#########################################################################
-## MIPS32 AU1X00
-#########################################################################
-dbau1000_config		: 	unconfig
-	@ >include/config.h
-	@echo "#define CONFIG_DBAU1000 1" >>include/config.h
-	@./mkconfig -a dbau1x00 mips mips dbau1x00
-
-dbau1100_config		: 	unconfig
-	@ >include/config.h
-	@echo "#define CONFIG_DBAU1100 1" >>include/config.h
-	@./mkconfig -a dbau1x00 mips mips dbau1x00
-
-dbau1500_config		: 	unconfig
-	@ >include/config.h
-	@echo "#define CONFIG_DBAU1500 1" >>include/config.h
-	@./mkconfig -a dbau1x00 mips mips dbau1x00
-
 #########################################################################
 #########################################################################

--- a/2278
+++ b/2278
--- a/board/altera/dk1c20/vectors.S
+++ b/board/altera/dk1c20/vectors.S
@@ -38,6 +38,8 @@
 *	_cwp_lolimit	-Handles register window underflows.
 *	_cwp_hilimit	-Handles register window overflows.
 *	_timebase_int	-Increments the timebase.
+ *	_brkpt_hw_int	-Hardware breakpoint handler.
+ *	_brkpt_sw_int	-Software breakpoint handler.
 *	_def_xhandler	-Default exception handler.
 *
 * _timebase_int handles a Nios Timer interrupt and increments the
@@ -58,9 +60,8 @@ _vectors:
 	.long	_def_xhandler@h		/* Vector 0  - NMI */
 	.long	_cwp_lolimit@h		/* Vector 1  -  underflow */
 	.long	_cwp_hilimit@h		/* Vector 2  - overflow	*/
-
-	.long	_def_xhandler@h		/* Vector 3 - GNUPro debug */
-	.long	_def_xhandler@h		/* Vector 4 - GNUPro debug */
+	.long	_brkpt_hw_int@h		/* Vector 3 - Breakpoint */
+	.long	_brkpt_sw_int@h		/* Vector 4 - Single step*/
 	.long	_def_xhandler@h		/* Vector 5 - GNUPro debug */
 	.long	_def_xhandler@h		/* Vector 6 - future reserved */
 	.long	_def_xhandler@h		/* Vector 7 - future reserved */
--- a/board/jse/flash.c
+++ b/board/jse/flash.c
@@ -54,19 +54,17 @@ static void flash_get_offsets (ulong base, flash_info_t * info);
 unsigned long flash_init (void)
 {
 	unsigned long size_b0;
-	unsigned long base_b0;

 	/* Init: no FLASHes known */
 	flash_info[0].flash_id = FLASH_UNKNOWN;

 	/* Static FLASH Bank configuration here - FIXME XXX */

-	size_b0 =
-		flash_get_size ((vu_long *) FLASH_BASE0_PRELIM,
-				&flash_info[0]);
+	size_b0 = flash_get_size ((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]);

 	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
-		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", size_b0, size_b0 << 20);
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0 << 20);
 	}

 	/* Only one bank */
@@ -212,15 +210,10 @@ void flash_print_info (flash_info_t * info)

 		if ((i % 5) == 0)
 			printf ("\n   ");
-#if 0				/* test-only */
-		printf (" %08lX%s",
-			info->start[i], info->protect[i] ? " (RO)" : "     "
-#else
 		printf (" %08lX%s%s",
 			info->start[i],
 			erased ? " E" : "  ", info->protect[i] ? "RO " : "   "
-#endif
-			);
+		);
 	}
 	printf ("\n");
 	return;
@@ -248,11 +241,7 @@ static ulong flash_get_size (vu_long * addr, flash_info_t * info)
 	addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
 	addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00900090;

-#ifdef CONFIG_ADCIOP
-	value = addr2[2];
-#else
 	value = addr2[0];
-#endif

 	switch (value) {
 	case (FLASH_WORD_SIZE) AMD_MANUFACT:
@@ -271,12 +260,7 @@ static ulong flash_get_size (vu_long * addr, flash_info_t * info)
 		return (0);	/* no or unknown flash  */
 	}

-#ifdef CONFIG_ADCIOP
-	value = addr2[0];	/* device ID            */
-	/*        printf("\ndev_code=%x\n", value); */
-#else
 	value = addr2[1];	/* device ID            */
-#endif

 	switch (value) {
 	case (FLASH_WORD_SIZE) AMD_ID_F040B:
@@ -387,36 +371,19 @@ static ulong flash_get_size (vu_long * addr, flash_info_t * info)
 	for (i = 0; i < info->sector_count; i++) {
 		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
 		/* D0 = 1 if protected */
-#ifdef CONFIG_ADCIOP
-		addr2 = (volatile FLASH_WORD_SIZE *) (info->start[i]);
-		info->protect[i] = addr2[4] & 1;
-#else
 		addr2 = (volatile FLASH_WORD_SIZE *) (info->start[i]);
 		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
 			info->protect[i] = 0;
 		else
 			info->protect[i] = addr2[2] & 1;
-#endif
 	}

 	/*
 	 * Prevent writes to uninitialized FLASH.
 	 */
 	if (info->flash_id != FLASH_UNKNOWN) {
-#if 0				/* test-only */
-#ifdef CONFIG_ADCIOP
-		addr2 = (volatile unsigned char *) info->start[0];
-		addr2[ADDR0] = 0xAA;
-		addr2[ADDR1] = 0x55;
-		addr2[ADDR0] = 0xF0;	/* reset bank */
-#else
 		addr2 = (FLASH_WORD_SIZE *) info->start[0];
 		*addr2 = (FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
-#endif
-#else  /* test-only */
-		addr2 = (FLASH_WORD_SIZE *) info->start[0];
-		*addr2 = (FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
-#endif /* test-only */
 	}

 	return (info->size);
--- a/board/kup/common/kup.c
+++ b/board/kup/common/kup.c
@@ -70,3 +70,14 @@ void poweron_key (void)
 	else
 		setenv ("key1", "on");
 }
+
+#ifdef CONFIG_POST
+/*
+ * Returns 1 if keys pressed to start the power-on long-running tests
+ * Called from board_init_f().
+ */
+int post_hotkeys_pressed (void)
+{
+	return (0);
+}
+#endif
--- a/board/kup/common/load_sernum_ethaddr.c
+++ b/board/kup/common/load_sernum_ethaddr.c
@@ -0,0 +1,94 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+/*-----------------------------------------------------------------------
+ * Process Hardware Information Block:
+ *
+ * If we boot on a system fresh from factory, check if the Hardware
+ * Information Block exists and save the information it contains.
+ *
+ * The KUP Hardware Information Block is defined as
+ * follows:
+ * - located in first flash bank
+ * - starts at offset CFG_HWINFO_OFFSET
+ * - size CFG_HWINFO_SIZE
+ *
+ * Internal structure:
+ * - sequence of ASCII character lines
+ * - fields separated by <CR><LF>
+ * - last field terminated by NUL character (0x00)
+ *
+ * Fields in Hardware Information Block:
+ * 1) Module Type
+ * 2) MAC Address
+ * 3) ....
+ */
+
+
+#define ETHADDR_TOKEN "ethaddr="
+#define LCD_TOKEN "lcd="
+
+void load_sernum_ethaddr (void)
+{
+	unsigned char *hwi;
+	unsigned char *var;
+	unsigned char hwi_stack[CFG_HWINFO_SIZE];
+	unsigned char *p;
+
+	hwi = (unsigned char *) (CFG_FLASH_BASE + CFG_HWINFO_OFFSET);
+	if (*((unsigned long *) hwi) != (unsigned long) CFG_HWINFO_MAGIC) {
+		printf ("HardwareInfo not found!\n");
+		return;
+	}
+	memcpy (hwi_stack, hwi, CFG_HWINFO_SIZE);
+
+	/*
+	 ** ethaddr
+	 */
+	var = strstr (hwi_stack, ETHADDR_TOKEN);
+	if (var) {
+		var += sizeof (ETHADDR_TOKEN) - 1;
+		p = strchr (var, '\r');
+		if (p < hwi + CFG_HWINFO_SIZE) {
+			*p = '\0';
+			setenv ("ethaddr", var);
+			*p = '\r';
+		}
+	}
+	/*
+	 ** lcd
+	 */
+	var = strstr (hwi_stack, LCD_TOKEN);
+	if (var) {
+		var += sizeof (LCD_TOKEN) - 1;
+		p = strchr (var, '\r');
+		if (p < hwi + CFG_HWINFO_SIZE) {
+			*p = '\0';
+			setenv ("lcd", var);
+			*p = '\r';
+		}
+	}
+}
--- a/board/kup/kup4k/Makefile
+++ b/board/kup/kup4k/Makefile
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk

 LIB	= lib$(BOARD).a

-OBJS	= $(BOARD).o ../common/flash.o ../common/kup.o
+OBJS	= $(BOARD).o ../common/flash.o ../common/kup.o ../common/load_sernum_ethaddr.o

 $(LIB):	.depend $(OBJS)
 	$(AR) crv $@ $(OBJS)
--- a/board/kup/kup4k/kup4k.c
+++ b/board/kup/kup4k/kup4k.c
@@ -129,11 +129,11 @@ int checkboard (void)
 	 */
 	immap->im_memctl.memc_or4 = 0xFFFF8926;
 	immap->im_memctl.memc_br4 = 0x90000401;
-
+	__asm__ ("eieio");
 	latch=(uchar *)0x90000200;
 	rev = (*latch & 0xF8) >> 3;
 	mod=(*latch & 0x03);
-	printf ("Board: KUP4K Rev %d.%d SN: %s\n",rev,mod,getenv("ethaddr"));
+	printf ("Board: KUP4K Rev %d.%d\n",rev,mod);
 	return (0);
 }

@@ -346,6 +346,7 @@ void lcd_logo (bd_t * bd)
 	 */
 	memctl->memc_or5 = 0xFFC007F0;	/* 4 MB  17 WS or externel TA */
 	memctl->memc_br5 = 0x80080801;	/* Start at 0x80080000 */
+	__asm__ ("eieio");

 	fb_info.VmemAddr = (unsigned char *) (S1D_PHYSICAL_VMEM_ADDR);
 	fb_info.RegAddr = (unsigned char *) (S1D_PHYSICAL_REG_ADDR);
--- a/board/kup/kup4x/Makefile
+++ b/board/kup/kup4x/Makefile
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk

 LIB	= lib$(BOARD).a

-OBJS	= $(BOARD).o ../common/flash.o ../common/kup.o
+OBJS	= $(BOARD).o ../common/flash.o ../common/kup.o ../common/load_sernum_ethaddr.o

 $(LIB):	.depend $(OBJS)
 	$(AR) crv $@ $(OBJS)
--- a/board/kup/kup4x/kup4x.c
+++ b/board/kup/kup4x/kup4x.c
@@ -24,6 +24,7 @@

 #include <common.h>
 #include <mpc8xx.h>
+#include <post.h>
 #include "../common/kup.h"
 #ifdef CONFIG_KUP4K_LOGO
 /* #include "s1d13706.h" */
@@ -115,19 +116,19 @@ int checkboard (void)
 {
 	volatile immap_t *immap = (immap_t *) CFG_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
-	uchar *latch, rev, mod;
+	volatile uchar *latch;
+	uchar rev, mod;

 	/*
 	 * Init ChipSelect #4 (CAN + HW-Latch)
 	 */
 	memctl->memc_or4 = 0xFFFF8926;
 	memctl->memc_br4 = 0x90000401;
-
-	latch = (uchar *) 0x90000200;
+	__asm__ ("eieio");
+	latch = (volatile uchar *) 0x90000200;
 	rev = (*latch & 0xF8) >> 3;
 	mod = (*latch & 0x03);
-	printf ("Board: KUP4X Rev %d.%d SN: %s\n", rev, mod,
-		getenv ("ethaddr"));
+	printf ("Board: KUP4X Rev %d.%d\n",rev,mod);
 	return (0);
 }

--- a/board/stxgp3/stxgp3.c
+++ b/board/stxgp3/stxgp3.c
@@ -195,7 +195,6 @@ const iop_conf_t iop_conf_tab[4][32] = {
    }
 };

-static	uint64_t	blinky_increment;
 static	uint64_t	next_led_update;
 static	uint		led_bit;

--- a/board/tqm8xx/flash.c
+++ b/board/tqm8xx/flash.c
@@ -29,6 +29,15 @@
 #include <mpc8xx.h>
 #include <environment.h>

+#include <asm/processor.h>
+
+#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M)
+# ifndef CFG_OR_TIMING_FLASH_AT_50MHZ
+#  define CFG_OR_TIMING_FLASH_AT_50MHZ	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+					 OR_SCY_2_CLK | OR_EHTR | OR_BI)
+# endif
+#endif /* CONFIG_TQM8xxL/M, !TQM866M */
+
 #ifndef	CFG_ENV_ADDR
 #define CFG_ENV_ADDR	(CFG_FLASH_BASE + CFG_ENV_OFFSET)
 #endif
@@ -51,6 +60,50 @@ unsigned long flash_init (void)
 	unsigned long size_b0, size_b1;
 	int i;

+#ifdef	CFG_OR_TIMING_FLASH_AT_50MHZ
+	int scy, trlx, flash_or_timing, clk_diff;
+
+	DECLARE_GLOBAL_DATA_PTR;
+
+	scy = (CFG_OR_TIMING_FLASH_AT_50MHZ & OR_SCY_MSK) >> 4;
+	if (CFG_OR_TIMING_FLASH_AT_50MHZ & OR_TRLX) {
+		trlx = OR_TRLX;
+		scy *= 2;
+	} else
+		trlx = 0;
+
+		/* We assume that each 10MHz of bus clock require 1-clk SCY
+		 * adjustment.
+		 */
+	clk_diff = (gd->bus_clk / 1000000) - 50;
+
+		/* We need proper rounding here. This is what the "+5" and "-5"
+		 * are here for.
+		 */
+	if (clk_diff >= 0)
+		scy += (clk_diff + 5) / 10;
+	else
+		scy += (clk_diff - 5) / 10;
+
+		/* For bus frequencies above 50MHz, we want to use relaxed timing
+		 * (OR_TRLX).
+		 */
+	if (gd->bus_clk >= 50000000)
+		trlx = OR_TRLX;
+	else
+		trlx = 0;
+
+	if (trlx)
+		scy /= 2;
+
+	if (scy > 0xf)
+		scy = 0xf;
+	if (scy < 1)
+		scy = 1;
+
+	flash_or_timing = (scy << 4) | trlx |
+	                  (CFG_OR_TIMING_FLASH_AT_50MHZ & ~(OR_TRLX | OR_SCY_MSK));
+#endif
 	/* Init: no FLASHes known */
 	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
@@ -95,7 +148,11 @@ unsigned long flash_init (void)
 		memctl->memc_br1, memctl->memc_or1);

 	/* Remap FLASH according to real size */
+#ifndef	CFG_OR_TIMING_FLASH_AT_50MHZ
 	memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK);
+#else
+	memctl->memc_or0 = flash_or_timing | (-size_b0 & OR_AM_MSK);
+#endif
 	memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;

 	debug ("## BR0: 0x%08x    OR0: 0x%08x\n",
@@ -146,7 +203,11 @@ unsigned long flash_init (void)
 #endif

 	if (size_b1) {
+#ifndef	CFG_OR_TIMING_FLASH_AT_50MHZ
 		memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000);
+#else
+		memctl->memc_or1 = flash_or_timing | (-size_b1 & 0xFFFF8000);
+#endif
 		memctl->memc_br1 = ((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) |
 				    BR_MS_GPCM | BR_V;

--- a/common/cmd_ace.c
+++ b/common/cmd_ace.c
@@ -53,7 +53,7 @@ static unsigned ace_readw(unsigned offset)
      return readw(CFG_SYSTEMACE_BASE+offset);
 }

-static unsigned ace_writew(unsigned val, unsigned offset)
+static void ace_writew(unsigned val, unsigned offset)
 {
      writew(val, CFG_SYSTEMACE_BASE+offset);
 }
@@ -119,7 +119,6 @@ static unsigned long systemace_read(int dev,
 				    unsigned long blkcnt,
 				    unsigned long *buffer)
 {
-      unsigned val;
      int retry;
      unsigned blk_countdown;
      unsigned char*dp = (unsigned char*)buffer;
@@ -218,4 +217,4 @@ static unsigned long systemace_read(int dev,

      return blkcnt;
 }
-#endif
+#endif	/* CONFIG_SYSTEMACE */
--- a/common/cmd_mii.c
+++ b/common/cmd_mii.c
@@ -31,8 +31,6 @@
 #if (CONFIG_COMMANDS & CFG_CMD_MII)
 #include <miiphy.h>

-#define	CONFIG_TERSE_MII	/* XXX necessary here because "miivals.h" is missing */
-
 #ifdef CONFIG_TERSE_MII
 /*
 * Display values from last command.
@@ -149,8 +147,6 @@ U_BOOT_CMD(

 #else /* ! CONFIG_TERSE_MII ================================================= */

-#include <miivals.h>
-
 typedef struct _MII_reg_desc_t {
 	ushort regno;
 	char * name;
@@ -343,14 +339,14 @@ static int special_field(
 	ushort regval)
 {
 	if ((regno == 0) && (pdesc->lo == 6)) {
-		ushort speed_bits = regval & MII_CTL_SPEED_MASK;
+		ushort speed_bits = regval & PHY_BMCR_SPEED_MASK;
 		printf("%2u,%2u =   b%u%u    speed selection = %s Mbps",
 			6, 13,
 			(regval >>  6) & 1,
 			(regval >> 13) & 1,
-			speed_bits == MII_CTL_SPEED_1000_MBPS ? "1000" :
-			speed_bits == MII_CTL_SPEED_100_MBPS  ? "100" :
-			speed_bits == MII_CTL_SPEED_10_MBPS   ? "10" :
+			speed_bits == PHY_BMCR_1000_MBPS ? "1000" :
+			speed_bits == PHY_BMCR_100_MBPS  ? "100" :
+			speed_bits == PHY_BMCR_10_MBPS   ? "10" :
 			"???");
 		return 1;
 	}
@@ -367,9 +363,9 @@ static int special_field(
 		ushort sel_bits = (regval >> pdesc->lo) & pdesc->mask;
 		printf("%2u-%2u = %5u    selector = %s",
 			pdesc->hi, pdesc->lo, sel_bits,
-			sel_bits == MII_AN_ADV_IEEE_802_3 ?
+			sel_bits == PHY_ANLPAR_PSB_802_3 ?
 				"IEEE 802.3" :
-			sel_bits == MII_AN_ADV_IEEE_802_9_ISLAN_16T ?
+			sel_bits == PHY_ANLPAR_PSB_802_9 ?
 				"IEEE 802.9 ISLAN-16T" :
 			"???");
 		return 1;
@@ -379,9 +375,9 @@ static int special_field(
 		ushort sel_bits = (regval >> pdesc->lo) & pdesc->mask;
 		printf("%2u-%2u =     %u    selector = %s",
 			pdesc->hi, pdesc->lo, sel_bits,
-			sel_bits == MII_AN_PARTNER_IEEE_802_3 ?
+			sel_bits == PHY_ANLPAR_PSB_802_3 ?
 				"IEEE 802.3" :
-			sel_bits == MII_AN_PARTNER_IEEE_802_9_ISLAN_16T ?
+			sel_bits == PHY_ANLPAR_PSB_802_9 ?
 				"IEEE 802.9 ISLAN-16T" :
 			"???");
 		return 1;
@@ -418,7 +414,7 @@ int do_mii (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 {
 	char		op;
 	unsigned char	addrlo, addrhi, reglo, reghi;
-	unsigned char	addr, reg;
+	unsigned char	addr = 0, reg = 0;
 	unsigned short	data;
 	int		rcode = 0;

--- a/common/env_common.c
+++ b/common/env_common.c
@@ -94,6 +94,9 @@ uchar default_environment[] = {
 #ifdef	CONFIG_ETH2ADDR
 	"eth2addr="	MK_STR(CONFIG_ETH2ADDR)		"\0"
 #endif
+#ifdef	CONFIG_ETH3ADDR
+	"eth3addr="	MK_STR(CONFIG_ETH3ADDR)		"\0"
+#endif
 #ifdef	CONFIG_IPADDR
 	"ipaddr="	MK_STR(CONFIG_IPADDR)		"\0"
 #endif
--- a/common/usb_storage.c
+++ b/common/usb_storage.c
@@ -1105,7 +1105,10 @@ int usb_stor_get_info(struct usb_device *dev,struct us_data *ss,block_dev_desc_t
 	unsigned long *capacity,*blksz;
 	ccb *pccb=&usb_ccb;

-	ss->transport_reset(ss);
+	/* For some mysterious reason the 256MB flash disk of Ours Technology, Inc
+	 * doesn't survive this reset */
+	if (dev->descriptor.idVendor != 0xea0 || dev->descriptor.idProduct != 0x6828)
+		ss->transport_reset(ss);
 	pccb->pdata=usb_stor_buf;

 	dev_desc->target=dev->devnum;
--- a/config.mk
+++ b/config.mk
@@ -126,7 +126,7 @@ endif
 # this option have to be placed behind -Wall -- that's why it is here
 ifeq ($(ARCH),nios)
 ifeq ($(findstring 2.9,$(shell $(CC) --version)),2.9)
-CFLAGS := $(CPPFLAGS) -Wno-trigraphs
+CFLAGS := $(CPPFLAGS) -Wall -Wno-trigraphs
 endif
 endif

--- a/cpu/arm925t/interrupts.c
+++ b/cpu/arm925t/interrupts.c
@@ -215,16 +215,9 @@ void set_timer (ulong t)
 	timestamp = t;
 }

-/* delay x useconds AND perserve advance timstamp value */
+/* delay x useconds AND preserve advance timestamp value */
 void udelay (unsigned long usec)
 {
-#ifdef CONFIG_INNOVATOROMAP1510
-#define LOOPS_PER_MSEC 60		/* tuned on omap1510 */
-	volatile int i, time_remaining = LOOPS_PER_MSEC * usec;
-
-	for (i = time_remaining; i > 0; i--) {
-	}
-#else
 	ulong tmo, tmp;

 	if(usec >= 1000){		/* if "big" number, spread normalization to seconds */
@@ -242,9 +235,8 @@ void udelay (unsigned long usec)
 	else
 		tmo += tmp;		/* else, set advancing stamp wake up time */

-	while (get_timer_masked () < tmo)/* loop till event */
+	while (get_timer_masked () < tmo) /* loop till event */
 		/*NOP*/;
-#endif
 }

 void reset_timer_masked (void)
--- a/cpu/at91rm9200/at91rm9200_ether.c
+++ b/cpu/at91rm9200/at91rm9200_ether.c
@@ -378,14 +378,21 @@ int eth_init (bd_t * bd)

 	p_mac = AT91C_BASE_EMAC;

-	*AT91C_PIOA_PDR = AT91C_PA16_EMDIO | AT91C_PA15_EMDC | AT91C_PA14_ERXER | AT91C_PA13_ERX1 | AT91C_PA12_ERX0 | AT91C_PA11_ECRS_ECRSDV | AT91C_PA10_ETX1 | AT91C_PA9_ETX0 | AT91C_PA8_ETXEN | AT91C_PA7_ETXCK_EREFCK;	/* PIO Disable Register */
+	/* PIO Disable Register */
+	*AT91C_PIOA_PDR = AT91C_PA16_EMDIO | AT91C_PA15_EMDC | AT91C_PA14_ERXER |
+			  AT91C_PA13_ERX1 | AT91C_PA12_ERX0 | AT91C_PA11_ECRS_ECRSDV |
+			  AT91C_PA10_ETX1 | AT91C_PA9_ETX0 | AT91C_PA8_ETXEN |
+			  AT91C_PA7_ETXCK_EREFCK;

 	*AT91C_PIOB_PDR = AT91C_PB25_EF100 |
-			AT91C_PB19_ERXCK | AT91C_PB18_ECOL | AT91C_PB17_ERXDV |
-			AT91C_PB16_ERX3 | AT91C_PB15_ERX2 | AT91C_PB14_ETXER |
-			AT91C_PB13_ETX3 | AT91C_PB12_ETX2;
+			  AT91C_PB19_ERXCK | AT91C_PB18_ECOL | AT91C_PB17_ERXDV |
+			  AT91C_PB16_ERX3 | AT91C_PB15_ERX2 | AT91C_PB14_ETXER |
+			  AT91C_PB13_ETX3 | AT91C_PB12_ETX2;

-	*AT91C_PIOB_BSR = AT91C_PB25_EF100 | AT91C_PB19_ERXCK | AT91C_PB18_ECOL | AT91C_PB17_ERXDV | AT91C_PB16_ERX3 | AT91C_PB15_ERX2 | AT91C_PB14_ETXER | AT91C_PB13_ETX3 | AT91C_PB12_ETX2;	/* Select B Register */
+	/* Select B Register */
+	*AT91C_PIOB_BSR = AT91C_PB25_EF100 | AT91C_PB19_ERXCK | AT91C_PB18_ECOL |
+			  AT91C_PB17_ERXDV | AT91C_PB16_ERX3 | AT91C_PB15_ERX2 |
+			  AT91C_PB14_ETXER | AT91C_PB13_ETX3 | AT91C_PB12_ETX2;

 	*AT91C_PMC_PCER = 1 << AT91C_ID_EMAC;	/* Peripheral Clock Enable Register */

@@ -400,6 +407,22 @@ int eth_init (bd_t * bd)
 	rbfdt[RBF_FRAMEMAX - 1].addr |= RBF_WRAP;
 	rbfp = &rbfdt[0];

+	p_mac->EMAC_SA2L = (bd->bi_enetaddr[3] << 24) | (bd->bi_enetaddr[2] << 16)
+			 | (bd->bi_enetaddr[1] <<  8) | (bd->bi_enetaddr[0]);
+	p_mac->EMAC_SA2H = (bd->bi_enetaddr[5] <<  8) | (bd->bi_enetaddr[4]);
+
+	p_mac->EMAC_RBQP = (long) (&rbfdt[0]);
+	p_mac->EMAC_RSR &= ~(AT91C_EMAC_RSR_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA);
+
+	p_mac->EMAC_CFG = (p_mac->EMAC_CFG | AT91C_EMAC_CAF | AT91C_EMAC_NBC)
+			& ~AT91C_EMAC_CLK;
+
+#ifdef CONFIG_AT91C_USE_RMII
+	p_mac->EMAC_CFG |= AT91C_EMAC_RMII;
+#endif
+
+	p_mac->EMAC_CTL |= AT91C_EMAC_TE | AT91C_EMAC_RE;
+
 	at91rm92000_GetPhyInterface ();

 	if (!pPhyOps->IsPhyConnected (p_mac))
@@ -416,22 +439,6 @@ int eth_init (bd_t * bd)
 		return 0;
 	}

-	p_mac->EMAC_SA2L = (bd->bi_enetaddr[3] << 24) | (bd->bi_enetaddr[2] << 16)
-			 | (bd->bi_enetaddr[1] << 8) | (bd->bi_enetaddr[0]);
-	p_mac->EMAC_SA2H = (bd->bi_enetaddr[5] << 8) | (bd->bi_enetaddr[4]);
-
-	p_mac->EMAC_RBQP = (long) (&rbfdt[0]);
-	p_mac->EMAC_RSR &= ~(AT91C_EMAC_RSR_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA);
-
-	p_mac->EMAC_CFG = (p_mac->EMAC_CFG | AT91C_EMAC_CAF | AT91C_EMAC_NBC)
-			& ~AT91C_EMAC_CLK;
-
-#ifdef CONFIG_AT91C_USE_RMII
-	p_mac->EMAC_CFG |= AT91C_EMAC_RMII;
-#endif
-
-	p_mac->EMAC_CTL |= AT91C_EMAC_TE | AT91C_EMAC_RE;
-
 	return 0;
 }

--- a/cpu/mpc5xxx/fec.c
+++ b/cpu/mpc5xxx/fec.c
@@ -238,7 +238,6 @@ static int mpc5xxx_fec_init(struct eth_device *dev, bd_t * bis)
 	DECLARE_GLOBAL_DATA_PTR;
 	mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
 	struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA;
-	const uint8 phyAddr = CONFIG_PHY_ADDR;	/* Only one PHY */

 #if (DEBUG & 0x1)
 	printf ("mpc5xxx_fec_init... Begin\n");
@@ -250,17 +249,6 @@ static int mpc5xxx_fec_init(struct eth_device *dev, bd_t * bis)
 	mpc5xxx_fec_rbd_init(fec);
 	mpc5xxx_fec_tbd_init(fec);

-	/*
-	 * Initialize GPIO pins
-	 */
-	if (fec->xcv_type == SEVENWIRE) {
-		/*  10MBit with 7-wire operation */
-		*(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00020000;
-	} else {
-		/* 100MBit with MD operation */
-		*(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00050000;
-	}
-
 	/*
 	 * Clear FEC-Lite interrupt event register(IEVENT)
 	 */
@@ -371,6 +359,68 @@ static int mpc5xxx_fec_init(struct eth_device *dev, bd_t * bis)
 	*(int *)FEC_TBD_NEXT = (int)fec->tbdBase;
 	*(int *)FEC_RBD_NEXT = (int)fec->rbdBase;

+	/*
+	 * Enable FEC-Lite controller
+	 */
+	fec->eth->ecntrl |= 0x00000006;
+
+#if (DEBUG & 0x2)
+	if (fec->xcv_type != SEVENWIRE)
+		mpc5xxx_fec_phydump ();
+#endif
+
+	/*
+	 * Enable SmartDMA receive task
+	 */
+	SDMA_TASK_ENABLE(FEC_RECV_TASK_NO);
+
+#if (DEBUG & 0x1)
+	printf("mpc5xxx_fec_init... Done \n");
+#endif
+
+	return 1;
+}
+
+/********************************************************************/
+static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
+	const uint8 phyAddr = CONFIG_PHY_ADDR;	/* Only one PHY */
+
+#if (DEBUG & 0x1)
+	printf ("mpc5xxx_fec_init_phy... Begin\n");
+#endif
+
+	/*
+	 * Initialize GPIO pins
+	 */
+	if (fec->xcv_type == SEVENWIRE) {
+		/*  10MBit with 7-wire operation */
+		*(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00020000;
+	} else {
+		/* 100MBit with MD operation */
+		*(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00050000;
+	}
+
+	/*
+	 * Clear FEC-Lite interrupt event register(IEVENT)
+	 */
+	fec->eth->ievent = 0xffffffff;
+
+	/*
+	 * Set interrupt mask register
+	 */
+	fec->eth->imask = 0x00000000;
+
+	if (fec->xcv_type != SEVENWIRE) {
+		/*
+		 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
+		 * and do not drop the Preamble.
+		 */
+		fec->eth->mii_speed = (((gd->ipb_clk >> 20) / 5) << 1);	/* No MII for 7-wire mode */
+	}
+
 	if (fec->xcv_type != SEVENWIRE) {
 		/*
 		 * Initialize PHY(LXT971A):
@@ -486,23 +536,14 @@ static int mpc5xxx_fec_init(struct eth_device *dev, bd_t * bis)

 	}

-	/*
-	 * Enable FEC-Lite controller
-	 */
-	fec->eth->ecntrl |= 0x00000006;
-
 #if (DEBUG & 0x2)
 	if (fec->xcv_type != SEVENWIRE)
 		mpc5xxx_fec_phydump ();
 #endif

-	/*
-	 * Enable SmartDMA receive task
-	 */
-	SDMA_TASK_ENABLE(FEC_RECV_TASK_NO);

 #if (DEBUG & 0x1)
-	printf("mpc5xxx_fec_init... Done \n");
+	printf("mpc5xxx_fec_init_phy... Done \n");
 #endif

 	return 1;
@@ -859,6 +900,7 @@ int mpc5xxx_fec_initialize(bd_t * bis)
 		mpc5xxx_fec_set_hwaddr(fec, env_enetaddr);
 	}

+	mpc5xxx_fec_init_phy(dev, bis);
 	return 1;
 }

--- a/cpu/mpc8xx/cpu.c
+++ b/cpu/mpc8xx/cpu.c
@@ -567,6 +567,17 @@ void reset_8xx_watchdog (volatile immap_t * immr)
 	immr->im_ioport.iop_padir |= WATCHDOG_BIT;	/* Output   */
 	immr->im_ioport.iop_paodr &= ~(WATCHDOG_BIT);	/* active output */

+	immr->im_ioport.iop_padat ^= WATCHDOG_BIT;	/* Toggle WDI   */
+# elif defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X)
+	/*
+	 * The KUP4 boards uses a TPS3705 Watchdog
+	 * with the trigger pin connected to port PA.5
+	 */
+# define WATCHDOG_BIT	0x0400
+	immr->im_ioport.iop_papar &= ~(WATCHDOG_BIT);	/* GPIO     */
+	immr->im_ioport.iop_padir |= WATCHDOG_BIT;	/* Output   */
+	immr->im_ioport.iop_paodr &= ~(WATCHDOG_BIT);	/* active output */
+
 	immr->im_ioport.iop_padat ^= WATCHDOG_BIT;	/* Toggle WDI   */
 # else
 	/*
--- a/cpu/mpc8xx/fec.c
+++ b/cpu/mpc8xx/fec.c
@@ -689,13 +689,14 @@ static int fec_init (struct eth_device *dev, bd_t * bd)
 		 * wait for the PHY to wake up after reset
 		 */
 		efis->actual_phy_addr = mii_discover_phy (dev);
-#else
-		efis->actual_phy_addr = -1;
-#endif
+
 		if (efis->actual_phy_addr == -1) {
 			printf ("Unable to discover phy!\n");
 			return 0;
 		}
+#else
+		efis->actual_phy_addr = -1;
+#endif
 	} else {
 		efis->actual_phy_addr = efis->phy_addr;
 	}
--- a/cpu/mpc8xx/scc.c
+++ b/cpu/mpc8xx/scc.c
@@ -45,7 +45,7 @@

 #define TX_BUF_CNT 2

-#define TOUT_LOOP 100
+#define TOUT_LOOP 10000	/* 10 ms to have a packet sent */

 static char txbuf[DBUF_LENGTH];

--- a/cpu/mpc8xx/speed.c
+++ b/cpu/mpc8xx/speed.c
@@ -347,4 +347,32 @@ static long init_pll_866 (long clk)

 #endif /* CONFIG_MPC866_et_al */

+#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M)
+/*
+ * Adjust sdram refresh rate to actual CPU clock
+ * and set timebase source according to actual CPU clock
+ */
+int adjust_sdram_tbs_8xx (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	long		  mamr;
+	long              sccr;
+
+	mamr = immr->im_memctl.memc_mamr;
+	mamr &= ~MAMR_PTA_MSK;
+	mamr |= ((gd->cpu_clk / CFG_PTA_PER_CLK) << MAMR_PTA_SHIFT);
+	immr->im_memctl.memc_mamr = mamr;
+
+	if (gd->cpu_clk < 67000000) {
+		sccr = immr->im_clkrst.car_sccr;
+		sccr |= SCCR_TBS;
+		immr->im_clkrst.car_sccr = sccr;
+	}
+
+	return (0);
+}
+#endif /* CONFIG_TQM8xxL/M, !TQM866M */
+
 /* ------------------------------------------------------------------------- */
--- a/cpu/nios/interrupts.c
+++ b/cpu/nios/interrupts.c
@@ -179,7 +179,7 @@ int do_irqinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	int vec;

 	printf ("\nInterrupt-Information:\n");
-	printf ("Nr  Routine   Arg       CouIt's ok to cnt\n");
+	printf ("Nr  Routine   Arg       Count\n");

 	for (vec=0; vec<64; vec++) {
 		if (irq_vecs[vec].handler != NULL) {
--- a/cpu/nios/serial.c
+++ b/cpu/nios/serial.c
@@ -26,6 +26,48 @@
 #include <watchdog.h>
 #include <nios-io.h>

+/*------------------------------------------------------------------
+ * JTAG acts as the serial port
+ *-----------------------------------------------------------------*/
+#if defined(CONFIG_CONSOLE_JTAG)
+
+static nios_jtag_t *jtag = (nios_jtag_t *)CFG_NIOS_CONSOLE;
+
+void serial_setbrg( void ){ return; }
+int serial_init( void ) { return(0);}
+
+void serial_putc (char c)
+{
+	while ((jtag->txcntl & NIOS_JTAG_TRDY) != 0)
+		WATCHDOG_RESET ();
+	jtag->txcntl = NIOS_JTAG_TRDY | (unsigned char)c;
+}
+
+void serial_puts (const char *s)
+{
+	while (*s != 0)
+		serial_putc (*s++);
+}
+
+int serial_tstc (void)
+{
+	return (jtag->rxcntl & NIOS_JTAG_RRDY);
+}
+
+int serial_getc (void)
+{
+	int c;
+	while (serial_tstc() == 0)
+		WATCHDOG_RESET ();
+	c = jtag->rxcntl & 0x0ff;
+	jtag->rxcntl = 0;
+	return (c);
+}
+
+/*------------------------------------------------------------------
+ * UART the serial port
+ *-----------------------------------------------------------------*/
+#else

 static nios_uart_t *uart = (nios_uart_t *)CFG_NIOS_CONSOLE;

@@ -34,12 +76,12 @@ static nios_uart_t *uart = (nios_uart_t *)CFG_NIOS_CONSOLE;
 /* Everything's already setup for fixed-baud PTF
 * assignment
 */
-void serial_setbrg( void ){ return; }
-int serial_init( void ) { return(0);}
+void serial_setbrg (void){ return; }
+int serial_init (void) { return (0);}

 #else

-void serial_setbrg( void )
+void serial_setbrg (void)
 {
 	DECLARE_GLOBAL_DATA_PTR;
 	unsigned div;
@@ -49,39 +91,44 @@ void serial_setbrg( void )
 	return;
 }

-int serial_init( void )
+int serial_init (void)
 {
-	serial_setbrg();
-	return(0);
+	serial_setbrg ();
+	return (0);
 }

 #endif /* CFG_NIOS_FIXEDBAUD */


-void serial_putc( char c )
+/*-----------------------------------------------------------------------
+ * UART CONSOLE
+ *---------------------------------------------------------------------*/
+void serial_putc (char c)
 {
 	if (c == '\n')
-		serial_putc('\r');
-	while( (uart->status & NIOS_UART_TRDY) == 0 )
+		serial_putc ('\r');
+	while ((uart->status & NIOS_UART_TRDY) == 0)
 		WATCHDOG_RESET ();
 	uart->txdata = (unsigned char)c;
 }

-void serial_puts( const char *s )
+void serial_puts (const char *s)
 {
-	while( *s != 0 ) {
-		serial_putc( *s++ );
+	while (*s != 0) {
+		serial_putc (*s++);
 	}
 }

-int serial_tstc( void )
+int serial_tstc (void)
 {
-	return( uart->status & NIOS_UART_RRDY);
+	return (uart->status & NIOS_UART_RRDY);
 }

-int serial_getc( void )
+int serial_getc (void)
 {
-	while( serial_tstc() == 0 )
+	while (serial_tstc () == 0)
 		WATCHDOG_RESET ();
 	return( uart->rxdata & 0x00ff );
 }
+
+#endif /* CONFIG_JTAG_CONSOLE */
--- a/cpu/nios/start.S
+++ b/cpu/nios/start.S
@@ -93,6 +93,14 @@ _start:
 	subi	%g6, 4			/* %g6 <- src addr */
 	ld	%g7, [%g7]		/* %g7 <- dst addr */

+	/* No need to move text sections if we're already located
+	 * at the proper address.
+	 */
+	cmp	%g7, %g6
+	ifs	cc_z
+	br	reloc
+	nop				/* delay slot */
+
 1:	cmp	%g7, %g5
 	skps	cc_nz
 	br	2f
@@ -114,6 +122,7 @@ _start:
 	 pfx	%xhi(reloc@h)
 	 movhi	%g0, %xlo(reloc@h)
 	 jmp	%g0
+	 nop				/* delay slot */
 reloc:

 	/*
@@ -140,6 +149,48 @@ reloc:
 	nop				/* delay slot */
 4:

+	/*
+	 * INIT VECTOR TABLE
+	 */
+	pfx	%hi(CFG_VECT_BASE)
+	movi	%g0, %lo(CFG_VECT_BASE)
+	pfx	%xhi(CFG_VECT_BASE)
+	movhi	%g0, %xlo(CFG_VECT_BASE)	/* dst */
+	mov	%l0, %g0
+
+	pfx	%hi(_vectors)
+	movi	%g1, %lo(_vectors)
+	pfx	%xhi(_vectors)
+	movhi	%g1, %xlo(_vectors)	/* src */
+	bgen	%g2, 6			/* cnt = 64 */
+
+	ldp	%g3, [%l0, 3]		/* bkpt vector */
+	ldp	%g4, [%l0, 4]		/* single step vector */
+
+5:	ld	%g7, [%g1]
+	addi	%g1, 4			/* src++ */
+	st	[%g0], %g7
+	addi	%g0, 4			/* dst++ */
+
+	subi	%g2, 1			/* cnt-- */
+	ifrnz	%g2
+	br	5b
+	nop				/* delay slot */
+
+#if defined(CONFIG_ROM_STUBS)
+	/* Restore the breakpoint and single step exception
+	 * vectors to their original values.
+	 */
+	stp	[%l0,3], %g3		/* breakpoint */
+	stp	[%l0,4], %g4		/* single step */
+#endif
+
+	/* For debug startup convenience ... software breakpoints
+	 * set prior to this point may not succeed ;-)
+	 */
+	.global __start
+__start:
+
 	/*
 	 * Call board_init -- never returns
 	 */
--- a/cpu/nios/traps.S
+++ b/cpu/nios/traps.S
@@ -557,3 +557,26 @@ _timebase_int:
 	mov	%fp, %sp

 	tret	%o7			/* Done */
+
+/*************************************************************************
+ * GDB stubs
+ ************************************************************************/
+	.text
+	.global _brkpt_hw_int, _brkpt_sw_int
+	.align	4
+
+_brkpt_hw_int:
+	movi	%l1, 9
+	pfx	3
+	wrctl	%l1
+	pfx	4
+	wrctl	%l1
+
+_brkpt_sw_int:
+	movi	%l1, 9
+	pfx	3
+	wrctl	%l1
+	pfx	4
+	wrctl	%l1
+
+	tret	%o7
--- a/cpu/ppc4xx/440gx_enet.c
+++ b/cpu/ppc4xx/440gx_enet.c
@@ -437,6 +437,22 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
 	 */
 	if ( ((devnum == 2) || (devnum ==3)) && (4 == ethgroup) ) {
 		miiphy_write (reg, 23, 0x1200);
+		/*
+		 * Vitesse VSC8201/Cicada CIS8201 errata:
+		 * Interoperability problem with Intel 82547EI phys
+		 * This work around (provided by Vitesse) changes
+		 * the default timer convergence from 8ms to 12ms
+		 */
+		miiphy_write (reg, 0x1f, 0x2a30);
+		miiphy_write (reg, 0x08, 0x0200);
+		miiphy_write (reg, 0x1f, 0x52b5);
+		miiphy_write (reg, 0x02, 0x0004);
+		miiphy_write (reg, 0x01, 0x0671);
+		miiphy_write (reg, 0x00, 0x8fae);
+		miiphy_write (reg, 0x1f, 0x2a30);
+		miiphy_write (reg, 0x08, 0x0000);
+		miiphy_write (reg, 0x1f, 0x0000);
+		/* end Vitesse/Cicada errata */
 	}
 #endif
 #endif
@@ -917,7 +933,7 @@ int enetInt (struct eth_device *dev)
 			mtdcr (uic0sr, UIC_MTE);
 		}
 		/* handle MAL RX EOB  interupt from a receive */
-		/* check for EOB on valid channels            */
+		/* check for EOB on valid channels	      */
 		if (my_uic0msr & UIC_MRE) {
 			mal_rx_eob = mfdcr (malrxeobisr);
 			if ((mal_rx_eob & (0x80000000 >> hw_p->devnum)) != 0) {	/* call emac routine for channel x */
@@ -1033,9 +1049,9 @@ static void enet_rcv (struct eth_device *dev, unsigned long malisr)
 						    MAX_ERR_LOG)
 							hw_p->rx_err_index =
 								0;
-					}	/* emac_erros         */
+					}	/* emac_erros */
 				}	/* data_len < max mtu */
-			}	/* if data_len        */
+			}	/* if data_len */
 			if (!data_len) {	/* no data */
 				hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY;	/* Free Recv Buffer */

--- a/doc/README.nios
+++ b/doc/README.nios
@@ -55,6 +55,12 @@ sources (when altera silicon is not involved). This isn't really
 a problem as little, if any, of the Altera source contains
 features that are not already available in U-Boot.

+1.3 Debugging via OCI
+---------------------
+The Nios port supports debugging with gdb and/or nios-console
+via the JTAG port. Stubs for debugging with gdb via the serial
+port are not currently implemented.
+

 2. CONFIGURATION OPTIONS/SETTINGS
 ----------------------------------
@@ -79,7 +85,11 @@ description).

 CONFIG_NIOS -- defined for all Nios-32 boards.

-CFG_NIOS_CONSOLE -- the base address of the console UART.
+CFG_NIOS_CONSOLE -- the base address of the console UART or the JTAG
+	stdio port. To enable a console via JTAG, define
+	CONFIG_CONSOLE_JTAG and set CGF_NIOS_CONSOLE to the base address
+	of the JTAG stdio port (normally OCI base + 0x00fa). Then
+	run nios-console with the -w option.
 	(standard-32: nasys_uart_0 resp. na_uart1_base).

 CFG_NIOS_FIXEDBAUD -- defined if the console UART PTF fixed_baud
@@ -176,20 +186,109 @@ GERMS monitor (that is, avoid running code stored in flash memory):
    3. Release CFG_NIOS_CPU_BUTTON_PIO, button number 0.


-5. BRAIN DAMAGE
+5. DEBUGGING WITH GDB
+---------------------
+
+Debug sessions using gdb are currently supported only via JTAG. The
+stubs for debugging via a serial port are not implemented. To enable
+the gdb JTAG stubs, simply reference _brkpt_hw_int and _brkpt_sw_int
+at vector table offsets 3 and 4, respectively. For an example, see
+board/altera/dk1c20/vectors.S.
+
+5.1 Vector Table Initialization and ROM Stubs
+---------------------------------------------
+If CONFIG_ROM_STUBS is defined, the debug breakpoint and single step
+entries in the vector table are restored to their initial values
+immediately _after_ initializing the vector table. Defining this macro
+is useful when ROM-based stubs are implemented.
+
+NOTE: The default GERMS monitor does NOT implement gdb stubs, nor does
+it initialize the vector table. Therefore, when debugging U-Boot, you
+should NOT set a software breakpoint prior to vector table initialization.
+
+5.2 Starting a Debug Session
+----------------------------
+If you're not familiar with gdb, you follow these step-by-step instructions.
+These instructions are NOT the only way to start a debug session, but they
+cover most of the individual functions to get you started.
+
+	1.  Start the JTAG gdb server. Open a Nios shell window and start
+	the server. When the server is started you must provide the base
+	address of the OCI core. For example, when using the Cyclone
+	development kit (DK1C20):
+
+		$ nios-gdb-server --ocibase=0x00920800 --tcpport=2342
+
+	2.  Start gdb. Open a Nios shell window, change to the top-level
+	U-Boot directory and start gdb, specifying the u-boot elf file:
+
+		$ nios-elf-gdb u-boot
+
+	3.  Update target settings. From the file menu, select
+	"Target Settings ..." and select the following, then click 'Ok':
+
+		Target:	Remote/TCP
+		Port :	2342   (same as in step 1)
+		Display download dialog: checked
+		All other check boxes: unchecked
+
+	4.  Connect to the target. Select menu: 'Run->Connect to target'.
+	You should see a dialog box indicating the you successfully connected
+	to the target.
+
+	5.  Download U-Boot. Select menu: 'Run->Download'.
+
+	6.  Open a gdb console window and set the source directory paths.
+	Select menu: 'View->Console'. In the console window, enter the
+	following commands, then close the console window:
+
+		(gdb) directory common
+		(gdb) directory cpu/nios
+		(gdb) directory lib_nios
+		(gdb) directory board/altera/dk1c20
+
+	Note that the last command is for the DK1C20 board only. If you
+	are using another board, specify that board's directory.
+
+	7.  Open the file board.c (using the file menu in the lower
+	left hand corner). Scroll to the board_init() routine and set
+	a breakpoint.
+
+	8. Run U-Boot. Just click on the run icon, or select menu:
+	'Run->Run'. U-Boot should start running, then break at your
+	breakpoint.
+
+	9.  Have fun & start learning more about gdb.
+
+
+5.3 For advanced Users
+----------------------
+A few notes for those more familiar with gdb.
+
+	-Serial port stubs are not implemented. Sorry, but it's just not
+	worth _my_ effort. The JTAG stubs work great and are ridiculously
+	simple to implement.
+
+	-If you need to debug the early startup code (prior to the vector
+	table initialization), use the nios-console debugger.
+
+	- Connect, download & run -- there are some problems here. Connect
+	download and run seperately to avoid trouble.
+
+6. BRAIN DAMAGE
 ----------------

 This section describes some of the unfortunate and avoidable aspects
 of working with the Nios CPU ... and some things you can do to
 reduce your pain.

-5.1 GERMS doesn't work with Hyperterminal
+6.1 GERMS doesn't work with Hyperterminal
 ------------------------------------------
 GERMS doesn't do CR/LF mapping that is compatible with Hyperterminal
 (or minicom) -- geez. Regardless of you opion of Hyperterminal, this
 sad design decision is remedied by using U-Boot.

-5.2 cygwin Incompatibility
+6.2 cygwin Incompatibility
 ---------------------------
 The version of cygwin distributed with the nios GNUPro toolchain is
 out-of-date and incompatible with the latest cygwin distributions.
@@ -202,7 +301,7 @@ topic).
 The solution ... well, you can wait for Altera ... or build as
 set of tools for linux.

-5.3 No native gcc
+6.3 No native gcc
 ------------------
 I'm not sure how this one slipped through the cracks ... but it is
 a real pain. Basically, if you want to build anything for the native
@@ -215,7 +314,7 @@ distro. Anybody who wants to use an already precompiled NIOS cross
 toolchain can it found in the CDK4NIOS project hosted by Source
 Forge at http://cdk4nios.sourceforge.net.

-5.4 Can't build default U-Boot
+6.4 Can't build default U-Boot
 -------------------------------
 By default, when you build U-Boot you will be building some native
 tools along with the target elf, bin, and srec files. Without a
@@ -232,15 +331,16 @@ environment.o: environment.c ../tools/envcrc
 		-c -o $@ environment.c

 With:
-environment.o: environment.c ../tools/envcrc
+environment.o: environment.c
 	$(CC) $(AFLAGS) -Wa,--no-warn \
 		-DENV_CRC=0 \
 		-c -o $@ environment.c

-BTW, thats a 'zero' ... not the letter 'O'.
+BTW, thats a 'zero' ... not the letter 'O'. And not that the
+"../tools/envcrc" dependency is removed.


-6. HELP WANTED
+7. HELP WANTED
 ---------------

 There are plenty of areas where help is needed. Here's are some ideas
--- a/drivers/ns8382x.c
+++ b/drivers/ns8382x.c
@@ -266,7 +266,7 @@ static int ns8382x_poll(struct eth_device *dev);
 static void ns8382x_disable(struct eth_device *dev);

 static struct pci_device_id supported[] = {
-	{PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_8382x},
+	{PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_83820},
 	{}
 };

--- a/drivers/sk98lin/skge.c
+++ b/drivers/sk98lin/skge.c
@@ -494,7 +494,7 @@ static struct proc_dir_entry	*pSkRootDir;
 static struct pci_device_id supported[] = {
 	{PCI_VENDOR_ID_3COM, 0x1700},
 	{PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE},
-	{PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE_SA},
+	{PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU},
 	{}
 };

--- a/drivers/sl811_usb.c
+++ b/drivers/sl811_usb.c
@@ -226,33 +226,50 @@ int usb_lowlevel_stop(void)
 	return 0;
 }

-int sl811_send_packet(int dir_to_host, int data1, __u8 *buffer, int len)
+static int calc_needed_buswidth(int bytes, int need_preamble)
+{
+	return !need_preamble ? bytes * 8 + 256 : 8 * 8 * bytes + 2048;
+}
+
+static int sl811_send_packet(struct usb_device *dev, unsigned long pipe, __u8 *buffer, int len)
 {
 	__u8 ctrl = SL811_USB_CTRL_ARM | SL811_USB_CTRL_ENABLE;
-	__u16 status;
-	int err = 0;
+	__u16 status = 0;
+	int err = 0, time_start = get_timer(0);
+	int need_preamble = !(rh_status.wPortStatus & USB_PORT_STAT_LOW_SPEED) &&
+		usb_pipeslow(pipe);

 	if (len > 239)
 		return -1;

-	if (!dir_to_host)
+	if (usb_pipeout(pipe))
 		ctrl |= SL811_USB_CTRL_DIR_OUT;
-	if (data1)
+	if (usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe)))
 		ctrl |= SL811_USB_CTRL_TOGGLE_1;
+	if (need_preamble)
+		ctrl |= SL811_USB_CTRL_PREAMBLE;

-	sl811_write(SL811_ADDR_A, 0x10);
-	sl811_write(SL811_LEN_A, len);
-	if (!dir_to_host && len)
-		sl811_write_buf(0x10, buffer, len);
+	sl811_write(SL811_INTRSTS, 0xff);

 	while (err < 3) {
-		if (sl811_read(SL811_SOFCNTDIV)*64 < len * 8 * 2)
+		sl811_write(SL811_ADDR_A, 0x10);
+		sl811_write(SL811_LEN_A, len);
+		if (usb_pipeout(pipe) && len)
+			sl811_write_buf(0x10, buffer, len);
+
+		if (!(rh_status.wPortStatus & USB_PORT_STAT_LOW_SPEED) &&
+		    sl811_read(SL811_SOFCNTDIV)*64 < calc_needed_buswidth(len, need_preamble))
 			ctrl |= SL811_USB_CTRL_SOF;
 		else
 			ctrl &= ~SL811_USB_CTRL_SOF;
+
 		sl811_write(SL811_CTRL_A, ctrl);
-		while (!(sl811_read(SL811_INTRSTS) & SL811_INTR_DONE_A))
-			; /* do nothing */
+ 		while (!(sl811_read(SL811_INTRSTS) & SL811_INTR_DONE_A)) {
+			if (5*CFG_HZ < get_timer(time_start)) {
+				printf("USB transmit timed out\n");
+				return -USB_ST_CRC_ERR;
+			}
+		}

 		sl811_write(SL811_INTRSTS, 0xff);
 		status = sl811_read(SL811_STS_A);
@@ -263,7 +280,7 @@ int sl811_send_packet(int dir_to_host, int data1, __u8 *buffer, int len)
 				PDEBUG(0, "usb transfer remainder = %d\n", remainder);
 				len -= remainder;
 			}
-			if (dir_to_host && len)
+			if (usb_pipein(pipe) && len)
 				sl811_read_buf(0x10, buffer, len);
 			return len;
 		}
@@ -275,7 +292,16 @@ int sl811_send_packet(int dir_to_host, int data1, __u8 *buffer, int len)
 		err++;
 	}

-	return -1;
+	err = 0;
+
+	if (status & SL811_USB_STS_ERROR)
+		err |= USB_ST_BUF_ERR;
+	if (status & SL811_USB_STS_TIMEOUT)
+		err |= USB_ST_CRC_ERR;
+	if (status & SL811_USB_STS_STALL)
+		err |= USB_ST_STALLED;
+
+	return -err;
 }

 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
@@ -283,7 +309,6 @@ int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
 {
 	int dir_out = usb_pipeout(pipe);
 	int ep = usb_pipeendpoint(pipe);
-	__u8* buf = (__u8*)buffer;
 	int max = usb_maxpacket(dev, pipe);
 	int done = 0;

@@ -295,11 +320,10 @@ int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
 	sl811_write(SL811_DEV_A, usb_pipedevice(pipe));
 	sl811_write(SL811_PIDEP_A, PIDEP(!dir_out ? USB_PID_IN : USB_PID_OUT, ep));
 	while (done < len) {
-		int res = sl811_send_packet(!dir_out, usb_gettoggle(dev, ep, dir_out),
-					    buf+done,
+		int res = sl811_send_packet(dev, pipe, (__u8*)buffer+done,
 					    max > len - done ? len - done : max);
 		if (res < 0) {
-			dev->status = res;
+			dev->status = -res;
 			return res;
 		}

@@ -320,45 +344,52 @@ int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
 {
 	int done = 0;
 	int devnum = usb_pipedevice(pipe);
+	int ep = usb_pipeendpoint(pipe);

 	dev->status = 0;

 	if (devnum == root_hub_devnum)
 		return sl811_rh_submit_urb(dev, pipe, buffer, len, setup);

-	PDEBUG(7, "dev = %d pipe = %ld buf = %p size = %d rt = %#x req = %#x\n",
-	       devnum, usb_pipeendpoint(pipe), buffer, len, (int)setup->requesttype,
-	       (int)setup->request);
+	PDEBUG(7, "dev = %d pipe = %ld buf = %p size = %d rt = %#x req = %#x bus = %i\n",
+	       devnum, ep, buffer, len, (int)setup->requesttype,
+	       (int)setup->request, sl811_read(SL811_SOFCNTDIV)*64);

 	sl811_write(SL811_DEV_A, devnum);
-	sl811_write(SL811_PIDEP_A, PIDEP(USB_PID_SETUP, 0));
+	sl811_write(SL811_PIDEP_A, PIDEP(USB_PID_SETUP, ep));
 	/* setup phase */
-	if (sl811_send_packet(0, 0, (__u8*)setup, sizeof(*setup)) == sizeof(*setup)) {
-		int dir_in = setup->requesttype & USB_DIR_IN;
-		__u8* buf = (__u8*)buffer;
-		int data1 = 1;
+	usb_settoggle(dev, ep, 1, 0);
+	if (sl811_send_packet(dev, usb_sndctrlpipe(dev, ep),
+			      (__u8*)setup, sizeof(*setup)) == sizeof(*setup)) {
+		int dir_in = usb_pipein(pipe);
 		int max = usb_maxpacket(dev, pipe);

 		/* data phase */
 		sl811_write(SL811_PIDEP_A,
-			    PIDEP(dir_in ? USB_PID_IN : USB_PID_OUT, 0));
+			    PIDEP(dir_in ? USB_PID_IN : USB_PID_OUT, ep));
+		usb_settoggle(dev, ep, usb_pipeout(pipe), 1);
 		while (done < len) {
-			int res = sl811_send_packet(dir_in, data1, buf+done,
+			int res = sl811_send_packet(dev, pipe, (__u8*)buffer+done,
 						    max > len - done ? len - done : max);
-			if (res < 0)
-				return res;
+			if (res < 0) {
+				PDEBUG(0, "status data failed!\n");
+				dev->status = -res;
+				return 0;
+			}
 			done += res;
-
+			usb_dotoggle(dev, ep, usb_pipeout(pipe));
 			if (dir_in && res < max) /* short packet */
 				break;
-
-			data1 = !data1;
 		}

 		/* status phase */
 		sl811_write(SL811_PIDEP_A,
-			    PIDEP(!dir_in ? USB_PID_IN : USB_PID_OUT, 0));
-		if (sl811_send_packet(!dir_in, 1, 0, 0) < 0) {
+			    PIDEP(!dir_in ? USB_PID_IN : USB_PID_OUT, ep));
+		usb_settoggle(dev, ep, !usb_pipeout(pipe), 1);
+		if (sl811_send_packet(dev,
+				      !dir_in ? usb_rcvctrlpipe(dev, ep) :
+				      usb_sndctrlpipe(dev, ep),
+				      0, 0) < 0) {
 			PDEBUG(0, "status phase failed!\n");
 			dev->status = -1;
 		}
@@ -375,7 +406,7 @@ int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
 int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
 		   int len, int interval)
 {
-	PDEBUG(7, "dev = %p pipe = %#lx buf = %p size = %d int = %d\n", dev, pipe,
+	PDEBUG(0, "dev = %p pipe = %#lx buf = %p size = %d int = %d\n", dev, pipe,
 	       buffer, len, interval);
 	return -1;
 }
@@ -476,7 +507,7 @@ static int ascii2utf (char *s, u8 *utf, int utfmax)
 * root_hub_string is used by each host controller's root hub code,
 * so that they're identified consistently throughout the system.
 */
-int usb_root_hub_string (int id, int serial, char *type, __u8 *data, int len)
+static int usb_root_hub_string (int id, int serial, char *type, __u8 *data, int len)
 {
 	char buf [30];

@@ -491,7 +522,7 @@ int usb_root_hub_string (int id, int serial, char *type, __u8 *data, int len)

 	/* serial number */
 	} else if (id == 1) {
-		sprintf (buf, "%x", serial);
+		sprintf (buf, "%#x", serial);

 	/* product description */
 	} else if (id == 2) {
@@ -503,7 +534,8 @@ int usb_root_hub_string (int id, int serial, char *type, __u8 *data, int len)
 	} else
 	    return 0;

-	data [0] = 2 + ascii2utf (buf, data + 2, len - 2);
+	ascii2utf (buf, data + 2, len - 2);
+	data [0] = 2 + strlen(buf) * 2;
 	data [1] = 3;
 	return data [0];
 }
--- a/examples/Makefile
+++ b/examples/Makefile
@@ -38,7 +38,7 @@ LOAD_ADDR = 0x80200000 -T mips.lds
 endif

 ifeq ($(ARCH),nios)
-LOAD_ADDR = 0x01000000 -L $(gcclibdir)/m32 -T nios.lds
+LOAD_ADDR = 0x00800000 -L $(gcclibdir)/m32 -T nios.lds
 endif

 ifeq ($(ARCH),m68k)
--- a/fs/jffs2/jffs2_1pass.c
+++ b/fs/jffs2/jffs2_1pass.c
@@ -217,7 +217,8 @@ static void *get_fl_mem(u32 off, u32 size, void *ext_buf)
 		return NULL;
 	}
 	if (read_nand_cached(off, size, buf) < 0) {
-		free(buf);
+		if (!ext_buf)
+			free(buf);
 		return NULL;
 	}

@@ -756,9 +757,11 @@ jffs2_1pass_list_inodes(struct b_lists * pL, u32 pino)
 			while (b2) {
 				jNode = (struct jffs2_raw_inode *)
 					get_fl_mem(b2->offset, sizeof(ojNode), &ojNode);
-				if (jNode->ino == jDir->ino
-				    && jNode->version >= i_version)
+				if (jNode->ino == jDir->ino && jNode->version >= i_version) {
+					if (i)
+						put_fl_mem(i);
 					i = get_fl_mem(b2->offset, sizeof(*i), NULL);
+				}
 				b2 = b2->next;
 			}

@@ -874,7 +877,7 @@ jffs2_1pass_resolve_inode(struct b_lists * pL, u32 ino)
 	while (b2) {
 		jNode = (struct jffs2_raw_inode *) get_node_mem(b2->offset);
 		if (jNode->ino == jDirFoundIno) {
-			src = (unsigned char *) (b2->offset + sizeof(struct jffs2_raw_inode));
+			src = (unsigned char *)jNode + sizeof(struct jffs2_raw_inode);

 #if 0
 			putLabeledWord("\t\t dsize = ", jNode->dsize);
--- a/include/common.h
+++ b/include/common.h
@@ -372,6 +372,7 @@ int	serial_tstc   (void);
 int	get_clocks (void);
 int	get_clocks_866 (void);
 int	sdram_adjust_866 (void);
+int	adjust_sdram_tbs_8xx (void);
 #if defined(CONFIG_8260)
 int	prt_8260_clks (void);
 #endif
--- a/include/configs/CATcenter.h
+++ b/include/configs/CATcenter.h
@@ -0,0 +1,703 @@
+/*
+ * (C) Copyright 2004 DENX Software Engineering,
+ *     Wolfgang Grandegger <wg@denx.de>
+ * (C) Copyright 2003
+ *     DAVE Srl
+ *
+ * http://www.dave-tech.it
+ * http://www.wawnet.biz
+ * mailto:info@wawnet.biz
+ *
+ * Credits: Stefan Roese, Wolfgang Denk
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_PPCHAMELEON_MODULE_BA	0	/* Basic    Model */
+#define CONFIG_PPCHAMELEON_MODULE_ME	1	/* Medium   Model */
+#define CONFIG_PPCHAMELEON_MODULE_HI	2	/* High-End Model */
+#ifndef CONFIG_PPCHAMELEON_MODULE_MODEL
+#define CONFIG_PPCHAMELEON_MODULE_MODEL CONFIG_PPCHAMELEON_MODULE_BA
+#endif
+
+/*
+ * Debug stuff
+ */
+#undef	__DEBUG_START_FROM_SRAM__
+#define __DISABLE_MACHINE_EXCEPTION__
+
+#ifdef __DEBUG_START_FROM_SRAM__
+#define CFG_DUMMY_FLASH_SIZE		1024*1024*4
+#endif
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
+#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
+#define CONFIG_PPCHAMELEONEVB	1	/* ...on a PPChameleonEVB board */
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
+#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
+
+#define CONFIG_SYS_CLK_FREQ	33333333 /* external frequency to pll	*/
+
+#define CONFIG_UART1_CONSOLE	1	/* Use second UART	*/
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#undef	CONFIG_BOOTARGS
+
+/* Ethernet stuff */
+#define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */
+#define CONFIG_ETHADDR	00:50:C2:1E:AF:FC
+#define CONFIG_ETH1ADDR 00:50:C2:1E:AF:FB
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+
+#undef CONFIG_EXT_PHY
+
+#define CONFIG_MII		1	/* MII PHY management		*/
+#ifndef	 CONFIG_EXT_PHY
+#define CONFIG_PHY_ADDR		1	/* PHY address			*/
+#else
+#define CONFIG_PHY_ADDR		2	/* PHY address			*/
+#endif
+#define CONFIG_PHY_CLK_FREQ	EMAC_STACR_CLK_66MHZ
+
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_EEPROM	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_IRQ	| \
+				CFG_CMD_MII	| \
+				CFG_CMD_NAND	| \
+				CFG_CMD_JFFS2)
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_RTC_MC146818		/* DS1685 is MC146818 compatible*/
+#define CFG_RTC_REG_BASE_ADDR	 0xF0000500 /* RTC Base Address		*/
+
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
+
+#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
+#ifdef	CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2	"> "
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
+
+#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#undef	CFG_EXT_SERIAL_CLOCK		/* no external serial clock used */
+#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
+#define CFG_BASE_BAUD		691200
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE	\
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
+
+#define CFG_LOAD_ADDR	0x100000	/* default load address */
+#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+
+/*-----------------------------------------------------------------------
+ * NAND-FLASH stuff
+ *-----------------------------------------------------------------------
+ */
+#define CFG_NAND0_BASE 0xFF400000
+#define CFG_NAND1_BASE 0xFF000000
+
+/* For CATcenter there is only NAND on the module */
+#define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/
+#define SECTORSIZE 512
+#define NAND_NO_RB
+
+#define ADDR_COLUMN 1
+#define ADDR_PAGE 2
+#define ADDR_COLUMN_PAGE 3
+
+#define NAND_ChipID_UNKNOWN	0x00
+#define NAND_MAX_FLOORS 1
+#define NAND_MAX_CHIPS 1
+
+#define CFG_NAND0_CE  (0x80000000 >> 1)	 /* our CE is GPIO1 */
+#define CFG_NAND0_CLE (0x80000000 >> 2)	 /* our CLE is GPIO2 */
+#define CFG_NAND0_ALE (0x80000000 >> 3)	 /* our ALE is GPIO3 */
+#define CFG_NAND0_RDY (0x80000000 >> 4)	 /* our RDY is GPIO4 */
+
+#define CFG_NAND1_CE  (0x80000000 >> 14)  /* our CE is GPIO14 */
+#define CFG_NAND1_CLE (0x80000000 >> 15)  /* our CLE is GPIO15 */
+#define CFG_NAND1_ALE (0x80000000 >> 16)  /* our ALE is GPIO16 */
+#define CFG_NAND1_RDY (0x80000000 >> 31)  /* our RDY is GPIO31 */
+
+
+#define NAND_DISABLE_CE(nand) do \
+{ \
+	switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \
+	{ \
+	    case CFG_NAND0_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CE); \
+		break; \
+	    case CFG_NAND1_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CE); \
+		break; \
+	} \
+} while(0)
+
+#define NAND_ENABLE_CE(nand) do \
+{ \
+	switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \
+	{ \
+	    case CFG_NAND0_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CE); \
+		break; \
+	    case CFG_NAND1_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CE); \
+		break; \
+	} \
+} while(0)
+
+
+#define NAND_CTL_CLRALE(nandptr) do \
+{ \
+	switch((unsigned long)nandptr) \
+	{ \
+	    case CFG_NAND0_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_ALE); \
+		break; \
+	    case CFG_NAND1_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_ALE); \
+		break; \
+	} \
+} while(0)
+
+#define NAND_CTL_SETALE(nandptr) do \
+{ \
+	switch((unsigned long)nandptr) \
+	{ \
+	    case CFG_NAND0_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_ALE); \
+		break; \
+	    case CFG_NAND1_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_ALE); \
+		break; \
+	} \
+} while(0)
+
+#define NAND_CTL_CLRCLE(nandptr) do \
+{ \
+	switch((unsigned long)nandptr) \
+	{ \
+	    case CFG_NAND0_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CLE); \
+		break; \
+	    case CFG_NAND1_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CLE); \
+		break; \
+	} \
+} while(0)
+
+#define NAND_CTL_SETCLE(nandptr) do { \
+	switch((unsigned long)nandptr) { \
+	case CFG_NAND0_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CLE); \
+		break; \
+	case CFG_NAND1_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CLE); \
+		break; \
+	} \
+} while(0)
+
+#ifdef NAND_NO_RB
+/* constant delay (see also tR in the datasheet) */
+#define NAND_WAIT_READY(nand) do { \
+	udelay(12); \
+} while (0)
+#else
+/* use the R/B pin */
+/* TBD */
+#endif
+
+#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
+#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
+#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
+#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#if 0	/* No PCI on CATcenter */
+#define PCI_HOST_ADAPTER 0		/* configure as pci adapter	*/
+#define PCI_HOST_FORCE	1		/* configure as pci host	*/
+#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
+
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_HOST PCI_HOST_FORCE	 /* select pci host function	 */
+#undef	CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+					/* resource configuration	*/
+
+#define CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
+
+#define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
+#define CFG_PCI_SUBSYS_DEVICEID 0x0405	/* PCI Device ID: CPCI-405	*/
+#define CFG_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
+#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CFG_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
+#define CFG_PCI_PTM2LA	0xffc00000	/* point to flash		*/
+#define CFG_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
+#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
+#endif	/* No PCI */
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0xFFFC0000
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
+
+#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+/*
+ * The following defines are added for buggy IOP480 byte interface.
+ * All other boards should use the standard values (CPCI405 etc.)
+ */
+#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
+
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+#if 0 /* test-only */
+#define CFG_JFFS2_FIRST_BANK	0	/* use for JFFS2			*/
+#define CFG_JFFS2_NUM_BANKS	1	/* ! second bank contains U-Boot	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * Environment Variable setup
+ */
+#define CFG_ENV_IS_IN_FLASH	1	/* use FLASH for environment vars */
+#define CFG_ENV_ADDR		0xFFFF8000	/* environment starts at the first small sector */
+#define CFG_ENV_SECT_SIZE	0x2000	/* 8196 bytes may be used for env vars*/
+#define CFG_ENV_ADDR_REDUND	0xFFFFA000
+#define CFG_ENV_SIZE_REDUND	0x2000
+
+#define CFG_NVRAM_BASE_ADDR	0xF0000500		/* NVRAM base address	*/
+#define CFG_NVRAM_SIZE		242			/* NVRAM size		*/
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (CAT24WC16) for environment
+ */
+#define CONFIG_HARD_I2C			/* I2c with hardware support */
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CFG_I2C_SLAVE		0x7F
+
+#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
+#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
+/*#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07*/
+#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+					/* 16 byte page write mode using*/
+					/* last 4 bits of the address	*/
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		16384	/* For IBM 405 CPUs, older 405 ppc's	*/
+					/* have only 8kB, 16kB is save here	*/
+#define CFG_CACHELINE_SIZE	32	/* ...			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0xFFC00000	/* FLASH bank #0	*/
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
+#define CFG_EBC_PB0AP		0x92015480
+#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 1 (External SRAM) initialization					*/
+/* Since this must replace NOR Flash, we use the same settings for CS0		*/
+#define CFG_EBC_PB1AP		0x92015480
+#define CFG_EBC_PB1CR		0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 2 (Flash Bank 1, NAND-FLASH) initialization			*/
+#define CFG_EBC_PB2AP		0x92015480
+#define CFG_EBC_PB2CR		0xFF458000  /* BAS=0xFF4,BS=4MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 3 (Flash Bank 2, NAND-FLASH) initialization			*/
+#define CFG_EBC_PB3AP		0x92015480
+#define CFG_EBC_PB3CR		0xFF058000  /* BAS=0xFF0,BS=4MB,BU=R/W,BW=8bit	*/
+
+
+#if 0 /* Roese */
+/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization			*/
+#define CFG_EBC_PB1AP		0x92015480
+#define CFG_EBC_PB1CR		0xFF858000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 2 (CAN0, 1) initialization					*/
+#define CFG_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 3 (CompactFlash IDE) initialization				*/
+#define CFG_EBC_PB3AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB3CR		0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 4 (NVRAM/RTC) initialization					*/
+#define CFG_EBC_PB4AP		0x01005280  /* TWT=2,WBN=1,WBF=1,TH=1,SOR=1	*/
+#define CFG_EBC_PB4CR		0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * FPGA stuff
+ */
+/* FPGA internal regs */
+#define CFG_FPGA_MODE		0x00
+#define CFG_FPGA_STATUS		0x02
+#define CFG_FPGA_TS		0x04
+#define CFG_FPGA_TS_LOW		0x06
+#define CFG_FPGA_TS_CAP0	0x10
+#define CFG_FPGA_TS_CAP0_LOW	0x12
+#define CFG_FPGA_TS_CAP1	0x14
+#define CFG_FPGA_TS_CAP1_LOW	0x16
+#define CFG_FPGA_TS_CAP2	0x18
+#define CFG_FPGA_TS_CAP2_LOW	0x1a
+#define CFG_FPGA_TS_CAP3	0x1c
+#define CFG_FPGA_TS_CAP3_LOW	0x1e
+
+/* FPGA Mode Reg */
+#define CFG_FPGA_MODE_CF_RESET	0x0001
+#define CFG_FPGA_MODE_TS_IRQ_ENABLE 0x0100
+#define CFG_FPGA_MODE_TS_IRQ_CLEAR  0x1000
+#define CFG_FPGA_MODE_TS_CLEAR	0x2000
+
+/* FPGA Status Reg */
+#define CFG_FPGA_STATUS_DIP0	0x0001
+#define CFG_FPGA_STATUS_DIP1	0x0002
+#define CFG_FPGA_STATUS_DIP2	0x0004
+#define CFG_FPGA_STATUS_FLASH	0x0008
+#define CFG_FPGA_STATUS_TS_IRQ	0x1000
+
+#define CFG_FPGA_SPARTAN2	1		/* using Xilinx Spartan 2 now	*/
+#define CFG_FPGA_MAX_SIZE	128*1024	/* 128kByte is enough for XC2S50E*/
+
+/* FPGA program pin configuration */
+#define CFG_FPGA_PRG		0x04000000	/* FPGA program pin (ppc output) */
+#define CFG_FPGA_CLK		0x02000000	/* FPGA clk pin (ppc output)	*/
+#define CFG_FPGA_DATA		0x01000000	/* FPGA data pin (ppc output)	*/
+#define CFG_FPGA_INIT		0x00010000	/* FPGA init pin (ppc input)	*/
+#define CFG_FPGA_DONE		0x00008000	/* FPGA done pin (ppc input)	*/
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
+#define CFG_TEMP_STACK_OCM	  1
+
+/* On Chip Memory location */
+#define CFG_OCM_DATA_ADDR	0xF8000000
+#define CFG_OCM_DATA_SIZE	0x1000
+#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
+
+#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Definitions for GPIO setup (PPC405EP specific)
+ *
+ * GPIO0[0]	- External Bus Controller BLAST output
+ * GPIO0[1-9]	- Instruction trace outputs -> GPIO
+ * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
+ * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
+ * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
+ * GPIO0[24-27] - UART0 control signal inputs/outputs
+ * GPIO0[28-29] - UART1 data signal input/output
+ * GPIO0[30]	- EMAC0 input
+ * GPIO0[31]	- EMAC1 reject packet as output
+ */
+#define CFG_GPIO0_OSRH		0x40000550
+#define CFG_GPIO0_OSRL		0x00000110
+#define CFG_GPIO0_ISR1H		0x00000000
+/*#define CFG_GPIO0_ISR1L	0x15555445*/
+#define CFG_GPIO0_ISR1L		0x15555444
+#define CFG_GPIO0_TSRH		0x00000000
+#define CFG_GPIO0_TSRL		0x00000000
+#define CFG_GPIO0_TCR		0xF7FF8014
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+
+#define CONFIG_NO_SERIAL_EEPROM
+
+/*--------------------------------------------------------------------*/
+
+#ifdef CONFIG_NO_SERIAL_EEPROM
+
+/*
+!-----------------------------------------------------------------------
+! Defines for entry options.
+! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that
+!	are plugged in the board will be utilized as non-ECC DIMMs.
+!-----------------------------------------------------------------------
+*/
+#undef		AUTO_MEMORY_CONFIG
+#define		DIMM_READ_ADDR 0xAB
+#define		DIMM_WRITE_ADDR 0xAA
+
+
+#define CPC0_PLLMR0  (CNTRL_DCR_BASE+0x0)  /* PLL mode 0 register		*/
+#define CPC0_BOOT    (CNTRL_DCR_BASE+0x1)  /* Chip Clock Status register	*/
+#define CPC0_CR1     (CNTRL_DCR_BASE+0x2)  /* Chip Control 1 register		*/
+#define CPC0_EPRCSR  (CNTRL_DCR_BASE+0x3)  /* EMAC PHY Rcv Clk Src register	*/
+#define CPC0_PLLMR1  (CNTRL_DCR_BASE+0x4)  /* PLL mode 1 register		*/
+#define CPC0_UCR     (CNTRL_DCR_BASE+0x5)  /* UART Control register		*/
+#define CPC0_SRR     (CNTRL_DCR_BASE+0x6)  /* Soft Reset register		*/
+#define CPC0_JTAGID  (CNTRL_DCR_BASE+0x7)  /* JTAG ID register			*/
+#define CPC0_SPARE   (CNTRL_DCR_BASE+0x8)  /* Spare DCR				*/
+#define CPC0_PCI     (CNTRL_DCR_BASE+0x9)  /* PCI Control register		*/
+
+/* Defines for CPC0_PLLMR1 Register fields */
+#define PLL_ACTIVE		0x80000000
+#define CPC0_PLLMR1_SSCS	0x80000000
+#define PLL_RESET		0x40000000
+#define CPC0_PLLMR1_PLLR	0x40000000
+    /* Feedback multiplier */
+#define PLL_FBKDIV		0x00F00000
+#define CPC0_PLLMR1_FBDV	0x00F00000
+#define PLL_FBKDIV_16		0x00000000
+#define PLL_FBKDIV_1		0x00100000
+#define PLL_FBKDIV_2		0x00200000
+#define PLL_FBKDIV_3		0x00300000
+#define PLL_FBKDIV_4		0x00400000
+#define PLL_FBKDIV_5		0x00500000
+#define PLL_FBKDIV_6		0x00600000
+#define PLL_FBKDIV_7		0x00700000
+#define PLL_FBKDIV_8		0x00800000
+#define PLL_FBKDIV_9		0x00900000
+#define PLL_FBKDIV_10		0x00A00000
+#define PLL_FBKDIV_11		0x00B00000
+#define PLL_FBKDIV_12		0x00C00000
+#define PLL_FBKDIV_13		0x00D00000
+#define PLL_FBKDIV_14		0x00E00000
+#define PLL_FBKDIV_15		0x00F00000
+    /* Forward A divisor */
+#define PLL_FWDDIVA		0x00070000
+#define CPC0_PLLMR1_FWDVA	0x00070000
+#define PLL_FWDDIVA_8		0x00000000
+#define PLL_FWDDIVA_7		0x00010000
+#define PLL_FWDDIVA_6		0x00020000
+#define PLL_FWDDIVA_5		0x00030000
+#define PLL_FWDDIVA_4		0x00040000
+#define PLL_FWDDIVA_3		0x00050000
+#define PLL_FWDDIVA_2		0x00060000
+#define PLL_FWDDIVA_1		0x00070000
+    /* Forward B divisor */
+#define PLL_FWDDIVB		0x00007000
+#define CPC0_PLLMR1_FWDVB	0x00007000
+#define PLL_FWDDIVB_8		0x00000000
+#define PLL_FWDDIVB_7		0x00001000
+#define PLL_FWDDIVB_6		0x00002000
+#define PLL_FWDDIVB_5		0x00003000
+#define PLL_FWDDIVB_4		0x00004000
+#define PLL_FWDDIVB_3		0x00005000
+#define PLL_FWDDIVB_2		0x00006000
+#define PLL_FWDDIVB_1		0x00007000
+    /* PLL tune bits */
+#define PLL_TUNE_MASK		0x000003FF
+#define PLL_TUNE_2_M_3		0x00000133	/*  2 <= M <= 3			*/
+#define PLL_TUNE_4_M_6		0x00000134	/*  3 <	 M <= 6			*/
+#define PLL_TUNE_7_M_10		0x00000138	/*  6 <	 M <= 10		*/
+#define PLL_TUNE_11_M_14	0x0000013C	/* 10 <	 M <= 14		*/
+#define PLL_TUNE_15_M_40	0x0000023E	/* 14 <	 M <= 40		*/
+#define PLL_TUNE_VCO_LOW	0x00000000	/* 500MHz <= VCO <=  800MHz	*/
+#define PLL_TUNE_VCO_HI		0x00000080	/* 800MHz <  VCO <= 1000MHz	*/
+
+/* Defines for CPC0_PLLMR0 Register fields */
+    /* CPU divisor */
+#define PLL_CPUDIV		0x00300000
+#define CPC0_PLLMR0_CCDV	0x00300000
+#define PLL_CPUDIV_1		0x00000000
+#define PLL_CPUDIV_2		0x00100000
+#define PLL_CPUDIV_3		0x00200000
+#define PLL_CPUDIV_4		0x00300000
+    /* PLB divisor */
+#define PLL_PLBDIV		0x00030000
+#define CPC0_PLLMR0_CBDV	0x00030000
+#define PLL_PLBDIV_1		0x00000000
+#define PLL_PLBDIV_2		0x00010000
+#define PLL_PLBDIV_3		0x00020000
+#define PLL_PLBDIV_4		0x00030000
+    /* OPB divisor */
+#define PLL_OPBDIV		0x00003000
+#define CPC0_PLLMR0_OPDV	0x00003000
+#define PLL_OPBDIV_1		0x00000000
+#define PLL_OPBDIV_2		0x00001000
+#define PLL_OPBDIV_3		0x00002000
+#define PLL_OPBDIV_4		0x00003000
+    /* EBC divisor */
+#define PLL_EXTBUSDIV		0x00000300
+#define CPC0_PLLMR0_EPDV	0x00000300
+#define PLL_EXTBUSDIV_2		0x00000000
+#define PLL_EXTBUSDIV_3		0x00000100
+#define PLL_EXTBUSDIV_4		0x00000200
+#define PLL_EXTBUSDIV_5		0x00000300
+    /* MAL divisor */
+#define PLL_MALDIV		0x00000030
+#define CPC0_PLLMR0_MPDV	0x00000030
+#define PLL_MALDIV_1		0x00000000
+#define PLL_MALDIV_2		0x00000010
+#define PLL_MALDIV_3		0x00000020
+#define PLL_MALDIV_4		0x00000030
+    /* PCI divisor */
+#define PLL_PCIDIV		0x00000003
+#define CPC0_PLLMR0_PPFD	0x00000003
+#define PLL_PCIDIV_1		0x00000000
+#define PLL_PCIDIV_2		0x00000001
+#define PLL_PCIDIV_3		0x00000002
+#define PLL_PCIDIV_4		0x00000003
+
+/* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 33.3MHz input clock to the 405EP) */
+#define PLLMR0_133_133_33_66_33	 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
+				  PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
+				  PLL_MALDIV_1 | PLL_PCIDIV_4)
+#define PLLMR1_133_133_33_66_33	 (PLL_FBKDIV_4	|  \
+				  PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \
+				  PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+#define PLLMR0_200_100_50_33	 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
+				  PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
+				  PLL_MALDIV_1 | PLL_PCIDIV_4)
+#define PLLMR1_200_100_50_33	 (PLL_FBKDIV_6	| \
+				  PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
+				  PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+#define PLLMR0_266_133_33_66_33	 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
+				  PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
+				  PLL_MALDIV_1 | PLL_PCIDIV_4)
+#define PLLMR1_266_133_33_66_33	 (PLL_FBKDIV_8	| \
+				  PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
+				  PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+#define PLLMR0_333_111_37_55_55	 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
+				  PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
+				  PLL_MALDIV_1 | PLL_PCIDIV_2)
+#define PLLMR1_333_111_37_55_55	 (PLL_FBKDIV_10 | \
+				  PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
+				  PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
+
+#if   (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI)
+/* Model HI */
+#define PLLMR0_DEFAULT		PLLMR0_333_111_37_55_55
+#define PLLMR1_DEFAULT		PLLMR1_333_111_37_55_55
+/* Model ME */
+#elif (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME)
+#define PLLMR0_DEFAULT		PLLMR0_266_133_33_66_33
+#define PLLMR1_DEFAULT		PLLMR1_266_133_33_66_33
+#else
+/* Model BA (default) */
+#define PLLMR0_DEFAULT		PLLMR0_133_133_33_66_33
+#define PLLMR1_DEFAULT		PLLMR1_133_133_33_66_33
+#endif
+
+#endif /* CONFIG_NO_SERIAL_EEPROM */
+
+#define CONFIG_JFFS2_NAND 1			/* jffs2 on nand support */
+#define CONFIG_JFFS2_NAND_DEV 0			/* nand device jffs2 lives on */
+#define CONFIG_JFFS2_NAND_OFF 0			/* start of jffs2 partition */
+#define CONFIG_JFFS2_NAND_SIZE 2*1024*1024	/* size of jffs2 partition */
+#define NAND_CACHE_PAGES 16			/* size of nand cache in 512 bytes pages */
+
+#endif	/* __CONFIG_H */
--- a/include/configs/DK1C20.h
+++ b/include/configs/DK1C20.h
@@ -471,6 +471,7 @@
 				 CFG_CMD_MII	| \
 				 CFG_CMD_PCI	| \
 				 CFG_CMD_PCMCIA | \
+				 CFG_CMD_REISER	| \
 				 CFG_CMD_SCSI	| \
 				 CFG_CMD_SPI	| \
 				 CFG_CMD_VFD	| \
--- a/include/configs/KUP4K.h
+++ b/include/configs/KUP4K.h
@@ -72,8 +72,8 @@
 "contrast=55\0"									\
 "silent=1\0"									\
 "load=tftp 200000 bootloader-4k.bitmap;tftp 100000 bootloader-4k.bin\0"		\
-"update=protect off 1:0-5;era 1:0-5;cp.b 100000 40000000 $(filesize);"		\
- "cp.b 200000 40040000 14000\0"
+"update=protect off 1:0-7;era 1:0-7;cp.b 100000 40000000 $(filesize);"		\
+ "cp.b 200000 40050000 14000\0"

 #define CONFIG_BOOTCOMMAND  \
    "run slot_a_boot;run slot_b_boot;run nfs_boot;run panic_boot"
@@ -85,7 +85,7 @@
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
 #undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/

-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+#define	CONFIG_WATCHDOG	1		/* watchdog enabled		*/

 #define CONFIG_STATUS_LED	1	/* Status LED enabled		*/

@@ -96,23 +96,81 @@
 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION

-#define CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/

-#define CONFIG_HARD_I2C
-#define CFG_I2C_SPEED	40000
-#define CFG_I2C_SLAVE	0x7F
+/*
+ * enable I2C and select the hardware/software driver
+ */
+#undef	CONFIG_HARD_I2C			/* I2C with hardware support	*/
+#define	CONFIG_SOFT_I2C         1	/* I2C bit-banged		*/

-#define CONFIG_ETHADDR			00:0B:64:00:00:00 /* our OUI from IEEE */
-#define CONFIG_KUP4K_LOGO		0x40040000  /* Address of logo bitmap */
+#define CFG_I2C_SPEED		93000	/* 93 kHz is supposed to work	*/
+#define CFG_I2C_SLAVE		0xFE
+
+#ifdef CONFIG_SOFT_I2C
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define PB_SCL		0x00000020	/* PB 26 */
+#define PB_SDA		0x00000010	/* PB 27 */
+
+#define I2C_INIT	(immr->im_cpm.cp_pbdir |=  PB_SCL)
+#define I2C_ACTIVE	(immr->im_cpm.cp_pbdir |=  PB_SDA)
+#define I2C_TRISTATE	(immr->im_cpm.cp_pbdir &= ~PB_SDA)
+#define I2C_READ	((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
+#define I2C_SDA(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
+			else    immr->im_cpm.cp_pbdat &= ~PB_SDA
+#define I2C_SCL(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
+			else    immr->im_cpm.cp_pbdat &= ~PB_SCL
+#define I2C_DELAY	udelay(2)	/* 1/4 I2C clock duration */
+#endif	/* CONFIG_SOFT_I2C */
+
+
+/*-----------------------------------------------------------------------
+ * I2C Configuration
+ */
+
+#define CFG_I2C_PICIO_ADDR	0x21	/* PCF8574 IO Expander			*/
+#define CFG_I2C_RTC_ADDR	0x51	/* PCF8563 RTC				*/
+
+
+/* List of I2C addresses to be verified by POST */
+
+#define I2C_ADDR_LIST	{CFG_I2C_PICIO_ADDR,	\
+			CFG_I2C_RTC_ADDR,	\
+			}
+
+
+#define CONFIG_RTC_PCF8563		/* use Philips PCF8563 RTC	*/
+
+#define CFG_DISCOVER_PHY
+
+#if 0
+#define CONFIG_ETHADDR                  00:0B:64:00:00:00 /* our OUI from IEEE */
+#endif
+#define CONFIG_KUP4K_LOGO               0x40050000  /* Address of logo bitmap */

 /* Define to allow the user to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
+#if 1
+/* POST support */
+
+#define CONFIG_POST		(CFG_POST_CPU	   | \
+				 CFG_POST_RTC	   | \
+				 CFG_POST_I2C)
+
+#ifdef CONFIG_POST
+#define CFG_CMD_POST_DIAG CFG_CMD_DIAG
+#else
+#define CFG_CMD_POST_DIAG 0
+#endif
+#endif

 #define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
 				CFG_CMD_DHCP	| \
-				CFG_CMD_IDE	| \
 				CFG_CMD_I2C	| \
-				CFG_CMD_DATE	)
+				CFG_CMD_DATE	| \
+				CFG_CMD_POST_DIAG	| \
+				CFG_CMD_IDE	)

 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
@@ -189,7 +247,7 @@
 #define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

 #define CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_OFFSET		0x30000 /*   Offset   of Environment Sector	*/
+#define CFG_ENV_OFFSET		0x40000 /*   Offset   of Environment Sector	*/
 #define CFG_ENV_SIZE		0x1000	/* Total Size of Environment Sector	*/
 #define CFG_ENV_SECT_SIZE	0x10000

@@ -201,10 +259,10 @@
 /*-----------------------------------------------------------------------
 * Hardware Information Block
 */
-#if 0
-#define CFG_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
-#define CFG_HWINFO_SIZE		0x00000040	/* size	  of HW Info block */
-#define CFG_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+#if 1
+#define CFG_HWINFO_OFFSET	0x000F0000	/* offset of HW Info block */
+#define CFG_HWINFO_SIZE		0x00000100	/* size   of HW Info block */
+#define CFG_HWINFO_MAGIC	0x4B26500D	/* 'K&P<CR>' */
 #endif
 /*-----------------------------------------------------------------------
 * Cache Configuration
@@ -220,7 +278,7 @@
 *-----------------------------------------------------------------------
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 */
-#if defined(CONFIG_WATCHDOG)
+#if 0 && defined(CONFIG_WATCHDOG)       /* KUP uses external TPS3705 WD */
 #define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 #else
--- a/include/configs/KUP4X.h
+++ b/include/configs/KUP4X.h
@@ -69,8 +69,9 @@
 #define CONFIG_EXTRA_ENV_SETTINGS						\
 "slot_a_boot=setenv bootargs root=/dev/hda2 ip=off;"				\
  "run addhw;diskboot 200000 0:1;bootm 200000\0"				\
-"slot_b_boot=setenv bootargs root=/dev/hda2 ip=off;"				\
- "run addhw;diskboot 200000 2:1;bootm 200000\0"					\
+"usb_boot=setenv bootargs root=/dev/sda2 ip=off;\
+ run addhw; sleep 2; usb reset; usb scan; usbboot 200000 0:1;\
+ usb stop; bootm 200000\0"      \
 "nfs_boot=dhcp;run nfsargs addip addhw;bootm 200000\0"				\
 "panic_boot=echo No Bootdevice !!! reset\0"					\
 "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath)\0"	\
@@ -85,7 +86,7 @@
 "cp.b 200000 40040000 14000\0"

 #define CONFIG_BOOTCOMMAND  \
-    "run slot_a_boot;run nfs_boot;run panic_boot"
+    "run usb_boot;run_slot_a_boot;run nfs_boot;run panic_boot"


 #define CONFIG_MISC_INIT_R	1
@@ -94,7 +95,7 @@
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
 #undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/

-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+#define	CONFIG_WATCHDOG		1	/* watchdog enabled		*/

 #define CONFIG_STATUS_LED	1	/* Status LED enabled		*/

@@ -105,19 +106,81 @@
 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION

-#define CONFIG_HARD_I2C
-#define CFG_I2C_SPEED 40000
-#define CFG_I2C_SLAVE 0x7F
+/*
+ * enable I2C and select the hardware/software driver
+ */
+#undef	CONFIG_HARD_I2C			/* I2C with hardware support	*/
+#define	CONFIG_SOFT_I2C         1	/* I2C bit-banged		*/

-#define CONFIG_ETHADDR			00:0B:64:80:00:00 /* our OUI from IEEE */
+#define CFG_I2C_SPEED		93000	/* 93 kHz is supposed to work	*/
+#define CFG_I2C_SLAVE		0xFE
+
+#ifdef CONFIG_SOFT_I2C
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define PB_SCL		0x00000020	/* PB 26 */
+#define PB_SDA		0x00000010	/* PB 27 */
+
+#define I2C_INIT	(immr->im_cpm.cp_pbdir |=  PB_SCL)
+#define I2C_ACTIVE	(immr->im_cpm.cp_pbdir |=  PB_SDA)
+#define I2C_TRISTATE	(immr->im_cpm.cp_pbdir &= ~PB_SDA)
+#define I2C_READ	((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
+#define I2C_SDA(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
+			else    immr->im_cpm.cp_pbdat &= ~PB_SDA
+#define I2C_SCL(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
+			else    immr->im_cpm.cp_pbdat &= ~PB_SCL
+#define I2C_DELAY	udelay(2)	/* 1/4 I2C clock duration */
+#endif	/* CONFIG_SOFT_I2C */
+
+
+/*-----------------------------------------------------------------------
+ * I2C Configuration
+ */
+
+#define CFG_I2C_PICIO_ADDR	0x21	/* PCF8574 IO Expander			*/
+#define CFG_I2C_RTC_ADDR	0x51	/* PCF8563 RTC				*/
+
+
+/* List of I2C addresses to be verified by POST */
+
+#define I2C_ADDR_LIST	{CFG_I2C_PICIO_ADDR,	\
+			CFG_I2C_RTC_ADDR,	\
+			}
+
+
+#define CONFIG_RTC_PCF8563		/* use Philips PCF8563 RTC	*/
+
+#define CFG_DISCOVER_PHY
+
+#if 0
+#define CONFIG_ETHADDR                  00:0B:64:80:00:00 /* our OUI from IEEE */
+#endif
 #undef CONFIG_KUP4K_LOGO

 /* Define to allow the user to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE

+
+#if 1
+/* POST support */
+
+#define CONFIG_POST		(CFG_POST_CPU	   | \
+				 CFG_POST_RTC	   | \
+				 CFG_POST_I2C)
+
+#ifdef CONFIG_POST
+#define CFG_CMD_POST_DIAG CFG_CMD_DIAG
+#else
+#define CFG_CMD_POST_DIAG 0
+#endif
+#endif
+
 #define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
 				CFG_CMD_DHCP	| \
 				CFG_CMD_I2C	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_POST_DIAG	| \
 				CFG_CMD_IDE	| \
 				CFG_CMD_USB	| \
 				CFG_CMD_FAT)
@@ -196,7 +259,7 @@
 #define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

 #define CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_OFFSET		0x30000 /*   Offset   of Environment Sector	*/
+#define CFG_ENV_OFFSET		0x40000 /*   Offset   of Environment Sector	*/
 #define CFG_ENV_SIZE		0x1000	/* Total Size of Environment Sector	*/
 #define CFG_ENV_SECT_SIZE	0x10000

@@ -208,10 +271,10 @@
 /*-----------------------------------------------------------------------
 * Hardware Information Block
 */
-#if 0
-#define CFG_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
-#define CFG_HWINFO_SIZE		0x00000040	/* size	  of HW Info block */
-#define CFG_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+#if 1
+#define CFG_HWINFO_OFFSET	0x000F0000	/* offset of HW Info block */
+#define CFG_HWINFO_SIZE		0x00000100	/* size   of HW Info block */
+#define CFG_HWINFO_MAGIC	0x4B26500D	/* 'K&P<CR>' */
 #endif
 /*-----------------------------------------------------------------------
 * Cache Configuration
@@ -227,7 +290,7 @@
 *-----------------------------------------------------------------------
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 */
-#if defined(CONFIG_WATCHDOG)
+#if 0 && defined(CONFIG_WATCHDOG)       /* KUP uses external TPS3705 WD */
 #define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 #else
--- a/include/configs/OCOTEA.h
+++ b/include/configs/OCOTEA.h
@@ -154,9 +154,9 @@
 #define CONFIG_NETMASK		255.255.255.0
 #define CONFIG_IPADDR		10.1.2.3
 #define CONFIG_ETHADDR		00:04:AC:E3:28:8A
-#define CONFIG_ETHADDR1		00:04:AC:E3:28:8B
-#define CONFIG_ETHADDR2		00:04:AC:E3:28:8C
-#define CONFIG_ETHADDR3		00:04:AC:E3:28:8D
+#define CONFIG_ETH1ADDR		00:04:AC:E3:28:8B
+#define CONFIG_ETH2ADDR		00:04:AC:E3:28:8C
+#define CONFIG_ETH3ADDR		00:04:AC:E3:28:8D
 #define CFG_RX_ETH_BUFFER	32	  /* Number of ethernet rx buffers & descriptors */
 #define CONFIG_SERVERIP		10.1.2.2

--- a/include/configs/PM520.h
+++ b/include/configs/PM520.h
@@ -30,7 +30,7 @@
 */

 #define CONFIG_MPC5200
-#define CONFIG_MPC5XXX		1	/* This is an MPC5xxx CPU */
+#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
 #define CONFIG_PM520		1	/* ... on PM520 board */

 #define CFG_MPC5XXX_CLKIN	33000000 /* ... running at 33MHz */
@@ -184,8 +184,11 @@
 /*
 * Ethernet configuration
 */
-#define CONFIG_MPC5XXX_FEC	1
-#define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */
+#define CONFIG_MPC5xxx_FEC	1
+/*
+ * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
+ */
+/* #define CONFIG_FEC_10MBIT 1 */
 #define CONFIG_PHY_ADDR		0x00

 /*
--- a/include/configs/PPChameleonEVB.h
+++ b/include/configs/PPChameleonEVB.h
@@ -92,9 +92,10 @@
 				CFG_CMD_EEPROM	| \
 				CFG_CMD_I2C	| \
 				CFG_CMD_IRQ	| \
+				CFG_CMD_JFFS2	| \
 				CFG_CMD_MII	| \
 				CFG_CMD_NAND	| \
-				CFG_CMD_JFFS2)
+				CFG_CMD_PCI	)

 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION
@@ -136,9 +137,9 @@
 #define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
 #define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

-#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#undef	CFG_EXT_SERIAL_CLOCK		/* no external serial clock used */
 #define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
-#define CFG_BASE_BAUD	    691200
+#define CFG_BASE_BAUD		691200

 /* The following table includes the supported baudrates */
 #define CFG_BAUDRATE_TABLE	\
@@ -339,8 +340,8 @@
 #define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */

 #if 0 /* test-only */
-#define CFG_JFFS2_FIRST_BANK	0	    /* use for JFFS2 */
-#define CFG_JFFS2_NUM_BANKS	1	    /* ! second bank contains U-Boot */
+#define CFG_JFFS2_FIRST_BANK	0	 /* use for JFFS2 */
+#define CFG_JFFS2_NUM_BANKS	1	 /* ! second bank contains U-Boot */
 #endif

 /*-----------------------------------------------------------------------
@@ -460,34 +461,27 @@
 #define CFG_FPGA_STATUS_FLASH	0x0008
 #define CFG_FPGA_STATUS_TS_IRQ	0x1000

-#define CFG_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now    */
-#define CFG_FPGA_MAX_SIZE	128*1024    /* 128kByte is enough for XC2S50E*/
+#define CFG_FPGA_SPARTAN2	1		/* using Xilinx Spartan 2 now	 */
+#define CFG_FPGA_MAX_SIZE	128*1024	/* 128kByte is enough for XC2S50E*/

 /* FPGA program pin configuration */
-#define CFG_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
-#define CFG_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output)     */
-#define CFG_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
-#define CFG_FPGA_INIT		0x00010000  /* FPGA init pin (ppc input)     */
-#define CFG_FPGA_DONE		0x00008000  /* FPGA done pin (ppc input)     */
+#define CFG_FPGA_PRG		0x04000000	/* FPGA program pin (ppc output) */
+#define CFG_FPGA_CLK		0x02000000	/* FPGA clk pin (ppc output)	 */
+#define CFG_FPGA_DATA		0x01000000	/* FPGA data pin (ppc output)	 */
+#define CFG_FPGA_INIT		0x00010000	/* FPGA init pin (ppc input)	 */
+#define CFG_FPGA_DONE		0x00008000	/* FPGA done pin (ppc input)	 */

 /*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in data cache)
 */
-#if 0 /* test-only */
-#define CFG_INIT_DCACHE_CS	4	/* use cs # 4 for data cache memory    */
-
-#define CFG_INIT_RAM_ADDR	0x40000000  /* use data cache		       */
-#define CFG_INIT_RAM_END	0x2000	/* End of used area in RAM	       */
-#else
 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CFG_TEMP_STACK_OCM	  1
+#define CFG_TEMP_STACK_OCM	1

 /* On Chip Memory location */
 #define CFG_OCM_DATA_ADDR	0xF8000000
 #define CFG_OCM_DATA_SIZE	0x1000
 #define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
 #define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
-#endif

 #define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
 #define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
@@ -537,147 +531,147 @@
 !	are plugged in the board will be utilized as non-ECC DIMMs.
 !-----------------------------------------------------------------------
 */
-#undef	      AUTO_MEMORY_CONFIG
-#define	       DIMM_READ_ADDR 0xAB
-#define	       DIMM_WRITE_ADDR 0xAA
+#undef		AUTO_MEMORY_CONFIG
+#define		DIMM_READ_ADDR 0xAB
+#define		DIMM_WRITE_ADDR 0xAA


-#define CPC0_PLLMR0  (CNTRL_DCR_BASE+0x0)  /* PLL mode 0 register	   */
-#define CPC0_BOOT    (CNTRL_DCR_BASE+0x1)  /* Chip Clock Status register   */
-#define CPC0_CR1     (CNTRL_DCR_BASE+0x2)  /* Chip Control 1 register	   */
-#define CPC0_EPRCSR  (CNTRL_DCR_BASE+0x3)  /* EMAC PHY Rcv Clk Src register*/
-#define CPC0_PLLMR1  (CNTRL_DCR_BASE+0x4)  /* PLL mode 1 register	   */
-#define CPC0_UCR     (CNTRL_DCR_BASE+0x5)  /* UART Control register	   */
-#define CPC0_SRR     (CNTRL_DCR_BASE+0x6)  /* Soft Reset register	   */
-#define CPC0_JTAGID  (CNTRL_DCR_BASE+0x7)  /* JTAG ID register		   */
-#define CPC0_SPARE   (CNTRL_DCR_BASE+0x8)  /* Spare DCR			   */
-#define CPC0_PCI     (CNTRL_DCR_BASE+0x9)  /* PCI Control register	   */
+#define CPC0_PLLMR0  (CNTRL_DCR_BASE+0x0)  /* PLL mode 0 register		*/
+#define CPC0_BOOT    (CNTRL_DCR_BASE+0x1)  /* Chip Clock Status register	*/
+#define CPC0_CR1     (CNTRL_DCR_BASE+0x2)  /* Chip Control 1 register		*/
+#define CPC0_EPRCSR  (CNTRL_DCR_BASE+0x3)  /* EMAC PHY Rcv Clk Src register	*/
+#define CPC0_PLLMR1  (CNTRL_DCR_BASE+0x4)  /* PLL mode 1 register		*/
+#define CPC0_UCR     (CNTRL_DCR_BASE+0x5)  /* UART Control register		*/
+#define CPC0_SRR     (CNTRL_DCR_BASE+0x6)  /* Soft Reset register		*/
+#define CPC0_JTAGID  (CNTRL_DCR_BASE+0x7)  /* JTAG ID register			*/
+#define CPC0_SPARE   (CNTRL_DCR_BASE+0x8)  /* Spare DCR				*/
+#define CPC0_PCI     (CNTRL_DCR_BASE+0x9)  /* PCI Control register		*/

 /* Defines for CPC0_PLLMR1 Register fields */
-#define PLL_ACTIVE		   0x80000000
-#define CPC0_PLLMR1_SSCS	   0x80000000
-#define PLL_RESET		   0x40000000
-#define CPC0_PLLMR1_PLLR	   0x40000000
+#define PLL_ACTIVE		0x80000000
+#define CPC0_PLLMR1_SSCS	0x80000000
+#define PLL_RESET		0x40000000
+#define CPC0_PLLMR1_PLLR	0x40000000
    /* Feedback multiplier */
-#define PLL_FBKDIV		   0x00F00000
-#define CPC0_PLLMR1_FBDV	   0x00F00000
-#define PLL_FBKDIV_16		   0x00000000
-#define PLL_FBKDIV_1		   0x00100000
-#define PLL_FBKDIV_2		   0x00200000
-#define PLL_FBKDIV_3		   0x00300000
-#define PLL_FBKDIV_4		   0x00400000
-#define PLL_FBKDIV_5		   0x00500000
-#define PLL_FBKDIV_6		   0x00600000
-#define PLL_FBKDIV_7		   0x00700000
-#define PLL_FBKDIV_8		   0x00800000
-#define PLL_FBKDIV_9		   0x00900000
-#define PLL_FBKDIV_10		   0x00A00000
-#define PLL_FBKDIV_11		   0x00B00000
-#define PLL_FBKDIV_12		   0x00C00000
-#define PLL_FBKDIV_13		   0x00D00000
-#define PLL_FBKDIV_14		   0x00E00000
-#define PLL_FBKDIV_15		   0x00F00000
+#define PLL_FBKDIV		0x00F00000
+#define CPC0_PLLMR1_FBDV	0x00F00000
+#define PLL_FBKDIV_16		0x00000000
+#define PLL_FBKDIV_1		0x00100000
+#define PLL_FBKDIV_2		0x00200000
+#define PLL_FBKDIV_3		0x00300000
+#define PLL_FBKDIV_4		0x00400000
+#define PLL_FBKDIV_5		0x00500000
+#define PLL_FBKDIV_6		0x00600000
+#define PLL_FBKDIV_7		0x00700000
+#define PLL_FBKDIV_8		0x00800000
+#define PLL_FBKDIV_9		0x00900000
+#define PLL_FBKDIV_10		0x00A00000
+#define PLL_FBKDIV_11		0x00B00000
+#define PLL_FBKDIV_12		0x00C00000
+#define PLL_FBKDIV_13		0x00D00000
+#define PLL_FBKDIV_14		0x00E00000
+#define PLL_FBKDIV_15		0x00F00000
    /* Forward A divisor */
-#define PLL_FWDDIVA		   0x00070000
-#define CPC0_PLLMR1_FWDVA	   0x00070000
-#define PLL_FWDDIVA_8		   0x00000000
-#define PLL_FWDDIVA_7		   0x00010000
-#define PLL_FWDDIVA_6		   0x00020000
-#define PLL_FWDDIVA_5		   0x00030000
-#define PLL_FWDDIVA_4		   0x00040000
-#define PLL_FWDDIVA_3		   0x00050000
-#define PLL_FWDDIVA_2		   0x00060000
-#define PLL_FWDDIVA_1		   0x00070000
+#define PLL_FWDDIVA		0x00070000
+#define CPC0_PLLMR1_FWDVA	0x00070000
+#define PLL_FWDDIVA_8		0x00000000
+#define PLL_FWDDIVA_7		0x00010000
+#define PLL_FWDDIVA_6		0x00020000
+#define PLL_FWDDIVA_5		0x00030000
+#define PLL_FWDDIVA_4		0x00040000
+#define PLL_FWDDIVA_3		0x00050000
+#define PLL_FWDDIVA_2		0x00060000
+#define PLL_FWDDIVA_1		0x00070000
    /* Forward B divisor */
-#define PLL_FWDDIVB		   0x00007000
-#define CPC0_PLLMR1_FWDVB	   0x00007000
-#define PLL_FWDDIVB_8		   0x00000000
-#define PLL_FWDDIVB_7		   0x00001000
-#define PLL_FWDDIVB_6		   0x00002000
-#define PLL_FWDDIVB_5		   0x00003000
-#define PLL_FWDDIVB_4		   0x00004000
-#define PLL_FWDDIVB_3		   0x00005000
-#define PLL_FWDDIVB_2		   0x00006000
-#define PLL_FWDDIVB_1		   0x00007000
+#define PLL_FWDDIVB		0x00007000
+#define CPC0_PLLMR1_FWDVB	0x00007000
+#define PLL_FWDDIVB_8		0x00000000
+#define PLL_FWDDIVB_7		0x00001000
+#define PLL_FWDDIVB_6		0x00002000
+#define PLL_FWDDIVB_5		0x00003000
+#define PLL_FWDDIVB_4		0x00004000
+#define PLL_FWDDIVB_3		0x00005000
+#define PLL_FWDDIVB_2		0x00006000
+#define PLL_FWDDIVB_1		0x00007000
    /* PLL tune bits */
-#define PLL_TUNE_MASK		 0x000003FF
-#define PLL_TUNE_2_M_3		 0x00000133	/*  2 <= M <= 3		      */
-#define PLL_TUNE_4_M_6		 0x00000134	/*  3 <	 M <= 6		      */
-#define PLL_TUNE_7_M_10		 0x00000138	/*  6 <	 M <= 10	      */
-#define PLL_TUNE_11_M_14	 0x0000013C	/* 10 <	 M <= 14	      */
-#define PLL_TUNE_15_M_40	 0x0000023E	/* 14 <	 M <= 40	      */
-#define PLL_TUNE_VCO_LOW	 0x00000000	/* 500MHz <= VCO <=  800MHz   */
-#define PLL_TUNE_VCO_HI		 0x00000080	/* 800MHz <  VCO <= 1000MHz   */
+#define PLL_TUNE_MASK		0x000003FF
+#define PLL_TUNE_2_M_3		0x00000133	/*  2 <= M <= 3			*/
+#define PLL_TUNE_4_M_6		0x00000134	/*  3 <	 M <= 6			*/
+#define PLL_TUNE_7_M_10		0x00000138	/*  6 <	 M <= 10		*/
+#define PLL_TUNE_11_M_14	0x0000013C	/* 10 <	 M <= 14		*/
+#define PLL_TUNE_15_M_40	0x0000023E	/* 14 <	 M <= 40		*/
+#define PLL_TUNE_VCO_LOW	0x00000000	/* 500MHz <= VCO <=  800MHz	*/
+#define PLL_TUNE_VCO_HI		0x00000080	/* 800MHz <  VCO <= 1000MHz	*/

 /* Defines for CPC0_PLLMR0 Register fields */
    /* CPU divisor */
-#define PLL_CPUDIV		   0x00300000
-#define CPC0_PLLMR0_CCDV	   0x00300000
-#define PLL_CPUDIV_1		   0x00000000
-#define PLL_CPUDIV_2		   0x00100000
-#define PLL_CPUDIV_3		   0x00200000
-#define PLL_CPUDIV_4		   0x00300000
+#define PLL_CPUDIV		0x00300000
+#define CPC0_PLLMR0_CCDV	0x00300000
+#define PLL_CPUDIV_1		0x00000000
+#define PLL_CPUDIV_2		0x00100000
+#define PLL_CPUDIV_3		0x00200000
+#define PLL_CPUDIV_4		0x00300000
    /* PLB divisor */
-#define PLL_PLBDIV		   0x00030000
-#define CPC0_PLLMR0_CBDV	   0x00030000
-#define PLL_PLBDIV_1		   0x00000000
-#define PLL_PLBDIV_2		   0x00010000
-#define PLL_PLBDIV_3		   0x00020000
-#define PLL_PLBDIV_4		   0x00030000
+#define PLL_PLBDIV		0x00030000
+#define CPC0_PLLMR0_CBDV	0x00030000
+#define PLL_PLBDIV_1		0x00000000
+#define PLL_PLBDIV_2		0x00010000
+#define PLL_PLBDIV_3		0x00020000
+#define PLL_PLBDIV_4		0x00030000
    /* OPB divisor */
-#define PLL_OPBDIV		   0x00003000
-#define CPC0_PLLMR0_OPDV	   0x00003000
-#define PLL_OPBDIV_1		   0x00000000
-#define PLL_OPBDIV_2		   0x00001000
-#define PLL_OPBDIV_3		   0x00002000
-#define PLL_OPBDIV_4		   0x00003000
+#define PLL_OPBDIV		0x00003000
+#define CPC0_PLLMR0_OPDV	0x00003000
+#define PLL_OPBDIV_1		0x00000000
+#define PLL_OPBDIV_2		0x00001000
+#define PLL_OPBDIV_3		0x00002000
+#define PLL_OPBDIV_4		0x00003000
    /* EBC divisor */
-#define PLL_EXTBUSDIV		   0x00000300
-#define CPC0_PLLMR0_EPDV	   0x00000300
-#define PLL_EXTBUSDIV_2		   0x00000000
-#define PLL_EXTBUSDIV_3		   0x00000100
-#define PLL_EXTBUSDIV_4		   0x00000200
-#define PLL_EXTBUSDIV_5		   0x00000300
+#define PLL_EXTBUSDIV		0x00000300
+#define CPC0_PLLMR0_EPDV	0x00000300
+#define PLL_EXTBUSDIV_2		0x00000000
+#define PLL_EXTBUSDIV_3		0x00000100
+#define PLL_EXTBUSDIV_4		0x00000200
+#define PLL_EXTBUSDIV_5		0x00000300
    /* MAL divisor */
-#define PLL_MALDIV		   0x00000030
-#define CPC0_PLLMR0_MPDV	   0x00000030
-#define PLL_MALDIV_1		   0x00000000
-#define PLL_MALDIV_2		   0x00000010
-#define PLL_MALDIV_3		   0x00000020
-#define PLL_MALDIV_4		   0x00000030
+#define PLL_MALDIV		0x00000030
+#define CPC0_PLLMR0_MPDV	0x00000030
+#define PLL_MALDIV_1		0x00000000
+#define PLL_MALDIV_2		0x00000010
+#define PLL_MALDIV_3		0x00000020
+#define PLL_MALDIV_4		0x00000030
    /* PCI divisor */
-#define PLL_PCIDIV		   0x00000003
-#define CPC0_PLLMR0_PPFD	   0x00000003
-#define PLL_PCIDIV_1		   0x00000000
-#define PLL_PCIDIV_2		   0x00000001
-#define PLL_PCIDIV_3		   0x00000002
-#define PLL_PCIDIV_4		   0x00000003
+#define PLL_PCIDIV		0x00000003
+#define CPC0_PLLMR0_PPFD	0x00000003
+#define PLL_PCIDIV_1		0x00000000
+#define PLL_PCIDIV_2		0x00000001
+#define PLL_PCIDIV_3		0x00000002
+#define PLL_PCIDIV_4		0x00000003

 /* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 33.3MHz input clock to the 405EP) */
 #define PLLMR0_133_133_33_66_33	 (PLL_CPUDIV_1 | PLL_PLBDIV_1 |	 \
-			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |	\
-			      PLL_MALDIV_1 | PLL_PCIDIV_4)
+				  PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |	\
+				  PLL_MALDIV_1 | PLL_PCIDIV_4)
 #define PLLMR1_133_133_33_66_33	 (PLL_FBKDIV_4	|  \
-			      PLL_FWDDIVA_6 | PLL_FWDDIVB_6 |  \
-			      PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-#define PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |  \
-			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |	\
-			      PLL_MALDIV_1 | PLL_PCIDIV_4)
-#define PLLMR1_200_100_50_33 (PLL_FBKDIV_6  |  \
-			      PLL_FWDDIVA_4 | PLL_FWDDIVB_4 |  \
-			      PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-#define PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |	\
-			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |	\
-			      PLL_MALDIV_1 | PLL_PCIDIV_4)
-#define PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8  |  \
-			      PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
-			      PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-#define PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 |	\
-			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |	\
-			      PLL_MALDIV_1 | PLL_PCIDIV_2)
-#define PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10	|  \
-			      PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
-			      PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
+				  PLL_FWDDIVA_6 | PLL_FWDDIVB_6 |  \
+				  PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+#define PLLMR0_200_100_50_33	 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |	 \
+				  PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |	\
+				  PLL_MALDIV_1 | PLL_PCIDIV_4)
+#define PLLMR1_200_100_50_33	 (PLL_FBKDIV_6	|  \
+				  PLL_FWDDIVA_4 | PLL_FWDDIVB_4 |  \
+				  PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+#define PLLMR0_266_133_33_66_33	 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
+				  PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |	\
+				  PLL_MALDIV_1 | PLL_PCIDIV_4)
+#define PLLMR1_266_133_33_66_33	 (PLL_FBKDIV_8	|  \
+				  PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
+				  PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+#define PLLMR0_333_111_37_55_55	 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
+				  PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |	\
+				  PLL_MALDIV_1 | PLL_PCIDIV_2)
+#define PLLMR1_333_111_37_55_55	 (PLL_FBKDIV_10 |  \
+				  PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
+				  PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)

 #if   (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI)
 /* Model HI */
@@ -696,7 +690,7 @@

 #endif /* CONFIG_NO_SERIAL_EEPROM */

-#define CONFIG_JFFS2_NAND 1 			/* jffs2 on nand support */
+#define CONFIG_JFFS2_NAND 1			/* jffs2 on nand support */
 #define CONFIG_JFFS2_NAND_DEV 0			/* nand device jffs2 lives on */
 #define CONFIG_JFFS2_NAND_OFF 0			/* start of jffs2 partition */
 #define CONFIG_JFFS2_NAND_SIZE 2*1024*1024	/* size of jffs2 partition */
--- a/include/configs/TQM823L.h
+++ b/include/configs/TQM823L.h
@@ -262,15 +262,8 @@
 *-----------------------------------------------------------------------
 * Reset PLL lock status sticky bit, timer expired status bit and timer
 * interrupt status bit
- *
- * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
 */
-#ifdef	CONFIG_80MHz	/* for 80 MHz, we use a 16 MHz clock * 5 */
-#define CFG_PLPRCR							\
-		( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
-#else			/* up to 66 MHz we use a 1:1 clock */
 #define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
-#endif	/* CONFIG_80MHz */

 /*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
@@ -279,17 +272,9 @@
 * power management and some other internal clocks
 */
 #define SCCR_MASK	SCCR_EBDF11
-#ifdef	CONFIG_80MHz	/* for 80 MHz, we use a 16 MHz clock * 5 */
-#define CFG_SCCR	(/* SCCR_TBS  | */ \
-			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+#define CFG_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 			 SCCR_DFALCD00)
-#else			/* up to 66 MHz we use a 1:1 clock */
-#define CFG_SCCR	(SCCR_TBS     | \
-			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
-			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
-			 SCCR_DFALCD00)
-#endif	/* CONFIG_80MHz */

 /*-----------------------------------------------------------------------
 * PCMCIA stuff
@@ -358,19 +343,8 @@
 /*
 * FLASH timing:
 */
-#if   defined(CONFIG_80MHz)
-/* 80 MHz CPU - 40 MHz bus: ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */
-#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | 0       | OR_CSNT_SAM | \
-				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
-#elif defined(CONFIG_66MHz)
-/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
 #define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
 				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
-#else		/*   50 MHz */
-/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
-#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
-				 OR_SCY_2_CLK | OR_EHTR | OR_BI)
-#endif	/*CONFIG_??MHz */

 #define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
 #define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
@@ -431,13 +405,9 @@
 * 66 Mhz => 66.000.000 / Divider = 129
 * 80 Mhz => 80.000.000 / Divider = 156
 */
-#if   defined(CONFIG_80MHz)
-#define CFG_MAMR_PTA		156
-#elif defined(CONFIG_66MHz)
-#define CFG_MAMR_PTA		129
-#else		/*   50 MHz */
-#define CFG_MAMR_PTA		 98
-#endif	/*CONFIG_??MHz */
+
+#define CFG_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
+#define CFG_MAMR_PTA	98

 /*
 * For 16 MBit, refresh rates could be 31.3 us
--- a/include/configs/TQM823M.h
+++ b/include/configs/TQM823M.h
@@ -254,15 +254,8 @@
 *-----------------------------------------------------------------------
 * Reset PLL lock status sticky bit, timer expired status bit and timer
 * interrupt status bit
- *
- * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
 */
-#ifdef	CONFIG_80MHz	/* for 80 MHz, we use a 16 MHz clock * 5 */
-#define CFG_PLPRCR							\
-		( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
-#else			/* up to 66 MHz we use a 1:1 clock */
 #define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
-#endif	/* CONFIG_80MHz */

 /*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
@@ -271,17 +264,9 @@
 * power management and some other internal clocks
 */
 #define SCCR_MASK	SCCR_EBDF11
-#ifdef	CONFIG_80MHz	/* for 80 MHz, we use a 16 MHz clock * 5 */
-#define CFG_SCCR	(/* SCCR_TBS  | */ \
-			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+#define CFG_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 			 SCCR_DFALCD00)
-#else			/* up to 66 MHz we use a 1:1 clock */
-#define CFG_SCCR	(SCCR_TBS     | \
-			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
-			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
-			 SCCR_DFALCD00)
-#endif	/* CONFIG_80MHz */

 /*-----------------------------------------------------------------------
 * PCMCIA stuff
@@ -350,19 +335,8 @@
 /*
 * FLASH timing:
 */
-#if   defined(CONFIG_80MHz)
-/* 80 MHz CPU - 40 MHz bus: ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */
-#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | 0       | OR_CSNT_SAM | \
-				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
-#elif defined(CONFIG_66MHz)
-/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
 #define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
 				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
-#else		/*   50 MHz */
-/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
-#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
-				 OR_SCY_2_CLK | OR_EHTR | OR_BI)
-#endif	/*CONFIG_??MHz */

 #define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
 #define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
@@ -423,13 +397,9 @@
 * 66 Mhz => 66.000.000 / Divider = 129
 * 80 Mhz => 80.000.000 / Divider = 156
 */
-#if   defined(CONFIG_80MHz)
-#define CFG_MAMR_PTA		156
-#elif defined(CONFIG_66MHz)
-#define CFG_MAMR_PTA		129
-#else		/*   50 MHz */
-#define CFG_MAMR_PTA		 98
-#endif	/*CONFIG_??MHz */
+
+#define CFG_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
+#define CFG_MAMR_PTA	98

 /*
 * For 16 MBit, refresh rates could be 31.3 us
--- a/include/configs/TQM850L.h
+++ b/include/configs/TQM850L.h
@@ -245,15 +245,8 @@
 *-----------------------------------------------------------------------
 * Reset PLL lock status sticky bit, timer expired status bit and timer
 * interrupt status bit
- *
- * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
 */
-#ifdef	CONFIG_80MHz	/* for 80 MHz, we use a 16 MHz clock * 5 */
-#define CFG_PLPRCR							\
-		( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
-#else			/* up to 66 MHz we use a 1:1 clock */
 #define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
-#endif	/* CONFIG_80MHz */

 /*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
@@ -262,17 +255,9 @@
 * power management and some other internal clocks
 */
 #define SCCR_MASK	SCCR_EBDF11
-#ifdef	CONFIG_80MHz	/* for 80 MHz, we use a 16 MHz clock * 5 */
-#define CFG_SCCR	(/* SCCR_TBS  | */ \
-			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+#define CFG_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 			 SCCR_DFALCD00)
-#else			/* up to 66 MHz we use a 1:1 clock */
-#define CFG_SCCR	(SCCR_TBS     | \
-			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
-			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
-			 SCCR_DFALCD00)
-#endif	/* CONFIG_80MHz */

 /*-----------------------------------------------------------------------
 * PCMCIA stuff
@@ -341,19 +326,8 @@
 /*
 * FLASH timing:
 */
-#if   defined(CONFIG_80MHz)
-/* 80 MHz CPU - 40 MHz bus: ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */
-#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | 0       | OR_CSNT_SAM | \
-				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
-#elif defined(CONFIG_66MHz)
-/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
 #define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
 				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
-#else		/*   50 MHz */
-/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
-#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
-				 OR_SCY_2_CLK | OR_EHTR | OR_BI)
-#endif	/*CONFIG_??MHz */

 #define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
 #define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
@@ -414,13 +388,9 @@
 * 66 Mhz => 66.000.000 / Divider = 129
 * 80 Mhz => 80.000.000 / Divider = 156
 */
-#if   defined(CONFIG_80MHz)
-#define CFG_MAMR_PTA		156
-#elif defined(CONFIG_66MHz)
-#define CFG_MAMR_PTA		129
-#else		/*   50 MHz */
-#define CFG_MAMR_PTA		 98
-#endif	/*CONFIG_??MHz */
+
+#define CFG_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
+#define CFG_MAMR_PTA	98

 /*
 * For 16 MBit, refresh rates could be 31.3 us
--- a/include/configs/TQM850M.h
+++ b/include/configs/TQM850M.h
@@ -244,15 +244,8 @@
 *-----------------------------------------------------------------------
 * Reset PLL lock status sticky bit, timer expired status bit and timer
 * interrupt status bit
- *
- * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
 */
-#ifdef	CONFIG_80MHz	/* for 80 MHz, we use a 16 MHz clock * 5 */
-#define CFG_PLPRCR							\
-		( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
-#else			/* up to 66 MHz we use a 1:1 clock */
 #define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
-#endif	/* CONFIG_80MHz */

 /*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
@@ -261,17 +254,9 @@
 * power management and some other internal clocks
 */
 #define SCCR_MASK	SCCR_EBDF11
-#ifdef	CONFIG_80MHz	/* for 80 MHz, we use a 16 MHz clock * 5 */
-#define CFG_SCCR	(/* SCCR_TBS  | */ \
-			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+#define CFG_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 			 SCCR_DFALCD00)
-#else			/* up to 66 MHz we use a 1:1 clock */
-#define CFG_SCCR	(SCCR_TBS     | \
-			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
-			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
-			 SCCR_DFALCD00)
-#endif	/* CONFIG_80MHz */

 /*-----------------------------------------------------------------------
 * PCMCIA stuff
@@ -340,19 +325,8 @@
 /*
 * FLASH timing:
 */
-#if   defined(CONFIG_80MHz)
-/* 80 MHz CPU - 40 MHz bus: ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */
-#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | 0       | OR_CSNT_SAM | \
-				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
-#elif defined(CONFIG_66MHz)
-/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
 #define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
 				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
-#else		/*   50 MHz */
-/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
-#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
-				 OR_SCY_2_CLK | OR_EHTR | OR_BI)
-#endif	/*CONFIG_??MHz */

 #define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
 #define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
@@ -413,13 +387,9 @@
 * 66 Mhz => 66.000.000 / Divider = 129
 * 80 Mhz => 80.000.000 / Divider = 156
 */
-#if   defined(CONFIG_80MHz)
-#define CFG_MAMR_PTA		156
-#elif defined(CONFIG_66MHz)
-#define CFG_MAMR_PTA		129
-#else		/*   50 MHz */
-#define CFG_MAMR_PTA		 98
-#endif	/*CONFIG_??MHz */
+
+#define CFG_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
+#define CFG_MAMR_PTA	98

 /*
 * For 16 MBit, refresh rates could be 31.3 us
--- a/include/configs/TQM855L.h
+++ b/include/configs/TQM855L.h
@@ -248,15 +248,8 @@
 *-----------------------------------------------------------------------
 * Reset PLL lock status sticky bit, timer expired status bit and timer
 * interrupt status bit
- *
- * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
 */
-#ifdef	CONFIG_80MHz	/* for 80 MHz, we use a 16 MHz clock * 5 */
-#define CFG_PLPRCR							\
-		( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
-#else			/* up to 66 MHz we use a 1:1 clock */
 #define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
-#endif	/* CONFIG_80MHz */

 /*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
@@ -265,17 +258,9 @@
 * power management and some other internal clocks
 */
 #define SCCR_MASK	SCCR_EBDF11
-#ifdef	CONFIG_80MHz	/* for 80 MHz, we use a 16 MHz clock * 5 */
-#define CFG_SCCR	(/* SCCR_TBS  | */ \
-			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+#define CFG_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 			 SCCR_DFALCD00)
-#else			/* up to 66 MHz we use a 1:1 clock */
-#define CFG_SCCR	(SCCR_TBS     | \
-			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
-			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
-			 SCCR_DFALCD00)
-#endif	/* CONFIG_80MHz */

 /*-----------------------------------------------------------------------
 * PCMCIA stuff
@@ -344,19 +329,8 @@
 /*
 * FLASH timing:
 */
-#if   defined(CONFIG_80MHz)
-/* 80 MHz CPU - 40 MHz bus: ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */
-#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | 0       | OR_CSNT_SAM | \
-				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
-#elif defined(CONFIG_66MHz)
-/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
 #define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
 				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
-#else		/*   50 MHz */
-/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
-#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
-				 OR_SCY_2_CLK | OR_EHTR | OR_BI)
-#endif	/*CONFIG_??MHz */

 #define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
 #define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
@@ -417,13 +391,9 @@
 * 66 Mhz => 66.000.000 / Divider = 129
 * 80 Mhz => 80.000.000 / Divider = 156
 */
-#if   defined(CONFIG_80MHz)
-#define CFG_MAMR_PTA		156
-#elif defined(CONFIG_66MHz)
-#define CFG_MAMR_PTA		129
-#else		/*   50 MHz */
-#define CFG_MAMR_PTA		 98
-#endif	/*CONFIG_??MHz */
+
+#define CFG_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
+#define CFG_MAMR_PTA	98

 /*
 * For 16 MBit, refresh rates could be 31.3 us
--- a/include/configs/TQM855M.h
+++ b/include/configs/TQM855M.h
@@ -283,15 +283,8 @@
 *-----------------------------------------------------------------------
 * Reset PLL lock status sticky bit, timer expired status bit and timer
 * interrupt status bit
- *
- * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
 */
-#ifdef	CONFIG_80MHz	/* for 80 MHz, we use a 16 MHz clock * 5 */
-#define CFG_PLPRCR							\
-		( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
-#else			/* up to 66 MHz we use a 1:1 clock */
 #define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
-#endif	/* CONFIG_80MHz */

 /*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
@@ -300,17 +293,9 @@
 * power management and some other internal clocks
 */
 #define SCCR_MASK	SCCR_EBDF11
-#ifdef	CONFIG_80MHz	/* for 80 MHz, we use a 16 MHz clock * 5 */
-#define CFG_SCCR	(/* SCCR_TBS  | */ \
-			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+#define CFG_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 			 SCCR_DFALCD00)
-#else			/* up to 66 MHz we use a 1:1 clock */
-#define CFG_SCCR	(SCCR_TBS     | \
-			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
-			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
-			 SCCR_DFALCD00)
-#endif	/* CONFIG_80MHz */

 /*-----------------------------------------------------------------------
 * PCMCIA stuff
@@ -379,19 +364,8 @@
 /*
 * FLASH timing:
 */
-#if   defined(CONFIG_80MHz)
-/* 80 MHz CPU - 40 MHz bus: ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */
-#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | 0       | OR_CSNT_SAM | \
-				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
-#elif defined(CONFIG_66MHz)
-/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
 #define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
 				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
-#else		/*   50 MHz */
-/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
-#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
-				 OR_SCY_2_CLK | OR_EHTR | OR_BI)
-#endif	/*CONFIG_??MHz */

 #define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
 #define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
@@ -452,13 +426,9 @@
 * 66 Mhz => 66.000.000 / Divider = 129
 * 80 Mhz => 80.000.000 / Divider = 156
 */
-#if   defined(CONFIG_80MHz)
-#define CFG_MAMR_PTA		156
-#elif defined(CONFIG_66MHz)
-#define CFG_MAMR_PTA		129
-#else		/*   50 MHz */
-#define CFG_MAMR_PTA		 98
-#endif	/*CONFIG_??MHz */
+
+#define CFG_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
+#define CFG_MAMR_PTA	98

 /*
 * For 16 MBit, refresh rates could be 31.3 us
--- a/include/configs/TQM860L.h
+++ b/include/configs/TQM860L.h
@@ -249,15 +249,8 @@
 *-----------------------------------------------------------------------
 * Reset PLL lock status sticky bit, timer expired status bit and timer
 * interrupt status bit
- *
- * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
 */
-#ifdef	CONFIG_80MHz	/* for 80 MHz, we use a 16 MHz clock * 5 */
-#define CFG_PLPRCR							\
-		( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
-#else			/* up to 66 MHz we use a 1:1 clock */
 #define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
-#endif	/* CONFIG_80MHz */

 /*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
@@ -266,17 +259,9 @@
 * power management and some other internal clocks
 */
 #define SCCR_MASK	SCCR_EBDF11
-#ifdef	CONFIG_80MHz	/* for 80 MHz, we use a 16 MHz clock * 5 */
-#define CFG_SCCR	(/* SCCR_TBS  | */ \
-			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+#define CFG_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 			 SCCR_DFALCD00)
-#else			/* up to 66 MHz we use a 1:1 clock */
-#define CFG_SCCR	(SCCR_TBS     | \
-			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
-			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
-			 SCCR_DFALCD00)
-#endif	/* CONFIG_80MHz */

 /*-----------------------------------------------------------------------
 * PCMCIA stuff
@@ -345,19 +330,8 @@
 /*
 * FLASH timing:
 */
-#if   defined(CONFIG_80MHz)
-/* 80 MHz CPU - 40 MHz bus: ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */
-#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | 0       | OR_CSNT_SAM | \
-				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
-#elif defined(CONFIG_66MHz)
-/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
 #define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
 				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
-#else		/*   50 MHz */
-/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
-#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
-				 OR_SCY_2_CLK | OR_EHTR | OR_BI)
-#endif	/*CONFIG_??MHz */

 #define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
 #define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
@@ -418,13 +392,9 @@
 * 66 Mhz => 66.000.000 / Divider = 129
 * 80 Mhz => 80.000.000 / Divider = 156
 */
-#if   defined(CONFIG_80MHz)
-#define CFG_MAMR_PTA		156
-#elif defined(CONFIG_66MHz)
-#define CFG_MAMR_PTA		129
-#else		/*   50 MHz */
-#define CFG_MAMR_PTA		 98
-#endif	/*CONFIG_??MHz */
+
+#define CFG_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
+#define CFG_MAMR_PTA	98

 /*
 * For 16 MBit, refresh rates could be 31.3 us
--- a/include/configs/TQM860M.h
+++ b/include/configs/TQM860M.h
@@ -250,15 +250,8 @@
 *-----------------------------------------------------------------------
 * Reset PLL lock status sticky bit, timer expired status bit and timer
 * interrupt status bit
- *
- * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
 */
-#ifdef	CONFIG_80MHz	/* for 80 MHz, we use a 16 MHz clock * 5 */
-#define CFG_PLPRCR							\
-		( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
-#else			/* up to 66 MHz we use a 1:1 clock */
 #define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
-#endif	/* CONFIG_80MHz */

 /*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
@@ -267,17 +260,9 @@
 * power management and some other internal clocks
 */
 #define SCCR_MASK	SCCR_EBDF11
-#ifdef	CONFIG_80MHz	/* for 80 MHz, we use a 16 MHz clock * 5 */
-#define CFG_SCCR	(/* SCCR_TBS  | */ \
-			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+#define CFG_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 			 SCCR_DFALCD00)
-#else			/* up to 66 MHz we use a 1:1 clock */
-#define CFG_SCCR	(SCCR_TBS     | \
-			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
-			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
-			 SCCR_DFALCD00)
-#endif	/* CONFIG_80MHz */

 /*-----------------------------------------------------------------------
 * PCMCIA stuff
@@ -346,19 +331,8 @@
 /*
 * FLASH timing:
 */
-#if   defined(CONFIG_80MHz)
-/* 80 MHz CPU - 40 MHz bus: ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */
-#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | 0       | OR_CSNT_SAM | \
-				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
-#elif defined(CONFIG_66MHz)
-/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
 #define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
 				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
-#else		/*   50 MHz */
-/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
-#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
-				 OR_SCY_2_CLK | OR_EHTR | OR_BI)
-#endif	/*CONFIG_??MHz */

 #define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
 #define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
@@ -419,13 +393,9 @@
 * 66 Mhz => 66.000.000 / Divider = 129
 * 80 Mhz => 80.000.000 / Divider = 156
 */
-#if   defined(CONFIG_80MHz)
-#define CFG_MAMR_PTA		156
-#elif defined(CONFIG_66MHz)
-#define CFG_MAMR_PTA		129
-#else		/*   50 MHz */
-#define CFG_MAMR_PTA		 98
-#endif	/*CONFIG_??MHz */
+
+#define CFG_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
+#define CFG_MAMR_PTA	98

 /*
 * For 16 MBit, refresh rates could be 31.3 us
--- a/include/configs/TQM862L.h
+++ b/include/configs/TQM862L.h
@@ -252,16 +252,8 @@
 *-----------------------------------------------------------------------
 * Reset PLL lock status sticky bit, timer expired status bit and timer
 * interrupt status bit
- *
- * If this is a 80 MHz or 100 MHz CPU,
- * set PLL multiplication factor to 5 (5 * 16 = 80, 5 * 20 = 100)
 */
-#if defined(CONFIG_80MHz) || defined(CONFIG_100MHz)
-#define CFG_PLPRCR							\
-		( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
-#else			/* up to 66 MHz we use a 1:1 clock */
 #define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
-#endif	/* CONFIG_80MHz | CONFIG_100MHz */

 /*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
@@ -270,17 +262,9 @@
 * power management and some other internal clocks
 */
 #define SCCR_MASK	SCCR_EBDF11
-#if defined(CONFIG_80MHz) || defined(CONFIG_100MHz) /* use 16/20 MHz * 5 */
-#define CFG_SCCR	(/* SCCR_TBS  | */ \
-			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+#define CFG_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 			 SCCR_DFALCD00)
-#else			/* up to 66 MHz we use a 1:1 clock */
-#define CFG_SCCR	(SCCR_TBS     | \
-			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
-			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
-			 SCCR_DFALCD00)
-#endif	/* CONFIG_80MHz | CONFIG_100MHz */

 /*-----------------------------------------------------------------------
 * PCMCIA stuff
@@ -349,24 +333,8 @@
 /*
 * FLASH timing:
 */
-#if defined(CONFIG_100MHz)
-/* 100 MHz CPU - 50 MHz bus:
- * ACS = 01, TRLX = 0, CSNT = 0, SCY = 7, EHTR = 0 */
-#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV4  | OR_SCY_7_CLK | OR_BI)
-#elif defined(CONFIG_80MHz)
-/* 80 MHz CPU - 40 MHz bus:
- * ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */
-#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | 0       | OR_CSNT_SAM | \
-				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
-#elif defined(CONFIG_66MHz)
-/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
 #define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
 				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
-#else		/*   50 MHz */
-/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
-#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
-				 OR_SCY_2_CLK | OR_EHTR | OR_BI)
-#endif	/*CONFIG_??MHz */

 #define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
 #define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
@@ -428,15 +396,9 @@
 *  80 Mhz =>  80.000.000 / Divider = 156
 * 100 Mhz => 100.000.000 / Divider = 195
 */
-#if   defined(CONFIG_100MHz)
-#define CFG_MAMR_PTA		195
-#elif defined(CONFIG_80MHz)
-#define CFG_MAMR_PTA		156
-#elif defined(CONFIG_66MHz)
-#define CFG_MAMR_PTA		129
-#else		/*   50 MHz */
-#define CFG_MAMR_PTA		 98
-#endif	/*CONFIG_??MHz */
+
+#define CFG_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
+#define CFG_MAMR_PTA	98

 /*
 * For 16 MBit, refresh rates could be 31.3 us
--- a/include/configs/TQM862M.h
+++ b/include/configs/TQM862M.h
@@ -253,16 +253,8 @@
 *-----------------------------------------------------------------------
 * Reset PLL lock status sticky bit, timer expired status bit and timer
 * interrupt status bit
- *
- * If this is a 80 MHz or 100 MHz CPU,
- * set PLL multiplication factor to 5 (5 * 16 = 80, 5 * 20 = 100)
 */
-#if defined(CONFIG_80MHz) || defined(CONFIG_100MHz)
-#define CFG_PLPRCR							\
-		( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
-#else			/* up to 66 MHz we use a 1:1 clock */
 #define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
-#endif	/* CONFIG_80MHz | CONFIG_100MHz */

 /*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
@@ -271,17 +263,9 @@
 * power management and some other internal clocks
 */
 #define SCCR_MASK	SCCR_EBDF11
-#if defined(CONFIG_80MHz) || defined(CONFIG_100MHz) /* use 16/20 MHz * 5 */
-#define CFG_SCCR	(/* SCCR_TBS  | */ \
-			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+#define CFG_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 			 SCCR_DFALCD00)
-#else			/* up to 66 MHz we use a 1:1 clock */
-#define CFG_SCCR	(SCCR_TBS     | \
-			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
-			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
-			 SCCR_DFALCD00)
-#endif	/* CONFIG_80MHz | CONFIG_100MHz */

 /*-----------------------------------------------------------------------
 * PCMCIA stuff
@@ -350,24 +334,8 @@
 /*
 * FLASH timing:
 */
-#if defined(CONFIG_100MHz)
-/* 100 MHz CPU - 50 MHz bus:
- * ACS = 01, TRLX = 0, CSNT = 0, SCY = 7, EHTR = 0 */
-#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV4  | OR_SCY_7_CLK | OR_BI)
-#elif defined(CONFIG_80MHz)
-/* 80 MHz CPU - 40 MHz bus:
- * ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */
-#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | 0       | OR_CSNT_SAM | \
-				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
-#elif defined(CONFIG_66MHz)
-/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
 #define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
 				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
-#else		/*   50 MHz */
-/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
-#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
-				 OR_SCY_2_CLK | OR_EHTR | OR_BI)
-#endif	/*CONFIG_??MHz */

 #define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
 #define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
@@ -429,15 +397,9 @@
 *  80 Mhz =>  80.000.000 / Divider = 156
 * 100 Mhz => 100.000.000 / Divider = 195
 */
-#if   defined(CONFIG_100MHz)
-#define CFG_MAMR_PTA		195
-#elif defined(CONFIG_80MHz)
-#define CFG_MAMR_PTA		156
-#elif defined(CONFIG_66MHz)
-#define CFG_MAMR_PTA		129
-#else		/*   50 MHz */
-#define CFG_MAMR_PTA		 98
-#endif	/*CONFIG_??MHz */
+
+#define CFG_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
+#define CFG_MAMR_PTA	98

 /*
 * For 16 MBit, refresh rates could be 31.3 us
--- a/include/configs/versatile.h
+++ b/include/configs/versatile.h
@@ -103,7 +103,7 @@
 #include <cmd_confdefs.h>

 #define CONFIG_BOOTDELAY	2
-#define CONFIG_BOOTARGS	"root=/dev/nfs mem=128M ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0"
+#define CONFIG_BOOTARGS "root=/dev/nfs mem=128M ip=dhcp netdev=25,0,0xf1010000,0xf1010010,eth0"
 /*#define CONFIG_BOOTCOMMAND "bootp ; bootm" */

 /*
--- a/include/miiphy.h
+++ b/include/miiphy.h
@@ -93,6 +93,11 @@ int  miiphy_link(unsigned char addr);
 #define PHY_BMCR_DPLX		0x0100
 #define PHY_BMCR_COL_TST	0x0080

+#define PHY_BMCR_SPEED_MASK     0x2040
+#define PHY_BMCR_1000_MBPS      0x0040
+#define PHY_BMCR_100_MBPS       0x2000
+#define PHY_BMCR_10_MBPS        0x0000
+
 /* phy BMSR */
 #define PHY_BMSR_100T4		0x8000
 #define PHY_BMSR_100TXF		0x4000
@@ -118,6 +123,10 @@ int  miiphy_link(unsigned char addr);
 #define PHY_ANLPAR_10		0x0020
 #define PHY_ANLPAR_100		0x0380	    /* we can run at 100 */

+#define PHY_ANLPAR_PSB_MASK     0x001f
+#define PHY_ANLPAR_PSB_802_3    0x0001
+#define PHY_ANLPAR_PSB_802_9    0x0002
+
 /* PHY_1000BTSR */
 #define PHY_1000BTSR_MSCF       0x8000
 #define PHY_1000BTSR_MSCR       0x4000
--- a/include/nios-io.h
+++ b/include/nios-io.h
@@ -167,4 +167,17 @@ typedef volatile struct nios_asmi_t {
 #define NIOS_ASMI_IEOP		(1 << 9)	/* rx eop int ena */
 #define NIOS_ASMI_SSO		(1 << 10)	/* slave select enable */

+/*------------------------------------------------------------------------
+ * JTAG UART
+ *----------------------------------------------------------------------*/
+typedef volatile struct nios_jtag_t {
+	unsigned short	rxcntl;			/* Rx data/cntl reg */
+	unsigned short	txcntl;			/* Tx data/cntl reg */
+	unsigned short	errcntl;		/* Err dta/cntl reg */
+}nios_jtag_t;
+
+/* status register */
+#define NIOS_JTAG_TRDY		(1 << 8)	/* tx ready bit */
+#define NIOS_JTAG_RRDY		(1 << 8)	/* rx ready bit */
+
 #endif /* __NIOSIO_H__ */
--- a/include/pci_ids.h
+++ b/include/pci_ids.h
--- a/include/version.h
+++ b/include/version.h
@@ -24,6 +24,6 @@
 #ifndef	__VERSION_H__
 #define	__VERSION_H__

-#define	U_BOOT_VERSION	"U-Boot 1.1.1"
+#define	U_BOOT_VERSION	"U-Boot 1.1.2"

 #endif	/* __VERSION_H__ */
--- a/lib_mips/board.c
+++ b/lib_mips/board.c
@@ -190,8 +190,8 @@ void board_init_f(ulong bootflag)
 	void copy_code (ulong);
 #endif

-		/* Pointer is writable since we allocated a register for it.
-		 */
+	/* Pointer is writable since we allocated a register for it.
+	 */
 	gd = &gd_data;
 	memset ((void *)gd, 0, sizeof (gd_t));

@@ -207,33 +207,27 @@ void board_init_f(ulong bootflag)
 	 */
 	addr = CFG_SDRAM_BASE + gd->ram_size;

-		/* We can reserve some RAM "on top" here.
-		 */
+	/* We can reserve some RAM "on top" here.
+	 */

-		/* round down to next 4 kB limit.
-		 */
+	/* round down to next 4 kB limit.
+	 */
 	addr &= ~(4096 - 1);
-#ifdef DEBUG
-	printf ("Top of RAM usable for U-Boot at: %08lx\n", addr);
-#endif
+	debug ("Top of RAM usable for U-Boot at: %08lx\n", addr);

-		/* Reserve memory for U-Boot code, data & bss
-		 * round down to next 16 kB limit
-		 */
+	/* Reserve memory for U-Boot code, data & bss
+	 * round down to next 16 kB limit
+	 */
 	addr -= len;
 	addr &= ~(16 * 1024 - 1);

-#ifdef DEBUG
-	printf ("Reserving %ldk for U-Boot at: %08lx\n", len >> 10, addr);
-#endif
+	debug ("Reserving %ldk for U-Boot at: %08lx\n", len >> 10, addr);

-	 	/* Reserve memory for malloc() arena.
-		 */
+	 /* Reserve memory for malloc() arena.
+	 */
 	addr_sp = addr - TOTAL_MALLOC_LEN;
-#ifdef DEBUG
-	printf ("Reserving %dk for malloc() at: %08lx\n",
+	debug ("Reserving %dk for malloc() at: %08lx\n",
 			TOTAL_MALLOC_LEN >> 10, addr_sp);
-#endif

 	/*
 	 * (permanently) allocate a Board Info struct
@@ -242,25 +236,20 @@ void board_init_f(ulong bootflag)
 	addr_sp -= sizeof(bd_t);
 	bd = (bd_t *)addr_sp;
 	gd->bd = bd;
-#ifdef DEBUG
-	printf ("Reserving %d Bytes for Board Info at: %08lx\n",
+	debug ("Reserving %d Bytes for Board Info at: %08lx\n",
 			sizeof(bd_t), addr_sp);
-#endif
+
 	addr_sp -= sizeof(gd_t);
 	id = (gd_t *)addr_sp;
-#ifdef DEBUG
-	printf ("Reserving %d Bytes for Global Data at: %08lx\n",
+	debug ("Reserving %d Bytes for Global Data at: %08lx\n",
 			sizeof (gd_t), addr_sp);
-#endif

-	 	/* Reserve memory for boot params.
-		 */
+ 	/* Reserve memory for boot params.
+	 */
 	addr_sp -= CFG_BOOTPARAMS_LEN;
 	bd->bi_boot_params = addr_sp;
-#ifdef DEBUG
-	printf ("Reserving %dk for malloc() at: %08lx\n",
+	debug ("Reserving %dk for boot params() at: %08lx\n",
 			CFG_BOOTPARAMS_LEN >> 10, addr_sp);
-#endif

 	/*
 	 * Finally, we set up a new (bigger) stack.
@@ -272,9 +261,8 @@ void board_init_f(ulong bootflag)
 	addr_sp &= ~0xF;
 	*((ulong *) addr_sp)-- = 0;
 	*((ulong *) addr_sp)-- = 0;
-#ifdef DEBUG
-	printf ("Stack Pointer at: %08lx\n", addr_sp);
-#endif
+	debug ("Stack Pointer at: %08lx\n", addr_sp);
+
 	/*
 	 * Save local variables to board info struct
 	 */
@@ -321,9 +309,7 @@ void board_init_r (gd_t *id, ulong dest_addr)
 	gd = id;
 	gd->flags |= GD_FLG_RELOC;	/* tell others: relocation done */

-#ifdef DEBUG
-	printf ("Now running in RAM - U-Boot at: %08lx\n", dest_addr);
-#endif
+	debug ("Now running in RAM - U-Boot at: %08lx\n", dest_addr);

 	gd->reloc_off = dest_addr - CFG_MONITOR_BASE;

--- a/lib_nios/board.c
+++ b/lib_nios/board.c
@@ -49,7 +49,6 @@

 extern void malloc_bin_reloc (void);
 typedef int (init_fnc_t) (void);
-extern unsigned _vectors[];

 /*
 * Begin and End of memory area for malloc(), and current "brk"
@@ -120,10 +119,6 @@ void board_init (void)
 	gd = (gd_t *)CFG_GBL_DATA_OFFSET;
 	memset( gd, 0, CFG_GBL_DATA_SIZE );

-	/* Copy exception vectors to the correct location.
-	 */
-	memcpy( (void *)CFG_VECT_BASE, _vectors, 256 );
-
 	gd->bd = (bd_t *)(gd+1);	/* At end of global data */
 	gd->baudrate = CONFIG_BAUDRATE;
 	gd->cpu_clk = CONFIG_SYS_CLK_FREQ;
--- a/lib_ppc/board.c
+++ b/lib_ppc/board.c
@@ -265,6 +265,9 @@ init_fnc_t *init_sequence[] = {

 #if !defined(CONFIG_TQM866M)
 	get_clocks,		/* get CPU and bus clocks (etc.) */
+#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M)
+	adjust_sdram_tbs_8xx,
+#endif
 	init_timebase,
 #endif
 #ifdef CFG_ALLOC_DPRAM
@@ -814,7 +817,7 @@ void board_init_r (gd_t *id, ulong dest_addr)
 #endif

 #if defined(CONFIG_TQM8xxL) || defined(CONFIG_TQM8260) || \
-    defined(CONFIG_CCM)
+    defined(CONFIG_CCM) || defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X)
 	load_sernum_ethaddr ();
 #endif
 	/* IP Address */
--- a/net/eth.c
+++ b/net/eth.c
@@ -122,7 +122,8 @@ int eth_initialize(bd_t *bis)
 #ifdef CONFIG_DB64460
 	mv6446x_eth_initialize(bis);
 #endif
-#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || ( defined(CONFIG_440) && !defined(CONFIG_NET_MULTI) )
+#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \
+  ( defined(CONFIG_440) && !defined(CONFIG_NET_MULTI) )
 	ppc_4xx_eth_initialize(bis);
 #endif
 #if defined(CONFIG_440) && defined(CONFIG_NET_MULTI)
@@ -134,6 +135,24 @@ int eth_initialize(bd_t *bis)
 #ifdef CONFIG_PLB2800_ETHER
 	plb2800_eth_initialize(bis);
 #endif
+#ifdef SCC_ENET
+	scc_initialize(bis);
+#endif
+#if defined(FEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
+	fec_initialize(bis);
+#endif
+#if defined(CONFIG_MPC5xxx_FEC)
+	mpc5xxx_fec_initialize(bis);
+#endif
+#if defined(CONFIG_SK98)
+	skge_initialize(bis);
+#endif
+#ifdef CONFIG_TSEC_ENET
+	tsec_initialize(bis);
+#endif
+#if defined(CONFIG_AU1X00)
+	au1x00_enet_initialize(bis);
+#endif
 #ifdef CONFIG_E1000
 	e1000_initialize(bis);
 #endif
@@ -158,24 +177,6 @@ int eth_initialize(bd_t *bis)
 #ifdef CONFIG_NS8382X
 	ns8382x_initialize(bis);
 #endif
-#ifdef SCC_ENET
-	scc_initialize(bis);
-#endif
-#if defined(FEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
-	fec_initialize(bis);
-#endif
-#if defined(CONFIG_MPC5xxx_FEC)
-	mpc5xxx_fec_initialize(bis);
-#endif
-#if defined(CONFIG_SK98)
-	skge_initialize(bis);
-#endif
-#ifdef CONFIG_TSEC_ENET
-       tsec_initialize(bis);
-#endif
-#if defined(CONFIG_AU1X00)
-	au1x00_enet_initialize(bis);
-#endif
 #if defined(CONFIG_RTL8139)
 	rtl8139_initialize(bis);
 #endif
@@ -213,13 +214,14 @@ int eth_initialize(bd_t *bis)
 				if (memcmp(dev->enetaddr, "\0\0\0\0\0\0", 6) &&
 				    memcmp(dev->enetaddr, env_enetaddr, 6))
 				{
-					printf("\nWarning: %s MAC addresses don't match:\n", dev->name);
-					printf("Address in SROM is         "
+					printf ("\nWarning: %s MAC addresses don't match:\n",
+						dev->name);
+					printf ("Address in SROM is         "
 					       "%02X:%02X:%02X:%02X:%02X:%02X\n",
 					       dev->enetaddr[0], dev->enetaddr[1],
 					       dev->enetaddr[2], dev->enetaddr[3],
 					       dev->enetaddr[4], dev->enetaddr[5]);
-					printf("Address in environment is  "
+					printf ("Address in environment is  "
 					       "%02X:%02X:%02X:%02X:%02X:%02X\n",
 					       env_enetaddr[0], env_enetaddr[1],
 					       env_enetaddr[2], env_enetaddr[3],
@@ -341,8 +343,7 @@ void eth_try_another(int first_restart)
 	if (!eth_current)
 		return;

-	if (first_restart)
-	{
+	if (first_restart) {
 		first_failed = eth_current;
 	}

@@ -357,8 +358,7 @@ void eth_try_another(int first_restart)
 	}
 #endif

-	if (first_failed == eth_current)
-	{
+	if (first_failed == eth_current) {
 		NetRestartWrap = 1;
 	}
 }
--- a/net/net.c
+++ b/net/net.c
@@ -1613,14 +1613,14 @@ ushort string_to_VLAN(char *s)
 	ushort id;

 	if (s == NULL)
-		return VLAN_NONE;
+		return htons(VLAN_NONE);

 	if (*s < '0' || *s > '9')
 		id = VLAN_NONE;
 	else
 		id = (ushort)simple_strtoul(s, NULL, 10);

-	return id;
+	return htons(id);
 }

 void print_IPaddr (IPaddr_t x)
--- a/nios_config.mk
+++ b/nios_config.mk
@@ -22,4 +22,4 @@
 # MA 02111-1307 USA
 #

-PLATFORM_CPPFLAGS += -m32 -DCONFIG_NIOS -D__NIOS__ -ffixed-g7
+PLATFORM_CPPFLAGS += -m32 -DCONFIG_NIOS -D__NIOS__ -ffixed-g7 -gstabs
Author	SHA1	Message	Date
wdenk	6945979126	Fix CONFIG_ETH*ADDR for Ocotea board. Sort Makefile. Update docs.	2004-05-29 16:53:29 +00:00
wdenk	e4cc71aa44	Patch by Scott McNutt, 25 Apr 2004: Add Nios GDB/JTAG Console support: - Add stubs to support gdb via JTAG. - Add support for console over JTAG. - Minor cleanup.	2004-05-19 21:33:14 +00:00
wdenk	10767ccb86	Add support for CATcenter board (based on PPChameleon ME module)	2004-05-13 13:23:58 +00:00
wdenk	02b11f8e09	Patch by Klaus Heydeck, 12 May 2004: Using external watchdog for KUP4 boards in mpc8xx/cpu.c; load_sernum_ethaddr() for KUP4 boards in lib_ppc/board.c; various changes to KUP4 board specific files	2004-05-12 22:54:36 +00:00
wdenk	6c1362cf63	Fix minor network problem on MPC5200	2004-05-12 22:18:31 +00:00
wdenk	953e2062c0	Fix handling of low-speed devices with SL811 USB controller (again).	2004-05-12 13:20:19 +00:00
wdenk	9d9e283790	Add some limited support for low-speed devices to SL811 USB controller (at least "usb reset" now passes successfully and "usb info" displays correct information)	2004-05-11 21:53:55 +00:00
wdenk	baac607c13	Change init sequence for multiple network interfaces: initialize on-chip interfaces before external cards.	2004-05-08 20:33:20 +00:00
wdenk	32877d66aa	* Fix memory leak in the NAND-specific JFFS2 code * Fix SL811 USB controller when attached to a USB hub	2004-05-05 19:44:41 +00:00
wdenk	62b4ac98a4	* Fix config option spelling in PM520 config file * Fix PHY discovery problem in cpu/mpc8xx/fec.c (introduced by patches by Pantelis Antoniou, 30 Mar 2004)	2004-05-05 08:31:53 +00:00
wdenk	2729af9d54	* Fix minor NAND JFFS2 related issue * Fixes for SL811 USB controller: - implement workaround for broken memory stick - improve error handling * Increase packet send timeout to 10 ms in cpu/mpc8xx/scc.c to better cope with congested networks.	2004-05-03 20:45:30 +00:00
wdenk	08f1080c9c	Make compile clean.	2004-04-25 16:40:11 +00:00
wdenk	fc1cfcdb12	* Back out Patch by Christian Hohnstaedt, 23 Apr 2004: (JFFS2 speed enhancements) because of using non-public data (PHYS_FLASH_SECT_SIZE) * Patch by Travis Sawyer, 23 Apr 2004: Fix VSC/CIS 8201 phy descrambler interoperability timing due to errata from Vitesse Semiconductor.	2004-04-25 15:41:35 +00:00
wdenk	0b8fa03b6d	* Patch by Christian Hohnstaedt, 23 Apr 2004: JFFS2 speed enhancements: - repair header CRC calculation in jffs2_1pass.c - add eraseblock size to the partition information to skip empty eraseblocks if we find more then 4k of free space. - The JFFS2 scanner is now fast enough to remove the spinning wheel so #ifdef-ed out. - add watchdog calls in long running loops * Patch by Philippe Robin, 22 Apr 2004: Fix ethernet configuration for "versatile" board * Patch by Kshitij Gupta, 21 Apr 2004: Remove busy loop and use MPU timer fr usleep() on OMAP1510/1610 boards * Patch by Steven Scholz, 24 Feb 2004: Fix a bug in AT91RM9200 ethernet driver: The MII interface is now initialized before accessing the PHY. * Cleanup PCI ID's	2004-04-25 14:37:29 +00:00
wdenk	b9711de102	* Patch by John Kerl, 19 Apr 2004: Use U-boot's miiphy.h for PHY register names, rather than introducing a new header file. * Update pci_ids.h from linux-2.4.26 * Patch by Masami Komiya, 19 Apr 2004: Fix problem cause by VLAN function on little endian architecture without VLAN environment	2004-04-25 13:18:40 +00:00
wdenk	e9132ea94c	Clean up the TQM8xx_YYMHz configurations; allow to use the same binary image for all clock frequencies. Implement run-time optimization of flash access timing based on the actual bus frequency.	2004-04-24 23:23:30 +00:00