* Fix debug code in omap5912osk flash driver

* Add support for MPC8247 based "IDS8247" board.
Add support for 2 x TSEC interfaces on the TQM8540 board.
2026-06-13 15:03:58 +03:00 · 2005-05-12 22:48:09 +00:00 · 2005-05-10 15:51:35 +00:00 · 2005-05-09 10:17:32 +00:00 · 2005-05-07 19:06:32 +00:00 · 2005-05-05 09:51:44 +00:00
106 changed files with 9676 additions and 3817 deletions
--- a/110
+++ b/110
@@ -2,6 +2,114 @@
 Changes for U-Boot 1.1.3:
 ======================================================================

+* Fix debug code in omap5912osk flash driver
+
+* Add support for MPC8247 based "IDS8247" board.
+
+* Add support for 2 x TSEC interfaces on the TQM8540 board.
+
+* On LWMON we must use the watchdog to reset the board as the CPU
+  genereated HRESET pulse is too short to reset the external
+  circuitry.
+
+* Add test tool to exercise SDRAM accesses in burst mode
+  (as standalone program, MPC8xx/PowerPC only)
+
+* Increase CFG_MONITOR_LEN for Rattler board to match actual code
+  size.
+
+* Major upate of JFFS2 code; now in sync with snapshot of MTD CVS of
+  March 13, 2005); new configuration option CONFIG_JFFS2_LZO_LZARI
+  added to support LZO and LZARI compression modes (undefined by
+  default).
+
+* Fix problem with symbolic links in JFFS2 code.
+
+* Use linker ASSERT statement to prevent undetected overlapping of
+  sections on PPChameleon board; other boards might use this, too.
+
+* Patch by Stefan Roese, 03 May 2005:
+  Update for P3G4
+  Fix problems in cmd_universe.c
+
+* Patch by Matthias Fuchs, 03 May 2005:
+  Added missing variable declaration in cmd_nand.c
+  Modified CFG_PCI_PTM1MS in configs/PLU405.h to map 128MB ram
+
+* Fix INKA4x0: use CS1 as gpio_wkup_6 output
+
+* Fix bug in the SDRAM initialization code for canmb, IceCube and
+  PM520 boards.
+  Fix PHY address for canmb board.
+
+* Cleanup serial console baudrate calculation on AT91RM9200;
+  get rid of obsolete CFG_AT91C_BRGR_DIVISOR definition
+
+* Patch by Matthias Fuchs, 18 Apr 2005:
+  Make PCI target address spaces on PMC405 and CPCI405 boards
+  configurable via environment variables
+
+* Auto-size RAM on canmb board.
+
+* Add support for canmb board
+
+* Patch by Stefan Roese, 13 Apr 2005:
+  Update for esd apc405
+
+* Fixes for TQM8560 board:
+  - fix clock rates
+  - remove debug messages
+  - fix flash sector protection
+
+* Patch by Steven Scholz, 07 Apr 2005:
+  Add i2c_reg_write() and i2c_reg_write() for at91rm9200 I2C
+
+* Patches by Steven Scholz, 07 Apr 2005:
+  Fix compiler warning in altera.c
+  Fix warning in cpu/arm920t/at91rm9200/i2c.c
+
+* Patch by Ladislav Michl, 06 Apr 2005:
+  Fix voiceblue configuration.
+
+* Patch by Stefan Roese, 06 Apr 2005:
+  Updates for OCOTEA board:
+  - Changed U-Boot size from 512kByte to 256kByte
+  - Fixed flash driver to support boot from soldered user flash
+  - Added README for switch from PIBS firmware to U-Boot
+
+* Patch by Travis Sawyer, 05 Apr 2005:
+  - Change timer frequency for ppc 440 from 10 ms to 1 ms.
+    Problem found by Andrew Wozniak.
+
+* Patch by Steven Scholz, 06 Apr 2005:
+  - creating SoC subdir for Atmel AT91RM9200 cpu/arm920t/at91rm9200
+  - moving code out of cpu/at91rm9200 into cpu/arm920t/at91rm9200
+
+* Patches by Robert Whaley, 29 Nov 2004:
+  - update the pxa-regs.h file for PXA27x chips
+  - add PXA27x based ADSVIX board
+  - add support for MMC on PXA27x processors
+
+* Patch by Andrew E. Mileski, 28 Nov 2004:
+  Fix PPC4xx SPD SDRAM detection bug
+
+* Patch by Hiroshi Ito, 26 Nov 2004:
+  Fix logic of "test -z" and "test -n" commands
+
+* Patch by Ladislav Michl, 05 Apr 2005:
+  Add support for VoiceBlue board.
+
+* Patch by Ladislav Michl, 05 Apr 2005:
+  Fix netboot_common() prototypes.
+
+* Patch by Steven Scholz, 05 Apr 2005:
+  Use i.MX watchdog timer for reset_cpu()
+
+* Patch by Steven Scholz, 05 Apr 2005:
+  Move reset_cpu() out of cpu/arm920t/start.S into the SoC specific
+  subdirectories cpu/arm920t/imx/ and cpu/arm920t/s3c24x0/
+  (now in interupts.c)
+
 * Add support for MPC8220 based "sorcery" board.

 * Add support for TQM8560 board.
@@ -28,7 +136,7 @@ Changes for U-Boot 1.1.3:

 * Patch by Tolunay Orkun, 16 November 2004:
  fix incorrect onboard Xilinx CPLD base address
-  
+
 * Patch by Jerry Van Baren, 08 Nov 2004:
  - Add low-boot option for MPC8260ADS board (if lowboot is selected,
    the jumper for the HRCW source should select flash. If lowboot is
--- a/4
+++ b/4
@@ -402,6 +402,10 @@ N: Christian Vejlbo
 E: christian.vejlbo@tellabs.com
 D: FADS860T ethernet support

+N: Robert Whaley
+E: rwhaley@applieddata.net
+D: Port to ARM PXA27x adsvix SBC
+
 N: Martin Winistoerfer
 E: martinwinistoerfer@gmx.ch
 D: Port to MPC555/556 microcontrollers and support for cmi board
--- a/8
+++ b/8
@@ -157,7 +157,7 @@ LIST_ARM9="	\
 	lpd7a400	mx1ads		mx1fs2		omap1510inn	\
 	omap1610h2	omap1610inn	omap730p2	scb9328		\
 	smdk2400	smdk2410	trab		VCMA9		\
-	versatile							\
+	versatile	voiceblue					\
 "

 #########################################################################
@@ -170,9 +170,9 @@ LIST_ARM11="omap2420h4"
 #########################################################################

 LIST_pxa="	\
-	cerf250		cradle		csb226		innokom		\
-	lubbock		wepep250	xaeniax		xm250		\
-	xsengine							\
+	adsvix		cerf250		cradle		csb226		\
+	innokom		lubbock		wepep250	xaeniax		\
+	xm250		xsengine							\
 "

 LIST_ixp="ixdp425"
--- a/43
+++ b/43
@@ -1,5 +1,5 @@
 #
-# (C) Copyright 2000-2004
+# (C) Copyright 2000-2005
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # See file CREDITS for list of people who contributed to this
@@ -215,6 +215,9 @@ unconfig:
 ## MPC5xx Systems
 #########################################################################

+canmb_config:	unconfig
+	@./mkconfig -a canmb ppc mpc5xxx canmb
+
 cmi_mpc5xx_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc5xx cmi

@@ -984,6 +987,9 @@ gw8260_config:	unconfig
 hymod_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8260 hymod

+IDS8247_config:	unconfig
+	@./mkconfig $(@:_config=) ppc mpc8260 ids8247
+
 IPHASE4539_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8260 iphase4539

@@ -1285,6 +1291,12 @@ xtract_omap1610xxx = $(subst _cs0boot,,$(subst _cs3boot,,$(subst _cs_autoboot,,$

 xtract_omap730p2 = $(subst _cs0boot,,$(subst _cs3boot,, $(subst _config,,$1)))

+at91rm9200dk_config	:	unconfig
+	@./mkconfig $(@:_config=) arm arm920t at91rm9200dk NULL at91rm9200
+
+cmc_pu2_config	:	unconfig
+	@./mkconfig $(@:_config=) arm arm920t cmc_pu2 NULL at91rm9200
+
 integratorap_config :	unconfig
 	@./mkconfig $(@:_config=) arm arm926ejs integratorap

@@ -1382,6 +1394,19 @@ VCMA9_config	:	unconfig
 versatile_config :	unconfig
 	@./mkconfig $(@:_config=) arm arm926ejs versatile

+voiceblue_smallflash_config	\
+voiceblue_config:	unconfig
+	@if [ "$(findstring _smallflash_,$@)" ] ; then \
+		echo "... boot from lower flash bank" ; \
+		echo "#define VOICEBLUE_SMALL_FLASH" >>include/config.h ; \
+		echo "VOICEBLUE_SMALL_FLASH=y" >board/voiceblue/config.tmp ; \
+	else \
+		echo "... boot from upper flash bank" ; \
+		>include/config.h ; \
+		echo "VOICEBLUE_SMALL_FLASH=n" >board/voiceblue/config.tmp ; \
+	fi
+	@./mkconfig -a voiceblue arm arm925t voiceblue
+
 #########################################################################
 ## S3C44B0 Systems
 #########################################################################
@@ -1405,20 +1430,13 @@ modnet50_config :	unconfig
 evb4510_config :	unconfig
 	@./mkconfig $(@:_config=) arm arm720t evb4510

-#########################################################################
-## AT91RM9200 Systems
-#########################################################################
-
-at91rm9200dk_config	:	unconfig
-	@./mkconfig $(@:_config=) arm at91rm9200 at91rm9200dk
-
-cmc_pu2_config	:	unconfig
-	@./mkconfig $(@:_config=) arm at91rm9200 cmc_pu2
-
 #########################################################################
 ## XScale Systems
 #########################################################################

+adsvix_config	:	unconfig
+	@./mkconfig $(@:_config=) arm pxa adsvix
+
 cerf250_config :	unconfig
 	@./mkconfig $(@:_config=) arm pxa cerf250

@@ -1636,7 +1654,8 @@ clean:
 		| xargs rm -f
 	rm -f examples/hello_world examples/timer \
 	      examples/eepro100_eeprom examples/sched \
-	      examples/mem_to_mem_idma2intr examples/82559_eeprom
+	      examples/mem_to_mem_idma2intr examples/82559_eeprom \
+	      examples/test_burst
 	rm -f tools/img2srec tools/mkimage tools/envcrc tools/gen_eth_addr
 	rm -f tools/mpc86x_clk tools/ncb
 	rm -f tools/easylogo/easylogo tools/bmp_logo
--- a/25
+++ b/25
@@ -126,12 +126,12 @@ Directory Hierarchy:
  - 74xx_7xx	Files specific to Freescale MPC74xx and 7xx CPUs
  - arm720t	Files specific to ARM 720 CPUs
  - arm920t	Files specific to ARM 920 CPUs
+    - at91rm9200 Files specific to Atmel AT91RM9200 CPU
    - imx	Files specific to Freescale MC9328 i.MX CPUs
    - s3c24x0	Files specific to Samsung S3C24X0 CPUs
  - arm925t	Files specific to ARM 925 CPUs
  - arm926ejs	Files specific to ARM 926 CPUs
  - arm1136	Files specific to ARM 1136 CPUs
-  - at91rm9200	Files specific to Atmel AT91RM9200 CPUs
  - i386	Files specific to i386 CPUs
  - ixp		Files specific to Intel XScale IXP CPUs
  - mcf52x2	Files specific to Freescale ColdFire MCF52x2 CPUs
@@ -2132,14 +2132,14 @@ Low Level (hardware related) configuration options:
 - CONFIG_SKIP_LOWLEVEL_INIT
 - CONFIG_SKIP_RELOCATE_UBOOT

-                [ARM only] If these variables are defined, then
-                certain low level initializations (like setting up
-                the memory controller) are omitted and/or U-Boot does
-                not relocate itself into RAM.
-                Normally these variables MUST NOT be defined. The
-                only exception is when U-Boot is loaded (to RAM) by
-                some other boot loader or by a debugger which
-                performs these intializations itself.
+		[ARM only] If these variables are defined, then
+		certain low level initializations (like setting up
+		the memory controller) are omitted and/or U-Boot does
+		not relocate itself into RAM.
+		Normally these variables MUST NOT be defined. The
+		only exception is when U-Boot is loaded (to RAM) by
+		some other boot loader or by a debugger which
+		performs these intializations itself.


 Building the Software:
@@ -3081,8 +3081,7 @@ Booting assumes that (the first part of) the image booted is a
 stage-2 loader which in turn loads and then invokes the kernel
 proper. Loader sources will eventually appear in the NetBSD source
 tree (probably in sys/arc/mpc8xx/stand/u-boot_stage2/); in the
-meantime, send mail to bruno@exet-ag.de and/or wd@denx.de for
-details.
+meantime, see ftp://ftp.denx.de/pub/u-boot/ppcboot_stage2.tar.gz


 Implementation Internals:
@@ -3382,6 +3381,7 @@ Since the number of patches for U-Boot is growing, we need to
 establish some rules. Submissions which do not conform to these rules
 may be rejected, even when they contain important and valuable stuff.

+Patches shall be sent to the u-boot-users mailing list.

 When you send a patch, please include the following information with
 it:
@@ -3439,3 +3439,6 @@ Notes:
  (using #ifdef), and the resulting code with the new feature
  disabled must not need more memory than the old code without your
  modification.
+
+* Remember that there is a size limit of 40 kB per message on the
+  u-boot-users mailing list. Compression may help.
--- a/board/adsvix/Makefile
+++ b/board/adsvix/Makefile
@@ -0,0 +1,48 @@
+
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= adsvix.o pcmcia.o
+SOBJS	:= lowlevel_init.o pxavoltage.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
--- a/board/adsvix/adsvix.c
+++ b/board/adsvix/adsvix.c
@@ -0,0 +1,77 @@
+/*
+ * (C) Copyright 2004
+ * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
+ *
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* memory and cpu-speed are setup before relocation */
+	/* so we do _nothing_ here */
+
+	/* arch number of ADSVIX-Board */
+	gd->bd->bi_arch_number = 620;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0xa000003c;
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	setenv("stdout", "serial");
+	setenv("stderr", "serial");
+	return 0;
+}
+
+
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
+	gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
+	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
+	gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
+
+	return 0;
+}
--- a/board/adsvix/config.mk
+++ b/board/adsvix/config.mk
@@ -0,0 +1 @@
+TEXT_BASE = 0xa1700000
--- a/board/adsvix/lowlevel_init.S
+++ b/board/adsvix/lowlevel_init.S
@@ -0,0 +1,466 @@
+/*
+ * This was originally from the Lubbock u-boot port.
+ *
+ * Most of this taken from Redboot hal_platform_setup.h with cleanup
+ *
+ * NOTE: I haven't clean this up considerably, just enough to get it
+ * running. See hal_platform_setup.h for the source. See
+ * board/cradle/lowlevel_init.S for another PXA250 setup that is
+ * much cleaner.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/pxa-regs.h>
+
+/* wait for coprocessor write complete */
+   .macro CPWAIT reg
+   mrc	p15,0,\reg,c2,c0,0
+   mov	\reg,\reg
+   sub	pc,pc,#4
+   .endm
+
+
+/*
+ *	Memory setup
+ */
+
+.globl lowlevel_init
+lowlevel_init:
+
+	/* Set up GPIO pins first ----------------------------------------- */
+
+	ldr		r0,	=GPSR0
+	ldr		r1,	=CFG_GPSR0_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPSR1
+	ldr		r1,	=CFG_GPSR1_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPSR2
+	ldr		r1,	=CFG_GPSR2_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPSR3
+	ldr		r1,	=CFG_GPSR3_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPCR0
+	ldr		r1,	=CFG_GPCR0_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPCR1
+	ldr		r1,	=CFG_GPCR1_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPCR2
+	ldr		r1,	=CFG_GPCR2_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPCR3
+	ldr		r1,	=CFG_GPCR3_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPDR0
+	ldr		r1,	=CFG_GPDR0_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPDR1
+	ldr		r1,	=CFG_GPDR1_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPDR2
+	ldr		r1,	=CFG_GPDR2_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPDR3
+	ldr		r1,	=CFG_GPDR3_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR0_L
+	ldr		r1,	=CFG_GAFR0_L_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR0_U
+	ldr		r1,	=CFG_GAFR0_U_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR1_L
+	ldr		r1,	=CFG_GAFR1_L_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR1_U
+	ldr		r1,	=CFG_GAFR1_U_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR2_L
+	ldr		r1,	=CFG_GAFR2_L_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR2_U
+	ldr		r1,	=CFG_GAFR2_U_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR3_L
+	ldr		r1,	=CFG_GAFR3_L_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR3_U
+	ldr		r1,	=CFG_GAFR3_U_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=PSSR		/* enable GPIO pins */
+	ldr		r1,	=CFG_PSSR_VAL
+	str		r1,   [r0]
+
+	/* ---------------------------------------------------------------- */
+	/* Enable memory interface					    */
+	/*								    */
+	/* The sequence below is based on the recommended init steps	    */
+	/* detailed in the Intel PXA250 Operating Systems Developers Guide, */
+	/* Chapter 10.							    */
+	/* ---------------------------------------------------------------- */
+
+	/* ---------------------------------------------------------------- */
+	/* Step 1: Wait for at least 200 microsedonds to allow internal	    */
+	/*	   clocks to settle. Only necessary after hard reset...	    */
+	/*	   FIXME: can be optimized later			    */
+	/* ---------------------------------------------------------------- */
+
+	ldr r3, =OSCR			/* reset the OS Timer Count to zero */
+	mov r2, #0
+	str r2, [r3]
+	ldr r4, =0x300			/* really 0x2E1 is about 200usec,   */
+					/* so 0x300 should be plenty	    */
+1:
+	ldr r2, [r3]
+	cmp r4, r2
+	bgt 1b
+
+mem_init:
+
+	ldr	r1,  =MEMC_BASE		/* get memory controller base addr. */
+
+	/* ---------------------------------------------------------------- */
+	/* Step 2a: Initialize Asynchronous static memory controller	    */
+	/* ---------------------------------------------------------------- */
+
+	/* MSC registers: timing, bus width, mem type			    */
+
+	/* MSC0: nCS(0,1)						    */
+	ldr	r2,   =CFG_MSC0_VAL
+	str	r2,   [r1, #MSC0_OFFSET]
+	ldr	r2,   [r1, #MSC0_OFFSET]	/* read back to ensure	    */
+						/* that data latches	    */
+	/* MSC1: nCS(2,3)						    */
+	ldr	r2,  =CFG_MSC1_VAL
+	str	r2,  [r1, #MSC1_OFFSET]
+	ldr	r2,  [r1, #MSC1_OFFSET]
+
+	/* MSC2: nCS(4,5)						    */
+	ldr	r2,  =CFG_MSC2_VAL
+	str	r2,  [r1, #MSC2_OFFSET]
+	ldr	r2,  [r1, #MSC2_OFFSET]
+
+	/* ---------------------------------------------------------------- */
+	/* Step 2b: Initialize Card Interface				    */
+	/* ---------------------------------------------------------------- */
+
+	/* MECR: Memory Expansion Card Register				    */
+	ldr	r2,  =CFG_MECR_VAL
+	str	r2,  [r1, #MECR_OFFSET]
+	ldr	r2,	[r1, #MECR_OFFSET]
+
+	/* MCMEM0: Card Interface slot 0 timing				    */
+	ldr	r2,  =CFG_MCMEM0_VAL
+	str	r2,  [r1, #MCMEM0_OFFSET]
+	ldr	r2,	[r1, #MCMEM0_OFFSET]
+
+	/* MCMEM1: Card Interface slot 1 timing				    */
+	ldr	r2,  =CFG_MCMEM1_VAL
+	str	r2,  [r1, #MCMEM1_OFFSET]
+	ldr	r2,	[r1, #MCMEM1_OFFSET]
+
+	/* MCATT0: Card Interface Attribute Space Timing, slot 0	    */
+	ldr	r2,  =CFG_MCATT0_VAL
+	str	r2,  [r1, #MCATT0_OFFSET]
+	ldr	r2,	[r1, #MCATT0_OFFSET]
+
+	/* MCATT1: Card Interface Attribute Space Timing, slot 1	    */
+	ldr	r2,  =CFG_MCATT1_VAL
+	str	r2,  [r1, #MCATT1_OFFSET]
+	ldr	r2,	[r1, #MCATT1_OFFSET]
+
+	/* MCIO0: Card Interface I/O Space Timing, slot 0		    */
+	ldr	r2,  =CFG_MCIO0_VAL
+	str	r2,  [r1, #MCIO0_OFFSET]
+	ldr	r2,	[r1, #MCIO0_OFFSET]
+
+	/* MCIO1: Card Interface I/O Space Timing, slot 1		    */
+	ldr	r2,  =CFG_MCIO1_VAL
+	str	r2,  [r1, #MCIO1_OFFSET]
+	ldr	r2,	[r1, #MCIO1_OFFSET]
+
+	/* ---------------------------------------------------------------- */
+	/* Step 2c: Write FLYCNFG  FIXME: what's that???		    */
+	/* ---------------------------------------------------------------- */
+	ldr	r2,  =CFG_FLYCNFG_VAL
+	str	r2,  [r1, #FLYCNFG_OFFSET]
+	str	r2,	[r1, #FLYCNFG_OFFSET]
+
+	/* ---------------------------------------------------------------- */
+	/* Step 2d: Initialize Timing for Sync Memory (SDCLK0)		    */
+	/* ---------------------------------------------------------------- */
+
+	/* Before accessing MDREFR we need a valid DRI field, so we set	    */
+	/* this to power on defaults + DRI field.			    */
+
+	ldr	r4,	[r1, #MDREFR_OFFSET]
+	ldr	r2,	=0xFFF
+	bic	r4,	r4, r2
+
+	ldr	r3,	=CFG_MDREFR_VAL
+	and	r3,	r3,  r2
+
+	orr	r4,	r4, r3
+	str	r4,	[r1, #MDREFR_OFFSET]	/* write back MDREFR	    */
+
+	orr	r4,  r4, #MDREFR_K0RUN
+	orr	r4,  r4, #MDREFR_K0DB4
+	orr	r4,  r4, #MDREFR_K0FREE
+	orr	r4,  r4, #MDREFR_K0DB2
+	orr	r4,  r4, #MDREFR_K1DB2
+	bic	r4,  r4, #MDREFR_K1FREE
+	bic	r4,  r4, #MDREFR_K2FREE
+
+	str	r4,	[r1, #MDREFR_OFFSET]	/* write back MDREFR	    */
+	ldr	r4,  [r1, #MDREFR_OFFSET]
+
+	/* Note: preserve the mdrefr value in r4			    */
+
+
+	/* ---------------------------------------------------------------- */
+	/* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
+	/* ---------------------------------------------------------------- */
+
+	/* Initialize SXCNFG register. Assert the enable bits		    */
+
+	/* Write SXMRS to cause an MRS command to all enabled banks of	    */
+	/* synchronous static memory. Note that SXLCR need not be written   */
+	/* at this time.						    */
+
+	ldr	r2,  =CFG_SXCNFG_VAL
+	str	r2,  [r1, #SXCNFG_OFFSET]
+
+	/* ---------------------------------------------------------------- */
+	/* Step 4: Initialize SDRAM					    */
+	/* ---------------------------------------------------------------- */
+
+	bic	r4, r4, #(MDREFR_K2FREE |MDREFR_K1FREE | MDREFR_K0FREE)
+
+	orr	r4, r4, #MDREFR_K1RUN
+	bic	r4, r4, #MDREFR_K2DB2
+	str	r4, [r1, #MDREFR_OFFSET]
+	ldr	r4, [r1, #MDREFR_OFFSET]
+
+	bic	r4, r4, #MDREFR_SLFRSH
+	str	r4, [r1, #MDREFR_OFFSET]
+	ldr	r4, [r1, #MDREFR_OFFSET]
+
+	orr	r4, r4, #MDREFR_E1PIN
+	str	r4, [r1, #MDREFR_OFFSET]
+	ldr	r4, [r1, #MDREFR_OFFSET]
+
+	nop
+	nop
+
+
+	/* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to  */
+	/*	    configure but not enable each SDRAM partition pair.	    */
+
+	ldr	r4,	=CFG_MDCNFG_VAL
+	bic	r4,	r4,	#(MDCNFG_DE0|MDCNFG_DE1)
+	bic	r4,	r4,	#(MDCNFG_DE2|MDCNFG_DE3)
+
+	str	r4,	[r1, #MDCNFG_OFFSET]	/* write back MDCNFG	    */
+	ldr	r4,	[r1, #MDCNFG_OFFSET]
+
+
+	/* Step 4e: Wait for the clock to the SDRAMs to stabilize,	    */
+	/*	    100..200 µsec.					    */
+
+	ldr r3, =OSCR			/* reset the OS Timer Count to zero */
+	mov r2, #0
+	str r2, [r3]
+	ldr r4, =0x300			/* really 0x2E1 is about 200usec,   */
+					/* so 0x300 should be plenty	    */
+1:
+	    ldr r2, [r3]
+	    cmp r4, r2
+	    bgt 1b
+
+
+	/* Step 4f: Trigger a number (usually 8) refresh cycles by	    */
+	/*	    attempting non-burst read or write accesses to disabled */
+	/*	    SDRAM, as commonly specified in the power up sequence   */
+	/*	    documented in SDRAM data sheets. The address(es) used   */
+	/*	    for this purpose must not be cacheable.		    */
+
+	ldr	r3,	=CFG_DRAM_BASE
+	str	r2,	[r3]
+	str	r2,	[r3]
+	str	r2,	[r3]
+	str	r2,	[r3]
+	str	r2,	[r3]
+	str	r2,	[r3]
+	str	r2,	[r3]
+	str	r2,	[r3]
+
+
+	/* Step 4g: Write MDCNFG with enable bits asserted		    */
+	/*	    (MDCNFG:DEx set to 1).				    */
+
+	ldr	r3,	[r1, #MDCNFG_OFFSET]
+	mov	r4, r3
+	orr	r3,	r3,	#MDCNFG_DE0
+	str	r3,	[r1, #MDCNFG_OFFSET]
+	mov	r0, r3
+
+	/* Step 4h: Write MDMRS.					    */
+
+	ldr	r2,  =CFG_MDMRS_VAL
+	str	r2,  [r1, #MDMRS_OFFSET]
+
+	/* enable APD */
+	ldr	r3,  [r1, #MDREFR_OFFSET]
+	orr	r3,  r3,  #MDREFR_APD
+	str	r3,  [r1, #MDREFR_OFFSET]
+
+	/* We are finished with Intel's memory controller initialisation    */
+
+setvoltage:
+
+	mov	r10,	lr
+	bl	initPXAvoltage	/* In case the board is rebooting with a    */
+	mov	lr,	r10	/* low voltage raise it up to a good one.   */
+
+wakeup:
+	/* Are we waking from sleep? */
+	ldr	r0,	=RCSR
+	ldr	r1,	[r0]
+	and	r1,	r1, #(RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR)
+	str	r1,	[r0]
+	teq	r1,	#RCSR_SMR
+
+	bne	initirqs
+
+	ldr	r0,	=PSSR
+	mov	r1,	#PSSR_PH
+	str	r1,	[r0]
+
+	/* if so, resume at PSPR */
+	ldr	r0,	=PSPR
+	ldr	r1,	[r0]
+	mov	pc,	r1
+
+	/* ---------------------------------------------------------------- */
+	/* Disable (mask) all interrupts at interrupt controller	    */
+	/* ---------------------------------------------------------------- */
+
+initirqs:
+
+	mov	r1,  #0		/* clear int. level register (IRQ, not FIQ) */
+	ldr	r2,  =ICLR
+	str	r1,  [r2]
+
+	ldr	r2,  =ICMR	/* mask all interrupts at the controller    */
+	str	r1,  [r2]
+
+	/* ---------------------------------------------------------------- */
+	/* Clock initialisation						    */
+	/* ---------------------------------------------------------------- */
+
+initclks:
+
+	/* Disable the peripheral clocks, and set the core clock frequency  */
+
+	/* Turn Off on-chip peripheral clocks (except for memory)	    */
+	/* for re-configuration.					    */
+	ldr	r1,  =CKEN
+	ldr	r2,  =CFG_CKEN
+	str	r2,  [r1]
+
+	/* ... and write the core clock config register			    */
+	ldr	r2,  =CFG_CCCR
+	ldr	r1,  =CCCR
+	str	r2,  [r1]
+
+	/* Turn on turbo mode */
+	mrc	p14, 0, r2, c6, c0, 0
+	orr	r2, r2, #0xB		/* Turbo, Fast-Bus, Freq change**/
+	mcr	p14, 0, r2, c6, c0, 0
+
+	/* Re-write MDREFR */
+	ldr	r1, =MEMC_BASE
+	ldr	r2, [r1, #MDREFR_OFFSET]
+	str	r2, [r1, #MDREFR_OFFSET]
+#ifdef RTC
+	/* enable the 32Khz oscillator for RTC and PowerManager		    */
+	ldr	r1,  =OSCC
+	mov	r2,  #OSCC_OON
+	str	r2,  [r1]
+
+	/* NOTE:  spin here until OSCC.OOK get set, meaning the PLL	    */
+	/* has settled.							    */
+60:
+	ldr	r2, [r1]
+	ands	r2, r2, #1
+	beq	60b
+#else
+#error "RTC not defined"
+#endif
+
+	/* Interrupt init: Mask all interrupts				    */
+    ldr r0, =ICMR /* enable no sources */
+	mov r1, #0
+    str r1, [r0]
+	/* FIXME */
+
+#ifdef NODEBUG
+	/*Disable software and data breakpoints */
+	mov	r0,#0
+	mcr	p15,0,r0,c14,c8,0  /* ibcr0 */
+	mcr	p15,0,r0,c14,c9,0  /* ibcr1 */
+	mcr	p15,0,r0,c14,c4,0  /* dbcon */
+
+	/*Enable all debug functionality */
+	mov	r0,#0x80000000
+	mcr	p14,0,r0,c10,c0,0  /* dcsr */
+#endif
+
+	/* ---------------------------------------------------------------- */
+	/* End lowlevel_init							    */
+	/* ---------------------------------------------------------------- */
+
+endlowlevel_init:
+
+	mov	pc, lr
--- a/board/adsvix/pcmcia.c
+++ b/board/adsvix/pcmcia.c
@@ -0,0 +1,67 @@
+/*
+ * (C) Copyright 2004
+ * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/pxa-regs.h>
+
+void pcmcia_power_on(void)
+{
+#if 0
+	if (!(GPLR(20) & GPIO_bit(20))) { /* 3.3V */
+		GPCR(81) = GPIO_bit(81);
+		GPSR(82) = GPIO_bit(82);
+	}
+	else if (!(GPLR(21) & GPIO_bit(21))) { /* 5.0V */
+		GPCR(81) = GPIO_bit(81);
+		GPCR(82) = GPIO_bit(82);
+	}
+#else
+#warning "Board will only supply 5V, wait for next HW spin for selectable power"
+	/* 5.0V */
+	GPCR(81) = GPIO_bit(81);
+	GPCR(82) = GPIO_bit(82);
+#endif
+
+	udelay(300000);
+
+	/* reset the card */
+	GPSR(52) = GPIO_bit(52);
+
+	/* enable PCMCIA */
+	GPCR(83) = GPIO_bit(83);
+
+	/* clear reset */
+	udelay(10);
+	GPCR(52) = GPIO_bit(52);
+
+	udelay(20000);
+}
+
+void pcmcia_power_off(void)
+{
+	/* 0V */
+	GPSR(81) = GPIO_bit(81);
+	GPSR(82) = GPIO_bit(82);
+	/* disable PCMCIA */
+	GPSR(83) = GPIO_bit(83);
+}
--- a/board/adsvix/pxavoltage.S
+++ b/board/adsvix/pxavoltage.S
@@ -0,0 +1,230 @@
+/*
+ * (C) Copyright 2004
+ * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch/pxa-regs.h>
+
+#define LTC1663_ADDR    0x20
+
+#define LTC1663_SY	0x01	/* Sync ACK */
+#define LTC1663_SD	0x04	/* shutdown */
+#define LTC1663_BG	0x04	/* Internal Voltage Ref */
+
+#define VOLT_1_55         18    /* DAC value for 1.55V */
+
+		.global	initPXAvoltage
+
+@ Set the voltage to 1.55V early in the boot process so we can run
+@ at a high clock speed and boot quickly.  Note that this is necessary
+@ because the reset button does not reset the CPU voltage, so if the
+@ voltage was low (say 0.85V) then the CPU would crash without this
+@ routine
+
+@ This routine clobbers r0-r4
+
+initializei2c:
+
+		ldr	r2, =CKEN
+		ldr	r3, [r2]
+		orr	r3, r3, #CKEN15_PWRI2C
+		str	r3, [r2]
+
+		ldr	r2, =PCFR
+		ldr	r3, [r2]
+		orr	r3, r3, #PCFR_PI2C_EN
+		str	r3, [r2]
+
+		/* delay for about 250msec
+		 */
+		ldr	r3, =OSCR
+		mov	r2, #0
+		str	r2, [r3]
+		ldr	r1, =0xC0000
+
+1:
+		ldr	r2, [r3]
+		cmp	r1, r2
+		bgt	1b
+		ldr	r0, =PWRICR
+		ldr	r1, [r0]
+		bic	r1, r1, #(ICR_MA | ICR_START | ICR_STOP)
+		str	r1, [r0]
+
+		orr	r1, r1, #ICR_UR
+		str	r1, [r0]
+
+		ldr	r2, =PWRISR
+		ldr	r3, =0x7ff
+		str	r3, [r2]
+
+		bic	r1, r1, #ICR_UR
+		str	r1, [r0]
+
+		mov	r1, #(ICR_GCD | ICR_SCLE)
+		str	r1, [r0]
+
+		orr	r1, r1, #ICR_IUE
+		str	r1, [r0]
+
+		orr	r1, r1, #ICR_FM
+		str	r1, [r0]
+
+		/* delay for about 1msec
+		 */
+		ldr	r3, =OSCR
+		mov	r2, #0
+		str	r2, [r3]
+		ldr	r1, =0xC00
+
+1:
+		ldr	r2, [r3]
+		cmp	r1, r2
+		bgt	1b
+		mov	pc, lr
+
+sendbytei2c:
+		ldr	r3, =PWRIDBR
+		str	r0, [r3]
+		ldr	r3, =PWRICR
+		ldr	r0, [r3]
+		orr	r0, r0, r1
+		bic	r0, r0, r2
+		str	r0, [r3]
+		orr	r0, r0, #ICR_TB
+		str	r0, [r3]
+
+		mov	r2, #0x100000
+
+waitfortxemptyi2c:
+
+		ldr	r0, =PWRISR
+		ldr	r1, [r0]
+
+		/* take it from the top if we don't get empty after a while */
+		subs	r2, r2, #1
+		moveq	lr, r4
+		beq	initPXAvoltage
+
+		tst	r1, #ISR_ITE
+
+		beq	waitfortxemptyi2c
+
+		orr	r1, r1, #ISR_ITE
+		str	r1, [r0]
+
+		mov	pc, lr
+
+initPXAvoltage:
+
+		mov	r4, lr
+
+		bl	setleds
+
+		bl	initializei2c
+
+		bl	setleds
+
+		/* now send the real message to set the correct voltage */
+		ldr	r0, =LTC1663_ADDR
+		mov	r0, r0, LSL #1
+		mov	r1, #ICR_START
+		ldr	r2, =(ICR_STOP | ICR_ALDIE | ICR_ACKNAK)
+		bl	sendbytei2c
+
+		bl	setleds
+
+		mov	r0, #LTC1663_BG
+		mov	r1, #0
+		mov	r2, #(ICR_STOP | ICR_START)
+		bl	sendbytei2c
+
+		bl	setleds
+
+		ldr	r0, =VOLT_1_55
+		and	r0, r0, #0xff
+		mov	r1, #0
+		mov	r2, #(ICR_STOP | ICR_START)
+		bl	sendbytei2c
+
+		bl	setleds
+
+		ldr	r0, =VOLT_1_55
+		mov	r0, r0, ASR #8
+		and	r0, r0, #0xff
+		mov	r1, #ICR_STOP
+		mov	r2, #ICR_START
+		bl	sendbytei2c
+
+		bl	setleds
+
+		@ delay a little for the volatage to stablize
+		ldr	r3, =OSCR
+		mov	r2, #0
+		str	r2, [r3]
+		ldr	r1, =0xC0
+
+1:
+		ldr	r2, [r3]
+		cmp	r1, r2
+		bgt	1b
+		mov	pc, r4
+
+setleds:
+	mov		pc, lr
+
+	ldr		r5, =0x40e00058
+	ldr		r3, [r5]
+	bic		r3, r3, #0x3
+	str		r3, [r5]
+	ldr		r5, =0x40e0000c
+	ldr		r3, [r5]
+	orr		r3, r3, #0x00010000
+	str		r3, [r5]
+
+	@ inner loop
+	mov		r0, #0x2
+1:
+
+	ldr		r5, =0x40e00018
+	mov		r3, #0x00010000
+	str		r3, [r5]
+
+	@ outer loop
+	mov		r3, #0x00F00000
+2:
+	subs		r3, r3, #1
+	bne		2b
+
+	ldr		r5, =0x40e00024
+	mov		r3, #0x00010000
+	str		r3, [r5]
+
+	@ outer loop
+	mov		r3, #0x00F00000
+3:
+	subs		r3, r3, #1
+	bne		3b
+
+	subs		r0, r0, #1
+	bne		1b
+
+	mov		pc, lr
--- a/board/adsvix/u-boot.lds
+++ b/board/adsvix/u-boot.lds
@@ -0,0 +1,55 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/pxa/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
--- a/board/at91rm9200dk/u-boot.lds
+++ b/board/at91rm9200dk/u-boot.lds
@@ -32,7 +32,7 @@ SECTIONS
 	. = ALIGN(4);
 	.text      :
 	{
-	  cpu/at91rm9200/start.o	(.text)
+	  cpu/arm920t/start.o	(.text)
 	  *(.text)
 	}

--- a/board/canmb/Makefile
+++ b/board/canmb/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2005
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o
+#../common/flash.o ../common/vpd.o ../common/am79c874.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
--- a/board/canmb/canmb.c
+++ b/board/canmb/canmb.c
@@ -0,0 +1,251 @@
+/*
+ * (C) Copyright 2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+
+#if defined(CONFIG_MPC5200_DDR)
+#include "mt46v16m16-75.h"
+#else
+#include "mt48lc16m32s2-75.h"
+#endif
+
+#ifndef CFG_RAMBOOT
+static void sdram_start (int hi_addr)
+{
+	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+	/* unlock mode register */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+#if SDRAM_DDR
+	/* set mode register: extended mode */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
+	__asm__ volatile ("sync");
+
+	/* set mode register: reset DLL */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
+	__asm__ volatile ("sync");
+#endif
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* auto refresh */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* set mode register */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
+	__asm__ volatile ("sync");
+
+	/* normal operation */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
+	__asm__ volatile ("sync");
+}
+#endif
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ *            use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
+ *            is something else than 0x00000000.
+ */
+
+#if defined(CONFIG_MPC5200)
+long int initdram (int board_type)
+{
+	ulong dramsize = 0;
+	ulong dramsize2 = 0;
+#ifndef CFG_RAMBOOT
+	ulong test1, test2;
+
+	/* setup SDRAM chip selects */
+	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
+	__asm__ volatile ("sync");
+
+	/* setup config registers */
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+	__asm__ volatile ("sync");
+
+#if SDRAM_DDR
+	/* set tap delay */
+	*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
+	__asm__ volatile ("sync");
+#endif
+
+	/* find RAM size using SDRAM CS0 only */
+	sdram_start(0);
+	test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+	sdram_start(1);
+	test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize < (1 << 20)) {
+		dramsize = 0;
+	}
+
+	/* set SDRAM CS0 size according to the amount of RAM found */
+	if (dramsize > 0) {
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
+	} else {
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
+	}
+
+	/* let SDRAM CS1 start right after CS0 */
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
+
+	/* find RAM size using SDRAM CS1 only */
+	if (!dramsize)
+		sdram_start(0);
+	test2 = test1 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+	if (!dramsize) {
+		sdram_start(1);
+		test2 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+	}
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize2 = test1;
+	} else {
+		dramsize2 = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize2 < (1 << 20)) {
+		dramsize2 = 0;
+	}
+
+	/* set SDRAM CS1 size according to the amount of RAM found */
+	if (dramsize2 > 0) {
+		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
+			| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
+	} else {
+		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
+	}
+
+#else /* CFG_RAMBOOT */
+
+	/* retrieve size of memory connected to SDRAM CS0 */
+	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
+	if (dramsize >= 0x13) {
+		dramsize = (1 << (dramsize - 0x13)) << 20;
+	} else {
+		dramsize = 0;
+	}
+
+	/* retrieve size of memory connected to SDRAM CS1 */
+	dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
+	if (dramsize2 >= 0x13) {
+		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
+	} else {
+		dramsize2 = 0;
+	}
+
+#endif /* CFG_RAMBOOT */
+
+	return dramsize + dramsize2;
+}
+
+#elif defined(CONFIG_MGT5100)
+
+long int initdram (int board_type)
+{
+	ulong dramsize = 0;
+#ifndef CFG_RAMBOOT
+	ulong test1, test2;
+
+	/* setup and enable SDRAM chip selects */
+	*(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
+	*(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
+	*(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
+	__asm__ volatile ("sync");
+
+	/* setup config registers */
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+
+	/* address select register */
+	*(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
+	__asm__ volatile ("sync");
+
+	/* find RAM size */
+	sdram_start(0);
+	test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+	sdram_start(1);
+	test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+
+	/* set SDRAM end address according to size */
+	*(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
+
+#else /* CFG_RAMBOOT */
+
+	/* Retrieve amount of SDRAM available */
+	dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
+
+#endif /* CFG_RAMBOOT */
+
+	return dramsize;
+}
+
+#else
+#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
+#endif
+
+int checkboard (void)
+{
+	puts ("Board: CANMB\n");
+	return 0;
+}
+
+int board_early_init_r (void)
+{
+	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
+	*(vu_long *)MPC5XXX_BOOTCS_START =
+	*(vu_long *)MPC5XXX_CS0_START = START_REG(CFG_FLASH_BASE);
+	*(vu_long *)MPC5XXX_BOOTCS_STOP =
+	*(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CFG_FLASH_BASE, CFG_FLASH_SIZE);
+	return 0;
+}
--- a/board/canmb/config.mk
+++ b/board/canmb/config.mk
@@ -0,0 +1,39 @@
+#
+# (C) Copyright 2005
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2003
+# Reinhard Meyer, EMK Elektronik GmbH, r.meyer@emk-elektronik.de
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# CANMB board
+#
+# allowed and functional TEXT_BASE values:
+#
+#   0xfe000000		low boot at 0x00000100 (default board setting)
+#	0x00100000		RAM load and test
+#
+
+TEXT_BASE = 0xFE000000
+#TEXT_BASE = 0x00100000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
--- a/board/canmb/mt48lc16m32s2-75.h
+++ b/board/canmb/mt48lc16m32s2-75.h
@@ -0,0 +1,43 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_DDR	0		/* is SDR */
+
+#if defined(CONFIG_MPC5200)
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE	0x00CD0000
+#define SDRAM_CONTROL	0x504F0000
+#define SDRAM_CONFIG1	0xD2322800
+#define SDRAM_CONFIG2	0x8AD70000
+
+#elif defined(CONFIG_MGT5100)
+/* Settings for XLB = 66 MHz */
+#define SDRAM_MODE	0x008D0000
+#define SDRAM_CONTROL	0x504F0000
+#define SDRAM_CONFIG1	0xC2222600
+#define SDRAM_CONFIG2	0x88B70004
+#define SDRAM_ADDRSEL	0x02000000
+
+#else
+#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
+#endif
--- a/board/canmb/u-boot.lds
+++ b/board/canmb/u-boot.lds
@@ -0,0 +1,122 @@
+/*
+ * (C) Copyright 2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc5xxx/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
--- a/board/cmc_pu2/u-boot.lds
+++ b/board/cmc_pu2/u-boot.lds
@@ -32,7 +32,7 @@ SECTIONS
 	. = ALIGN(4);
 	.text      :
 	{
-	  cpu/at91rm9200/start.o	(.text)
+	  cpu/arm920t/start.o	(.text)
 	  *(.text)
 	}

--- a/board/dave/PPChameleonEVB/u-boot.lds
+++ b/board/dave/PPChameleonEVB/u-boot.lds
@@ -140,6 +140,7 @@ SECTIONS
   *(COMMON)
  }

+  ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified.");
  . = 0xFFFF8000;
  .ppcenv :
  {
--- a/board/esd/apc405/apc405.c
+++ b/board/esd/apc405/apc405.c
@@ -63,10 +63,56 @@ unsigned char logo_bmp[] =
 */
 #include "../common/lcd.c"

-#include "../common/"CFG_LCD_HEADER_NAME
+#include CFG_LCD_HEADER_NAME
 #endif /* CONFIG_LCD_USED */


+int board_revision(void)
+{
+	unsigned long cntrl0Reg;
+	unsigned long value;
+
+	/*
+	 * Get version of APC405 board from GPIO's
+	 */
+
+	/*
+	 * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO)
+	 */
+	cntrl0Reg = mfdcr(cntrl0);
+	mtdcr(cntrl0, cntrl0Reg | 0x03000000);
+	out32(GPIO0_ODR, in32(GPIO0_ODR) & ~0x00180000);
+	out32(GPIO0_TCR, in32(GPIO0_TCR) & ~0x00180000);
+	udelay(1000);                   /* wait some time before reading input */
+	value = in32(GPIO0_IR) & 0x00180000;       /* get config bits */
+
+	/*
+	 * Restore GPIO settings
+	 */
+	mtdcr(cntrl0, cntrl0Reg);
+
+	switch (value) {
+	case 0x00180000:
+		/* CS2==1 && CS3==1 -> version <= 1.2 */
+		return 2;
+	case 0x00080000:
+		/* CS2==0 && CS3==1 -> version 1.3 */
+		return 3;
+#if 0 /* not yet manufactured ! */
+	case 0x00100000:
+		/* CS2==1 && CS3==0 -> version 1.4 */
+		return 4;
+	case 0x00000000:
+		/* CS2==0 && CS3==0 -> version 1.5 */
+		return 5;
+#endif
+	default:
+		/* should not be reached! */
+		return 0;
+	}
+}
+
+
 int board_early_init_f (void)
 {
 	/*
@@ -120,8 +166,12 @@ int misc_init_f (void)

 int misc_init_r (void)
 {
+	DECLARE_GLOBAL_DATA_PTR;
+
 	volatile unsigned short *fpga_mode =
 		(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
+	volatile unsigned short *fpga_ctrl2 =
+		(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL2);
 	volatile unsigned char *duart0_mcr =
 		(unsigned char *)((ulong)DUART0_BA + 4);
 	volatile unsigned char *duart1_mcr =
@@ -204,6 +254,11 @@ int misc_init_r (void)
 	SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
 	udelay(1000); /* wait 1ms */

+	/*
+	 * Write board revision in FPGA
+	 */
+	*fpga_ctrl2 = (*fpga_ctrl2 & 0xfff0) | (gd->board_type & 0x000f);
+
 	/*
 	 * Enable power on PS/2 interface (with reset)
 	 */
@@ -228,8 +283,11 @@ int misc_init_r (void)
 		 logo_bmp, sizeof(logo_bmp));

 	/*
-	 * Enable microcontroller and setup backlight PWM controller
+	 * Reset microcontroller and setup backlight PWM controller
 	 */
+	*fpga_mode |= 0x0014;
+	for (i=0;i<10;i++)
+		udelay(1000);
 	*fpga_mode |= 0x001c;
 	*fuji_lcdbl_pwm = 0x00ff;

@@ -243,6 +301,8 @@ int misc_init_r (void)

 int checkboard (void)
 {
+	DECLARE_GLOBAL_DATA_PTR;
+
 	unsigned char str[64];
 	int i = getenv_r ("serial#", str, sizeof(str));

@@ -254,7 +314,8 @@ int checkboard (void)
 		puts(str);
 	}

-	putc ('\n');
+	gd->board_type = board_revision();
+	printf(", Rev 1.%ld\n", gd->board_type);

 	/*
 	 * Disable sleep mode in LXT971
--- a/board/esd/apc405/fpgadata.c
+++ b/board/esd/apc405/fpgadata.c
--- a/board/esd/pmc405/fpgadata.c
+++ b/board/esd/pmc405/fpgadata.c
@@ -6,26 +6,26 @@
  0x00,0x00,0x03,0x09,0x03,0xff,0xfd,0x03,0xff,0xfd,0x04,0x00,0x00,0x00,0x00,0x02,
  0x08,0xea,0x08,0x00,0x00,0x00,0x22,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x00,
  0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,
-  0x00,0x04,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x08,0x00,0x01,0x00,
+  0x00,0x04,0x38,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x08,0x00,0x01,0x00,
  0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x0c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,
  0x00,0x00,0x10,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x20,0x00,0x01,
-  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x24,0x00,0x01,0x00,0x00,0x00,0x00,0x01,
+  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x24,0x38,0x01,0x00,0x00,0x00,0x00,0x01,
  0x09,0x00,0x00,0x28,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x2c,0x00,
  0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x30,0x00,0x01,0x00,0x00,0x00,0x00,
  0x01,0x09,0x00,0x00,0x40,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x44,
-  0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x48,0x00,0x01,0x00,0x00,0x00,
+  0x14,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x48,0x00,0x01,0x00,0x00,0x00,
  0x00,0x01,0x09,0x00,0x00,0x4c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,
  0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x00,0x50,0x00,0x03,0x00,0x00,
  0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x00,0x80,0x00,0x01,0x00,
  0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,
-  0x00,0x00,0x84,0x38,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x84,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,
  0x09,0x00,0x00,0x88,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x8c,0x00,
  0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x90,0x00,0x01,0x00,0x00,0x00,0x00,
  0x01,0x09,0x00,0x00,0xa0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0xa4,
-  0x38,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0xa8,0x00,0x01,0x00,0x00,0x00,
+  0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0xa8,0x00,0x01,0x00,0x00,0x00,
  0x00,0x01,0x09,0x00,0x00,0xac,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,
  0xb0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0xc0,0x00,0x01,0x00,0x00,
-  0x00,0x00,0x01,0x09,0x00,0x00,0xc4,0x14,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,
+  0x00,0x00,0x01,0x09,0x00,0x00,0xc4,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,
  0x00,0xc8,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0xcc,0x00,0x01,0x00,
  0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,
  0x00,0x00,0xd0,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,
@@ -128,34 +128,34 @@
  0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x04,0xc8,0x00,0x01,0x00,0x00,0x00,0x00,
  0x01,0x09,0x00,0x04,0xcc,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,
  0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x04,0xd0,0x00,0x03,0x00,0x00,0x00,
-  0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x05,0x00,0x80,0x01,0x00,0x00,
+  0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x05,0x00,0xc0,0x11,0x00,0x00,
  0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,
-  0x05,0x04,0x40,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,
-  0x00,0x05,0x08,0x00,0x31,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,0x0c,0x80,0x01,
-  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,0x10,0x00,0x01,0x00,0x00,0x00,0x00,0x01,
-  0x09,0x00,0x05,0x20,0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,0x24,0x04,
-  0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,0x28,0x00,0x01,0x00,0x00,0x00,0x00,
-  0x01,0x09,0x00,0x05,0x2c,0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,0x30,
-  0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,0x40,0xa0,0x11,0x00,0x00,0x00,
-  0x00,0x01,0x09,0x00,0x05,0x44,0xe8,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,
-  0x48,0x40,0x09,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,0x4c,0x80,0x11,0x00,0x00,
+  0x05,0x04,0xc0,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,
+  0x00,0x05,0x08,0x40,0x31,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,0x0c,0x00,0x01,
+  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,0x10,0x80,0x01,0x00,0x00,0x00,0x00,0x01,
+  0x09,0x00,0x05,0x20,0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,0x24,0x00,
+  0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,0x28,0x00,0x01,0x00,0x00,0x00,0x00,
+  0x01,0x09,0x00,0x05,0x2c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,0x30,
+  0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,0x40,0x20,0x19,0x00,0x00,0x00,
+  0x00,0x01,0x09,0x00,0x05,0x44,0x20,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,
+  0x48,0x48,0x09,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,0x4c,0x00,0x01,0x00,0x00,
  0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,
-  0x05,0x50,0x80,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,
-  0x00,0x05,0x80,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,
-  0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x05,0x84,0x04,0x31,0x00,0x00,0x00,0x00,0x00,
-  0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x05,0x88,0xc0,0x01,0x00,0x00,0x00,0x00,
-  0x01,0x09,0x00,0x05,0x8c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,0x90,
+  0x05,0x50,0x00,0x13,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,
+  0x00,0x05,0x80,0x00,0x21,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,
+  0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x05,0x84,0x00,0x11,0x00,0x00,0x00,0x00,0x00,
+  0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x05,0x88,0x80,0x01,0x00,0x00,0x00,0x00,
+  0x01,0x09,0x00,0x05,0x8c,0x80,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,0x90,
  0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,0xa0,0x04,0x01,0x00,0x00,0x00,
  0x00,0x01,0x09,0x00,0x05,0xa4,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,
-  0xa8,0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,0xac,0x00,0x01,0x00,0x00,
+  0xa8,0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,0xac,0x00,0x11,0x00,0x00,
  0x00,0x00,0x01,0x09,0x00,0x05,0xb0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,
-  0x05,0xc0,0x08,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,0xc4,0x00,0x09,0x00,
-  0x00,0x00,0x00,0x01,0x09,0x00,0x05,0xc8,0x80,0x11,0x00,0x00,0x00,0x00,0x01,0x09,
-  0x00,0x05,0xcc,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,
+  0x05,0xc0,0xc8,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,0xc4,0x08,0x09,0x00,
+  0x00,0x00,0x00,0x01,0x09,0x00,0x05,0xc8,0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x09,
+  0x00,0x05,0xcc,0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,
  0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x05,0xd0,0x00,0x03,0x00,0x00,0x00,0x00,0x00,
  0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x06,0x03,0x02,0x01,0x00,0x00,0x00,0x00,
  0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x06,0x07,
-  0x02,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x06,
+  0x42,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x06,
  0x0b,0x02,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x06,0x0f,0x02,0x01,0x00,0x00,
  0x00,0x00,0x01,0x09,0x00,0x06,0x13,0x02,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,
  0x06,0x23,0x03,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x06,0x27,0x03,0x01,0x00,
@@ -165,8 +165,8 @@
  0x09,0x00,0x06,0x44,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x06,0x48,0x00,
  0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x06,0x4c,0x00,0x01,0x00,0x00,0x00,0x00,
  0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x06,0x50,
-  0x80,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x06,
-  0x80,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,
+  0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x06,
+  0x80,0x04,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,
  0x00,0x00,0x00,0x09,0x00,0x06,0x84,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,
  0x00,0x00,0x00,0x00,0x09,0x00,0x06,0x88,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,
  0x00,0x06,0x8c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x06,0x90,0x00,0x01,
@@ -175,10 +175,10 @@
  0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x06,0xac,0x00,0x01,0x00,0x00,0x00,0x00,
  0x01,0x09,0x00,0x06,0xb0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x06,0xc0,
  0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x06,0xc4,0x00,0x01,0x00,0x00,0x00,
-  0x00,0x01,0x09,0x00,0x06,0xc8,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x06,
-  0xcc,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,
+  0x00,0x01,0x09,0x00,0x06,0xc8,0x40,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x06,
+  0xcc,0x80,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,
  0x00,0x00,0x00,0x09,0x00,0x06,0xd0,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,
-  0x00,0x00,0x00,0x03,0x09,0x00,0x07,0x03,0x02,0x01,0x00,0x00,0x00,0x00,0x01,0x01,
+  0x00,0x00,0x00,0x03,0x09,0x00,0x07,0x02,0x02,0x01,0x00,0x00,0x00,0x00,0x01,0x01,
  0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x07,0x07,0x02,0x01,
  0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x07,0x0b,0x02,
  0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x07,0x0f,0x02,0x01,0x00,0x00,0x00,0x00,
@@ -207,7 +207,7 @@
  0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x08,0x04,0x00,0x01,0x00,0x00,
  0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x08,0x08,0x00,0x01,0x00,
  0x00,0x00,0x00,0x01,0x09,0x00,0x08,0x0e,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,
-  0x00,0x08,0x10,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x08,0x22,0x01,0x01,
+  0x00,0x08,0x10,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x08,0x23,0x01,0x01,
  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x08,0x26,0x01,0x01,0x00,0x00,0x00,0x00,0x01,
  0x09,0x00,0x08,0x28,0x01,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x08,0x2e,0x01,
  0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x08,0x30,0x00,0x01,0x00,0x00,0x00,0x00,
@@ -258,8 +258,8 @@
  0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x0a,0x08,0x00,0x01,0x00,0x00,0x00,0x00,0x01,
  0x09,0x00,0x0a,0x0c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0a,0x10,0x00,
  0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0a,0x20,0x00,0x01,0x00,0x00,0x00,0x00,
-  0x01,0x09,0x00,0x0a,0x24,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0a,0x28,
-  0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0a,0x2e,0x00,0x01,0x00,0x00,0x00,
+  0x01,0x09,0x00,0x0a,0x26,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0a,0x28,
+  0x01,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0a,0x2c,0x01,0x01,0x00,0x00,0x00,
  0x00,0x01,0x09,0x00,0x0a,0x30,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0a,
  0x40,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0a,0x44,0x00,0x01,0x00,0x00,
  0x00,0x00,0x01,0x09,0x00,0x0a,0x48,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,
@@ -278,13 +278,13 @@
  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0a,0xcc,0x00,0x01,0x00,0x00,0x00,0x00,0x01,
  0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x0a,0xd0,0x00,
  0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x0b,0x00,
-  0x02,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,
+  0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,
  0x00,0x00,0x09,0x00,0x0b,0x04,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,
  0x00,0x00,0x00,0x09,0x00,0x0b,0x0a,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,
  0x0b,0x0c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0b,0x10,0x00,0x01,0x00,
-  0x00,0x00,0x00,0x01,0x09,0x00,0x0b,0x20,0x01,0x01,0x00,0x00,0x00,0x00,0x01,0x09,
+  0x00,0x00,0x00,0x01,0x09,0x00,0x0b,0x22,0x01,0x01,0x00,0x00,0x00,0x00,0x01,0x09,
  0x00,0x0b,0x26,0x01,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0b,0x28,0x01,0x01,
-  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0b,0x2c,0x01,0x01,0x00,0x00,0x00,0x00,0x01,
+  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0b,0x2e,0x01,0x01,0x00,0x00,0x00,0x00,0x01,
  0x09,0x00,0x0b,0x30,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0b,0x40,0x00,
  0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0b,0x44,0x00,0x01,0x00,0x00,0x00,0x00,
  0x01,0x09,0x00,0x0b,0x48,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0b,0x4c,
@@ -327,12 +327,12 @@
  0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0c,0xc8,0x00,0x01,0x00,0x00,0x00,0x00,
  0x01,0x09,0x00,0x0c,0xcc,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,
  0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x0c,0xd0,0x00,0x03,0x00,0x00,0x00,
-  0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x0d,0x03,0x46,0x01,0x00,0x00,
+  0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x0d,0x03,0x02,0x01,0x00,0x00,
  0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,
  0x0d,0x07,0x02,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,
  0x00,0x0d,0x0b,0x02,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0d,0x0f,0x02,0x01,
  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0d,0x13,0x02,0x01,0x00,0x00,0x00,0x00,0x01,
-  0x09,0x00,0x0d,0x23,0x03,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0d,0x27,0x03,
+  0x09,0x00,0x0d,0x23,0x03,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0d,0x27,0x07,
  0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0d,0x2b,0x03,0x01,0x00,0x00,0x00,0x00,
  0x01,0x09,0x00,0x0d,0x2f,0x01,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0d,0x30,
  0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0d,0x40,0x00,0x01,0x00,0x00,0x00,
@@ -340,7 +340,7 @@
  0x48,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0d,0x4c,0x00,0x01,0x00,0x00,
  0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,
  0x0d,0x50,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,
-  0x00,0x0d,0x80,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x0d,0x80,0x04,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,
  0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x0d,0x84,0x00,0x01,0x00,0x00,0x00,0x00,0x00,
  0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x0d,0x88,0x00,0x01,0x00,0x00,0x00,0x00,
  0x01,0x09,0x00,0x0d,0x8c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0d,0x90,
@@ -354,27 +354,27 @@
  0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x0d,0xd0,0x00,0x03,0x00,0x00,0x00,0x00,0x00,
  0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x0e,0x00,0x00,0x01,0x00,0x00,0x00,0x00,
  0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x0e,0x04,
-  0x40,0x11,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x0e,
-  0x08,0x80,0x31,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0e,0x0c,0x80,0x01,0x00,0x00,
+  0xc0,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x0e,
+  0x08,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0e,0x0c,0x80,0x01,0x00,0x00,
  0x00,0x00,0x01,0x09,0x00,0x0e,0x10,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,
-  0x0e,0x20,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0e,0x24,0x04,0x01,0x00,
-  0x00,0x00,0x00,0x01,0x09,0x00,0x0e,0x28,0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x09,
+  0x0e,0x20,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0e,0x24,0x00,0x11,0x00,
+  0x00,0x00,0x00,0x01,0x09,0x00,0x0e,0x28,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,
  0x00,0x0e,0x2c,0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0e,0x30,0x00,0x01,
-  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0e,0x40,0x48,0x01,0x00,0x00,0x00,0x00,0x01,
-  0x09,0x00,0x0e,0x44,0x20,0x09,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0e,0x48,0x80,
-  0x19,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0e,0x4c,0x80,0x11,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0e,0x40,0x60,0x01,0x00,0x00,0x00,0x00,0x01,
+  0x09,0x00,0x0e,0x44,0x48,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0e,0x48,0xc0,
+  0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0e,0x4c,0x80,0x11,0x00,0x00,0x00,0x00,
  0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x0e,0x50,
  0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x0e,
-  0x80,0x80,0x31,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,
-  0x00,0x00,0x00,0x09,0x00,0x0e,0x84,0x84,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,
-  0x00,0x00,0x00,0x00,0x09,0x00,0x0e,0x88,0x40,0x01,0x00,0x00,0x00,0x00,0x01,0x09,
+  0x80,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,
+  0x00,0x00,0x00,0x09,0x00,0x0e,0x84,0x00,0x21,0x00,0x00,0x00,0x00,0x00,0x01,0x00,
+  0x00,0x00,0x00,0x00,0x09,0x00,0x0e,0x88,0x40,0x11,0x00,0x00,0x00,0x00,0x01,0x09,
  0x00,0x0e,0x8c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0e,0x90,0x00,0x01,
-  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0e,0xa0,0x04,0x11,0x00,0x00,0x00,0x00,0x01,
-  0x09,0x00,0x0e,0xa4,0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0e,0xa8,0x00,
+  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0e,0xa0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,
+  0x09,0x00,0x0e,0xa4,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0e,0xa8,0x00,
  0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0e,0xac,0x00,0x01,0x00,0x00,0x00,0x00,
  0x01,0x09,0x00,0x0e,0xb0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0e,0xc0,
-  0xa0,0x19,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0e,0xc4,0xc8,0x11,0x00,0x00,0x00,
-  0x00,0x01,0x09,0x00,0x0e,0xc8,0x40,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0e,
+  0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0e,0xc4,0xa0,0x01,0x00,0x00,0x00,
+  0x00,0x01,0x09,0x00,0x0e,0xc8,0x08,0x09,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0e,
  0xcc,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,
  0x00,0x00,0x00,0x09,0x00,0x0e,0xd0,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,
  0x00,0x00,0x00,0x03,0x09,0x00,0x0f,0x00,0x02,0x01,0x00,0x00,0x00,0x00,0x01,0x01,
@@ -403,17 +403,17 @@
  0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,
  0x00,0x09,0x00,0x0f,0xd0,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,
  0x00,0x03,0x09,0x00,0x10,0x01,0x82,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,
-  0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x10,0x04,0x82,0x01,0x00,0x00,
+  0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x10,0x05,0x82,0x01,0x00,0x00,
  0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x10,0x0a,0x82,0x01,0x00,
-  0x00,0x00,0x00,0x01,0x09,0x00,0x10,0x0e,0x82,0x01,0x00,0x00,0x00,0x00,0x01,0x09,
-  0x00,0x10,0x12,0x02,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x10,0x20,0x03,0x11,
+  0x00,0x00,0x00,0x01,0x09,0x00,0x10,0x0c,0x82,0x01,0x00,0x00,0x00,0x00,0x01,0x09,
+  0x00,0x10,0x12,0x82,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x10,0x20,0x03,0x11,
  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x10,0x26,0x03,0x11,0x00,0x00,0x00,0x00,0x01,
  0x09,0x00,0x10,0x2a,0x03,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x10,0x2c,0x01,
-  0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x10,0x30,0x00,0x01,0x00,0x00,0x00,0x00,
+  0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x10,0x30,0x00,0x11,0x00,0x00,0x00,0x00,
  0x01,0x09,0x00,0x10,0x40,0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x10,0x44,
  0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x10,0x48,0x00,0x11,0x00,0x00,0x00,
  0x00,0x01,0x09,0x00,0x10,0x4c,0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,
-  0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x10,0x50,0x00,0x03,0x00,0x00,
+  0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x10,0x50,0x00,0x13,0x00,0x00,
  0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x10,0x80,0x00,0x01,0x00,
  0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,
  0x00,0x10,0x84,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,
@@ -427,31 +427,31 @@
  0x10,0xc8,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x10,0xcc,0x00,0x01,0x00,
  0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,
  0x00,0x10,0xd0,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,
-  0x09,0x00,0x11,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,
-  0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x11,0x04,0x04,0x01,0x00,0x00,0x00,0x00,
-  0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x11,0x08,0x00,0x11,0x00,0x00,0x00,
+  0x09,0x00,0x11,0x00,0xc0,0x11,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,
+  0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x11,0x04,0x00,0x11,0x00,0x00,0x00,0x00,
+  0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x11,0x08,0x80,0x21,0x00,0x00,0x00,
  0x00,0x01,0x09,0x00,0x11,0x0c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x11,
-  0x10,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x11,0x20,0x00,0x01,0x00,0x00,
-  0x00,0x00,0x01,0x09,0x00,0x11,0x24,0x04,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,
-  0x11,0x28,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x11,0x2c,0x00,0x01,0x00,
+  0x10,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x11,0x20,0x00,0x11,0x00,0x00,
+  0x00,0x00,0x01,0x09,0x00,0x11,0x24,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,
+  0x11,0x28,0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x11,0x2c,0x00,0x01,0x00,
  0x00,0x00,0x00,0x01,0x09,0x00,0x11,0x30,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,
-  0x00,0x11,0x40,0xa0,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x11,0x44,0x40,0x01,
-  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x11,0x48,0x80,0x09,0x00,0x00,0x00,0x00,0x01,
-  0x09,0x00,0x11,0x4c,0x80,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,
-  0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x11,0x50,0x80,0x03,0x00,0x00,0x00,0x00,
-  0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x11,0x80,0x00,0x11,0x00,0x00,0x00,
+  0x00,0x11,0x40,0x08,0x19,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x11,0x44,0x20,0x09,
+  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x11,0x48,0xc0,0x11,0x00,0x00,0x00,0x00,0x01,
+  0x09,0x00,0x11,0x4c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,
+  0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x11,0x50,0x00,0x03,0x00,0x00,0x00,0x00,
+  0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x11,0x80,0x00,0x01,0x00,0x00,0x00,
  0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x11,
-  0x84,0x80,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,
-  0x11,0x88,0x40,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x11,0x8c,0x00,0x01,0x00,
-  0x00,0x00,0x00,0x01,0x09,0x00,0x11,0x90,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,
-  0x00,0x11,0xa0,0x04,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x11,0xa4,0x00,0x11,
+  0x84,0x00,0x21,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,
+  0x11,0x88,0x40,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x11,0x8c,0x00,0x01,0x00,
+  0x00,0x00,0x00,0x01,0x09,0x00,0x11,0x90,0x80,0x01,0x00,0x00,0x00,0x00,0x01,0x09,
+  0x00,0x11,0xa0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x11,0xa4,0x00,0x01,
  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x11,0xa8,0x00,0x01,0x00,0x00,0x00,0x00,0x01,
  0x09,0x00,0x11,0xac,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x11,0xb0,0x00,
-  0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x11,0xc0,0x40,0x09,0x00,0x00,0x00,0x00,
-  0x01,0x09,0x00,0x11,0xc4,0x28,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x11,0xc8,
-  0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x11,0xcc,0x00,0x01,0x00,0x00,0x00,
+  0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x11,0xc0,0x20,0x01,0x00,0x00,0x00,0x00,
+  0x01,0x09,0x00,0x11,0xc4,0xc0,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x11,0xc8,
+  0x08,0x09,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x11,0xcc,0x00,0x01,0x00,0x00,0x00,
  0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x11,
-  0xd0,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,
+  0xd0,0x00,0x13,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,
  0x12,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,
  0x00,0x00,0x00,0x00,0x09,0x00,0x12,0x04,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x01,
  0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x12,0x08,0x00,0x01,0x00,0x00,0x00,0x00,0x01,
@@ -493,7 +493,7 @@
  0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x13,0x84,0x00,0x01,0x00,
  0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x13,0x88,0x00,0x01,
  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x13,0x8c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,
-  0x09,0x00,0x13,0x90,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x13,0xa0,0x00,
+  0x09,0x00,0x13,0x90,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x13,0xa2,0x00,
  0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x13,0xa4,0x00,0x01,0x00,0x00,0x00,0x00,
  0x01,0x09,0x00,0x13,0xa8,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x13,0xac,
  0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x13,0xb0,0x00,0x01,0x00,0x00,0x00,
@@ -503,8 +503,8 @@
  0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x13,0xd0,0x00,0x03,0x00,
  0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x14,0x00,0x00,0x01,
  0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,
-  0x09,0x00,0x14,0x05,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,
-  0x00,0x09,0x00,0x14,0x08,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x14,0x0c,
+  0x09,0x00,0x14,0x04,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,
+  0x00,0x09,0x00,0x14,0x08,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x14,0x0e,
  0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x14,0x10,0x00,0x01,0x00,0x00,0x00,
  0x00,0x01,0x09,0x00,0x14,0x23,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x14,
  0x24,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x14,0x28,0x00,0x01,0x00,0x00,
@@ -528,55 +528,55 @@
  0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x14,0xd0,0x00,0x03,0x00,0x00,0x00,
  0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x15,0x00,0x00,0x01,0x00,0x00,
  0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,
-  0x15,0x04,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,
-  0x00,0x15,0x08,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x15,0x0c,0x00,0x01,
-  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x15,0x10,0x00,0x01,0x00,0x00,0x00,0x00,0x01,
-  0x09,0x00,0x15,0x20,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x15,0x24,0x00,
-  0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x15,0x28,0x00,0x01,0x00,0x00,0x00,0x00,
-  0x01,0x09,0x00,0x15,0x2c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x15,0x30,
-  0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x15,0x40,0x00,0x01,0x00,0x00,0x00,
-  0x00,0x01,0x09,0x00,0x15,0x44,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x15,
-  0x48,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x15,0x4c,0x00,0x01,0x00,0x00,
+  0x15,0x04,0x00,0x11,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,
+  0x00,0x15,0x08,0xc0,0x31,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x15,0x0c,0x80,0x01,
+  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x15,0x10,0x80,0x01,0x00,0x00,0x00,0x00,0x01,
+  0x09,0x00,0x15,0x20,0x04,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x15,0x24,0x00,
+  0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x15,0x28,0x00,0x11,0x00,0x00,0x00,0x00,
+  0x01,0x09,0x00,0x15,0x2c,0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x15,0x30,
+  0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x15,0x40,0x28,0x01,0x00,0x00,0x00,
+  0x00,0x01,0x09,0x00,0x15,0x44,0x28,0x09,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x15,
+  0x48,0x48,0x19,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x15,0x4c,0x00,0x11,0x00,0x00,
  0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,
-  0x15,0x50,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,
-  0x00,0x15,0x80,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,
-  0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x15,0x84,0x00,0xc1,0x00,0x00,0x00,0x00,0x00,
+  0x15,0x50,0x00,0x13,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,
+  0x00,0x15,0x80,0xc0,0x31,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,
+  0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x15,0x84,0xc0,0x21,0x00,0x00,0x00,0x00,0x00,
  0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x15,0x88,0x00,0x01,0x00,0x00,0x00,0x00,
  0x01,0x09,0x00,0x15,0x8c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x15,0x90,
-  0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x15,0xa0,0x00,0x01,0x00,0x00,0x00,
-  0x00,0x01,0x09,0x00,0x15,0xa4,0x80,0xe1,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x15,
+  0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x15,0xa0,0x00,0x11,0x00,0x00,0x00,
+  0x00,0x01,0x09,0x00,0x15,0xa4,0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x15,
  0xa8,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x15,0xac,0x00,0x01,0x00,0x00,
  0x00,0x00,0x01,0x09,0x00,0x15,0xb0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,
-  0x15,0xc0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x15,0xc4,0x00,0x61,0x00,
+  0x15,0xc0,0xc0,0x19,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x15,0xc4,0x40,0x11,0x00,
  0x00,0x00,0x00,0x01,0x09,0x00,0x15,0xc8,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,
-  0x00,0x15,0xcc,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,
+  0x00,0x15,0xcc,0x80,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,
  0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x15,0xd0,0x00,0x03,0x00,0x00,0x00,0x00,0x00,
-  0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x16,0x02,0x06,0x01,0x00,0x00,0x00,0x00,
+  0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x16,0x02,0x02,0x01,0x00,0x00,0x00,0x00,
  0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x16,0x06,
-  0x02,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x16,
-  0x0b,0x02,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x16,0x0d,0x02,0x01,0x00,0x00,
+  0x3a,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x16,
+  0x0b,0x42,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x16,0x0d,0x02,0x01,0x00,0x00,
  0x00,0x00,0x01,0x09,0x00,0x16,0x13,0x02,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,
-  0x16,0x20,0x03,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x16,0x27,0x03,0x01,0x00,
+  0x16,0x20,0x03,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x16,0x27,0x3b,0x01,0x00,
  0x00,0x00,0x00,0x01,0x09,0x00,0x16,0x2b,0x03,0x01,0x00,0x00,0x00,0x00,0x01,0x09,
  0x00,0x16,0x2d,0x01,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x16,0x30,0x00,0x01,
  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x16,0x40,0x00,0x09,0x00,0x00,0x00,0x00,0x01,
-  0x09,0x00,0x16,0x44,0x00,0x09,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x16,0x48,0x00,
+  0x09,0x00,0x16,0x44,0x14,0x09,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x16,0x48,0x00,
  0x09,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x16,0x4c,0x00,0x01,0x00,0x00,0x00,0x00,
  0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x16,0x50,
  0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x16,
-  0x83,0x42,0x11,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,
+  0x83,0x02,0x11,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,
  0x00,0x00,0x00,0x09,0x00,0x16,0x87,0x02,0x11,0x00,0x00,0x00,0x00,0x00,0x01,0x00,
  0x00,0x00,0x00,0x00,0x09,0x00,0x16,0x8b,0x02,0x11,0x00,0x00,0x00,0x00,0x01,0x09,
  0x00,0x16,0x8f,0x02,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x16,0x93,0x02,0x01,
  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x16,0xa3,0x03,0x01,0x00,0x00,0x00,0x00,0x01,
-  0x09,0x00,0x16,0xa7,0x03,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x16,0xab,0x03,
+  0x09,0x00,0x16,0xa7,0x07,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x16,0xab,0x03,
  0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x16,0xaf,0x01,0x01,0x00,0x00,0x00,0x00,
  0x01,0x09,0x00,0x16,0xb0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x16,0xc0,
-  0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x16,0xc4,0x80,0x01,0x00,0x00,0x00,
-  0x00,0x01,0x09,0x00,0x16,0xc8,0x40,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x16,
+  0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x16,0xc4,0x00,0x01,0x00,0x00,0x00,
+  0x00,0x01,0x09,0x00,0x16,0xc8,0x08,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x16,
  0xcc,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,
  0x00,0x00,0x00,0x09,0x00,0x16,0xd0,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,
-  0x00,0x00,0x00,0x03,0x09,0x00,0x17,0x03,0x02,0x01,0x00,0x00,0x00,0x00,0x01,0x01,
+  0x00,0x00,0x00,0x03,0x09,0x00,0x17,0x02,0x02,0x01,0x00,0x00,0x00,0x00,0x01,0x01,
  0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x17,0x07,0x02,0x01,
  0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x17,0x0b,0x02,
  0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x17,0x0f,0x02,0x01,0x00,0x00,0x00,0x00,
@@ -593,7 +593,7 @@
  0x00,0x09,0x00,0x17,0x84,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,
  0x00,0x00,0x09,0x00,0x17,0x88,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x17,
  0x8e,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x17,0x90,0x00,0x01,0x00,0x00,
-  0x00,0x00,0x01,0x09,0x00,0x17,0xa2,0x01,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,
+  0x00,0x00,0x01,0x09,0x00,0x17,0xa3,0x01,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,
  0x17,0xa6,0x01,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x17,0xa8,0x01,0x01,0x00,
  0x00,0x00,0x00,0x01,0x09,0x00,0x17,0xae,0x01,0x01,0x00,0x00,0x00,0x00,0x01,0x09,
  0x00,0x17,0xb0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x17,0xc0,0x00,0x01,
@@ -618,9 +618,9 @@
  0x00,0x18,0x84,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,
  0x09,0x00,0x18,0x88,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x18,0x8c,0x00,
  0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x18,0x90,0x00,0x01,0x00,0x00,0x00,0x00,
-  0x01,0x09,0x00,0x18,0xa0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x18,0xa4,
-  0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x18,0xa8,0x00,0x01,0x00,0x00,0x00,
-  0x00,0x01,0x09,0x00,0x18,0xae,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x18,
+  0x01,0x09,0x00,0x18,0xa0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x18,0xa6,
+  0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x18,0xa8,0x01,0x01,0x00,0x00,0x00,
+  0x00,0x01,0x09,0x00,0x18,0xac,0x01,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x18,
  0xb0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x18,0xc0,0x00,0x01,0x00,0x00,
  0x00,0x00,0x01,0x09,0x00,0x18,0xc4,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,
  0x18,0xc8,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x18,0xcc,0x00,0x01,0x00,
@@ -658,16 +658,16 @@
  0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1a,0x20,0x00,0x11,0x00,0x00,0x00,0x00,
  0x01,0x09,0x00,0x1a,0x24,0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1a,0x28,
  0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1a,0x2c,0x00,0x11,0x00,0x00,0x00,
-  0x00,0x01,0x09,0x00,0x1a,0x30,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1a,
+  0x00,0x01,0x09,0x00,0x1a,0x30,0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1a,
  0x40,0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1a,0x44,0x00,0x11,0x00,0x00,
  0x00,0x00,0x01,0x09,0x00,0x1a,0x48,0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,
  0x1a,0x4c,0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,
-  0x00,0x00,0x00,0x00,0x09,0x00,0x1a,0x50,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,
+  0x00,0x00,0x00,0x00,0x09,0x00,0x1a,0x50,0x00,0x13,0x00,0x00,0x00,0x00,0x00,0x01,
  0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x1a,0x82,0x81,0x01,0x00,0x00,0x00,0x00,0x01,
  0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x1a,0x84,0x80,
  0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x1a,0x88,
  0x80,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1a,0x8c,0x80,0x01,0x00,0x00,0x00,
-  0x00,0x01,0x09,0x00,0x1a,0x90,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1a,
+  0x00,0x01,0x09,0x00,0x1a,0x90,0x80,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1a,
  0xa0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1a,0xa4,0x00,0x01,0x00,0x00,
  0x00,0x00,0x01,0x09,0x00,0x1a,0xa8,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,
  0x1a,0xac,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1a,0xb0,0x00,0x01,0x00,
@@ -1006,7 +1006,7 @@
  0x00,0x28,0x10,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x28,0x20,0x00,0x11,
  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x28,0x24,0x00,0x11,0x00,0x00,0x00,0x00,0x01,
  0x09,0x00,0x28,0x28,0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x28,0x2c,0x00,
-  0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x28,0x30,0x00,0x01,0x00,0x00,0x00,0x00,
+  0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x28,0x30,0x00,0x11,0x00,0x00,0x00,0x00,
  0x01,0x09,0x00,0x28,0x40,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x28,0x44,
  0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x28,0x48,0x00,0x01,0x00,0x00,0x00,
  0x00,0x01,0x09,0x00,0x28,0x4c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,
@@ -1015,7 +1015,7 @@
  0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,
  0x00,0x28,0x84,0x80,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,
  0x09,0x00,0x28,0x88,0x80,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x28,0x8c,0x80,
-  0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x28,0x90,0x00,0x01,0x00,0x00,0x00,0x00,
+  0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x28,0x90,0x80,0x01,0x00,0x00,0x00,0x00,
  0x01,0x09,0x00,0x28,0xa0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x28,0xa4,
  0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x28,0xa8,0x00,0x01,0x00,0x00,0x00,
  0x00,0x01,0x09,0x00,0x28,0xac,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x28,
@@ -1023,30 +1023,30 @@
  0x00,0x00,0x01,0x09,0x00,0x28,0xc4,0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,
  0x28,0xc8,0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x28,0xcc,0x00,0x11,0x00,
  0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,
-  0x00,0x28,0xd0,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,
-  0x09,0x00,0x29,0x00,0x80,0x31,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,
-  0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x29,0x04,0x84,0x31,0x00,0x00,0x00,0x00,
-  0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x29,0x08,0xc0,0x01,0x00,0x00,0x00,
+  0x00,0x28,0xd0,0x00,0x13,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,
+  0x09,0x00,0x29,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,
+  0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x29,0x04,0x00,0x01,0x00,0x00,0x00,0x00,
+  0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x29,0x08,0x00,0x01,0x00,0x00,0x00,
  0x00,0x01,0x09,0x00,0x29,0x0c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x29,
-  0x10,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x29,0x20,0x04,0x11,0x00,0x00,
-  0x00,0x00,0x01,0x09,0x00,0x29,0x24,0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,
-  0x29,0x28,0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x29,0x2c,0x00,0x01,0x00,
+  0x10,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x29,0x20,0x00,0x01,0x00,0x00,
+  0x00,0x00,0x01,0x09,0x00,0x29,0x24,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,
+  0x29,0x28,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x29,0x2c,0x00,0x01,0x00,
  0x00,0x00,0x00,0x01,0x09,0x00,0x29,0x30,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,
-  0x00,0x29,0x40,0xe8,0x19,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x29,0x44,0xe8,0x19,
-  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x29,0x48,0xc0,0x11,0x00,0x00,0x00,0x00,0x01,
+  0x00,0x29,0x40,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x29,0x44,0x00,0x01,
+  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x29,0x48,0x00,0x01,0x00,0x00,0x00,0x00,0x01,
  0x09,0x00,0x29,0x4c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,
-  0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x29,0x50,0x80,0x03,0x00,0x00,0x00,0x00,
+  0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x29,0x50,0x00,0x03,0x00,0x00,0x00,0x00,
  0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x29,0x80,0x00,0x01,0x00,0x00,0x00,
  0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x29,
-  0x84,0x40,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,
-  0x29,0x88,0x00,0x31,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x29,0x8c,0x80,0x01,0x00,
+  0x84,0x00,0xc1,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,
+  0x29,0x88,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x29,0x8c,0x00,0x01,0x00,
  0x00,0x00,0x00,0x01,0x09,0x00,0x29,0x90,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,
-  0x00,0x29,0xa0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x29,0xa4,0x04,0x01,
+  0x00,0x29,0xa0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x29,0xa4,0x80,0xe1,
  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x29,0xa8,0x00,0x01,0x00,0x00,0x00,0x00,0x01,
-  0x09,0x00,0x29,0xac,0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x29,0xb0,0x00,
+  0x09,0x00,0x29,0xac,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x29,0xb0,0x00,
  0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x29,0xc0,0x00,0x01,0x00,0x00,0x00,0x00,
-  0x01,0x09,0x00,0x29,0xc4,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x29,0xc8,
-  0x00,0x09,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x29,0xcc,0x80,0x11,0x00,0x00,0x00,
+  0x01,0x09,0x00,0x29,0xc4,0x00,0x61,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x29,0xc8,
+  0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x29,0xcc,0x00,0x01,0x00,0x00,0x00,
  0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x29,
  0xd0,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,
  0x2a,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,
@@ -1351,25 +1351,25 @@
  0x01,0x04,0x00,0x00,0x00,0x00,0x02,0x08,0xe8,0x08,0x00,0x00,0x00,0x06,0x01,0x00,
  0x09,0x05,0x00,0x02,0x08,0xee,0x04,0x00,0x00,0x00,0x01,0x08,0x00,0x00,0x00,0x22,
  0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x00,0x00,0x00,0x03,0x00,0x00,0x00,0x00,
-  0x00,0x01,0x03,0xff,0xff,0xff,0xff,0x09,0x00,0x00,0x04,0x00,0x03,0x00,0x00,0x00,
-  0x00,0x01,0x09,0x00,0x00,0x08,0x00,0x03,0x00,0x00,0x04,0x00,0x01,0x09,0x00,0x00,
+  0x00,0x01,0x03,0xff,0xff,0xff,0xff,0x09,0x00,0x00,0x04,0x38,0x03,0x00,0x00,0x00,
+  0x00,0x01,0x09,0x00,0x00,0x08,0x00,0x03,0x00,0x00,0x04,0x38,0x01,0x09,0x00,0x00,
  0x0c,0x00,0x03,0x00,0x00,0x08,0x00,0x01,0x09,0x00,0x00,0x10,0x00,0x03,0x00,0x00,
  0x0c,0x00,0x01,0x09,0x00,0x00,0x20,0x00,0x03,0x00,0x00,0x10,0x00,0x01,0x09,0x00,
-  0x00,0x24,0x00,0x03,0x00,0x00,0x20,0x00,0x01,0x09,0x00,0x00,0x28,0x00,0x03,0x00,
-  0x00,0x24,0x00,0x01,0x09,0x00,0x00,0x2c,0x00,0x03,0x00,0x00,0x28,0x00,0x01,0x09,
+  0x00,0x24,0x38,0x03,0x00,0x00,0x20,0x00,0x01,0x09,0x00,0x00,0x28,0x00,0x03,0x00,
+  0x00,0x24,0x38,0x01,0x09,0x00,0x00,0x2c,0x00,0x03,0x00,0x00,0x28,0x00,0x01,0x09,
  0x00,0x00,0x30,0x00,0x03,0x00,0x00,0x2c,0x00,0x01,0x09,0x00,0x00,0x40,0x00,0x03,
-  0x00,0x00,0x30,0x00,0x01,0x09,0x00,0x00,0x44,0x00,0x03,0x00,0x00,0x40,0x00,0x01,
-  0x09,0x00,0x00,0x48,0x00,0x03,0x00,0x00,0x44,0x00,0x01,0x09,0x00,0x00,0x4c,0x00,
+  0x00,0x00,0x30,0x00,0x01,0x09,0x00,0x00,0x44,0x14,0x03,0x00,0x00,0x40,0x00,0x01,
+  0x09,0x00,0x00,0x48,0x00,0x03,0x00,0x00,0x44,0x14,0x01,0x09,0x00,0x00,0x4c,0x00,
  0x03,0x00,0x00,0x48,0x00,0x01,0x09,0x00,0x00,0x50,0x00,0x03,0x00,0x00,0x4c,0x00,
  0x01,0x09,0x00,0x00,0x80,0x00,0x03,0x00,0x00,0x50,0x00,0x01,0x09,0x00,0x00,0x84,
-  0x38,0x03,0x00,0x00,0x80,0x00,0x01,0x09,0x00,0x00,0x88,0x00,0x03,0x00,0x00,0x84,
-  0x38,0x01,0x09,0x00,0x00,0x8c,0x00,0x03,0x00,0x00,0x88,0x00,0x01,0x09,0x00,0x00,
+  0x00,0x03,0x00,0x00,0x80,0x00,0x01,0x09,0x00,0x00,0x88,0x00,0x03,0x00,0x00,0x84,
+  0x00,0x01,0x09,0x00,0x00,0x8c,0x00,0x03,0x00,0x00,0x88,0x00,0x01,0x09,0x00,0x00,
  0x90,0x00,0x03,0x00,0x00,0x8c,0x00,0x01,0x09,0x00,0x00,0xa0,0x00,0x03,0x00,0x00,
-  0x90,0x00,0x01,0x09,0x00,0x00,0xa4,0x38,0x03,0x00,0x00,0xa0,0x00,0x01,0x09,0x00,
-  0x00,0xa8,0x00,0x03,0x00,0x00,0xa4,0x38,0x01,0x09,0x00,0x00,0xac,0x00,0x03,0x00,
+  0x90,0x00,0x01,0x09,0x00,0x00,0xa4,0x00,0x03,0x00,0x00,0xa0,0x00,0x01,0x09,0x00,
+  0x00,0xa8,0x00,0x03,0x00,0x00,0xa4,0x00,0x01,0x09,0x00,0x00,0xac,0x00,0x03,0x00,
  0x00,0xa8,0x00,0x01,0x09,0x00,0x00,0xb0,0x00,0x03,0x00,0x00,0xac,0x00,0x01,0x09,
-  0x00,0x00,0xc0,0x00,0x03,0x00,0x00,0xb0,0x00,0x01,0x09,0x00,0x00,0xc4,0x14,0x03,
-  0x00,0x00,0xc0,0x00,0x01,0x09,0x00,0x00,0xc8,0x00,0x03,0x00,0x00,0xc4,0x14,0x01,
+  0x00,0x00,0xc0,0x00,0x03,0x00,0x00,0xb0,0x00,0x01,0x09,0x00,0x00,0xc4,0x00,0x03,
+  0x00,0x00,0xc0,0x00,0x01,0x09,0x00,0x00,0xc8,0x00,0x03,0x00,0x00,0xc4,0x00,0x01,
  0x09,0x00,0x00,0xcc,0x00,0x03,0x00,0x00,0xc8,0x00,0x01,0x09,0x00,0x00,0xd0,0x00,
  0x03,0x00,0x00,0xcc,0x00,0x01,0x09,0x00,0x01,0x00,0x01,0x03,0x00,0x00,0xd0,0x00,
  0x01,0x09,0x00,0x01,0x04,0x00,0x03,0x00,0x01,0x00,0x01,0x01,0x09,0x00,0x01,0x08,
@@ -1454,30 +1454,30 @@
  0x00,0x01,0x09,0x00,0x04,0xc4,0x00,0x03,0x00,0x04,0xc0,0x00,0x01,0x09,0x00,0x04,
  0xc8,0x00,0x03,0x00,0x04,0xc4,0x00,0x01,0x09,0x00,0x04,0xcc,0x00,0x03,0x00,0x04,
  0xc8,0x00,0x01,0x09,0x00,0x04,0xd0,0x00,0x03,0x00,0x04,0xcc,0x00,0x01,0x09,0x00,
-  0x05,0x00,0x80,0x03,0x00,0x04,0xd0,0x00,0x01,0x09,0x00,0x05,0x04,0x40,0x03,0x00,
-  0x05,0x00,0x80,0x01,0x09,0x00,0x05,0x08,0x00,0x33,0x00,0x05,0x04,0x40,0x01,0x09,
-  0x00,0x05,0x0c,0x80,0x03,0x00,0x05,0x08,0x00,0x31,0x09,0x00,0x05,0x10,0x00,0x03,
-  0x00,0x05,0x0c,0x80,0x01,0x09,0x00,0x05,0x20,0x00,0x13,0x00,0x05,0x10,0x00,0x01,
-  0x09,0x00,0x05,0x24,0x04,0x03,0x00,0x05,0x20,0x00,0x11,0x09,0x00,0x05,0x28,0x00,
-  0x03,0x00,0x05,0x24,0x04,0x01,0x09,0x00,0x05,0x2c,0x00,0x13,0x00,0x05,0x28,0x00,
-  0x01,0x09,0x00,0x05,0x30,0x00,0x03,0x00,0x05,0x2c,0x00,0x11,0x09,0x00,0x05,0x40,
-  0xa0,0x13,0x00,0x05,0x30,0x00,0x01,0x09,0x00,0x05,0x44,0xe8,0x03,0x00,0x05,0x40,
-  0xa0,0x11,0x09,0x00,0x05,0x48,0x40,0x0b,0x00,0x05,0x44,0xe8,0x01,0x09,0x00,0x05,
-  0x4c,0x80,0x13,0x00,0x05,0x48,0x40,0x09,0x09,0x00,0x05,0x50,0x80,0x03,0x00,0x05,
-  0x4c,0x80,0x11,0x09,0x00,0x05,0x80,0x00,0x03,0x00,0x05,0x50,0x80,0x01,0x01,0x03,
-  0xff,0xfc,0xfc,0xff,0x09,0x00,0x05,0x84,0x04,0x33,0x00,0x05,0x80,0x00,0x01,0x01,
-  0x03,0xff,0xff,0xff,0xff,0x09,0x00,0x05,0x88,0xc0,0x03,0x00,0x05,0x84,0x04,0x31,
-  0x09,0x00,0x05,0x8c,0x00,0x03,0x00,0x05,0x88,0xc0,0x01,0x09,0x00,0x05,0x90,0x00,
-  0x03,0x00,0x05,0x8c,0x00,0x01,0x09,0x00,0x05,0xa0,0x04,0x03,0x00,0x05,0x90,0x00,
+  0x05,0x00,0xc0,0x13,0x00,0x04,0xd0,0x00,0x01,0x09,0x00,0x05,0x04,0xc0,0x03,0x00,
+  0x05,0x00,0xc0,0x11,0x09,0x00,0x05,0x08,0x40,0x33,0x00,0x05,0x04,0xc0,0x01,0x09,
+  0x00,0x05,0x0c,0x00,0x03,0x00,0x05,0x08,0x40,0x31,0x09,0x00,0x05,0x10,0x80,0x03,
+  0x00,0x05,0x0c,0x00,0x01,0x09,0x00,0x05,0x20,0x00,0x13,0x00,0x05,0x10,0x80,0x01,
+  0x09,0x00,0x05,0x24,0x00,0x13,0x00,0x05,0x20,0x00,0x11,0x09,0x00,0x05,0x28,0x00,
+  0x03,0x00,0x05,0x24,0x00,0x11,0x09,0x00,0x05,0x2c,0x00,0x03,0x00,0x05,0x28,0x00,
+  0x01,0x09,0x00,0x05,0x30,0x00,0x13,0x00,0x05,0x2c,0x00,0x01,0x09,0x00,0x05,0x40,
+  0x20,0x1b,0x00,0x05,0x30,0x00,0x11,0x09,0x00,0x05,0x44,0x20,0x13,0x00,0x05,0x40,
+  0x20,0x19,0x09,0x00,0x05,0x48,0x48,0x0b,0x00,0x05,0x44,0x20,0x11,0x09,0x00,0x05,
+  0x4c,0x00,0x03,0x00,0x05,0x48,0x48,0x09,0x09,0x00,0x05,0x50,0x00,0x13,0x00,0x05,
+  0x4c,0x00,0x01,0x09,0x00,0x05,0x80,0x00,0x23,0x00,0x05,0x50,0x00,0x11,0x01,0x03,
+  0xff,0xfc,0xfc,0xff,0x09,0x00,0x05,0x84,0x00,0x13,0x00,0x05,0x80,0x00,0x21,0x01,
+  0x03,0xff,0xff,0xff,0xff,0x09,0x00,0x05,0x88,0x80,0x03,0x00,0x05,0x84,0x00,0x11,
+  0x09,0x00,0x05,0x8c,0x80,0x03,0x00,0x05,0x88,0x80,0x01,0x09,0x00,0x05,0x90,0x00,
+  0x03,0x00,0x05,0x8c,0x80,0x01,0x09,0x00,0x05,0xa0,0x04,0x03,0x00,0x05,0x90,0x00,
  0x01,0x09,0x00,0x05,0xa4,0x00,0x03,0x00,0x05,0xa0,0x04,0x01,0x09,0x00,0x05,0xa8,
-  0x00,0x13,0x00,0x05,0xa4,0x00,0x01,0x09,0x00,0x05,0xac,0x00,0x03,0x00,0x05,0xa8,
-  0x00,0x11,0x09,0x00,0x05,0xb0,0x00,0x03,0x00,0x05,0xac,0x00,0x01,0x09,0x00,0x05,
-  0xc0,0x08,0x03,0x00,0x05,0xb0,0x00,0x01,0x09,0x00,0x05,0xc4,0x00,0x0b,0x00,0x05,
-  0xc0,0x08,0x01,0x09,0x00,0x05,0xc8,0x80,0x13,0x00,0x05,0xc4,0x00,0x09,0x09,0x00,
-  0x05,0xcc,0x00,0x03,0x00,0x05,0xc8,0x80,0x11,0x09,0x00,0x05,0xd0,0x00,0x03,0x00,
-  0x05,0xcc,0x00,0x01,0x09,0x00,0x06,0x03,0x02,0x03,0x00,0x05,0xd0,0x00,0x01,0x09,
-  0x00,0x06,0x07,0x02,0x03,0x00,0x06,0x03,0x02,0x01,0x09,0x00,0x06,0x0b,0x02,0x03,
-  0x00,0x06,0x07,0x02,0x01,0x09,0x00,0x06,0x0f,0x02,0x03,0x00,0x06,0x0b,0x02,0x01,
+  0x00,0x13,0x00,0x05,0xa4,0x00,0x01,0x09,0x00,0x05,0xac,0x00,0x13,0x00,0x05,0xa8,
+  0x00,0x11,0x09,0x00,0x05,0xb0,0x00,0x03,0x00,0x05,0xac,0x00,0x11,0x09,0x00,0x05,
+  0xc0,0xc8,0x03,0x00,0x05,0xb0,0x00,0x01,0x09,0x00,0x05,0xc4,0x08,0x0b,0x00,0x05,
+  0xc0,0xc8,0x01,0x09,0x00,0x05,0xc8,0x00,0x13,0x00,0x05,0xc4,0x08,0x09,0x09,0x00,
+  0x05,0xcc,0x00,0x13,0x00,0x05,0xc8,0x00,0x11,0x09,0x00,0x05,0xd0,0x00,0x03,0x00,
+  0x05,0xcc,0x00,0x11,0x09,0x00,0x06,0x03,0x02,0x03,0x00,0x05,0xd0,0x00,0x01,0x09,
+  0x00,0x06,0x07,0x42,0x03,0x00,0x06,0x03,0x02,0x01,0x09,0x00,0x06,0x0b,0x02,0x03,
+  0x00,0x06,0x07,0x42,0x01,0x09,0x00,0x06,0x0f,0x02,0x03,0x00,0x06,0x0b,0x02,0x01,
  0x09,0x00,0x06,0x13,0x02,0x03,0x00,0x06,0x0f,0x02,0x01,0x09,0x00,0x06,0x23,0x03,
  0x03,0x00,0x06,0x13,0x02,0x01,0x09,0x00,0x06,0x27,0x03,0x03,0x00,0x06,0x23,0x03,
  0x01,0x09,0x00,0x06,0x2b,0x03,0x03,0x00,0x06,0x27,0x03,0x01,0x09,0x00,0x06,0x2f,
@@ -1485,8 +1485,8 @@
  0x01,0x01,0x09,0x00,0x06,0x40,0x00,0x03,0x00,0x06,0x30,0x00,0x01,0x09,0x00,0x06,
  0x44,0x00,0x03,0x00,0x06,0x40,0x00,0x01,0x09,0x00,0x06,0x48,0x00,0x03,0x00,0x06,
  0x44,0x00,0x01,0x09,0x00,0x06,0x4c,0x00,0x03,0x00,0x06,0x48,0x00,0x01,0x09,0x00,
-  0x06,0x50,0x80,0x03,0x00,0x06,0x4c,0x00,0x01,0x09,0x00,0x06,0x80,0x00,0x03,0x00,
-  0x06,0x50,0x80,0x01,0x09,0x00,0x06,0x84,0x00,0x03,0x00,0x06,0x80,0x00,0x01,0x09,
+  0x06,0x50,0x00,0x03,0x00,0x06,0x4c,0x00,0x01,0x09,0x00,0x06,0x80,0x04,0x03,0x00,
+  0x06,0x50,0x00,0x01,0x09,0x00,0x06,0x84,0x00,0x03,0x00,0x06,0x80,0x04,0x01,0x09,
  0x00,0x06,0x88,0x00,0x03,0x00,0x06,0x84,0x00,0x01,0x09,0x00,0x06,0x8c,0x00,0x03,
  0x00,0x06,0x88,0x00,0x01,0x09,0x00,0x06,0x90,0x00,0x03,0x00,0x06,0x8c,0x00,0x01,
  0x09,0x00,0x06,0xa0,0x00,0x03,0x00,0x06,0x90,0x00,0x01,0x09,0x00,0x06,0xa4,0x00,
@@ -1494,10 +1494,10 @@
  0x01,0x09,0x00,0x06,0xac,0x00,0x03,0x00,0x06,0xa8,0x00,0x01,0x09,0x00,0x06,0xb0,
  0x00,0x03,0x00,0x06,0xac,0x00,0x01,0x09,0x00,0x06,0xc0,0x00,0x03,0x00,0x06,0xb0,
  0x00,0x01,0x09,0x00,0x06,0xc4,0x00,0x03,0x00,0x06,0xc0,0x00,0x01,0x09,0x00,0x06,
-  0xc8,0x00,0x03,0x00,0x06,0xc4,0x00,0x01,0x09,0x00,0x06,0xcc,0x00,0x03,0x00,0x06,
-  0xc8,0x00,0x01,0x09,0x00,0x06,0xd0,0x00,0x03,0x00,0x06,0xcc,0x00,0x01,0x09,0x00,
-  0x07,0x03,0x02,0x03,0x00,0x06,0xd0,0x00,0x01,0x09,0x00,0x07,0x07,0x02,0x03,0x00,
-  0x07,0x03,0x02,0x01,0x09,0x00,0x07,0x0b,0x02,0x03,0x00,0x07,0x07,0x02,0x01,0x09,
+  0xc8,0x40,0x03,0x00,0x06,0xc4,0x00,0x01,0x09,0x00,0x06,0xcc,0x80,0x03,0x00,0x06,
+  0xc8,0x40,0x01,0x09,0x00,0x06,0xd0,0x00,0x03,0x00,0x06,0xcc,0x80,0x01,0x09,0x00,
+  0x07,0x02,0x02,0x03,0x00,0x06,0xd0,0x00,0x01,0x09,0x00,0x07,0x07,0x02,0x03,0x00,
+  0x07,0x02,0x02,0x01,0x09,0x00,0x07,0x0b,0x02,0x03,0x00,0x07,0x07,0x02,0x01,0x09,
  0x00,0x07,0x0f,0x02,0x03,0x00,0x07,0x0b,0x02,0x01,0x09,0x00,0x07,0x11,0x02,0x03,
  0x00,0x07,0x0f,0x02,0x01,0x09,0x00,0x07,0x23,0x03,0x03,0x00,0x07,0x11,0x02,0x01,
  0x09,0x00,0x07,0x27,0x03,0x03,0x00,0x07,0x23,0x03,0x01,0x09,0x00,0x07,0x2b,0x03,
@@ -1520,8 +1520,8 @@
  0xd0,0x00,0x01,0x09,0x00,0x08,0x04,0x00,0x03,0x00,0x08,0x00,0x02,0x01,0x09,0x00,
  0x08,0x08,0x00,0x03,0x00,0x08,0x04,0x00,0x01,0x09,0x00,0x08,0x0e,0x00,0x03,0x00,
  0x08,0x08,0x00,0x01,0x09,0x00,0x08,0x10,0x00,0x03,0x00,0x08,0x0e,0x00,0x01,0x09,
-  0x00,0x08,0x22,0x01,0x03,0x00,0x08,0x10,0x00,0x01,0x09,0x00,0x08,0x26,0x01,0x03,
-  0x00,0x08,0x22,0x01,0x01,0x09,0x00,0x08,0x28,0x01,0x03,0x00,0x08,0x26,0x01,0x01,
+  0x00,0x08,0x23,0x01,0x03,0x00,0x08,0x10,0x00,0x01,0x09,0x00,0x08,0x26,0x01,0x03,
+  0x00,0x08,0x23,0x01,0x01,0x09,0x00,0x08,0x28,0x01,0x03,0x00,0x08,0x26,0x01,0x01,
  0x09,0x00,0x08,0x2e,0x01,0x03,0x00,0x08,0x28,0x01,0x01,0x09,0x00,0x08,0x30,0x00,
  0x03,0x00,0x08,0x2e,0x01,0x01,0x09,0x00,0x08,0x40,0x00,0x03,0x00,0x08,0x30,0x00,
  0x01,0x09,0x00,0x08,0x44,0x00,0x03,0x00,0x08,0x40,0x00,0x01,0x09,0x00,0x08,0x48,
@@ -1562,9 +1562,9 @@
  0x00,0x01,0x09,0x00,0x0a,0x08,0x00,0x03,0x00,0x0a,0x04,0x00,0x01,0x09,0x00,0x0a,
  0x0c,0x00,0x03,0x00,0x0a,0x08,0x00,0x01,0x09,0x00,0x0a,0x10,0x00,0x03,0x00,0x0a,
  0x0c,0x00,0x01,0x09,0x00,0x0a,0x20,0x00,0x03,0x00,0x0a,0x10,0x00,0x01,0x09,0x00,
-  0x0a,0x24,0x00,0x03,0x00,0x0a,0x20,0x00,0x01,0x09,0x00,0x0a,0x28,0x00,0x03,0x00,
-  0x0a,0x24,0x00,0x01,0x09,0x00,0x0a,0x2e,0x00,0x03,0x00,0x0a,0x28,0x00,0x01,0x09,
-  0x00,0x0a,0x30,0x00,0x03,0x00,0x0a,0x2e,0x00,0x01,0x09,0x00,0x0a,0x40,0x00,0x03,
+  0x0a,0x26,0x00,0x03,0x00,0x0a,0x20,0x00,0x01,0x09,0x00,0x0a,0x28,0x01,0x03,0x00,
+  0x0a,0x26,0x00,0x01,0x09,0x00,0x0a,0x2c,0x01,0x03,0x00,0x0a,0x28,0x01,0x01,0x09,
+  0x00,0x0a,0x30,0x00,0x03,0x00,0x0a,0x2c,0x01,0x01,0x09,0x00,0x0a,0x40,0x00,0x03,
  0x00,0x0a,0x30,0x00,0x01,0x09,0x00,0x0a,0x44,0x00,0x03,0x00,0x0a,0x40,0x00,0x01,
  0x09,0x00,0x0a,0x48,0x00,0x03,0x00,0x0a,0x44,0x00,0x01,0x09,0x00,0x0a,0x4c,0x00,
  0x03,0x00,0x0a,0x48,0x00,0x01,0x09,0x00,0x0a,0x50,0x00,0x03,0x00,0x0a,0x4c,0x00,
@@ -1578,14 +1578,14 @@
  0x00,0x0a,0xc0,0x00,0x43,0x00,0x0a,0xb0,0x00,0x01,0x09,0x00,0x0a,0xc4,0x00,0x03,
  0x00,0x0a,0xc0,0x00,0x41,0x09,0x00,0x0a,0xc8,0x00,0x03,0x00,0x0a,0xc4,0x00,0x01,
  0x09,0x00,0x0a,0xcc,0x00,0x03,0x00,0x0a,0xc8,0x00,0x01,0x09,0x00,0x0a,0xd0,0x00,
-  0x03,0x00,0x0a,0xcc,0x00,0x01,0x09,0x00,0x0b,0x00,0x02,0x03,0x00,0x0a,0xd0,0x00,
-  0x01,0x09,0x00,0x0b,0x04,0x00,0x03,0x00,0x0b,0x00,0x02,0x01,0x09,0x00,0x0b,0x0a,
+  0x03,0x00,0x0a,0xcc,0x00,0x01,0x09,0x00,0x0b,0x00,0x00,0x03,0x00,0x0a,0xd0,0x00,
+  0x01,0x09,0x00,0x0b,0x04,0x00,0x03,0x00,0x0b,0x00,0x00,0x01,0x09,0x00,0x0b,0x0a,
  0x00,0x03,0x00,0x0b,0x04,0x00,0x01,0x09,0x00,0x0b,0x0c,0x00,0x03,0x00,0x0b,0x0a,
  0x00,0x01,0x09,0x00,0x0b,0x10,0x00,0x03,0x00,0x0b,0x0c,0x00,0x01,0x09,0x00,0x0b,
-  0x20,0x01,0x03,0x00,0x0b,0x10,0x00,0x01,0x09,0x00,0x0b,0x26,0x01,0x03,0x00,0x0b,
-  0x20,0x01,0x01,0x09,0x00,0x0b,0x28,0x01,0x03,0x00,0x0b,0x26,0x01,0x01,0x09,0x00,
-  0x0b,0x2c,0x01,0x03,0x00,0x0b,0x28,0x01,0x01,0x09,0x00,0x0b,0x30,0x00,0x03,0x00,
-  0x0b,0x2c,0x01,0x01,0x09,0x00,0x0b,0x40,0x00,0x03,0x00,0x0b,0x30,0x00,0x01,0x09,
+  0x22,0x01,0x03,0x00,0x0b,0x10,0x00,0x01,0x09,0x00,0x0b,0x26,0x01,0x03,0x00,0x0b,
+  0x22,0x01,0x01,0x09,0x00,0x0b,0x28,0x01,0x03,0x00,0x0b,0x26,0x01,0x01,0x09,0x00,
+  0x0b,0x2e,0x01,0x03,0x00,0x0b,0x28,0x01,0x01,0x09,0x00,0x0b,0x30,0x00,0x03,0x00,
+  0x0b,0x2e,0x01,0x01,0x09,0x00,0x0b,0x40,0x00,0x03,0x00,0x0b,0x30,0x00,0x01,0x09,
  0x00,0x0b,0x44,0x00,0x03,0x00,0x0b,0x40,0x00,0x01,0x09,0x00,0x0b,0x48,0x00,0x03,
  0x00,0x0b,0x44,0x00,0x01,0x09,0x00,0x0b,0x4c,0x00,0x03,0x00,0x0b,0x48,0x00,0x01,
  0x09,0x00,0x0b,0x50,0x00,0x03,0x00,0x0b,0x4c,0x00,0x01,0x09,0x00,0x0b,0x80,0x00,
@@ -1619,19 +1619,19 @@
  0xac,0x00,0x01,0x09,0x00,0x0c,0xc0,0x00,0x03,0x00,0x0c,0xb0,0x00,0x01,0x09,0x00,
  0x0c,0xc4,0x00,0x03,0x00,0x0c,0xc0,0x00,0x01,0x09,0x00,0x0c,0xc8,0x00,0x03,0x00,
  0x0c,0xc4,0x00,0x01,0x09,0x00,0x0c,0xcc,0x00,0x03,0x00,0x0c,0xc8,0x00,0x01,0x09,
-  0x00,0x0c,0xd0,0x00,0x03,0x00,0x0c,0xcc,0x00,0x01,0x09,0x00,0x0d,0x03,0x46,0x03,
-  0x00,0x0c,0xd0,0x00,0x01,0x09,0x00,0x0d,0x07,0x02,0x03,0x00,0x0d,0x03,0x46,0x01,
+  0x00,0x0c,0xd0,0x00,0x03,0x00,0x0c,0xcc,0x00,0x01,0x09,0x00,0x0d,0x03,0x02,0x03,
+  0x00,0x0c,0xd0,0x00,0x01,0x09,0x00,0x0d,0x07,0x02,0x03,0x00,0x0d,0x03,0x02,0x01,
  0x09,0x00,0x0d,0x0b,0x02,0x03,0x00,0x0d,0x07,0x02,0x01,0x09,0x00,0x0d,0x0f,0x02,
  0x03,0x00,0x0d,0x0b,0x02,0x01,0x09,0x00,0x0d,0x13,0x02,0x03,0x00,0x0d,0x0f,0x02,
  0x01,0x09,0x00,0x0d,0x23,0x03,0x03,0x00,0x0d,0x13,0x02,0x01,0x09,0x00,0x0d,0x27,
-  0x03,0x03,0x00,0x0d,0x23,0x03,0x01,0x09,0x00,0x0d,0x2b,0x03,0x03,0x00,0x0d,0x27,
-  0x03,0x01,0x09,0x00,0x0d,0x2f,0x01,0x03,0x00,0x0d,0x2b,0x03,0x01,0x09,0x00,0x0d,
+  0x07,0x03,0x00,0x0d,0x23,0x03,0x01,0x09,0x00,0x0d,0x2b,0x03,0x03,0x00,0x0d,0x27,
+  0x07,0x01,0x09,0x00,0x0d,0x2f,0x01,0x03,0x00,0x0d,0x2b,0x03,0x01,0x09,0x00,0x0d,
  0x30,0x00,0x03,0x00,0x0d,0x2f,0x01,0x01,0x09,0x00,0x0d,0x40,0x00,0x03,0x00,0x0d,
  0x30,0x00,0x01,0x09,0x00,0x0d,0x44,0x00,0x03,0x00,0x0d,0x40,0x00,0x01,0x09,0x00,
  0x0d,0x48,0x00,0x03,0x00,0x0d,0x44,0x00,0x01,0x09,0x00,0x0d,0x4c,0x00,0x03,0x00,
  0x0d,0x48,0x00,0x01,0x09,0x00,0x0d,0x50,0x00,0x03,0x00,0x0d,0x4c,0x00,0x01,0x09,
-  0x00,0x0d,0x80,0x00,0x03,0x00,0x0d,0x50,0x00,0x01,0x09,0x00,0x0d,0x84,0x00,0x03,
-  0x00,0x0d,0x80,0x00,0x01,0x09,0x00,0x0d,0x88,0x00,0x03,0x00,0x0d,0x84,0x00,0x01,
+  0x00,0x0d,0x80,0x04,0x03,0x00,0x0d,0x50,0x00,0x01,0x09,0x00,0x0d,0x84,0x00,0x03,
+  0x00,0x0d,0x80,0x04,0x01,0x09,0x00,0x0d,0x88,0x00,0x03,0x00,0x0d,0x84,0x00,0x01,
  0x09,0x00,0x0d,0x8c,0x00,0x03,0x00,0x0d,0x88,0x00,0x01,0x09,0x00,0x0d,0x90,0x00,
  0x03,0x00,0x0d,0x8c,0x00,0x01,0x09,0x00,0x0d,0xa0,0x00,0x03,0x00,0x0d,0x90,0x00,
  0x01,0x09,0x00,0x0d,0xa4,0x00,0x03,0x00,0x0d,0xa0,0x00,0x01,0x09,0x00,0x0d,0xa8,
@@ -1641,26 +1641,26 @@
  0xc0,0x00,0x01,0x09,0x00,0x0d,0xc8,0x00,0x03,0x00,0x0d,0xc4,0x00,0x01,0x09,0x00,
  0x0d,0xcc,0x00,0x03,0x00,0x0d,0xc8,0x00,0x01,0x09,0x00,0x0d,0xd0,0x00,0x03,0x00,
  0x0d,0xcc,0x00,0x01,0x09,0x00,0x0e,0x00,0x00,0x03,0x00,0x0d,0xd0,0x00,0x01,0x09,
-  0x00,0x0e,0x04,0x40,0x13,0x00,0x0e,0x00,0x00,0x01,0x09,0x00,0x0e,0x08,0x80,0x33,
-  0x00,0x0e,0x04,0x40,0x11,0x09,0x00,0x0e,0x0c,0x80,0x03,0x00,0x0e,0x08,0x80,0x31,
+  0x00,0x0e,0x04,0xc0,0x03,0x00,0x0e,0x00,0x00,0x01,0x09,0x00,0x0e,0x08,0x00,0x03,
+  0x00,0x0e,0x04,0xc0,0x01,0x09,0x00,0x0e,0x0c,0x80,0x03,0x00,0x0e,0x08,0x00,0x01,
  0x09,0x00,0x0e,0x10,0x00,0x03,0x00,0x0e,0x0c,0x80,0x01,0x09,0x00,0x0e,0x20,0x00,
-  0x03,0x00,0x0e,0x10,0x00,0x01,0x09,0x00,0x0e,0x24,0x04,0x03,0x00,0x0e,0x20,0x00,
-  0x01,0x09,0x00,0x0e,0x28,0x00,0x13,0x00,0x0e,0x24,0x04,0x01,0x09,0x00,0x0e,0x2c,
-  0x00,0x13,0x00,0x0e,0x28,0x00,0x11,0x09,0x00,0x0e,0x30,0x00,0x03,0x00,0x0e,0x2c,
-  0x00,0x11,0x09,0x00,0x0e,0x40,0x48,0x03,0x00,0x0e,0x30,0x00,0x01,0x09,0x00,0x0e,
-  0x44,0x20,0x0b,0x00,0x0e,0x40,0x48,0x01,0x09,0x00,0x0e,0x48,0x80,0x1b,0x00,0x0e,
-  0x44,0x20,0x09,0x09,0x00,0x0e,0x4c,0x80,0x13,0x00,0x0e,0x48,0x80,0x19,0x09,0x00,
-  0x0e,0x50,0x00,0x03,0x00,0x0e,0x4c,0x80,0x11,0x09,0x00,0x0e,0x80,0x80,0x33,0x00,
-  0x0e,0x50,0x00,0x01,0x09,0x00,0x0e,0x84,0x84,0x03,0x00,0x0e,0x80,0x80,0x31,0x09,
-  0x00,0x0e,0x88,0x40,0x03,0x00,0x0e,0x84,0x84,0x01,0x09,0x00,0x0e,0x8c,0x00,0x03,
-  0x00,0x0e,0x88,0x40,0x01,0x09,0x00,0x0e,0x90,0x00,0x03,0x00,0x0e,0x8c,0x00,0x01,
-  0x09,0x00,0x0e,0xa0,0x04,0x13,0x00,0x0e,0x90,0x00,0x01,0x09,0x00,0x0e,0xa4,0x00,
-  0x13,0x00,0x0e,0xa0,0x04,0x11,0x09,0x00,0x0e,0xa8,0x00,0x03,0x00,0x0e,0xa4,0x00,
-  0x11,0x09,0x00,0x0e,0xac,0x00,0x03,0x00,0x0e,0xa8,0x00,0x01,0x09,0x00,0x0e,0xb0,
-  0x00,0x03,0x00,0x0e,0xac,0x00,0x01,0x09,0x00,0x0e,0xc0,0xa0,0x1b,0x00,0x0e,0xb0,
-  0x00,0x01,0x09,0x00,0x0e,0xc4,0xc8,0x13,0x00,0x0e,0xc0,0xa0,0x19,0x09,0x00,0x0e,
-  0xc8,0x40,0x03,0x00,0x0e,0xc4,0xc8,0x11,0x09,0x00,0x0e,0xcc,0x00,0x03,0x00,0x0e,
-  0xc8,0x40,0x01,0x09,0x00,0x0e,0xd0,0x00,0x03,0x00,0x0e,0xcc,0x00,0x01,0x09,0x00,
+  0x03,0x00,0x0e,0x10,0x00,0x01,0x09,0x00,0x0e,0x24,0x00,0x13,0x00,0x0e,0x20,0x00,
+  0x01,0x09,0x00,0x0e,0x28,0x00,0x03,0x00,0x0e,0x24,0x00,0x11,0x09,0x00,0x0e,0x2c,
+  0x00,0x13,0x00,0x0e,0x28,0x00,0x01,0x09,0x00,0x0e,0x30,0x00,0x03,0x00,0x0e,0x2c,
+  0x00,0x11,0x09,0x00,0x0e,0x40,0x60,0x03,0x00,0x0e,0x30,0x00,0x01,0x09,0x00,0x0e,
+  0x44,0x48,0x13,0x00,0x0e,0x40,0x60,0x01,0x09,0x00,0x0e,0x48,0xc0,0x03,0x00,0x0e,
+  0x44,0x48,0x11,0x09,0x00,0x0e,0x4c,0x80,0x13,0x00,0x0e,0x48,0xc0,0x01,0x09,0x00,
+  0x0e,0x50,0x00,0x03,0x00,0x0e,0x4c,0x80,0x11,0x09,0x00,0x0e,0x80,0x00,0x03,0x00,
+  0x0e,0x50,0x00,0x01,0x09,0x00,0x0e,0x84,0x00,0x23,0x00,0x0e,0x80,0x00,0x01,0x09,
+  0x00,0x0e,0x88,0x40,0x13,0x00,0x0e,0x84,0x00,0x21,0x09,0x00,0x0e,0x8c,0x00,0x03,
+  0x00,0x0e,0x88,0x40,0x11,0x09,0x00,0x0e,0x90,0x00,0x03,0x00,0x0e,0x8c,0x00,0x01,
+  0x09,0x00,0x0e,0xa0,0x00,0x03,0x00,0x0e,0x90,0x00,0x01,0x09,0x00,0x0e,0xa4,0x00,
+  0x03,0x00,0x0e,0xa0,0x00,0x01,0x09,0x00,0x0e,0xa8,0x00,0x03,0x00,0x0e,0xa4,0x00,
+  0x01,0x09,0x00,0x0e,0xac,0x00,0x03,0x00,0x0e,0xa8,0x00,0x01,0x09,0x00,0x0e,0xb0,
+  0x00,0x03,0x00,0x0e,0xac,0x00,0x01,0x09,0x00,0x0e,0xc0,0x00,0x03,0x00,0x0e,0xb0,
+  0x00,0x01,0x09,0x00,0x0e,0xc4,0xa0,0x03,0x00,0x0e,0xc0,0x00,0x01,0x09,0x00,0x0e,
+  0xc8,0x08,0x0b,0x00,0x0e,0xc4,0xa0,0x01,0x09,0x00,0x0e,0xcc,0x00,0x03,0x00,0x0e,
+  0xc8,0x08,0x09,0x09,0x00,0x0e,0xd0,0x00,0x03,0x00,0x0e,0xcc,0x00,0x01,0x09,0x00,
  0x0f,0x00,0x02,0x03,0x00,0x0e,0xd0,0x00,0x01,0x09,0x00,0x0f,0x04,0x00,0x03,0x00,
  0x0f,0x00,0x02,0x01,0x09,0x00,0x0f,0x0a,0x00,0x03,0x00,0x0f,0x04,0x00,0x01,0x09,
  0x00,0x0f,0x0c,0x00,0x03,0x00,0x0f,0x0a,0x00,0x01,0x09,0x00,0x0f,0x12,0x00,0x03,
@@ -1682,17 +1682,17 @@
  0x00,0x03,0x00,0x0f,0xc0,0x10,0x01,0x09,0x00,0x0f,0xc8,0x00,0x03,0x00,0x0f,0xc4,
  0x00,0x01,0x09,0x00,0x0f,0xcc,0x00,0x03,0x00,0x0f,0xc8,0x00,0x01,0x09,0x00,0x0f,
  0xd0,0x00,0x03,0x00,0x0f,0xcc,0x00,0x01,0x09,0x00,0x10,0x01,0x82,0x03,0x00,0x0f,
-  0xd0,0x00,0x01,0x09,0x00,0x10,0x04,0x82,0x03,0x00,0x10,0x01,0x82,0x01,0x09,0x00,
-  0x10,0x0a,0x82,0x03,0x00,0x10,0x04,0x82,0x01,0x09,0x00,0x10,0x0e,0x82,0x03,0x00,
-  0x10,0x0a,0x82,0x01,0x09,0x00,0x10,0x12,0x02,0x03,0x00,0x10,0x0e,0x82,0x01,0x09,
-  0x00,0x10,0x20,0x03,0x13,0x00,0x10,0x12,0x02,0x01,0x09,0x00,0x10,0x26,0x03,0x13,
+  0xd0,0x00,0x01,0x09,0x00,0x10,0x05,0x82,0x03,0x00,0x10,0x01,0x82,0x01,0x09,0x00,
+  0x10,0x0a,0x82,0x03,0x00,0x10,0x05,0x82,0x01,0x09,0x00,0x10,0x0c,0x82,0x03,0x00,
+  0x10,0x0a,0x82,0x01,0x09,0x00,0x10,0x12,0x82,0x03,0x00,0x10,0x0c,0x82,0x01,0x09,
+  0x00,0x10,0x20,0x03,0x13,0x00,0x10,0x12,0x82,0x01,0x09,0x00,0x10,0x26,0x03,0x13,
  0x00,0x10,0x20,0x03,0x11,0x09,0x00,0x10,0x2a,0x03,0x13,0x00,0x10,0x26,0x03,0x11,
  0x09,0x00,0x10,0x2c,0x01,0x13,0x00,0x10,0x2a,0x03,0x11,0x09,0x00,0x10,0x30,0x00,
-  0x03,0x00,0x10,0x2c,0x01,0x11,0x09,0x00,0x10,0x40,0x00,0x13,0x00,0x10,0x30,0x00,
-  0x01,0x09,0x00,0x10,0x44,0x00,0x13,0x00,0x10,0x40,0x00,0x11,0x09,0x00,0x10,0x48,
+  0x13,0x00,0x10,0x2c,0x01,0x11,0x09,0x00,0x10,0x40,0x00,0x13,0x00,0x10,0x30,0x00,
+  0x11,0x09,0x00,0x10,0x44,0x00,0x13,0x00,0x10,0x40,0x00,0x11,0x09,0x00,0x10,0x48,
  0x00,0x13,0x00,0x10,0x44,0x00,0x11,0x09,0x00,0x10,0x4c,0x00,0x13,0x00,0x10,0x48,
-  0x00,0x11,0x09,0x00,0x10,0x50,0x00,0x03,0x00,0x10,0x4c,0x00,0x11,0x09,0x00,0x10,
-  0x80,0x00,0x03,0x00,0x10,0x50,0x00,0x01,0x09,0x00,0x10,0x84,0x00,0x03,0x00,0x10,
+  0x00,0x11,0x09,0x00,0x10,0x50,0x00,0x13,0x00,0x10,0x4c,0x00,0x11,0x09,0x00,0x10,
+  0x80,0x00,0x03,0x00,0x10,0x50,0x00,0x11,0x09,0x00,0x10,0x84,0x00,0x03,0x00,0x10,
  0x80,0x00,0x01,0x09,0x00,0x10,0x88,0x00,0x03,0x00,0x10,0x84,0x00,0x01,0x09,0x00,
  0x10,0x8c,0x00,0x03,0x00,0x10,0x88,0x00,0x01,0x09,0x00,0x10,0x90,0x00,0x03,0x00,
  0x10,0x8c,0x00,0x01,0x09,0x00,0x10,0xa0,0x00,0x03,0x00,0x10,0x90,0x00,0x01,0x09,
@@ -1702,28 +1702,28 @@
  0x03,0x00,0x10,0xb0,0x00,0x01,0x09,0x00,0x10,0xc4,0x00,0x03,0x00,0x10,0xc0,0x00,
  0x01,0x09,0x00,0x10,0xc8,0x00,0x03,0x00,0x10,0xc4,0x00,0x01,0x09,0x00,0x10,0xcc,
  0x00,0x03,0x00,0x10,0xc8,0x00,0x01,0x09,0x00,0x10,0xd0,0x00,0x03,0x00,0x10,0xcc,
-  0x00,0x01,0x09,0x00,0x11,0x00,0x00,0x03,0x00,0x10,0xd0,0x00,0x01,0x09,0x00,0x11,
-  0x04,0x04,0x03,0x00,0x11,0x00,0x00,0x01,0x09,0x00,0x11,0x08,0x00,0x13,0x00,0x11,
-  0x04,0x04,0x01,0x09,0x00,0x11,0x0c,0x00,0x03,0x00,0x11,0x08,0x00,0x11,0x09,0x00,
-  0x11,0x10,0x00,0x03,0x00,0x11,0x0c,0x00,0x01,0x09,0x00,0x11,0x20,0x00,0x03,0x00,
-  0x11,0x10,0x00,0x01,0x09,0x00,0x11,0x24,0x04,0x03,0x00,0x11,0x20,0x00,0x01,0x09,
-  0x00,0x11,0x28,0x00,0x03,0x00,0x11,0x24,0x04,0x01,0x09,0x00,0x11,0x2c,0x00,0x03,
-  0x00,0x11,0x28,0x00,0x01,0x09,0x00,0x11,0x30,0x00,0x03,0x00,0x11,0x2c,0x00,0x01,
-  0x09,0x00,0x11,0x40,0xa0,0x03,0x00,0x11,0x30,0x00,0x01,0x09,0x00,0x11,0x44,0x40,
-  0x03,0x00,0x11,0x40,0xa0,0x01,0x09,0x00,0x11,0x48,0x80,0x0b,0x00,0x11,0x44,0x40,
-  0x01,0x09,0x00,0x11,0x4c,0x80,0x03,0x00,0x11,0x48,0x80,0x09,0x09,0x00,0x11,0x50,
-  0x80,0x03,0x00,0x11,0x4c,0x80,0x01,0x09,0x00,0x11,0x80,0x00,0x13,0x00,0x11,0x50,
-  0x80,0x01,0x09,0x00,0x11,0x84,0x80,0x03,0x00,0x11,0x80,0x00,0x11,0x09,0x00,0x11,
-  0x88,0x40,0x03,0x00,0x11,0x84,0x80,0x01,0x09,0x00,0x11,0x8c,0x00,0x03,0x00,0x11,
-  0x88,0x40,0x01,0x09,0x00,0x11,0x90,0x00,0x03,0x00,0x11,0x8c,0x00,0x01,0x09,0x00,
-  0x11,0xa0,0x04,0x03,0x00,0x11,0x90,0x00,0x01,0x09,0x00,0x11,0xa4,0x00,0x13,0x00,
-  0x11,0xa0,0x04,0x01,0x09,0x00,0x11,0xa8,0x00,0x03,0x00,0x11,0xa4,0x00,0x11,0x09,
-  0x00,0x11,0xac,0x00,0x03,0x00,0x11,0xa8,0x00,0x01,0x09,0x00,0x11,0xb0,0x00,0x03,
-  0x00,0x11,0xac,0x00,0x01,0x09,0x00,0x11,0xc0,0x40,0x0b,0x00,0x11,0xb0,0x00,0x01,
-  0x09,0x00,0x11,0xc4,0x28,0x13,0x00,0x11,0xc0,0x40,0x09,0x09,0x00,0x11,0xc8,0x00,
-  0x03,0x00,0x11,0xc4,0x28,0x11,0x09,0x00,0x11,0xcc,0x00,0x03,0x00,0x11,0xc8,0x00,
-  0x01,0x09,0x00,0x11,0xd0,0x00,0x03,0x00,0x11,0xcc,0x00,0x01,0x09,0x00,0x12,0x00,
-  0x00,0x03,0x00,0x11,0xd0,0x00,0x01,0x09,0x00,0x12,0x04,0x00,0x03,0x00,0x12,0x00,
+  0x00,0x01,0x09,0x00,0x11,0x00,0xc0,0x13,0x00,0x10,0xd0,0x00,0x01,0x09,0x00,0x11,
+  0x04,0x00,0x13,0x00,0x11,0x00,0xc0,0x11,0x09,0x00,0x11,0x08,0x80,0x23,0x00,0x11,
+  0x04,0x00,0x11,0x09,0x00,0x11,0x0c,0x00,0x03,0x00,0x11,0x08,0x80,0x21,0x09,0x00,
+  0x11,0x10,0x00,0x03,0x00,0x11,0x0c,0x00,0x01,0x09,0x00,0x11,0x20,0x00,0x13,0x00,
+  0x11,0x10,0x00,0x01,0x09,0x00,0x11,0x24,0x00,0x03,0x00,0x11,0x20,0x00,0x11,0x09,
+  0x00,0x11,0x28,0x00,0x13,0x00,0x11,0x24,0x00,0x01,0x09,0x00,0x11,0x2c,0x00,0x03,
+  0x00,0x11,0x28,0x00,0x11,0x09,0x00,0x11,0x30,0x00,0x03,0x00,0x11,0x2c,0x00,0x01,
+  0x09,0x00,0x11,0x40,0x08,0x1b,0x00,0x11,0x30,0x00,0x01,0x09,0x00,0x11,0x44,0x20,
+  0x0b,0x00,0x11,0x40,0x08,0x19,0x09,0x00,0x11,0x48,0xc0,0x13,0x00,0x11,0x44,0x20,
+  0x09,0x09,0x00,0x11,0x4c,0x00,0x03,0x00,0x11,0x48,0xc0,0x11,0x09,0x00,0x11,0x50,
+  0x00,0x03,0x00,0x11,0x4c,0x00,0x01,0x09,0x00,0x11,0x80,0x00,0x03,0x00,0x11,0x50,
+  0x00,0x01,0x09,0x00,0x11,0x84,0x00,0x23,0x00,0x11,0x80,0x00,0x01,0x09,0x00,0x11,
+  0x88,0x40,0x13,0x00,0x11,0x84,0x00,0x21,0x09,0x00,0x11,0x8c,0x00,0x03,0x00,0x11,
+  0x88,0x40,0x11,0x09,0x00,0x11,0x90,0x80,0x03,0x00,0x11,0x8c,0x00,0x01,0x09,0x00,
+  0x11,0xa0,0x00,0x03,0x00,0x11,0x90,0x80,0x01,0x09,0x00,0x11,0xa4,0x00,0x03,0x00,
+  0x11,0xa0,0x00,0x01,0x09,0x00,0x11,0xa8,0x00,0x03,0x00,0x11,0xa4,0x00,0x01,0x09,
+  0x00,0x11,0xac,0x00,0x03,0x00,0x11,0xa8,0x00,0x01,0x09,0x00,0x11,0xb0,0x00,0x13,
+  0x00,0x11,0xac,0x00,0x01,0x09,0x00,0x11,0xc0,0x20,0x03,0x00,0x11,0xb0,0x00,0x11,
+  0x09,0x00,0x11,0xc4,0xc0,0x03,0x00,0x11,0xc0,0x20,0x01,0x09,0x00,0x11,0xc8,0x08,
+  0x0b,0x00,0x11,0xc4,0xc0,0x01,0x09,0x00,0x11,0xcc,0x00,0x03,0x00,0x11,0xc8,0x08,
+  0x09,0x09,0x00,0x11,0xd0,0x00,0x13,0x00,0x11,0xcc,0x00,0x01,0x09,0x00,0x12,0x00,
+  0x00,0x03,0x00,0x11,0xd0,0x00,0x11,0x09,0x00,0x12,0x04,0x00,0x03,0x00,0x12,0x00,
  0x00,0x01,0x09,0x00,0x12,0x08,0x00,0x03,0x00,0x12,0x04,0x00,0x01,0x09,0x00,0x12,
  0x0c,0x00,0x03,0x00,0x12,0x08,0x00,0x01,0x09,0x00,0x12,0x10,0x00,0x03,0x00,0x12,
  0x0c,0x00,0x01,0x09,0x00,0x12,0x20,0x00,0x03,0x00,0x12,0x10,0x00,0x01,0x09,0x00,
@@ -1757,17 +1757,17 @@
  0x03,0x00,0x13,0x50,0x00,0x01,0x09,0x00,0x13,0x84,0x00,0x03,0x00,0x13,0x80,0x00,
  0x01,0x09,0x00,0x13,0x88,0x00,0x03,0x00,0x13,0x84,0x00,0x01,0x09,0x00,0x13,0x8c,
  0x00,0x03,0x00,0x13,0x88,0x00,0x01,0x09,0x00,0x13,0x90,0x00,0x03,0x00,0x13,0x8c,
-  0x00,0x01,0x09,0x00,0x13,0xa0,0x00,0x03,0x00,0x13,0x90,0x00,0x01,0x09,0x00,0x13,
-  0xa4,0x00,0x03,0x00,0x13,0xa0,0x00,0x01,0x09,0x00,0x13,0xa8,0x00,0x03,0x00,0x13,
+  0x00,0x01,0x09,0x00,0x13,0xa2,0x00,0x03,0x00,0x13,0x90,0x00,0x01,0x09,0x00,0x13,
+  0xa4,0x00,0x03,0x00,0x13,0xa2,0x00,0x01,0x09,0x00,0x13,0xa8,0x00,0x03,0x00,0x13,
  0xa4,0x00,0x01,0x09,0x00,0x13,0xac,0x00,0x03,0x00,0x13,0xa8,0x00,0x01,0x09,0x00,
  0x13,0xb0,0x00,0x03,0x00,0x13,0xac,0x00,0x01,0x09,0x00,0x13,0xc0,0x00,0x03,0x00,
  0x13,0xb0,0x00,0x01,0x09,0x00,0x13,0xc4,0x00,0x03,0x00,0x13,0xc0,0x00,0x01,0x09,
  0x00,0x13,0xc8,0x00,0x03,0x00,0x13,0xc4,0x00,0x01,0x09,0x00,0x13,0xcc,0x00,0x03,
  0x00,0x13,0xc8,0x00,0x01,0x09,0x00,0x13,0xd0,0x00,0x03,0x00,0x13,0xcc,0x00,0x01,
-  0x09,0x00,0x14,0x00,0x00,0x03,0x00,0x13,0xd0,0x00,0x01,0x09,0x00,0x14,0x05,0x00,
-  0x03,0x00,0x14,0x00,0x00,0x01,0x09,0x00,0x14,0x08,0x00,0x03,0x00,0x14,0x05,0x00,
-  0x01,0x09,0x00,0x14,0x0c,0x00,0x03,0x00,0x14,0x08,0x00,0x01,0x09,0x00,0x14,0x10,
-  0x00,0x03,0x00,0x14,0x0c,0x00,0x01,0x09,0x00,0x14,0x23,0x00,0x03,0x00,0x14,0x10,
+  0x09,0x00,0x14,0x00,0x00,0x03,0x00,0x13,0xd0,0x00,0x01,0x09,0x00,0x14,0x04,0x00,
+  0x03,0x00,0x14,0x00,0x00,0x01,0x09,0x00,0x14,0x08,0x00,0x03,0x00,0x14,0x04,0x00,
+  0x01,0x09,0x00,0x14,0x0e,0x00,0x03,0x00,0x14,0x08,0x00,0x01,0x09,0x00,0x14,0x10,
+  0x00,0x03,0x00,0x14,0x0e,0x00,0x01,0x09,0x00,0x14,0x23,0x00,0x03,0x00,0x14,0x10,
  0x00,0x01,0x09,0x00,0x14,0x24,0x00,0x03,0x00,0x14,0x23,0x00,0x01,0x09,0x00,0x14,
  0x28,0x00,0x03,0x00,0x14,0x24,0x00,0x01,0x09,0x00,0x14,0x2e,0x00,0x03,0x00,0x14,
  0x28,0x00,0x01,0x09,0x00,0x14,0x30,0x00,0x03,0x00,0x14,0x2e,0x00,0x01,0x09,0x00,
@@ -1785,49 +1785,49 @@
  0x14,0xc4,0x00,0x03,0x00,0x14,0xc0,0x00,0x01,0x09,0x00,0x14,0xc8,0x00,0x03,0x00,
  0x14,0xc4,0x00,0x01,0x09,0x00,0x14,0xcc,0x00,0x03,0x00,0x14,0xc8,0x00,0x01,0x09,
  0x00,0x14,0xd0,0x00,0x03,0x00,0x14,0xcc,0x00,0x01,0x09,0x00,0x15,0x00,0x00,0x03,
-  0x00,0x14,0xd0,0x00,0x01,0x09,0x00,0x15,0x04,0x00,0x03,0x00,0x15,0x00,0x00,0x01,
-  0x09,0x00,0x15,0x08,0x00,0x03,0x00,0x15,0x04,0x00,0x01,0x09,0x00,0x15,0x0c,0x00,
-  0x03,0x00,0x15,0x08,0x00,0x01,0x09,0x00,0x15,0x10,0x00,0x03,0x00,0x15,0x0c,0x00,
-  0x01,0x09,0x00,0x15,0x20,0x00,0x03,0x00,0x15,0x10,0x00,0x01,0x09,0x00,0x15,0x24,
-  0x00,0x03,0x00,0x15,0x20,0x00,0x01,0x09,0x00,0x15,0x28,0x00,0x03,0x00,0x15,0x24,
-  0x00,0x01,0x09,0x00,0x15,0x2c,0x00,0x03,0x00,0x15,0x28,0x00,0x01,0x09,0x00,0x15,
-  0x30,0x00,0x03,0x00,0x15,0x2c,0x00,0x01,0x09,0x00,0x15,0x40,0x00,0x03,0x00,0x15,
-  0x30,0x00,0x01,0x09,0x00,0x15,0x44,0x00,0x03,0x00,0x15,0x40,0x00,0x01,0x09,0x00,
-  0x15,0x48,0x00,0x03,0x00,0x15,0x44,0x00,0x01,0x09,0x00,0x15,0x4c,0x00,0x03,0x00,
-  0x15,0x48,0x00,0x01,0x09,0x00,0x15,0x50,0x00,0x03,0x00,0x15,0x4c,0x00,0x01,0x09,
-  0x00,0x15,0x80,0x00,0x03,0x00,0x15,0x50,0x00,0x01,0x09,0x00,0x15,0x84,0x00,0xc3,
-  0x00,0x15,0x80,0x00,0x01,0x09,0x00,0x15,0x88,0x00,0x03,0x00,0x15,0x84,0x00,0xc1,
+  0x00,0x14,0xd0,0x00,0x01,0x09,0x00,0x15,0x04,0x00,0x13,0x00,0x15,0x00,0x00,0x01,
+  0x09,0x00,0x15,0x08,0xc0,0x33,0x00,0x15,0x04,0x00,0x11,0x09,0x00,0x15,0x0c,0x80,
+  0x03,0x00,0x15,0x08,0xc0,0x31,0x09,0x00,0x15,0x10,0x80,0x03,0x00,0x15,0x0c,0x80,
+  0x01,0x09,0x00,0x15,0x20,0x04,0x03,0x00,0x15,0x10,0x80,0x01,0x09,0x00,0x15,0x24,
+  0x00,0x03,0x00,0x15,0x20,0x04,0x01,0x09,0x00,0x15,0x28,0x00,0x13,0x00,0x15,0x24,
+  0x00,0x01,0x09,0x00,0x15,0x2c,0x00,0x13,0x00,0x15,0x28,0x00,0x11,0x09,0x00,0x15,
+  0x30,0x00,0x13,0x00,0x15,0x2c,0x00,0x11,0x09,0x00,0x15,0x40,0x28,0x03,0x00,0x15,
+  0x30,0x00,0x11,0x09,0x00,0x15,0x44,0x28,0x0b,0x00,0x15,0x40,0x28,0x01,0x09,0x00,
+  0x15,0x48,0x48,0x1b,0x00,0x15,0x44,0x28,0x09,0x09,0x00,0x15,0x4c,0x00,0x13,0x00,
+  0x15,0x48,0x48,0x19,0x09,0x00,0x15,0x50,0x00,0x13,0x00,0x15,0x4c,0x00,0x11,0x09,
+  0x00,0x15,0x80,0xc0,0x33,0x00,0x15,0x50,0x00,0x11,0x09,0x00,0x15,0x84,0xc0,0x23,
+  0x00,0x15,0x80,0xc0,0x31,0x09,0x00,0x15,0x88,0x00,0x03,0x00,0x15,0x84,0xc0,0x21,
  0x09,0x00,0x15,0x8c,0x00,0x03,0x00,0x15,0x88,0x00,0x01,0x09,0x00,0x15,0x90,0x00,
-  0x03,0x00,0x15,0x8c,0x00,0x01,0x09,0x00,0x15,0xa0,0x00,0x03,0x00,0x15,0x90,0x00,
-  0x01,0x09,0x00,0x15,0xa4,0x80,0xe3,0x00,0x15,0xa0,0x00,0x01,0x09,0x00,0x15,0xa8,
-  0x00,0x03,0x00,0x15,0xa4,0x80,0xe1,0x09,0x00,0x15,0xac,0x00,0x03,0x00,0x15,0xa8,
+  0x03,0x00,0x15,0x8c,0x00,0x01,0x09,0x00,0x15,0xa0,0x00,0x13,0x00,0x15,0x90,0x00,
+  0x01,0x09,0x00,0x15,0xa4,0x00,0x13,0x00,0x15,0xa0,0x00,0x11,0x09,0x00,0x15,0xa8,
+  0x00,0x03,0x00,0x15,0xa4,0x00,0x11,0x09,0x00,0x15,0xac,0x00,0x03,0x00,0x15,0xa8,
  0x00,0x01,0x09,0x00,0x15,0xb0,0x00,0x03,0x00,0x15,0xac,0x00,0x01,0x09,0x00,0x15,
-  0xc0,0x00,0x03,0x00,0x15,0xb0,0x00,0x01,0x09,0x00,0x15,0xc4,0x00,0x63,0x00,0x15,
-  0xc0,0x00,0x01,0x09,0x00,0x15,0xc8,0x00,0x03,0x00,0x15,0xc4,0x00,0x61,0x09,0x00,
-  0x15,0xcc,0x00,0x03,0x00,0x15,0xc8,0x00,0x01,0x09,0x00,0x15,0xd0,0x00,0x03,0x00,
-  0x15,0xcc,0x00,0x01,0x09,0x00,0x16,0x02,0x06,0x03,0x00,0x15,0xd0,0x00,0x01,0x09,
-  0x00,0x16,0x06,0x02,0x03,0x00,0x16,0x02,0x06,0x01,0x09,0x00,0x16,0x0b,0x02,0x03,
-  0x00,0x16,0x06,0x02,0x01,0x09,0x00,0x16,0x0d,0x02,0x03,0x00,0x16,0x0b,0x02,0x01,
+  0xc0,0xc0,0x1b,0x00,0x15,0xb0,0x00,0x01,0x09,0x00,0x15,0xc4,0x40,0x13,0x00,0x15,
+  0xc0,0xc0,0x19,0x09,0x00,0x15,0xc8,0x00,0x03,0x00,0x15,0xc4,0x40,0x11,0x09,0x00,
+  0x15,0xcc,0x80,0x03,0x00,0x15,0xc8,0x00,0x01,0x09,0x00,0x15,0xd0,0x00,0x03,0x00,
+  0x15,0xcc,0x80,0x01,0x09,0x00,0x16,0x02,0x02,0x03,0x00,0x15,0xd0,0x00,0x01,0x09,
+  0x00,0x16,0x06,0x3a,0x03,0x00,0x16,0x02,0x02,0x01,0x09,0x00,0x16,0x0b,0x42,0x03,
+  0x00,0x16,0x06,0x3a,0x01,0x09,0x00,0x16,0x0d,0x02,0x03,0x00,0x16,0x0b,0x42,0x01,
  0x09,0x00,0x16,0x13,0x02,0x03,0x00,0x16,0x0d,0x02,0x01,0x09,0x00,0x16,0x20,0x03,
-  0x03,0x00,0x16,0x13,0x02,0x01,0x09,0x00,0x16,0x27,0x03,0x03,0x00,0x16,0x20,0x03,
-  0x01,0x09,0x00,0x16,0x2b,0x03,0x03,0x00,0x16,0x27,0x03,0x01,0x09,0x00,0x16,0x2d,
+  0x03,0x00,0x16,0x13,0x02,0x01,0x09,0x00,0x16,0x27,0x3b,0x03,0x00,0x16,0x20,0x03,
+  0x01,0x09,0x00,0x16,0x2b,0x03,0x03,0x00,0x16,0x27,0x3b,0x01,0x09,0x00,0x16,0x2d,
  0x01,0x03,0x00,0x16,0x2b,0x03,0x01,0x09,0x00,0x16,0x30,0x00,0x03,0x00,0x16,0x2d,
  0x01,0x01,0x09,0x00,0x16,0x40,0x00,0x0b,0x00,0x16,0x30,0x00,0x01,0x09,0x00,0x16,
-  0x44,0x00,0x0b,0x00,0x16,0x40,0x00,0x09,0x09,0x00,0x16,0x48,0x00,0x0b,0x00,0x16,
-  0x44,0x00,0x09,0x09,0x00,0x16,0x4c,0x00,0x03,0x00,0x16,0x48,0x00,0x09,0x09,0x00,
-  0x16,0x50,0x00,0x03,0x00,0x16,0x4c,0x00,0x01,0x09,0x00,0x16,0x83,0x42,0x13,0x00,
-  0x16,0x50,0x00,0x01,0x09,0x00,0x16,0x87,0x02,0x13,0x00,0x16,0x83,0x42,0x11,0x09,
+  0x44,0x14,0x0b,0x00,0x16,0x40,0x00,0x09,0x09,0x00,0x16,0x48,0x00,0x0b,0x00,0x16,
+  0x44,0x14,0x09,0x09,0x00,0x16,0x4c,0x00,0x03,0x00,0x16,0x48,0x00,0x09,0x09,0x00,
+  0x16,0x50,0x00,0x03,0x00,0x16,0x4c,0x00,0x01,0x09,0x00,0x16,0x83,0x02,0x13,0x00,
+  0x16,0x50,0x00,0x01,0x09,0x00,0x16,0x87,0x02,0x13,0x00,0x16,0x83,0x02,0x11,0x09,
  0x00,0x16,0x8b,0x02,0x13,0x00,0x16,0x87,0x02,0x11,0x09,0x00,0x16,0x8f,0x02,0x03,
  0x00,0x16,0x8b,0x02,0x11,0x09,0x00,0x16,0x93,0x02,0x03,0x00,0x16,0x8f,0x02,0x01,
-  0x09,0x00,0x16,0xa3,0x03,0x03,0x00,0x16,0x93,0x02,0x01,0x09,0x00,0x16,0xa7,0x03,
-  0x03,0x00,0x16,0xa3,0x03,0x01,0x09,0x00,0x16,0xab,0x03,0x03,0x00,0x16,0xa7,0x03,
+  0x09,0x00,0x16,0xa3,0x03,0x03,0x00,0x16,0x93,0x02,0x01,0x09,0x00,0x16,0xa7,0x07,
+  0x03,0x00,0x16,0xa3,0x03,0x01,0x09,0x00,0x16,0xab,0x03,0x03,0x00,0x16,0xa7,0x07,
  0x01,0x09,0x00,0x16,0xaf,0x01,0x03,0x00,0x16,0xab,0x03,0x01,0x09,0x00,0x16,0xb0,
  0x00,0x03,0x00,0x16,0xaf,0x01,0x01,0x09,0x00,0x16,0xc0,0x00,0x03,0x00,0x16,0xb0,
-  0x00,0x01,0x09,0x00,0x16,0xc4,0x80,0x03,0x00,0x16,0xc0,0x00,0x01,0x09,0x00,0x16,
-  0xc8,0x40,0x03,0x00,0x16,0xc4,0x80,0x01,0x09,0x00,0x16,0xcc,0x00,0x03,0x00,0x16,
-  0xc8,0x40,0x01,0x09,0x00,0x16,0xd0,0x00,0x03,0x00,0x16,0xcc,0x00,0x01,0x09,0x00,
-  0x17,0x03,0x02,0x03,0x00,0x16,0xd0,0x00,0x01,0x09,0x00,0x17,0x07,0x02,0x03,0x00,
-  0x17,0x03,0x02,0x01,0x09,0x00,0x17,0x0b,0x02,0x03,0x00,0x17,0x07,0x02,0x01,0x09,
+  0x00,0x01,0x09,0x00,0x16,0xc4,0x00,0x03,0x00,0x16,0xc0,0x00,0x01,0x09,0x00,0x16,
+  0xc8,0x08,0x03,0x00,0x16,0xc4,0x00,0x01,0x09,0x00,0x16,0xcc,0x00,0x03,0x00,0x16,
+  0xc8,0x08,0x01,0x09,0x00,0x16,0xd0,0x00,0x03,0x00,0x16,0xcc,0x00,0x01,0x09,0x00,
+  0x17,0x02,0x02,0x03,0x00,0x16,0xd0,0x00,0x01,0x09,0x00,0x17,0x07,0x02,0x03,0x00,
+  0x17,0x02,0x02,0x01,0x09,0x00,0x17,0x0b,0x02,0x03,0x00,0x17,0x07,0x02,0x01,0x09,
  0x00,0x17,0x0f,0x02,0x03,0x00,0x17,0x0b,0x02,0x01,0x09,0x00,0x17,0x11,0x02,0x03,
  0x00,0x17,0x0f,0x02,0x01,0x09,0x00,0x17,0x23,0x03,0x03,0x00,0x17,0x11,0x02,0x01,
  0x09,0x00,0x17,0x27,0x03,0x03,0x00,0x17,0x23,0x03,0x01,0x09,0x00,0x17,0x2b,0x03,
@@ -1839,8 +1839,8 @@
  0x4c,0x00,0x01,0x09,0x00,0x17,0x80,0x0a,0x03,0x00,0x17,0x50,0x00,0x01,0x09,0x00,
  0x17,0x84,0x00,0x03,0x00,0x17,0x80,0x0a,0x01,0x09,0x00,0x17,0x88,0x00,0x03,0x00,
  0x17,0x84,0x00,0x01,0x09,0x00,0x17,0x8e,0x00,0x03,0x00,0x17,0x88,0x00,0x01,0x09,
-  0x00,0x17,0x90,0x00,0x03,0x00,0x17,0x8e,0x00,0x01,0x09,0x00,0x17,0xa2,0x01,0x03,
-  0x00,0x17,0x90,0x00,0x01,0x09,0x00,0x17,0xa6,0x01,0x03,0x00,0x17,0xa2,0x01,0x01,
+  0x00,0x17,0x90,0x00,0x03,0x00,0x17,0x8e,0x00,0x01,0x09,0x00,0x17,0xa3,0x01,0x03,
+  0x00,0x17,0x90,0x00,0x01,0x09,0x00,0x17,0xa6,0x01,0x03,0x00,0x17,0xa3,0x01,0x01,
  0x09,0x00,0x17,0xa8,0x01,0x03,0x00,0x17,0xa6,0x01,0x01,0x09,0x00,0x17,0xae,0x01,
  0x03,0x00,0x17,0xa8,0x01,0x01,0x09,0x00,0x17,0xb0,0x00,0x03,0x00,0x17,0xae,0x01,
  0x01,0x09,0x00,0x17,0xc0,0x00,0x03,0x00,0x17,0xb0,0x00,0x01,0x09,0x00,0x17,0xc4,
@@ -1861,9 +1861,9 @@
  0x80,0x00,0x01,0x09,0x00,0x18,0x88,0x00,0x03,0x00,0x18,0x84,0x00,0x01,0x09,0x00,
  0x18,0x8c,0x00,0x03,0x00,0x18,0x88,0x00,0x01,0x09,0x00,0x18,0x90,0x00,0x03,0x00,
  0x18,0x8c,0x00,0x01,0x09,0x00,0x18,0xa0,0x00,0x03,0x00,0x18,0x90,0x00,0x01,0x09,
-  0x00,0x18,0xa4,0x00,0x03,0x00,0x18,0xa0,0x00,0x01,0x09,0x00,0x18,0xa8,0x00,0x03,
-  0x00,0x18,0xa4,0x00,0x01,0x09,0x00,0x18,0xae,0x00,0x03,0x00,0x18,0xa8,0x00,0x01,
-  0x09,0x00,0x18,0xb0,0x00,0x03,0x00,0x18,0xae,0x00,0x01,0x09,0x00,0x18,0xc0,0x00,
+  0x00,0x18,0xa6,0x00,0x03,0x00,0x18,0xa0,0x00,0x01,0x09,0x00,0x18,0xa8,0x01,0x03,
+  0x00,0x18,0xa6,0x00,0x01,0x09,0x00,0x18,0xac,0x01,0x03,0x00,0x18,0xa8,0x01,0x01,
+  0x09,0x00,0x18,0xb0,0x00,0x03,0x00,0x18,0xac,0x01,0x01,0x09,0x00,0x18,0xc0,0x00,
  0x03,0x00,0x18,0xb0,0x00,0x01,0x09,0x00,0x18,0xc4,0x00,0x03,0x00,0x18,0xc0,0x00,
  0x01,0x09,0x00,0x18,0xc8,0x00,0x03,0x00,0x18,0xc4,0x00,0x01,0x09,0x00,0x18,0xcc,
  0x00,0x03,0x00,0x18,0xc8,0x00,0x01,0x09,0x00,0x18,0xd0,0x00,0x03,0x00,0x18,0xcc,
@@ -1894,15 +1894,15 @@
  0x0c,0x00,0x01,0x09,0x00,0x1a,0x20,0x00,0x13,0x00,0x1a,0x10,0x00,0x01,0x09,0x00,
  0x1a,0x24,0x00,0x13,0x00,0x1a,0x20,0x00,0x11,0x09,0x00,0x1a,0x28,0x00,0x13,0x00,
  0x1a,0x24,0x00,0x11,0x09,0x00,0x1a,0x2c,0x00,0x13,0x00,0x1a,0x28,0x00,0x11,0x09,
-  0x00,0x1a,0x30,0x00,0x03,0x00,0x1a,0x2c,0x00,0x11,0x09,0x00,0x1a,0x40,0x00,0x13,
-  0x00,0x1a,0x30,0x00,0x01,0x09,0x00,0x1a,0x44,0x00,0x13,0x00,0x1a,0x40,0x00,0x11,
+  0x00,0x1a,0x30,0x00,0x13,0x00,0x1a,0x2c,0x00,0x11,0x09,0x00,0x1a,0x40,0x00,0x13,
+  0x00,0x1a,0x30,0x00,0x11,0x09,0x00,0x1a,0x44,0x00,0x13,0x00,0x1a,0x40,0x00,0x11,
  0x09,0x00,0x1a,0x48,0x00,0x13,0x00,0x1a,0x44,0x00,0x11,0x09,0x00,0x1a,0x4c,0x00,
-  0x13,0x00,0x1a,0x48,0x00,0x11,0x09,0x00,0x1a,0x50,0x00,0x03,0x00,0x1a,0x4c,0x00,
-  0x11,0x09,0x00,0x1a,0x82,0x81,0x03,0x00,0x1a,0x50,0x00,0x01,0x09,0x00,0x1a,0x84,
+  0x13,0x00,0x1a,0x48,0x00,0x11,0x09,0x00,0x1a,0x50,0x00,0x13,0x00,0x1a,0x4c,0x00,
+  0x11,0x09,0x00,0x1a,0x82,0x81,0x03,0x00,0x1a,0x50,0x00,0x11,0x09,0x00,0x1a,0x84,
  0x80,0x03,0x00,0x1a,0x82,0x81,0x01,0x09,0x00,0x1a,0x88,0x80,0x03,0x00,0x1a,0x84,
  0x80,0x01,0x09,0x00,0x1a,0x8c,0x80,0x03,0x00,0x1a,0x88,0x80,0x01,0x09,0x00,0x1a,
-  0x90,0x00,0x03,0x00,0x1a,0x8c,0x80,0x01,0x09,0x00,0x1a,0xa0,0x00,0x03,0x00,0x1a,
-  0x90,0x00,0x01,0x09,0x00,0x1a,0xa4,0x00,0x03,0x00,0x1a,0xa0,0x00,0x01,0x09,0x00,
+  0x90,0x80,0x03,0x00,0x1a,0x8c,0x80,0x01,0x09,0x00,0x1a,0xa0,0x00,0x03,0x00,0x1a,
+  0x90,0x80,0x01,0x09,0x00,0x1a,0xa4,0x00,0x03,0x00,0x1a,0xa0,0x00,0x01,0x09,0x00,
  0x1a,0xa8,0x00,0x03,0x00,0x1a,0xa4,0x00,0x01,0x09,0x00,0x1a,0xac,0x00,0x03,0x00,
  0x1a,0xa8,0x00,0x01,0x09,0x00,0x1a,0xb0,0x00,0x03,0x00,0x1a,0xac,0x00,0x01,0x09,
  0x00,0x1a,0xc0,0x00,0x03,0x00,0x1a,0xb0,0x00,0x01,0x09,0x00,0x1a,0xc4,0x00,0x03,
@@ -2183,41 +2183,41 @@
  0x00,0x28,0x20,0x00,0x13,0x00,0x28,0x10,0x00,0x01,0x09,0x00,0x28,0x24,0x00,0x13,
  0x00,0x28,0x20,0x00,0x11,0x09,0x00,0x28,0x28,0x00,0x13,0x00,0x28,0x24,0x00,0x11,
  0x09,0x00,0x28,0x2c,0x00,0x13,0x00,0x28,0x28,0x00,0x11,0x09,0x00,0x28,0x30,0x00,
-  0x03,0x00,0x28,0x2c,0x00,0x11,0x09,0x00,0x28,0x40,0x00,0x03,0x00,0x28,0x30,0x00,
-  0x01,0x09,0x00,0x28,0x44,0x00,0x03,0x00,0x28,0x40,0x00,0x01,0x09,0x00,0x28,0x48,
+  0x13,0x00,0x28,0x2c,0x00,0x11,0x09,0x00,0x28,0x40,0x00,0x03,0x00,0x28,0x30,0x00,
+  0x11,0x09,0x00,0x28,0x44,0x00,0x03,0x00,0x28,0x40,0x00,0x01,0x09,0x00,0x28,0x48,
  0x00,0x03,0x00,0x28,0x44,0x00,0x01,0x09,0x00,0x28,0x4c,0x00,0x03,0x00,0x28,0x48,
  0x00,0x01,0x09,0x00,0x28,0x50,0x00,0x03,0x00,0x28,0x4c,0x00,0x01,0x09,0x00,0x28,
  0x80,0x80,0x03,0x00,0x28,0x50,0x00,0x01,0x09,0x00,0x28,0x84,0x80,0x03,0x00,0x28,
  0x80,0x80,0x01,0x09,0x00,0x28,0x88,0x80,0x03,0x00,0x28,0x84,0x80,0x01,0x09,0x00,
-  0x28,0x8c,0x80,0x03,0x00,0x28,0x88,0x80,0x01,0x09,0x00,0x28,0x90,0x00,0x03,0x00,
-  0x28,0x8c,0x80,0x01,0x09,0x00,0x28,0xa0,0x00,0x03,0x00,0x28,0x90,0x00,0x01,0x09,
+  0x28,0x8c,0x80,0x03,0x00,0x28,0x88,0x80,0x01,0x09,0x00,0x28,0x90,0x80,0x03,0x00,
+  0x28,0x8c,0x80,0x01,0x09,0x00,0x28,0xa0,0x00,0x03,0x00,0x28,0x90,0x80,0x01,0x09,
  0x00,0x28,0xa4,0x00,0x03,0x00,0x28,0xa0,0x00,0x01,0x09,0x00,0x28,0xa8,0x00,0x03,
  0x00,0x28,0xa4,0x00,0x01,0x09,0x00,0x28,0xac,0x00,0x03,0x00,0x28,0xa8,0x00,0x01,
  0x09,0x00,0x28,0xb0,0x00,0x03,0x00,0x28,0xac,0x00,0x01,0x09,0x00,0x28,0xc0,0x00,
  0x13,0x00,0x28,0xb0,0x00,0x01,0x09,0x00,0x28,0xc4,0x00,0x13,0x00,0x28,0xc0,0x00,
  0x11,0x09,0x00,0x28,0xc8,0x00,0x13,0x00,0x28,0xc4,0x00,0x11,0x09,0x00,0x28,0xcc,
-  0x00,0x13,0x00,0x28,0xc8,0x00,0x11,0x09,0x00,0x28,0xd0,0x00,0x03,0x00,0x28,0xcc,
-  0x00,0x11,0x09,0x00,0x29,0x00,0x80,0x33,0x00,0x28,0xd0,0x00,0x01,0x09,0x00,0x29,
-  0x04,0x84,0x33,0x00,0x29,0x00,0x80,0x31,0x09,0x00,0x29,0x08,0xc0,0x03,0x00,0x29,
-  0x04,0x84,0x31,0x09,0x00,0x29,0x0c,0x00,0x03,0x00,0x29,0x08,0xc0,0x01,0x09,0x00,
-  0x29,0x10,0x00,0x03,0x00,0x29,0x0c,0x00,0x01,0x09,0x00,0x29,0x20,0x04,0x13,0x00,
-  0x29,0x10,0x00,0x01,0x09,0x00,0x29,0x24,0x00,0x13,0x00,0x29,0x20,0x04,0x11,0x09,
-  0x00,0x29,0x28,0x00,0x13,0x00,0x29,0x24,0x00,0x11,0x09,0x00,0x29,0x2c,0x00,0x03,
-  0x00,0x29,0x28,0x00,0x11,0x09,0x00,0x29,0x30,0x00,0x03,0x00,0x29,0x2c,0x00,0x01,
-  0x09,0x00,0x29,0x40,0xe8,0x1b,0x00,0x29,0x30,0x00,0x01,0x09,0x00,0x29,0x44,0xe8,
-  0x1b,0x00,0x29,0x40,0xe8,0x19,0x09,0x00,0x29,0x48,0xc0,0x13,0x00,0x29,0x44,0xe8,
-  0x19,0x09,0x00,0x29,0x4c,0x00,0x03,0x00,0x29,0x48,0xc0,0x11,0x09,0x00,0x29,0x50,
-  0x80,0x03,0x00,0x29,0x4c,0x00,0x01,0x09,0x00,0x29,0x80,0x00,0x03,0x00,0x29,0x50,
-  0x80,0x01,0x09,0x00,0x29,0x84,0x40,0x03,0x00,0x29,0x80,0x00,0x01,0x09,0x00,0x29,
-  0x88,0x00,0x33,0x00,0x29,0x84,0x40,0x01,0x09,0x00,0x29,0x8c,0x80,0x03,0x00,0x29,
-  0x88,0x00,0x31,0x09,0x00,0x29,0x90,0x00,0x03,0x00,0x29,0x8c,0x80,0x01,0x09,0x00,
-  0x29,0xa0,0x00,0x03,0x00,0x29,0x90,0x00,0x01,0x09,0x00,0x29,0xa4,0x04,0x03,0x00,
-  0x29,0xa0,0x00,0x01,0x09,0x00,0x29,0xa8,0x00,0x03,0x00,0x29,0xa4,0x04,0x01,0x09,
-  0x00,0x29,0xac,0x00,0x13,0x00,0x29,0xa8,0x00,0x01,0x09,0x00,0x29,0xb0,0x00,0x03,
-  0x00,0x29,0xac,0x00,0x11,0x09,0x00,0x29,0xc0,0x00,0x03,0x00,0x29,0xb0,0x00,0x01,
-  0x09,0x00,0x29,0xc4,0x00,0x03,0x00,0x29,0xc0,0x00,0x01,0x09,0x00,0x29,0xc8,0x00,
-  0x0b,0x00,0x29,0xc4,0x00,0x01,0x09,0x00,0x29,0xcc,0x80,0x13,0x00,0x29,0xc8,0x00,
-  0x09,0x09,0x00,0x29,0xd0,0x00,0x03,0x00,0x29,0xcc,0x80,0x11,0x09,0x00,0x2a,0x00,
+  0x00,0x13,0x00,0x28,0xc8,0x00,0x11,0x09,0x00,0x28,0xd0,0x00,0x13,0x00,0x28,0xcc,
+  0x00,0x11,0x09,0x00,0x29,0x00,0x00,0x03,0x00,0x28,0xd0,0x00,0x11,0x09,0x00,0x29,
+  0x04,0x00,0x03,0x00,0x29,0x00,0x00,0x01,0x09,0x00,0x29,0x08,0x00,0x03,0x00,0x29,
+  0x04,0x00,0x01,0x09,0x00,0x29,0x0c,0x00,0x03,0x00,0x29,0x08,0x00,0x01,0x09,0x00,
+  0x29,0x10,0x00,0x03,0x00,0x29,0x0c,0x00,0x01,0x09,0x00,0x29,0x20,0x00,0x03,0x00,
+  0x29,0x10,0x00,0x01,0x09,0x00,0x29,0x24,0x00,0x03,0x00,0x29,0x20,0x00,0x01,0x09,
+  0x00,0x29,0x28,0x00,0x03,0x00,0x29,0x24,0x00,0x01,0x09,0x00,0x29,0x2c,0x00,0x03,
+  0x00,0x29,0x28,0x00,0x01,0x09,0x00,0x29,0x30,0x00,0x03,0x00,0x29,0x2c,0x00,0x01,
+  0x09,0x00,0x29,0x40,0x00,0x03,0x00,0x29,0x30,0x00,0x01,0x09,0x00,0x29,0x44,0x00,
+  0x03,0x00,0x29,0x40,0x00,0x01,0x09,0x00,0x29,0x48,0x00,0x03,0x00,0x29,0x44,0x00,
+  0x01,0x09,0x00,0x29,0x4c,0x00,0x03,0x00,0x29,0x48,0x00,0x01,0x09,0x00,0x29,0x50,
+  0x00,0x03,0x00,0x29,0x4c,0x00,0x01,0x09,0x00,0x29,0x80,0x00,0x03,0x00,0x29,0x50,
+  0x00,0x01,0x09,0x00,0x29,0x84,0x00,0xc3,0x00,0x29,0x80,0x00,0x01,0x09,0x00,0x29,
+  0x88,0x00,0x03,0x00,0x29,0x84,0x00,0xc1,0x09,0x00,0x29,0x8c,0x00,0x03,0x00,0x29,
+  0x88,0x00,0x01,0x09,0x00,0x29,0x90,0x00,0x03,0x00,0x29,0x8c,0x00,0x01,0x09,0x00,
+  0x29,0xa0,0x00,0x03,0x00,0x29,0x90,0x00,0x01,0x09,0x00,0x29,0xa4,0x80,0xe3,0x00,
+  0x29,0xa0,0x00,0x01,0x09,0x00,0x29,0xa8,0x00,0x03,0x00,0x29,0xa4,0x80,0xe1,0x09,
+  0x00,0x29,0xac,0x00,0x03,0x00,0x29,0xa8,0x00,0x01,0x09,0x00,0x29,0xb0,0x00,0x03,
+  0x00,0x29,0xac,0x00,0x01,0x09,0x00,0x29,0xc0,0x00,0x03,0x00,0x29,0xb0,0x00,0x01,
+  0x09,0x00,0x29,0xc4,0x00,0x63,0x00,0x29,0xc0,0x00,0x01,0x09,0x00,0x29,0xc8,0x00,
+  0x03,0x00,0x29,0xc4,0x00,0x61,0x09,0x00,0x29,0xcc,0x00,0x03,0x00,0x29,0xc8,0x00,
+  0x01,0x09,0x00,0x29,0xd0,0x00,0x03,0x00,0x29,0xcc,0x00,0x01,0x09,0x00,0x2a,0x00,
  0x00,0x03,0x00,0x29,0xd0,0x00,0x01,0x09,0x00,0x2a,0x04,0x00,0x03,0x00,0x2a,0x00,
  0x00,0x01,0x09,0x00,0x2a,0x08,0x00,0x03,0x00,0x2a,0x04,0x00,0x01,0x09,0x00,0x2a,
  0x0c,0x00,0x03,0x00,0x2a,0x08,0x00,0x01,0x09,0x00,0x2a,0x10,0x00,0x03,0x00,0x2a,
--- a/board/evb64260/pci.c
+++ b/board/evb64260/pci.c
@@ -629,6 +629,7 @@ static void gt_setup_ide (struct pci_controller *hose,
 	}
 }

+#ifndef CONFIG_P3G4
 static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
 {
 	unsigned char pin, irq;
@@ -642,6 +643,7 @@ static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
 			pci_write_config_byte (dev, PCI_INTERRUPT_LINE, irq);
 	}
 }
+#endif

 struct pci_config_table gt_config_table[] = {
 	{PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE,
@@ -651,12 +653,16 @@ struct pci_config_table gt_config_table[] = {
 };

 struct pci_controller pci0_hose = {
+#ifndef CONFIG_P3G4
 	fixup_irq:gt_fixup_irq,
+#endif
 	config_table:gt_config_table,
 };

 struct pci_controller pci1_hose = {
+#ifndef CONFIG_P3G4
 	fixup_irq:gt_fixup_irq,
+#endif
 	config_table:gt_config_table,
 };

@@ -692,8 +698,10 @@ void pci_init_board (void)

 	pci_register_hose (&pci0_hose);

+#ifndef CONFIG_P3G4
 	pciArbiterEnable (PCI_HOST0);
 	pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1);
+#endif

 	command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
 	command |= PCI_COMMAND_MASTER;
@@ -735,8 +743,10 @@ void pci_init_board (void)

 	pci_register_hose (&pci1_hose);

+#ifndef CONFIG_P3G4
 	pciArbiterEnable (PCI_HOST1);
 	pciParkingDisable (PCI_HOST1, 1, 1, 1, 1, 1, 1, 1);
+#endif

 	command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
 	command |= PCI_COMMAND_MASTER;
--- a/board/icecube/icecube.c
+++ b/board/icecube/icecube.c
@@ -133,10 +133,13 @@ long int initdram (int board_type)
 	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */

 	/* find RAM size using SDRAM CS1 only */
-	sdram_start(0);
-	test1 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
-	sdram_start(1);
-	test2 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+	if (!dramsize)
+		sdram_start(0);
+	test2 = test1 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+	if (!dramsize) {
+		sdram_start(1);
+		test2 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+	}
 	if (test1 > test2) {
 		sdram_start(0);
 		dramsize2 = test1;
--- a/board/ids8247/Makefile
+++ b/board/ids8247/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2005
+# Heiko Schocher, DENX Software Engineering, <hs@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
--- a/cpu/at91rm9200/config.mk
+++ b/cpu/at91rm9200/config.mk
@@ -1,7 +1,6 @@
 #
-# (C) Copyright 2002
-# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
-# Marius Groeger <mgroeger@sysgo.de>
+# (C) Copyright 2005
+# Heiko Schocher, DENX Software Engineering, <hs@denx.de>
 #
 # See file CREDITS for list of people who contributed to this
 # project.
@@ -21,7 +20,15 @@
 # Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 # MA 02111-1307 USA
 #
-PLATFORM_RELFLAGS += -fno-strict-aliasing  -fno-common -ffixed-r8 \
-	-mshort-load-bytes -msoft-float

-PLATFORM_CPPFLAGS += -mapcs-32 -march=armv4 -mtune=arm7tdmi
+#
+# IDS 8247 Board
+#
+
+# This should be equal to the CFG_FLASH_BASE define in config_IDS8247.h
+# for the "final" configuration, with U-Boot in flash, or the address
+# in RAM where U-Boot is loaded at for debugging.
+#
+TEXT_BASE = 0xfff00000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)
--- a/board/ids8247/flash.c
+++ b/board/ids8247/flash.c
@@ -0,0 +1,484 @@
+/*
+ * (C) Copyright 2005
+ * Heiko Schocher, DENX Software Engineering, <hs@denx.de>
+ *
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#undef DEBUG
+
+#include <common.h>
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+# ifndef  CFG_ENV_ADDR
+#  define CFG_ENV_ADDR	(CFG_FLASH_BASE + CFG_ENV_OFFSET)
+# endif
+# ifndef  CFG_ENV_SIZE
+#  define CFG_ENV_SIZE	CFG_ENV_SECT_SIZE
+# endif
+# ifndef  CFG_ENV_SECT_SIZE
+#  define CFG_ENV_SECT_SIZE  CFG_ENV_SIZE
+# endif
+#endif
+
+/*-----------------------------------------------------------------------
+ * Protection Flags:
+ */
+#define FLAG_PROTECT_SET	0x01
+#define FLAG_PROTECT_CLEAR	0x02
+
+/* Board support for 1 or 2 flash devices */
+#undef FLASH_PORT_WIDTH32
+#undef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH8
+
+#ifdef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH	ushort
+#define FLASH_PORT_WIDTHV	vu_short
+#elif FLASH_PORT_WIDTH32
+#define FLASH_PORT_WIDTH	ulong
+#define FLASH_PORT_WIDTHV	vu_long
+#else /* FLASH_PORT_WIDTH8 */
+#define FLASH_PORT_WIDTH	uchar
+#define FLASH_PORT_WIDTHV	vu_char
+#endif
+
+#define FPW			FLASH_PORT_WIDTH
+#define FPWV			FLASH_PORT_WIDTHV
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (FPWV * addr, flash_info_t * info);
+static int write_data (flash_info_t * info, ulong dest, FPW data);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0;
+	int i;
+	volatile immap_t * immr = (immap_t *)CFG_IMMR;
+	volatile memctl8260_t *memctl = &immr->im_memctl;
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+	size_b0 = flash_get_size ((FPW *) CFG_FLASH0_BASE, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0 << 20);
+	}
+
+	memctl->memc_or0 = 0xff800060;
+	memctl->memc_br0 = 0xff800801;
+
+	flash_get_offsets (0xff800000, &flash_info[0]);
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	/* monitor protection ON by default */
+	(void) flash_protect (FLAG_PROTECT_SET,
+				CFG_MONITOR_BASE,
+				CFG_MONITOR_BASE + monitor_flash_len - 1,
+				&flash_info[0]);
+#endif
+
+#ifdef	CFG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect (FLAG_PROTECT_SET,
+			CFG_ENV_ADDR,
+			CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+			&flash_info[0]);
+#endif
+
+	flash_info[0].size = size_b0;
+
+	return (size_b0);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00020000);
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F320J3A:
+		printf ("28F320J3A\n");
+		break;
+	case FLASH_28F640J3A:
+		printf ("28F640J3A\n");
+		break;
+	case FLASH_28F128J3A:
+		printf ("28F128J3A\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (FPWV * addr, flash_info_t * info)
+{
+	FPW value;
+
+	addr[0] = (FPW) 0x00900090;
+
+	value = addr[0];
+
+	debug ("Manuf. ID @ 0x%08lx: 0x%08lx\n", (ulong)addr, value);
+
+	switch (value) {
+	case (FPW) INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+		return (0);			/* no or unknown flash  */
+	}
+
+#ifdef FLASH_PORT_WIDTH8
+	value = addr[2];			/* device ID        */
+#else
+	value = addr[1];			/* device ID        */
+#endif
+
+	debug ("Device ID @ 0x%08lx: 0x%08lx\n", (ulong)(&addr[1]), value);
+
+	switch (value) {
+	case (FPW) INTEL_ID_28F320J3A:
+		info->flash_id += FLASH_28F320J3A;
+		info->sector_count = 32;
+		info->size = 0x00400000;
+		break;				/* => 4 MB     */
+
+	case (FPW) INTEL_ID_28F640J3A:
+		info->flash_id += FLASH_28F640J3A;
+		info->sector_count = 64;
+		info->size = 0x00800000;
+		break;				/* => 8 MB     */
+
+	case (FPW) INTEL_ID_28F128J3A:
+		info->flash_id += FLASH_28F128J3A;
+		info->sector_count = 128;
+		info->size = 0x01000000;
+		break;				/* => 16 MB     */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+				info->sector_count, CFG_MAX_FLASH_SECT);
+		info->sector_count = CFG_MAX_FLASH_SECT;
+	}
+
+	addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong type, start, now, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	start = get_timer (0);
+	last = start;
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			FPWV *addr = (FPWV *) (info->start[sect]);
+			FPW status;
+
+			/* Disable interrupts which might cause a timeout here */
+			flag = disable_interrupts ();
+
+			*addr = (FPW) 0x00500050;	/* clear status register */
+			*addr = (FPW) 0x00200020;	/* erase setup */
+			*addr = (FPW) 0x00D000D0;	/* erase confirm */
+
+			/* re-enable interrupts if necessary */
+			if (flag)
+				enable_interrupts ();
+
+			/* wait at least 80us - let's wait 1 ms */
+			udelay (1000);
+
+			while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+			    if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
+				printf ("Timeout\n");
+				*addr = (FPW) 0x00B000B0;	/* suspend erase     */
+				*addr = (FPW) 0x00FF00FF;	/* reset to read mode */
+				rcode = 1;
+				break;
+			    }
+
+			    /* show that we're waiting */
+			    if ((now - last) > 1000) {	/* every second */
+				putc ('.');
+				last = now;
+			    }
+			}
+
+			*addr = (FPW) 0x00FF00FF;	/* reset to read mode */
+		}
+	}
+	printf (" done\n");
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	FPW data;
+
+	int i, l, rc, port_width;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+/* get lower word aligned address */
+#ifdef FLASH_PORT_WIDTH16
+	wp = (addr & ~1);
+	port_width = 2;
+#elif defined(FLASH_PORT_WIDTH32)
+	wp = (addr & ~3);
+	port_width = 4;
+#else
+	wp = addr;
+	port_width = 1;
+#endif
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < port_width && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < port_width; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_data (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= port_width) {
+		data = 0;
+		for (i = 0; i < port_width; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+		cnt -= port_width;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < port_width; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_data (info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t * info, ulong dest, FPW data)
+{
+	FPWV *addr = (FPWV *) dest;
+	ulong status;
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr);
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	*addr = (FPW) 0x00400040;	/* write setup */
+	*addr = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+
+	start = get_timer (0);
+
+	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+		if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+			return (1);
+		}
+	}
+
+	*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (0);
+}
--- a/board/ids8247/ids8247.c
+++ b/board/ids8247/ids8247.c
@@ -0,0 +1,318 @@
+/*
+ * (C) Copyright 2005
+ * Heiko Schocher, DENX Software Engineering, <hs@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc8260.h>
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A configuration */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PA31 */ {   0,   1,	 1,   0,   0,	0   }, /* FCC1 COL */
+	/* PA30 */ {   0,   1,	 1,   0,   0,	0   }, /* FCC1 CRS */
+	/* PA29 */ {   0,   1,	 1,   1,   0,	0   }, /* FCC1 TXER */
+	/* PA28 */ {   0,   1,	 1,   1,   0,	0   }, /* FCC1 TXEN */
+	/* PA27 */ {   0,   1,	 1,   0,   0,	0   }, /* FCC1 RXDV */
+	/* PA26 */ {   0,   1,	 1,   0,   0,	0   }, /* FCC1 RXER */
+	/* PA25 */ {   0,   0,	 0,   0,   1,	0   }, /* 8247_P0 */
+#if defined(CONFIG_SOFT_I2C)
+	/* PA24 */ {   1,   0,	 0,   0,   1,	1   }, /* I2C_SDA2 */
+	/* PA23 */ {   1,   0,	 0,   1,   1,	1   }, /* I2C_SCL2 */
+#else /* normal I/O port pins */
+	/* PA24 */ {   0,   0,	 0,   1,   0,	0   }, /* PA24 */
+	/* PA23 */ {   0,   0,	 0,   1,   0,	0   }, /* PA23 */
+#endif
+	/* PA22 */ {   0,   0,	 0,   0,   1,	0   }, /* SMC2_DCD */
+	/* PA21 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC1 TXD3 */
+	/* PA20 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC1 TXD2 */
+	/* PA19 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC1 TXD1 */
+	/* PA18 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC1 TXD0 */
+	/* PA17 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC1 RXD0 */
+	/* PA16 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC1 RXD1 */
+	/* PA15 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC1 RXD2 */
+	/* PA14 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC1 RXD3 */
+	/* PA13 */ {   0,   0,	 0,   1,   1,	0   }, /* SMC2_RTS */
+	/* PA12 */ {   0,   0,	 0,   0,   1,	0   }, /* SMC2_CTS */
+	/* PA11 */ {   0,   0,	 0,   1,   1,	0   }, /* SMC2_DTR */
+	/* PA10 */ {   0,   0,	 0,   0,   1,	0   }, /* SMC2_DSR */
+	/* PA9	*/ {   0,   1,	 0,   1,   0,	0   }, /* SMC2 TXD */
+	/* PA8	*/ {   0,   1,	 0,   0,   0,	0   }, /* SMC2 RXD */
+	/* PA7	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA7 */
+	/* PA6	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA6 */
+	/* PA5	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA5 */
+	/* PA4	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA4 */
+	/* PA3	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA3 */
+	/* PA2	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA2 */
+	/* PA1	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA1 */
+	/* PA0	*/ {   0,   0,	 0,   1,   0,	0   }  /* PA0 */
+    },
+
+    /* Port B configuration */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PB31 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC2 MII TX_ER */
+	/* PB30 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RX_DV */
+	/* PB29 */ {   1,   1,	 1,   1,   0,	0   }, /* FCC2 MII TX_EN */
+	/* PB28 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RX_ER */
+	/* PB27 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII COL */
+	/* PB26 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII CRS */
+	/* PB25 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC2 MII TxD[3] */
+	/* PB24 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC2 MII TxD[2] */
+	/* PB23 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC2 MII TxD[1] */
+	/* PB22 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC2 MII TxD[0] */
+	/* PB21 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RxD[0] */
+	/* PB20 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RxD[1] */
+	/* PB19 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RxD[2] */
+	/* PB18 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RxD[3] */
+	/* PB17 */ {   0,   0,	 0,   0,   0,	0   }, /* PB17 */
+	/* PB16 */ {   0,   0,	 0,   0,   0,	0   }, /* PB16 */
+	/* PB15 */ {   0,   0,	 0,   0,   0,	0   }, /* PB15 */
+	/* PB14 */ {   0,   0,	 0,   0,   0,	0   }, /* PB14 */
+	/* PB13 */ {   0,   0,	 0,   0,   0,	0   }, /* PB13 */
+	/* PB12 */ {   0,   0,	 0,   0,   0,	0   }, /* PB12 */
+	/* PB11 */ {   0,   0,	 0,   0,   0,	0   }, /* PB11 */
+	/* PB10 */ {   0,   0,	 0,   0,   0,	0   }, /* PB10 */
+	/* PB9	*/ {   0,   0,	 0,   0,   0,	0   }, /* PB9 */
+	/* PB8	*/ {   0,   0,	 0,   0,   0,	0   }, /* PB8 */
+	/* PB7	*/ {   0,   0,	 0,   0,   0,	0   }, /* PB7 */
+	/* PB6	*/ {   0,   0,	 0,   0,   0,	0   }, /* PB6 */
+	/* PB5	*/ {   0,   0,	 0,   0,   0,	0   }, /* PB5 */
+	/* PB4	*/ {   0,   0,	 0,   0,   0,	0   }, /* PB4 */
+	/* PB3	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
+	/* PB2	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
+	/* PB1	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
+	/* PB0	*/ {   0,   0,	 0,   0,   0,	0   }  /* pin doesn't exist */
+    },
+
+    /* Port C */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PC31 */ {   0,   0,	 0,   1,   0,	0   }, /* PC31 */
+	/* PC30 */ {   0,   0,	 0,   1,   0,	0   }, /* PC30 */
+	/* PC29 */ {   0,   1,	 0,   0,   0,	0   }, /* SCC1 EN *CLSN */
+	/* PC28 */ {   0,   1,	 1,   0,   0,	0   }, /* SYNC_OUT */
+	/* PC27 */ {   0,   0,	 0,   1,   0,	0   }, /* PC27 */
+	/* PC26 */ {   0,   0,	 0,   1,   0,	0   }, /* PC26 */
+	/* PC25 */ {   0,   1,	 1,   0,   0,	0   }, /* SYNC_IN */
+	/* PC24 */ {   0,   0,	 0,   1,   0,	0   }, /* PC24 */
+	/* PC23 */ {   0,   1,	 0,   1,   0,	0   }, /* ATMTFCLK */
+	/* PC22 */ {   0,   1,	 0,   0,   0,	0   }, /* ATMRFCLK */
+	/* PC21 */ {   0,   1,	 0,   0,   0,	0   }, /* SCC1 EN RXCLK */
+	/* PC20 */ {   0,   1,	 0,   0,   0,	0   }, /* SCC1 EN TXCLK */
+	/* PC19 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RX_CLK */
+	/* PC18 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII TX_CLK */
+	/* PC17 */ {   0,   0,	 0,   1,   0,	0   }, /* PC17 */
+	/* PC16 */ {   0,   0,	 0,   1,   0,	0   }, /* PC16 */
+	/* PC15 */ {   0,   0,	 0,   1,   0,	0   }, /* PC15 */
+	/* PC14 */ {   0,   1,	 0,   0,   0,	0   }, /* SCC1 EN *CD */
+	/* PC13 */ {   0,   0,	 0,   1,   0,	0   }, /* PC13 */
+	/* PC12 */ {   0,   0,	 0,   1,   0,	0   }, /* PC12 */
+	/* PC11 */ {   0,   0,	 0,   1,   0,	0   }, /* PC11 */
+	/* PC10 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC2 MDC */
+	/* PC9	*/ {   0,   0,	 0,   1,   0,	0   }, /* FCC2 MDIO */
+	/* PC8	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC8 */
+	/* PC7	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC7 */
+	/* PC6	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC6 */
+	/* PC5	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC5 */
+	/* PC4	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC4 */
+	/* PC3	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC3 */
+	/* PC2	*/ {   0,   0,	 0,   1,   0,	1   }, /* ENET FDE */
+	/* PC1	*/ {   0,   0,	 0,   1,   0,	0   }, /* ENET DSQE */
+	/* PC0	*/ {   0,   0,	 0,   1,   0,	0   }, /* ENET LBK */
+    },
+
+    /* Port D */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PD31 */ {   0,   1,	 0,   0,   0,	0   }, /* SCC1 EN RxD */
+	/* PD30 */ {   0,   1,	 1,   1,   0,	0   }, /* SCC1 EN TxD */
+	/* PD29 */ {   0,   1,	 0,   1,   0,	0   }, /* SCC1 EN TENA */
+	/* PD28 */ {   0,   0,	 0,   1,   0,	0   }, /* PD28 */
+	/* PD27 */ {   0,   0,	 0,   1,   0,	0   }, /* PD27 */
+	/* PD26 */ {   0,   0,	 0,   1,   0,	0   }, /* PD26 */
+	/* PD25 */ {   0,   1,	 0,   0,   0,	0   }, /* SCC3_RX */
+	/* PD24 */ {   0,   1,	 0,   1,   0,	0   }, /* SCC3_TX */
+	/* PD23 */ {   0,   1,	 0,   1,   0,	0   }, /* SCC3_RTS */
+	/* PD22 */ {   0,   1,	 0,   0,   0,	0   }, /* SCC4_RXD */
+	/* PD21 */ {   0,   1,	 0,   1,   0,	0   }, /* SCC4_TXD */
+	/* PD20 */ {   0,   1,	 0,   1,   0,	0   }, /* SCC4_RTS */
+	/* PD19 */ {   0,   1,	 1,   0,   0,	0   }, /* SPI_SEL */
+	/* PD18 */ {   0,   1,	 1,   0,   0,	0   }, /* SPI_CLK */
+	/* PD17 */ {   0,   1,	 1,   0,   0,	0   }, /* SPI_MOSI */
+	/* PD16 */ {   0,   1,	 1,   0,   0,	0   }, /* SPI_MISO */
+#if defined(CONFIG_HARD_I2C)
+	/* PD15 */ {   1,   1,	 1,   0,   1,	0   }, /* I2C SDA1 */
+	/* PD14 */ {   1,   1,	 1,   0,   1,	0   }, /* I2C SCL1 */
+#else /* normal I/O port pins */
+	/* PD15 */ {   0,   1,	 1,   0,   1,	0   }, /* PD15 */
+	/* PD14 */ {   0,   1,	 1,   0,   1,	0   }, /* PD14 */
+#endif
+	/* PD13 */ {   0,   0,	 0,   0,   0,	0   }, /* PD13 */
+	/* PD12 */ {   0,   0,	 0,   0,   0,	0   }, /* PD12 */
+	/* PD11 */ {   0,   0,	 0,   0,   0,	0   }, /* PD11 */
+	/* PD10 */ {   0,   0,	 0,   0,   0,	0   }, /* PD10 */
+	/* PD9	*/ {   0,   0,	 0,   0,   0,	0   }, /* PD9 */
+	/* PD8	*/ {   0,   0,	 0,   0,   0,	0   }, /* PD8 */
+	/* PD7	*/ {   0,   0,	 0,   1,   0,	1   }, /* MII_MDIO */
+	/* PD6	*/ {   0,   0,	 0,   1,   0,	1   }, /* PD6 */
+	/* PD5	*/ {   0,   0,	 0,   1,   0,	1   }, /* PD5 */
+	/* PD4	*/ {   0,   0,	 0,   1,   0,	1   }, /* PD4 */
+	/* PD3	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
+	/* PD2	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
+	/* PD1	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
+	/* PD0	*/ {   0,   0,	 0,   0,   0,	0   }  /* pin doesn't exist */
+    }
+};
+
+/* ------------------------------------------------------------------------- */
+
+/* Check Board Identity:
+ */
+int checkboard (void)
+{
+	puts ("Board: IDS 8247\n");
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
+ *
+ * This routine performs standard 8260 initialization sequence
+ * and calculates the available memory size. It may be called
+ * several times to try different SDRAM configurations on both
+ * 60x and local buses.
+ */
+static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
+						  ulong orx, volatile uchar * base)
+{
+	volatile uchar c = 0xff;
+	volatile uint *sdmr_ptr;
+	volatile uint *orx_ptr;
+	ulong maxsize, size;
+	int i;
+
+	/* We must be able to test a location outsize the maximum legal size
+	 * to find out THAT we are outside; but this address still has to be
+	 * mapped by the controller. That means, that the initial mapping has
+	 * to be (at least) twice as large as the maximum expected size.
+	 */
+	maxsize = (1 + (~orx | 0x7fff)) / 2;
+
+	sdmr_ptr = &memctl->memc_psdmr;
+	orx_ptr = &memctl->memc_or2;
+
+	*orx_ptr = orx;
+
+	/*
+	 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
+	 *
+	 * "At system reset, initialization software must set up the
+	 *  programmable parameters in the memory controller banks registers
+	 *  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
+	 *  system software should execute the following initialization sequence
+	 *  for each SDRAM device.
+	 *
+	 *  1. Issue a PRECHARGE-ALL-BANKS command
+	 *  2. Issue eight CBR REFRESH commands
+	 *  3. Issue a MODE-SET command to initialize the mode register
+	 *
+	 *  The initial commands are executed by setting P/LSDMR[OP] and
+	 *  accessing the SDRAM with a single-byte transaction."
+	 *
+	 * The appropriate BRx/ORx registers have already been set when we
+	 * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
+	 */
+
+	*sdmr_ptr = sdmr | PSDMR_OP_PREA;
+	*base = c;
+
+	*sdmr_ptr = sdmr | PSDMR_OP_CBRR;
+	for (i = 0; i < 8; i++)
+		*base = c;
+
+	*sdmr_ptr = sdmr | PSDMR_OP_MRW;
+	*(base + CFG_MRS_OFFS) = c;	/* setting MR on address lines */
+
+	*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
+	*base = c;
+
+	size = get_ram_size((long *)base, maxsize);
+	*orx_ptr = orx | ~(size - 1);
+
+	return (size);
+}
+
+long int initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8260_t *memctl = &immap->im_memctl;
+
+	long psize, lsize;
+
+	psize = 16 * 1024 * 1024;
+	lsize = 0;
+
+	memctl->memc_psrt = CFG_PSRT;
+	memctl->memc_mptpr = CFG_MPTPR;
+
+#ifndef CFG_RAMBOOT
+	/* 60x SDRAM setup:
+	 */
+	psize = try_init (memctl, CFG_PSDMR, CFG_OR2,
+						  (uchar *) CFG_SDRAM_BASE);
+#endif /* CFG_RAMBOOT */
+
+	icache_enable ();
+
+	return (psize);
+}
+
+int misc_init_r (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_flashstart = 0xff800000;
+}
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+extern ulong
+nand_probe (ulong physadr);
+
+void
+nand_init (void)
+{
+	ulong totlen = 0;
+
+	debug ("Probing at 0x%.8x\n", CFG_NAND0_BASE);
+	totlen += nand_probe (CFG_NAND0_BASE);
+
+	printf ("%4lu MB\n", totlen >>20);
+}
+
+#endif	/* CFG_CMD_NAND */
--- a/board/ids8247/u-boot.lds
+++ b/board/ids8247/u-boot.lds
@@ -0,0 +1,123 @@
+/*
+ * (C) Copyright 2001
+ * Heiko Schocher, DENX Software Engineering, <hs@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc8260/start.o	(.text)
+    *(.text)
+    common/environment.o(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
--- a/board/ocotea/config.mk
+++ b/board/ocotea/config.mk
@@ -30,7 +30,7 @@
 ifeq ($(ramsym),1)
 TEXT_BASE = 0x07FD0000
 else
-TEXT_BASE = 0xFFF80000
+TEXT_BASE = 0xFFFC0000
 endif

 PLATFORM_CPPFLAGS += -DCONFIG_440=1
--- a/board/ocotea/flash.c
+++ b/board/ocotea/flash.c
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2004
+ * (C) Copyright 2004-2005
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
@@ -43,7 +43,9 @@
 #define DEBUGF(x...)
 #endif				/* DEBUG */

-#define     BOOT_SMALL_FLASH        32	/* 00100000 */
+#define     BOOT_SMALL_FLASH        0x40 /* 01000000 */
+#define     FLASH_ONBD_N            2	/* 00000010 */
+#define     FLASH_SRAM_SEL          1	/* 00000001 */
 #define     FLASH_ONBD_N            2	/* 00000010 */
 #define     FLASH_SRAM_SEL          1	/* 00000001 */

@@ -55,8 +57,8 @@
 flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips        */

 static unsigned long flash_addr_table[8][CFG_MAX_FLASH_BANKS] = {
-	{0xFF800000, 0xFF900000, 0xFFC00000},	/* 0:000: configuraton 4 */
-	{0xFF900000, 0xFF800000, 0xFFC00000},	/* 1:001: configuraton 3 */
+	{0xFF800000, 0xFF880000, 0xFFC00000},	/* 0:000: configuraton 4 */
+	{0xFF900000, 0xFF980000, 0xFFC00000},	/* 1:001: configuraton 3 */
 	{0x00000000, 0x00000000, 0x00000000},	/* 2:010: configuraton 8 */
 	{0x00000000, 0x00000000, 0x00000000},	/* 3:011: configuraton 7 */
 	{0xFFE00000, 0xFFF00000, 0xFF800000},	/* 4:100: configuraton 2 */
@@ -131,6 +133,12 @@ unsigned long flash_init(void)
 		total_b += flash_info[i].size;
 	}

+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -CFG_MONITOR_LEN,
+			    0xffffffff,
+			    &flash_info[2]);
+
 	return total_b;
 }

@@ -153,6 +161,9 @@ void flash_print_info(flash_info_t * info)
 	case FLASH_MAN_AMD:
 		printf("AMD ");
 		break;
+	case FLASH_MAN_STM:
+		printf("STM ");
+		break;
 	case FLASH_MAN_FUJ:
 		printf("FUJITSU ");
 		break;
@@ -300,6 +311,11 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info)
 		info->sector_count = 8;
 		info->size = 0x0080000;	/* => 512 ko */
 		break;
+	case (FLASH_WORD_SIZE) STM_ID_M29W040B:
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x0080000;	/* => 512 ko */
+		break;
 	case (FLASH_WORD_SIZE) AMD_ID_LV033C:
 		info->flash_id += FLASH_AMDLV033C;
 		info->sector_count = 64;
@@ -312,8 +328,8 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info)

 	/* set up sector start address table */
 	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
-	    (info->flash_id == FLASH_AM040) ||
-	    (info->flash_id == FLASH_AMD016)) {
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) ||
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) {
 		for (i = 0; i < info->sector_count; i++)
 			info->start[i] = base + (i * 0x00010000);
 	} else {
@@ -343,6 +359,15 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info)
 		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
 		/* D0 = 1 if protected */
 		addr2 = (volatile FLASH_WORD_SIZE *) (info->start[i]);
+
+		/* For AMD29033C flash we need to resend the command of	*
+		 * reading flash protection for upper 8 Mb of flash	*/
+		if ( i == 32 ) {
+			addr2[ADDR0] = (FLASH_WORD_SIZE) 0xAAAAAAAA;
+			addr2[ADDR1] = (FLASH_WORD_SIZE) 0x55555555;
+			addr2[ADDR0] = (FLASH_WORD_SIZE) 0x90909090;
+		}
+
 		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
 			info->protect[i] = 0;
 		else
@@ -432,7 +457,6 @@ int flash_erase(flash_info_t * info, int s_first, int s_last)
 	for (sect = s_first; sect <= s_last; sect++) {
 		if (info->protect[sect] == 0) {	/* not protected */
 			addr2 = (FLASH_WORD_SIZE *) (info->start[sect]);
-			printf("Erasing sector %p\n", addr2);

 			if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
 				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
--- a/board/ocotea/ocotea.c
+++ b/board/ocotea/ocotea.c
@@ -37,6 +37,15 @@ void fpga_init (void);
 int board_early_init_f (void)
 {
 	unsigned long mfr;
+	unsigned char *fpga_base = (unsigned char *) CFG_FPGA_BASE;
+	unsigned char switch_status;
+	unsigned long cs0_base;
+	unsigned long cs0_size;
+	unsigned long cs0_twt;
+	unsigned long cs2_base;
+	unsigned long cs2_size;
+	unsigned long cs2_twt;
+
 	/*-------------------------------------------------------------------------+
 	  | Initialize EBC CONFIG
 	  +-------------------------------------------------------------------------*/
@@ -47,17 +56,49 @@ int board_early_init_f (void)
 	      EBC_CFG_PME_DISABLE | EBC_CFG_PR_32);

 	/*-------------------------------------------------------------------------+
-	  | 1 MB FLASH / 1 MB SRAM. Initialize bank 0 with default values.
+	  | FPGA. Initialize bank 7 with default values.
 	  +-------------------------------------------------------------------------*/
-	mtebc(pb0ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(8)|
+	mtebc(pb7ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)|
 	      EBC_BXAP_BCE_DISABLE|
 	      EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
 	      EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
 	      EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
 	      EBC_BXAP_BEM_WRITEONLY|
 	      EBC_BXAP_PEN_DISABLED);
-	mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(0xFFE00000)|
-	      EBC_BXCR_BS_2MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
+	mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48300000)|
+	      EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
+
+	/* read FPGA base register FPGA_REG0 */
+	switch_status = *fpga_base;
+
+	if (switch_status & 0x40) {
+		cs0_base = 0xFFE00000;
+		cs0_size = EBC_BXCR_BS_2MB;
+		cs0_twt = 8;
+		cs2_base = 0xFF800000;
+		cs2_size = EBC_BXCR_BS_4MB;
+		cs2_twt = 10;
+	} else {
+		cs0_base = 0xFFC00000;
+		cs0_size = EBC_BXCR_BS_4MB;
+		cs0_twt = 10;
+		cs2_base = 0xFF800000;
+		cs2_size = EBC_BXCR_BS_2MB;
+		cs2_twt = 8;
+	}
+
+	/*-------------------------------------------------------------------------+
+	  | 1 MB FLASH / 1 MB SRAM. Initialize bank 0 with default values.
+	  +-------------------------------------------------------------------------*/
+	mtebc(pb0ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs0_twt)|
+	      EBC_BXAP_BCE_DISABLE|
+	      EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
+	      EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
+	      EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
+	      EBC_BXAP_BEM_WRITEONLY|
+	      EBC_BXAP_PEN_DISABLED);
+	mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(cs0_base)|
+	      cs0_size|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);

 	/*-------------------------------------------------------------------------+
 	  | 8KB NVRAM/RTC. Initialize bank 1 with default values.
@@ -75,15 +116,15 @@ int board_early_init_f (void)
 	/*-------------------------------------------------------------------------+
 	  | 4 MB FLASH. Initialize bank 2 with default values.
 	  +-------------------------------------------------------------------------*/
-	mtebc(pb2ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(10)|
+	mtebc(pb2ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs2_twt)|
 	      EBC_BXAP_BCE_DISABLE|
 	      EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
 	      EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
 	      EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
 	      EBC_BXAP_BEM_WRITEONLY|
 	      EBC_BXAP_PEN_DISABLED);
-	mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(0xFF800000)|
-	      EBC_BXCR_BS_4MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
+	mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(cs2_base)|
+	      cs2_size|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);

 	/*-------------------------------------------------------------------------+
 	  | FPGA. Initialize bank 7 with default values.
--- a/board/omap5912osk/flash.c
+++ b/board/omap5912osk/flash.c
@@ -236,14 +236,14 @@ static ulong flash_get_size (FPW * addr, flash_info_t * info)
 		info->flash_id +=FLASH_28F256K3;
 		info->sector_count = 259;
 		info->size = 0x02000000;
-			    printf ("\Intel StrataFlash 28F256K3C device initialized\n");
+		debug ("Intel StrataFlash 28F256K3C device initialized\n");
 		break;			/* => 32 MB	*/

 	case (FPW) (INTEL_ID_28F128J3A):
 		info->flash_id +=FLASH_28F128J3A;
 		info->sector_count = 259;
 		info->size = 0x02000000;
-			    printf ("\Micron StrataFlash MT28F128J3 device initialized\n");
+		debug ("Micron StrataFlash MT28F128J3 device initialized\n");
 		break;			/* => 32 MB	*/

 	default:
--- a/board/pm520/pm520.c
+++ b/board/pm520/pm520.c
@@ -133,10 +133,13 @@ long int initdram (int board_type)
 	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */

 	/* find RAM size using SDRAM CS1 only */
-	sdram_start(0);
-	test1 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
-	sdram_start(1);
-	test2 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+	if (!dramsize)
+		sdram_start(0);
+	test2 = test1 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+	if (!dramsize) {
+		sdram_start(1);
+		test2 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+	}
 	if (test1 > test2) {
 		sdram_start(0);
 		dramsize2 = test1;
--- a/board/sorcery/sorcery.c
+++ b/board/sorcery/sorcery.c
@@ -31,7 +31,7 @@ long int initdram (int board_type)
 	ulong size;

 	size = dramSetup ();
-	
+
 	return get_ram_size((ulong *)CFG_SDRAM_BASE, size);
 }

--- a/board/voiceblue/Makefile
+++ b/board/voiceblue/Makefile
@@ -0,0 +1,64 @@
+# (C) Copyright 2000-2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de
+#
+# (C) Copyright 2005
+# Ladislav Michl, 2N Telekomunikace, michl@2n.cz
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License version 2 as
+# published by the Free Software Foundation.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= voiceblue.o
+SOBJS	:= setup.o
+
+gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
+
+LOAD_ADDR = 0x10400000
+
+all:	$(LIB) eeprom.srec eeprom.bin
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+eeprom.srec:	eeprom.o
+	$(LD) -g -Ttext $(LOAD_ADDR) -o $(<:.o=) -e $(<:.o=) $^ \
+		-L../../examples -lstubs \
+		-L../../lib_generic -lgeneric \
+		-L$(gcclibdir) -lgcc
+	$(OBJCOPY) -O srec $(<:.o=) $@
+
+eeprom.bin:	eeprom.srec
+	$(OBJCOPY) -O binary $< $@ 2>/dev/null
+
+clean:
+	rm -f $(SOBJS) $(OBJS) eeprom eeprom.srec eeprom.bin
+
+distclean:	clean
+	rm -f $(LIB) core config.tmp *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
--- a/board/voiceblue/config.mk
+++ b/board/voiceblue/config.mk
@@ -0,0 +1,16 @@
+#
+# Linux-Kernel is expected to be at 1000'8000,
+# entry 1000'8000 (mem base + reserved)
+#
+
+sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp
+
+ifeq ($(VOICEBLUE_SMALL_FLASH),y)
+# We load ourself to internal SRAM at 2001'2000
+# Check map file when changing TEXT_BASE.
+# Everything has fit into 192kB internal SRAM!
+TEXT_BASE = 0x20012000
+else
+# Running in SDRAM...
+TEXT_BASE = 0x13000000
+endif
--- a/board/voiceblue/eeprom.c
+++ b/board/voiceblue/eeprom.c
@@ -0,0 +1,140 @@
+/*
+ * (C) Copyright 2005
+ * Ladislav Michl, 2N Telekomunikace, michl@2n.cz
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Some code shamelessly stolen back from Robin Getz.
+ */
+
+#define DEBUG
+
+#include <common.h>
+#include <exports.h>
+#include "../drivers/smc91111.h"
+
+#define SMC_BASE_ADDRESS CONFIG_SMC91111_BASE
+
+static int verify_macaddr(char *);
+static int set_mac(char *);
+
+int eeprom(int argc, char *argv[])
+{
+	app_startup(argv);
+	if (get_version() != XF_VERSION) {
+		printf("Wrong XF_VERSION.\n");
+		printf("Application expects ABI version %d\n", XF_VERSION);
+		printf("Actual U-Boot ABI version %d\n", (int)get_version());
+		return 1;
+	}
+
+	if ((SMC_inw (BANK_SELECT) & 0xFF00) != 0x3300) {
+		printf("SMSC91111 not found.\n");
+		return 2;
+	}
+
+	if (argc != 2) {
+		printf("VoiceBlue EEPROM writer\n");
+		printf("Built: %s at %s\n", __DATE__ , __TIME__ );
+		printf("Usage:\n\t<mac_address>");
+		return 3;
+	}
+
+	set_mac(argv[1]);
+	if (verify_macaddr(argv[1])) {
+		printf("*** ERROR ***\n");
+		return 4;
+	}
+
+	return 0;
+}
+
+static u16 read_eeprom_reg(u16 reg)
+{
+	int timeout;
+
+	SMC_SELECT_BANK(2);
+	SMC_outw(reg, PTR_REG);
+
+	SMC_SELECT_BANK(1);
+	SMC_outw(SMC_inw (CTL_REG) | CTL_EEPROM_SELECT | CTL_RELOAD,
+		 CTL_REG);
+	timeout = 100;
+	while((SMC_inw (CTL_REG) & CTL_RELOAD) && --timeout)
+		udelay(100);
+	if (timeout == 0) {
+		printf("Timeout Reading EEPROM register %02x\n", reg);
+		return 0;
+	}
+
+	return SMC_inw (GP_REG);
+}
+
+static int write_eeprom_reg(u16 value, u16 reg)
+{
+	int timeout;
+
+	SMC_SELECT_BANK(2);
+	SMC_outw(reg, PTR_REG);
+
+	SMC_SELECT_BANK(1);
+	SMC_outw(value, GP_REG);
+	SMC_outw(SMC_inw (CTL_REG) | CTL_EEPROM_SELECT | CTL_STORE, CTL_REG);
+	timeout = 100;
+	while ((SMC_inw(CTL_REG) & CTL_STORE) && --timeout)
+		udelay (100);
+	if (timeout == 0) {
+		printf("Timeout Writing EEPROM register %02x\n", reg);
+		return 0;
+	}
+
+	return 1;
+}
+
+static int verify_macaddr(char *s)
+{
+	u16 reg;
+	int i, err = 0;
+
+	printf("Verifying MAC Address: ");
+	err = i = 0;
+	for (i = 0; i < 3; i++) {
+		reg = read_eeprom_reg(0x20 + i);
+		printf("%02x:%02x%c", reg & 0xff, reg >> 8, i != 2 ? ':' : '\n');
+		err |= reg != ((u16 *)s)[i];
+	}
+
+	return err ? 0 : 1;
+}
+
+static int set_mac(char *s)
+{
+	int i;
+	char *e, eaddr[6];
+
+	/* turn string into mac value */
+	for (i = 0; i < 6; i++) {
+		eaddr[i] = simple_strtoul(s, &e, 16);
+		s = (*e) ? e+1 : e;
+	}
+
+	for (i = 0; i < 3; i++)
+		write_eeprom_reg(*(((u16 *)eaddr) + i), 0x20 + i);
+
+	return 0;
+}
--- a/board/voiceblue/setup.S
+++ b/board/voiceblue/setup.S
@@ -0,0 +1,280 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2004 Ales Jindra <jindra@2n.cz>
+ * (C) Copyright 2005 Ladislav Michl <michl@2n.cz>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+_TEXT_BASE:
+	.word	TEXT_BASE	/* SDRAM load addr from config.mk */
+
+OMAP5910_LPG1_BASE:		.word 0xfffbd000
+OMAP5910_TIPB_SWITCHES_BASE:	.word 0xfffbc800
+OMAP5910_MPU_TC_BASE:		.word 0xfffecc00
+OMAP5910_MPU_CLKM_BASE:		.word 0xfffece00
+OMAP5910_ULPD_PWR_MNG_BASE:	.word 0xfffe0800
+OMAP5910_DPLL1_BASE:		.word 0xfffecf00
+OMAP5910_GPIO_BASE:		.word 0xfffce000
+OMAP5910_MPU_WD_TIMER_BASE:	.word 0xfffec800
+OMAP5910_MPUI_BASE:		.word 0xfffec900
+
+_OMAP5910_ARM_CKCTL:		.word OMAP5910_ARM_CKCTL
+_OMAP5910_ARM_EN_CLK:		.word OMAP5910_ARM_EN_CLK
+
+OMAP5910_MPUI_CTRL:		.word 0x0000ff1b
+
+VAL_EMIFS_CS0_CONFIG:		.word 0x00009090
+VAL_EMIFS_CS1_CONFIG:		.word 0x00003031
+VAL_EMIFS_CS2_CONFIG:		.word 0x00003031
+VAL_EMIFS_CS3_CONFIG:		.word 0x0000c0c0
+VAL_EMIFS_DYN_WAIT:		.word 0x00000000
+/* autorefresh counter 0x246 ((64000000/13.4)-400)/8192) */
+				/*     SLRF       SD_RET     ARE        SDRAM_TYPE   ARCV           SDRAM_FREQUENCY PWD     CLK */
+VAL_EMIFF_SDRAM_CONFIG:		.word ((0 << 0) | (0 << 1) | (3 << 2) | (0xd << 4) | (0x246 << 8) | (0 << 24) | (0 << 26) | (0 << 27))
+VAL_EMIFF_SDRAM_CONFIG2:	.word 0x00000003
+VAL_EMIFF_MRS:			.word 0x00000037
+
+/*
+ * GPIO04 - D4 (Onboard LED)
+ * GPIO07 - LAN91C111 reset
+ */
+GPIO_DIRECTION:
+	.word 0x0000ff6f
+/*
+ * Disable everything, but D4 LED (connected through invertor)
+ */
+GPIO_OUTPUT:
+	.word 0x00000010
+
+MUX_CONFIG_BASE:
+	.word 0xfffe1000
+
+MUX_CONFIG_VALUES:
+	.align 4
+	.word 0x00000000	@ FUNC_MUX_CTRL_0
+	.word 0x00000000	@ FUNC_MUX_CTRL_1
+	.word 0x00000000	@ FUNC_MUX_CTRL_2
+	.word 0x00000000	@ FUNC_MUX_CTRL_3
+	.word 0x00000000	@ FUNC_MUX_CTRL_4
+	.word 0x12082480	@ FUNC_MUX_CTRL_5
+	.word 0x00000004	@ FUNC_MUX_CTRL_6
+	.word 0x00000003	@ FUNC_MUX_CTRL_7
+	.word 0x10001200	@ FUNC_MUX_CTRL_8
+	.word 0x01201012	@ FUNC_MUX_CTRL_9
+	.word 0x02081248	@ FUNC_MUX_CTRL_A
+	.word 0x00001248	@ FUNC_MUX_CTRL_B
+	.word 0x12240000	@ FUNC_MUX_CTRL_C
+	.word 0x00002000	@ FUNC_MUX_CTRL_D
+	.word 0x00000000	@ PULL_DWN_CTRL_0
+	.word 0x0000085f	@ PULL_DWN_CTRL_1
+	.word 0x01001000	@ PULL_DWN_CTRL_2
+	.word 0x00000000	@ PULL_DWN_CTRL_3
+	.word 0x00000000	@ GATE_INH_CTRL_0
+	.word 0x00000000	@ VOLTAGE_CTRL_0
+	.word 0x00000000	@ TEST_DBG_CTRL_0
+	.word 0x00000006	@ MOD_CONF_CTRL_0
+	.word 0x0000eaef	@ COMP_MODE_CTRL_0
+
+MUX_CONFIG_OFFSETS:
+	.align 1
+	.byte 0x00		@ FUNC_MUX_CTRL_0
+	.byte 0x04		@ FUNC_MUX_CTRL_1
+	.byte 0x08		@ FUNC_MUX_CTRL_2
+	.byte 0x10		@ FUNC_MUX_CTRL_3
+	.byte 0x14		@ FUNC_MUX_CTRL_4
+	.byte 0x18		@ FUNC_MUX_CTRL_5
+	.byte 0x1c		@ FUNC_MUX_CTRL_6
+	.byte 0x20		@ FUNC_MUX_CTRL_7
+	.byte 0x24		@ FUNC_MUX_CTRL_8
+	.byte 0x28		@ FUNC_MUX_CTRL_9
+	.byte 0x2c		@ FUNC_MUX_CTRL_A
+	.byte 0x30		@ FUNC_MUX_CTRL_B
+	.byte 0x34		@ FUNC_MUX_CTRL_C
+	.byte 0x38		@ FUNC_MUX_CTRL_D
+	.byte 0x40		@ PULL_DWN_CTRL_0
+	.byte 0x44		@ PULL_DWN_CTRL_1
+	.byte 0x48		@ PULL_DWN_CTRL_2
+	.byte 0x4c		@ PULL_DWN_CTRL_3
+	.byte 0x50		@ GATE_INH_CTRL_0
+	.byte 0x60		@ VOLTAGE_CTRL_0
+	.byte 0x70		@ TEST_DBG_CTRL_0
+	.byte 0x80		@ MOD_CONF_CTRL_0
+	.byte 0x0c		@ COMP_MODE_CTRL_0
+	.byte 0xff
+
+.globl platformsetup
+platformsetup:
+	/* Improve performance a bit... */
+	mrc	p15, 0, r1, c0, c0, 0		@ read C15 ID register
+	mrc	p15, 0, r1, c0, c0, 1		@ read C15 Cache information register
+	mrc	p15, 0, r1, c1, c0, 0		@ read C15 Control register
+	orr	r1, r1, #0x1000			@ enable I-cache, map interrupt vector 0xffff0000
+	mcr	p15, 0, r1, c1, c0, 0		@ write C15 Control register
+	mov	r1, #0x00
+	mcr	p15, 0, r1, c7, c5, 0		@ Flush I-cache
+	nop
+	nop
+	nop
+	nop
+
+	/* Setup clocking mode */
+	ldr	r0, OMAP5910_MPU_CLKM_BASE	@ prepare base of CLOCK unit
+	ldrh	r1, [r0, #0x18]			@ get reset status
+	bic	r1, r1, #(7 << 11)		@ clear clock select
+	orr	r1, r1, #(2 << 11)		@ set synchronous scalable
+	mov	r2, #0				@ set wait counter to 100 clock cycles
+
+icache_loop:
+	cmp	r2, #0x01
+	streqh	r1, [r0, #0x18]
+	add	r2, r2, #0x01
+	cmp	r2, #0x10
+	bne	icache_loop
+	nop
+
+	/* Setup clock divisors */
+	ldr	r0, OMAP5910_MPU_CLKM_BASE	@ base of CLOCK unit
+	ldr	r1, _OMAP5910_ARM_CKCTL
+	orr	r1, r1, #0x2000			@ enable DSP clock
+	strh	r1, [r0, #0x00]			@ setup clock divisors
+
+	/* Setup DPLL to generate requested freq */
+	ldr	r0, OMAP5910_DPLL1_BASE		@ base of DPLL1 register
+	mov	r1, #0x0010			@ set PLL_ENABLE
+	orr	r1, r1, #0x2000			@ set IOB to new locking
+	orr	r1, r1, #(OMAP5910_DPLL_MUL << 7) @ setup multiplier CLKREF
+	orr	r1, r1, #(OMAP5910_DPLL_DIV << 5) @ setup divider CLKREF
+	strh	r1, [r0]			@ write
+
+locking:
+	ldrh	r1, [r0]			@ get DPLL value
+	tst	r1, #0x01
+	beq	locking				@ while LOCK not set
+
+	/* Enable clock */
+	ldr	r0, OMAP5910_MPU_CLKM_BASE	@ base of CLOCK unit
+	mov	r1, #(1 << 10)			@ disable idle mode do not check
+						@ nWAKEUP pin, other remain active
+	strh	r1, [r0, #0x04]
+	ldr	r1, _OMAP5910_ARM_EN_CLK
+	strh	r1, [r0, #0x08]
+	mov	r1, #0x003f			@ FLASH.RP not enabled in idle and
+						@ max delayed ( 32 x CLKIN )
+	strh	r1, [r0, #0x0c]
+
+	/* Configure 5910 pins functions to match our board. */
+	ldr     r0, MUX_CONFIG_BASE
+	adr	r1, MUX_CONFIG_VALUES
+	adr	r2, MUX_CONFIG_OFFSETS
+next_mux_cfg:
+	ldrb	r3, [r2], #1
+	ldr	r4, [r1], #4
+	cmp	r3, #0xff
+	strne	r4, [r0, r3]
+	bne	next_mux_cfg
+
+	/* Configure GPIO pins (also enables onboard LED) */
+	ldr	r0, OMAP5910_GPIO_BASE
+	ldr	r1, GPIO_OUTPUT
+	strh    r1, [r0, #0x04]
+	ldr	r1, GPIO_DIRECTION
+	strh	r1, [r0, #0x08]
+
+	/* EnablePeripherals */
+	ldr	r0, OMAP5910_MPU_CLKM_BASE	@ CLOCK unit
+	mov	r1, #0x0001			@ Peripheral enable
+	strh	r1, [r0, #0x14]
+
+	/* Program LED Pulse Generator */
+	ldr	r0, OMAP5910_LPG1_BASE		@ 1st LED Pulse Generator
+	mov	r1, #0x7F			@ Set obscure frequency in
+	strb	r1, [r0, #0x00]			@ LCR
+	mov	r1, #0x01			@ Enable clock (CLK_EN) in
+	strb    r1, [r0, #0x04]			@ PMR
+
+	/* TIPB Lock UART1 */
+	ldr	r0, OMAP5910_TIPB_SWITCHES_BASE	@ prepare base of TIPB switches
+	mov	r1, #1				@ ARM allocated
+	strh	r1, [r0,#0x04]			@ clear IRQ line and status bits
+	strh	r1, [r0,#0x00]
+	ldrh	r1, [r0,#0x04]
+
+	/* Disable watchdog */
+	ldr	r0, OMAP5910_MPU_WD_TIMER_BASE
+	mov	r1, #0xf5
+	strh	r1, [r0, #0x8]
+	mov	r1, #0xa0
+	strh	r1, [r0, #0x8]
+
+	/* Enable MCLK */
+	ldr	r0, OMAP5910_ULPD_PWR_MNG_BASE
+	mov	r1, #0x6
+	strh	r1, [r0, #0x34]
+	strh	r1, [r0, #0x34]
+
+	/* Setup clock divisors */
+	ldr	r0, OMAP5910_ULPD_PWR_MNG_BASE	@ base of ULDPL DPLL1 register
+
+	mov	r1, #0x0010			@ set PLL_ENABLE
+	orr	r1, r1, #0x2000			@ set IOB to new locking
+	strh	r1, [r0]			@ write
+
+ulocking:
+	ldrh	r1, [r0]			@ get DPLL value
+	tst	r1, #1
+	beq	ulocking			@ while LOCK not set
+
+	/* EMIF init */
+	ldr	r0, OMAP5910_MPU_TC_BASE
+	ldrh	r1, [r0, #0x0c]			@ EMIFS_CONFIG_REG
+	bic	r1, r1, #0x0c			@ pwr down disabled, flash WP
+	orr	r1, r1, #0x01
+	str	r1, [r0, #0x0c]
+
+	ldr	r1, VAL_EMIFS_CS0_CONFIG
+	str	r1, [r0, #0x10]			@ EMIFS_CS0_CONFIG
+	ldr	r1, VAL_EMIFS_CS1_CONFIG
+	str	r1, [r0, #0x14]			@ EMIFS_CS1_CONFIG
+	ldr	r1, VAL_EMIFS_CS2_CONFIG
+	str	r1, [r0, #0x18]			@ EMIFS_CS2_CONFIG
+	ldr	r1, VAL_EMIFS_CS3_CONFIG
+	str	r1, [r0, #0x1c]			@ EMIFS_CS3_CONFIG
+	ldr	r1, VAL_EMIFS_DYN_WAIT
+	str	r1, [r0, #0x40]			@ EMIFS_CFG_DYN_WAIT
+
+	/* Setup SDRAM */
+	ldr	r1, VAL_EMIFF_SDRAM_CONFIG
+	str	r1, [r0, #0x20]			@ EMIFF_SDRAM_CONFIG
+	ldr	r1, VAL_EMIFF_SDRAM_CONFIG2
+	str	r1, [r0, #0x3c]			@ EMIFF_SDRAM_CONFIG2
+	ldr	r1, VAL_EMIFF_MRS
+	str	r1, [r0, #0x24]			@ EMIFF_MRS
+	/* SDRAM needs 100us to stabilize */
+	mov	r0, #0x4000
+sdelay:
+	subs	r0, r0, #0x1
+	bne 	sdelay
+
+	/* back to arch calling code */
+	mov	pc, lr
+.end
--- a/board/voiceblue/u-boot.lds
+++ b/board/voiceblue/u-boot.lds
@@ -0,0 +1,55 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/arm925t/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
--- a/board/voiceblue/voiceblue.c
+++ b/board/voiceblue/voiceblue.c
@@ -0,0 +1,151 @@
+/*
+ * (C) Copyright 2005 2N TELEKOMUNIKACE, Ladislav Michl
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+int board_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	*((volatile unsigned char *) VOICEBLUE_LED_REG) = 0xaa;
+
+	/* arch number of VoiceBlue board */
+	/* TODO: use define from asm/mach-types.h */
+	gd->bd->bi_arch_number = 218;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0x10000100;
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	*((volatile unsigned short *) VOICEBLUE_LED_REG) = 0xff;
+
+ 	/* Take the Ethernet controller out of reset and wait
+ 	 * for the EEPROM load to complete. */
+	*((volatile unsigned short *) GPIO_DATA_OUTPUT_REG) |= 0x80;
+	udelay(10);	/* doesn't work before interrupt_init call */
+	*((volatile unsigned short *) GPIO_DATA_OUTPUT_REG) &= ~0x80;
+	udelay(500);
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+#ifndef VOICEBLUE_SMALL_FLASH
+
+#include <jffs2/jffs2.h>
+
+extern flash_info_t flash_info[];
+static struct part_info partinfo;
+static int current_part = -1;
+
+/* Partition table (Linux MTD see it this way)
+ *
+ * 0 - U-Boot
+ * 1 - env
+ * 2 - redundant env
+ * 3 - data1 (jffs2)
+ * 4 - data2 (jffs2)
+ */
+
+static struct {
+	ulong offset;
+	ulong size;
+} part[5];
+
+static void partition_flash(flash_info_t *info)
+{
+	char mtdparts[128];
+	int i, n, size, psize;
+	const ulong plen[3] = { CFG_MONITOR_LEN, CFG_ENV_SIZE, CFG_ENV_SIZE };
+
+	size = n = 0;
+	for (i = 0; i < 4; i++) {
+		part[i].offset = info->start[n];
+		psize = i < 3 ? plen[i] : (info->size - size) / 2;
+		while (part[i].size < psize) {
+			if (++n > info->sector_count) {
+				printf("Partitioning error. System halted.\n");
+				while (1) ;
+			}
+			part[i].size += info->start[n] - info->start[n - 1];
+		}
+		size += part[i].size;
+	}
+	part[4].offset = info->start[n];
+	part[4].size = info->start[info->sector_count - 1] - info->start[n];
+
+	sprintf(mtdparts, "omapflash.0:"
+			"%dk(U-Boot)ro,%dk(env),%dk(r_env),%dk(data1),-(data2)",
+			part[0].size >> 10, part[1].size >> 10,
+			part[2].size >> 10, part[3].size >> 10);
+	setenv ("mtdparts", mtdparts);
+}
+
+struct part_info* jffs2_part_info(int part_num)
+{
+	void *jffs2_priv_saved = partinfo.jffs2_priv;
+
+	if (part_num != 3 && part_num != 4)
+		return NULL;
+
+	if (current_part != part_num) {
+		memset(&partinfo, 0, sizeof(partinfo));
+		current_part = part_num;
+		partinfo.offset = (char*) part[part_num].offset;
+		partinfo.size = part[part_num].size;
+		partinfo.usr_priv = &current_part;
+		partinfo.jffs2_priv = jffs2_priv_saved;
+	}
+
+	return &partinfo;
+}
+
+#endif
+
+int misc_init_r(void)
+{
+	*((volatile unsigned short *) VOICEBLUE_LED_REG) = 0x55;
+
+#ifndef VOICEBLUE_SMALL_FLASH
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf("Unknown flash. System halted.\n");
+		while (1) ;
+	}
+	partition_flash(&flash_info[0]);
+#endif
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	*((volatile unsigned char *) VOICEBLUE_LED_REG) = 0x00;
+
+	return 0;
+}
--- a/common/altera.c
+++ b/common/altera.c
@@ -158,6 +158,7 @@ int altera_info( Altera_desc *desc )
 				/* Add new family types here */
 			default:
 				/* we don't need a message here - we give one up above */
+				break;
 			}
 		} else {
 			printf ("No Device Function Table.\n");
--- a/common/cmd_nand.c
+++ b/common/cmd_nand.c
@@ -670,11 +670,12 @@ static int NanD_IdentChip(struct nand_chip *nand, int floor, int chip)
 	id = READ_NAND(nand->IO_ADDR);

 	NAND_DISABLE_CE(nand);  /* set pin high */
-	/* No response - return failure */
-	if (mfr == 0xff || mfr == 0) {
+
 #ifdef NAND_DEBUG
-		printf("NanD_Command (ReadID) got %d %d\n", mfr, id);
+	printf("NanD_Command (ReadID) got %x %x\n", mfr, id);
 #endif
+	if (mfr == 0xff || mfr == 0) {
+		/* No response - return failure */
 		return 0;
 	}

@@ -1218,6 +1219,8 @@ static int nand_write_page (struct nand_chip *nand,
 	}
 	if (nand->bus16) {
 		for (i = 0; i < nand->oobsize; i += 2) {
+			u16 val;
+
 			val = READ_NAND (nand->IO_ADDR);
 			nand->data_buf[i] = val & 0xff;
 			nand->data_buf[i + 1] = val >> 8;
--- a/common/cmd_net.c
+++ b/common/cmd_net.c
@@ -33,7 +33,7 @@

 extern int do_bootm (cmd_tbl_t *, int, int, char *[]);

-static int netboot_common (int, cmd_tbl_t *, int , char *[]);
+static int netboot_common (proto_t, cmd_tbl_t *, int , char *[]);

 int do_bootp (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
@@ -152,7 +152,7 @@ static void netboot_update_env (void)
 }

 static int
-netboot_common (int proto, cmd_tbl_t *cmdtp, int argc, char *argv[])
+netboot_common (proto_t proto, cmd_tbl_t *cmdtp, int argc, char *argv[])
 {
 	char *s;
 	int   rcode = 0;
--- a/common/cmd_universe.c
+++ b/common/cmd_universe.c
@@ -72,6 +72,9 @@ int universe_init(void)
 	dev->busdevfn = busdevfn;

 	pci_read_config_dword(busdevfn, PCI_BASE_ADDRESS_1, &val);
+	if (val & 1) {
+		pci_read_config_dword(busdevfn, PCI_BASE_ADDRESS_0, &val);
+	}
 	val &= ~0xf;
 	dev->uregs = (UNIVERSE *)val;

@@ -102,7 +105,13 @@ int universe_init(void)
 	 *   Arbitration Mode
 	 *   DTACK Enable
 	 */
-	writel(0x15060000, &dev->uregs->misc_ctl);
+	writel(0x15040000 | (readl(&dev->uregs->misc_ctl) & 0x00020000), &dev->uregs->misc_ctl);
+
+	if (readl(&dev->uregs->misc_ctl) & 0x00020000) {
+		debug ("System Controller!\n"); /* test-only */
+	} else {
+		debug ("Not System Controller!\n"); /* test-only */
+	}

 	/*
 	 * Lets turn off interrupts
@@ -114,12 +123,14 @@ int universe_init(void)
 	writel(0x0000, &dev->uregs->lint_map1);  /* Map all ints to 0 */
 	eieio();

+	return 0;
+
 break_30:
 	free(dev);
 break_20:
 	lastError = result;

-	return 0;
+	return result;
 }


@@ -193,13 +204,13 @@ int universe_pci_slave_window(unsigned int pciAddr, unsigned int vmeAddr, int si

 	switch (pms & PCI_MS_Mxx) {
 	case PCI_MS_MEM:
-		ctl = 0x00000000;
+		ctl |= 0x00000000;
 		break;
 	case PCI_MS_IO:
-		ctl = 0x00000001;
+		ctl |= 0x00000001;
 		break;
 	case PCI_MS_CONFIG:
-		ctl = 0x00000002;
+		ctl |= 0x00000002;
 		break;
 	}

@@ -278,13 +289,13 @@ int universe_vme_slave_window(unsigned int vmeAddr, unsigned int pciAddr, int si

 	switch (pms & PCI_MS_Mxx) {
 	case PCI_MS_MEM:
-		ctl = 0x00000000;
+		ctl |= 0x00000000;
 		break;
 	case PCI_MS_IO:
-		ctl = 0x00000001;
+		ctl |= 0x00000001;
 		break;
 	case PCI_MS_CONFIG:
-		ctl = 0x00000002;
+		ctl |= 0x00000002;
 		break;
 	}

--- a/common/command.c
+++ b/common/command.c
@@ -136,9 +136,9 @@ do_test (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])

 		if (adv == 2) {
 			if (strcmp(ap[0], "-z") == 0)
-				expr = strlen(ap[1]) == 0 ? 0 : 1;
-			else if (strcmp(ap[0], "-n") == 0)
 				expr = strlen(ap[1]) == 0 ? 1 : 0;
+			else if (strcmp(ap[0], "-n") == 0)
+				expr = strlen(ap[1]) == 0 ? 0 : 1;
 			else {
 				expr = 1;
 				break;
--- a/cpu/arm920t/at91rm9200/Makefile
+++ b/cpu/arm920t/at91rm9200/Makefile
@@ -1,5 +1,5 @@
 #
-# (C) Copyright 2003
+# (C) Copyright 2000-2005
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # See file CREDITS for list of people who contributed to this
@@ -23,22 +23,20 @@

 include $(TOPDIR)/config.mk

-LIB	= lib$(CPU).a
+LIB	= lib$(SOC).a

-START	= start.o
-OBJS	= serial.o interrupts.o cpu.o \
-	  at91rm9200_ether.o i2c.o
-SOBJS	= lowlevel.o
+OBJS	= ether.o i2c.o interrupts.o serial.o
+SOBJS	= lowlevel_init.o

-all:	.depend $(START) $(LIB)
+all:	.depend $(LIB)

 $(LIB):	$(OBJS) $(SOBJS)
 	$(AR) crv $@ $(OBJS) $(SOBJS)

 #########################################################################

-.depend:	Makefile $(START:.o=.S) $(OBJS:.o=.c)
-		$(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@
+.depend:	Makefile $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@

 sinclude .depend

--- a/cpu/at91rm9200/at91rm9200_ether.c
+++ b/cpu/at91rm9200/at91rm9200_ether.c
--- a/cpu/arm920t/at91rm9200/i2c.c
+++ b/cpu/arm920t/at91rm9200/i2c.c
@@ -138,12 +138,12 @@ i2c_read (unsigned char chip, unsigned int addr, int alen,

 int
 i2c_write(unsigned char chip, unsigned int addr, int alen,
-							unsigned char *buffer, int len)
+	  unsigned char *buffer, int len)
 {
+#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
 	int i;
 	unsigned char *buf;

-#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
 	/* we only allow one address byte */
 	if (alen > 1)
 		return 1;
@@ -189,4 +189,19 @@ i2c_init(int speed, int slaveaddr)
 	debug ("Found AT91 i2c\n");
 	return;
 }
+
+uchar i2c_reg_read(uchar i2c_addr, uchar reg)
+{
+	char buf;
+
+	i2c_read(i2c_addr, reg, 1, &buf, 1);
+
+	return(buf);
+}
+
+void i2c_reg_write(uchar i2c_addr, uchar reg, uchar val)
+{
+	i2c_write(i2c_addr, reg, 1, &val, 1);
+}
+
 #endif /* CONFIG_HARD_I2C */
--- a/cpu/arm920t/at91rm9200/interrupts.c
+++ b/cpu/arm920t/at91rm9200/interrupts.c
@@ -31,9 +31,9 @@
 */

 #include <common.h>
-#include <asm/io.h>
+/*#include <asm/io.h>*/
 #include <asm/arch/hardware.h>
-#include <asm/proc/ptrace.h>
+/*#include <asm/proc/ptrace.h>*/

 /* the number of clocks per CFG_HZ */
 #define TIMER_LOAD_VAL (CFG_HZ_CLOCK/CFG_HZ)
@@ -42,119 +42,11 @@
 #define READ_TIMER (tmr->TC_CV & 0x0000ffff)
 AT91PS_TC tmr;

-#ifdef CONFIG_USE_IRQ
-#error There is no IRQ support for AT91RM9200 in U-Boot yet.
-#else
-void enable_interrupts (void)
-{
-	return;
-}
-int disable_interrupts (void)
-{
-	return 0;
-}
-#endif
-
-
-void bad_mode (void)
-{
-	panic ("Resetting CPU ...\n");
-	reset_cpu (0);
-}
-
-void show_regs (struct pt_regs *regs)
-{
-	unsigned long flags;
-	const char *processor_modes[] = {
-	"USER_26",	"FIQ_26",	"IRQ_26",	"SVC_26",
-	"UK4_26",	"UK5_26",	"UK6_26",	"UK7_26",
-	"UK8_26",	"UK9_26",	"UK10_26",	"UK11_26",
-	"UK12_26",	"UK13_26",	"UK14_26",	"UK15_26",
-	"USER_32",	"FIQ_32",	"IRQ_32",	"SVC_32",
-	"UK4_32",	"UK5_32",	"UK6_32",	"ABT_32",
-	"UK8_32",	"UK9_32",	"UK10_32",	"UND_32",
-	"UK12_32",	"UK13_32",	"UK14_32",	"SYS_32",
-	};
-
-	flags = condition_codes (regs);
-
-	printf ("pc : [<%08lx>]    lr : [<%08lx>]\n"
-		"sp : %08lx  ip : %08lx  fp : %08lx\n",
-		instruction_pointer (regs),
-		regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp);
-	printf ("r10: %08lx  r9 : %08lx  r8 : %08lx\n",
-		regs->ARM_r10, regs->ARM_r9, regs->ARM_r8);
-	printf ("r7 : %08lx  r6 : %08lx  r5 : %08lx  r4 : %08lx\n",
-		regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4);
-	printf ("r3 : %08lx  r2 : %08lx  r1 : %08lx  r0 : %08lx\n",
-		regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0);
-	printf ("Flags: %c%c%c%c",
-		flags & CC_N_BIT ? 'N' : 'n',
-		flags & CC_Z_BIT ? 'Z' : 'z',
-		flags & CC_C_BIT ? 'C' : 'c',
-		flags & CC_V_BIT ? 'V' : 'v');
-	printf ("  IRQs %s  FIQs %s  Mode %s%s\n",
-		interrupts_enabled (regs) ? "on" : "off",
-		fast_interrupts_enabled (regs) ? "on" : "off",
-		processor_modes[processor_mode (regs)],
-		thumb_mode (regs) ? " (T)" : "");
-}
-
-void do_undefined_instruction (struct pt_regs *pt_regs)
-{
-	printf ("undefined instruction\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
-void do_software_interrupt (struct pt_regs *pt_regs)
-{
-	printf ("software interrupt\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
-void do_prefetch_abort (struct pt_regs *pt_regs)
-{
-	printf ("prefetch abort\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
-void do_data_abort (struct pt_regs *pt_regs)
-{
-	printf ("data abort\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
-void do_not_used (struct pt_regs *pt_regs)
-{
-	printf ("not used\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
-void do_fiq (struct pt_regs *pt_regs)
-{
-	printf ("fast interrupt request\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
-void do_irq (struct pt_regs *pt_regs)
-{
-	printf ("interrupt request\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
 static ulong timestamp;
 static ulong lastinc;

 int interrupt_init (void)
 {
-
 	tmr = AT91C_BASE_TC0;

 	/* enables TC1.0 clock */
@@ -266,3 +158,53 @@ ulong get_tbclk (void)
 	tbclk = CFG_HZ;
 	return tbclk;
 }
+
+/*
+ * Reset the cpu by setting up the watchdog timer and let him time out
+ * or toggle a GPIO pin on the AT91RM9200DK board
+ */
+void reset_cpu (ulong ignored)
+{
+
+#ifdef CONFIG_DBGU
+	AT91PS_USART us = (AT91PS_USART) AT91C_BASE_DBGU;
+#endif
+#ifdef CONFIG_USART0
+	AT91PS_USART us = AT91C_BASE_US0;
+#endif
+#ifdef CONFIG_USART1
+	AT91PS_USART us = AT91C_BASE_US1;
+#endif
+#ifdef CONFIG_AT91RM9200DK
+	AT91PS_PIO pio = AT91C_BASE_PIOA;
+#endif
+
+	/*shutdown the console to avoid strange chars during reset */
+	us->US_CR = (AT91C_US_RSTRX | AT91C_US_RSTTX);
+
+#ifdef CONFIG_AT91RM9200DK
+	/* Clear PA19 to trigger the hard reset */
+	pio->PIO_CODR = 0x00080000;
+	pio->PIO_OER  = 0x00080000;
+	pio->PIO_PER  = 0x00080000;
+#endif
+
+	/* this is the way Linux does it */
+
+	/* FIXME:
+	 * These defines should be moved into
+	 * include/asm-arm/arch-at91rm9200/AT91RM9200.h
+	 * as soon as the whitespace fix gets applied.
+	 */
+	#define AT91C_ST_RSTEN (0x1 << 16)
+	#define AT91C_ST_EXTEN (0x1 << 17)
+	#define AT91C_ST_WDRST (0x1 <<  0)
+	#define ST_WDMR *((unsigned long *)0xfffffd08)	/* watchdog mode register */
+	#define ST_CR *((unsigned long *)0xfffffd00)	/* system clock control register */
+
+	ST_WDMR = AT91C_ST_RSTEN | AT91C_ST_EXTEN | 1 ;
+	ST_CR = AT91C_ST_WDRST;
+
+	while (1);
+	/* Never reached */
+}
--- a/cpu/arm920t/at91rm9200/lowlevel_init.S
+++ b/cpu/arm920t/at91rm9200/lowlevel_init.S
--- a/cpu/arm920t/at91rm9200/serial.c
+++ b/cpu/arm920t/at91rm9200/serial.c
@@ -55,11 +55,8 @@ void serial_setbrg (void)

 	if ((baudrate = gd->baudrate) <= 0)
 		baudrate = CONFIG_BAUDRATE;
-	if (baudrate == 0 || baudrate == CONFIG_BAUDRATE)
-		us->US_BRGR = CFG_AT91C_BRGR_DIVISOR;	/* hardcode so no __divsi3 */
-	else
-		/* MASTER_CLOCK/(16 * baudrate) */
-		us->US_BRGR = (AT91C_MASTER_CLOCK >> 4)/baudrate;
+	/* MASTER_CLOCK/(16 * baudrate) */
+	us->US_BRGR = (AT91C_MASTER_CLOCK >> 4)/baudrate;
 }

 int serial_init (void)
--- a/cpu/arm920t/imx/interrupts.c
+++ b/cpu/arm920t/imx/interrupts.c
@@ -117,4 +117,23 @@ ulong get_tbclk (void)
 	return tbclk;
 }

+/*
+ * Reset the cpu by setting up the watchdog timer and let him time out
+ */
+void reset_cpu (ulong ignored)
+{
+	/* Disable watchdog and set Time-Out field to 0 */
+	WCR = 0x00000000;
+
+	/* Write Service Sequence */
+	WSR = 0x00005555;
+	WSR = 0x0000AAAA;
+
+	/* Enable watchdog */
+	WCR = 0x00000001;
+
+	while (1);
+	/*NOTREACHED*/
+}
+
 #endif /* defined (CONFIG_IMX) */
--- a/cpu/arm920t/s3c24x0/interrupts.c
+++ b/cpu/arm920t/s3c24x0/interrupts.c
@@ -185,4 +185,33 @@ ulong get_tbclk (void)
 	return tbclk;
 }

+/*
+ * reset the cpu by setting up the watchdog timer and let him time out
+ */
+void reset_cpu (ulong ignored)
+{
+	volatile S3C24X0_WATCHDOG * watchdog;
+
+#ifdef CONFIG_TRAB
+	extern void disable_vfd (void);
+
+	disable_vfd();
+#endif
+
+	watchdog = S3C24X0_GetBase_WATCHDOG();
+
+	/* Disable watchdog */
+	watchdog->WTCON = 0x0000;
+
+	/* Initialize watchdog timer count register */
+	watchdog->WTCNT = 0x0001;
+
+	/* Enable watchdog timer; assert reset at timer timeout */
+	watchdog->WTCON = 0x0021;
+
+	while(1);	/* loop forever and wait for reset to happen */
+
+	/*NOTREACHED*/
+}
+
 #endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) */
--- a/cpu/arm920t/start.S
+++ b/cpu/arm920t/start.S
@@ -433,39 +433,3 @@ fiq:
 	bl 	do_fiq

 #endif
-
-	.align	5
-.globl reset_cpu
-reset_cpu:
-#ifdef CONFIG_S3C2400
-	bl	disable_interrupts
-# ifdef CONFIG_TRAB
-	bl	disable_vfd
-# endif
-	ldr	r1, _rWTCON
-	ldr	r2, _rWTCNT
-	/* Disable watchdog */
-	mov	r3, #0x0000
-	str	r3, [r1]
-	/* Initialize watchdog timer count register */
-	mov	r3, #0x0001
-	str	r3, [r2]
-	/* Enable watchdog timer; assert reset at timer timeout */
-	mov	r3, #0x0021
-	str	r3, [r1]
-_loop_forever:
-	b	_loop_forever
-_rWTCON:
-	.word	0x15300000
-_rWTCNT:
-	.word	0x15300008
-#else /* ! CONFIG_S3C2400 */
-	mov     ip, #0
-	mcr     p15, 0, ip, c7, c7, 0           @ invalidate cache
-	mcr     p15, 0, ip, c8, c7, 0           @ flush TLB (v4)
-	mrc     p15, 0, ip, c1, c0, 0           @ get ctrl register
-	bic     ip, ip, #0x000f                 @ ............wcam
-	bic     ip, ip, #0x2100                 @ ..v....s........
-	mcr     p15, 0, ip, c1, c0, 0           @ ctrl register
-	mov     pc, r0
-#endif /* CONFIG_S3C2400 */
--- a/cpu/at91rm9200/cpu.c
+++ b/cpu/at91rm9200/cpu.c
@@ -1,200 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * CPU specific code
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-
-#if !defined(CONFIG_DBGU) && !defined(CONFIG_USART0) && !defined(CONFIG_USART1)
-#error must define one of CONFIG_DBGU or CONFIG_USART0 or CONFIG_USART1
-#endif
-
-/* read co-processor 15, register #1 (control register) */
-static unsigned long read_p15_c1(void)
-{
-    unsigned long value;
-
-    __asm__ __volatile__(
-	"mrc     p15, 0, %0, c1, c0, 0   @ read control reg\n"
-	: "=r" (value)
-	:
-	: "memory");
-    /*printf("p15/c1 is = %08lx\n", value); */
-    return value;
-}
-
-/* write to co-processor 15, register #1 (control register) */
-static void write_p15_c1(unsigned long value)
-{
-    /*printf("write %08lx to p15/c1\n", value); */
-    __asm__ __volatile__(
-	"mcr     p15, 0, %0, c1, c0, 0   @ write it back\n"
-	: "=r" (value)
-	:
-	: "memory");
-
-    read_p15_c1();
-}
-
-static void cp_delay(void)
-{
-    volatile int i;
-
-    /* copro seems to need some delay between reading and writing */
-    for (i=0; i<100; i++);
-}
-/* See also ARM Ref. Man. */
-#define C1_MMU		(1<<0)	/* mmu off/on */
-#define C1_ALIGN	(1<<1)	/* alignment faults off/on */
-#define C1_IDC		(1<<2)	/* icache and/or dcache off/on */
-#define C1_WRITE_BUFFER	(1<<3)	/* write buffer off/on */
-#define C1_BIG_ENDIAN	(1<<7)	/* big endian off/on */
-#define C1_SYS_PROT	(1<<8)	/* system protection */
-#define C1_ROM_PROT	(1<<9)	/* ROM protection */
-#define C1_HIGH_VECTORS	(1<<13)	/* location of vectors: low/high addresses */
-
-int cpu_init(void)
-{
-	/*
-	 * setup up stacks if necessary
-	 */
-#ifdef CONFIG_USE_IRQ
-	DECLARE_GLOBAL_DATA_PTR;
-
-	IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
-	FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
-#endif
-	return 0;
-}
-
-int cleanup_before_linux(void)
-{
-    /*
-     * this function is called just before we call linux
-     * it prepares the processor for linux
-     *
-     * we turn off caches etc ...
-     * and we set the CPU-speed to 73 MHz - see start.S for details
-     */
-
-    disable_interrupts();
-    return 0;
-}
-
-int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
-
-#ifdef CFG_SOFT_RESET
-    disable_interrupts();
-    reset_cpu(0);
-#else
-#ifdef CONFIG_DBGU
-   AT91PS_USART us = (AT91PS_USART) AT91C_BASE_DBGU;
-#endif
-#ifdef CONFIG_USART0
-   AT91PS_USART us = AT91C_BASE_US0;
-#endif
-#ifdef CONFIG_USART1
-   AT91PS_USART us = AT91C_BASE_US1;
-#endif
-   AT91PS_PIO pio = AT91C_BASE_PIOA;
-
-   /*shutdown the console to avoid strange chars during reset */
-   us->US_CR = (AT91C_US_RSTRX | AT91C_US_RSTTX);
-
-#ifdef CONFIG_AT91RM9200DK
-   /* Clear PA19 to trigger the hard reset */
-   pio->PIO_CODR = 0x00080000;
-   pio->PIO_OER  = 0x00080000;
-   pio->PIO_PER  = 0x00080000;
-#endif
-#ifdef CONFIG_CMC_PU2
-/* this is the way Linux does it */
-#define AT91C_ST_RSTEN (0x1 << 16)
-#define AT91C_ST_EXTEN (0x1 << 17)
-#define AT91C_ST_WDRST (0x1 <<  0)
-/* watchdog mode register */
-#define ST_WDMR *((unsigned long *)0xfffffd08)
-/* system clock control register */
-#define ST_CR *((unsigned long *)0xfffffd00)
-	ST_WDMR = AT91C_ST_RSTEN | AT91C_ST_EXTEN | 1 ;
-	ST_CR = AT91C_ST_WDRST;
-   /* Never reached */
-#endif
-#endif
-   return 0;
-}
-
-void icache_enable(void)
-{
-    ulong reg;
-    reg = read_p15_c1();
-    cp_delay();
-    write_p15_c1(reg | C1_IDC);
-}
-
-void icache_disable(void)
-{
-    ulong reg;
-    reg = read_p15_c1();
-    cp_delay();
-    write_p15_c1(reg & ~C1_IDC);
-}
-
-int icache_status(void)
-{
-    return (read_p15_c1() & C1_IDC) != 0;
-    return 0;
-}
-
-void dcache_enable(void)
-{
-    ulong reg;
-    reg = read_p15_c1();
-    cp_delay();
-    write_p15_c1(reg | C1_IDC);
-}
-
-void dcache_disable(void)
-{
-    ulong reg;
-    reg = read_p15_c1();
-    cp_delay();
-    write_p15_c1(reg & ~C1_IDC);
-}
-
-int dcache_status(void)
-{
-    return (read_p15_c1() & C1_IDC) != 0;
-    return 0;
-}
--- a/cpu/at91rm9200/start.S
+++ b/cpu/at91rm9200/start.S
@@ -1,391 +0,0 @@
-/*
- *  armboot - Startup Code for ARM720 CPU-core
- *
- *  Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
- *  Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-#include "config.h"
-#include "version.h"
-
-
-/*
- *************************************************************************
- *
- * Jump vector table as in table 3.1 in [1]
- *
- *************************************************************************
- */
-
-
-.globl _start
-_start:	b       reset
-	ldr	pc, _undefined_instruction
-	ldr	pc, _software_interrupt
-	ldr	pc, _prefetch_abort
-	ldr	pc, _data_abort
-	ldr	pc, _not_used
-	ldr	pc, _irq
-	ldr	pc, _fiq
-
-_undefined_instruction:	.word undefined_instruction
-_software_interrupt:	.word software_interrupt
-_prefetch_abort:	.word prefetch_abort
-_data_abort:		.word data_abort
-_not_used:		.word not_used
-_irq:			.word irq
-_fiq:			.word fiq
-
-	.balignl 16,0xdeadbeef
-
-
-/*
- *************************************************************************
- *
- * Startup Code (reset vector)
- *
- * do important init only if we don't start from memory!
- * relocate armboot to ram
- * setup stack
- * jump to second stage
- *
- *************************************************************************
- */
-
-_TEXT_BASE:
-	.word	TEXT_BASE
-
-.globl _armboot_start
-_armboot_start:
-	.word _start
-
-/*
- * These are defined in the board-specific linker script.
- */
-.globl _bss_start
-_bss_start:
-	.word __bss_start
-
-.globl _bss_end
-_bss_end:
-	.word _end
-
-#ifdef CONFIG_USE_IRQ
-/* IRQ stack memory (calculated at run-time) */
-.globl IRQ_STACK_START
-IRQ_STACK_START:
-	.word	0x0badc0de
-
-/* IRQ stack memory (calculated at run-time) */
-.globl FIQ_STACK_START
-FIQ_STACK_START:
-	.word 0x0badc0de
-#endif
-
-
-/*
- * the actual reset code
- */
-
-reset:
-	/*
-	 * set the cpu to SVC32 mode
-	 */
-	mrs     r0,cpsr
-	bic     r0,r0,#0x1f
-	orr     r0,r0,#0xd3 /* was 13 */
-	msr     cpsr,r0
-
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-	/* scratch stack */
-/****	ldr 	r1, =0x00204000		****/
-	/* Insure word alignment */
-/****	bic     r1, r1, #3		****/
-	/* Init stack SYS	 */
-/****	mov     sp, r1			****/
-	/*
-	 * This does a lot more than just set up the memory, which
-	 * is why it's called lowlevel_init
-	 */
-	bl	lowlevel_init /* in lowlevel.S */
-
-	/*
-	 * Read/modify/write CP15 control register
-	 * disable MMU, enable I-Cache, select Asychronous Clocking Mode
-	 */
-
-	mrc     p15, 0, r0, c1, c0, 0	@ read cp15 control register (cp15 r1) in r0
-	bic	r0, r0, #0x00002300	@ clear bits 13, 9:8 (--V- --RS)
-	bic	r0, r0, #0x0000008f	@ clear bits 7, 3:0 (B--- WCAM)
-	orr	r0, r0, #0x00000002	@ set bit 2 (A) Align
-	orr	r0, r0, #0x00000004	@ set bit 3 (C) D-Cache
-	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-Cache
-	orr	r0, r0, #0xC0000000	@ set bits 31:30 (iA, nF)
-	mcr     p15, 0, r0, c1, c0, 0	@ write r0 in cp15 control register (cp15 r1)
-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
-	/*
-	 * relocate exeception table
-	 */
-	ldr	r0, =_start
-	ldr	r1, =0x0
-	mov	r2, #16
-copyex:
-	subs	r2, r2, #1
-	ldr	r3, [r0], #4
-	str	r3, [r1], #4
-	bne	copyex
-
-	/*
-	 * we do sys-critical inits only at reboot,
-	 * not when booting from ram!
-	 */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-	bl      cpu_init_crit
-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
-
-#ifndef CONFIG_SKIP_RELOCATE_UBOOT
-relocate:				/* relocate U-Boot to RAM	    */
-	adr	r0, _start		/* r0 <- current position of code   */
-	ldr	r1, _TEXT_BASE		/* test if we run from flash or RAM */
-	cmp     r0, r1                  /* don't reloc during debug         */
-	beq     stack_setup
-
-	ldr	r2, _armboot_start
-	ldr	r3, _bss_start
-	sub	r2, r3, r2		/* r2 <- size of armboot            */
-	add	r2, r0, r2		/* r2 <- source end address         */
-
-copy_loop:
-	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
-	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end addreee [r2]    */
-	ble	copy_loop
-#endif	/* CONFIG_SKIP_RELOCATE_UBOOT */
-
-	/* Set up the stack						    */
-stack_setup:
-	ldr	r0, _TEXT_BASE		/* upper 128 KiB: relocated uboot   */
-	sub	r0, r0, #CFG_MALLOC_LEN	/* malloc area                      */
-	sub	r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo                        */
-#ifdef CONFIG_USE_IRQ
-	sub	r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
-#endif
-	sub	sp, r0, #12		/* leave 3 words for abort-stack    */
-
-clear_bss:
-	ldr	r0, _bss_start		/* find start of bss segment        */
-	ldr	r1, _bss_end		/* stop here                        */
-	mov 	r2, #0x00000000		/* clear                            */
-
-clbss_l:str	r2, [r0]		/* clear loop...                    */
-	add	r0, r0, #4
-	cmp	r0, r1
-	ble	clbss_l
-
-	ldr pc,_start_armboot
-
-_start_armboot: .word start_armboot
-
-/*
- *************************************************************************
- *
- * CPU_init_critical registers
- *
- *************************************************************************
- */
-
-cpu_init_crit:
-	/* do nothing for now */
-	mov	pc, lr
-
-
-/*
- *************************************************************************
- *
- * Interrupt handling
- *
- *************************************************************************
- */
-
-@
-@ IRQ stack frame.
-@
-#define S_FRAME_SIZE	72
-
-#define S_OLD_R0	68
-#define S_PSR		64
-#define S_PC		60
-#define S_LR		56
-#define S_SP		52
-
-#define S_IP		48
-#define S_FP		44
-#define S_R10		40
-#define S_R9		36
-#define S_R8		32
-#define S_R7		28
-#define S_R6		24
-#define S_R5		20
-#define S_R4		16
-#define S_R3		12
-#define S_R2		8
-#define S_R1		4
-#define S_R0		0
-
-#define MODE_SVC 0x13
-#define I_BIT	 0x80
-
-/*
- * use bad_save_user_regs for abort/prefetch/undef/swi ...
- * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
- */
-
-	.macro	bad_save_user_regs
-	sub	sp, sp, #S_FRAME_SIZE
-	stmia	sp, {r0 - r12}			@ Calling r0-r12
-	add     r8, sp, #S_PC
-
-	ldr	r2, _armboot_start
-	sub	r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
-	sub	r2, r2, #(CFG_GBL_DATA_SIZE+8)  @ set base 2 words into abort stack
-	ldmia	r2, {r2 - r4}                   @ get pc, cpsr, old_r0
-	add	r0, sp, #S_FRAME_SIZE		@ restore sp_SVC
-
-	add	r5, sp, #S_SP
-	mov	r1, lr
-	stmia	r5, {r0 - r4}                   @ save sp_SVC, lr_SVC, pc, cpsr, old_r
-	mov	r0, sp
-	.endm
-
-	.macro	irq_save_user_regs
-	sub	sp, sp, #S_FRAME_SIZE
-	stmia	sp, {r0 - r12}			@ Calling r0-r12
-	add     r8, sp, #S_PC
-	stmdb   r8, {sp, lr}^                   @ Calling SP, LR
-	str     lr, [r8, #0]                    @ Save calling PC
-	mrs     r6, spsr
-	str     r6, [r8, #4]                    @ Save CPSR
-	str     r0, [r8, #8]                    @ Save OLD_R0
-	mov	r0, sp
-	.endm
-
-	.macro	irq_restore_user_regs
-	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
-	mov	r0, r0
-	ldr	lr, [sp, #S_PC]			@ Get PC
-	add	sp, sp, #S_FRAME_SIZE
-	subs	pc, lr, #4			@ return & move spsr_svc into cpsr
-	.endm
-
-	.macro get_bad_stack
-	ldr	r13, _armboot_start		@ setup our mode stack
-	sub	r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
-	sub	r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
-
-	str	lr, [r13]			@ save caller lr / spsr
-	mrs	lr, spsr
-	str     lr, [r13, #4]
-
-	mov	r13, #MODE_SVC			@ prepare SVC-Mode
-	msr	spsr_c, r13
-	mov	lr, pc
-	movs	pc, lr
-	.endm
-
-	.macro get_irq_stack			@ setup IRQ stack
-	ldr	sp, IRQ_STACK_START
-	.endm
-
-	.macro get_fiq_stack			@ setup FIQ stack
-	ldr	sp, FIQ_STACK_START
-	.endm
-
-/*
- * exception handlers
- */
-	.align  5
-undefined_instruction:
-	get_bad_stack
-	bad_save_user_regs
-	bl 	do_undefined_instruction
-
-	.align	5
-software_interrupt:
-	get_bad_stack
-	bad_save_user_regs
-	bl 	do_software_interrupt
-
-	.align	5
-prefetch_abort:
-	get_bad_stack
-	bad_save_user_regs
-	bl 	do_prefetch_abort
-
-	.align	5
-data_abort:
-	get_bad_stack
-	bad_save_user_regs
-	bl 	do_data_abort
-
-	.align	5
-not_used:
-	get_bad_stack
-	bad_save_user_regs
-	bl 	do_not_used
-
-#ifdef CONFIG_USE_IRQ
-
-	.align	5
-irq:
-	get_irq_stack
-	irq_save_user_regs
-	bl 	do_irq
-	irq_restore_user_regs
-
-	.align	5
-fiq:
-	get_fiq_stack
-	/* someone ought to write a more effiction fiq_save_user_regs */
-	irq_save_user_regs
-	bl 	do_fiq
-	irq_restore_user_regs
-
-#else
-
-	.align	5
-irq:
-	get_bad_stack
-	bad_save_user_regs
-	bl 	do_irq
-
-	.align	5
-fiq:
-	get_bad_stack
-	bad_save_user_regs
-	bl 	do_fiq
-
-#endif
-
-	.align	5
-.globl reset_cpu
-reset_cpu:
-	mov     pc, r0
--- a/cpu/mpc5xxx/fec.c
+++ b/cpu/mpc5xxx/fec.c
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2003
+ * (C) Copyright 2003-2005
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * This file is based on mpc4200fec.c,
@@ -869,9 +869,9 @@ int mpc5xxx_fec_initialize(bd_t * bis)
 	fec->eth = (ethernet_regs *)MPC5XXX_FEC;
 	fec->tbdBase = (FEC_TBD *)FEC_BD_BASE;
 	fec->rbdBase = (FEC_RBD *)(FEC_BD_BASE + FEC_TBD_NUM * sizeof(FEC_TBD));
-#if defined(CONFIG_ICECUBE) || defined(CONFIG_PM520)   || \
-    defined(CONFIG_TOP5200) || defined(CONFIG_TQM5200) || \
-    defined(CONFIG_INKA4X0)
+#if defined(CONFIG_CANMB)   || defined(CONFIG_ICECUBE) || \
+    defined(CONFIG_INKA4X0) || defined(CONFIG_PM520)   || \
+    defined(CONFIG_TOP5200) || defined(CONFIG_TQM5200)
 # ifndef CONFIG_FEC_10MBIT
 	fec->xcv_type = MII100;
 # else
--- a/cpu/mpc8220/speed.c
+++ b/cpu/mpc8220/speed.c
@@ -74,7 +74,7 @@ int get_clocks (void)
 	gd->inp_clk = CFG_MPC8220_CLKIN;

 	/* Read XLB to PCI(INP) clock multiplier */
-	pci2bus = (*((volatile u32 *)PCI_REG_PCIGSCR) & 
+	pci2bus = (*((volatile u32 *)PCI_REG_PCIGSCR) &
 		PCI_REG_PCIGSCR_PCI2XLB_CLK_MASK)>>PCI_REG_PCIGSCR_PCI2XLB_CLK_BIT;

 	/* XLB bus clock */
--- a/cpu/mpc8220/start.S
+++ b/cpu/mpc8220/start.S
@@ -111,7 +111,7 @@ boot_warm:

 	/* MBAR is mirrored into the MBAR SPR */
 	mtspr	MBAR,r3
-	mtspr	SPRN_SPRG7W,r3	
+	mtspr	SPRN_SPRG7W,r3
 	lis	r4, CFG_DEFAULT_MBAR@h
 	stw	r3, 0(r4)
 #endif /* CFG_DEFAULT_MBAR */
--- a/cpu/mpc8220/uart.c
+++ b/cpu/mpc8220/uart.c
@@ -47,7 +47,7 @@ int psc_serial_init (void)
 	/* write to CSR: RX/TX baud rate from timers */
 	psc->sr_csr = 0xdd000000;

-	psc->mr1_2 = PSC_MR1_BITS_CHAR_8 | PSC_MR1_NO_PARITY | PSC_MR2_STOP_BITS_1; 
+	psc->mr1_2 = PSC_MR1_BITS_CHAR_8 | PSC_MR1_NO_PARITY | PSC_MR2_STOP_BITS_1;

 	/* Setting up BaudRate */
 	counter = ((gd->bus_clk / gd->baudrate)) >> 5;
--- a/cpu/mpc85xx/cpu.c
+++ b/cpu/mpc85xx/cpu.c
@@ -145,7 +145,7 @@ unsigned long get_tbclk (void)
 	sys_info_t  sys_info;

 	get_sys_info(&sys_info);
-	return ((sys_info.freqSystemBus + 3L) / 4L);
+	return ((sys_info.freqSystemBus + 7L) / 8L);
 }


--- a/cpu/mpc85xx/ether_fcc.c
+++ b/cpu/mpc85xx/ether_fcc.c
@@ -135,7 +135,7 @@ static RTXBD rtx __attribute__ ((aligned(8)));
 #error "rtx must be 64-bit aligned"
 #endif

-#define ET_DEBUG
+#undef ET_DEBUG

 static int fec_send(struct eth_device* dev, volatile void *packet, int length)
 {
@@ -157,7 +157,7 @@ static int fec_send(struct eth_device* dev, volatile void *packet, int length)
    rtx.txbd[txIdx].cbd_bufaddr = (uint)packet;
    rtx.txbd[txIdx].cbd_datlen = length;
    rtx.txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST | \
-			       BD_ENET_TX_TC );
+			       BD_ENET_TX_TC | BD_ENET_TX_PAD);

    for(i=0; rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) {
 	if (i >= TOUT_LOOP) {
@@ -414,7 +414,7 @@ static int fec_init(struct eth_device* dev, bd_t *bis)
 	immr->im_cpm.im_cpm_fcc3.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
    }

-    return 0;
+    return 1;
 }

 static void fec_halt(struct eth_device* dev)
--- a/cpu/mpc85xx/tsec.c
+++ b/cpu/mpc85xx/tsec.c
@@ -277,7 +277,7 @@ static int init_phy(struct eth_device *dev)
 	struct phy_info *curphy;

 	/* Assign a Physical address to the TBI */
-	
+
 	{
 		volatile tsec_t *regs = (volatile tsec_t *)(TSEC_BASE_ADDR);
 		regs->tbipa = TBIPA_VALUE;
@@ -809,33 +809,33 @@ struct phy_info phy_info_dm9161 = {

 uint mii_parse_lxt971_sr2(uint mii_reg, struct tsec_private *priv)
 {
-        unsigned int speed;
-        if (priv->link) {
-                speed = mii_reg & MIIM_LXT971_SR2_SPEED_MASK;
+	unsigned int speed;
+	if (priv->link) {
+		speed = mii_reg & MIIM_LXT971_SR2_SPEED_MASK;

-                switch (speed) {
-                case MIIM_LXT971_SR2_10HDX:
-                        priv->speed = 10;
-                        priv->duplexity = 0;
-                        break;
-                case MIIM_LXT971_SR2_10FDX:
-                        priv->speed = 10;
-                        priv->duplexity = 1;
-                        break;
-                case MIIM_LXT971_SR2_100HDX:
-                        priv->speed = 100;
-                        priv->duplexity = 0;
-                default:
-                        priv->speed = 100;
-                        priv->duplexity = 1;
-                        break;
-                }
-        } else {
-                priv->speed = 0;
-                priv->duplexity = 0;
-        }
+		switch (speed) {
+		case MIIM_LXT971_SR2_10HDX:
+			priv->speed = 10;
+			priv->duplexity = 0;
+			break;
+		case MIIM_LXT971_SR2_10FDX:
+			priv->speed = 10;
+			priv->duplexity = 1;
+			break;
+		case MIIM_LXT971_SR2_100HDX:
+			priv->speed = 100;
+			priv->duplexity = 0;
+		default:
+			priv->speed = 100;
+			priv->duplexity = 1;
+			break;
+		}
+	} else {
+		priv->speed = 0;
+		priv->duplexity = 0;
+	}

-        return 0;
+	return 0;
 }

 static struct phy_info phy_info_lxt971 = {
--- a/cpu/mpc8xx/cpu.c
+++ b/cpu/mpc8xx/cpu.c
@@ -463,6 +463,8 @@ void upmconfig (uint upm, uint * table, uint size)

 /* ------------------------------------------------------------------------- */

+#ifndef CONFIG_LWMON
+
 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
 	ulong msr, addr;
@@ -497,6 +499,32 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	return 1;
 }

+#else	/* CONFIG_LWMON */
+
+/*
+ * On the LWMON board, the MCLR reset input of the PIC's on the board
+ * uses a 47K/1n RC combination which has a 47us time  constant.  The
+ * low  signal on the HRESET pin of the CPU is only 512 clocks = 8 us
+ * and thus too short to reset the external hardware. So we  use  the
+ * watchdog to reset the board.
+ */
+int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	/* prevent triggering the watchdog */
+	disable_interrupts ();
+
+	/* make sure the watchdog is running */
+	reset_8xx_watchdog ((immap_t *) CFG_IMMR);
+
+	/* wait for watchdog reset */
+	while (1) {};
+
+	/* NOTREACHED */
+	return 1;
+}
+
+#endif	/* CONFIG_LWMON */
+
 /* ------------------------------------------------------------------------- */

 /*
@@ -558,6 +586,9 @@ void watchdog_reset (void)
 	if (re_enable)
 		enable_interrupts ();
 }
+#endif /* CONFIG_WATCHDOG */
+
+#if defined(CONFIG_WATCHDOG) || defined(CONFIG_LWMON)

 void reset_8xx_watchdog (volatile immap_t * immr)
 {
--- a/cpu/ppc4xx/405gp_pci.c
+++ b/cpu/ppc4xx/405gp_pci.c
@@ -98,6 +98,7 @@ void pci_405gp_init(struct pci_controller *hose)
 #if defined(CONFIG_CPCI405) || defined(CONFIG_PMC405)
 	unsigned long ptmla[2]    = {bd->bi_memstart, bd->bi_flashstart};
 	unsigned long ptmms[2]    = {~(bd->bi_memsize - 1) | 1, ~(bd->bi_flashsize - 1) | 1};
+	char *ptmla_str, *ptmms_str;
 #else
 	unsigned long ptmla[2]    = {CFG_PCI_PTM1LA, CFG_PCI_PTM2LA};
 	unsigned long ptmms[2]    = {CFG_PCI_PTM1MS, CFG_PCI_PTM2MS};
@@ -119,6 +120,22 @@ void pci_405gp_init(struct pci_controller *hose)
 #endif
 #endif

+#if defined(CONFIG_CPCI405) || defined(CONFIG_PMC405)
+	ptmla_str = getenv("ptm1la");
+	ptmms_str = getenv("ptm1ms");
+	if(NULL != ptmla_str && NULL != ptmms_str ) {
+	        ptmla[0] = simple_strtoul (ptmla_str, NULL, 16);
+		ptmms[0] = simple_strtoul (ptmms_str, NULL, 16);
+	}
+
+	ptmla_str = getenv("ptm2la");
+	ptmms_str = getenv("ptm2ms");
+	if(NULL != ptmla_str && NULL != ptmms_str ) {
+	        ptmla[1] = simple_strtoul (ptmla_str, NULL, 16);
+		ptmms[1] = simple_strtoul (ptmms_str, NULL, 16);
+	}
+#endif
+
 	/*
 	 * Register the hose
 	 */
--- a/cpu/ppc4xx/cpu.c
+++ b/cpu/ppc4xx/cpu.c
@@ -175,8 +175,11 @@ int checkcpu (void)
 	case PVR_440GX_RB:
 		puts("X Rev. B");
 		break;
+	case PVR_440GX_RC:
+		puts("X Rev. C");
+		break;
 	default:
-		printf ("UNKNOWN (PVR=%08x)", pvr);
+		printf (" UNKNOWN (PVR=%08x)", pvr);
 		break;
 	}
 #endif
--- a/cpu/ppc4xx/interrupts.c
+++ b/cpu/ppc4xx/interrupts.c
@@ -134,7 +134,7 @@ int interrupt_init_cpu (unsigned *decrementer_count)
 	mtspr( dec, 0 );		/* Prevent exception after TSR clear*/
 	mtspr( decar, 0 );		/* clear reload */
 	mtspr( tsr, 0x08000000 );	/* clear DEC status */
-	val = gd->bd->bi_intfreq/100;	/* 10 msec */
+	val = gd->bd->bi_intfreq/1000;	/* 1 msec */
 	mtspr( decar, val );		/* Set auto-reload value */
 	mtspr( dec, val );		/* Set inital val */
 #else
--- a/cpu/ppc4xx/spd_sdram.c
+++ b/cpu/ppc4xx/spd_sdram.c
@@ -1082,7 +1082,7 @@ void program_rtr (unsigned long* dimm_populated,
 	    case 0x00:
 		refresh_rate = 15625;
 		break;
-	    case 0x011:
+	    case 0x01:
 		refresh_rate = 15625/4;
 		break;
 	    case 0x02:
--- a/cpu/pxa/mmc.c
+++ b/cpu/pxa/mmc.c
@@ -72,13 +72,11 @@ mmc_cmd(ushort cmd, ushort argh, ushort argl, ushort cmdat)

 	status = MMC_STAT;
 	debug("MMC status %x\n", status);
-	if (status & MMC_STAT_TIME_OUT_RESPONSE)
-	{
+	if (status & MMC_STAT_TIME_OUT_RESPONSE) {
 		return 0;
 	}

-	switch (cmdat & 0x3)
-	{
+	switch (cmdat & 0x3) {
 		case MMC_CMDAT_R1:
 		case MMC_CMDAT_R3:
 			words = 3;
@@ -91,8 +89,7 @@ mmc_cmd(ushort cmd, ushort argh, ushort argl, ushort cmdat)
 		default:
 			return 0;
 	}
-	for (i = words-1; i >= 0; i--)
-	{
+	for (i = words-1; i >= 0; i--) {
 		ulong res_fifo = MMC_RES;
 		int offset = i << 1;

@@ -100,8 +97,7 @@ mmc_cmd(ushort cmd, ushort argh, ushort argl, ushort cmdat)
 		resp[offset+1] = ((uchar *)&res_fifo)[1];
 	}
 #ifdef MMC_DEBUG
-	for (i=0; i<words*2; i += 2)
-	{
+	for (i=0; i<words*2; i += 2) {
 		printf("MMC resp[%d] = %02x\n", i, resp[i]);
 		printf("MMC resp[%d] = %02x\n", i+1, resp[i+1]);
 	}
@@ -118,8 +114,7 @@ mmc_block_read(uchar *dst, ulong src, ulong len)
 	ushort argh, argl;
 	ulong status;

-	if (len == 0)
-	{
+	if (len == 0) {
 		return 0;
 	}

@@ -143,16 +138,21 @@ mmc_block_read(uchar *dst, ulong src, ulong len)


 	MMC_I_MASK = ~MMC_I_MASK_RXFIFO_RD_REQ;
-	while (len)
-	{
-		if (MMC_I_REG & MMC_I_REG_RXFIFO_RD_REQ)
-		{
+	while (len) {
+		if (MMC_I_REG & MMC_I_REG_RXFIFO_RD_REQ) {
+#ifdef CONFIG_PXA27X
+			int i;
+			for (i=min(len,32); i; i--) {
+				*dst++ = * ((volatile uchar *) &MMC_RXFIFO);
+				len--;
+			}
+#else
 			*dst++ = MMC_RXFIFO;
 			len--;
+#endif
 		}
 		status = MMC_STAT;
-		if (status & MMC_STAT_ERRORS)
-		{
+		if (status & MMC_STAT_ERRORS) {
 			printf("MMC_STAT error %lx\n", status);
 			return -1;
 		}
@@ -160,8 +160,7 @@ mmc_block_read(uchar *dst, ulong src, ulong len)
 	MMC_I_MASK = ~MMC_I_MASK_DATA_TRAN_DONE;
 	while (!(MMC_I_REG & MMC_I_REG_DATA_TRAN_DONE));
 	status = MMC_STAT;
-	if (status & MMC_STAT_ERRORS)
-	{
+	if (status & MMC_STAT_ERRORS) {
 		printf("MMC_STAT error %lx\n", status);
 		return -1;
 	}
@@ -177,8 +176,7 @@ mmc_block_write(ulong dst, uchar *src, int len)
 	ushort argh, argl;
 	ulong status;

-	if (len == 0)
-	{
+	if (len == 0) {
 		return 0;
 	}

@@ -200,25 +198,20 @@ mmc_block_write(ulong dst, uchar *src, int len)
 			MMC_CMDAT_R1|MMC_CMDAT_WRITE|MMC_CMDAT_BLOCK|MMC_CMDAT_DATA_EN);

 	MMC_I_MASK = ~MMC_I_MASK_TXFIFO_WR_REQ;
-	while (len)
-	{
-		if (MMC_I_REG & MMC_I_REG_TXFIFO_WR_REQ)
-		{
+	while (len) {
+		if (MMC_I_REG & MMC_I_REG_TXFIFO_WR_REQ) {
 			int i, bytes = min(32,len);

-			for (i=0; i<bytes; i++)
-			{
+			for (i=0; i<bytes; i++) {
 				MMC_TXFIFO = *src++;
 			}
-			if (bytes < 32)
-			{
+			if (bytes < 32) {
 				MMC_PRTBUF = MMC_PRTBUF_BUF_PART_FULL;
 			}
 			len -= bytes;
 		}
 		status = MMC_STAT;
-		if (status & MMC_STAT_ERRORS)
-		{
+		if (status & MMC_STAT_ERRORS) {
 			printf("MMC_STAT error %lx\n", status);
 			return -1;
 		}
@@ -228,8 +221,7 @@ mmc_block_write(ulong dst, uchar *src, int len)
 	MMC_I_MASK = ~MMC_I_MASK_PRG_DONE;
 	while (!(MMC_I_REG & MMC_I_REG_PRG_DONE));
 	status = MMC_STAT;
-	if (status & MMC_STAT_ERRORS)
-	{
+	if (status & MMC_STAT_ERRORS) {
 		printf("MMC_STAT error %lx\n", status);
 		return -1;
 	}
@@ -245,13 +237,11 @@ mmc_read(ulong src, uchar *dst, int size)
 	ulong end, part_start, part_end, part_len, aligned_start, aligned_end;
 	ulong mmc_block_size, mmc_block_address;

-	if (size == 0)
-	{
+	if (size == 0) {
 		return 0;
 	}

-	if (!mmc_ready)
-	{
+	if (!mmc_ready) {
 		printf("Please initial the MMC first\n");
 		return -1;
 	}
@@ -269,13 +259,11 @@ mmc_read(ulong src, uchar *dst, int size)
 	/* all block aligned accesses */
 	debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
 	src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
-	if (part_start)
-	{
+	if (part_start) {
 		part_len = mmc_block_size - part_start;
 		debug("ps src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
 		src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
-		if ((mmc_block_read(mmc_buf, aligned_start, mmc_block_size)) < 0)
-		{
+		if ((mmc_block_read(mmc_buf, aligned_start, mmc_block_size)) < 0) {
 			return -1;
 		}
 		memcpy(dst, mmc_buf+part_start, part_len);
@@ -284,23 +272,19 @@ mmc_read(ulong src, uchar *dst, int size)
 	}
 	debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
 	src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
-	for (; src < aligned_end; src += mmc_block_size, dst += mmc_block_size)
-	{
+	for (; src < aligned_end; src += mmc_block_size, dst += mmc_block_size) {
 		debug("al src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
 		src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
-		if ((mmc_block_read((uchar *)(dst), src, mmc_block_size)) < 0)
-		{
+		if ((mmc_block_read((uchar *)(dst), src, mmc_block_size)) < 0) {
 			return -1;
 		}
 	}
 	debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
 	src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
-	if (part_end && src < end)
-	{
+	if (part_end && src < end) {
 		debug("pe src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
 		src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
-		if ((mmc_block_read(mmc_buf, aligned_end, mmc_block_size)) < 0)
-		{
+		if ((mmc_block_read(mmc_buf, aligned_end, mmc_block_size)) < 0) {
 			return -1;
 		}
 		memcpy(dst, mmc_buf, part_end);
@@ -316,13 +300,11 @@ mmc_write(uchar *src, ulong dst, int size)
 	ulong end, part_start, part_end, part_len, aligned_start, aligned_end;
 	ulong mmc_block_size, mmc_block_address;

-	if (size == 0)
-	{
+	if (size == 0) {
 		return 0;
 	}

-	if (!mmc_ready)
-	{
+	if (!mmc_ready) {
 		printf("Please initial the MMC first\n");
 		return -1;
 	}
@@ -340,18 +322,15 @@ mmc_write(uchar *src, ulong dst, int size)
 	/* all block aligned accesses */
 	debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
 	src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
-	if (part_start)
-	{
+	if (part_start) {
 		part_len = mmc_block_size - part_start;
 		debug("ps src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
 		(ulong)src, dst, end, part_start, part_end, aligned_start, aligned_end);
-		if ((mmc_block_read(mmc_buf, aligned_start, mmc_block_size)) < 0)
-		{
+		if ((mmc_block_read(mmc_buf, aligned_start, mmc_block_size)) < 0) {
 			return -1;
 		}
 		memcpy(mmc_buf+part_start, src, part_len);
-		if ((mmc_block_write(aligned_start, mmc_buf, mmc_block_size)) < 0)
-		{
+		if ((mmc_block_write(aligned_start, mmc_buf, mmc_block_size)) < 0) {
 			return -1;
 		}
 		dst += part_len;
@@ -359,28 +338,23 @@ mmc_write(uchar *src, ulong dst, int size)
 	}
 	debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
 	src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
-	for (; dst < aligned_end; src += mmc_block_size, dst += mmc_block_size)
-	{
+	for (; dst < aligned_end; src += mmc_block_size, dst += mmc_block_size) {
 		debug("al src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
 		src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
-		if ((mmc_block_write(dst, (uchar *)src, mmc_block_size)) < 0)
-		{
+		if ((mmc_block_write(dst, (uchar *)src, mmc_block_size)) < 0) {
 			return -1;
 		}
 	}
 	debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
 	src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
-	if (part_end && dst < end)
-	{
+	if (part_end && dst < end) {
 		debug("pe src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
 		src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
-		if ((mmc_block_read(mmc_buf, aligned_end, mmc_block_size)) < 0)
-		{
+		if ((mmc_block_read(mmc_buf, aligned_end, mmc_block_size)) < 0) {
 			return -1;
 		}
 		memcpy(mmc_buf, src, part_end);
-		if ((mmc_block_write(aligned_end, mmc_buf, mmc_block_size)) < 0)
-		{
+		if ((mmc_block_write(aligned_end, mmc_buf, mmc_block_size)) < 0) {
 			return -1;
 		}
 	}
@@ -412,6 +386,11 @@ mmc_init(int verbose)
 	set_GPIO_mode( GPIO8_MMCCS0_MD );
 #endif
 	CKEN |= CKEN12_MMC; /* enable MMC unit clock */
+#if defined(CONFIG_ADSVIX)
+	/* turn on the power */
+	GPCR(114) = GPIO_bit(114);
+	udelay(1000);
+#endif

 	mmc_csd.c_size = 0;

@@ -423,21 +402,22 @@ mmc_init(int verbose)
 	retries = 10;
 	resp = mmc_cmd(0, 0, 0, 0);
 	resp = mmc_cmd(1, 0x00ff, 0xc000, MMC_CMDAT_INIT|MMC_CMDAT_BUSY|MMC_CMDAT_R3);
-	while (retries-- && resp && !(resp[4] & 0x80))
-	{
+	while (retries-- && resp && !(resp[4] & 0x80)) {
 		debug("resp %x %x\n", resp[0], resp[1]);
+#ifdef CONFIG_PXA27X
+		udelay(10000);
+#else
 		udelay(50);
+#endif
 		resp = mmc_cmd(1, 0x00ff, 0xff00, MMC_CMDAT_BUSY|MMC_CMDAT_R3);
 	}

 	/* try to get card id */
 	resp = mmc_cmd(2, 0, 0, MMC_CMDAT_R2);
-	if (resp)
-	{
+	if (resp) {
 		/* TODO configure mmc driver depending on card attributes */
 		mmc_cid_t *cid = (mmc_cid_t *)resp;
-		if (verbose)
-		{
+		if (verbose) {
 			printf("MMC found. Card desciption is:\n");
 			printf("Manufacturer ID = %02x%02x%02x\n",
 							cid->id[0], cid->id[1], cid->id[2]);
@@ -451,6 +431,7 @@ mmc_init(int verbose)
 		}
 		/* fill in device description */
 		mmc_dev.if_type = IF_TYPE_MMC;
+		mmc_dev.part_type = PART_TYPE_DOS;
 		mmc_dev.dev = 0;
 		mmc_dev.lun = 0;
 		mmc_dev.type = 0;
@@ -468,8 +449,7 @@ mmc_init(int verbose)
 		/* MMC exists, get CSD too */
 		resp = mmc_cmd(MMC_CMD_SET_RCA, MMC_DEFAULT_RCA, 0, MMC_CMDAT_R1);
 		resp = mmc_cmd(MMC_CMD_SEND_CSD, MMC_DEFAULT_RCA, 0, MMC_CMDAT_R2);
-		if (resp)
-		{
+		if (resp) {
 			mmc_csd_t *csd = (mmc_csd_t *)resp;
 			memcpy(&mmc_csd, csd, sizeof(csd));
 			rc = 0;
@@ -478,7 +458,11 @@ mmc_init(int verbose)
 		}
 	}

+#ifdef CONFIG_PXA27X
+	MMC_CLKRT = 1;	/* 10 MHz - see Intel errata */
+#else
 	MMC_CLKRT = 0;	/* 20 MHz */
+#endif
 	resp = mmc_cmd(7, MMC_DEFAULT_RCA, 0, MMC_CMDAT_R1);

 	fat_register_device(&mmc_dev,1); /* partitions start counting with 1 */
@@ -496,11 +480,10 @@ int
 mmc2info(ulong addr)
 {
 	/* FIXME hard codes to 32 MB device */
-	if (addr >= CFG_MMC_BASE && addr < CFG_MMC_BASE + 0x02000000)
-	{
+	if (addr >= CFG_MMC_BASE && addr < CFG_MMC_BASE + 0x02000000) {
 		return 1;
 	}
 	return 0;
 }

-#endif
+#endif	/* CONFIG_MMC */
--- a/doc/README.ocotea-PIBS-to-U-Boot
+++ b/doc/README.ocotea-PIBS-to-U-Boot
@@ -0,0 +1,99 @@
+------------------------------------------
+Installation of U-Boot using PIBS firmware
+------------------------------------------
+
+This document describes how to install U-Boot on the Ocotea PPC440GX
+Evaluation Board. We do not erase the PIBS firmware but install U-Boot in the
+soldered FLASH. After this you should be able to switch between PIBS and
+U-Boot via the switch U46 SW1. Please check that SW1 is off (= open) before
+continuing.
+
+Connect to the serial port 0 (J11 lower) of the Ocotea board using the cu
+program. See the hints for configuring cu above. Make sure you can
+communicate with the PIBS firmware: reset the board and hit ENTER a couple of
+times until you see the PIBS prompt (PIBS $). Then proceed as follows:
+
+
+Read MAC Addresses from PIBS
+----------------------------
+
+To read the configured MAC addresses available on your Ocotea board please use
+the following commands:
+
+PIBS $ echo $hwdaddr0
+000173017FE3
+PIBS $ echo $hwdaddr1
+000173017FE4
+PIBS $ echo $hwdaddr2
+000173017FE1
+PIBS $ echo $hwdaddr3
+000173017FE2
+
+In U-Boot this is stored in the following environment variables:
+
+* Ethernet Address 0: ethaddr = 000173017FE3 (==> 00:01:73:01:7F:E3)
+* Ethernet Address 1: eth1addr = 000173017FE4 (==> 00:01:73:01:7F:E4)
+* Ethernet Address 2: eth2addr = 000173017FE1 (==> 00:01:73:01:7F:E1)
+* Ethernet Address 3: eth3addr = 000173017FE2 (==> 00:01:73:01:7F:E2)
+
+
+Configure the network interface (ent0 == emac0)
+-----------------------------------------------
+
+To download the U-Boot image we need to configure the ethernet interface with
+the following commands:
+
+PIBS $ ifconfig ent0 192.168.160.142 netmask 255.255.0.0 up
+PIBS $ set ipdstaddr0=192.168.1.1
+status: writing PIBS variable value to FLASH
+PIBS $ set bootfilename=/tftpboot/ocotea/u-boot.bin
+status: writing PIBS variable value to FLASH
+
+Please insert correct parameters for your configuration (ip-addresses and
+file-location).
+
+
+Program U-Boot into soldered User-FLASH
+---------------------------------------
+
+Please make sure to use a newer version of U-Boot (at least 1.1.3), since
+older versions don't support running from user-FLASH.
+
+To program U-Boot into the soldered user-FLASH use the following command:
+
+PIBS $ storefile bin eth 0xffbc0000
+
+This commands loads the file vis ethernet into ram and copies it into the
+user-FLASH.
+
+
+Switch to U-Boot
+----------------
+
+Now you can turn your board off and switch SW1 (U46) to on (= closed). After
+powering the board you should see the following message:
+
+U-Boot 1.1.3 (Apr  5 2005 - 22:59:57)
+
+IBM PowerPC 440 GX Rev. C
+Board: IBM 440GX Evaluation Board
+	VCO: 1066 MHz
+	CPU: 533 MHz
+	PLB: 152 MHz
+	OPB: 76 MHz
+	EPB: 76 MHz
+I2C:   ready
+DRAM:  256 MB
+FLASH:	5 MB
+PCI:   Bus Dev VenId DevId Class Int
+In:    serial
+Out:   serial
+Err:   serial
+KGDB:  kgdb ready
+ready
+Net:   ppc_440x_eth0, ppc_440x_eth1, ppc_440x_eth2, ppc_440x_eth3
+BEDBUG:ready
+=>
+
+
+April 06 2005, Stefan Roese <sr@denx.de>
--- a/drivers/cfi_flash.c
+++ b/drivers/cfi_flash.c
@@ -48,6 +48,7 @@
 #include <asm/processor.h>
 #include <asm/byteorder.h>
 #include <linux/byteorder/swab.h>
+#include <environment.h>
 #ifdef	CFG_FLASH_CFI_DRIVER

 /*
--- a/drivers/netconsole.c
+++ b/drivers/netconsole.c
@@ -153,11 +153,12 @@ int nc_start (void)
 	nc_port = 6666;		/* default port */

 	if (getenv ("ncip")) {
+		char *p;
+
 		nc_ip = getenv_IPaddr ("ncip");
 		if (!nc_ip)
 			return -1;	/* ncip is 0.0.0.0 */
-		char *p = strchr (getenv ("ncip"), ':');
-		if (p)
+		if ((p = strchr (getenv ("ncip"), ':')) != NULL)
 			nc_port = simple_strtoul (p + 1, NULL, 10);
 	} else
 		nc_ip = ~0;		/* ncip is not set */
@@ -188,13 +189,13 @@ void nc_putc (char c)

 void nc_puts (const char *s)
 {
+	int len;
+
 	if (output_recursion)
 		return;
 	output_recursion = 1;

-	int len = strlen (s);
-
-	if (len > 512)
+	if ((len = strlen (s)) > 512)
 		len = 512;

 	nc_send_packet (s, len);
@@ -204,6 +205,8 @@ void nc_puts (const char *s)

 int nc_getc (void)
 {
+	uchar c;
+
 	input_recursion = 1;

 	net_timeout = 0;	/* no timeout */
@@ -212,8 +215,8 @@ int nc_getc (void)

 	input_recursion = 0;

-	uchar c = input_buffer[input_offset];
-	input_offset++;
+	c = input_buffer[input_offset++];
+
 	if (input_offset >= sizeof input_buffer)
 		input_offset -= sizeof input_buffer;
 	input_size--;
--- a/examples/Makefile
+++ b/examples/Makefile
@@ -58,6 +58,11 @@ include $(TOPDIR)/config.mk
 SREC	= hello_world.srec
 BIN	= hello_world.bin hello_world

+ifeq ($(ARCH),ppc)
+SREC	= test_burst.srec
+BIN	= test_burst.bin test_burst
+endif
+
 ifeq ($(ARCH),i386)
 SREC   += 82559_eeprom.srec
 BIN    += 82559_eeprom.bin 82559_eeprom
@@ -96,6 +101,7 @@ LIB	= libstubs.a
 LIBAOBJS=
 ifeq ($(ARCH),ppc)
 LIBAOBJS+= $(ARCH)_longjmp.o $(ARCH)_setjmp.o
+LIBAOBJS+= test_burst_lib.o
 endif
 LIBCOBJS= stubs.o
 LIBOBJS	= $(LIBAOBJS) $(LIBCOBJS)
--- a/examples/test_burst.c
+++ b/examples/test_burst.c
@@ -0,0 +1,275 @@
+/*
+ * (C) Copyright 2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * The test exercises SDRAM accesses in burst mode
+ */
+
+#include <common.h>
+#include <exports.h>
+
+#include <commproc.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+
+#include <serial.h>
+#include <watchdog.h>
+
+#include "test_burst.h"
+
+/* 8 MB test region of physical RAM */
+#define TEST_PADDR	0x00800000
+/* The uncached virtual region */
+#define TEST_VADDR_NC	0x00800000
+/* The cached virtual region */
+#define TEST_VADDR_C	0x01000000
+/* When an error is detected, the address where the error has been found,
+   and also the current and the expected data will be written to
+   the following flash address
+*/
+#define TEST_FLASH_ADDR	0x40100000
+
+static void test_prepare (void);
+static int test_burst_start (unsigned long size, unsigned long pattern);
+static void test_map_8M (unsigned long paddr, unsigned long vaddr, int cached);
+static int test_mmu_is_on(void);
+static void test_desc(unsigned long size);
+static void test_error(char * step, volatile void * addr, unsigned long val, unsigned long pattern);
+static void signal_start(void);
+static void signal_error(void);
+static void test_usage(void);
+
+static unsigned long test_pattern [] = {
+	0x00000000,
+	0xffffffff,
+	0x55555555,
+	0xaaaaaaaa,
+};
+
+
+int test_burst (int argc, char *argv[])
+{
+	unsigned long size = CACHE_LINE_SIZE;
+	int res;
+	int i;
+
+	if (argc == 2) {
+		char * d;
+		for (size = 0, d = argv[1]; *d >= '0' && *d <= '9'; d++) {
+			size *= 10;
+			size += *d - '0';
+		}
+		if (size == 0 || *d) {
+			test_usage();
+			return 1;
+		}
+	} else if (argc > 2) {
+		test_usage();
+		return 1;
+	}
+
+	size +=  (CACHE_LINE_SIZE - 1);
+	size &= ~(CACHE_LINE_SIZE - 1);
+
+	if (!test_mmu_is_on()) {
+		test_prepare();
+	}
+
+	test_desc(size);
+
+	for (i = 0; i < sizeof(test_pattern) / sizeof(test_pattern[0]); i++) {
+		res = test_burst_start(size, test_pattern[i]);
+		if (res != 0) {
+			goto Done;
+		}
+	}
+Done:
+	return res;
+}
+
+static void test_prepare (void)
+{
+	volatile immap_t *immr = (immap_t *)  CFG_IMMR;
+
+	printf ("\n");
+
+	caches_init();
+	disable_interrupts();
+	mmu_init();
+
+	printf ("Interrupts are disabled\n");
+	printf ("I-Cache is ON\n");
+	printf ("D-Cache is ON\n");
+	printf ("MMU is ON\n");
+
+	printf ("\n");
+
+	test_map_8M (TEST_PADDR, TEST_VADDR_NC, 0);
+	test_map_8M (TEST_PADDR, TEST_VADDR_C,  1);
+
+	test_map_8M (TEST_FLASH_ADDR & 0xFF800000, TEST_FLASH_ADDR & 0xFF800000, 0);
+
+	/* Configure PD.8 and PD.9 as general purpose output */
+	immr->im_ioport.iop_pdpar &= ~0x00C0;
+	immr->im_ioport.iop_pddir |=  0x00C0;
+}
+
+static int test_burst_start (unsigned long size, unsigned long pattern)
+{
+	volatile unsigned long * vaddr_c = (unsigned long *)TEST_VADDR_C;
+	volatile unsigned long * vaddr_nc = (unsigned long *)TEST_VADDR_NC;
+	int i, n;
+	int res = 1;
+
+	printf ("Test pattern %08x ...", pattern);
+
+	n = size / 4;
+
+	for (i = 0; i < n; i ++) {
+		vaddr_c [i] = pattern;
+	}
+	signal_start();
+	flush_dcache_range((unsigned long)vaddr_c, (unsigned long)(vaddr_c + n) - 1);
+
+	for (i = 0; i < n; i ++) {
+		register unsigned long tmp = vaddr_nc [i];
+		if (tmp != pattern) {
+			test_error("2a", vaddr_nc + i, tmp, pattern);
+			goto Done;
+		}
+	}
+
+	for (i = 0; i < n; i ++) {
+		register unsigned long tmp = vaddr_c [i];
+		if (tmp != pattern) {
+			test_error("2b", vaddr_c + i, tmp, pattern);
+			goto Done;
+		}
+	}
+
+	for (i = 0; i < n; i ++) {
+		vaddr_nc [i] = pattern;
+	}
+
+	for (i = 0; i < n; i ++) {
+		register unsigned long tmp = vaddr_nc [i];
+		if (tmp != pattern) {
+			test_error("3a", vaddr_nc + i, tmp, pattern);
+			goto Done;
+		}
+	}
+
+	signal_start();
+	for (i = 0; i < n; i ++) {
+		register unsigned long tmp = vaddr_c [i];
+		if (tmp != pattern) {
+			test_error("3b", vaddr_c + i, tmp, pattern);
+			goto Done;
+		}
+	}
+
+	res = 0;
+Done:
+	printf(" %s\n", res == 0 ? "OK" : "");
+
+	return res;
+}
+
+static void test_map_8M (unsigned long paddr, unsigned long vaddr, int cached)
+{
+	mtspr (MD_EPN, (vaddr & 0xFFFFFC00) | MI_EVALID);
+	mtspr (MD_TWC, MI_PS8MEG | MI_SVALID);
+	mtspr (MD_RPN, (paddr & 0xFFFFF000) | MI_BOOTINIT | (cached ? 0 : 2));
+	mtspr (MD_AP, MI_Kp);
+}
+
+static int test_mmu_is_on(void)
+{
+	unsigned long msr;
+
+	asm volatile("mfmsr %0" : "=r" (msr) :);
+
+	return msr & MSR_DR;
+}
+
+static void test_desc(unsigned long size)
+{
+	printf(
+	"The following tests will be conducted:\n"
+	"1)  Map %d-byte region of physical RAM at 0x%08x\n"
+	"    into two virtual regions:\n"
+	"    one cached at 0x%08x and\n"
+	"    the the other uncached at 0x%08x.\n",
+	size, TEST_PADDR, TEST_VADDR_NC, TEST_VADDR_C);
+
+	puts(
+	"2)  Fill the cached region with a pattern, and flush the cache\n"
+	"2a) Check the uncached region to match the pattern\n"
+	"2b) Check the cached region to match the pattern\n"
+	"3)  Fill the uncached region with a pattern\n"
+	"3a) Check the cached region to match the pattern\n"
+	"3b) Check the uncached region to match the pattern\n"
+	"2b) Change the patterns and go to step 2\n"
+	"\n"
+	);
+}
+
+static void test_error(
+	char * step, volatile void * addr, unsigned long val, unsigned long pattern)
+{
+	volatile unsigned long * p = (void *)TEST_FLASH_ADDR;
+
+	signal_error();
+
+	p[0] = (unsigned long)addr;
+	p[1] = val;
+	p[2] = pattern;
+
+	printf ("\nError at step %s, addr %08x: read %08x, pattern %08x",
+		step, addr, val, pattern);
+}
+
+static void signal_start(void)
+{
+	volatile immap_t *immr = (immap_t *)  CFG_IMMR;
+
+	if (immr->im_ioport.iop_pddat & 0x0080) {
+		immr->im_ioport.iop_pddat &= ~0x0080;
+	} else {
+		immr->im_ioport.iop_pddat |= 0x0080;
+	}
+}
+
+static void signal_error(void)
+{
+	volatile immap_t *immr = (immap_t *)  CFG_IMMR;
+
+	if (immr->im_ioport.iop_pddat & 0x0040) {
+		immr->im_ioport.iop_pddat &= ~0x0040;
+	} else {
+		immr->im_ioport.iop_pddat |= 0x0040;
+	}
+}
+
+static void test_usage(void)
+{
+	printf("Usage: go 0x40004 [size]\n");
+}
--- a/examples/test_burst.h
+++ b/examples/test_burst.h
@@ -0,0 +1,38 @@
+/*
+ * (C) Copyright 2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _TEST_BURST_H
+#define _TEST_BURST_H
+
+/* Cache line size */
+#define CACHE_LINE_SIZE		16
+/* Binary logarithm of the cache line size */
+#define LG_CACHE_LINE_SIZE	4
+
+#ifndef __ASSEMBLY__
+extern void mmu_init(void);
+extern void caches_init(void);
+extern void flush_dcache_range(unsigned long start, unsigned long stop);
+#endif
+
+#endif /* _TEST_BURST_H */
--- a/examples/test_burst_lib.S
+++ b/examples/test_burst_lib.S
@@ -0,0 +1,170 @@
+/*
+ * (C) Copyright 2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include "test_burst.h"
+
+	.text
+/*
+ *	void mmu_init(void);
+ *
+ *	This function turns the MMU on
+ *
+ *	Three 8 MByte regions are mapped 1:1, uncached
+ *	- SDRAM lower 8 MByte
+ *	- SDRAM higher 8 MByte
+ *	- IMMR
+ */
+	.global mmu_init
+mmu_init:
+	tlbia			/* Invalidate all TLB entries */
+	li	r8, 0
+	mtspr	MI_CTR, r8	/* Set instruction control to zero */
+	lis	r8, MD_RESETVAL@h
+	mtspr	MD_CTR, r8	/* Set data TLB control */
+
+	/* Now map the lower 8 Meg into the TLBs.  For this quick hack,
+	 * we can load the instruction and data TLB registers with the
+	 * same values.
+	 */
+	li	r8, MI_EVALID		/* Create EPN for address 0 */
+	mtspr	MI_EPN, r8
+	mtspr	MD_EPN, r8
+	li	r8, MI_PS8MEG		/* Set 8M byte page */
+	ori	r8, r8, MI_SVALID	/* Make it valid */
+	mtspr	MI_TWC, r8
+	mtspr	MD_TWC, r8
+	li	r8, MI_BOOTINIT|0x2	/* Create RPN for address 0 */
+	mtspr	MI_RPN, r8		/* Store TLB entry */
+	mtspr	MD_RPN, r8
+	lis	r8, MI_Kp@h		/* Set the protection mode */
+	mtspr	MI_AP, r8
+	mtspr	MD_AP, r8
+
+	/* Now map the higher 8 Meg into the TLBs.  For this quick hack,
+	 * we can load the instruction and data TLB registers with the
+	 * same values.
+	 */
+	lwz	r9,20(r29)		/* gd->ram_size */
+	addis	r9,r9,-0x80
+
+	mr	r8, r9			/* Higher 8 Meg in SDRAM */
+	ori	r8, r8, MI_EVALID	/* Mark page valid */
+	mtspr	MI_EPN, r8
+	mtspr	MD_EPN, r8
+	li	r8, MI_PS8MEG		/* Set 8M byte page */
+	ori	r8, r8, MI_SVALID	/* Make it valid */
+	mtspr	MI_TWC, r8
+	mtspr	MD_TWC, r8
+	mr	r8, r9
+	ori	r8, r8, MI_BOOTINIT|0x2
+	mtspr	MI_RPN, r8		/* Store TLB entry */
+	mtspr	MD_RPN, r8
+	lis	r8, MI_Kp@h		/* Set the protection mode */
+	mtspr	MI_AP, r8
+	mtspr	MD_AP, r8
+
+	/* Map another 8 MByte at the IMMR to get the processor
+	 * internal registers (among other things).
+	 */
+	mfspr	r9, 638			/* Get current IMMR */
+	andis.	r9, r9, 0xff80		/* Get 8Mbyte boundary */
+
+	mr	r8, r9			/* Create vaddr for TLB */
+	ori	r8, r8, MD_EVALID	/* Mark it valid */
+	mtspr	MD_EPN, r8
+	li	r8, MD_PS8MEG		/* Set 8M byte page */
+	ori	r8, r8, MD_SVALID	/* Make it valid */
+	mtspr	MD_TWC, r8
+	mr	r8, r9			/* Create paddr for TLB */
+	ori	r8, r8, MI_BOOTINIT|0x2 /* Inhibit cache -- Cort */
+	mtspr	MD_RPN, r8
+
+	/* We now have the lower and higher 8 Meg mapped into TLB entries,
+	 * and the caches ready to work.
+	 */
+	mfmsr	r0
+	ori	r0,r0,MSR_DR|MSR_IR
+	mtspr	SRR1,r0
+	mflr	r0
+	mtspr	SRR0,r0
+	SYNC
+	rfi	/* enables MMU */
+
+/*
+ *	void caches_init(void);
+ */
+	.globl	caches_init
+caches_init:
+	sync
+
+	mfspr	r3, IC_CST		/* Clear error bits */
+	mfspr	r3, DC_CST
+
+	lis	r3, IDC_UNALL@h		/* Unlock all */
+	mtspr	IC_CST, r3
+	mtspr	DC_CST, r3
+
+	lis	r3, IDC_INVALL@h	/* Invalidate all */
+	mtspr	IC_CST, r3
+	mtspr	DC_CST, r3
+
+	lis	r3, IDC_ENABLE@h	/* Enable all */
+	mtspr	IC_CST, r3
+	mtspr	DC_CST, r3
+
+	blr
+
+/*
+ *	void flush_dcache_range(unsigned long start, unsigned long stop);
+ */
+	.global flush_dcache_range
+flush_dcache_range:
+	li	r5,CACHE_LINE_SIZE-1
+	andc	r3,r3,r5
+	subf	r4,r3,r4
+	add	r4,r4,r5
+	srwi.	r4,r4,LG_CACHE_LINE_SIZE
+	beqlr
+	mtctr	r4
+
+1:	dcbf	0,r3
+	addi	r3,r3,CACHE_LINE_SIZE
+	bdnz	1b
+	sync				/* wait for dcbf's to get to ram */
+	blr
+
+/*
+ *	void disable_interrupts(void);
+ */
+	.global disable_interrupts
+disable_interrupts:
+	mfmsr	r0
+	rlwinm	r0,r0,0,17,15
+	mtmsr	r0
+	blr
--- a/fs/jffs2/Makefile
+++ b/fs/jffs2/Makefile
@@ -27,6 +27,7 @@ LIB	= libjffs2.a

 AOBJS	=
 COBJS	= jffs2_1pass.o compr_rtime.o compr_rubin.o compr_zlib.o mini_inflate.o
+COBJS	+= compr_lzo.o compr_lzari.o
 OBJS	= $(AOBJS) $(COBJS)

 #CPPFLAGS +=
--- a/fs/jffs2/compr_lzari.c
+++ b/fs/jffs2/compr_lzari.c
@@ -0,0 +1,262 @@
+/*
+ * JFFS2 -- Journalling Flash File System, Version 2.
+ *
+ * Copyright (C) 2004 Patrik Kluba,
+ *                    University of Szeged, Hungary
+ *
+ * For licensing information, see the file 'LICENCE' in the
+ * jffs2 directory.
+ *
+ * $Id: compr_lzari.c,v 1.3 2004/06/23 16:34:39 havasi Exp $
+ *
+ */
+
+/*
+   Lempel-Ziv-Arithmetic coding compression module for jffs2
+   Based on the LZARI source included in LDS (lossless datacompression sources)
+*/
+
+/* -*- Mode: C; indent-tabs-mode: t; c-basic-offset: 4; tab-width: 4 -*- */
+
+/*
+Original copyright follows:
+
+**************************************************************
+	LZARI.C -- A Data Compression Program
+	(tab = 4 spaces)
+**************************************************************
+	4/7/1989 Haruhiko Okumura
+	Use, distribute, and modify this program freely.
+	Please send me your improved versions.
+		PC-VAN		SCIENCE
+		NIFTY-Serve	PAF01022
+		CompuServe	74050,1022
+**************************************************************
+
+LZARI.C (c)1989 by Haruyasu Yoshizaki, Haruhiko Okumura, and Kenji Rikitake.
+All rights reserved. Permission granted for non-commercial use.
+
+*/
+
+/*
+
+	2004-02-18  pajko <pajko(AT)halom(DOT)u-szeged(DOT)hu>
+				Removed unused variables and fixed no return value
+
+	2004-02-16  pajko <pajko(AT)halom(DOT)u-szeged(DOT)hu>
+				Initial release
+
+*/
+
+
+#include <config.h>
+#if ((CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CONFIG_JFFS2_LZO_LZARI))
+
+#include <linux/stddef.h>
+#include <jffs2/jffs2.h>
+
+
+#define N			4096	/* size of ring buffer */
+#define F			60	/* upper limit for match_length */
+#define THRESHOLD		2	/* encode string into position and length
+					   if match_length is greater than this */
+#define NIL			N	/* index for root of binary search trees */
+
+static unsigned char
+		text_buf[N + F - 1];	/* ring buffer of size N,
+			with extra F-1 bytes to facilitate string comparison */
+
+/********** Arithmetic Compression **********/
+
+/*  If you are not familiar with arithmetic compression, you should read
+		I. E. Witten, R. M. Neal, and J. G. Cleary,
+			Communications of the ACM, Vol. 30, pp. 520-540 (1987),
+	from which much have been borrowed.  */
+
+#define M   15
+
+/*	Q1 (= 2 to the M) must be sufficiently large, but not so
+	large as the unsigned long 4 * Q1 * (Q1 - 1) overflows.  */
+
+#define Q1  (1UL << M)
+#define Q2  (2 * Q1)
+#define Q3  (3 * Q1)
+#define Q4  (4 * Q1)
+#define MAX_CUM (Q1 - 1)
+
+#define N_CHAR  (256 - THRESHOLD + F)
+	/* character code = 0, 1, ..., N_CHAR - 1 */
+
+static unsigned long char_to_sym[N_CHAR], sym_to_char[N_CHAR + 1];
+static unsigned long
+	sym_freq[N_CHAR + 1],  /* frequency for symbols */
+	sym_cum[N_CHAR + 1],   /* cumulative freq for symbols */
+	position_cum[N + 1];   /* cumulative freq for positions */
+
+static void StartModel(void)  /* Initialize model */
+{
+	unsigned long ch, sym, i;
+
+	sym_cum[N_CHAR] = 0;
+	for (sym = N_CHAR; sym >= 1; sym--) {
+		ch = sym - 1;
+		char_to_sym[ch] = sym;  sym_to_char[sym] = ch;
+		sym_freq[sym] = 1;
+		sym_cum[sym - 1] = sym_cum[sym] + sym_freq[sym];
+	}
+	sym_freq[0] = 0;  /* sentinel (!= sym_freq[1]) */
+	position_cum[N] = 0;
+	for (i = N; i >= 1; i--)
+		position_cum[i - 1] = position_cum[i] + 10000 / (i + 200);
+			/* empirical distribution function (quite tentative) */
+			/* Please devise a better mechanism! */
+}
+
+static void UpdateModel(unsigned long sym)
+{
+	unsigned long c, ch_i, ch_sym;
+	unsigned long i;
+	if (sym_cum[0] >= MAX_CUM) {
+		c = 0;
+		for (i = N_CHAR; i > 0; i--) {
+			sym_cum[i] = c;
+			c += (sym_freq[i] = (sym_freq[i] + 1) >> 1);
+		}
+		sym_cum[0] = c;
+	}
+	for (i = sym; sym_freq[i] == sym_freq[i - 1]; i--) ;
+	if (i < sym) {
+		ch_i = sym_to_char[i];    ch_sym = sym_to_char[sym];
+		sym_to_char[i] = ch_sym;  sym_to_char[sym] = ch_i;
+		char_to_sym[ch_i] = sym;  char_to_sym[ch_sym] = i;
+	}
+	sym_freq[i]++;
+	while (--i > 0) sym_cum[i]++;
+	sym_cum[0]++;
+}
+
+static unsigned long BinarySearchSym(unsigned long x)
+	/* 1      if x >= sym_cum[1],
+	   N_CHAR if sym_cum[N_CHAR] > x,
+	   i such that sym_cum[i - 1] > x >= sym_cum[i] otherwise */
+{
+	unsigned long i, j, k;
+
+	i = 1;  j = N_CHAR;
+	while (i < j) {
+		k = (i + j) / 2;
+		if (sym_cum[k] > x) i = k + 1;  else j = k;
+	}
+	return i;
+}
+
+unsigned long BinarySearchPos(unsigned long x)
+	/* 0 if x >= position_cum[1],
+	   N - 1 if position_cum[N] > x,
+	   i such that position_cum[i] > x >= position_cum[i + 1] otherwise */
+{
+	unsigned long i, j, k;
+
+	i = 1;  j = N;
+	while (i < j) {
+		k = (i + j) / 2;
+		if (position_cum[k] > x) i = k + 1;  else j = k;
+	}
+	return i - 1;
+}
+
+static int Decode(unsigned char *srcbuf, unsigned char *dstbuf, unsigned long srclen,
+					unsigned long dstlen)	/* Just the reverse of Encode(). */
+{
+	unsigned long i, r, j, k, c, range, sym;
+	unsigned char *ip, *op;
+	unsigned char *srcend = srcbuf + srclen;
+	unsigned char *dstend = dstbuf + dstlen;
+	unsigned char buffer = 0;
+	unsigned char mask = 0;
+	unsigned long low = 0;
+	unsigned long high = Q4;
+	unsigned long value = 0;
+
+	ip = srcbuf;
+	op = dstbuf;
+	for (i = 0; i < M + 2; i++) {
+		value *= 2;
+		if ((mask >>= 1) == 0) {
+			buffer = (ip >= srcend) ? 0 : *(ip++);
+			mask = 128;
+		}
+		value += ((buffer & mask) != 0);
+	}
+
+	StartModel();
+	for (i = 0; i < N - F; i++) text_buf[i] = ' ';
+	r = N - F;
+
+	while (op < dstend) {
+		range = high - low;
+		sym = BinarySearchSym((unsigned long)
+				(((value - low + 1) * sym_cum[0] - 1) / range));
+		high = low + (range * sym_cum[sym - 1]) / sym_cum[0];
+		low +=       (range * sym_cum[sym    ]) / sym_cum[0];
+		for ( ; ; ) {
+			if (low >= Q2) {
+				value -= Q2;  low -= Q2;  high -= Q2;
+			} else if (low >= Q1 && high <= Q3) {
+				value -= Q1;  low -= Q1;  high -= Q1;
+			} else if (high > Q2) break;
+			low += low;  high += high;
+			value *= 2;
+			if ((mask >>= 1) == 0) {
+				buffer = (ip >= srcend) ? 0 : *(ip++);
+				mask = 128;
+			}
+			value += ((buffer & mask) != 0);
+		}
+		c = sym_to_char[sym];
+		UpdateModel(sym);
+		if (c < 256) {
+			if (op >= dstend) return -1;
+			*(op++) = c;
+			text_buf[r++] = c;
+			r &= (N - 1);
+		} else {
+			j = c - 255 + THRESHOLD;
+			range = high - low;
+			i = BinarySearchPos((unsigned long)
+				(((value - low + 1) * position_cum[0] - 1) / range));
+			high = low + (range * position_cum[i    ]) / position_cum[0];
+			low +=       (range * position_cum[i + 1]) / position_cum[0];
+			for ( ; ; ) {
+				if (low >= Q2) {
+					value -= Q2;  low -= Q2;  high -= Q2;
+				} else if (low >= Q1 && high <= Q3) {
+					value -= Q1;  low -= Q1;  high -= Q1;
+				} else if (high > Q2) break;
+				low += low;  high += high;
+				value *= 2;
+				if ((mask >>= 1) == 0) {
+					buffer = (ip >= srcend) ? 0 : *(ip++);
+					mask = 128;
+				}
+				value += ((buffer & mask) != 0);
+			}
+			i = (r - i - 1) & (N - 1);
+			for (k = 0; k < j; k++) {
+				c = text_buf[(i + k) & (N - 1)];
+				if (op >= dstend) return -1;
+				*(op++) = c;
+				text_buf[r++] = c;
+				r &= (N - 1);
+			}
+		}
+	}
+	return 0;
+}
+
+int lzari_decompress(unsigned char *data_in, unsigned char *cpage_out,
+		      u32 srclen, u32 destlen)
+{
+    return Decode(data_in, cpage_out, srclen, destlen);
+}
+#endif /* ((CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CONFIG_JFFS2_LZO_LZARI)) */
--- a/fs/jffs2/compr_lzo.c
+++ b/fs/jffs2/compr_lzo.c
@@ -0,0 +1,405 @@
+/*
+ * JFFS2 -- Journalling Flash File System, Version 2.
+ *
+ * Copyright (C) 2004 Patrik Kluba,
+ *		      University of Szeged, Hungary
+ *
+ * For licensing information, see the file 'LICENCE' in the
+ * jffs2 directory.
+ *
+ * $Id: compr_lzo.c,v 1.3 2004/06/23 16:34:39 havasi Exp $
+ *
+ */
+
+/*
+   LZO1X-1 (and -999) compression module for jffs2
+   based on the original LZO sources
+*/
+
+/* -*- Mode: C; indent-tabs-mode: t; c-basic-offset: 4; tab-width: 4 -*- */
+
+/*
+   Original copyright notice follows:
+
+   lzo1x_9x.c -- implementation of the LZO1X-999 compression algorithm
+   lzo_ptr.h -- low-level pointer constructs
+   lzo_swd.ch -- sliding window dictionary
+   lzoconf.h -- configuration for the LZO real-time data compression library
+   lzo_mchw.ch -- matching functions using a window
+   minilzo.c -- mini subset of the LZO real-time data compression library
+   config1x.h -- configuration for the LZO1X algorithm
+   lzo1x.h -- public interface of the LZO1X compression algorithm
+
+   These files are part of the LZO real-time data compression library.
+
+   Copyright (C) 1996-2002 Markus Franz Xaver Johannes Oberhumer
+   All Rights Reserved.
+
+   The LZO library is free software; you can redistribute it and/or
+   modify it under the terms of the GNU General Public License as
+   published by the Free Software Foundation; either version 2 of
+   the License, or (at your option) any later version.
+
+   The LZO library is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with the LZO library; see the file COPYING.
+   If not, write to the Free Software Foundation, Inc.,
+   59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+   Markus F.X.J. Oberhumer
+   <markus@oberhumer.com>
+*/
+
+/*
+
+	2004-02-16  pajko <pajko(AT)halom(DOT)u-szeged(DOT)hu>
+				Initial release
+					-removed all 16 bit code
+					-all sensitive data will be on 4 byte boundary
+					-removed check parts for library use
+					-removed all but LZO1X-* compression
+
+*/
+
+
+#include <config.h>
+#if ((CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CONFIG_JFFS2_LZO_LZARI))
+
+#include <linux/stddef.h>
+#include <jffs2/jffs2.h>
+#include <jffs2/compr_rubin.h>
+
+/* Integral types that have *exactly* the same number of bits as a lzo_voidp */
+typedef unsigned long lzo_ptr_t;
+typedef long lzo_sptr_t;
+
+/* data type definitions */
+#define U32 unsigned long
+#define S32 signed long
+#define I32 long
+#define U16 unsigned short
+#define S16 signed short
+#define I16 short
+#define U8 unsigned char
+#define S8 signed char
+#define I8 char
+
+#define M1_MAX_OFFSET	0x0400
+#define M2_MAX_OFFSET	0x0800
+#define M3_MAX_OFFSET	0x4000
+#define M4_MAX_OFFSET	0xbfff
+
+#define __COPY4(dst,src)  * (lzo_uint32p)(dst) = * (const lzo_uint32p)(src)
+#define COPY4(dst,src)	__COPY4((lzo_ptr_t)(dst),(lzo_ptr_t)(src))
+
+#define TEST_IP		(ip < ip_end)
+#define TEST_OP		(op <= op_end)
+
+#define NEED_IP(x) \
+	    if ((lzo_uint)(ip_end - ip) < (lzo_uint)(x))  goto input_overrun
+#define NEED_OP(x) \
+	    if ((lzo_uint)(op_end - op) < (lzo_uint)(x))  goto output_overrun
+#define TEST_LOOKBEHIND(m_pos,out)    if (m_pos < out) goto lookbehind_overrun
+
+typedef U32 lzo_uint32;
+typedef I32 lzo_int32;
+typedef U32 lzo_uint;
+typedef I32 lzo_int;
+typedef int lzo_bool;
+
+#define lzo_byte		U8
+#define lzo_bytep		U8 *
+#define lzo_charp		char *
+#define lzo_voidp		void *
+#define lzo_shortp		short *
+#define lzo_ushortp		unsigned short *
+#define lzo_uint32p		lzo_uint32 *
+#define lzo_int32p		lzo_int32 *
+#define lzo_uintp		lzo_uint *
+#define lzo_intp		lzo_int *
+#define lzo_voidpp		lzo_voidp *
+#define lzo_bytepp		lzo_bytep *
+#define lzo_sizeof_dict_t		sizeof(lzo_bytep)
+
+#define LZO_E_OK		    0
+#define LZO_E_ERROR		    (-1)
+#define LZO_E_OUT_OF_MEMORY	    (-2)	/* not used right now */
+#define LZO_E_NOT_COMPRESSIBLE	    (-3)	/* not used right now */
+#define LZO_E_INPUT_OVERRUN	    (-4)
+#define LZO_E_OUTPUT_OVERRUN	    (-5)
+#define LZO_E_LOOKBEHIND_OVERRUN    (-6)
+#define LZO_E_EOF_NOT_FOUND	    (-7)
+#define LZO_E_INPUT_NOT_CONSUMED    (-8)
+
+#define PTR(a)				((lzo_ptr_t) (a))
+#define PTR_LINEAR(a)		PTR(a)
+#define PTR_ALIGNED_4(a)	((PTR_LINEAR(a) & 3) == 0)
+#define PTR_ALIGNED_8(a)	((PTR_LINEAR(a) & 7) == 0)
+#define PTR_ALIGNED2_4(a,b)	(((PTR_LINEAR(a) | PTR_LINEAR(b)) & 3) == 0)
+#define PTR_ALIGNED2_8(a,b)	(((PTR_LINEAR(a) | PTR_LINEAR(b)) & 7) == 0)
+#define PTR_LT(a,b)			(PTR(a) < PTR(b))
+#define PTR_GE(a,b)			(PTR(a) >= PTR(b))
+#define PTR_DIFF(a,b)		((lzo_ptrdiff_t) (PTR(a) - PTR(b)))
+#define pd(a,b)			((lzo_uint) ((a)-(b)))
+
+typedef ptrdiff_t lzo_ptrdiff_t;
+
+static int
+lzo1x_decompress (const lzo_byte * in, lzo_uint in_len,
+		  lzo_byte * out, lzo_uintp out_len, lzo_voidp wrkmem)
+{
+	register lzo_byte *op;
+	register const lzo_byte *ip;
+	register lzo_uint t;
+
+	register const lzo_byte *m_pos;
+
+	const lzo_byte *const ip_end = in + in_len;
+	lzo_byte *const op_end = out + *out_len;
+
+	*out_len = 0;
+
+	op = out;
+	ip = in;
+
+	if (*ip > 17)
+	{
+		t = *ip++ - 17;
+		if (t < 4)
+			goto match_next;
+		NEED_OP (t);
+		NEED_IP (t + 1);
+		do
+			*op++ = *ip++;
+		while (--t > 0);
+		goto first_literal_run;
+	}
+
+	while (TEST_IP && TEST_OP)
+	{
+		t = *ip++;
+		if (t >= 16)
+			goto match;
+		if (t == 0)
+		{
+			NEED_IP (1);
+			while (*ip == 0)
+			{
+				t += 255;
+				ip++;
+				NEED_IP (1);
+			}
+			t += 15 + *ip++;
+		}
+		NEED_OP (t + 3);
+		NEED_IP (t + 4);
+		if (PTR_ALIGNED2_4 (op, ip))
+		{
+			COPY4 (op, ip);
+
+			op += 4;
+			ip += 4;
+			if (--t > 0)
+			{
+				if (t >= 4)
+				{
+					do
+					{
+						COPY4 (op, ip);
+						op += 4;
+						ip += 4;
+						t -= 4;
+					}
+					while (t >= 4);
+					if (t > 0)
+						do
+							*op++ = *ip++;
+						while (--t > 0);
+				}
+				else
+					do
+						*op++ = *ip++;
+					while (--t > 0);
+			}
+		}
+		else
+		{
+			*op++ = *ip++;
+			*op++ = *ip++;
+			*op++ = *ip++;
+			do
+				*op++ = *ip++;
+			while (--t > 0);
+		}
+	      first_literal_run:
+
+		t = *ip++;
+		if (t >= 16)
+			goto match;
+
+		m_pos = op - (1 + M2_MAX_OFFSET);
+		m_pos -= t >> 2;
+		m_pos -= *ip++ << 2;
+		TEST_LOOKBEHIND (m_pos, out);
+		NEED_OP (3);
+		*op++ = *m_pos++;
+		*op++ = *m_pos++;
+		*op++ = *m_pos;
+
+		goto match_done;
+
+		while (TEST_IP && TEST_OP)
+		{
+		      match:
+			if (t >= 64)
+			{
+				m_pos = op - 1;
+				m_pos -= (t >> 2) & 7;
+				m_pos -= *ip++ << 3;
+				t = (t >> 5) - 1;
+				TEST_LOOKBEHIND (m_pos, out);
+				NEED_OP (t + 3 - 1);
+				goto copy_match;
+
+			}
+			else if (t >= 32)
+			{
+				t &= 31;
+				if (t == 0)
+				{
+					NEED_IP (1);
+					while (*ip == 0)
+					{
+						t += 255;
+						ip++;
+						NEED_IP (1);
+					}
+					t += 31 + *ip++;
+				}
+
+				m_pos = op - 1;
+				m_pos -= (ip[0] >> 2) + (ip[1] << 6);
+
+				ip += 2;
+			}
+			else if (t >= 16)
+			{
+				m_pos = op;
+				m_pos -= (t & 8) << 11;
+
+				t &= 7;
+				if (t == 0)
+				{
+					NEED_IP (1);
+					while (*ip == 0)
+					{
+						t += 255;
+						ip++;
+						NEED_IP (1);
+					}
+					t += 7 + *ip++;
+				}
+
+				m_pos -= (ip[0] >> 2) + (ip[1] << 6);
+
+				ip += 2;
+				if (m_pos == op)
+					goto eof_found;
+				m_pos -= 0x4000;
+			}
+			else
+			{
+
+				m_pos = op - 1;
+				m_pos -= t >> 2;
+				m_pos -= *ip++ << 2;
+				TEST_LOOKBEHIND (m_pos, out);
+				NEED_OP (2);
+				*op++ = *m_pos++;
+				*op++ = *m_pos;
+
+				goto match_done;
+			}
+
+			TEST_LOOKBEHIND (m_pos, out);
+			NEED_OP (t + 3 - 1);
+			if (t >= 2 * 4 - (3 - 1)
+			    && PTR_ALIGNED2_4 (op, m_pos))
+			{
+				COPY4 (op, m_pos);
+				op += 4;
+				m_pos += 4;
+				t -= 4 - (3 - 1);
+				do
+				{
+					COPY4 (op, m_pos);
+					op += 4;
+					m_pos += 4;
+					t -= 4;
+				}
+				while (t >= 4);
+				if (t > 0)
+					do
+						*op++ = *m_pos++;
+					while (--t > 0);
+			}
+			else
+
+			{
+			      copy_match:
+				*op++ = *m_pos++;
+				*op++ = *m_pos++;
+				do
+					*op++ = *m_pos++;
+				while (--t > 0);
+			}
+
+		      match_done:
+			t = ip[-2] & 3;
+
+			if (t == 0)
+				break;
+
+		      match_next:
+			NEED_OP (t);
+			NEED_IP (t + 1);
+			do
+				*op++ = *ip++;
+			while (--t > 0);
+			t = *ip++;
+		}
+	}
+	*out_len = op - out;
+	return LZO_E_EOF_NOT_FOUND;
+
+      eof_found:
+	*out_len = op - out;
+	return (ip == ip_end ? LZO_E_OK :
+		(ip <
+		 ip_end ? LZO_E_INPUT_NOT_CONSUMED : LZO_E_INPUT_OVERRUN));
+
+      input_overrun:
+	*out_len = op - out;
+	return LZO_E_INPUT_OVERRUN;
+
+      output_overrun:
+	*out_len = op - out;
+	return LZO_E_OUTPUT_OVERRUN;
+
+      lookbehind_overrun:
+	*out_len = op - out;
+	return LZO_E_LOOKBEHIND_OVERRUN;
+}
+
+int lzo_decompress(unsigned char *data_in, unsigned char *cpage_out,
+		      u32 srclen, u32 destlen)
+{
+	lzo_uint outlen = destlen;
+	return lzo1x_decompress (data_in, srclen, cpage_out, &outlen, NULL);
+}
+
+#endif /* ((CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CONFIG_JFFS2_LZO_LZARI)) */
--- a/fs/jffs2/jffs2_1pass.c
+++ b/fs/jffs2/jffs2_1pass.c
@@ -274,7 +274,11 @@ static char *compr_names[] = {
 	"RUBINMIPS",
 	"COPY",
 	"DYNRUBIN",
-	"ZLIB"
+	"ZLIB",
+#if defined(CONFIG_JFFS2_LZO_LZARI)
+	"LZO",
+	"LZARI",
+#endif
 };

 /* Spinning wheel */
@@ -583,6 +587,14 @@ jffs2_1pass_read_inode(struct b_lists *pL, u32 inode, char *dest)
 				case JFFS2_COMPR_ZLIB:
 					ret = zlib_decompress(src, lDest, jNode->csize, jNode->dsize);
 					break;
+#if defined(CONFIG_JFFS2_LZO_LZARI)
+				case JFFS2_COMPR_LZO:
+					ret = lzo_decompress(src, lDest, jNode->csize, jNode->dsize);
+					break;
+				case JFFS2_COMPR_LZARI:
+					ret = lzari_decompress(src, lDest, jNode->csize, jNode->dsize);
+					break;
+#endif
 				default:
 					/* unknown */
 					putLabeledWord("UNKOWN COMPRESSION METHOD = ", jNode->compr);
@@ -760,7 +772,11 @@ jffs2_1pass_list_inodes(struct b_lists * pL, u32 pino)
 				if (jNode->ino == jDir->ino && jNode->version >= i_version) {
 					if (i)
 						put_fl_mem(i);
-					i = get_fl_mem(b2->offset, sizeof(*i), NULL);
+
+					if (jDir->type == DT_LNK)
+						i = get_node_mem(b2->offset);
+					else
+						i = get_fl_mem(b2->offset, sizeof(*i), NULL);
 				}
 				b2 = b2->next;
 			}
--- a/include/asm-arm/arch-imx/imx-regs.h
+++ b/include/asm-arm/arch-imx/imx-regs.h
@@ -52,6 +52,12 @@
 #define IMX_AITC_BASE              (0x23000 + IMX_IO_BASE)
 #define IMX_CSI_BASE               (0x24000 + IMX_IO_BASE)

+/* Watchdog Registers*/
+
+#define WCR  __REG(IMX_WDT_BASE + 0x00) /* Watchdog Control Register */
+#define WSR  __REG(IMX_WDT_BASE + 0x04) /* Watchdog Service Register */
+#define WSTR __REG(IMX_WDT_BASE + 0x08) /* Watchdog Status Register  */
+
 /* SYSCTRL Registers */
 #define SIDR   __REG(IMX_SYSCTRL_BASE + 0x4) /* Silicon ID Register		    */
 #define FMCR   __REG(IMX_SYSCTRL_BASE + 0x8) /* Function Multiplex Control Register */
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
--- a/include/asm-ppc/processor.h
+++ b/include/asm-ppc/processor.h
@@ -718,6 +718,7 @@
 #define PVR_440GP_RC	0x40120481
 #define PVR_440GX_RA	0x51B21850
 #define PVR_440GX_RB	0x51B21851
+#define PVR_440GX_RC	0x51B21892
 #define PVR_405EP_RB	0x51210950
 #define PVR_601		0x00010000
 #define PVR_602		0x00050000
--- a/include/configs/APC405.h
+++ b/include/configs/APC405.h
@@ -42,6 +42,8 @@

 #define CONFIG_SYS_CLK_FREQ     33333400 /* external frequency to pll   */

+#define CONFIG_BOARD_TYPES	1	/* support board types		*/
+
 #define CONFIG_BAUDRATE		9600
 #define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/

@@ -321,6 +323,7 @@

 /* FPGA internal regs */
 #define CFG_FPGA_CTRL           0x008
+#define CFG_FPGA_CTRL2          0x00a

 /* FPGA Control Reg */
 #define CFG_FPGA_CTRL_CF_RESET  0x0001
@@ -348,7 +351,7 @@

 /* Image information... */
 #define CONFIG_LCD_USED         CONFIG_LCD_BIG
-#define CFG_LCD_HEADER_NAME     "s1d13806_640_480_16bpp.h"
+#define CFG_LCD_HEADER_NAME     "../common/s1d13806_640_480_16bpp.h"
 #define CFG_LCD_LOGO_NAME       "logo_640_480_24bpp.c"

 #define CFG_LCD_MEM             CFG_LCD_BIG_MEM
--- a/include/configs/IDS8247.h
+++ b/include/configs/IDS8247.h
@@ -0,0 +1,524 @@
+/*
+ * (C) Copyright 2005
+ * Heiko Schocher, DENX Software Engineering, <hs@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC8260		1	/* This is a MPC8260 CPU		*/
+#define CONFIG_MPC8272_FAMILY	1
+#define CONFIG_IDS8247		1
+#define CPU_ID_STR		"MPC8247"
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define	CONFIG_BOOTCOUNT_LIMIT
+
+#define CONFIG_PREBOOT	"echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=$(serverip):$(rootpath)\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw "			\
+	"console=ttyS0,115200\0"					\
+	"addip=setenv bootargs $(bootargs) "				\
+		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"	\
+		":$(hostname):$(netdev):off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm $(kernel_addr)\0"				\
+	"flash_self=run ramargs addip;"					\
+		"bootm $(kernel_addr) $(ramdisk_addr)\0"		\
+	"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0"	\
+	"rootpath=/opt/eldk/ppc_82xx\0"					\
+	"bootfile=/tftpboot/IDS8247/uImage\0"				\
+	"kernel_addr=ff800000\0"					\
+	"ramdisk_addr=ffa00000\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#define CONFIG_MISC_INIT_R	1
+
+/* enable I2C and select the hardware/software driver */
+#undef  CONFIG_HARD_I2C			/* I2C with hardware support	*/
+#define CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CFG_I2C_SLAVE		0x7F
+
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+
+#define I2C_PORT	0		/* Port A=0, B=1, C=2, D=3 */
+#define I2C_ACTIVE	(iop->pdir |=  0x00000080)
+#define I2C_TRISTATE	(iop->pdir &= ~0x00000080)
+#define I2C_READ	((iop->pdat & 0x00000080) != 0)
+#define I2C_SDA(bit)	if(bit) iop->pdat |=  0x00000080; \
+			else    iop->pdat &= ~0x00000080
+#define I2C_SCL(bit)	if(bit) iop->pdat |=  0x00000100; \
+			else    iop->pdat &= ~0x00000100
+#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
+
+#if 0
+#define CFG_I2C_EEPROM_ADDR	0x50
+#define CFG_I2C_EEPROM_ADDR_LEN 2
+#define CFG_EEPROM_PAGE_WRITE_BITS	4
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
+
+#define CONFIG_I2C_X
+#endif
+
+/*
+ * select serial console configuration
+ * use the extern UART for the console
+ */
+#define	CONFIG_CONS_INDEX	1
+#define CONFIG_BAUDRATE		115200
+/*
+ * NS16550 Configuration
+ */
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+
+#define CFG_NS16550_REG_SIZE    1
+
+#define CFG_NS16550_CLK         14745600
+
+#define	CFG_UART_BASE	0xE0000000
+#define CFG_UART_SIZE	0x10000
+
+#define CFG_NS16550_COM1        (CFG_UART_BASE + 0x8000)
+
+/*
+ * select ethernet configuration
+ *
+ * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
+ * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
+ * for FCC)
+ *
+ * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
+ * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
+ * from CONFIG_COMMANDS to remove support for networking.
+ *
+ */
+#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC       */
+#define	CONFIG_ETHER_ON_FCC		/* define if ether on FCC       */
+#undef	CONFIG_ETHER_NONE		/* define if ether on something else */
+#define	CONFIG_ETHER_INDEX    2		/* which SCC/FCC channel for ethernet */
+
+/*
+ * - Rx-CLK is CLK13
+ * - Tx-CLK is CLK14
+ * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
+ * - Enable Full Duplex in FSMR
+ */
+# define CFG_CMXFCR_MASK	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
+# define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
+# define CFG_CPMFCR_RAMTYPE	0
+# define CFG_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
+
+
+/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
+#define CONFIG_8260_CLKIN	66666666	/* in Hz */
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_NAND	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_SNTP	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END	0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CFG_LOAD_ADDR	0x100000	/* default load address	*/
+
+#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#define	CFG_RESET_ADDRESS 0xFDFFFFFC	/* "bad" address		*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */
+
+
+/* What should the base address of the main FLASH be and how big is
+ * it (in MBytes)? This must contain TEXT_BASE from board/ids8247/config.mk
+ * The main FLASH is whichever is connected to *CS0.
+ */
+#define CFG_FLASH0_BASE 0xFFF00000
+#define CFG_FLASH0_SIZE 8
+
+/* Flash bank size (for preliminary settings)
+ */
+#define CFG_FLASH_SIZE CFG_FLASH0_SIZE
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks      */
+#define CFG_MAX_FLASH_SECT	64	/* max num of sects on one chip */
+
+#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
+#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
+
+/* Environment in flash */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE+0x60000)
+#define CFG_ENV_SIZE		0x20000
+#define CFG_ENV_SECT_SIZE	0x20000
+
+/*-----------------------------------------------------------------------
+ * NAND-FLASH stuff
+ *-----------------------------------------------------------------------
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+
+#define CFG_NAND0_BASE 0xE1000000
+
+#define CFG_MAX_NAND_DEVICE     1       /* Max number of NAND devices           */
+#define SECTORSIZE 512
+#define NAND_NO_RB
+
+#define ADDR_COLUMN 1
+#define ADDR_PAGE 2
+#define ADDR_COLUMN_PAGE 3
+
+#define NAND_ChipID_UNKNOWN     0x00
+#define NAND_MAX_FLOORS 1
+#define NAND_MAX_CHIPS 1
+
+#define NAND_DISABLE_CE(nand) do \
+{ \
+	*(((volatile __u8 *)(nand->IO_ADDR)) + 0xc) = 0; \
+} while(0)
+
+#define NAND_ENABLE_CE(nand) do \
+{ \
+	*(((volatile __u8 *)(nand->IO_ADDR)) + 0x8) = 0; \
+} while(0)
+
+#define NAND_CTL_CLRALE(nandptr) do \
+{ \
+	*(((volatile __u8 *)nandptr) + 0x8) = 0; \
+} while(0)
+
+#define NAND_CTL_SETALE(nandptr) do \
+{ \
+	*(((volatile __u8 *)nandptr) + 0x9) = 0; \
+} while(0)
+
+#define NAND_CTL_CLRCLE(nandptr) do \
+{ \
+	*(((volatile __u8 *)nandptr) + 0x8) = 0; \
+} while(0)
+
+#define NAND_CTL_SETCLE(nandptr) do \
+{ \
+	*(((volatile __u8 *)nandptr) + 0xa) = 0; \
+} while(0)
+
+#ifdef NAND_NO_RB
+/* constant delay (see also tR in the datasheet) */
+#define NAND_WAIT_READY(nand) do { \
+	udelay(12); \
+} while (0)
+#else
+/* use the R/B pin */
+#endif
+
+#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr + 0x2)) = (__u8)(d); } while(0)
+#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr + 0x1)) = (__u8)(d); } while(0)
+#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr + 0x0)) = (__u8)d; } while(0)
+#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)(adr + 0x0)))
+
+#endif /* CFG_CMD_NAND */
+
+/*-----------------------------------------------------------------------
+ * Hard Reset Configuration Words
+ *
+ * if you change bits in the HRCW, you must also change the CFG_*
+ * defines for the various registers affected by the HRCW e.g. changing
+ * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
+ */
+#define CFG_HRCW_MASTER	(HRCW_BPS01 | HRCW_BMS | HRCW_ISB100 | HRCW_APPC10 | HRCW_MODCK_H1000)
+
+/* no slaves so just fill with zeros */
+#define CFG_HRCW_SLAVE1		0
+#define CFG_HRCW_SLAVE2		0
+#define CFG_HRCW_SLAVE3		0
+#define CFG_HRCW_SLAVE4		0
+#define CFG_HRCW_SLAVE5		0
+#define CFG_HRCW_SLAVE6		0
+#define CFG_HRCW_SLAVE7		0
+
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xF0000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define CFG_INIT_RAM_END	0x2000  /* End of used area in DPRAM    */
+#define CFG_GBL_DATA_SIZE	128 /* size in bytes reserved for initial data*/
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ *
+ * 60x SDRAM is mapped at CFG_SDRAM_BASE
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		CFG_FLASH0_BASE
+#define CFG_MONITOR_BASE	TEXT_BASE
+#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH*/
+#define BOOTFLAG_WARM		0x02	/* Software reboot                 */
+
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * HIDx - Hardware Implementation-dependent Registers                    2-11
+ *-----------------------------------------------------------------------
+ * HID0 also contains cache control - initially enable both caches and
+ * invalidate contents, then the final state leaves only the instruction
+ * cache enabled. Note that Power-On and Hard reset invalidate the caches,
+ * but Soft reset does not.
+ *
+ * HID1 has only read-only information - nothing to set.
+ */
+
+#define CFG_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI)
+#define CFG_HID0_FINAL  0
+#define CFG_HID2        0
+
+/*-----------------------------------------------------------------------
+ * RMR - Reset Mode Register                                     5-5
+ *-----------------------------------------------------------------------
+ * turn on Checkstop Reset Enable
+ */
+#define CFG_RMR         0
+
+/*-----------------------------------------------------------------------
+ * BCR - Bus Configuration                                       4-25
+ *-----------------------------------------------------------------------
+ */
+#define CFG_BCR		0
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration                             4-31
+ *-----------------------------------------------------------------------
+ */
+#define CFG_SIUMCR      (SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_BCTLC01)
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control                             4-35
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
+#else
+#define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+			 SYPCR_SWRI|SYPCR_SWP)
+#endif /* CONFIG_WATCHDOG */
+
+/*-----------------------------------------------------------------------
+ * TMCNTSC - Time Counter Status and Control                     4-40
+ *-----------------------------------------------------------------------
+ * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
+ * and enable Time Counter
+ */
+#define CFG_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control                 4-42
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
+ * Periodic timer
+ */
+#define CFG_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock Control                                   9-8
+ *-----------------------------------------------------------------------
+ * Ensure DFBRG is Divide by 16
+ */
+#define CFG_SCCR        (0x00000028 | SCCR_DFBRG01)
+
+/*-----------------------------------------------------------------------
+ * RCCR - RISC Controller Configuration                         13-7
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RCCR        0
+
+/*
+ * Init Memory Controller:
+ *
+ * Bank Bus     Machine PortSz  Device
+ * ---- ---     ------- ------  ------
+ *  0   60x     GPCM    16 bit  FLASH
+ *  1   60x     GPCM     8 bit  NAND
+ *  2   60x     SDRAM   32 bit  SDRAM
+ *  3   60x     GPCM     8 bit  UART
+ *
+ */
+
+#define SDRAM_MAX_SIZE	0x08000000	/* max. 128 MB		*/
+
+/* Minimum mask to separate preliminary
+ * address ranges for CS[0:2]
+ */
+#define CFG_GLOBAL_SDRAM_LIMIT	(32<<20)	/* less than 32 MB */
+
+#define CFG_MPTPR       0x6600
+
+/*-----------------------------------------------------------------------------
+ * Address for Mode Register Set (MRS) command
+ *-----------------------------------------------------------------------------
+ */
+#define CFG_MRS_OFFS	0x00000110
+
+
+/* Bank 0 - FLASH
+ */
+#define CFG_BR0_PRELIM  ((CFG_FLASH_BASE & BRx_BA_MSK)  |\
+			 BRx_PS_8                       |\
+			 BRx_MS_GPCM_P                  |\
+			 BRx_V)
+
+#define CFG_OR0_PRELIM  (MEG_TO_AM(CFG_FLASH_SIZE)      |\
+			 ORxG_SCY_6_CLK                 )
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+/* Bank 1 - NAND Flash
+*/
+#define	CFG_NAND_BASE		CFG_NAND0_BASE
+#define	CFG_NAND_SIZE		0x8000
+
+#define CFG_OR_TIMING_NAND	0x000036
+
+#define CFG_BR1_PRELIM  ((CFG_NAND_BASE & BRx_BA_MSK) | BRx_PS_8 | BRx_MS_GPCM_P | BRx_V  )
+#define CFG_OR1_PRELIM  (P2SZ_TO_AM(CFG_NAND_SIZE) | CFG_OR_TIMING_NAND )
+#endif
+
+/* Bank 2 - 60x bus SDRAM
+ */
+#define CFG_PSRT        0x20
+#define CFG_LSRT        0x20
+
+#define CFG_BR2_PRELIM  ((CFG_SDRAM_BASE & BRx_BA_MSK)  |\
+			 BRx_PS_32                      |\
+			 BRx_MS_SDRAM_P                 |\
+			 BRx_V)
+
+#define CFG_OR2_PRELIM	CFG_OR2
+
+
+/* SDRAM initialization values
+*/
+#define CFG_OR2    ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
+			 ORxS_BPD_4                     |\
+			 ORxS_ROWST_PBI0_A10             |\
+			 ORxS_NUMR_12)
+
+#define CFG_PSDMR  (PSDMR_SDAM_A13_IS_A5 |\
+			 PSDMR_BSMA_A15_A17           |\
+			 PSDMR_SDA10_PBI0_A11         |\
+			 PSDMR_RFRC_5_CLK               |\
+			 PSDMR_PRETOACT_2W              |\
+			 PSDMR_ACTTORW_2W               |\
+			 PSDMR_BL                       |\
+			 PSDMR_LDOTOPRE_2C              |\
+			 PSDMR_WRC_3C                   |\
+			 PSDMR_CL_3)
+
+/* Bank 3 - UART
+*/
+
+#define CFG_BR3_PRELIM  ((CFG_UART_BASE & BRx_BA_MSK) | BRx_PS_8 | BRx_MS_GPCM_P | BRx_V  )
+#define CFG_OR3_PRELIM  (((-CFG_UART_SIZE) & ORxG_AM_MSK) | ORxG_CSNT | ORxG_SCY_1_CLK | ORxG_TRLX )
+
+#endif	/* __CONFIG_H */
--- a/include/configs/NC650.h
+++ b/include/configs/NC650.h
@@ -122,6 +122,7 @@
 				CFG_CMD_DHCP	| \
 				CFG_CMD_I2C	| \
 				CFG_CMD_NAND	| \
+				CFG_CMD_JFFS2	| \
 				CFG_CMD_NFS	| \
 				CFG_CMD_SNTP	)

@@ -398,5 +399,10 @@
 #define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
 #define BOOTFLAG_WARM	0x02		/* Software reboot			*/

+#define CONFIG_JFFS2_NAND 1			/* jffs2 on nand support */
+#define CONFIG_JFFS2_NAND_DEV 0			/* nand device jffs2 lives on */
+#define CONFIG_JFFS2_NAND_OFF 0			/* start of jffs2 partition */
+#define CONFIG_JFFS2_NAND_SIZE 4*1024*1024	/* size of jffs2 partition */
+#define NAND_CACHE_PAGES 16			/* size of nand cache in 512 bytes pages */

 #endif	/* __CONFIG_H */
--- a/include/configs/OCOTEA.h
+++ b/include/configs/OCOTEA.h
@@ -49,7 +49,7 @@
 *----------------------------------------------------------------------*/
 #define CFG_SDRAM_BASE	    0x00000000	    /* _must_ be 0		*/
 #define CFG_FLASH_BASE	    0xff800000	    /* start of FLASH		*/
-#define CFG_MONITOR_BASE    0xfff80000	    /* start of monitor		*/
+#define CFG_MONITOR_BASE    0xfffc0000	    /* start of monitor		*/
 #define CFG_PCI_MEMBASE	    0x80000000	    /* mapped pci memory	*/
 #define CFG_PERIPHERAL_BASE 0xe0000000	    /* internal peripherals	*/
 #define CFG_ISRAM_BASE	    0xc0000000	    /* internal SRAM		*/
--- a/include/configs/P3G4.h
+++ b/include/configs/P3G4.h
@@ -28,8 +28,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H

-#include <asm/processor.h>
-
 #ifndef __ASSEMBLY__
 #include <galileo/core.h>
 #endif
@@ -66,7 +64,7 @@
 * mpsc channel, change CONFIG_MPSC_PORT to the desired value.
 */
 #define	CONFIG_MPSC
-#define CONFIG_MPSC_PORT	1
+#define CONFIG_MPSC_PORT	0

 #define CONFIG_NET_MULTI        /* attempt all available adapters */

@@ -75,20 +73,46 @@

 #undef CONFIG_ETHER_PORT_MII	/* use RMII */

-#if 1
+#if 0
 #define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
 #else
 #define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
 #endif
 #define CONFIG_ZERO_BOOTDELAY_CHECK

+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
 #undef	CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND						     \
-	"bootp;" 						     \
-	"setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath " \
-	"ip=$ipaddr:$serverip:$gatewayip:" \
-	"$netmask:$hostname:eth0:none;" \
-	"bootm"
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"hostname=p3g4\0"						\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=$(serverip):$(rootpath)\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs $(bootargs) "				\
+		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"	\
+		":$(hostname):$(netdev):off panic=1\0"			\
+	"addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\
+	"flash_nfs=run nfsargs addip addtty;"				\
+		"bootm $(kernel_addr)\0"				\
+	"flash_self=run ramargs addip addtty;"				\
+		"bootm $(kernel_addr) $(ramdisk_addr)\0"		\
+	"net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;"     \
+	        "bootm\0"						\
+	"rootpath=/opt/eldk/ppc_74xx\0"					\
+	"bootfile=/tftpboot/p3g4/uImage\0"				\
+	"kernel_addr=ff000000\0"					\
+	"ramdisk_addr=ff010000\0"					\
+	"load=tftp 100000 /tftpboot/p3g4/u-boot.bin\0"			\
+	"update=protect off fff00000 fff3ffff;era fff00000 fff3ffff;"	\
+		"cp.b 100000 fff00000 $(filesize);"			\
+		"setenv filesize;saveenv\0"				\
+	"upd=run load;run update\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"

 #define CONFIG_LOADS_ECHO	0	/* echo off for serial download	*/
 #define	CFG_LOADS_BAUD_CHANGE		/* allow baudrate changes	*/
@@ -101,7 +125,15 @@

 #define	CONFIG_TIMESTAMP		/* Print image info with timestamp */

-#define CONFIG_COMMANDS	(CONFIG_CMD_DFL | CFG_CMD_ASKENV)
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_ASKENV	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_PCI	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_MII	| \
+				CFG_CMD_PING	| \
+				CFG_CMD_UNIVERSE| \
+				CFG_CMD_BSP	)

 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
@@ -271,21 +303,20 @@
 /* PCI MEMORY MAP section */
 #define CFG_PCI0_MEM_BASE	0x80000000
 #define CFG_PCI0_MEM_SIZE	_128M
+#define CFG_PCI0_0_MEM_SPACE	(CFG_PCI0_MEM_BASE)
+
 #define CFG_PCI1_MEM_BASE	0x88000000
 #define CFG_PCI1_MEM_SIZE	_128M
-
-#define CFG_PCI0_0_MEM_SPACE	(CFG_PCI0_MEM_BASE)
 #define CFG_PCI1_0_MEM_SPACE	(CFG_PCI1_MEM_BASE)

-
 /* PCI I/O MAP section */
 #define CFG_PCI0_IO_BASE	0xfa000000
 #define CFG_PCI0_IO_SIZE	_16M
-#define CFG_PCI1_IO_BASE	0xfb000000
-#define CFG_PCI1_IO_SIZE	_16M
-
 #define CFG_PCI0_IO_SPACE	(CFG_PCI0_IO_BASE)
 #define CFG_PCI0_IO_SPACE_PCI	0x00000000
+
+#define CFG_PCI1_IO_BASE	0xfb000000
+#define CFG_PCI1_IO_SIZE	_16M
 #define CFG_PCI1_IO_SPACE	(CFG_PCI1_IO_BASE)
 #define CFG_PCI1_IO_SPACE_PCI	0x00000000

--- a/include/configs/PLU405.h
+++ b/include/configs/PLU405.h
@@ -212,7 +212,7 @@
 #define CFG_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
 #define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
 #define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
-#define CFG_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1MS  0xf8000001      /* 128MB, enable hard-wired to 1 */
 #define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
 #define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
 #define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
--- a/include/configs/PMC405.h
+++ b/include/configs/PMC405.h
@@ -252,7 +252,7 @@
 #define CFG_EBC_PB1CR	FLASH1_BA | 0x9A000 /* BAS=0xFE0,BS=16MB,BU=R/W,BW=16bit*/

 /* Memory Bank 2 (CAN0, 1, RTC) initialization					*/
-#define CFG_EBC_PB2AP	0x03000040   /* TWT=6,TH=0,CSN=0,OEN=0,WBN=0,WBF=0	*/
+#define CFG_EBC_PB2AP	0x03000440   /* TWT=5,TH=2,CSN=0,OEN=0,WBN=0,WBF=0      */
 #define CFG_EBC_PB2CR	CAN_BA | 0x18000    /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/

 /* Memory Bank 3 (CompactFlash IDE, FPGA internal) initialization		*/
--- a/include/configs/PPChameleonEVB.h
+++ b/include/configs/PPChameleonEVB.h
@@ -772,7 +772,7 @@
 #define CONFIG_JFFS2_NAND 1			/* jffs2 on nand support */
 #define CONFIG_JFFS2_NAND_DEV 0			/* nand device jffs2 lives on */
 #define CONFIG_JFFS2_NAND_OFF 0			/* start of jffs2 partition */
-#define CONFIG_JFFS2_NAND_SIZE 2*1024*1024	/* size of jffs2 partition */
+#define CONFIG_JFFS2_NAND_SIZE 4*1024*1024	/* size of jffs2 partition */
 #define NAND_CACHE_PAGES 16			/* size of nand cache in 512 bytes pages */

 #endif	/* __CONFIG_H */
--- a/include/configs/Rattler.h
+++ b/include/configs/Rattler.h
@@ -195,7 +195,7 @@
 #define CFG_RAMBOOT
 #endif

-#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/

 #define CFG_ENV_IS_IN_FLASH

--- a/include/configs/TQM8540.h
+++ b/include/configs/TQM8540.h
@@ -279,7 +279,7 @@
 #endif

 #define CONFIG_MII		1	/* MII PHY management */
-#undef CONFIG_MPC85XX_TSEC1
+#define CONFIG_MPC85XX_TSEC1	1
 #define CONFIG_MPC85XX_TSEC2	1
 #define TSEC1_PHY_ADDR		0
 #define TSEC2_PHY_ADDR		1
@@ -287,9 +287,12 @@
 #define TSEC2_PHYIDX		0

 #define CONFIG_MPC85XX_FEC	1
-#define FEC_PHY_ADDR		0
+#define FEC_PHY_ADDR		2
 #define FEC_PHYIDX		0

+#define CONFIG_HAS_ETH1
+#define CONFIG_HAS_ETH2
+
 #define CONFIG_ETHPRIME		"ENET1"

 #endif	/* CONFIG_TSEC_ENET */
--- a/include/configs/TQM8560.h
+++ b/include/configs/TQM8560.h
@@ -279,18 +279,17 @@
 #define TSEC2_PHY_ADDR		1
 #define TSEC2_PHYIDX		0

+#endif  /* CONFIG_TSEC_ENET */
+
 #define CONFIG_ETHER_ON_FCC
 #define CONFIG_ETHER_ON_FCC3
 #define CFG_CMXFCR_MASK3      (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
-#define CFG_CMXFCR_VALUE3     (CMXFCR_RF2CS_CLK15 | CMXFCR_TF2CS_CLK14)
+#define CFG_CMXFCR_VALUE3     (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK14)
 #define CFG_CPMFCR_RAMTYPE    0
-#define CFG_FCC_PSMR          (FCC_PSMR_FDE)
+#define CFG_FCC_PSMR          (FCC_PSMR_FDE | FCC_PSMR_LPB)

 #define CONFIG_ETHPRIME		"ENET1"

-#endif	/* CONFIG_TSEC_ENET */
-
-
 /*
 * Environment
 */
--- a/include/configs/adsvix.h
+++ b/include/configs/adsvix.h
@@ -0,0 +1,347 @@
+/*
+ * (C) Copyright 2004
+ * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
+ *
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Configuation settings for the LUBBOCK board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_PXA27X		1	/* This is an PXA27x CPU    */
+#define CONFIG_ADSVIX		1	/* on a Adsvix Board     */
+#define CONFIG_MMC		1
+#define BOARD_LATE_INIT		1
+
+#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */
+
+#define RTC
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN	    (CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_FFUART	       1       /* we use FFUART on ADSVIX */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE	       38400
+
+#define CONFIG_DOS_PARTITION   1
+
+#define CONFIG_COMMANDS		((CONFIG_CMD_DFL & ~CFG_CMD_NET) | CFG_CMD_MMC | CFG_CMD_FAT | CFG_CMD_IDE | CFG_CMD_PCMCIA)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef CONFIG_SHOW_BOOT_PROGRESS
+
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_SERVERIP		192.168.1.99
+#define CONFIG_BOOTCOMMAND	"run boot_flash"
+#define CONFIG_BOOTARGS		"console=ttyS0,38400 ramdisk_size=12288"\
+				" rw root=/dev/ram initrd=0xa0800000,5m"
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"program_boot_cf="						\
+			"mw.b 0xa0010000 0xff 0x20000; "		\
+			"if	 pinit on && "				\
+				"ide reset && "				\
+				"fatload ide 0 0xa0010000 u-boot.bin; "	\
+			"then "						\
+				"protect off 0x0 0x1ffff; "		\
+				"erase 0x0 0x1ffff; "			\
+				"cp.b 0xa0010000 0x0 0x20000; "		\
+			"fi\0"						\
+	"program_uzImage_cf="						\
+			"mw.b 0xa0010000 0xff 0x180000; "		\
+			"if	 pinit on && "				\
+				"ide reset && "				\
+				"fatload ide 0 0xa0010000 uzImage; "	\
+			"then "						\
+				"protect off 0x40000 0x1bffff; "	\
+				"erase 0x40000 0x1bffff; "		\
+				"cp.b 0xa0010000 0x40000 0x180000; "	\
+			"fi\0"						\
+	"program_ramdisk_cf="						\
+			"mw.b 0xa0010000 0xff 0x500000; "		\
+			"if	 pinit on && "				\
+				"ide reset && "				\
+				"fatload ide 0 0xa0010000 ramdisk.gz; "	\
+			"then "						\
+				"protect off 0x1c0000 0x6bffff; "	\
+				"erase 0x1c0000 0x6bffff; "		\
+				"cp.b 0xa0010000 0x1c0000 0x500000; "	\
+			"fi\0"						\
+	"boot_cf="							\
+			"if	 pinit on && "				\
+				"ide reset && "				\
+				"fatload ide 0 0xa0030000 uzImage && "	\
+				"fatload ide 0 0xa0800000 ramdisk.gz; "	\
+			"then "						\
+				"bootm 0xa0030000; "			\
+			"fi\0"						\
+	"program_boot_mmc="						\
+			"mw.b 0xa0010000 0xff 0x20000; "		\
+			"if	 mmcinit && "				\
+				"fatload mmc 0 0xa0010000 u-boot.bin; "	\
+			"then "						\
+				"protect off 0x0 0x1ffff; "		\
+				"erase 0x0 0x1ffff; "			\
+				"cp.b 0xa0010000 0x0 0x20000; "		\
+			"fi\0"						\
+	"program_uzImage_mmc="						\
+			"mw.b 0xa0010000 0xff 0x180000; "		\
+			"if	 mmcinit && "				\
+				"fatload mmc 0 0xa0010000 uzImage; "	\
+			"then "						\
+				"protect off 0x40000 0x1bffff; "	\
+				"erase 0x40000 0x1bffff; "		\
+				"cp.b 0xa0010000 0x40000 0x180000; "	\
+			"fi\0"						\
+	"program_ramdisk_mmc="						\
+			"mw.b 0xa0010000 0xff 0x500000; "		\
+			"if	 mmcinit && "				\
+				"fatload mmc 0 0xa0010000 ramdisk.gz; "	\
+			"then "						\
+				"protect off 0x1c0000 0x6bffff; "	\
+				"erase 0x1c0000 0x6bffff; "		\
+				"cp.b 0xa0010000 0x1c0000 0x500000; "	\
+			"fi\0"						\
+	"boot_mmc="							\
+			"if	 mmcinit && "				\
+				"fatload mmc 0 0xa0030000 uzImage && "	\
+				"fatload mmc 0 0xa0800000 ramdisk.gz; "	\
+			"then "						\
+				"bootm 0xa0030000; "			\
+			"fi\0"						\
+	"boot_flash="							\
+			"cp.b 0x1c0000 0xa0800000 0x500000; "		\
+			"bootm 0x40000\0"				\
+
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_CMDLINE_TAG	 1	/* enable passing of ATAGs	*/
+/* #define CONFIG_INITRD_TAG	 1 */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400		/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2		/* which serial port to use */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_HUSH_PARSER		1
+#define CFG_PROMPT_HUSH_PS2	"> "
+
+#define CFG_LONGHELP				/* undef to save memory		*/
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT		"$ "		/* Monitor Command Prompt */
+#else
+#define CFG_PROMPT		"=> "		/* Monitor Command Prompt */
+#endif
+#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CFG_DEVICE_NULLDEV	1
+
+#define CFG_MEMTEST_START	0xa0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM	*/
+
+#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR		0xa1000000	/* default load address */
+
+#define CFG_HZ			3686400		/* incrementer freq: 3.6864 MHz */
+#define CFG_CPUSPEED		0x207		/* need to look more closely, I think this is Turbo = 2x, L=91Mhz */
+
+						/* valid baudrates */
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#define CFG_MMC_BASE		0xF0000000
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
+#endif
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	4	   /* we have 2 banks of DRAM */
+#define PHYS_SDRAM_1		0xa0000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE	0x04000000 /* 64 MB */
+#define PHYS_SDRAM_2		0xa4000000 /* SDRAM Bank #2 */
+#define PHYS_SDRAM_2_SIZE	0x00000000 /* 0 MB */
+#define PHYS_SDRAM_3		0xa8000000 /* SDRAM Bank #3 */
+#define PHYS_SDRAM_3_SIZE	0x00000000 /* 0 MB */
+#define PHYS_SDRAM_4		0xac000000 /* SDRAM Bank #4 */
+#define PHYS_SDRAM_4_SIZE	0x00000000 /* 0 MB */
+
+#define PHYS_FLASH_1		0x00000000 /* Flash Bank #1 */
+
+#define CFG_DRAM_BASE		0xa0000000
+#define CFG_DRAM_SIZE		0x04000000
+
+#define CFG_FLASH_BASE		PHYS_FLASH_1
+
+/*
+ * GPIO settings
+ */
+
+#define CFG_GPSR0_VAL		0x00018004
+#define CFG_GPSR1_VAL		0x004F0080
+#define CFG_GPSR2_VAL		0x13EFC000
+#define CFG_GPSR3_VAL		0x0006E032
+#define CFG_GPCR0_VAL		0x084AFE1A
+#define CFG_GPCR1_VAL		0x003003F2
+#define CFG_GPCR2_VAL		0x0C014000
+#define CFG_GPCR3_VAL		0x00000C00
+#define CFG_GPDR0_VAL		0xCBC3BFFC
+#define CFG_GPDR1_VAL		0x00FFABF3
+#define CFG_GPDR2_VAL		0x1EEFFC00
+#define CFG_GPDR3_VAL		0x0187EC32
+#define CFG_GAFR0_L_VAL		0x84400000
+#define CFG_GAFR0_U_VAL		0xA51A8010
+#define CFG_GAFR1_L_VAL		0x699A955A
+#define CFG_GAFR1_U_VAL		0x0005A0AA
+#define CFG_GAFR2_L_VAL		0x40000000
+#define CFG_GAFR2_U_VAL		0x0109A400
+#define CFG_GAFR3_L_VAL		0x54000000
+#define CFG_GAFR3_U_VAL		0x00001409
+
+#define CFG_PSSR_VAL		0x20
+
+/*
+ * Clock settings
+ */
+#define CFG_CKEN		0x00400200
+#define CFG_CCCR		0x02000290 /*   520Mhz */
+/* #define CFG_CCCR		0x02000210  416 Mhz */
+
+/*
+ * Memory settings
+ */
+
+#define CFG_MSC0_VAL		0x23F2B3DB
+#define CFG_MSC1_VAL		0x0000CCD1
+#define CFG_MSC2_VAL		0x0000B884
+#define CFG_MDCNFG_VAL		0x08000AC8
+#define CFG_MDREFR_VAL		0x0000001E
+#define CFG_MDMRS_VAL		0x00000000
+
+#define CFG_FLYCNFG_VAL		0x00010001
+#define CFG_SXCNFG_VAL		0x40044004
+
+/*
+ * PCMCIA and CF Interfaces
+ */
+#define CFG_MECR_VAL		0x00000002
+#define CFG_MCMEM0_VAL		0x00004204
+#define CFG_MCMEM1_VAL		0x00000000
+#define CFG_MCATT0_VAL		0x00010504
+#define CFG_MCATT1_VAL		0x00000000
+#define CFG_MCIO0_VAL		0x00008407
+#define CFG_MCIO1_VAL		0x00000000
+
+#define CONFIG_PXA_PCMCIA 1
+#define CONFIG_PXA_IDE 1
+
+#define CONFIG_PCMCIA_SLOT_A 1
+/* just to keep build system happy  */
+
+#define CFG_PCMCIA_MEM_ADDR     0x28000000
+#define CFG_PCMCIA_MEM_SIZE     0x04000000
+
+
+#define CFG_IDE_MAXBUS		1
+/* max. 1 IDE bus		*/
+#define CFG_IDE_MAXDEVICE	1
+/* max. 1 drive per IDE bus	*/
+
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_BASE_ADDR	0x20000000
+
+/* Offset for data I/O			*/
+#define CFG_ATA_DATA_OFFSET	0x1f0
+
+/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	0x1f0
+
+/* Offset for alternate registers	*/
+#define CFG_ATA_ALT_OFFSET	0x3f0
+
+/*
+ * FLASH and environment organization
+ */
+
+#define CFG_FLASH_CFI
+#define CFG_FLASH_CFI_DRIVER	1
+
+#define CFG_MONITOR_BASE	0
+#define CFG_MONITOR_LEN		0x20000
+
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	4 + 255  /* max number of sectors on one chip    */
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT	(25*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT	(25*CFG_HZ) /* Timeout for Flash Write */
+
+/* write flash less slowly */
+#define CFG_FLASH_USE_BUFFER_WRITE 1
+
+/* Flash environment locations */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_ADDR		(PHYS_FLASH_1 + CFG_MONITOR_LEN)	/* Addr of Environment Sector	*/
+#define CFG_ENV_SIZE		0x20000	/* Total Size of Environment     	*/
+#define CFG_ENV_SECT_SIZE	0x20000	/* Total Size of Environment Sector	*/
+
+#endif	/* __CONFIG_H */
--- a/include/configs/at91rm9200dk.h
+++ b/include/configs/at91rm9200dk.h
@@ -32,8 +32,12 @@

 #define AT91_SLOW_CLOCK		32768	/* slow clock */

-#define CONFIG_AT91RM9200DK	1	/* on an AT91RM9200DK Board	 */
-#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */
+#define CONFIG_ARM920T		1	/* This is an ARM920T Core	*/
+#define CONFIG_AT91RM9200	1	/* It's an Atmel AT91RM9200 SoC	*/
+#define CONFIG_AT91RM9200DK	1	/* on an AT91RM9200DK Board	*/
+#undef  CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/
+#define USE_920T_MMU		1
+
 #define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs	*/
 #define CONFIG_SETUP_MEMORY_TAGS 1
 #define CONFIG_INITRD_TAG	1
@@ -77,8 +81,6 @@

 #define CONFIG_BAUDRATE 115200

-#define CFG_AT91C_BRGR_DIVISOR	33	/* hardcode so no __divsi3 : AT91C_MASTER_CLOCK / baudrate / 16 */
-
 /*
 * Hardware drivers
 */
--- a/include/configs/canmb.h
+++ b/include/configs/canmb.h
@@ -0,0 +1,219 @@
+/*
+ * (C) Copyright 2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
+#define CONFIG_MPC5200		1	/* More exactly a MPC5200 */
+#define CONFIG_CANMB  		1	/* ... on canmb board - we need this for FEC.C */
+
+#define CFG_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */
+
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
+#define BOOTFLAG_WARM		0x02	/* Software reboot	     */
+
+#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+#define CONFIG_BOARD_EARLY_INIT_R
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
+#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+/*
+ * Supported commands
+ */
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_ASKENV	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_IMMAP	| \
+				CFG_CMD_MII 	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_REGINFO	| \
+				CFG_CMD_SNTP	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * MUST be low boot - HIGHBOOT is not supported anymore
+ */
+#if (TEXT_BASE == 0xFE000000)		/* Boot low with 32 MB Flash */
+#   define CFG_LOWBOOT		1
+#   define CFG_LOWBOOT16	1
+#else
+#   error "TEXT_BASE must be 0xFE000000"
+#endif
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=$(serverip):$(rootpath)\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs $(bootargs) "				\
+		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"	\
+		":$(hostname):$(netdev):off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm $(kernel_addr)\0"				\
+	"flash_self=run ramargs addip;"					\
+		"bootm $(kernel_addr) $(ramdisk_addr)\0"		\
+	"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0"	\
+	"rootpath=/opt/eldk/ppc_6xx\0"					\
+	"bootfile=/tftpboot/canmb/uImage\0"				\
+	""
+
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+/*
+ * IPB Bus clocking configuration.
+ */
+#undef CFG_IPBSPEED_133   		/* define for 133MHz speed */
+
+/*
+ * Flash configuration, expect one 16 Megabyte Bank at most
+ */
+#define CFG_FLASH_BASE		0xFE000000
+#define CFG_FLASH_SIZE		0x02000000
+#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks      */
+#define CFG_MAX_FLASH_SECT	256	/* max num of sects on one chip */
+
+#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
+#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
+
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_FLASH_CFI
+#define CFG_FLASH_EMPTY_INFO
+
+/*
+ * Environment settings
+ */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_OFFSET		(2*128*1024)
+#define CFG_ENV_SIZE		0x2000
+#define CFG_ENV_SECT_SIZE       (128*1024)
+
+/*
+ * Memory map
+ *
+ * Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000
+ */
+#define CFG_MBAR			0xf0000000	/* DO NOT CHANGE this */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_DEFAULT_MBAR	0x80000000
+
+/* Use SRAM until RAM will be available */
+#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
+#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */
+
+
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_BASE    TEXT_BASE
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#   define CFG_RAMBOOT		1
+#endif
+
+#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC	1
+#define	CONFIG_PHY_ADDR		0x0
+/*
+ * GPIO configuration:
+ * PSC1,2,3 predefined as UART
+ * PCI disabled
+ * Ethernet 100 with MD
+ */
+#define CFG_GPS_PORT_CONFIG	0x00058444
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory	    */
+#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
+#else
+#  define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
+#define CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
+#define CFG_MEMTEST_END		0x01f00000	/* 1 ... 31 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x200000	/* default load address */
+
+#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+
+#define CONFIG_RTC_MPC5200	1	/* use internal MPC5200 RTC */
+
+/*
+ * Various low-level settings
+ */
+#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CFG_HID0_FINAL		HID0_ICE
+
+#define CFG_BOOTCS_START	CFG_FLASH_BASE
+#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
+#define CFG_BOOTCS_CFG		0x00047D01
+#define CFG_CS0_START		CFG_FLASH_BASE
+#define CFG_CS0_SIZE		CFG_FLASH_SIZE
+
+#define CFG_CS_BURST		0x00000000
+#define CFG_CS_DEADCYCLE	0x33333333
+
+#define CFG_RESET_ADDRESS	0x7f000000
+
+#endif /* __CONFIG_H */
--- a/include/configs/cmc_pu2.h
+++ b/include/configs/cmc_pu2.h
@@ -31,9 +31,13 @@

 #define AT91_SLOW_CLOCK		32768	/* slow clock */

-#define CONFIG_AT91RM9200DK	1	/* on an AT91RM9200DK Board	 */
-#define CONFIG_CMC_PU2		1	/* on an CMC_PU2 Board	 */
-#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */
+#define CONFIG_ARM920T		1	/* This is an ARM920T Core	*/
+#define CONFIG_AT91RM9200	1	/* It's an Atmel AT91RM9200 SoC	*/
+#define CONFIG_AT91RM9200DK	1	/* on an AT91RM9200DK Board	*/
+#define CONFIG_CMC_PU2		1	/* on an CMC_PU2 Board		*/
+#undef  CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/
+#define USE_920T_MMU		1
+
 #define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs	*/
 #define CONFIG_SETUP_MEMORY_TAGS 1
 #define CONFIG_INITRD_TAG	1
@@ -78,8 +82,6 @@

 #define CONFIG_BAUDRATE		9600

-#define CFG_AT91C_BRGR_DIVISOR	450	/* hardcode so no __divsi3 : AT91C_MASTER_CLOCK /(baudrate * 16) */
-
 /*
 * Hardware drivers
 */
--- a/Show More
+++ b/Show More
Author	SHA1	Message	Date
wdenk	9dd41a7b0c	* Fix debug code in omap5912osk flash driver * Add support for MPC8247 based "IDS8247" board.	2005-05-12 22:48:09 +00:00
wdenk	d44e14b5fc	Add support for 2 x TSEC interfaces on the TQM8540 board.	2005-05-10 15:51:35 +00:00
wdenk	ed16fefcba	On LWMON we must use the watchdog to reset the board as the CPU genereated HRESET pulse is too short to reset the external circuitry.	2005-05-09 10:17:32 +00:00
wdenk	931da93e0f	Add test tool to exercise SDRAM accesses in burst mode (as standalone program, MPC8xx/PowerPC only)	2005-05-07 19:06:32 +00:00
wdenk	412babe304	It's better to handle LZO and LZARI compression mdoes for JFFS2 with a single #define.	2005-05-05 09:51:44 +00:00
wdenk	60fc6cbbb7	Increase CFG_MONITOR_LEN for Rattler board to match actual code size.	2005-05-05 09:13:21 +00:00
wdenk	07cc099941	Major upate of JFFS2 code; now in sync with snapshot of MTD CVS of March 13, 2005); new configuration options CONFIG_JFFS2_LZO and CONFIG_JFFS2_LZARI are added. Both are undefined by default.	2005-05-05 00:04:14 +00:00
wdenk	cf8bc5773c	Fix problem with symbolic links in JFFS2 code.	2005-05-04 23:50:54 +00:00
wdenk	a710d4be80	Use linker ASSERT statement to prevent undetected overlapping of sections on PPChameleon board; other boards might use this, too.	2005-05-04 23:44:59 +00:00
wdenk	90dc67049d	README: add explanation about patch policy net/net.c: fix indentation	2005-05-03 14:12:25 +00:00
stroese	434cf850a4	* Patch by Stefan Roese, 03 May 2005: Update for P3G4 Fix problems in cmd_universe.c * Patch by Matthias Fuchs, 03 May 2005: Added missing variable declaration in cmd_nand.c Modified CFG_PCI_PTM1MS in configs/PLU405.h to map 128MB ram	2005-05-03 06:19:57 +00:00
stroese	81b83c9ecc	* Patch by Matthias Fuchs, 03 May 2005: Added missing variable declaration in cmd_nand.c Modified CFG_PCI_PTM1MS in configs/PLU405.h to map 128MB ram	2005-05-03 06:12:20 +00:00
stroese	dcb2f95a60	* Patch by Stefan Roese, 03 May 2005: Update for P3G4 Fix problems in cmd_universe.c	2005-05-03 06:06:41 +00:00
wdenk	9f709b6cee	Fix INKA4x0: use CS1 as gpio_wkup_6 output	2005-04-22 15:09:09 +00:00
wdenk	a63109281a	Fix bug in the SDRAM initialization code for canmb, IceCube and PM520 boards. Fix PHY address for canmb board.	2005-04-21 21:10:22 +00:00
wdenk	7cc1438d43	get rid of obsolete CFG_AT91C_BRGR_DIVISOR definition	2005-04-20 14:38:59 +00:00
wdenk	ec0ca73190	Cleanup serial console baudrate calculation on AT91RM9200	2005-04-20 12:36:05 +00:00
wdenk	b2323ea6f9	Auto-size RAM on canmb board. Cleanup.	2005-04-20 09:28:54 +00:00
stroese	fddae7b811	* Patch by Matthias Fuchs, 18 Apr 2005: Make PCI target address spaces on PMC405 and CPCI405 boards configurable via environment variables	2005-04-20 06:52:40 +00:00
wdenk	5e5f9ed254	Add support for canmb board	2005-04-13 23:15:10 +00:00
stroese	4c2a366db3	* Patch by Stefan Roese, 13 Apr 2005: Update for esd apc405	2005-04-13 10:08:39 +00:00
stroese	04e93ec979	Update for esd apc405	2005-04-13 10:06:07 +00:00
wdenk	2a8af18738	* Fixes for TQM8560 board: - fix clock rates - remove debug messages - fix flash sector protection * Patch by Steven Scholz, 07 Apr 2005: Fix warning in cpu/arm920t/at91rm9200/i2c.c	2005-04-13 10:02:42 +00:00
wdenk	e694e08a8b	Cleanup	2005-04-07 22:41:05 +00:00
wdenk	b77fad3b25	* Patch by Steven Scholz, 07 Apr 2005: Add i2c_reg_write() and i2c_reg_write() for at91rm9200 I2C * Patch by Steven Scholz, 07 Apr 2005: Fix compiler warning in altera.c * Patch by Ladislav Michl, 06 Apr 2005: Fix voiceblue configuration.	2005-04-07 22:36:40 +00:00
stroese	7ec2550238	* Patch by Stefan Roese, 06 Apr 2005: Updates for OCOTEA board: - Changed U-Boot size from 512kByte to 256kByte - Fixed flash driver to support boot from soldered user flash - Added README for switch from PIBS firmware to U-Boot	2005-04-07 05:35:12 +00:00
stroese	0a7c5391a0	Add PPC440GX Revision C	2005-04-07 05:33:41 +00:00
stroese	68e0236f7e	* Patch by Travis Sawyer, 05 Apr 2005: - Change timer frequency for ppc 440 from 10 ms to 1 ms. Problem found by Andrew Wozniak.	2005-04-07 05:32:44 +00:00
wdenk	a85f9f21aa	Patch by Steven Scholz, 06 Apr 2005: - creating SoC subdir for Atmel AT91RM9200 cpu/arm920t/at91rm9200 - moving code out of cpu/at91rm9200 into cpu/arm920t/at91rm9200	2005-04-06 13:52:31 +00:00
wdenk	20787e23b8	* Patches by Robert Whaley, 29 Nov 2004: - update the pxa-regs.h file for PXA27x chips - add PXA27x based ADSVIX board - add support for MMC on PXA27x processors * Patch by Andrew E. Mileski, 28 Nov 2004: Fix PPC4xx SPD SDRAM detection bug * Patch by Hiroshi Ito, 26 Nov 2004: Fix logic of "test -z" and "test -n" commands	2005-04-06 00:04:16 +00:00
wdenk	3c2b3d454d	* Patch by Ladislav Michl, 05 Apr 2005: Add support for VoiceBlue board. * Patch by Ladislav Michl, 05 Apr 2005: Fix netboot_common() prototypes. * Cleanup.	2005-04-05 23:32:21 +00:00
wdenk	b304c96871	Patches by Steven Scholz, 05 Apr 2005: - Use i.MX watchdog timer for reset_cpu() - Move reset_cpu() out of cpu/arm920t/start.S into the SoC specific subdirectories cpu/arm920t/imx/ and cpu/arm920t/s3c24x0/ (now in interupts.c)	2005-04-05 22:30:50 +00:00