* Patch by Detlev Zundel, 30 Jun 2005:

Fix LCD logo for lwmon board which got lost in the merge of 8xx and PXA LCD code

CHANGELOG

@@ -2,6 +2,72 @@
 Changes for U-Boot 1.1.3:
 ======================================================================
 
+* Patch by Stefan Roese, 1 Jul 2005:
+  Fix PHY address for CATcenter board (now correct!)
+
+* Patch by Stefan Roese, 30 Jun 2005:
+  Fix PHY addresses for PPChameleon and CATcenter boards
+  Change MAINTAINER for most esd boards
+
+* Patch by Detlev Zundel, 30 Jun 2005:
+  Fix LCD logo for lwmon board which got lost in the merge of 8xx and PXA LCD code
+
+* Fix baudrate calculation problem on MPC5200 systems
+
+* Add EEPROM and RTC support for HMI1001 board
+
+* Patch by Detlev Zundel, 20 Jun 2005:
+  Fix initialization of low active GPIO pins on inka4x0 board
+
+* Enable redundant environment, disable HW flash protection of
+  HMI1001 board
+
+* Patch by Travis Sawyer, 10 Jun 2005:
+  Initialize allocated dev and private hw structures
+  after their respective allocation in 440gx_enet.c
+
+* Patch by Steven Scholz, 10 Jun 2005:
+  Fix byteorder problems with second argument of "bootm" with
+  standalone images;
+
+* Add support for HMI1001 board
+
+* Disable "date" and "sntp" commands on TQM866M
+
+* Fix watchdog reset problems on LWMON board
+
+* Patch by Juergen Selent, 17 May 2005:
+  Add support for Funkwerk VoVPN gateway module.
+
+* Cleanup debug code for MPC8220 FEC driver
+
+* Extend burst mode RAM test program to take a loop count
+  (0 = infinite)
+
+* Use CONFIG_DRIVER_KS8695ETH to enable KS8695 ethernet driver on
+  those boards that use it.
+
+* Patches by Greg Ungerer, 19 May 2005:
+  - add support for the KS8695P (ARM 922 based) CPU
+  - add support for the OpenGear CM4008, CM4116 and CM4148 boards
+
+* Patch by Steven Scholz, 19 May 2005:
+  Add support for CONFIG_SERIAL_TAG on ARM boards
+
+* Add PCI support for Sorcery board.
+  Code cleanup (especially Sorcery / Alaska / Yukon serial driver).
+
+* Fix compile problems caused by new burst mode SDRAM test;
+  make port pins to trigger logic analyzer configurable
+
+* Fix timer handling on MPC85xx systems
+
+* Fix debug code in omap5912osk flash driver
+
+* Add support for MPC8247 based "IDS8247" board.
+
+* Add support for 2 x TSEC interfaces on the TQM8540 board.
+
 * On LWMON we must use the watchdog to reset the board as the CPU
   genereated HRESET pulse is too short to reset the external
   circuitry.

CREDITS

@@ -394,6 +394,10 @@ N: Rune Torgersen
 E: <runet@innovsys.com>
 D: Support for Motorola MPC8266ADS board
 
+N: Greg Ungerer
+E: greg.ungerer@opengear.com
+D: Support for ks8695 CPU, and OpenGear cmXXXX boards
+
 N: David Updegraff
 E: dave@cray.com
 D: Port to Cray L1 board; DHCP vendor extensions

MAINTAINERS

@@ -230,7 +230,7 @@ Daniel Poirot <dan.poirot@windriver.com>
 	sbc8240			MPC8240
 	sbc405			PPC405GP
 
-Stefan Roese <stefan.roese@esd-electronics.com>
+Matthias Fuchs <matthias.fuchs@esd-electronics.com>
 
 	ADCIOP			IOP480 (PPC401)
 	APC405			PPC405GP
@@ -298,6 +298,8 @@ Jon Loeliger <jdl@freescale.com>
 
 	MPC8540ADS		MPC8540
 	MPC8560ADS		MPC8560
+	MPC8541CDS		MPC8541
+	MPC8555CDS		MPC8555
 
 Dan Malek <dan@embeddededge.com>
 
@@ -413,6 +415,12 @@ Andrea Scian <andrea.scian@dave-tech.it>
 
 	B2				ARM7TDMI (S3C44B0X)
 
+Greg Ungerer <greg.ungerer@opengear.com>
+
+	cm4008			ks8695p
+	cm4116			ks8695p
+	cm4148			ks8695p
+
 Alex Züpke <azu@sysgo.de>
 
 	lart			SA1100
@@ -490,7 +498,7 @@ Yasushi Shoji <yashi@atmark-techno.com>
 #	Board			CPU					#
 #########################################################################
 
-Stefan Roese <stefan.roese@esd-electronics.com>
+Matthias Fuchs <matthias.fuchs@esd-electronics.com>
 
 	TASREG			MCF5249
 

MAKEALL

@@ -129,11 +129,11 @@ LIST_7xx="	\
 	BAB7xx		CPCI750		ELPPC				\
 "
 
-LIST_ppc="${LIST_5xx}  ${LIST_5xxx} \
-	  ${LIST_8xx}  \
-	  ${LIST_824x} ${LIST_8260} \
-	  ${LIST_85xx}	\
-	  ${LIST_4xx}		    \
+LIST_ppc="${LIST_5xx}  ${LIST_5xxx}		\
+	  ${LIST_8xx}				\
+	  ${LIST_8220} ${LIST_824x} ${LIST_8260} \
+	  ${LIST_85xx}				\
+	  ${LIST_4xx}				\
 	  ${LIST_74xx} ${LIST_7xx}"
 
 #########################################################################

Makefile

@@ -227,6 +227,10 @@ PATI_config:		unconfig
 #########################################################################
 ## MPC5xxx Systems
 #########################################################################
+
+hmi1001_config:         unconfig
+	@./mkconfig hmi1001 ppc mpc5xxx hmi1001
+
 Lite5200_config				\
 Lite5200_LOWBOOT_config			\
 Lite5200_LOWBOOT08_config		\
@@ -987,6 +991,9 @@ gw8260_config:	unconfig
 hymod_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8260 hymod
 
+IDS8247_config:	unconfig
+	@./mkconfig $(@:_config=) ppc mpc8260 ids8247
+
 IPHASE4539_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8260 iphase4539
 
@@ -1149,6 +1156,11 @@ TQM8265_AA_config:  unconfig
 	fi
 	@./mkconfig -a TQM8260 ppc mpc8260 tqm8260
 
+VoVPN-GW_66MHz_config	\
+VoVPN-GW_100MHz_config:		unconfig
+	@echo "#define CONFIG_CLKIN_$(word 2,$(subst _, ,$@))" > include/config.h
+	@./mkconfig -a VoVPN-GW ppc mpc8260 vovpn-gw funkwerk
+
 ZPC1900_config: unconfig
 	@./mkconfig $(@:_config=) ppc mpc8260 zpc1900
 
@@ -1404,6 +1416,12 @@ voiceblue_config:	unconfig
 	fi
 	@./mkconfig -a voiceblue arm arm925t voiceblue
 
+cm4008_config	:	unconfig
+	@./mkconfig $(@:_config=) arm arm920t cm4008 NULL ks8695
+
+cm41xx_config	:	unconfig
+	@./mkconfig $(@:_config=) arm arm920t cm41xx NULL ks8695
+
 #########################################################################
 ## S3C44B0 Systems
 #########################################################################

board/alaska/Makefile

@@ -24,7 +24,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= lib$(BOARD).a
 
-OBJS	:= $(BOARD).o flash.o extserial.o
+OBJS	:= $(BOARD).o flash.o
 
 $(LIB):	$(OBJS) $(SOBJS)
 	$(AR) crv $@ $(OBJS)

board/alaska/extserial.c

@@ -1,110 +0,0 @@
-/*
- * (C) Copyright 2004, Freescale, Inc
- * TsiChung Liew, Tsi-Chung.Liew@freescale.com.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-
-/*
- * Minimal serial functions needed to use one of the PSC ports
- * as serial console interface.
- */
-
-#include <common.h>
-#include <mpc8220.h>
-
-#if defined (CONFIG_EXTUART_CONSOLE)
-#   include <ns16550.h>
-
-#   define PADSERIAL_BAUD_115200   0x40
-#   define PADSERIAL_BAUD_57600    0x20
-#   define PADSERIAL_BAUD_9600     0
-#   define PADCARD_FREQ            18432000
-
-const NS16550_t com_port = (NS16550_t) CFG_NS16550_COM1;
-
-int ext_serial_init (void)
-{
-	DECLARE_GLOBAL_DATA_PTR;
-	volatile u8 *dipswitch = (volatile u8 *) (CFG_CPLD_BASE + 0x1002);
-	int baud_divisor;
-
-	/* Find out the baud rate speed on debug card dip switches */
-	if (*dipswitch & PADSERIAL_BAUD_115200)
-		gd->baudrate = 115200;
-	else if (*dipswitch & PADSERIAL_BAUD_57600)
-		gd->baudrate = 57600;
-	else
-		gd->baudrate = 9600;
-
-	/* Debug card frequency */
-	baud_divisor = PADCARD_FREQ / (16 * gd->baudrate);
-
-	NS16550_init (com_port, baud_divisor);
-
-	return (0);
-}
-
-void ext_serial_putc (const char c)
-{
-	if (c == '\n')
-		NS16550_putc (com_port, '\r');
-
-	NS16550_putc (com_port, c);
-}
-
-void ext_serial_puts (const char *s)
-{
-	while (*s) {
-		serial_putc (*s++);
-	}
-}
-
-int ext_serial_getc (void)
-{
-	return NS16550_getc (com_port);
-}
-
-int ext_serial_tstc (void)
-{
-	return NS16550_tstc (com_port);
-}
-
-void ext_serial_setbrg (void)
-{
-	DECLARE_GLOBAL_DATA_PTR;
-
-	volatile u8 *dipswitch = (volatile u8 *) (CFG_CPLD_BASE + 0x1002);
-	int baud_divisor;
-
-	/* Find out the baud rate speed on debug card dip switches */
-	if (*dipswitch & PADSERIAL_BAUD_115200)
-		gd->baudrate = 115200;
-	else if (*dipswitch & PADSERIAL_BAUD_57600)
-		gd->baudrate = 57600;
-	else
-		gd->baudrate = 9600;
-
-	/* Debug card frequency */
-	baud_divisor = PADCARD_FREQ / (16 * gd->baudrate);
-
-	NS16550_reinit (com_port, baud_divisor);
-}
-#endif /* CONFIG_EXTUART_CONSOLE */

board/cm4008/Makefile

@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2000, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= cm4008.o flash.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################

board/cm4008/cm4008.c

@@ -0,0 +1,101 @@
+/*
+ * (C) Copyright 2005
+ * Greg Ungerer, OpenGear Inc, <greg.ungerer@opengear.com>
+ *
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/platform.h>
+
+/* ------------------------------------------------------------------------- */
+
+#define	ks8695_read(a)	  *((volatile unsigned int *) (KS8695_IO_BASE+(a)))
+#define	ks8695_write(a,b) *((volatile unsigned int *) (KS8695_IO_BASE+(a))) = (b)
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+int env_flash_cmdline (void)
+{
+	unsigned char *sp = (unsigned char *) 0x0201c020;
+	unsigned char *ep;
+	int len;
+
+	/* Check if "erase" push button is depressed */
+	if ((ks8695_read(KS8695_GPIO_DATA) & 0x8) == 0) {
+		printf("### Entering network recovery mode...\n");
+		setenv("bootargs", "console=ttyAM0,115200 mem=16M initrd=0x400000,6M root=/dev/ram0");
+		setenv("bootcmd", "bootp 0x400000; gofsk 0x400000");
+		setenv("bootdelay", "2");
+		return 0;
+	}
+
+	/* Check for flash based kernel boot args to use as default */
+	for (ep = sp, len = 0; ((len < 1024) && (*ep != 0)); ep++, len++)
+		;
+
+	if ((len > 0) && (len <1024))
+		setenv("bootargs", sp);
+
+	return 0;
+}
+
+int board_late_init (void)
+{
+	return 0;
+}
+
+
+int board_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* arch number of CM4008 */
+	gd->bd->bi_arch_number = 624;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0x00000100;
+
+	/* power down all but port 0 on the switch */
+	ks8695_write(KS8695_SWITCH_LPPM12, 0x00000005);
+	ks8695_write(KS8695_SWITCH_LPPM34, 0x00050005);
+
+	return 0;
+}
+
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size  = PHYS_SDRAM_1_SIZE;
+
+	return (0);
+}

board/cm4008/config.mk

@@ -0,0 +1 @@
+TEXT_BASE = 0x00f00000

board/cm4008/flash.c

@@ -0,0 +1,409 @@
+/*
+ * (C) Copyright 2005
+ * Greg Ungerer, OpenGear Inc, greg.ungerer@opengear.com
+ *
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips */
+
+#define mb() __asm__ __volatile__ ("" : : : "memory")
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (unsigned char * addr, flash_info_t * info);
+static int write_data (flash_info_t * info, ulong dest, unsigned char data);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+void inline spin_wheel (void);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	int i;
+	ulong size = 0;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		switch (i) {
+		case 0:
+			flash_get_size ((unsigned char *) PHYS_FLASH_1, &flash_info[i]);
+			flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
+			break;
+		case 1:
+			/* ignore for now */
+			flash_info[i].flash_id = FLASH_UNKNOWN;
+			break;
+		default:
+			panic ("configured too many flash banks!\n");
+			break;
+		}
+		size += flash_info[i].size;
+	}
+
+	/* Protect monitor and environment sectors
+	 */
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_FLASH_BASE,
+		       CFG_FLASH_BASE + _bss_start - _armboot_start,
+		       &flash_info[0]);
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN)
+		return;
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
+			info->protect[i] = 0;
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F128J3A:
+		printf ("28F128J3A\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i], info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (unsigned char * addr, flash_info_t * info)
+{
+	volatile unsigned char value;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x5555] = 0xAA;
+	addr[0x2AAA] = 0x55;
+	addr[0x5555] = 0x90;
+
+	mb ();
+	value = addr[0];
+
+	switch (value) {
+
+	case (unsigned char)INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = 0xFF;	/* restore read mode */
+		return (0);	/* no or unknown flash  */
+	}
+
+	mb ();
+	value = addr[2];	/* device ID            */
+
+	switch (value) {
+
+	case (unsigned char)INTEL_ID_28F640J3A:
+		info->flash_id += FLASH_28F640J3A;
+		info->sector_count = 64;
+		info->size = 0x00800000;
+		break;		/* => 8 MB     */
+
+	case (unsigned char)INTEL_ID_28F128J3A:
+		info->flash_id += FLASH_28F128J3A;
+		info->sector_count = 128;
+		info->size = 0x01000000;
+		break;		/* => 16 MB     */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+			info->sector_count, CFG_MAX_FLASH_SECT);
+		info->sector_count = CFG_MAX_FLASH_SECT;
+	}
+
+	addr[0] = 0xFF;	/* restore read mode */
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong type;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot)
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+	else
+		printf ("\n");
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			volatile unsigned char *addr;
+			unsigned char status;
+
+			printf ("Erasing sector %2d ... ", sect);
+
+			/* arm simple, non interrupt dependent timer */
+			reset_timer_masked ();
+
+			addr = (volatile unsigned char *) (info->start[sect]);
+			*addr = 0x50;	/* clear status register */
+			*addr = 0x20;	/* erase setup */
+			*addr = 0xD0;	/* erase confirm */
+
+			while (((status = *addr) & 0x80) != 0x80) {
+				if (get_timer_masked () >
+				    CFG_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					*addr = 0xB0;	/* suspend erase */
+					*addr = 0xFF;	/* reset to read mode */
+					rcode = 1;
+					break;
+				}
+			}
+
+			*addr = 0x50;	/* clear status register cmd */
+			*addr = 0xFF;	/* resest to read mode */
+
+			printf (" done\n");
+		}
+	}
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	unsigned char data;
+	int count, i, l, rc, port_width;
+
+	if (info->flash_id == FLASH_UNKNOWN)
+		return 4;
+
+	wp = addr;
+	port_width = 1;
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < port_width && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < port_width; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_data (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	count = 0;
+	while (cnt >= port_width) {
+		data = 0;
+		for (i = 0; i < port_width; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+		cnt -= port_width;
+		if (count++ > 0x800) {
+			spin_wheel ();
+			count = 0;
+		}
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < port_width; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_data (info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t * info, ulong dest, unsigned char data)
+{
+	volatile unsigned char *addr = (volatile unsigned char *) dest;
+	ulong status;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf ("not erased at %08lx (%lx)\n", (ulong) addr,
+			(ulong) * addr);
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	*addr = 0x40;	/* write setup */
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();
+
+	/* wait while polling the status register */
+	while (((status = *addr) & 0x80) != 0x80) {
+		if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+			*addr = 0xFF;	/* restore read mode */
+			return (1);
+		}
+	}
+
+	*addr = 0xFF;	/* restore read mode */
+
+	return (0);
+}
+
+void inline spin_wheel (void)
+{
+	static int p = 0;
+	static char w[] = "\\/-";
+
+	printf ("\010%c", w[p]);
+	(++p == 3) ? (p = 0) : 0;
+}

board/cm4008/u-boot.lds

@@ -0,0 +1,55 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/arm920t/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}

board/cm41xx/Makefile

@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2000, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= cm41xx.o flash.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################

board/cm41xx/cm41xx.c

@@ -0,0 +1,101 @@
+/*
+ * (C) Copyright 2005
+ * Greg Ungerer, OpenGear Inc, <greg.ungerer@opengear.com>
+ *
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/platform.h>
+
+/* ------------------------------------------------------------------------- */
+
+#define	ks8695_read(a)	  *((volatile unsigned int *) (KS8695_IO_BASE+(a)))
+#define	ks8695_write(a,b) *((volatile unsigned int *) (KS8695_IO_BASE+(a))) = (b)
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+int env_flash_cmdline (void)
+{
+	unsigned char *sp = (unsigned char *) 0x0201c020;
+	unsigned char *ep;
+	int len;
+
+	/* Check if "erase" push button is depressed */
+	if ((ks8695_read(KS8695_GPIO_DATA) & 0x8) == 0) {
+		printf("### Entering network recovery mode...\n");
+		setenv("bootargs", "console=ttyAM0,115200 mem=32M initrd=0x400000,8M root=/dev/ram0");
+		setenv("bootcmd", "bootp 0x400000; gofsk 0x400000");
+		setenv("bootdelay", "2");
+		return 0;
+	}
+
+	/* Check for flash based kernel boot args to use as default */
+	for (ep = sp, len = 0; ((len < 1024) && (*ep != 0)); ep++, len++)
+		;
+
+	if ((len > 0) && (len <1024))
+		setenv("bootargs", sp);
+
+	return 0;
+}
+
+int board_late_init (void)
+{
+	return 0;
+}
+
+
+int board_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* arch number of CM41xx */
+	gd->bd->bi_arch_number = 672;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0x00000100;
+
+	/* power down all but port 0 on the switch */
+	ks8695_write(KS8695_SWITCH_LPPM12, 0x00000005);
+	ks8695_write(KS8695_SWITCH_LPPM34, 0x00050005);
+
+	return 0;
+}
+
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size  = PHYS_SDRAM_1_SIZE;
+
+	return (0);
+}

board/cm41xx/config.mk

@@ -0,0 +1 @@
+TEXT_BASE = 0x00f00000

board/cm41xx/flash.c

@@ -0,0 +1,409 @@
+/*
+ * (C) Copyright 2005
+ * Greg Ungerer, OpenGear Inc, greg.ungerer@opengear.com
+ *
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips */
+
+#define mb() __asm__ __volatile__ ("" : : : "memory")
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (unsigned char * addr, flash_info_t * info);
+static int write_data (flash_info_t * info, ulong dest, unsigned char data);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+void inline spin_wheel (void);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	int i;
+	ulong size = 0;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		switch (i) {
+		case 0:
+			flash_get_size ((unsigned char *) PHYS_FLASH_1, &flash_info[i]);
+			flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
+			break;
+		case 1:
+			/* ignore for now */
+			flash_info[i].flash_id = FLASH_UNKNOWN;
+			break;
+		default:
+			panic ("configured too many flash banks!\n");
+			break;
+		}
+		size += flash_info[i].size;
+	}
+
+	/* Protect monitor and environment sectors
+	 */
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_FLASH_BASE,
+		       CFG_FLASH_BASE + _bss_start - _armboot_start,
+		       &flash_info[0]);
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN)
+		return;
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
+			info->protect[i] = 0;
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F128J3A:
+		printf ("28F128J3A\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i], info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (unsigned char * addr, flash_info_t * info)
+{
+	volatile unsigned char value;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x5555] = 0xAA;
+	addr[0x2AAA] = 0x55;
+	addr[0x5555] = 0x90;
+
+	mb ();
+	value = addr[0];
+
+	switch (value) {
+
+	case (unsigned char)INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = 0xFF;	/* restore read mode */
+		return (0);	/* no or unknown flash  */
+	}
+
+	mb ();
+	value = addr[2];	/* device ID            */
+
+	switch (value) {
+
+	case (unsigned char)INTEL_ID_28F640J3A:
+		info->flash_id += FLASH_28F640J3A;
+		info->sector_count = 64;
+		info->size = 0x00800000;
+		break;		/* => 8 MB     */
+
+	case (unsigned char)INTEL_ID_28F128J3A:
+		info->flash_id += FLASH_28F128J3A;
+		info->sector_count = 128;
+		info->size = 0x01000000;
+		break;		/* => 16 MB     */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+			info->sector_count, CFG_MAX_FLASH_SECT);
+		info->sector_count = CFG_MAX_FLASH_SECT;
+	}
+
+	addr[0] = 0xFF;	/* restore read mode */
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong type;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot)
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+	else
+		printf ("\n");
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			volatile unsigned char *addr;
+			unsigned char status;
+
+			printf ("Erasing sector %2d ... ", sect);
+
+			/* arm simple, non interrupt dependent timer */
+			reset_timer_masked ();
+
+			addr = (volatile unsigned char *) (info->start[sect]);
+			*addr = 0x50;	/* clear status register */
+			*addr = 0x20;	/* erase setup */
+			*addr = 0xD0;	/* erase confirm */
+
+			while (((status = *addr) & 0x80) != 0x80) {
+				if (get_timer_masked () >
+				    CFG_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					*addr = 0xB0;	/* suspend erase */
+					*addr = 0xFF;	/* reset to read mode */
+					rcode = 1;
+					break;
+				}
+			}
+
+			*addr = 0x50;	/* clear status register cmd */
+			*addr = 0xFF;	/* resest to read mode */
+
+			printf (" done\n");
+		}
+	}
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	unsigned char data;
+	int count, i, l, rc, port_width;
+
+	if (info->flash_id == FLASH_UNKNOWN)
+		return 4;
+
+	wp = addr;
+	port_width = 1;
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < port_width && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < port_width; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_data (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	count = 0;
+	while (cnt >= port_width) {
+		data = 0;
+		for (i = 0; i < port_width; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+		cnt -= port_width;
+		if (count++ > 0x800) {
+			spin_wheel ();
+			count = 0;
+		}
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < port_width; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_data (info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t * info, ulong dest, unsigned char data)
+{
+	volatile unsigned char *addr = (volatile unsigned char *) dest;
+	ulong status;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf ("not erased at %08lx (%lx)\n", (ulong) addr,
+			(ulong) * addr);
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	*addr = 0x40;	/* write setup */
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();
+
+	/* wait while polling the status register */
+	while (((status = *addr) & 0x80) != 0x80) {
+		if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+			*addr = 0xFF;	/* restore read mode */
+			return (1);
+		}
+	}
+
+	*addr = 0xFF;	/* restore read mode */
+
+	return (0);
+}
+
+void inline spin_wheel (void)
+{
+	static int p = 0;
+	static char w[] = "\\/-";
+
+	printf ("\010%c", w[p]);
+	(++p == 3) ? (p = 0) : 0;
+}

board/cm41xx/u-boot.lds

@@ -0,0 +1,55 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/arm920t/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}

board/funkwerk/vovpn-gw/Makefile

@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o flash.o m88e6060.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################

board/funkwerk/vovpn-gw/config.mk

@@ -0,0 +1,21 @@
+# (C) Copyright 2004
+# Elmeg Communications Systems GmbH, Juergen Selent (j.selent@elmeg.de)
+#
+# Support for the Elmeg VoVPN Gateway Module
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+TEXT_BASE = 0xfff00000

board/funkwerk/vovpn-gw/flash.c

@@ -0,0 +1,506 @@
+/*
+ * (C) Copyright 2004
+ * Elmeg Communications Systems GmbH, Juergen Selent (j.selent@elmeg.de)
+ *
+ * Support for the Elmeg VoVPN Gateway Module
+ * ------------------------------------------
+ * This is a signle bank flashdriver for INTEL 28F320J3, 28F640J3
+ * and 28F128J3A flashs working in 8 Bit mode.
+ *
+ * Most of this code is taken from existing u-boot source code.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+flash_info_t				flash_info[CFG_MAX_FLASH_BANKS];
+
+#define FLASH_CMD_READ_ID		0x90
+#define FLASH_CMD_READ_STATUS		0x70
+#define FLASH_CMD_RESET			0xff
+#define FLASH_CMD_BLOCK_ERASE		0x20
+#define FLASH_CMD_ERASE_CONFIRM		0xd0
+#define FLASH_CMD_CLEAR_STATUS		0x50
+#define FLASH_CMD_SUSPEND_ERASE		0xb0
+#define FLASH_CMD_WRITE			0x40
+#define FLASH_CMD_WRITE_BUFF		0xe8
+#define FLASH_CMD_PROG_RESUME		0xd0
+#define FLASH_CMD_PROTECT		0x60
+#define FLASH_CMD_PROTECT_SET		0x01
+#define FLASH_CMD_PROTECT_CLEAR		0xd0
+#define FLASH_STATUS_DONE		0x80
+
+#define FLASH_WRITE_BUFFER_SIZE		32
+
+#ifdef CFG_FLASH_16BIT
+#define FLASH_WORD_SIZE			unsigned short
+#define FLASH_ID_MASK			0xffff
+#define FLASH_CMD_ADDR_SHIFT		0
+#else
+#define FLASH_WORD_SIZE			unsigned char
+#define FLASH_ID_MASK			0xff
+/* A0 is not used in either 8x or 16x for READ ID */
+#define FLASH_CMD_ADDR_SHIFT		1
+#endif
+
+
+static unsigned long
+flash_get(volatile FLASH_WORD_SIZE *addr, flash_info_t *info)
+{
+	volatile FLASH_WORD_SIZE *p;
+	FLASH_WORD_SIZE value;
+	int i;
+
+	addr[0] = FLASH_CMD_READ_ID;
+
+	/* manufactor */
+	value = addr[0 << FLASH_CMD_ADDR_SHIFT];
+	switch (value) {
+	case (INTEL_MANUFACT & FLASH_ID_MASK):
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		*addr = FLASH_CMD_RESET;
+		return (0);
+
+	}
+
+	/* device */
+	value = addr[1 << FLASH_CMD_ADDR_SHIFT];
+	switch (value) {
+	case (INTEL_ID_28F320J3A & FLASH_ID_MASK):
+		info->flash_id += FLASH_28F320J3A;
+		info->sector_count = 32;
+		info->size = 0x00400000;
+		break;
+	case (INTEL_ID_28F640J3A & FLASH_ID_MASK):
+		info->flash_id += FLASH_28F640J3A;
+		info->sector_count = 64;
+		info->size = 0x00800000;
+		break;
+	case (INTEL_ID_28F128J3A & FLASH_ID_MASK):
+		info->flash_id += FLASH_28F128J3A;
+		info->sector_count = 128;
+		info->size = 0x01000000;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		*addr = FLASH_CMD_RESET;
+		return (0);
+	}
+
+	/* setup sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		info->start[i] = (unsigned long)addr + (i * info->size/info->sector_count);
+	}
+
+	/* check protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		p = (volatile FLASH_WORD_SIZE *)(info->start[i]);
+		info->protect[i] = p[2 << FLASH_CMD_ADDR_SHIFT] & 1;
+	}
+
+	/* reset bank */
+	*addr = FLASH_CMD_RESET;
+	return (info->size);
+}
+
+unsigned long
+flash_init(void)
+{
+	unsigned long	size;
+	int		i;
+
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+	size = flash_get((volatile FLASH_WORD_SIZE *)CFG_FLASH_BASE, &flash_info[0]);
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH Size=0x%08lx\n", size);
+		return (0);
+	}
+
+	/* always protect 1 sector containing the HRCW */
+	flash_protect(FLAG_PROTECT_SET,
+		      flash_info[0].start[0],
+		      flash_info[0].start[1] - 1,
+		      &flash_info[0]);
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_MONITOR_FLASH,
+		      CFG_MONITOR_FLASH+CFG_MONITOR_LEN-1,
+		      &flash_info[0]);
+#endif
+#ifdef	CFG_ENV_IS_IN_FLASH
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_ENV_ADDR,
+		      CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1,
+		      &flash_info[0]);
+#endif
+	return (size);
+}
+
+void
+flash_print_info(flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:	printf ("INTEL ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F320J3A:	printf ("28F320JA3 (32 Mbit)\n");
+				break;
+	case FLASH_28F640J3A:	printf ("28F640JA3 (64 Mbit)\n");
+				break;
+	case FLASH_28F128J3A:	printf ("28F128JA3 (128 Mbit)\n");
+				break;
+	default:		printf ("Unknown Chip Type");
+				break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+}
+
+int
+flash_erase(flash_info_t *info, int s_first, int s_last)
+{
+	unsigned long start, now, last;
+	int flag, prot, sect;
+	volatile FLASH_WORD_SIZE *addr;
+	FLASH_WORD_SIZE status;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return (1);
+	}
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("Cannot erase unknown flash - aborted\n");
+		return (1);
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+	} else {
+		printf ("\n");
+	}
+
+	start = get_timer (0);
+	last  = start;
+
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect]) {
+			continue;
+		}
+
+		addr = (volatile FLASH_WORD_SIZE *)(info->start[sect]);
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+
+#ifdef DEBUG
+		printf("Erase sector %d at start addr 0x%08X", sect, (unsigned int)info->start[sect]);
+#endif
+
+		*addr = FLASH_CMD_CLEAR_STATUS;
+		*addr = FLASH_CMD_BLOCK_ERASE;
+		*addr = FLASH_CMD_ERASE_CONFIRM;
+
+		/* re-enable interrupts if necessary */
+		if (flag) {
+			enable_interrupts();
+		}
+
+		/* wait at least 80us - let's wait 1 ms */
+		udelay (1000);
+
+		while (((status = *addr) & FLASH_STATUS_DONE) != FLASH_STATUS_DONE) {
+			if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+				printf("Flash erase timeout at address %lx\n", info->start[sect]);
+				*addr = FLASH_CMD_SUSPEND_ERASE;
+				*addr = FLASH_CMD_RESET;
+				return (1);
+			}
+
+			/* show that we're waiting */
+			if ((now - last) > 1000) {	/* every second */
+				putc ('.');
+				last = now;
+			}
+		}
+		*addr = FLASH_CMD_RESET;
+	}
+	printf (" done\n");
+	return (0);
+}
+
+static int
+write_buff2( volatile FLASH_WORD_SIZE *dst,
+	     volatile FLASH_WORD_SIZE *src,
+	     unsigned long cnt )
+{
+	unsigned long start;
+	FLASH_WORD_SIZE status;
+	int flag, i;
+
+	start = get_timer (0);
+	while (1) {
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+		dst[0] = FLASH_CMD_WRITE_BUFF;
+		if ((status = *dst) & FLASH_STATUS_DONE) {
+			break;
+		}
+
+		/* re-enable interrupts if necessary */
+		if (flag) {
+			enable_interrupts();
+		}
+
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			return (-1);
+		}
+	}
+	dst[0] = (FLASH_WORD_SIZE)(cnt - 1);
+	for (i=0; i<cnt; i++) {
+		dst[i] = src[i];
+	}
+	dst[0] = FLASH_CMD_PROG_RESUME;
+
+	if (flag) {
+		enable_interrupts();
+	}
+
+	return( 0 );
+}
+
+static int
+poll_status( volatile FLASH_WORD_SIZE *addr )
+{
+	unsigned long start;
+
+	start = get_timer (0);
+	/* wait for error or finish */
+	while (1) {
+		if (*addr == FLASH_STATUS_DONE) {
+			if (*addr == FLASH_STATUS_DONE) {
+				break;
+			}
+		}
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			*addr = FLASH_CMD_RESET;
+			return (-1);
+		}
+	}
+	*addr = FLASH_CMD_RESET;
+	return (0);
+}
+
+/*
+ * write_buff return values:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+int
+write_buff(flash_info_t *info, uchar *src, ulong udst, ulong cnt)
+{
+	volatile FLASH_WORD_SIZE *addr, *dst;
+	unsigned long bcnt;
+	int flag, i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return (4);
+	}
+
+	addr = (volatile FLASH_WORD_SIZE *)(info->start[0]);
+	dst = (volatile FLASH_WORD_SIZE *) udst;
+
+#ifdef CFG_FLASH_16BIT
+#error NYI
+#else
+	while (cnt > 0) {
+		/* Check if buffer write is possible */
+		if (cnt > 1 && (((unsigned long)dst & (FLASH_WRITE_BUFFER_SIZE - 1)) == 0)) {
+			bcnt = cnt > FLASH_WRITE_BUFFER_SIZE ? FLASH_WRITE_BUFFER_SIZE : cnt;
+			/* Check if Flash is (sufficiently) erased */
+			for (i=0; i<bcnt; i++) {
+				if ((dst[i] & src[i]) != src[i]) {
+					return (2);
+				}
+			}
+			if (write_buff2( dst,src,bcnt ) != 0) {
+				addr[0] = FLASH_CMD_READ_STATUS;
+			}
+			if (poll_status( dst ) != 0) {
+				return (1);
+			}
+			cnt -= bcnt;
+			dst += bcnt;
+			src += bcnt;
+			continue;
+		}
+
+		/* Check if Flash is (sufficiently) erased */
+		if ((*dst & *src) != *src) {
+			return (2);
+		}
+
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+		addr[0] = FLASH_CMD_ERASE_CONFIRM;
+		addr[0] = FLASH_CMD_WRITE;
+		*dst++ = *src++;
+		/* re-enable interrupts if necessary */
+		if (flag) {
+			enable_interrupts();
+		}
+
+		if (poll_status( dst ) != 0) {
+			return (1);
+		}
+		cnt --;
+	}
+#endif
+	return (0);
+}
+
+int
+flash_real_protect(flash_info_t *info, long sector, int prot)
+{
+	volatile FLASH_WORD_SIZE *addr;
+	unsigned long start;
+
+	addr = (volatile FLASH_WORD_SIZE *)(info->start[sector]);
+	*addr = FLASH_CMD_CLEAR_STATUS;
+	*addr = FLASH_CMD_PROTECT;
+
+	if(prot) {
+		*addr = FLASH_CMD_PROTECT_SET;
+	} else {
+		*addr = FLASH_CMD_PROTECT_CLEAR;
+	}
+
+	/* wait for error or finish */
+	start = get_timer (0);
+	while(!(addr[0] & FLASH_STATUS_DONE)){
+		if (get_timer(start) > CFG_FLASH_ERASE_TOUT) {
+			printf("Flash protect timeout at address %lx\n",  info->start[sector]);
+			addr[0] = FLASH_CMD_RESET;
+			return (1);
+		}
+	}
+
+	/* Set software protect flag */
+	info->protect[sector] = prot;
+	*addr = FLASH_CMD_RESET;
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ * Support for flash file system (JFFS2)
+ *
+ * We use custom partition info function because we have to fit the
+ * file system image between first sector (containing hard reset
+ * configuration word) and the sector containing U-Boot image. Standard
+ * partition info function does not allow for last sector specification
+ * and assumes that the file system occupies flash bank up to and
+ * including bank's last sector.
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CFG_JFFS_CUSTOM_PART)
+#error TODO
+
+#ifndef CFG_JFFS2_FIRST_SECTOR
+#define CFG_JFFS2_FIRST_SECTOR 0
+#endif
+#ifndef CFG_JFFS2_FIRST_BANK
+#define CFG_JFFS2_FIRST_BANK 0
+#endif
+#ifndef CFG_JFFS2_NUM_BANKS
+#define CFG_JFFS2_NUM_BANKS 1
+#endif
+#define CFG_JFFS2_LAST_BANK (CFG_JFFS2_FIRST_BANK + CFG_JFFS2_NUM_BANKS - 1)
+
+#include <jffs2/jffs2.h>
+
+static struct part_info partition;
+
+struct part_info *jffs2_part_info(int part_num)
+{
+	int i;
+
+	if (part_num == 0) {
+		if (partition.usr_priv == 0) {
+			partition.offset =
+				(unsigned char *) flash_info[CFG_JFFS2_FIRST_BANK].start[CFG_JFFS2_FIRST_SECTOR];
+			for (i = CFG_JFFS2_FIRST_BANK; i <= CFG_JFFS2_LAST_BANK; i++)
+				partition.size += flash_info[i].size;
+			partition.size -=
+				flash_info[CFG_JFFS2_FIRST_BANK].start[CFG_JFFS2_FIRST_SECTOR] -
+				flash_info[CFG_JFFS2_FIRST_BANK].start[0];
+#ifdef CFG_JFFS2_LAST_SECTOR
+			i = flash_info[CFG_JFFS2_LAST_BANK].sector_count - 1;
+			partition.size -=
+				flash_info[CFG_JFFS2_LAST_BANK].start[i] -
+				flash_info[CFG_JFFS2_LAST_BANK].start[CFG_JFFS2_LAST_SECTOR];
+#endif
+
+			partition.usr_priv = (void *)1;
+		}
+		return &partition;
+	}
+	return 0;
+}
+
+#endif /* JFFS2 */

board/funkwerk/vovpn-gw/m88e6060.c

@@ -0,0 +1,262 @@
+/*
+ * (C) Copyright 2004
+ * Elmeg Communications Systems GmbH, Juergen Selent (j.selent@elmeg.de)
+ *
+ * Support for the Elmeg VoVPN Gateway Module
+ * ------------------------------------------
+ * Initialize Marvell M88E6060 Switch
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc8260.h>
+#include <asm/m8260_pci.h>
+#include <net.h>
+#include <miiphy.h>
+
+#include "m88e6060.h"
+
+#if (CONFIG_COMMANDS & CFG_CMD_NET)
+static int		prtTab[M88X_PRT_CNT] = { 8, 9, 10, 11, 12, 13 };
+static int		phyTab[M88X_PHY_CNT] = { 0, 1, 2, 3, 4 };
+
+static m88x_regCfg_t	prtCfg0[] = {
+	{  4, 0x3e7c, 0x8000 },
+	{  4, 0x3e7c, 0x8003 },
+	{  6, 0x0fc0, 0x001e },
+	{ -1, 0xffff, 0x0000 }
+};
+
+static m88x_regCfg_t	prtCfg1[] = {
+	{  4, 0x3e7c, 0x8000 },
+	{  4, 0x3e7c, 0x8003 },
+	{  6, 0x0fc0, 0x001d },
+	{ -1, 0xffff, 0x0000 }
+};
+
+static m88x_regCfg_t	prtCfg2[] = {
+	{  4, 0x3e7c, 0x8000 },
+	{  4, 0x3e7c, 0x8003 },
+	{  6, 0x0fc0, 0x001b },
+	{ -1, 0xffff, 0x0000 }
+};
+
+static m88x_regCfg_t	prtCfg3[] = {
+	{  4, 0x3e7c, 0x8000 },
+	{  4, 0x3e7c, 0x8003 },
+	{  6, 0x0fc0, 0x0017 },
+	{ -1, 0xffff, 0x0000 }
+};
+
+static m88x_regCfg_t	prtCfg4[] = {
+	{  4, 0x3e7c, 0x8000 },
+	{  4, 0x3e7c, 0x8003 },
+	{  6, 0x0fc0, 0x000f },
+	{ -1, 0xffff, 0x0000 }
+};
+
+static m88x_regCfg_t	*prtCfg[M88X_PRT_CNT] = {
+	prtCfg0,prtCfg1,prtCfg2,prtCfg3,prtCfg4,NULL
+};
+
+static m88x_regCfg_t	phyCfgX[] = {
+	{  4, 0xfa1f, 0x01e0 },
+	{  0, 0x213f, 0x1200 },
+	{ 24, 0x81ff, 0x1200 },
+	{ -1, 0xffff, 0x0000 }
+};
+
+static m88x_regCfg_t	*phyCfg[M88X_PHY_CNT] = {
+	phyCfgX,phyCfgX,phyCfgX,phyCfgX,NULL
+};
+
+#if 0
+static void
+m88e6060_dump( int devAddr )
+{
+	int		i, j;
+	unsigned short	val[6];
+
+	printf( "M88E6060 Register Dump\n" );
+	printf( "====================================\n" );
+	printf( "PortNo    0    1    2    3    4    5\n" );
+	for (i=0; i<6; i++)
+		miiphy_read( devAddr+prtTab[i],M88X_PRT_STAT,&val[i] );
+	printf( "STAT   %04hx %04hx %04hx %04hx %04hx %04hx\n",
+		val[0],val[1],val[2],val[3],val[4],val[5] );
+
+	for (i=0; i<6; i++)
+		miiphy_read( devAddr+prtTab[i],M88X_PRT_ID,&val[i] );
+	printf( "ID     %04hx %04hx %04hx %04hx %04hx %04hx\n",
+		val[0],val[1],val[2],val[3],val[4],val[5] );
+
+	for (i=0; i<6; i++)
+		miiphy_read( devAddr+prtTab[i],M88X_PRT_CNTL,&val[i] );
+	printf( "CNTL   %04hx %04hx %04hx %04hx %04hx %04hx\n",
+		val[0],val[1],val[2],val[3],val[4],val[5] );
+
+	for (i=0; i<6; i++)
+		miiphy_read( devAddr+prtTab[i],M88X_PRT_VLAN,&val[i] );
+	printf( "VLAN   %04hx %04hx %04hx %04hx %04hx %04hx\n",
+		val[0],val[1],val[2],val[3],val[4],val[5] );
+
+	for (i=0; i<6; i++)
+		miiphy_read( devAddr+prtTab[i],M88X_PRT_PAV,&val[i] );
+	printf( "PAV    %04hx %04hx %04hx %04hx %04hx %04hx\n",
+		val[0],val[1],val[2],val[3],val[4],val[5] );
+
+	for (i=0; i<6; i++)
+		miiphy_read( devAddr+prtTab[i],M88X_PRT_RX,&val[i] );
+	printf( "RX     %04hx %04hx %04hx %04hx %04hx %04hx\n",
+		val[0],val[1],val[2],val[3],val[4],val[5] );
+
+	for (i=0; i<6; i++)
+		miiphy_read( devAddr+prtTab[i],M88X_PRT_TX,&val[i] );
+	printf( "TX     %04hx %04hx %04hx %04hx %04hx %04hx\n",
+		val[0],val[1],val[2],val[3],val[4],val[5] );
+
+	printf( "------------------------------------\n" );
+	printf( "PhyNo     0    1    2    3    4\n" );
+	for (i=0; i<9; i++) {
+		for (j=0; j<5; j++) {
+			miiphy_read( devAddr+phyTab[j],i,&val[j] );
+		}
+		printf( "0x%02x   %04hx %04hx %04hx %04hx %04hx\n",
+			i,val[0],val[1],val[2],val[3],val[4] );
+	}
+	for (i=0x10; i<0x1d; i++) {
+		for (j=0; j<5; j++) {
+			miiphy_read( devAddr+phyTab[j],i,&val[j] );
+		}
+		printf( "0x%02x   %04hx %04hx %04hx %04hx %04hx\n",
+			i,val[0],val[1],val[2],val[3],val[4] );
+	}
+}
+#endif
+
+int
+m88e6060_initialize( int devAddr )
+{
+	static char	*_f = "m88e6060_initialize:";
+	m88x_regCfg_t	*p;
+	int		err;
+	int		i;
+	unsigned short	val;
+
+	/*** reset all phys into powerdown ************************************/
+	for (i=0, err=0; i<M88X_PHY_CNT; i++) {
+		err += miiphy_read( devAddr+phyTab[i],M88X_PHY_CNTL,&val );
+		/* keep SpeedLSB, Duplex */
+		val &= 0x2100;
+		/* set SWReset, AnegEn, PwrDwn, RestartAneg */
+		val |= 0x9a00;
+		err += miiphy_write( devAddr+phyTab[i],M88X_PHY_CNTL,val );
+	}
+	if (err) {
+		printf( "%s [ERR] reset phys\n",_f );
+		return( -1 );
+	}
+
+	/*** disable all ports ************************************************/
+	for (i=0, err=0; i<M88X_PRT_CNT; i++) {
+		err += miiphy_read( devAddr+prtTab[i],M88X_PRT_CNTL,&val );
+		val &= 0xfffc;
+		err += miiphy_write( devAddr+prtTab[i],M88X_PRT_CNTL,val );
+	}
+	if (err) {
+		printf( "%s [ERR] disable ports\n",_f );
+		return( -1 );
+	}
+
+	/*** initialize switch ************************************************/
+	/* set switch mac addr */
+#define ea eth_get_dev()->enetaddr
+	val = (ea[4] <<  8) | ea[5];
+	err = miiphy_write( devAddr+15,M88X_GLB_MAC45,val );
+	val = (ea[2] <<  8) | ea[3];
+	err += miiphy_write( devAddr+15,M88X_GLB_MAC23,val );
+	val = (ea[0] <<  8) | ea[1];
+#undef ea
+	val &= 0xfeff;		/* clear DiffAddr */
+	err += miiphy_write( devAddr+15,M88X_GLB_MAC01,val );
+	if (err) {
+		printf( "%s [ERR] switch mac address register\n",_f );
+		return( -1 );
+	}
+
+	/* !DiscardExcessive, MaxFrameSize, CtrMode */
+	err = miiphy_read( devAddr+15,M88X_GLB_CNTL,&val );
+	val &= 0xd870;
+	val |= 0x0500;
+	err += miiphy_write( devAddr+15,M88X_GLB_CNTL,val );
+	if (err) {
+		printf( "%s [ERR] switch global control register\n",_f );
+		return( -1 );
+	}
+
+	/* LernDis off, ATUSize 1024, AgeTime 5min */
+	err = miiphy_read( devAddr+15,M88X_ATU_CNTL,&val );
+	val &= 0x000f;
+	val |= 0x2130;
+	err += miiphy_write( devAddr+15,M88X_ATU_CNTL,val );
+	if (err) {
+		printf( "%s [ERR] atu control register\n",_f );
+		return( -1 );
+	}
+
+	/*** initialize ports *************************************************/
+	for (i=0; i<M88X_PRT_CNT; i++) {
+		if ((p = prtCfg[i]) == NULL) {
+			continue;
+		}
+		while (p->reg != -1) {
+			err = 0;
+			err += miiphy_read( devAddr+prtTab[i],p->reg,&val );
+			val &= p->msk;
+			val |= p->val;
+			err += miiphy_write( devAddr+prtTab[i],p->reg,val );
+			if (err) {
+				printf( "%s [ERR] config port %d register %d\n",_f,i,p->reg );
+				/* XXX what todo */
+			}
+			p++;
+		}
+	}
+
+	/*** initialize phys **************************************************/
+	for (i=0; i<M88X_PHY_CNT; i++) {
+		if ((p = phyCfg[i]) == NULL) {
+			continue;
+		}
+		while (p->reg != -1) {
+			err = 0;
+			err += miiphy_read( devAddr+phyTab[i],p->reg,&val );
+			val &= p->msk;
+			val |= p->val;
+			err += miiphy_write( devAddr+phyTab[i],p->reg,val );
+			if (err) {
+				printf( "%s [ERR] config phy %d register %d\n",_f,i,p->reg );
+				/* XXX what todo */
+			}
+			p++;
+		}
+	}
+	udelay(100000);
+	return( 0 );
+}
+#endif

board/funkwerk/vovpn-gw/m88e6060.h

@@ -0,0 +1,88 @@
+/*
+ * (C) Copyright 2004
+ * Elmeg Communications Systems GmbH, Juergen Selent (j.selent@elmeg.de)
+ *
+ * Support for the Elmeg VoVPN Gateway Module
+ * ------------------------------------------
+ * Initialize Marvell M88E6060 Switch
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _INC_m88e6060_h_
+#define _INC_m88e6060_h_
+
+/* ************************************************************************** */
+/* *** DEFINES ************************************************************** */
+
+/* switch hw */
+#define M88X_PRT_CNT			6
+#define M88X_PHY_CNT			5
+
+/* phy register offsets */
+#define M88X_PHY_CNTL			0x00
+#define M88X_PHY_STAT			0x00
+#define M88X_PHY_ID0			0x02
+#define M88X_PHY_ID1			0x03
+#define M88X_PHY_ANEG_ADV		0x04
+#define M88X_PHY_LPA			0x05
+#define M88X_PHY_ANEG_EXP		0x06
+#define M88X_PHY_NPT			0x07
+#define M88X_PHY_LPNP			0x08
+
+/* port register offsets */
+#define M88X_PRT_STAT			0x00
+#define M88X_PRT_ID			0x03
+#define M88X_PRT_CNTL			0x04
+#define M88X_PRT_VLAN			0x06
+#define M88X_PRT_PAV			0x0b
+#define M88X_PRT_RX			0x10
+#define M88X_PRT_TX			0x11
+
+/* global/atu register offsets */
+#define M88X_GLB_STAT			0x00
+#define M88X_GLB_MAC01			0x01
+#define M88X_GLB_MAC23			0x02
+#define M88X_GLB_MAC45			0x03
+#define M88X_GLB_CNTL			0x04
+#define M88X_ATU_CNTL			0x0a
+#define M88X_ATU_OP			0x0b
+
+/* id0 register - 0x02 */
+#define M88X_PHY_ID0_VALUE		0x0141
+
+/* id1 register - 0x03 */
+#define M88X_PHY_ID1_VALUE		0x0c80		/* without revision ! */
+
+
+/* misc */
+#define M88E6060_ID		((M88X_PHY_ID0_VALUE<<16) | M88X_PHY_ID1_VALUE)
+
+/* ************************************************************************** */
+/* *** TYPEDEFS ************************************************************* */
+
+typedef struct {
+	int		reg;
+	unsigned short	msk;
+	unsigned short	val;
+} m88x_regCfg_t;
+
+/* ************************************************************************** */
+/* *** PROTOTYPES *********************************************************** */
+
+extern int		m88e6060_initialize( int );
+
+#endif	/* _INC_m88e6060_h_ */

board/funkwerk/vovpn-gw/u-boot.lds

@@ -0,0 +1,122 @@
+/*
+ * (C) Copyright 2001-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Modified by Yuli Barcohen <yuli@arabellasw.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc8260/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
+ENTRY(_start)

board/funkwerk/vovpn-gw/vovpn-gw.c

@@ -0,0 +1,375 @@
+/*
+ * (C) Copyright 2004
+ * Elmeg Communications Systems GmbH, Juergen Selent (j.selent@elmeg.de)
+ *
+ * Support for the Elmeg VoVPN Gateway Module
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc8260.h>
+#include <asm/m8260_pci.h>
+#include <miiphy.h>
+
+#include "m88e6060.h"
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+    /* Port A configuration */
+    {	/*	     conf ppar psor pdir podr pdat */
+	/* PA31 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1252           */
+	/* PA30 */ { 1,   0,   0,   0,   0,   0 }, /* GPI    BP_RES           */
+	/* PA29 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1253           */
+	/* PA28 */ { 1,   1,   1,   1,   0,   0 }, /* FCC1   RMII TX_EN       */
+	/* PA27 */ { 1,   1,   1,   0,   0,   0 }, /* FCC1   RMII CRS_DV      */
+	/* PA26 */ { 1,   1,   1,   0,   0,   0 }, /* FCC1   RMII RX_ERR      */
+	/* PA25 */ { 1,   0,   0,   0,   0,   0 }, /* GPI    HWID             */
+	/* PA24 */ { 1,   0,   0,   0,   0,   0 }, /* GPI    HWID             */
+	/* PA23 */ { 1,   0,   0,   0,   0,   0 }, /* GPI    HWID             */
+	/* PA22 */ { 1,   0,   0,   0,   0,   0 }, /* GPI    HWID             */
+	/* PA21 */ { 1,   0,   0,   0,   0,   0 }, /* GPI    HWID             */
+	/* PA20 */ { 1,   0,   0,   1,   0,   1 }, /* GPO    LED STATUS       */
+	/* PA19 */ { 1,   1,   0,   1,   0,   0 }, /* FCC1   RMII TxD[1]      */
+	/* PA18 */ { 1,   1,   0,   1,   0,   0 }, /* FCC1   RMII TxD[0]      */
+	/* PA17 */ { 1,   1,   0,   0,   0,   0 }, /* FCC1   RMII RxD[0]      */
+	/* PA16 */ { 1,   1,   0,   0,   0,   0 }, /* FCC1   RMII RxD[1]      */
+	/* PA15 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1255           */
+	/* PA14 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP????           */
+	/* PA13 */ { 1,   0,   0,   1,   0,   1 }, /* GPO    EN_BCTL1 XXX jse */
+	/* PA12 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    SWITCH RESET     */
+	/* PA11 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    DSP SL1 RESET    */
+	/* PA10 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    DSP SL2 RESET    */
+	/* PA9  */ { 1,   1,   0,   1,   0,   0 }, /* SMC2   TXD              */
+	/* PA8  */ { 1,   1,   0,   0,   0,   0 }, /* SMC2   RXD              */
+	/* PA7  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exit       */
+	/* PA6  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exit       */
+	/* PA5  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exit       */
+	/* PA4  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exit       */
+	/* PA3  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exit       */
+	/* PA2  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exit       */
+	/* PA1  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exit       */
+	/* PA0  */ { 0,   0,   0,   0,   0,   0 }  /* pin does not exit       */
+    },
+
+    /* Port B configuration */
+    {   /*	     conf ppar psor pdir podr pdat */
+	/* PB31 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1257           */
+	/* PB30 */ { 1,   1,   0,   0,   0,   0 }, /* FCC2   RMII CRS_DV      */
+	/* PB29 */ { 1,   1,   1,   1,   0,   0 }, /* FCC2   RMII TX_EN       */
+	/* PB28 */ { 1,   1,   0,   0,   0,   0 }, /* FCC2   RMII RX_ERR      */
+	/* PB27 */ { 1,   1,   1,   0,   1,   0 }, /* TDM_B2 L1TXD XXX val=0  */
+	/* PB26 */ { 1,   1,   1,   0,   1,   0 }, /* TDM_B2 L1RXD XXX val,dr */
+	/* PB25 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1259           */
+	/* PB24 */ { 1,   1,   1,   0,   0,   0 }, /* TDM_B2 L1RSYNC          */
+	/* PB23 */ { 1,   1,   0,   1,   0,   0 }, /* FCC2   RMII TxD[1]      */
+	/* PB22 */ { 1,   1,   0,   1,   0,   0 }, /* FCC2   RMII TxD[0]      */
+	/* PB21 */ { 1,   1,   0,   0,   0,   0 }, /* FCC2   RMII RxD[0]      */
+	/* PB20 */ { 1,   1,   0,   0,   0,   0 }, /* FCC2   RMII RxD[1]      */
+	/* PB19 */ { 1,   0,   0,   1,   0,   1 }, /* GPO    PHY MDC          */
+	/* PB18 */ { 1,   0,   0,   0,   0,   0 }, /* GPIO   PHY MDIO         */
+	/* PB17 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB16 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB15 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB14 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB13 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB12 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB11 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB10 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB9  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB8  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB7  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB6  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB5  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB4  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB3  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB2  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB1  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB0  */ { 0,   0,   0,   0,   0,   0 }  /* pin does not exist      */
+    },
+
+    /* Port C */
+    {   /*	     conf ppar psor pdir podr pdat */
+	/* PC31 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PC30 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PC29 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1183           */
+	/* PC28 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1184           */
+	/* PC27 */ { 1,   1,   0,   0,   0,   0 }, /* CLK5   TDM_A1 RX        */
+	/* PC26 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1185           */
+	/* PC25 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1178           */
+	/* PC24 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1186           */
+	/* PC23 */ { 1,   1,   0,   0,   0,   0 }, /* CLK9   TDM_B2 RX        */
+	/* PC22 */ { 1,   1,   0,   0,   0,   0 }, /* CLK10  FCC1 RMII REFCLK */
+	/* PC21 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1187           */
+	/* PC20 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1182           */
+	/* PC19 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1188           */
+	/* PC18 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    HW RESET         */
+	/* PC17 */ { 1,   1,   0,   1,   0,   0 }, /* BRG8   SWITCH CLKIN     */
+	/* PC16 */ { 1,   1,   0,   0,   0,   0 }, /* CLK16  FCC2 RMII REFCLK */
+	/* PC15 */ { 1,   0,   0,   0,   0,   0 }, /* GPI    SL1_MTYPE_3      */
+	/* PC14 */ { 1,   0,   0,   0,   0,   0 }, /* GPI    SL1_MTYPE_2      */
+	/* PC13 */ { 1,   0,   0,   0,   0,   0 }, /* GPI    SL1_MTYPE_1      */
+	/* PC12 */ { 1,   0,   0,   0,   0,   0 }, /* GPI    SL1_MTYPE_0      */
+	/* PC11 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1176           */
+	/* PC10 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1177           */
+	/* PC9  */ { 1,   0,   0,   0,   0,   0 }, /* GPI    SL2_MTYPE_3      */
+	/* PC8  */ { 1,   0,   0,   0,   0,   0 }, /* GPI    SL2_MTYPE_2      */
+	/* PC7  */ { 1,   0,   0,   0,   0,   0 }, /* GPI    SL2_MTYPE_1      */
+	/* PC6  */ { 1,   0,   0,   0,   0,   0 }, /* GPI    SL2_MTYPE_0      */
+	/* PC5  */ { 1,   1,   0,   1,   0,   0 }, /* SMC1   TXD              */
+	/* PC4  */ { 1,   1,   0,   0,   0,   0 }, /* SMC1   RXD              */
+	/* PC3  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PC2  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PC1  */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1192           */
+	/* PC0  */ { 1,   0,   0,   0,   0,   0 }, /* GPI    RACK             */
+    },
+
+    /* Port D */
+    {   /*	     conf ppar psor pdir podr pdat */
+	/* PD31 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1193           */
+	/* PD30 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1194           */
+	/* PD29 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1195           */
+	/* PD28 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD27 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD26 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD25 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1179           */
+	/* PD24 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1180           */
+	/* PD23 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1181           */
+	/* PD22 */ { 1,   1,   1,   0,   1,   0 }, /* TDM_A2 L1TXD            */
+	/* PD21 */ { 1,   1,   1,   0,   1,   0 }, /* TDM_A2 L1RXD            */
+	/* PD20 */ { 1,   1,   1,   0,   0,   0 }, /* TDM_A2 L1RSYNC          */
+	/* PD19 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1196           */
+	/* PD18 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1197           */
+	/* PD17 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1198           */
+	/* PD16 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1199           */
+	/* PD15 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1250           */
+	/* PD14 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1251           */
+	/* PD13 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD12 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD11 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD10 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD9  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD8  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD7  */ { 0,   0,   0,   1,   0,   0 }, /* GPO    FL_BYTE          */
+	/* PD6  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD5  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD4  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD3  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD2  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD1  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD0  */ { 0,   0,   0,   0,   0,   0 }  /* pin does not exist      */
+    }
+};
+
+void reset_phy (void)
+{
+	volatile ioport_t *iop;
+#if (CONFIG_COMMANDS & CFG_CMD_NET)
+	int i;
+	unsigned short val;
+#endif
+
+	iop = ioport_addr((immap_t *)CFG_IMMR, 0);
+
+	/* Reset the PHY */
+	iop->pdat &= 0xfff7ffff;	/* PA12 = |SWITCH_RESET */
+#if (CONFIG_COMMANDS & CFG_CMD_NET)
+	udelay(20000);
+	iop->pdat |= 0x00080000;
+	for (i=0; i<100; i++) {
+		udelay(20000);
+		if (miiphy_read( CFG_PHY_ADDR,2,&val ) == 0) {
+			break;
+		}
+	}
+	/* initialize switch */
+	m88e6060_initialize( CFG_PHY_ADDR );
+#endif
+}
+
+static unsigned long UPMATable[] = {
+	0x8fffec00,  0x0ffcfc00,  0x0ffcfc00,  0x0ffcfc00, //Words 0 to 3
+	0x0ffcfc04,  0x3ffdfc00,  0xfffffc01,  0xfffffc01, //Words 4 to 7
+	0xfffffc00,  0xfffffc04,  0xfffffc01,  0xfffffc00, //Words 8 to 11
+	0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc00, //Words 12 to 15
+	0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc00, //Words 16 to 19
+	0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc01, //Words 20 to 23
+	0x8fffec00,  0x00fffc00,  0x00fffc00,  0x00fffc00, //Words 24 to 27
+	0x0ffffc04,  0xfffffc01,  0xfffffc01,  0xfffffc01, //Words 28 to 31
+	0xfffffc00,  0xfffffc01,  0xfffffc01,  0xfffffc00, //Words 32 to 35
+	0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc00, //Words 36 to 39
+	0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc00, //Words 40 to 43
+	0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc01, //Words 44 to 47
+	0xfffffc00,  0xfffffc04,  0xfffffc01,  0xfffffc00, //Words 48 to 51
+	0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc00, //Words 52 to 55
+	0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc01, //Words 56 to 59
+	0xffffec00,  0xffffec04,  0xffffec00,  0xfffffc01  //Words 60 to 63
+};
+
+int board_early_init_f (void)
+{
+	volatile immap_t *immap;
+	volatile memctl8260_t *memctl;
+	volatile unsigned char *dummy;
+	int i;
+
+	immap = (immap_t *) CFG_IMMR;
+	memctl = &immap->im_memctl;
+
+#if 0
+	/* CS2-5 - DSP via UPMA */
+	dummy = (volatile unsigned char *) (memctl->memc_br2 & BRx_BA_MSK);
+	memctl->memc_mar = 0;
+	memctl->memc_mamr = MxMR_OP_WARR;
+	for (i = 0; i < 64; i++) {
+		memctl->memc_mdr = UPMATable[i];
+		*dummy = 0;
+	}
+	memctl->memc_mamr = 0x00044440;
+#else
+	/* CS7 - DPRAM via UPMA */
+	dummy = (volatile unsigned char *) (memctl->memc_br7 & BRx_BA_MSK);
+	memctl->memc_mar = 0;
+	memctl->memc_mamr = MxMR_OP_WARR;
+	for (i = 0; i < 64; i++) {
+		memctl->memc_mdr = UPMATable[i];
+		*dummy = 0;
+	}
+	memctl->memc_mamr = 0x00044440;
+#endif
+	return 0;
+}
+
+int misc_init_r (void)
+{
+	volatile ioport_t *iop;
+	unsigned char temp;
+#if 0
+	/* DUMP UPMA RAM */
+	volatile immap_t *immap;
+	volatile memctl8260_t *memctl;
+	volatile unsigned char *dummy;
+	unsigned char c;
+	int i;
+
+	immap = (immap_t *) CFG_IMMR;
+	memctl = &immap->im_memctl;
+
+
+	dummy = (volatile unsigned char *) (memctl->memc_br7 & BRx_BA_MSK);
+	memctl->memc_mar = 0;
+	memctl->memc_mamr = MxMR_OP_RARR;
+	for (i = 0; i < 64; i++) {
+		c = *dummy;
+		printf( "UPMA[%02d]: 0x%08lx,0x%08lx: 0x%08lx\n",i,
+		        memctl->memc_mamr,
+		        memctl->memc_mar,
+		        memctl->memc_mdr );
+	}
+	memctl->memc_mamr = 0x00044440;
+#endif
+	/* enable buffers (DSP, DPRAM) */
+	iop = ioport_addr((immap_t *)CFG_IMMR, 0);
+	iop->pdat &= 0xfffbffff;	/* PA13 = |EN_M_BCTL1 */
+
+	/* destroy DPRAM magic */
+	*(volatile unsigned char *)0xf0500000 = 0x00;
+
+	/* clear any pending DPRAM irq */
+	temp = *(volatile unsigned char *)0xf05003ff;
+
+	/* write module-id into DPRAM */
+	*(volatile unsigned char *)0xf0500201 = 0x50;
+
+	return 0;
+}
+
+#if defined(CONFIG_HAVE_OWN_RESET)
+int
+do_reset (void *cmdtp, int flag, int argc, char *argv[])
+{
+	volatile ioport_t *iop;
+
+	iop = ioport_addr((immap_t *)CFG_IMMR, 2);
+	iop->pdat |= 0x00002000;	/* PC18 = HW_RESET */
+	return 1;
+}
+#endif	/* CONFIG_HAVE_OWN_RESET */
+
+#define ns2clk(ns) (ns / (1000000000 / CONFIG_8260_CLKIN) + 1)
+
+long int initdram (int board_type)
+{
+#ifndef CFG_RAMBOOT
+	volatile immap_t *immap;
+	volatile memctl8260_t *memctl;
+	volatile uchar *ramaddr;
+	int i;
+	uchar c;
+
+	immap = (immap_t *) CFG_IMMR;
+	memctl = &immap->im_memctl;
+	ramaddr = (uchar *) CFG_SDRAM_BASE;
+	c = 0xff;
+
+	immap->im_siu_conf.sc_ppc_acr  = 0x02;
+	immap->im_siu_conf.sc_ppc_alrh = 0x01267893;
+	immap->im_siu_conf.sc_ppc_alrl = 0x89abcdef;
+	immap->im_siu_conf.sc_tescr1   = 0x00000000;
+	immap->im_siu_conf.sc_tescr2   = 0x00000000;
+
+	memctl->memc_mptpr = CFG_MPTPR;
+	memctl->memc_psrt = CFG_PSRT;
+	memctl->memc_or1 = CFG_OR1_PRELIM;
+	memctl->memc_br1 = CFG_SDRAM_BASE | CFG_BR1_PRELIM;
+
+	/* Precharge all banks */
+	memctl->memc_psdmr = CFG_PSDMR | 0x28000000;
+	*ramaddr = c;
+
+	/* CBR refresh */
+	memctl->memc_psdmr = CFG_PSDMR | 0x08000000;
+	for (i = 0; i < 8; i++)
+		*ramaddr = c;
+
+	/* Mode Register write */
+	memctl->memc_psdmr = CFG_PSDMR | 0x18000000;
+	*ramaddr = c;
+
+	/* Refresh enable */
+	memctl->memc_psdmr = CFG_PSDMR | 0x40000000;
+	*ramaddr = c;
+#endif /* CFG_RAMBOOT */
+
+	return (CFG_SDRAM_SIZE);
+}
+
+int checkboard (void)
+{
+#ifdef CONFIG_CLKIN_66MHz
+	puts ("Board: Elmeg VoVPN Gateway Module (66MHz)\n");
+#else
+	puts ("Board: Elmeg VoVPN Gateway Module (100MHz)\n");
+#endif
+	return 0;
+}

board/hmi1001/Makefile

@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2003-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################

board/hmi1001/config.mk

@@ -0,0 +1,41 @@
+#
+# (C) Copyright 2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# INKA 4X0 board:
+#
+#	Valid values for TEXT_BASE are:
+#
+#	0xFFE00000   boot high
+#
+#	0x00100000   boot from RAM (for testing only)
+#
+
+ifndef TEXT_BASE
+## Standard: boot high
+TEXT_BASE = 0xFFF00000
+## For testing: boot from RAM
+#TEXT_BASE = 0x00100000
+endif
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board

board/hmi1001/hmi1001.c

@@ -0,0 +1,172 @@
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * (C) Copyright 2004
+ * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+
+#ifndef CFG_RAMBOOT
+static void sdram_start (int hi_addr)
+{
+	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+	/* unlock mode register */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+#if SDRAM_DDR
+	/* set mode register: extended mode */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
+	__asm__ volatile ("sync");
+
+	/* set mode register: reset DLL */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
+	__asm__ volatile ("sync");
+#endif
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* auto refresh */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* set mode register */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
+	__asm__ volatile ("sync");
+
+	/* normal operation */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
+	__asm__ volatile ("sync");
+}
+#endif
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ *	      use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
+ *	      is something else than 0x00000000.
+ */
+
+long int initdram (int board_type)
+{
+	ulong dramsize = 0;
+#ifndef CFG_RAMBOOT
+	ulong test1, test2;
+
+	/* setup SDRAM chip selects */
+	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */
+	__asm__ volatile ("sync");
+
+	/* setup config registers */
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+	__asm__ volatile ("sync");
+
+#if SDRAM_DDR
+	/* set tap delay */
+	*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
+	__asm__ volatile ("sync");
+#endif
+
+	/* find RAM size using SDRAM CS0 only */
+	sdram_start(0);
+	test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000);
+	sdram_start(1);
+	test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000);
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize < (1 << 20)) {
+		dramsize = 0;
+	}
+
+	/* set SDRAM CS0 size according to the amount of RAM found */
+	if (dramsize > 0) {
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
+			__builtin_ffs(dramsize >> 20) - 1;
+	} else {
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
+	}
+
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
+#else /* CFG_RAMBOOT */
+
+	/* retrieve size of memory connected to SDRAM CS0 */
+	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
+	if (dramsize >= 0x13) {
+		dramsize = (1 << (dramsize - 0x13)) << 20;
+	} else {
+		dramsize = 0;
+	}
+
+	/* retrieve size of memory connected to SDRAM CS1 */
+	dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
+	if (dramsize2 >= 0x13) {
+		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
+	} else {
+		dramsize2 = 0;
+	}
+
+#endif /* CFG_RAMBOOT */
+
+/*	return dramsize + dramsize2; */
+	return dramsize;
+}
+
+int checkboard (void)
+{
+	puts ("Board: HMI1001\n");
+	return 0;
+}
+
+int misc_init_f (void)
+{
+	return 0;
+}
+
+int board_early_init_r (void)
+{
+	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
+	*(vu_long *)MPC5XXX_BOOTCS_START =
+	*(vu_long *)MPC5XXX_CS0_START = START_REG(CFG_FLASH_BASE);
+	*(vu_long *)MPC5XXX_BOOTCS_STOP =
+	*(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CFG_FLASH_BASE, CFG_FLASH_SIZE);
+	return 0;
+}

board/hmi1001/u-boot.lds

@@ -0,0 +1,133 @@
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within  */
+    /* the sector layout of our flash chips!    XXX FIXME XXX   */
+
+    cpu/mpc5xxx/start.o          (.text)
+    cpu/mpc5xxx/traps.o          (.text)
+    lib_generic/crc32.o         (.text)
+    lib_ppc/cache.o             (.text)
+    lib_ppc/time.o              (.text)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/environment.o        (.ppcenv)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}

board/ids8247/Makefile

@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2005
+# Heiko Schocher, DENX Software Engineering, <hs@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################

board/ids8247/config.mk

@@ -0,0 +1,34 @@
+#
+# (C) Copyright 2005
+# Heiko Schocher, DENX Software Engineering, <hs@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# IDS 8247 Board
+#
+
+# This should be equal to the CFG_FLASH_BASE define in config_IDS8247.h
+# for the "final" configuration, with U-Boot in flash, or the address
+# in RAM where U-Boot is loaded at for debugging.
+#
+TEXT_BASE = 0xfff00000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)

board/ids8247/flash.c

@@ -0,0 +1,484 @@
+/*
+ * (C) Copyright 2005
+ * Heiko Schocher, DENX Software Engineering, <hs@denx.de>
+ *
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#undef DEBUG
+
+#include <common.h>
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+# ifndef  CFG_ENV_ADDR
+#  define CFG_ENV_ADDR	(CFG_FLASH_BASE + CFG_ENV_OFFSET)
+# endif
+# ifndef  CFG_ENV_SIZE
+#  define CFG_ENV_SIZE	CFG_ENV_SECT_SIZE
+# endif
+# ifndef  CFG_ENV_SECT_SIZE
+#  define CFG_ENV_SECT_SIZE  CFG_ENV_SIZE
+# endif
+#endif
+
+/*-----------------------------------------------------------------------
+ * Protection Flags:
+ */
+#define FLAG_PROTECT_SET	0x01
+#define FLAG_PROTECT_CLEAR	0x02
+
+/* Board support for 1 or 2 flash devices */
+#undef FLASH_PORT_WIDTH32
+#undef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH8
+
+#ifdef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH	ushort
+#define FLASH_PORT_WIDTHV	vu_short
+#elif FLASH_PORT_WIDTH32
+#define FLASH_PORT_WIDTH	ulong
+#define FLASH_PORT_WIDTHV	vu_long
+#else /* FLASH_PORT_WIDTH8 */
+#define FLASH_PORT_WIDTH	uchar
+#define FLASH_PORT_WIDTHV	vu_char
+#endif
+
+#define FPW			FLASH_PORT_WIDTH
+#define FPWV			FLASH_PORT_WIDTHV
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (FPWV * addr, flash_info_t * info);
+static int write_data (flash_info_t * info, ulong dest, FPW data);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0;
+	int i;
+	volatile immap_t * immr = (immap_t *)CFG_IMMR;
+	volatile memctl8260_t *memctl = &immr->im_memctl;
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+	size_b0 = flash_get_size ((FPW *) CFG_FLASH0_BASE, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0 << 20);
+	}
+
+	memctl->memc_or0 = 0xff800060;
+	memctl->memc_br0 = 0xff800801;
+
+	flash_get_offsets (0xff800000, &flash_info[0]);
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	/* monitor protection ON by default */
+	(void) flash_protect (FLAG_PROTECT_SET,
+				CFG_MONITOR_BASE,
+				CFG_MONITOR_BASE + monitor_flash_len - 1,
+				&flash_info[0]);
+#endif
+
+#ifdef	CFG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect (FLAG_PROTECT_SET,
+			CFG_ENV_ADDR,
+			CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+			&flash_info[0]);
+#endif
+
+	flash_info[0].size = size_b0;
+
+	return (size_b0);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00020000);
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F320J3A:
+		printf ("28F320J3A\n");
+		break;
+	case FLASH_28F640J3A:
+		printf ("28F640J3A\n");
+		break;
+	case FLASH_28F128J3A:
+		printf ("28F128J3A\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (FPWV * addr, flash_info_t * info)
+{
+	FPW value;
+
+	addr[0] = (FPW) 0x00900090;
+
+	value = addr[0];
+
+	debug ("Manuf. ID @ 0x%08lx: 0x%08lx\n", (ulong)addr, value);
+
+	switch (value) {
+	case (FPW) INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+		return (0);			/* no or unknown flash  */
+	}
+
+#ifdef FLASH_PORT_WIDTH8
+	value = addr[2];			/* device ID        */
+#else
+	value = addr[1];			/* device ID        */
+#endif
+
+	debug ("Device ID @ 0x%08lx: 0x%08lx\n", (ulong)(&addr[1]), value);
+
+	switch (value) {
+	case (FPW) INTEL_ID_28F320J3A:
+		info->flash_id += FLASH_28F320J3A;
+		info->sector_count = 32;
+		info->size = 0x00400000;
+		break;				/* => 4 MB     */
+
+	case (FPW) INTEL_ID_28F640J3A:
+		info->flash_id += FLASH_28F640J3A;
+		info->sector_count = 64;
+		info->size = 0x00800000;
+		break;				/* => 8 MB     */
+
+	case (FPW) INTEL_ID_28F128J3A:
+		info->flash_id += FLASH_28F128J3A;
+		info->sector_count = 128;
+		info->size = 0x01000000;
+		break;				/* => 16 MB     */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+				info->sector_count, CFG_MAX_FLASH_SECT);
+		info->sector_count = CFG_MAX_FLASH_SECT;
+	}
+
+	addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong type, start, now, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	start = get_timer (0);
+	last = start;
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			FPWV *addr = (FPWV *) (info->start[sect]);
+			FPW status;
+
+			/* Disable interrupts which might cause a timeout here */
+			flag = disable_interrupts ();
+
+			*addr = (FPW) 0x00500050;	/* clear status register */
+			*addr = (FPW) 0x00200020;	/* erase setup */
+			*addr = (FPW) 0x00D000D0;	/* erase confirm */
+
+			/* re-enable interrupts if necessary */
+			if (flag)
+				enable_interrupts ();
+
+			/* wait at least 80us - let's wait 1 ms */
+			udelay (1000);
+
+			while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+			    if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
+				printf ("Timeout\n");
+				*addr = (FPW) 0x00B000B0;	/* suspend erase     */
+				*addr = (FPW) 0x00FF00FF;	/* reset to read mode */
+				rcode = 1;
+				break;
+			    }
+
+			    /* show that we're waiting */
+			    if ((now - last) > 1000) {	/* every second */
+				putc ('.');
+				last = now;
+			    }
+			}
+
+			*addr = (FPW) 0x00FF00FF;	/* reset to read mode */
+		}
+	}
+	printf (" done\n");
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	FPW data;
+
+	int i, l, rc, port_width;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+/* get lower word aligned address */
+#ifdef FLASH_PORT_WIDTH16
+	wp = (addr & ~1);
+	port_width = 2;
+#elif defined(FLASH_PORT_WIDTH32)
+	wp = (addr & ~3);
+	port_width = 4;
+#else
+	wp = addr;
+	port_width = 1;
+#endif
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < port_width && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < port_width; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_data (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= port_width) {
+		data = 0;
+		for (i = 0; i < port_width; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+		cnt -= port_width;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < port_width; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_data (info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t * info, ulong dest, FPW data)
+{
+	FPWV *addr = (FPWV *) dest;
+	ulong status;
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr);
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	*addr = (FPW) 0x00400040;	/* write setup */
+	*addr = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+
+	start = get_timer (0);
+
+	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+		if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+			return (1);
+		}
+	}
+
+	*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (0);
+}

board/ids8247/ids8247.c

@@ -0,0 +1,318 @@
+/*
+ * (C) Copyright 2005
+ * Heiko Schocher, DENX Software Engineering, <hs@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc8260.h>
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A configuration */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PA31 */ {   0,   1,	 1,   0,   0,	0   }, /* FCC1 COL */
+	/* PA30 */ {   0,   1,	 1,   0,   0,	0   }, /* FCC1 CRS */
+	/* PA29 */ {   0,   1,	 1,   1,   0,	0   }, /* FCC1 TXER */
+	/* PA28 */ {   0,   1,	 1,   1,   0,	0   }, /* FCC1 TXEN */
+	/* PA27 */ {   0,   1,	 1,   0,   0,	0   }, /* FCC1 RXDV */
+	/* PA26 */ {   0,   1,	 1,   0,   0,	0   }, /* FCC1 RXER */
+	/* PA25 */ {   0,   0,	 0,   0,   1,	0   }, /* 8247_P0 */
+#if defined(CONFIG_SOFT_I2C)
+	/* PA24 */ {   1,   0,	 0,   0,   1,	1   }, /* I2C_SDA2 */
+	/* PA23 */ {   1,   0,	 0,   1,   1,	1   }, /* I2C_SCL2 */
+#else /* normal I/O port pins */
+	/* PA24 */ {   0,   0,	 0,   1,   0,	0   }, /* PA24 */
+	/* PA23 */ {   0,   0,	 0,   1,   0,	0   }, /* PA23 */
+#endif
+	/* PA22 */ {   0,   0,	 0,   0,   1,	0   }, /* SMC2_DCD */
+	/* PA21 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC1 TXD3 */
+	/* PA20 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC1 TXD2 */
+	/* PA19 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC1 TXD1 */
+	/* PA18 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC1 TXD0 */
+	/* PA17 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC1 RXD0 */
+	/* PA16 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC1 RXD1 */
+	/* PA15 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC1 RXD2 */
+	/* PA14 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC1 RXD3 */
+	/* PA13 */ {   0,   0,	 0,   1,   1,	0   }, /* SMC2_RTS */
+	/* PA12 */ {   0,   0,	 0,   0,   1,	0   }, /* SMC2_CTS */
+	/* PA11 */ {   0,   0,	 0,   1,   1,	0   }, /* SMC2_DTR */
+	/* PA10 */ {   0,   0,	 0,   0,   1,	0   }, /* SMC2_DSR */
+	/* PA9	*/ {   0,   1,	 0,   1,   0,	0   }, /* SMC2 TXD */
+	/* PA8	*/ {   0,   1,	 0,   0,   0,	0   }, /* SMC2 RXD */
+	/* PA7	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA7 */
+	/* PA6	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA6 */
+	/* PA5	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA5 */
+	/* PA4	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA4 */
+	/* PA3	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA3 */
+	/* PA2	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA2 */
+	/* PA1	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA1 */
+	/* PA0	*/ {   0,   0,	 0,   1,   0,	0   }  /* PA0 */
+    },
+
+    /* Port B configuration */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PB31 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC2 MII TX_ER */
+	/* PB30 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RX_DV */
+	/* PB29 */ {   1,   1,	 1,   1,   0,	0   }, /* FCC2 MII TX_EN */
+	/* PB28 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RX_ER */
+	/* PB27 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII COL */
+	/* PB26 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII CRS */
+	/* PB25 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC2 MII TxD[3] */
+	/* PB24 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC2 MII TxD[2] */
+	/* PB23 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC2 MII TxD[1] */
+	/* PB22 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC2 MII TxD[0] */
+	/* PB21 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RxD[0] */
+	/* PB20 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RxD[1] */
+	/* PB19 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RxD[2] */
+	/* PB18 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RxD[3] */
+	/* PB17 */ {   0,   0,	 0,   0,   0,	0   }, /* PB17 */
+	/* PB16 */ {   0,   0,	 0,   0,   0,	0   }, /* PB16 */
+	/* PB15 */ {   0,   0,	 0,   0,   0,	0   }, /* PB15 */
+	/* PB14 */ {   0,   0,	 0,   0,   0,	0   }, /* PB14 */
+	/* PB13 */ {   0,   0,	 0,   0,   0,	0   }, /* PB13 */
+	/* PB12 */ {   0,   0,	 0,   0,   0,	0   }, /* PB12 */
+	/* PB11 */ {   0,   0,	 0,   0,   0,	0   }, /* PB11 */
+	/* PB10 */ {   0,   0,	 0,   0,   0,	0   }, /* PB10 */
+	/* PB9	*/ {   0,   0,	 0,   0,   0,	0   }, /* PB9 */
+	/* PB8	*/ {   0,   0,	 0,   0,   0,	0   }, /* PB8 */
+	/* PB7	*/ {   0,   0,	 0,   0,   0,	0   }, /* PB7 */
+	/* PB6	*/ {   0,   0,	 0,   0,   0,	0   }, /* PB6 */
+	/* PB5	*/ {   0,   0,	 0,   0,   0,	0   }, /* PB5 */
+	/* PB4	*/ {   0,   0,	 0,   0,   0,	0   }, /* PB4 */
+	/* PB3	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
+	/* PB2	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
+	/* PB1	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
+	/* PB0	*/ {   0,   0,	 0,   0,   0,	0   }  /* pin doesn't exist */
+    },
+
+    /* Port C */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PC31 */ {   0,   0,	 0,   1,   0,	0   }, /* PC31 */
+	/* PC30 */ {   0,   0,	 0,   1,   0,	0   }, /* PC30 */
+	/* PC29 */ {   0,   1,	 0,   0,   0,	0   }, /* SCC1 EN *CLSN */
+	/* PC28 */ {   0,   1,	 1,   0,   0,	0   }, /* SYNC_OUT */
+	/* PC27 */ {   0,   0,	 0,   1,   0,	0   }, /* PC27 */
+	/* PC26 */ {   0,   0,	 0,   1,   0,	0   }, /* PC26 */
+	/* PC25 */ {   0,   1,	 1,   0,   0,	0   }, /* SYNC_IN */
+	/* PC24 */ {   0,   0,	 0,   1,   0,	0   }, /* PC24 */
+	/* PC23 */ {   0,   1,	 0,   1,   0,	0   }, /* ATMTFCLK */
+	/* PC22 */ {   0,   1,	 0,   0,   0,	0   }, /* ATMRFCLK */
+	/* PC21 */ {   0,   1,	 0,   0,   0,	0   }, /* SCC1 EN RXCLK */
+	/* PC20 */ {   0,   1,	 0,   0,   0,	0   }, /* SCC1 EN TXCLK */
+	/* PC19 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RX_CLK */
+	/* PC18 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII TX_CLK */
+	/* PC17 */ {   0,   0,	 0,   1,   0,	0   }, /* PC17 */
+	/* PC16 */ {   0,   0,	 0,   1,   0,	0   }, /* PC16 */
+	/* PC15 */ {   0,   0,	 0,   1,   0,	0   }, /* PC15 */
+	/* PC14 */ {   0,   1,	 0,   0,   0,	0   }, /* SCC1 EN *CD */
+	/* PC13 */ {   0,   0,	 0,   1,   0,	0   }, /* PC13 */
+	/* PC12 */ {   0,   0,	 0,   1,   0,	0   }, /* PC12 */
+	/* PC11 */ {   0,   0,	 0,   1,   0,	0   }, /* PC11 */
+	/* PC10 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC2 MDC */
+	/* PC9	*/ {   0,   0,	 0,   1,   0,	0   }, /* FCC2 MDIO */
+	/* PC8	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC8 */
+	/* PC7	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC7 */
+	/* PC6	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC6 */
+	/* PC5	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC5 */
+	/* PC4	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC4 */
+	/* PC3	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC3 */
+	/* PC2	*/ {   0,   0,	 0,   1,   0,	1   }, /* ENET FDE */
+	/* PC1	*/ {   0,   0,	 0,   1,   0,	0   }, /* ENET DSQE */
+	/* PC0	*/ {   0,   0,	 0,   1,   0,	0   }, /* ENET LBK */
+    },
+
+    /* Port D */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PD31 */ {   0,   1,	 0,   0,   0,	0   }, /* SCC1 EN RxD */
+	/* PD30 */ {   0,   1,	 1,   1,   0,	0   }, /* SCC1 EN TxD */
+	/* PD29 */ {   0,   1,	 0,   1,   0,	0   }, /* SCC1 EN TENA */
+	/* PD28 */ {   0,   0,	 0,   1,   0,	0   }, /* PD28 */
+	/* PD27 */ {   0,   0,	 0,   1,   0,	0   }, /* PD27 */
+	/* PD26 */ {   0,   0,	 0,   1,   0,	0   }, /* PD26 */
+	/* PD25 */ {   0,   1,	 0,   0,   0,	0   }, /* SCC3_RX */
+	/* PD24 */ {   0,   1,	 0,   1,   0,	0   }, /* SCC3_TX */
+	/* PD23 */ {   0,   1,	 0,   1,   0,	0   }, /* SCC3_RTS */
+	/* PD22 */ {   0,   1,	 0,   0,   0,	0   }, /* SCC4_RXD */
+	/* PD21 */ {   0,   1,	 0,   1,   0,	0   }, /* SCC4_TXD */
+	/* PD20 */ {   0,   1,	 0,   1,   0,	0   }, /* SCC4_RTS */
+	/* PD19 */ {   0,   1,	 1,   0,   0,	0   }, /* SPI_SEL */
+	/* PD18 */ {   0,   1,	 1,   0,   0,	0   }, /* SPI_CLK */
+	/* PD17 */ {   0,   1,	 1,   0,   0,	0   }, /* SPI_MOSI */
+	/* PD16 */ {   0,   1,	 1,   0,   0,	0   }, /* SPI_MISO */
+#if defined(CONFIG_HARD_I2C)
+	/* PD15 */ {   1,   1,	 1,   0,   1,	0   }, /* I2C SDA1 */
+	/* PD14 */ {   1,   1,	 1,   0,   1,	0   }, /* I2C SCL1 */
+#else /* normal I/O port pins */
+	/* PD15 */ {   0,   1,	 1,   0,   1,	0   }, /* PD15 */
+	/* PD14 */ {   0,   1,	 1,   0,   1,	0   }, /* PD14 */
+#endif
+	/* PD13 */ {   0,   0,	 0,   0,   0,	0   }, /* PD13 */
+	/* PD12 */ {   0,   0,	 0,   0,   0,	0   }, /* PD12 */
+	/* PD11 */ {   0,   0,	 0,   0,   0,	0   }, /* PD11 */
+	/* PD10 */ {   0,   0,	 0,   0,   0,	0   }, /* PD10 */
+	/* PD9	*/ {   0,   0,	 0,   0,   0,	0   }, /* PD9 */
+	/* PD8	*/ {   0,   0,	 0,   0,   0,	0   }, /* PD8 */
+	/* PD7	*/ {   0,   0,	 0,   1,   0,	1   }, /* MII_MDIO */
+	/* PD6	*/ {   0,   0,	 0,   1,   0,	1   }, /* PD6 */
+	/* PD5	*/ {   0,   0,	 0,   1,   0,	1   }, /* PD5 */
+	/* PD4	*/ {   0,   0,	 0,   1,   0,	1   }, /* PD4 */
+	/* PD3	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
+	/* PD2	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
+	/* PD1	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
+	/* PD0	*/ {   0,   0,	 0,   0,   0,	0   }  /* pin doesn't exist */
+    }
+};
+
+/* ------------------------------------------------------------------------- */
+
+/* Check Board Identity:
+ */
+int checkboard (void)
+{
+	puts ("Board: IDS 8247\n");
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
+ *
+ * This routine performs standard 8260 initialization sequence
+ * and calculates the available memory size. It may be called
+ * several times to try different SDRAM configurations on both
+ * 60x and local buses.
+ */
+static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
+						  ulong orx, volatile uchar * base)
+{
+	volatile uchar c = 0xff;
+	volatile uint *sdmr_ptr;
+	volatile uint *orx_ptr;
+	ulong maxsize, size;
+	int i;
+
+	/* We must be able to test a location outsize the maximum legal size
+	 * to find out THAT we are outside; but this address still has to be
+	 * mapped by the controller. That means, that the initial mapping has
+	 * to be (at least) twice as large as the maximum expected size.
+	 */
+	maxsize = (1 + (~orx | 0x7fff)) / 2;
+
+	sdmr_ptr = &memctl->memc_psdmr;
+	orx_ptr = &memctl->memc_or2;
+
+	*orx_ptr = orx;
+
+	/*
+	 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
+	 *
+	 * "At system reset, initialization software must set up the
+	 *  programmable parameters in the memory controller banks registers
+	 *  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
+	 *  system software should execute the following initialization sequence
+	 *  for each SDRAM device.
+	 *
+	 *  1. Issue a PRECHARGE-ALL-BANKS command
+	 *  2. Issue eight CBR REFRESH commands
+	 *  3. Issue a MODE-SET command to initialize the mode register
+	 *
+	 *  The initial commands are executed by setting P/LSDMR[OP] and
+	 *  accessing the SDRAM with a single-byte transaction."
+	 *
+	 * The appropriate BRx/ORx registers have already been set when we
+	 * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
+	 */
+
+	*sdmr_ptr = sdmr | PSDMR_OP_PREA;
+	*base = c;
+
+	*sdmr_ptr = sdmr | PSDMR_OP_CBRR;
+	for (i = 0; i < 8; i++)
+		*base = c;
+
+	*sdmr_ptr = sdmr | PSDMR_OP_MRW;
+	*(base + CFG_MRS_OFFS) = c;	/* setting MR on address lines */
+
+	*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
+	*base = c;
+
+	size = get_ram_size((long *)base, maxsize);
+	*orx_ptr = orx | ~(size - 1);
+
+	return (size);
+}
+
+long int initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8260_t *memctl = &immap->im_memctl;
+
+	long psize, lsize;
+
+	psize = 16 * 1024 * 1024;
+	lsize = 0;
+
+	memctl->memc_psrt = CFG_PSRT;
+	memctl->memc_mptpr = CFG_MPTPR;
+
+#ifndef CFG_RAMBOOT
+	/* 60x SDRAM setup:
+	 */
+	psize = try_init (memctl, CFG_PSDMR, CFG_OR2,
+						  (uchar *) CFG_SDRAM_BASE);
+#endif /* CFG_RAMBOOT */
+
+	icache_enable ();
+
+	return (psize);
+}
+
+int misc_init_r (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_flashstart = 0xff800000;
+}
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+extern ulong
+nand_probe (ulong physadr);
+
+void
+nand_init (void)
+{
+	ulong totlen = 0;
+
+	debug ("Probing at 0x%.8x\n", CFG_NAND0_BASE);
+	totlen += nand_probe (CFG_NAND0_BASE);
+
+	printf ("%4lu MB\n", totlen >>20);
+}
+
+#endif	/* CFG_CMD_NAND */

board/ids8247/u-boot.lds

@@ -0,0 +1,123 @@
+/*
+ * (C) Copyright 2001
+ * Heiko Schocher, DENX Software Engineering, <hs@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc8260/start.o	(.text)
+    *(.text)
+    common/environment.o(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}

board/inka4x0/inka4x0.c

@@ -173,6 +173,7 @@ void flash_preinit(void)
 	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
 }
 
+#define GPIO_WKUP_7	0x80000000UL
 #define GPIO_PSC3_9	0x04000000UL
 
 int misc_init_f (void)
@@ -189,13 +190,13 @@ int misc_init_f (void)
 
 	/* Initialize GPIO output pins.
 	 */
-	/* Configure GPT as GPIO output */
+	/* Configure GPT as GPIO output (and set them as they control low-active LEDs */
 	*(vu_long *)MPC5XXX_GPT0_ENABLE =
 	*(vu_long *)MPC5XXX_GPT1_ENABLE =
 	*(vu_long *)MPC5XXX_GPT2_ENABLE =
 	*(vu_long *)MPC5XXX_GPT3_ENABLE =
 	*(vu_long *)MPC5XXX_GPT4_ENABLE =
-	*(vu_long *)MPC5XXX_GPT5_ENABLE = 0x24;
+	*(vu_long *)MPC5XXX_GPT5_ENABLE = 0x34;
 
 	/* Configure GPT7 as PWM timer, 1kHz, no ints. */
 	*(vu_long *)MPC5XXX_GPT7_ENABLE = 0;/* Disable */
@@ -216,6 +217,8 @@ int misc_init_f (void)
 	*(vu_long *)MPC5XXX_WU_GPIO_ENABLE |= 0xc4000000;
 	*(vu_long *)MPC5XXX_WU_GPIO_DIR |= 0xc4000000;
 
+	/* Set LR mirror bit because it is low-active */
+	*(vu_long *)MPC5XXX_WU_GPIO_DATA    |= GPIO_WKUP_7;
 	/*
 	 * Reset Coral-P graphics controller
 	 */

board/omap5912osk/flash.c

@@ -236,14 +236,14 @@ static ulong flash_get_size (FPW * addr, flash_info_t * info)
 		info->flash_id +=FLASH_28F256K3;
 		info->sector_count = 259;
 		info->size = 0x02000000;
-			    printf ("\Intel StrataFlash 28F256K3C device initialized\n");
+		debug ("Intel StrataFlash 28F256K3C device initialized\n");
 		break;			/* => 32 MB	*/
 
 	case (FPW) (INTEL_ID_28F128J3A):
 		info->flash_id +=FLASH_28F128J3A;
 		info->sector_count = 259;
 		info->size = 0x02000000;
-			    printf ("\Micron StrataFlash MT28F128J3 device initialized\n");
+		debug ("Micron StrataFlash MT28F128J3 device initialized\n");
 		break;			/* => 32 MB	*/
 
 	default:

board/sorcery/sorcery.c

@@ -25,6 +25,7 @@
 #include <mpc8220.h>
 #include <asm/processor.h>
 #include <asm/mmu.h>
+#include <pci.h>
 
 long int initdram (int board_type)
 {
@@ -41,3 +42,19 @@ int checkboard (void)
 
 	return 0;
 }
+
+#if defined(CONFIG_PCI)
+/*
+ * Initialize PCI devices, report devices found.
+ */
+static struct pci_controller hose;
+
+#endif /* CONFIG_PCI */
+
+void pci_init_board (void)
+{
+#ifdef CONFIG_PCI
+	extern void pci_mpc8220_init (struct pci_controller *hose);
+	pci_mpc8220_init (&hose);
+#endif /* CONFIG_PCI */
+}

common/cmd_bootm.c

@@ -261,7 +261,7 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 		name = "Standalone Application";
 		/* A second argument overwrites the load address */
 		if (argc > 2) {
-			hdr->ih_load = simple_strtoul(argv[2], NULL, 16);
+			hdr->ih_load = htonl(simple_strtoul(argv[2], NULL, 16));
 		}
 		break;
 	case IH_TYPE_KERNEL:

common/cmd_jffs2.c

@@ -175,10 +175,9 @@ do_jffs2_fsload(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 int
 do_jffs2_ls(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
-   struct part_info* jffs2_part_info(int);
-   int jffs2_1pass_ls(struct part_info *,char *);
-
-   char *filename = "/";
+	struct part_info* jffs2_part_info(int);
+	int jffs2_1pass_ls(struct part_info *,char *);
+	char *filename = "/";
 	int ret;
 	struct part_info *part;
 
@@ -235,11 +234,11 @@ do_jffs2_chpart(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
 	int tmp_part;
 	char str_part_num[3];
-   struct part_info* jffs2_part_info(int);
+	struct part_info* jffs2_part_info(int);
 
-   if (argc >= 2) {
+	if (argc >= 2) {
 		tmp_part = simple_strtoul(argv[1], NULL, 16);
-	}else{
+	} else {
 		puts ("Need partition number in argument list\n");
 		return 0;
 

common/cmd_nand.c

@@ -670,11 +670,12 @@ static int NanD_IdentChip(struct nand_chip *nand, int floor, int chip)
 	id = READ_NAND(nand->IO_ADDR);
 
 	NAND_DISABLE_CE(nand);  /* set pin high */
-	/* No response - return failure */
-	if (mfr == 0xff || mfr == 0) {
+
 #ifdef NAND_DEBUG
-		printf("NanD_Command (ReadID) got %d %d\n", mfr, id);
+	printf("NanD_Command (ReadID) got %x %x\n", mfr, id);
 #endif
+	if (mfr == 0xff || mfr == 0) {
+		/* No response - return failure */
 		return 0;
 	}
 

common/cmd_usb.c

@@ -609,7 +609,7 @@ U_BOOT_CMD(
 	"usb tree  - show USB device tree\n"
 	"usb info [dev] - show available USB devices\n"
 	"usb scan  - (re-)scan USB bus for storage devices\n"
-	"usb device [dev] - show or set current USB storage device\n"
+	"usb dev [dev] - show or set current USB storage device\n"
 	"usb part [dev] - print partition table of one or all USB storage devices\n"
 	"usb read addr blk# cnt - read `cnt' blocks starting at block `blk#'\n"
 	"    to memory address `addr'\n"

common/lcd.c

@@ -58,6 +58,15 @@
 /************************************************************************/
 #include <video_font.h>		/* Get font data, width and height	*/
 
+/************************************************************************/
+/* ** LOGO DATA								*/
+/************************************************************************/
+#ifdef CONFIG_LCD_LOGO
+# include <bmp_logo.h>		/* Get logo data, width and height	*/
+# if (CONSOLE_COLOR_WHITE >= BMP_LOGO_OFFSET)
+#  error Default Color Map overlaps with Logo Color Map
+# endif
+#endif
 
 ulong lcd_setmem (ulong addr);
 
@@ -269,7 +278,7 @@ static void lcd_drawchars (ushort x, ushort y, uchar *str, int count)
 
 static inline void lcd_puts_xy (ushort x, ushort y, uchar *s)
 {
-#if defined(CONFIG_LCD_LOGO) && !defined(LCD_INFO_BELOW_LOGO)
+#if defined(CONFIG_LCD_LOGO) && !defined(CONFIG_LCD_INFO_BELOW_LOGO)
 	lcd_drawchars (x, y+BMP_LOGO_HEIGHT, s, strlen (s));
 #else
 	lcd_drawchars (x, y, s, strlen (s));
@@ -280,7 +289,7 @@ static inline void lcd_puts_xy (ushort x, ushort y, uchar *s)
 
 static inline void lcd_putc_xy (ushort x, ushort y, uchar c)
 {
-#if defined(CONFIG_LCD_LOGO) && !defined(LCD_INFO_BELOW_LOGO)
+#if defined(CONFIG_LCD_LOGO) && !defined(CONFIG_LCD_INFO_BELOW_LOGO)
 	lcd_drawchars (x, y+BMP_LOGO_HEIGHT, &c, 1);
 #else
 	lcd_drawchars (x, y, &c, 1);
@@ -420,7 +429,7 @@ static int lcd_init (void *lcdbase)
 
 	/* Initialize the console */
 	console_col = 0;
-#ifdef LCD_INFO_BELOW_LOGO
+#ifdef CONFIG_LCD_INFO_BELOW_LOGO
 	console_row = 7 + BMP_LOGO_HEIGHT / VIDEO_FONT_HEIGHT;
 #else
 	console_row = 1;	/* leave 1 blank line below logo */
@@ -655,6 +664,7 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
 	fb   = (uchar *) (lcd_base +
 		(y + height - 1) * lcd_line_length + x);
 	for (i = 0; i < height; ++i) {
+		WATCHDOG_RESET();
 		for (j = 0; j < width ; j++)
 #if defined(CONFIG_PXA250)
 			*(fb++)=*(bmap++);
@@ -672,12 +682,12 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
 
 static void *lcd_logo (void)
 {
-#ifdef LCD_INFO
+#ifdef CONFIG_LCD_INFO
 	DECLARE_GLOBAL_DATA_PTR;
 
 	char info[80];
 	char temp[32];
-#endif /* LCD_INFO */
+#endif /* CONFIG_LCD_INFO */
 
 #ifdef CONFIG_SPLASH_SCREEN
 	char *s;
@@ -699,7 +709,7 @@ static void *lcd_logo (void)
 #endif /* CONFIG_LCD_LOGO */
 
 #ifdef CONFIG_MPC823
-#ifdef LCD_INFO
+# ifdef CONFIG_LCD_INFO
 	sprintf (info, "%s (%s - %s) ", U_BOOT_VERSION, __DATE__, __TIME__);
 	lcd_drawchars (LCD_INFO_X, LCD_INFO_Y, info, strlen(info));
 
@@ -710,7 +720,7 @@ static void *lcd_logo (void)
 	sprintf (info, "    Wolfgang DENK, wd@denx.de");
 	lcd_drawchars (LCD_INFO_X, LCD_INFO_Y + VIDEO_FONT_HEIGHT * 2,
 					info, strlen(info));
-#ifdef LCD_INFO_BELOW_LOGO
+#  ifdef CONFIG_LCD_INFO_BELOW_LOGO
 	sprintf (info, "MPC823 CPU at %s MHz",
 		strmhz(temp, gd->cpu_clk));
 	lcd_drawchars (LCD_INFO_X, LCD_INFO_Y + VIDEO_FONT_HEIGHT * 3,
@@ -720,7 +730,7 @@ static void *lcd_logo (void)
 		gd->bd->bi_flashsize >> 20 );
 	lcd_drawchars (LCD_INFO_X, LCD_INFO_Y + VIDEO_FONT_HEIGHT * 4,
 					info, strlen(info));
-#else
+#  else
 	/* leave one blank line */
 
 	sprintf (info, "MPC823 CPU at %s MHz, %ld MB RAM, %ld MB Flash",
@@ -730,15 +740,15 @@ static void *lcd_logo (void)
 	lcd_drawchars (LCD_INFO_X, LCD_INFO_Y + VIDEO_FONT_HEIGHT * 4,
 					info, strlen(info));
 
+#  endif /* CONFIG_LCD_INFO_BELOW_LOGO */
+# endif /* CONFIG_LCD_INFO */
 #endif /* CONFIG_MPC823 */
-#endif /* LCD_INFO_BELOW_LOGO */
-#endif /* LCD_INFO */
 
-#if defined(CONFIG_LCD_LOGO) && !defined(LCD_INFO_BELOW_LOGO)
+#if defined(CONFIG_LCD_LOGO) && !defined(CONFIG_LCD_INFO_BELOW_LOGO)
 	return ((void *)((ulong)lcd_base + BMP_LOGO_HEIGHT * lcd_line_length));
 #else
 	return ((void *)lcd_base);
-#endif /* CONFIG_LCD_LOGO */
+#endif /* CONFIG_LCD_LOGO && !CONFIG_LCD_INFO_BELOW_LOGO */
 }
 
 /************************************************************************/

cpu/arm920t/ks8695/Makefile

@@ -0,0 +1,43 @@
+#
+# (C) Copyright 2000-2005
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(SOC).a
+
+OBJS	= interrupts.o serial.o
+SOBJS	= lowlevel_init.o
+
+all:	.depend $(LIB)
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+#########################################################################
+
+.depend:	Makefile $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################

cpu/arm920t/ks8695/interrupts.c

@@ -0,0 +1,112 @@
+/*
+ * (C) Copyright 2004-2005, Greg Ungerer <greg.ungerer@opengear.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/platform.h>
+
+/*
+ * Handy KS8695 register access functions.
+ */
+#define	ks8695_read(a)    *((volatile ulong *) (KS8695_IO_BASE + (a)))
+#define	ks8695_write(a,v) *((volatile ulong *) (KS8695_IO_BASE + (a))) = (v)
+
+int timer_inited;
+ulong timer_ticks;
+
+int interrupt_init (void)
+{
+	/* nothing happens here - we don't setup any IRQs */
+	return (0);
+}
+
+/*
+ * Initial timer set constants. Nothing complicated, just set for a 1ms
+ * tick.
+ */
+#define	TIMER_INTERVAL	(TICKS_PER_uSEC * mSEC_1)
+#define	TIMER_COUNT	(TIMER_INTERVAL / 2)
+#define	TIMER_PULSE	TIMER_COUNT
+
+void reset_timer_masked(void)
+{
+	/* Set the hadware timer for 1ms */
+	ks8695_write(KS8695_TIMER1, TIMER_COUNT);
+	ks8695_write(KS8695_TIMER1_PCOUNT, TIMER_PULSE);
+	ks8695_write(KS8695_TIMER_CTRL, 0x2);
+	timer_ticks = 0;
+	timer_inited++;
+}
+
+void reset_timer(void)
+{
+	reset_timer_masked();
+}
+
+ulong get_timer_masked(void)
+{
+	/* Check for timer wrap */
+	if (ks8695_read(KS8695_INT_STATUS) & KS8695_INTMASK_TIMERINT1) {
+		/* Clear interrupt condition */
+		ks8695_write(KS8695_INT_STATUS, KS8695_INTMASK_TIMERINT1);
+		timer_ticks++;
+	}
+	return timer_ticks;
+}
+
+ulong get_timer(ulong base)
+{
+       return (get_timer_masked() - base);
+}
+
+void set_timer(ulong t)
+{
+	timer_ticks = t;
+}
+
+void udelay(ulong usec)
+{
+	ulong start = get_timer_masked();
+	ulong end;
+
+	if (!timer_inited)
+		reset_timer();
+
+	/* Only 1ms resolution :-( */
+	end = usec / 1000;
+	while (get_timer(start) < end)
+		;
+}
+
+void reset_cpu (ulong ignored)
+{
+	ulong tc;
+
+	/* Set timer0 to watchdog, and let it timeout */
+	tc = ks8695_read(KS8695_TIMER_CTRL) & 0x2;
+	ks8695_write(KS8695_TIMER_CTRL, tc);
+	ks8695_write(KS8695_TIMER0, ((10 << 8) | 0xff));
+	ks8695_write(KS8695_TIMER_CTRL, (tc | 0x1));
+
+	/* Should only wait here till watchdog resets */
+	for (;;)
+		;
+}

cpu/arm920t/ks8695/lowlevel_init.S

@@ -0,0 +1,205 @@
+/*
+ *  lowlevel_init.S - basic hardware initialization for the KS8695 CPU
+ *
+ *  Copyright (c) 2004-2005, Greg Ungerer <greg.ungerer@opengear.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/platform.h>
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+
+/*
+ *************************************************************************
+ *
+ * Handy dandy macros
+ *
+ *************************************************************************
+ */
+
+/* Delay a bit */
+.macro DELAY_FOR cycles, reg0
+	ldr     \reg0, =\cycles
+	subs    \reg0, \reg0, #1
+	subne   pc,  pc, #0xc
+.endm
+
+/*
+ *************************************************************************
+ *
+ * Some local storage.
+ *
+ *************************************************************************
+ */
+
+/* Should we boot with an interactive console or not */
+.globl serial_console
+
+/*
+ *************************************************************************
+ *
+ * Raw hardware initialization code. The important thing is to get
+ * SDRAM setup and running. We do some other basic things here too,
+ * like getting the PLL set for high speed, and init the LEDs.
+ *
+ *************************************************************************
+ */
+
+.globl lowlevel_init
+lowlevel_init:
+
+#if DEBUG
+	/*
+	 * enable UART for early debug trace
+	 */
+	ldr	r1, =(KS8695_IO_BASE+KS8695_UART_DIVISOR)
+	mov	r2, #0xd9
+	str	r2, [r1]		/* 115200 baud */
+	ldr	r1, =(KS8695_IO_BASE+KS8695_UART_LINE_CTRL)
+	mov	r2, #0x03
+	str	r2, [r1]		/* 8 data bits, no parity, 1 stop */
+	ldr	r1, =(KS8695_IO_BASE+KS8695_UART_TX_HOLDING)
+	mov	r2, #0x41
+	str	r2, [r1]		/* write 'A' */
+#endif
+#if DEBUG
+	ldr	r1, =(KS8695_IO_BASE+KS8695_UART_TX_HOLDING)
+	mov	r2, #0x42
+	str	r2, [r1]
+#endif
+
+	/*
+	 * remap the memory and flash regions. we want to end up with
+	 * ram from address 0, and flash at 32MB.
+	 */
+	ldr	r1, =(KS8695_IO_BASE+KS8695_MEM_CTRL0)
+	ldr	r2, =0xbfc00040
+	str	r2, [r1]		/* large flash map */
+	ldr	pc, =(highflash+0x02000000-0x00f00000)	/* jump to high flash address */
+highflash:
+	ldr	r2, =0x8fe00040
+	str	r2, [r1]		/* remap flash range */
+
+	/*
+	 * remap the second select region to the 4MB immediately after
+	 * the first region. This way if you have a larger flash (say 8Mb)
+	 * then you can have it all mapped nicely. Has no effect if you
+	 * only have a 4Mb or smaller flash.
+	 */
+	ldr	r1, =(KS8695_IO_BASE+KS8695_MEM_CTRL1)
+	ldr	r2, =0x9fe40040
+	str	r2, [r1]		/* remap flash2 region, contiguous */
+	ldr	r1, =(KS8695_IO_BASE+KS8695_MEM_GENERAL)
+	ldr	r2, =0x30000005
+	str	r2, [r1]		/* enable both flash selects */
+
+#ifdef CONFIG_CM41xx
+	/*
+	 * map the second flash chip, using the external IO lines.
+	 */
+	ldr	r1, =(KS8695_IO_BASE+KS8695_IO_CTRL0)
+	ldr	r2, =0xafe80b6d
+	str	r2, [r1]		/* remap io0 region, contiguous */
+	ldr	r1, =(KS8695_IO_BASE+KS8695_IO_CTRL1)
+	ldr	r2, =0xbfec0b6d
+	str	r2, [r1]		/* remap io1 region, contiguous */
+	ldr	r1, =(KS8695_IO_BASE+KS8695_MEM_GENERAL)
+	ldr	r2, =0x30050005
+	str	r2, [r1]		/* enable second flash */
+#endif
+
+	/*
+	 * before relocating, we have to setup RAM timing
+	 */
+	ldr	r1, =(KS8695_IO_BASE+KS8695_SDRAM_CTRL0)
+#if (PHYS_SDRAM_1_SIZE == 0x02000000)
+	ldr	r2, =0x7fc0000e		/* 32MB */
+#else
+	ldr	r2, =0x3fc0000e		/* 16MB */
+#endif
+	str	r2, [r1]		/* configure sdram bank0 setup */
+	ldr	r1, =(KS8695_IO_BASE+KS8695_SDRAM_CTRL1)
+	mov	r2, #0
+	str	r2, [r1]		/* configure sdram bank1 setup */
+
+	ldr	r1, =(KS8695_IO_BASE+KS8695_SDRAM_GENERAL)
+	ldr	r2, =0x0000000a
+	str	r2, [r1]		/* set RAS/CAS timing */
+
+	ldr	r1, =(KS8695_IO_BASE+KS8695_SDRAM_BUFFER)
+	ldr	r2, =0x00030000
+	str	r2, [r1]		/* send NOP command */
+	DELAY_FOR 0x100, r0
+	ldr	r2, =0x00010000
+	str	r2, [r1]		/* send PRECHARGE-ALL */
+	DELAY_FOR 0x100, r0
+
+	ldr	r1, =(KS8695_IO_BASE+KS8695_SDRAM_REFRESH)
+	ldr	r2, =0x00000020
+	str	r2, [r1]		/* set for fast refresh */
+	DELAY_FOR 0x100, r0
+	ldr	r2, =0x00000190
+	str	r2, [r1]		/* set normal refresh timing */
+
+	ldr	r1, =(KS8695_IO_BASE+KS8695_SDRAM_BUFFER)
+	ldr	r2, =0x00020033
+	str	r2, [r1]		/* send mode command */
+	DELAY_FOR 0x100, r0
+	ldr	r2, =0x01f00000
+	str	r2, [r1]		/* enable sdram fifos */
+
+	/*
+	 * set pll to top speed
+	 */
+	ldr	r1, =(KS8695_IO_BASE+KS8695_SYSTEN_BUS_CLOCK)
+	mov	r2, #0
+	str	r2, [r1]		/* set pll clock to 166MHz */
+
+	ldr	r1, =(KS8695_IO_BASE+KS8695_SWITCH_CTRL0)
+	ldr	r2, [r1]		/* Get switch ctrl0 register       */
+	and	r2, r2, #0x0fc00000	/* Mask out LED control bits       */
+	orr	r2, r2, #0x01800000	/* Set Link/activity/speed actions */
+	str	r2, [r1]
+
+#ifdef CONFIG_CM4008
+	ldr	r1, =(KS8695_IO_BASE+KS8695_GPIO_MODE)
+	ldr	r2, =0x0000fe30
+	str	r2, [r1]		/* enable LED's as outputs	    */
+	ldr	r1, =(KS8695_IO_BASE+KS8695_GPIO_DATA)
+	ldr	r2, =0x0000fe20
+	str	r2, [r1]		/* turn on power LED		    */
+#endif
+#if defined(CONFIG_CM4008) || defined(CONFIG_CM41xx)
+	ldr	r2, [r1]		/* get current GPIO input data	    */
+	tst	r2, #0x8		/* check if "erase" depressed	    */
+	beq	nobutton
+	mov	r2, #0			/* be quiet on boot, no console	    */
+	ldr	r1, =serial_console
+	str	r2, [r1]
+nobutton:
+#endif
+
+	add	lr, lr, #0x02000000	/* flash is now mapped high */
+	add	ip, ip, #0x02000000	/* this is a hack */
+	mov	pc, lr			/* all done, return */
+
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */

cpu/arm920t/ks8695/serial.c

@@ -0,0 +1,116 @@
+/*
+ * serial.c -- KS8695 serial driver
+ *
+ * (C) Copyright 2004, Greg Ungerer <greg.ungerer@opengear.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <common.h>
+#include <asm/arch/platform.h>
+
+#ifndef CONFIG_SERIAL1
+#error "Bad: you didn't configure serial ..."
+#endif
+
+/*
+ *	Define the UART hardware register access structure.
+ */
+struct ks8695uart {
+	unsigned int	RX;		/* 0x00	- Receive data (r) */
+	unsigned int	TX;		/* 0x04	- Transmit data (w) */
+	unsigned int	FCR;		/* 0x08	- Fifo Control (r/w) */
+	unsigned int	LCR;		/* 0x0c	- Line Control (r/w) */
+	unsigned int	MCR;		/* 0x10	- Modem Control (r/w) */
+	unsigned int	LSR;		/* 0x14	- Line Status (r/w) */
+	unsigned int	MSR;		/* 0x18	- Modem Status (r/w) */
+	unsigned int	BD;		/* 0x1c	- Baud Rate (r/w) */
+	unsigned int	SR;		/* 0x20	- Status (r/w) */
+};
+
+#define	KS8695_UART_ADDR	((void *) (KS8695_IO_BASE + KS8695_UART_RX_BUFFER))
+#define	KS8695_UART_CLK		25000000
+
+
+/*
+ * Under some circumstances we want to be "quiet" and not issue any
+ * serial output - though we want u-boot to otherwise work and behave
+ * the same. By default be noisy.
+ */
+int serial_console = 1;
+
+
+void serial_setbrg(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	volatile struct ks8695uart *uartp = KS8695_UART_ADDR;
+
+	/* Set to global baud rate and 8 data bits, no parity, 1 stop bit*/
+	uartp->BD = KS8695_UART_CLK / gd->baudrate;
+	uartp->LCR = KS8695_UART_LINEC_WLEN8;
+}
+
+int serial_init(void)
+{
+	serial_console = 1;
+	serial_setbrg();
+	return 0;
+}
+
+void serial_raw_putc(const char c)
+{
+	volatile struct ks8695uart *uartp = KS8695_UART_ADDR;
+	int i;
+
+	for (i = 0; (i < 0x100000); i++) {
+		if (uartp->LSR & KS8695_UART_LINES_TXFE)
+			break;
+	}
+
+	uartp->TX = c;
+}
+
+void serial_putc(const char c)
+{
+	if (serial_console) {
+		serial_raw_putc(c);
+		if (c == '\n')
+			serial_raw_putc('\r');
+	}
+}
+
+int serial_tstc(void)
+{
+	volatile struct ks8695uart *uartp = KS8695_UART_ADDR;
+	if (serial_console)
+		return ((uartp->LSR & KS8695_UART_LINES_RXFE) ? 1 : 0);
+	return 0;
+}
+
+void serial_puts(const char *s)
+{
+	char c;
+	while ((c = *s++) != 0)
+		serial_putc(c);
+}
+
+int serial_getc(void)
+{
+	volatile struct ks8695uart *uartp = KS8695_UART_ADDR;
+
+	while ((uartp->LSR & KS8695_UART_LINES_RXFE) == 0)
+		;
+	return (uartp->RX);
+}

cpu/mpc5xxx/fec.c

@@ -869,9 +869,10 @@ int mpc5xxx_fec_initialize(bd_t * bis)
 	fec->eth = (ethernet_regs *)MPC5XXX_FEC;
 	fec->tbdBase = (FEC_TBD *)FEC_BD_BASE;
 	fec->rbdBase = (FEC_RBD *)(FEC_BD_BASE + FEC_TBD_NUM * sizeof(FEC_TBD));
-#if defined(CONFIG_CANMB)   || defined(CONFIG_ICECUBE) || \
-    defined(CONFIG_INKA4X0) || defined(CONFIG_PM520)   || \
-    defined(CONFIG_TOP5200) || defined(CONFIG_TQM5200)
+#if defined(CONFIG_CANMB)   || defined(CONFIG_HMI1001)	|| \
+    defined(CONFIG_ICECUBE) || defined(CONFIG_INKA4X0)	|| \
+    defined(CONFIG_PM520)   || defined(CONFIG_TOP5200)	|| \
+    defined(CONFIG_TQM5200)
 # ifndef CONFIG_FEC_10MBIT
 	fec->xcv_type = MII100;
 # else

cpu/mpc5xxx/serial.c

@@ -154,11 +154,11 @@ serial_setbrg(void)
 #if defined(CONFIG_MGT5100)
 	baseclk = CFG_MPC5XXX_CLKIN / 32;
 #elif defined(CONFIG_MPC5200)
-	baseclk = gd->ipb_clk / 32;
+	baseclk = (gd->ipb_clk + 16) / 32;
 #endif
 
 	/* set up UART divisor */
-	div = baseclk / gd->baudrate;
+	div = (baseclk + (gd->baudrate/2)) / gd->baudrate;
 	psc->ctur = div >> 8;
 	psc->ctlr = div & 0xff;
 }

cpu/mpc8220/Makefile

@@ -28,8 +28,8 @@ LIB	= lib$(CPU).a
 START	= start.o
 ASOBJS	= io.o fec_dma_tasks.o
 OBJS	= cpu.o cpu_init.o dramSetup.o fec.o i2c.o \
-	  interrupts.o loadtask.o serial.o speed.o \
-	  traps.o uart.o
+	  interrupts.o loadtask.o speed.o \
+	  traps.o uart.o pci.o
 
 all:	.depend $(START) $(ASOBJS) $(LIB)
 

cpu/mpc8220/cpu_init.c

@@ -49,6 +49,8 @@ void cpu_init_f (void)
 	portcfg->pcfg1 = 0;
 	portcfg->pcfg2 = 0;
 	portcfg->pcfg3 = 0;
+	portcfg->pcfg2 = CFG_GP1_PORT2_CONFIG;
+	portcfg->pcfg3 = CFG_PCI_PORT3_CONFIG | CFG_GP2_PORT3_CONFIG;
 
 	/*
 	 * Flexbus Controller: configure chip selects and enable them
@@ -109,7 +111,7 @@ void cpu_init_f (void)
 
 	/* Master Priority Enable */
 	xlbarb->mastPriority = 0;
-	xlbarb->mastPriEn = 0x1f;
+	xlbarb->mastPriEn = 0xff;
 }
 
 /*

cpu/mpc8220/dramSetup.c

@@ -543,12 +543,7 @@ u32 dramSetup (void)
 	}
 
 	/* Set up the Drive Strength register */
-	temp = ((DRIVE_STRENGTH_LOW << SDRAMDS_SBE_SHIFT)
-		| (DRIVE_STRENGTH_HIGH << SDRAMDS_SBC_SHIFT)
-		| (DRIVE_STRENGTH_LOW << SDRAMDS_SBA_SHIFT)
-		| (DRIVE_STRENGTH_OFF << SDRAMDS_SBS_SHIFT)
-		| (DRIVE_STRENGTH_LOW << SDRAMDS_SBD_SHIFT));
-	sysconf->sdramds = temp;
+	sysconf->sdramds = CFG_SDRAM_DRIVE_STRENGTH;
 
 	/* ********************** Cfg 1 ************************* */
 

cpu/mpc8220/fec.c

@@ -14,19 +14,18 @@
 #include "dma.h"
 #include "fec.h"
 
-#define DEBUG	0
-/*tbd - rtm */
-/*#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \
-    defined(CONFIG_MPC8220_FEC)*/
+#undef  DEBUG
+#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \
+    defined(CONFIG_MPC8220_FEC)
 
-#if (CONFIG_COMMANDS & CFG_CMD_NET)
+/*#if (CONFIG_COMMANDS & CFG_CMD_NET)*/
 
-#if (DEBUG & 0x60)
+#ifdef DEBUG
 static void tfifo_print (mpc8220_fec_priv * fec);
 static void rfifo_print (mpc8220_fec_priv * fec);
 #endif /* DEBUG */
 
-#if (DEBUG & 0x40)
+#ifdef DEBUG
 static u32 local_crc32 (char *string, unsigned int crc_value, int len);
 #endif
 
@@ -38,7 +37,7 @@ typedef struct {
 } NBUF;
 
 /********************************************************************/
-#if (DEBUG & 0x2)
+#ifdef DEBUG
 static void mpc8220_fec_phydump (void)
 {
 	u16 phyStatus, i;
@@ -145,7 +144,7 @@ static void mpc8220_fec_tbd_scrub (mpc8220_fec_priv * fec)
 {
 	FEC_TBD *pUsedTbd;
 
-#if (DEBUG & 0x1)
+#ifdef DEBUG
 	printf ("tbd_scrub: fec->cleanTbdNum = %d, fec->usedTbdIndex = %d\n",
 		fec->cleanTbdNum, fec->usedTbdIndex);
 #endif
@@ -156,7 +155,7 @@ static void mpc8220_fec_tbd_scrub (mpc8220_fec_priv * fec)
 	while (fec->cleanTbdNum < FEC_TBD_NUM) {
 		pUsedTbd = &fec->tbdBase[fec->usedTbdIndex];
 		if (pUsedTbd->status & FEC_TBD_READY) {
-#if (DEBUG & 0x20)
+#ifdef DEBUG
 			printf ("Cannot clean TBD %d, in use\n",
 				fec->cleanTbdNum);
 #endif
@@ -243,7 +242,7 @@ static int mpc8220_fec_init (struct eth_device *dev, bd_t * bis)
 	struct mpc8220_dma *dma = (struct mpc8220_dma *) MMAP_DMA;
 	const u8 phyAddr = CONFIG_PHY_ADDR;	/* Only one PHY */
 
-#if (DEBUG & 0x1)
+#ifdef DEBUG
 	printf ("mpc8220_fec_init... Begin\n");
 #endif
 
@@ -305,7 +304,7 @@ static int mpc8220_fec_init (struct eth_device *dev, bd_t * bis)
 	 */
 	fec->eth->rfifo_cntrl = 0x0c000000;
 	fec->eth->rfifo_alarm = 0x0000030c;
-#if (DEBUG & 0x22)
+#ifdef DEBUG
 	if (fec->eth->rfifo_status & 0x00700000) {
 		printf ("mpc8220_fec_init() RFIFO error\n");
 	}
@@ -316,7 +315,7 @@ static int mpc8220_fec_init (struct eth_device *dev, bd_t * bis)
 	 */
 	/*fec->eth->tfifo_cntrl = 0x0c000000; */ /*tbd - rtm */
 	fec->eth->tfifo_cntrl = 0x0e000000;
-#if (DEBUG & 0x2)
+#ifdef DEBUG
 	printf ("tfifo_status: 0x%08x\n", fec->eth->tfifo_status);
 	printf ("tfifo_alarm: 0x%08x\n", fec->eth->tfifo_alarm);
 #endif
@@ -408,7 +407,7 @@ static int mpc8220_fec_init (struct eth_device *dev, bd_t * bis)
 			/*
 			 * Force 10Base-T, FDX operation
 			 */
-#if (DEBUG & 0x2)
+#ifdef DEBUG
 			printf ("Forcing 10 Mbps ethernet link... ");
 #endif
 			miiphy_read (phyAddr, 0x1, &phyStatus);
@@ -421,13 +420,13 @@ static int mpc8220_fec_init (struct eth_device *dev, bd_t * bis)
 			do {	/* wait for link status to go down */
 				udelay (10000);
 				if ((timeout--) == 0) {
-#if (DEBUG & 0x2)
+#ifdef DEBUG
 					printf ("hmmm, should not have waited...");
 #endif
 					break;
 				}
 				miiphy_read (phyAddr, 0x1, &phyStatus);
-#if (DEBUG & 0x2)
+#ifdef DEBUG
 				printf ("=");
 #endif
 			} while ((phyStatus & 0x0004)); /* !link up */
@@ -440,12 +439,12 @@ static int mpc8220_fec_init (struct eth_device *dev, bd_t * bis)
 					break;
 				}
 				miiphy_read (phyAddr, 0x1, &phyStatus);
-#if (DEBUG & 0x2)
+#ifdef DEBUG
 				printf ("+");
 #endif
 			} while (!(phyStatus & 0x0004));	/* !link up */
 
-#if (DEBUG & 0x2)
+#ifdef DEBUG
 			printf ("done.\n");
 #endif
 		} else {	/* MII100 */
@@ -467,7 +466,7 @@ static int mpc8220_fec_init (struct eth_device *dev, bd_t * bis)
 				udelay (1000);
 
 				if ((timeout--) == 0) {
-#if (DEBUG & 0x2)
+#ifdef DEBUG
 					printf ("PHY auto neg 0 failed...\n");
 #endif
 					return -1;
@@ -475,14 +474,14 @@ static int mpc8220_fec_init (struct eth_device *dev, bd_t * bis)
 
 				if (miiphy_read (phyAddr, 0x1, &phyStatus) !=
 				    0) {
-#if (DEBUG & 0x2)
+#ifdef DEBUG
 					printf ("PHY auto neg 1 failed 0x%04x...\n", phyStatus);
 #endif
 					return -1;
 				}
 			} while (!(phyStatus & 0x0004));
 
-#if (DEBUG & 0x2)
+#ifdef DEBUG
 			printf ("PHY auto neg complete! \n");
 #endif
 		}
@@ -494,7 +493,7 @@ static int mpc8220_fec_init (struct eth_device *dev, bd_t * bis)
 	 */
 	fec->eth->ecntrl |= 0x00000006;
 
-#if (DEBUG & 0x2)
+#ifdef DEBUG
 	if (fec->xcv_type != SEVENWIRE)
 		mpc8220_fec_phydump ();
 #endif
@@ -504,7 +503,7 @@ static int mpc8220_fec_init (struct eth_device *dev, bd_t * bis)
 	 */
 	DMA_TASK_ENABLE (FEC_RECV_TASK_NO);
 
-#if (DEBUG & 0x1)
+#ifdef DEBUG
 	printf ("mpc8220_fec_init... Done \n");
 #endif
 
@@ -517,7 +516,7 @@ static void mpc8220_fec_halt (struct eth_device *dev)
 	mpc8220_fec_priv *fec = (mpc8220_fec_priv *) dev->priv;
 	int counter = 0xffff;
 
-#if (DEBUG & 0x2)
+#ifdef DEBUG
 	if (fec->xcv_type != SEVENWIRE)
 		mpc8220_fec_phydump ();
 #endif
@@ -566,12 +565,12 @@ static void mpc8220_fec_halt (struct eth_device *dev)
 	 */
 	udelay (10);
 
-#if (DEBUG & 0x3)
+#ifdef DEBUG
 	printf ("Ethernet task stopped\n");
 #endif
 }
 
-#if (DEBUG & 0x60)
+#ifdef DEBUG
 /********************************************************************/
 
 static void tfifo_print (mpc8220_fec_priv * fec)
@@ -635,7 +634,7 @@ static int mpc8220_fec_send (struct eth_device *dev, volatile void *eth_data,
 	mpc8220_fec_priv *fec = (mpc8220_fec_priv *) dev->priv;
 	FEC_TBD *pTbd;
 
-#if (DEBUG & 0x20)
+#ifdef DEBUG
 	printf ("tbd status: 0x%04x\n", fec->tbdBase[0].status);
 	tfifo_print (fec);
 #endif
@@ -656,7 +655,7 @@ static int mpc8220_fec_send (struct eth_device *dev, volatile void *eth_data,
 	 * Check the number of vacant TxBDs.
 	 */
 	if (fec->cleanTbdNum < 1) {
-#if (DEBUG & 0x20)
+#ifdef DEBUG
 		printf ("No available TxBDs ...\n");
 #endif
 		return -1;
@@ -671,7 +670,7 @@ static int mpc8220_fec_send (struct eth_device *dev, volatile void *eth_data,
 	pTbd->status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
 	fec->tbdIndex = (fec->tbdIndex + 1) % FEC_TBD_NUM;
 
-#if (DEBUG & 0x100)
+#ifdef DEBUG
 	printf ("DMA_TASK_ENABLE, fec->tbdIndex = %d \n", fec->tbdIndex);
 #endif
 
@@ -688,23 +687,23 @@ static int mpc8220_fec_send (struct eth_device *dev, volatile void *eth_data,
 	 * Enable SmartDMA transmit task
 	 */
 
-#if (DEBUG & 0x20)
+#ifdef DEBUG
 	tfifo_print (fec);
 #endif
 
 	DMA_TASK_ENABLE (FEC_XMIT_TASK_NO);
 
-#if (DEBUG & 0x20)
+#ifdef DEBUG
 	tfifo_print (fec);
 #endif
 
-#if (DEBUG & 0x8)
+#ifdef DEBUG
 	printf ("+");
 #endif
 
 	fec->cleanTbdNum -= 1;
 
-#if (DEBUG & 0x129) && (DEBUG & 0x80000000)
+#ifdef DEBUG
 	printf ("smartDMA ethernet Tx task enabled\n");
 #endif
 	/*
@@ -712,7 +711,7 @@ static int mpc8220_fec_send (struct eth_device *dev, volatile void *eth_data,
 	 */
 	while (pTbd->status & FEC_TBD_READY) {
 		udelay (10);
-#if (DEBUG & 0x8)
+#ifdef DEBUG
 		printf ("TDB status = %04x\n", pTbd->status);
 #endif
 	}
@@ -733,10 +732,8 @@ static int mpc8220_fec_recv (struct eth_device *dev)
 	int frame_length, len = 0;
 	NBUF *frame;
 
-#if (DEBUG & 0x1)
+#ifdef DEBUG
 	printf ("mpc8220_fec_recv %d Start...\n", fec->rbdIndex);
-#endif
-#if (DEBUG & 0x8)
 	printf ("-");
 #endif
 
@@ -902,7 +899,7 @@ int miiphy_read (u8 phyAddr, u8 regAddr, u16 * retVal)
 	while ((timeout--) && (!(eth->ievent & 0x00800000)));
 
 	if (timeout == 0) {
-#if (DEBUG & 0x2)
+#ifdef DEBUG
 		printf ("Read MDIO failed...\n");
 #endif
 		return -1;
@@ -941,7 +938,7 @@ int miiphy_write (u8 phyAddr, u8 regAddr, u16 data)
 	while ((timeout--) && (!(eth->ievent & 0x00800000)));
 
 	if (timeout == 0) {
-#if (DEBUG & 0x2)
+#ifdef DEBUG
 		printf ("Write MDIO failed...\n");
 #endif
 		return -1;
@@ -955,7 +952,7 @@ int miiphy_write (u8 phyAddr, u8 regAddr, u16 data)
 	return 0;
 }
 
-#if (DEBUG & 0x40)
+#ifdef DEBUG
 static u32 local_crc32 (char *string, unsigned int crc_value, int len)
 {
 	int i;

cpu/mpc8220/pci.c

@@ -0,0 +1,191 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ * Copyright (C) 2003 Motorola Inc.
+ * Xianghua Xiao (x.xiao@motorola.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * PCI Configuration space access support for MPC8220 PCI Bridge
+ */
+#include <common.h>
+#include <mpc8220.h>
+#include <pci.h>
+#include <asm/io.h>
+
+#if defined(CONFIG_PCI)
+
+/* System RAM mapped over PCI */
+#define CONFIG_PCI_SYS_MEM_BUS	 CFG_SDRAM_BASE
+#define CONFIG_PCI_SYS_MEM_PHYS	 CFG_SDRAM_BASE
+#define CONFIG_PCI_SYS_MEM_SIZE	 (1024 * 1024 * 1024)
+
+#define cfg_read(val, addr, type, op)		*val = op((type)(addr));
+#define cfg_write(val, addr, type, op)		op((type *)(addr), (val));
+
+#define PCI_OP(rw, size, type, op, mask)				\
+int mpc8220_pci_##rw##_config_##size(struct pci_controller *hose,	\
+	pci_dev_t dev, int offset, type val)				\
+{									\
+	u32 addr = 0;							\
+	u16 cfg_type = 0;						\
+	addr = ((offset & 0xfc) | cfg_type | (dev)  | 0x80000000);	\
+	out_be32(hose->cfg_addr, addr);					\
+	__asm__ __volatile__("sync");					\
+	cfg_##rw(val, hose->cfg_data + (offset & mask), type, op);	\
+	out_be32(hose->cfg_addr, addr & 0x7fffffff);			\
+	__asm__ __volatile__("sync");					\
+	return 0;							\
+}
+
+PCI_OP(read, byte, u8 *, in_8, 3)
+PCI_OP(read, word, u16 *, in_le16, 2)
+PCI_OP(write, byte, u8, out_8, 3)
+PCI_OP(write, word, u16, out_le16, 2)
+PCI_OP(write, dword, u32, out_le32, 0)
+
+int mpc8220_pci_read_config_dword(struct pci_controller *hose, pci_dev_t dev,
+	int offset, u32 *val)
+{
+	u32 addr;
+	u32 tmpv;
+	u32 mask = 2;	 /* word access */
+	/* Read lower 16 bits */
+	addr = ((offset & 0xfc) | (dev) | 0x80000000);
+	out_be32(hose->cfg_addr, addr);
+	__asm__ __volatile__("sync");
+	*val = (u32) in_le16((u16 *) (hose->cfg_data + (offset & mask)));
+	out_be32(hose->cfg_addr, addr & 0x7fffffff);
+	__asm__ __volatile__("sync");
+
+	/* Read upper 16 bits */
+	offset += 2;
+	addr = ((offset & 0xfc) | 1 | (dev) | 0x80000000);
+	out_be32(hose->cfg_addr, addr);
+	__asm__ __volatile__("sync");
+	tmpv = (u32) in_le16((u16 *) (hose->cfg_data + (offset & mask)));
+	out_be32(hose->cfg_addr, addr & 0x7fffffff);
+	__asm__ __volatile__("sync");
+
+	/* combine results into dword value */
+	*val = (tmpv << 16) | *val;
+
+	return 0;
+}
+
+void
+pci_mpc8220_init(struct pci_controller *hose)
+{
+	u32 win0, win1, win2;
+	volatile mpc8220_xcpci_t *xcpci =
+		(volatile mpc8220_xcpci_t *) MMAP_XCPCI;
+
+	volatile pcfg8220_t *portcfg = (volatile pcfg8220_t *) MMAP_PCFG;
+
+	win0 = (u32) CONFIG_PCI_MEM_PHYS;
+	win1 = (u32) CONFIG_PCI_IO_PHYS;
+	win2 = (u32) CONFIG_PCI_CFG_PHYS;
+
+	/* Assert PCI reset */
+	out_be32 (&xcpci->glb_stat_ctl, PCI_GLB_STAT_CTRL_PR);
+
+	/* Disable prefetching but read-multiples will still prefetch */
+	out_be32 (&xcpci->target_ctrl, 0x00000000);
+
+	/* Initiator windows */
+	out_be32 (&xcpci->init_win0,  (win0 >> 16) | win0 | 0x003f0000);
+	out_be32 (&xcpci->init_win1, ((win1 >> 16) | win1 ));
+	out_be32 (&xcpci->init_win2, ((win2 >> 16) | win2 ));
+
+	out_be32 (&xcpci->init_win_cfg,
+		PCI_INIT_WIN_CFG_WIN0_CTRL_EN |
+		PCI_INIT_WIN_CFG_WIN1_CTRL_EN | PCI_INIT_WIN_CFG_WIN1_CTRL_IO |
+		PCI_INIT_WIN_CFG_WIN2_CTRL_EN | PCI_INIT_WIN_CFG_WIN2_CTRL_IO);
+
+	out_be32 (&xcpci->init_ctrl, 0x00000000);
+
+	/* Enable bus master and mem access */
+	out_be32 (&xcpci->stat_cmd_reg, PCI_STAT_CMD_B | PCI_STAT_CMD_M);
+
+	/* Cache line size and master latency */
+	out_be32 (&xcpci->bist_htyp_lat_cshl, (0xf8 << PCI_CFG1_LT_SHIFT));
+
+	out_be32 (&xcpci->base0, PCI_BASE_ADDR_REG0); /* 256MB - MBAR space */
+	out_be32 (&xcpci->base1, PCI_BASE_ADDR_REG1); /* 1GB - SDRAM space */
+
+	out_be32 (&xcpci->target_bar0,
+		PCI_TARGET_BASE_ADDR_REG0 | PCI_TARGET_BASE_ADDR_EN);
+	out_be32 (&xcpci->target_bar1,
+		PCI_TARGET_BASE_ADDR_REG1 | PCI_TARGET_BASE_ADDR_EN);
+
+	/* Deassert reset bit */
+	out_be32 (&xcpci->glb_stat_ctl, 0x00000000);
+
+	/* Enable PCI bus master support */
+	/* Set PCIGNT1, PCIREQ1, PCIREQ0/PCIGNTIN, PCIGNT0/PCIREQOUT,
+	       PCIREQ2, PCIGNT2 */
+	out_be32((volatile u32 *)&portcfg->pcfg3,
+		(in_be32((volatile u32 *)&portcfg->pcfg3) & 0xFC3FCE7F));
+	out_be32((volatile u32 *)&portcfg->pcfg3,
+		(in_be32((volatile u32 *)&portcfg->pcfg3) | 0x01400180));
+
+	hose->first_busno = 0;
+	hose->last_busno = 0xff;
+
+	pci_set_region(hose->regions + 0,
+		CONFIG_PCI_MEM_BUS,
+		CONFIG_PCI_MEM_PHYS,
+		CONFIG_PCI_MEM_SIZE,
+		PCI_REGION_MEM);
+
+	pci_set_region(hose->regions + 1,
+		CONFIG_PCI_IO_BUS,
+		CONFIG_PCI_IO_PHYS,
+		CONFIG_PCI_IO_SIZE,
+		PCI_REGION_IO);
+
+	pci_set_region(hose->regions + 2,
+		CONFIG_PCI_SYS_MEM_BUS,
+		CONFIG_PCI_SYS_MEM_PHYS,
+		CONFIG_PCI_SYS_MEM_SIZE,
+		PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+	hose->region_count = 3;
+
+	hose->cfg_addr = &(xcpci->cfg_adr);
+	hose->cfg_data = CONFIG_PCI_CFG_BUS;
+
+	pci_set_ops(hose,
+		mpc8220_pci_read_config_byte,
+		mpc8220_pci_read_config_word,
+		mpc8220_pci_read_config_dword,
+		mpc8220_pci_write_config_byte,
+		mpc8220_pci_write_config_word,
+		mpc8220_pci_write_config_dword);
+
+	/* Hose scan */
+	pci_register_hose(hose);
+	hose->last_busno = pci_hose_scan(hose);
+
+	out_be32 (&xcpci->base0, PCI_BASE_ADDR_REG0); /* 256MB - MBAR space */
+	out_be32 (&xcpci->base1, PCI_BASE_ADDR_REG1); /* 1GB - SDRAM space */
+}
+
+#endif /* CONFIG_PCI */

cpu/mpc8220/serial.c

@@ -1,131 +0,0 @@
-/*
- * (C) Copyright 2004, Freescale, Inc
- * TsiChung Liew, Tsi-Chung.Liew@freescale.com.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-
-/*
- * Minimal serial functions needed to use one of the PSC ports
- * as serial console interface.
- */
-
-#include <common.h>
-#include <mpc8220.h>
-
-int serial_init (void)
-{
-	DECLARE_GLOBAL_DATA_PTR;
-
-#if defined (CONFIG_EXTUART_CONSOLE)
-	volatile uchar *cpld = (volatile uchar *) CFG_CPLD_BASE;
-#endif
-
-	/* Check CPLD Switch 2 whether is external or internal */
-#if defined (CONFIG_EXTUART_CONSOLE)
-	if ((*cpld & 0x02) == 0x02) {
-		gd->bExtUart = 1;
-		return ext_serial_init ();
-	} else
-#endif
-	{
-#if defined(CONFIG_PSC_CONSOLE)
-		gd->bExtUart = 0;
-		return psc_serial_init ();
-#endif
-	}
-
-	return (0);
-}
-
-void serial_putc (const char c)
-{
-	DECLARE_GLOBAL_DATA_PTR;
-
-	if (gd->bExtUart) {
-#if defined (CONFIG_EXTUART_CONSOLE)
-		ext_serial_putc (c);
-#endif
-	} else {
-#if defined(CONFIG_PSC_CONSOLE)
-		psc_serial_putc (c);
-#endif
-	}
-}
-
-void serial_puts (const char *s)
-{
-	DECLARE_GLOBAL_DATA_PTR;
-
-	if (gd->bExtUart) {
-#if defined (CONFIG_EXTUART_CONSOLE)
-		ext_serial_puts (s);
-#endif
-	} else {
-#if defined(CONFIG_PSC_CONSOLE)
-		psc_serial_puts (s);
-#endif
-	}
-}
-
-int serial_getc (void)
-{
-	DECLARE_GLOBAL_DATA_PTR;
-
-	if (gd->bExtUart) {
-#if defined (CONFIG_EXTUART_CONSOLE)
-		return ext_serial_getc ();
-#endif
-	} else {
-#if defined(CONFIG_PSC_CONSOLE)
-		return psc_serial_getc ();
-#endif
-	}
-}
-
-int serial_tstc (void)
-{
-	DECLARE_GLOBAL_DATA_PTR;
-
-	if (gd->bExtUart) {
-#if defined (CONFIG_EXTUART_CONSOLE)
-		return ext_serial_tstc ();
-#endif
-	} else {
-#if defined(CONFIG_PSC_CONSOLE)
-		return psc_serial_tstc ();
-#endif
-	}
-}
-
-void serial_setbrg (void)
-{
-	DECLARE_GLOBAL_DATA_PTR;
-
-	if (gd->bExtUart) {
-#if defined (CONFIG_EXTUART_CONSOLE)
-		ext_serial_setbrg ();
-#endif
-	} else {
-#if defined(CONFIG_PSC_CONSOLE)
-		psc_serial_setbrg ();
-#endif
-	}
-}

cpu/mpc8220/uart.c

@@ -33,7 +33,7 @@
 #define PSC_BASE   MMAP_PSC1
 
 #if defined(CONFIG_PSC_CONSOLE)
-int psc_serial_init (void)
+int serial_init (void)
 {
 	DECLARE_GLOBAL_DATA_PTR;
 	volatile psc8220_t *psc = (psc8220_t *) PSC_BASE;
@@ -68,7 +68,7 @@ int psc_serial_init (void)
 	return (0);
 }
 
-void psc_serial_putc (const char c)
+void serial_putc (const char c)
 {
 	volatile psc8220_t *psc = (psc8220_t *) PSC_BASE;
 
@@ -81,14 +81,14 @@ void psc_serial_putc (const char c)
 	psc->xmitbuf[0] = c;
 }
 
-void psc_serial_puts (const char *s)
+void serial_puts (const char *s)
 {
 	while (*s) {
 		serial_putc (*s++);
 	}
 }
 
-int psc_serial_getc (void)
+int serial_getc (void)
 {
 	volatile psc8220_t *psc = (psc8220_t *) PSC_BASE;
 
@@ -97,14 +97,14 @@ int psc_serial_getc (void)
 	return psc->xmitbuf[2];
 }
 
-int psc_serial_tstc (void)
+int serial_tstc (void)
 {
 	volatile psc8220_t *psc = (psc8220_t *) PSC_BASE;
 
 	return (psc->sr_csr & PSC_SR_RXRDY);
 }
 
-void psc_serial_setbrg (void)
+void serial_setbrg (void)
 {
 	DECLARE_GLOBAL_DATA_PTR;
 

cpu/mpc8260/cpu.c

@@ -220,6 +220,7 @@ void upmconfig (uint upm, uint * table, uint size)
 
 /* ------------------------------------------------------------------------- */
 
+#if !defined(CONFIG_HAVE_OWN_RESET)
 int
 do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 {
@@ -253,6 +254,7 @@ do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 	return 1;
 
 }
+#endif	/* CONFIG_HAVE_OWN_RESET */
 
 /* ------------------------------------------------------------------------- */
 

cpu/mpc85xx/interrupts.c

@@ -49,6 +49,22 @@ static __inline__ void set_msr(unsigned long msr)
 	asm volatile("isync");
 }
 
+static __inline__ unsigned long get_dec (void)
+{
+	unsigned long val;
+
+	asm volatile ("mfdec %0":"=r" (val):);
+
+	return val;
+}
+
+
+static __inline__ void set_dec (unsigned long val)
+{
+	if (val)
+		asm volatile ("mtdec %0"::"r" (val));
+}
+
 void enable_interrupts (void)
 {
 	set_msr (get_msr() | MSR_EE);
@@ -62,9 +78,17 @@ int disable_interrupts (void)
 	return ((msr & MSR_EE) != 0);
 }
 
-/* interrupt is not supported yet */
 int interrupt_init (void)
 {
+	volatile immap_t *immr = (immap_t *)CFG_IMMR;
+
+	immr->im_pic.gcr = MPC85xx_PICGCR_RST;
+	while (immr->im_pic.gcr & MPC85xx_PICGCR_RST);
+	immr->im_pic.gcr = MPC85xx_PICGCR_M;
+	decrementer_count = get_tbclk() / CFG_HZ;
+	mtspr(SPRN_TCR, TCR_PIE);
+	set_dec (decrementer_count);
+	set_msr (get_msr () | MSR_EE);
 	return (0);
 }
 
@@ -96,9 +120,9 @@ volatile ulong timestamp = 0;
  */
 void timer_interrupt(struct pt_regs *regs)
 {
-	printf ("*** Timer Interrupt *** ");
 	timestamp++;
-
+	set_dec (decrementer_count);
+	mtspr(SPRN_TSR, TSR_PIS);
 #if defined(CONFIG_WATCHDOG)
 	if ((timestamp % 1000) == 0)
 		reset_85xx_watchdog();

cpu/mpc85xx/start.S

@@ -115,8 +115,8 @@ _start_e500:
 	 * BookE: isync after MSR,PID; msync_isync after tlbivax & tlbwe
 	 * E500:  msync,isync before L1CSR0
 	 * E500:  isync after BBEAR,BBTAR,BUCSR,DBCR0,DBCR1,HID0,HID1,
-	 *        L1CSR0, L1CSR1, MAS[0,1,2,3,4,6],MMUCSR0, PID[0,1,2],
-	 *        SPEFCSR
+	 *	  L1CSR0, L1CSR1, MAS[0,1,2,3,4,6],MMUCSR0, PID[0,1,2],
+	 *	  SPEFCSR
 	 */
 
 	/* invalidate d-cache */
@@ -172,21 +172,21 @@ _start_e500:
 	mtspr	TCR,r0
 
 	mtspr	BUCSR,r0	/* disable branch prediction */
-	mtspr   MAS4,r0
-	mtspr   MAS6,r0
+	mtspr	MAS4,r0
+	mtspr	MAS6,r0
 	isync
 
 	/* Setup interrupt vectors */
-	lis     r1,0xfff8
+	lis	r1,TEXT_BASE@h
 	mtspr IVPR, r1
 
-	li      r1,0x0100
+	li	r1,0x0100
 	mtspr	IVOR0,r1	/* 0: Critical input */
-	li      r1,0x0200
+	li	r1,0x0200
 	mtspr	IVOR1,r1	/* 1: Machine check */
-	li      r1,0x0300
+	li	r1,0x0300
 	mtspr	IVOR2,r1	/* 2: Data storage */
-	li      r1,0x0400
+	li	r1,0x0400
 	mtspr	IVOR3,r1	/* 3: Instruction storage */
 	li	r1,0x0500
 	mtspr	IVOR4,r1	/* 4: External interrupt */
@@ -196,16 +196,20 @@ _start_e500:
 	mtspr	IVOR6,r1	/* 6: Program check */
 	li	r1,0x0800
 	mtspr	IVOR7,r1	/* 7: floating point unavailable */
-	li	r1,0x0c00
+	li	r1,0x0900
 	mtspr	IVOR8,r1	/* 8: System call */
 	/* 9: Auxiliary processor unavailable(unsupported) */
-	li	r1,0x1000
+	li	r1,0x0a00
 	mtspr	IVOR10,r1	/* 10: Decrementer */
-	li	r1,0x1400
+	li	r1,0x0b00
+	mtspr	IVOR11,r1	/* 11: Interval timer */
+	li	r1,0x0c00
+	mtspr	IVOR12,r1	/* 11: Watchdog timer */
+	li	r10,0x0d00
 	mtspr	IVOR13,r1	/* 13: Data TLB error */
-	li	r1,0x1300
+	li	r1,0x0e00
 	mtspr	IVOR14,r1	/* 14: Instruction TLB error */
-	li	r1,0x2000
+	li	r1,0x0f00
 	mtspr	IVOR15,r1	/* 15: Debug */
 
 	/*
@@ -214,16 +218,16 @@ _start_e500:
 	 * Note: There is a fixup earlier for Errata CPU4 on
 	 * Rev 1 parts that must precede this MMU invalidation.
 	 */
-	li      r2, 0x001e
-	mtspr   MMUCSR0, r2
+	li	r2, 0x001e
+	mtspr	MMUCSR0, r2
 	isync
 
 	/*
 	 * Invalidate all TLB0 entries.
 	 */
-	li 	r3,4
+	li	r3,4
 	li	r4,0
-	tlbivax	r4,r3
+	tlbivax r4,r3
 	/*
 	 * To avoid REV1 Errata CPU6 issues, make sure
 	 * the instruction following tlbivax is not a store.
@@ -240,7 +244,7 @@ _start_e500:
 	 * (e.g. board/<yourboard>/init.S)
 	 *
 	 */
-	bl 	tlb1_entry
+	bl	tlb1_entry
 	mr	r5,r0
 	li	r1,0x0020	/* max 16 TLB1 plus some TLB0 entries */
 	mtctr	r1
@@ -269,8 +273,8 @@ _start_e500:
 	lis	r4, CFG_CCSRBAR_DEFAULT@h
 	ori	r4, r4, CFG_CCSRBAR_DEFAULT@l
 
-	lis   	r5, CFG_CCSRBAR@h
-	ori   	r5, r5, CFG_CCSRBAR@l
+	lis	r5, CFG_CCSRBAR@h
+	ori	r5, r5, CFG_CCSRBAR@l
 	srwi	r6,r5,12
 	stw	r6, 0(r4)
 	isync
@@ -290,7 +294,7 @@ _start_e500:
 	lis	r7,CFG_CCSRBAR@h
 	ori	r7,r7,CFG_CCSRBAR@l
 
-	bl 	law_entry
+	bl	law_entry
 	mr	r6,r0
 	li	r1,0x0007	/* 8 LAWs, but reserve one for boot-over-rio-or-pci */
 	mtctr	r1
@@ -380,35 +384,35 @@ _start:
 
 /* L1 DCache is used for initial RAM */
 	mfspr	r2, L1CSR0
-	ori    	r2, r2, 0x0003
-	oris   	r2, r2, 0x0001
-	mtspr  	L1CSR0, r2	/* enable/invalidate L1 Dcache */
+	ori	r2, r2, 0x0003
+	oris	r2, r2, 0x0001
+	mtspr	L1CSR0, r2	/* enable/invalidate L1 Dcache */
 	isync
 
 	/* Allocate Initial RAM in data cache.
 	 */
-	lis     r3, CFG_INIT_RAM_ADDR@h
-	ori     r3, r3, CFG_INIT_RAM_ADDR@l
-	li      r2, 512 /* 512*32=16K */
-	mtctr   r2
+	lis	r3, CFG_INIT_RAM_ADDR@h
+	ori	r3, r3, CFG_INIT_RAM_ADDR@l
+	li	r2, 512 /* 512*32=16K */
+	mtctr	r2
 	li	r0, 0
 1:
 	dcbz	r0, r3
-	dcbtls  0,r0, r3
-	addi    r3, r3, 32
-	bdnz    1b
+	dcbtls	0,r0, r3
+	addi	r3, r3, 32
+	bdnz	1b
 
 #ifndef CFG_RAMBOOT
-	/* Calculate absolute address in FLASH and jump there           */
+	/* Calculate absolute address in FLASH and jump there		*/
 	/*--------------------------------------------------------------*/
-	lis     r3, CFG_MONITOR_BASE@h
-	ori     r3, r3, CFG_MONITOR_BASE@l
-	addi    r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
-	mtlr    r3
+	lis	r3, CFG_MONITOR_BASE@h
+	ori	r3, r3, CFG_MONITOR_BASE@l
+	addi	r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
+	mtlr	r3
 	blr
 
 in_flash:
-#endif  /* CFG_RAMBOOT */
+#endif	/* CFG_RAMBOOT */
 
 	/* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/
 	lis	r1,CFG_INIT_RAM_ADDR@h
@@ -485,105 +489,84 @@ ProgramCheck:
 	/* No FPU on MPC85xx.  This exception is not supposed to happen.
 	*/
 	STD_EXCEPTION(0x0800, FPUnavailable, UnknownException)
-	STD_EXCEPTION(0x0900, Decrementer, timer_interrupt)
-	STD_EXCEPTION(0x0a00, Trap_0a, UnknownException)
-	STD_EXCEPTION(0x0b00, Trap_0b, UnknownException)
 
-	. = 0x0c00
+	. = 0x0900
 /*
  * r0 - SYSCALL number
  * r3-... arguments
  */
 SystemCall:
-	addis   r11,r0,0                /* get functions table addr */
-	ori     r11,r11,0               /* Note: this code is patched in trap_init */
-	addis   r12,r0,0                /* get number of functions */
-	ori     r12,r12,0
+	addis	r11,r0,0		/* get functions table addr */
+	ori	r11,r11,0		/* Note: this code is patched in trap_init */
+	addis	r12,r0,0		/* get number of functions */
+	ori	r12,r12,0
 
-	cmplw   0, r0, r12
-	bge     1f
+	cmplw	0, r0, r12
+	bge	1f
 
-	rlwinm  r0,r0,2,0,31            /* fn_addr = fn_tbl[r0] */
-	add     r11,r11,r0
-	lwz     r11,0(r11)
+	rlwinm	r0,r0,2,0,31		/* fn_addr = fn_tbl[r0] */
+	add	r11,r11,r0
+	lwz	r11,0(r11)
 
-	li      r20,0xd00-4             /* Get stack pointer */
-	lwz     r12,0(r20)
-	subi    r12,r12,12              /* Adjust stack pointer */
-	li      r0,0xc00+_end_back-SystemCall
-	cmplw   0, r0, r12              /* Check stack overflow */
-	bgt     1f
-	stw     r12,0(r20)
+	li	r20,0xd00-4		/* Get stack pointer */
+	lwz	r12,0(r20)
+	subi	r12,r12,12		/* Adjust stack pointer */
+	li	r0,0xc00+_end_back-SystemCall
+	cmplw	0, r0, r12		/* Check stack overflow */
+	bgt	1f
+	stw	r12,0(r20)
 
-	mflr    r0
-	stw     r0,0(r12)
-	mfspr   r0,SRR0
-	stw     r0,4(r12)
-	mfspr   r0,SRR1
-	stw     r0,8(r12)
+	mflr	r0
+	stw	r0,0(r12)
+	mfspr	r0,SRR0
+	stw	r0,4(r12)
+	mfspr	r0,SRR1
+	stw	r0,8(r12)
 
-	li      r12,0xc00+_back-SystemCall
-	mtlr    r12
-	mtspr   SRR0,r11
+	li	r12,0xc00+_back-SystemCall
+	mtlr	r12
+	mtspr	SRR0,r11
 
-1:      SYNC
+1:	SYNC
 	rfi
 _back:
 
-	mfmsr   r11                     /* Disable interrupts */
-	li      r12,0
-	ori     r12,r12,MSR_EE
-	andc    r11,r11,r12
-	SYNC                            /* Some chip revs need this... */
-	mtmsr   r11
+	mfmsr	r11			/* Disable interrupts */
+	li	r12,0
+	ori	r12,r12,MSR_EE
+	andc	r11,r11,r12
+	SYNC				/* Some chip revs need this... */
+	mtmsr	r11
 	SYNC
 
-	li      r12,0xd00-4             /* restore regs */
-	lwz     r12,0(r12)
+	li	r12,0xd00-4		/* restore regs */
+	lwz	r12,0(r12)
 
-	lwz     r11,0(r12)
-	mtlr    r11
-	lwz     r11,4(r12)
-	mtspr   SRR0,r11
-	lwz     r11,8(r12)
-	mtspr   SRR1,r11
+	lwz	r11,0(r12)
+	mtlr	r11
+	lwz	r11,4(r12)
+	mtspr	SRR0,r11
+	lwz	r11,8(r12)
+	mtspr	SRR1,r11
 
-	addi    r12,r12,12              /* Adjust stack pointer */
-	li      r20,0xd00-4
-	stw     r12,0(r20)
+	addi	r12,r12,12		/* Adjust stack pointer */
+	li	r20,0xd00-4
+	stw	r12,0(r20)
 
 	SYNC
 	rfi
 _end_back:
 
-	STD_EXCEPTION(0xd00, SingleStep, UnknownException)
+	STD_EXCEPTION(0x0a00, Decrementer, timer_interrupt)
+	STD_EXCEPTION(0x0b00, IntervalTimer, UnknownException)
+	STD_EXCEPTION(0x0c00, WatchdogTimer, UnknownException)
 
-	STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
-	STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
+	STD_EXCEPTION(0x0d00, DataTLBError, UnknownException)
+	STD_EXCEPTION(0x0e00, InstructionTLBError, UnknownException)
 
-	STD_EXCEPTION(0x1000, PIT, PITException)
+	CRIT_EXCEPTION(0x0f00, DebugBreakpoint, DebugException )
 
-	STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
-	STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
-	STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
-	STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
-
-	STD_EXCEPTION(0x1500, Reserved5, UnknownException)
-	STD_EXCEPTION(0x1600, Reserved6, UnknownException)
-	STD_EXCEPTION(0x1700, Reserved7, UnknownException)
-	STD_EXCEPTION(0x1800, Reserved8, UnknownException)
-	STD_EXCEPTION(0x1900, Reserved9, UnknownException)
-	STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
-	STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
-
-	STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
-	STD_EXCEPTION(0x1d00, InstructionBreakpoint, UnknownException)
-	STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
-	STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
-
-	CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException )
-
-	.globl  _end_of_vectors
+	.globl	_end_of_vectors
 _end_of_vectors:
 
 
@@ -1077,72 +1060,69 @@ clear_bss:
 	 * r3: dest_addr
 	 * r7: source address, r8: end address, r9: target address
 	 */
-	.globl  trap_init
+	.globl	trap_init
 trap_init:
-	lwz     r7, GOT(_start)
-	lwz     r8, GOT(_end_of_vectors)
+	lwz	r7, GOT(_start)
+	lwz	r8, GOT(_end_of_vectors)
 
 	li	r9, 0x100		/* reset vector always at 0x100 */
 
-	cmplw   0, r7, r8
-	bgelr                           /* return if r7>=r8 - just in case */
+	cmplw	0, r7, r8
+	bgelr				/* return if r7>=r8 - just in case */
 
-	mflr    r4                      /* save link register           */
+	mflr	r4			/* save link register		*/
 1:
-	lwz     r0, 0(r7)
-	stw     r0, 0(r9)
-	addi    r7, r7, 4
-	addi    r9, r9, 4
-	cmplw   0, r7, r8
-	bne     1b
+	lwz	r0, 0(r7)
+	stw	r0, 0(r9)
+	addi	r7, r7, 4
+	addi	r9, r9, 4
+	cmplw	0, r7, r8
+	bne	1b
 
 	/*
 	 * relocate `hdlr' and `int_return' entries
 	 */
-	li      r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
-	li      r8, Alignment - _start + EXC_OFF_SYS_RESET
+	li	r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
+	bl	trap_reloc
+	li	r7, .L_DataStorage - _start + EXC_OFF_SYS_RESET
+	bl	trap_reloc
+	li	r7, .L_InstStorage - _start + EXC_OFF_SYS_RESET
+	bl	trap_reloc
+	li	r7, .L_ExtInterrupt - _start + EXC_OFF_SYS_RESET
+	bl	trap_reloc
+	li	r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
+	bl	trap_reloc
+	li	r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
+	bl	trap_reloc
+	li	r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
+	bl	trap_reloc
+	li	r7, .L_Decrementer - _start + EXC_OFF_SYS_RESET
+	bl	trap_reloc
+	li	r7, .L_IntervalTimer - _start + EXC_OFF_SYS_RESET
+	li	r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
 2:
-	bl      trap_reloc
-	addi    r7, r7, 0x100           /* next exception vector        */
-	cmplw   0, r7, r8
-	blt     2b
+	bl	trap_reloc
+	addi	r7, r7, 0x100		/* next exception vector	*/
+	cmplw	0, r7, r8
+	blt	2b
 
-	li      r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
-	bl      trap_reloc
+	lis	r7,0x0
+	mtspr	IVPR, r7
 
-	li      r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
-	bl      trap_reloc
-
-	li      r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
-	li      r8, SystemCall - _start + EXC_OFF_SYS_RESET
-3:
-	bl      trap_reloc
-	addi    r7, r7, 0x100           /* next exception vector        */
-	cmplw   0, r7, r8
-	blt     3b
-
-	li      r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
-	li      r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
-4:
-	bl      trap_reloc
-	addi    r7, r7, 0x100           /* next exception vector        */
-	cmplw   0, r7, r8
-	blt     4b
-
-	mtlr    r4                      /* restore link register        */
+	mtlr	r4			/* restore link register	*/
 	blr
 
 	/*
 	 * Function: relocate entries for one exception vector
 	 */
 trap_reloc:
-	lwz     r0, 0(r7)               /* hdlr ...                     */
-	add     r0, r0, r3              /*  ... += dest_addr            */
-	stw     r0, 0(r7)
+	lwz	r0, 0(r7)		/* hdlr ...			*/
+	add	r0, r0, r3		/*  ... += dest_addr		*/
+	stw	r0, 0(r7)
 
-	lwz     r0, 4(r7)               /* int_return ...               */
-	add     r0, r0, r3              /*  ... += dest_addr            */
-	stw     r0, 4(r7)
+	lwz	r0, 4(r7)		/* int_return ...		*/
+	add	r0, r0, r3		/*  ... += dest_addr		*/
+	stw	r0, 4(r7)
 
 	blr
 
@@ -1158,7 +1138,7 @@ unlock_ram_in_cache:
 	dcbi	r0, r3
 	addi	r3, r3, 32
 	bdnz	1b
-	sync			/* Wait for all icbi to complete on bus	*/
+	sync			/* Wait for all icbi to complete on bus */
 	isync
 	blr
 #endif

cpu/mpc8xx/lcd.c

@@ -46,12 +46,13 @@
 /************************************************************************/
 /* ** CONFIG STUFF -- should be moved to board config file		*/
 /************************************************************************/
-#define CONFIG_LCD_LOGO
-#define LCD_INFO		/* Display Logo, (C) and system info	*/
+#ifndef CONFIG_LCD_INFO
+#define CONFIG_LCD_INFO		/* Display Logo, (C) and system info	*/
+#endif
 
 #if defined(CONFIG_V37) || defined(CONFIG_EDT32F10)
 #undef CONFIG_LCD_LOGO
-#undef LCD_INFO
+#undef CONFIG_LCD_INFO
 #endif
 
 /*----------------------------------------------------------------------*/
@@ -155,7 +156,7 @@ vidinfo_t panel_info = {
     3, 0, 0, 1, 1, 15, 4, 0, 3
 		/* wbl, vpw, lcdac, wbf */
 };
-#define LCD_INFO_BELOW_LOGO
+#define CONFIG_LCD_INFO_BELOW_LOGO
 #endif /* CONFIG_SHARP_LQ057Q3DC02 */
 /*----------------------------------------------------------------------*/
 
@@ -179,7 +180,7 @@ vidinfo_t panel_info = {
     3, 0, 0, 1, 1, 248, 4, 0, 35
 		/* wbl, vpw, lcdac, wbf */
 };
-#define LCD_INFO_BELOW_LOGO
+#define CONFIG_LCD_INFO_BELOW_LOGO
 #endif /* CONFIG_SHARP_LQ065T9DR51U */
 
 #ifdef CONFIG_SHARP_LQ084V1DG21

cpu/ppc4xx/440gx_enet.c

@@ -1216,6 +1216,7 @@ int ppc_440x_eth_initialize (bd_t * bis)
 				"Cannot allocate eth_device %d\n", eth_num);
 			return (-1);
 		}
+		memset(dev, 0, sizeof(*dev));
 
 		/* Allocate our private use data */
 		hw = (EMAC_440GX_HW_PST) malloc (sizeof (*hw));
@@ -1226,6 +1227,7 @@ int ppc_440x_eth_initialize (bd_t * bis)
 			free (dev);
 			return (-1);
 		}
+		memset(hw, 0, sizeof(*hw));
 
 		switch (eth_num) {
 		default:		/* fall through */

drivers/Makefile

@@ -47,7 +47,8 @@ OBJS	= 3c589.o 5701rls.o ali512x.o \
 	  status_led.o sym53c8xx.o \
 	  ti_pci1410a.o tigon3.o \
 	  usbdcore.o usbdcore_ep0.o usbdcore_omap1510.o usbtty.o \
-	  videomodes.o w83c553f.o
+	  videomodes.o w83c553f.o \
+	  ks8695eth.o
 
 all:	$(LIB)
 

drivers/cfi_flash.c

@@ -189,6 +189,7 @@ static ulong flash_get_size (ulong base, int banknum);
 static int flash_write_cfiword (flash_info_t * info, ulong dest, cfiword_t cword);
 static int flash_full_status_check (flash_info_t * info, flash_sect_t sector,
 				    ulong tout, char *prompt);
+static flash_info_t *flash_get_info(ulong base);
 #ifdef CFG_FLASH_USE_BUFFER_WRITE
 static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp, int len);
 #endif
@@ -341,8 +342,8 @@ unsigned long flash_init (void)
 #if (CFG_MONITOR_BASE >= CFG_FLASH_BASE)
 	flash_protect (FLAG_PROTECT_SET,
 		       CFG_MONITOR_BASE,
-		       CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
-		       &flash_info[0]);
+		       CFG_MONITOR_BASE + monitor_flash_len  - 1,
+		       flash_get_info(CFG_MONITOR_BASE));
 #endif
 
 	/* Environment protection ON by default */
@@ -350,7 +351,7 @@ unsigned long flash_init (void)
 	flash_protect (FLAG_PROTECT_SET,
 		       CFG_ENV_ADDR,
 		       CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
-		       &flash_info[0]);
+		       flash_get_info(CFG_ENV_ADDR));
 #endif
 
 	/* Redundant environment protection ON by default */
@@ -358,11 +359,28 @@ unsigned long flash_init (void)
 	flash_protect (FLAG_PROTECT_SET,
 		       CFG_ENV_ADDR_REDUND,
 		       CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1,
-		       &flash_info[0]);
+		       flash_get_info(CFG_ENV_ADDR_REDUND));
 #endif
 	return (size);
 }
 
+/*-----------------------------------------------------------------------
+ */
+static flash_info_t *flash_get_info(ulong base)
+{
+	int i;
+	flash_info_t * info;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) {
+		info = & flash_info[i];
+		if (info->size && info->start[0] <= base &&
+		    base <= info->start[0] + info->size - 1)
+			break;
+	}
+
+	return i == CFG_MAX_FLASH_BANKS ? 0 : info;
+}
+
 /*-----------------------------------------------------------------------
  */
 int flash_erase (flash_info_t * info, int s_first, int s_last)

drivers/ks8695eth.c

@@ -0,0 +1,238 @@
+/*
+ * ks8695eth.c -- KS8695 ethernet driver
+ *
+ * (C) Copyright 2004-2005, Greg Ungerer <greg.ungerer@opengear.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifdef	CONFIG_DRIVER_KS8695ETH
+
+/****************************************************************************/
+
+#include <common.h>
+#include <malloc.h>
+#include <net.h>
+#include <asm/io.h>
+#include <asm/arch/platform.h>
+
+/****************************************************************************/
+
+/*
+ * Hardware register access to the KS8695 LAN ethernet port
+ * (well, it is the 4 port switch really).
+ */
+#define	ks8695_read(a)    *((volatile unsigned long *) (KS8695_IO_BASE + (a)))
+#define	ks8695_write(a,v) *((volatile unsigned long *) (KS8695_IO_BASE + (a))) = (v)
+
+/****************************************************************************/
+
+/*
+ * Define the descriptor in-memory data structures.
+ */
+struct ks8695_txdesc {
+	uint32_t	owner;
+	uint32_t	ctrl;
+	uint32_t	addr;
+	uint32_t	next;
+};
+
+struct ks8695_rxdesc {
+	uint32_t	status;
+	uint32_t	ctrl;
+	uint32_t	addr;
+	uint32_t	next;
+};
+
+/****************************************************************************/
+
+/*
+ * Allocate local data structures to use for receiving and sending
+ * packets. Just to keep it all nice and simple.
+ */
+
+#define	TXDESCS		4
+#define	RXDESCS		4
+#define	BUFSIZE		2048
+
+volatile struct ks8695_txdesc ks8695_tx[TXDESCS] __attribute__((aligned(256)));
+volatile struct ks8695_rxdesc ks8695_rx[RXDESCS] __attribute__((aligned(256)));
+volatile uint8_t ks8695_bufs[BUFSIZE*(TXDESCS+RXDESCS)] __attribute__((aligned(2048)));;
+
+/****************************************************************************/
+
+/*
+ *	Ideally we want to use the MAC address stored in flash.
+ *	But we do some sanity checks in case they are not present
+ *	first.
+ */
+unsigned char eth_mac[] = {
+	0x00, 0x13, 0xc6, 0x00, 0x00, 0x00
+};
+
+void ks8695_getmac(void)
+{
+	unsigned char *fp;
+	int i;
+
+	/* Check if flash MAC is valid */
+	fp = (unsigned char *) 0x0201c000;
+	for (i = 0; (i < 6); i++) {
+		if ((fp[i] != 0) && (fp[i] != 0xff))
+			break;
+	}
+
+	/* If we found a valid looking MAC address then use it */
+	if (i < 6)
+		memcpy(&eth_mac[0], fp, 6);
+}
+
+/****************************************************************************/
+
+void eth_reset(bd_t *bd)
+{
+	int i;
+
+	debug ("%s(%d): eth_reset()\n", __FILE__, __LINE__);
+
+	/* Reset the ethernet engines first */
+	ks8695_write(KS8695_LAN_DMA_TX, 0x80000000);
+	ks8695_write(KS8695_LAN_DMA_RX, 0x80000000);
+
+	ks8695_getmac();
+
+	/* Set MAC address */
+	ks8695_write(KS8695_LAN_MAC_LOW, (eth_mac[5] | (eth_mac[4] << 8) |
+		(eth_mac[3] << 16) | (eth_mac[2] << 24)));
+	ks8695_write(KS8695_LAN_MAC_HIGH, (eth_mac[1] | (eth_mac[0] << 8)));
+
+	/* Turn the 4 port switch on */
+	i = ks8695_read(KS8695_SWITCH_CTRL0);
+	ks8695_write(KS8695_SWITCH_CTRL0, (i | 0x1));
+	/* ks8695_write(KS8695_WAN_CONTROL, 0x3f000066); */
+
+	/* Initialize descriptor rings */
+	for (i = 0; (i < TXDESCS); i++) {
+		ks8695_tx[i].owner = 0;
+		ks8695_tx[i].ctrl = 0;
+		ks8695_tx[i].addr = (uint32_t) &ks8695_bufs[i*BUFSIZE];
+		ks8695_tx[i].next = (uint32_t) &ks8695_tx[i+1];
+	}
+	ks8695_tx[TXDESCS-1].ctrl = 0x02000000;
+	ks8695_tx[TXDESCS-1].next = (uint32_t) &ks8695_tx[0];
+
+	for (i = 0; (i < RXDESCS); i++) {
+		ks8695_rx[i].status = 0x80000000;
+		ks8695_rx[i].ctrl = BUFSIZE - 4;
+		ks8695_rx[i].addr = (uint32_t) &ks8695_bufs[(i+TXDESCS)*BUFSIZE];
+		ks8695_rx[i].next = (uint32_t) &ks8695_rx[i+1];
+	}
+	ks8695_rx[RXDESCS-1].ctrl |= 0x00080000;
+	ks8695_rx[RXDESCS-1].next = (uint32_t) &ks8695_rx[0];
+
+	/* The KS8695 is pretty slow reseting the ethernets... */
+	udelay(2000000);
+
+	/* Enable the ethernet engine */
+	ks8695_write(KS8695_LAN_TX_LIST, (uint32_t) &ks8695_tx[0]);
+	ks8695_write(KS8695_LAN_RX_LIST, (uint32_t) &ks8695_rx[0]);
+	ks8695_write(KS8695_LAN_DMA_TX, 0x3);
+	ks8695_write(KS8695_LAN_DMA_RX, 0x71);
+	ks8695_write(KS8695_LAN_DMA_RX_START, 0x1);
+
+	printf("KS8695 ETHERNET: ");
+	for (i = 0; (i < 5); i++) {
+		bd->bi_enetaddr[i] = eth_mac[i];
+		printf("%02x:", eth_mac[i]);
+	}
+	bd->bi_enetaddr[i] = eth_mac[i];
+	printf("%02x\n", eth_mac[i]);
+}
+
+/****************************************************************************/
+
+int eth_init(bd_t *bd)
+{
+	debug ("%s(%d): eth_init()\n", __FILE__, __LINE__);
+
+	eth_reset(bd);
+	return 0;
+}
+
+/****************************************************************************/
+
+void eth_halt(void)
+{
+	debug ("%s(%d): eth_halt()\n", __FILE__, __LINE__);
+
+	/* Reset the ethernet engines */
+	ks8695_write(KS8695_LAN_DMA_TX, 0x80000000);
+	ks8695_write(KS8695_LAN_DMA_RX, 0x80000000);
+}
+
+/****************************************************************************/
+
+int eth_rx(void)
+{
+	volatile struct ks8695_rxdesc *dp;
+	int i, len = 0;
+
+	debug ("%s(%d): eth_rx()\n", __FILE__, __LINE__);
+
+	for (i = 0; (i < RXDESCS); i++) {
+		dp= &ks8695_rx[i];
+		if ((dp->status & 0x80000000) == 0) {
+			len = (dp->status & 0x7ff) - 4;
+			NetReceive((void *) dp->addr, len);
+			dp->status = 0x80000000;
+			ks8695_write(KS8695_LAN_DMA_RX_START, 0x1);
+			break;
+		}
+	}
+
+	return len;
+}
+
+/****************************************************************************/
+
+int eth_send(volatile void *packet, int len)
+{
+	volatile struct ks8695_txdesc *dp;
+	static int next = 0;
+
+	debug ("%s(%d): eth_send(packet=%x,len=%d)\n", __FILE__, __LINE__,
+		packet, len);
+
+	dp = &ks8695_tx[next];
+	memcpy((void *) dp->addr, packet, len);
+
+	if (len < 64) {
+		memset(dp->addr+len, 0, 64-len);
+		len = 64;
+	}
+
+	dp->ctrl = len | 0xe0000000;
+	dp->owner = 0x80000000;
+
+	ks8695_write(KS8695_LAN_DMA_TX, 0x3);
+	ks8695_write(KS8695_LAN_DMA_TX_START, 0x1);
+
+	if (++next >= TXDESCS)
+		next = 0;
+
+	return len;
+}
+
+#endif	/* CONFIG_DRIVER_KS8695ETH */

examples/Makefile

@@ -58,7 +58,7 @@ include $(TOPDIR)/config.mk
 SREC	= hello_world.srec
 BIN	= hello_world.bin hello_world
 
-ifeq ($(ARCH),ppc)
+ifeq ($(CPU),mpc8xx)
 SREC	= test_burst.srec
 BIN	= test_burst.bin test_burst
 endif
@@ -101,6 +101,8 @@ LIB	= libstubs.a
 LIBAOBJS=
 ifeq ($(ARCH),ppc)
 LIBAOBJS+= $(ARCH)_longjmp.o $(ARCH)_setjmp.o
+endif
+ifeq ($(CPU),mpc8xx)
 LIBAOBJS+= test_burst_lib.o
 endif
 LIBCOBJS= stubs.o

examples/test_burst.c

@@ -47,12 +47,32 @@
 */
 #define TEST_FLASH_ADDR	0x40100000
 
+/* Define GPIO ports to signal start of burst transfers and errors */
+#ifdef CONFIG_LWMON
+/* Use PD.8 to signal start of burst transfers */
+#define GPIO1_DAT	(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat)
+#define GPIO1_BIT	0x0080
+/* Configure PD.8 as general purpose output */
+#define GPIO1_INIT \
+	((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pdpar &= ~GPIO1_BIT; \
+	((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddir |=  GPIO1_BIT;
+/* Use PD.9 to signal error */
+#define GPIO2_DAT	(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat)
+#define GPIO2_BIT	0x0040
+/* Configure PD.9 as general purpose output */
+#define GPIO2_INIT \
+	((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pdpar &= ~GPIO2_BIT; \
+	((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddir |=  GPIO2_BIT;
+#endif /* CONFIG_LWMON */
+
+
 static void test_prepare (void);
 static int test_burst_start (unsigned long size, unsigned long pattern);
 static void test_map_8M (unsigned long paddr, unsigned long vaddr, int cached);
 static int test_mmu_is_on(void);
 static void test_desc(unsigned long size);
 static void test_error(char * step, volatile void * addr, unsigned long val, unsigned long pattern);
+static void signal_init(void);
 static void signal_start(void);
 static void signal_error(void);
 static void test_usage(void);
@@ -68,10 +88,11 @@ static unsigned long test_pattern [] = {
 int test_burst (int argc, char *argv[])
 {
 	unsigned long size = CACHE_LINE_SIZE;
-	int res;
-	int i;
+	unsigned int pass = 0;
+	int res = 0;
+	int i, j;
 
-	if (argc == 2) {
+	if (argc == 3) {
 		char * d;
 		for (size = 0, d = argv[1]; *d >= '0' && *d <= '9'; d++) {
 			size *= 10;
@@ -81,7 +102,15 @@ int test_burst (int argc, char *argv[])
 			test_usage();
 			return 1;
 		}
-	} else if (argc > 2) {
+		for (d = argv[2]; *d >= '0' && *d <= '9'; d++) {
+			pass *= 10;
+			pass += *d - '0';
+		}
+		if (*d) {
+			test_usage();
+			return 1;
+		}
+	} else if (argc > 3) {
 		test_usage();
 		return 1;
 	}
@@ -95,11 +124,19 @@ int test_burst (int argc, char *argv[])
 
 	test_desc(size);
 
-	for (i = 0; i < sizeof(test_pattern) / sizeof(test_pattern[0]); i++) {
-		res = test_burst_start(size, test_pattern[i]);
-		if (res != 0) {
-			goto Done;
+	for (j = 0; !pass || j < pass; j++) {
+		for (i = 0; i < sizeof(test_pattern) / sizeof(test_pattern[0]);
+		     i++) {
+			res = test_burst_start(size, test_pattern[i]);
+			if (res != 0) {
+				goto Done;
+			}
 		}
+
+		printf ("Iteration #%d passed\n", j + 1);
+
+		if (tstc() && 0x03 == getc())
+			break;
 	}
 Done:
 	return res;
@@ -107,8 +144,6 @@ Done:
 
 static void test_prepare (void)
 {
-	volatile immap_t *immr = (immap_t *)  CFG_IMMR;
-
 	printf ("\n");
 
 	caches_init();
@@ -127,9 +162,8 @@ static void test_prepare (void)
 
 	test_map_8M (TEST_FLASH_ADDR & 0xFF800000, TEST_FLASH_ADDR & 0xFF800000, 0);
 
-	/* Configure PD.8 and PD.9 as general purpose output */
-	immr->im_ioport.iop_pdpar &= ~0x00C0;
-	immr->im_ioport.iop_pddir |=  0x00C0;
+	/* Configure GPIO ports */
+	signal_init();
 }
 
 static int test_burst_start (unsigned long size, unsigned long pattern)
@@ -247,29 +281,39 @@ static void test_error(
 		step, addr, val, pattern);
 }
 
+static void signal_init(void)
+{
+#if defined(GPIO1_INIT)
+	GPIO1_INIT;
+#endif
+#if defined(GPIO2_INIT)
+	GPIO2_INIT;
+#endif
+}
+
 static void signal_start(void)
 {
-	volatile immap_t *immr = (immap_t *)  CFG_IMMR;
-
-	if (immr->im_ioport.iop_pddat & 0x0080) {
-		immr->im_ioport.iop_pddat &= ~0x0080;
+#if defined(GPIO1_INIT)
+	if (GPIO1_DAT & GPIO1_BIT) {
+		GPIO1_DAT &= ~GPIO1_BIT;
 	} else {
-		immr->im_ioport.iop_pddat |= 0x0080;
+		GPIO1_DAT |= GPIO1_BIT;
 	}
+#endif
 }
 
 static void signal_error(void)
 {
-	volatile immap_t *immr = (immap_t *)  CFG_IMMR;
-
-	if (immr->im_ioport.iop_pddat & 0x0040) {
-		immr->im_ioport.iop_pddat &= ~0x0040;
+#if defined(GPIO2_INIT)
+	if (GPIO2_DAT & GPIO2_BIT) {
+		GPIO2_DAT &= ~GPIO2_BIT;
 	} else {
-		immr->im_ioport.iop_pddat |= 0x0040;
+		GPIO2_DAT |= GPIO2_BIT;
 	}
+#endif
 }
 
 static void test_usage(void)
 {
-	printf("Usage: go 0x40004 [size]\n");
+	printf("Usage: go 0x40004 [size] [count]\n");
 }

include/asm-arm/arch-ks8695/platform.h

@@ -0,0 +1,306 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307	 USA
+ */
+#ifndef __address_h
+#define __address_h			1
+
+#define KS8695_SDRAM_START	    0x00000000
+#define KS8695_SDRAM_SIZE	    0x01000000
+#define KS8695_MEM_SIZE		    KS8695_SDRAM_SIZE
+#define KS8695_MEM_START	    KS8695_SDRAM_START
+
+#define KS8695_PCMCIA_IO_BASE	    0x03800000
+#define KS8695_PCMCIA_IO_SIZE	    0x00040000
+
+#define KS8695_IO_BASE		    0x03FF0000
+#define KS8695_IO_SIZE		    0x00010000
+
+#define KS8695_SYSTEN_CONFIG	    0x00
+#define KS8695_SYSTEN_BUS_CLOCK	    0x04
+
+#define KS8695_FLASH_START	    0x02800000
+#define KS8695_FLASH_SIZE	    0x00400000
+
+/*i/o control registers offset difinitions*/
+#define KS8695_IO_CTRL0		    0x4000
+#define KS8695_IO_CTRL1		    0x4004
+#define KS8695_IO_CTRL2		    0x4008
+#define KS8695_IO_CTRL3		    0x400C
+
+/*memory control registers offset difinitions*/
+#define KS8695_MEM_CTRL0	    0x4010
+#define KS8695_MEM_CTRL1	    0x4014
+#define KS8695_MEM_CTRL2	    0x4018
+#define KS8695_MEM_CTRL3	    0x401C
+#define KS8695_MEM_GENERAL	    0x4020
+#define KS8695_SDRAM_CTRL0	    0x4030
+#define KS8695_SDRAM_CTRL1	    0x4034
+#define KS8695_SDRAM_GENERAL	    0x4038
+#define KS8695_SDRAM_BUFFER	    0x403C
+#define KS8695_SDRAM_REFRESH	    0x4040
+
+/*WAN control registers offset difinitions*/
+#define KS8695_WAN_DMA_TX	    0x6000
+#define KS8695_WAN_DMA_RX	    0x6004
+#define KS8695_WAN_DMA_TX_START	    0x6008
+#define KS8695_WAN_DMA_RX_START	    0x600C
+#define KS8695_WAN_TX_LIST	    0x6010
+#define KS8695_WAN_RX_LIST	    0x6014
+#define KS8695_WAN_MAC_LOW	    0x6018
+#define KS8695_WAN_MAC_HIGH	    0x601C
+#define KS8695_WAN_MAC_ELOW	    0x6080
+#define KS8695_WAN_MAC_EHIGH	    0x6084
+
+/*LAN control registers offset difinitions*/
+#define KS8695_LAN_DMA_TX	    0x8000
+#define KS8695_LAN_DMA_RX	    0x8004
+#define KS8695_LAN_DMA_TX_START	    0x8008
+#define KS8695_LAN_DMA_RX_START	    0x800C
+#define KS8695_LAN_TX_LIST	    0x8010
+#define KS8695_LAN_RX_LIST	    0x8014
+#define KS8695_LAN_MAC_LOW	    0x8018
+#define KS8695_LAN_MAC_HIGH	    0x801C
+#define KS8695_LAN_MAC_ELOW	    0X8080
+#define KS8695_LAN_MAC_EHIGH	    0X8084
+
+/*HPNA control registers offset difinitions*/
+#define KS8695_HPNA_DMA_TX	    0xA000
+#define KS8695_HPNA_DMA_RX	    0xA004
+#define KS8695_HPNA_DMA_TX_START    0xA008
+#define KS8695_HPNA_DMA_RX_START    0xA00C
+#define KS8695_HPNA_TX_LIST	    0xA010
+#define KS8695_HPNA_RX_LIST	    0xA014
+#define KS8695_HPNA_MAC_LOW	    0xA018
+#define KS8695_HPNA_MAC_HIGH	    0xA01C
+#define KS8695_HPNA_MAC_ELOW	    0xA080
+#define KS8695_HPNA_MAC_EHIGH	    0xA084
+
+/*UART control registers offset difinitions*/
+#define KS8695_UART_RX_BUFFER	    0xE000
+#define KS8695_UART_TX_HOLDING	    0xE004
+
+#define KS8695_UART_FIFO_CTRL	    0xE008
+#define KS8695_UART_FIFO_TRIG01	    0x00
+#define KS8695_UART_FIFO_TRIG04	    0x80
+#define KS8695_UART_FIFO_TXRST	    0x03
+#define KS8695_UART_FIFO_RXRST	    0x02
+#define KS8695_UART_FIFO_FEN	    0x01
+
+#define KS8695_UART_LINE_CTRL	    0xE00C
+#define KS8695_UART_LINEC_BRK	    0x40
+#define KS8695_UART_LINEC_EPS	    0x10
+#define KS8695_UART_LINEC_PEN	    0x08
+#define KS8695_UART_LINEC_STP2	    0x04
+#define KS8695_UART_LINEC_WLEN8	    0x03
+#define KS8695_UART_LINEC_WLEN7	    0x02
+#define KS8695_UART_LINEC_WLEN6	    0x01
+#define KS8695_UART_LINEC_WLEN5	    0x00
+
+#define KS8695_UART_MODEM_CTRL	    0xE010
+#define KS8695_UART_MODEMC_RTS	    0x02
+#define KS8695_UART_MODEMC_DTR	    0x01
+
+#define KS8695_UART_LINE_STATUS	    0xE014
+#define KS8695_UART_LINES_TXFE	    0x20
+#define KS8695_UART_LINES_BE	    0x10
+#define KS8695_UART_LINES_FE	    0x08
+#define KS8695_UART_LINES_PE	    0x04
+#define KS8695_UART_LINES_OE	    0x02
+#define KS8695_UART_LINES_RXFE	    0x01
+#define KS8695_UART_LINES_ANY	    (KS8695_UART_LINES_OE|KS8695_UART_LINES_BE|KS8695_UART_LINES_PE|KS8695_UART_LINES_FE)
+
+#define KS8695_UART_MODEM_STATUS    0xE018
+#define KS8695_UART_MODEM_DCD	    0x80
+#define KS8695_UART_MODEM_DSR	    0x20
+#define KS8695_UART_MODEM_CTS	    0x10
+#define KS8695_UART_MODEM_DDCD	    0x08
+#define KS8695_UART_MODEM_DDSR	    0x02
+#define KS8695_UART_MODEM_DCTS	    0x01
+#define UART8695_MODEM_ANY	    0xFF
+
+#define KS8695_UART_DIVISOR	    0xE01C
+#define KS8695_UART_STATUS	    0xE020
+
+/*Interrupt controlller registers offset difinitions*/
+#define KS8695_INT_CONTL	    0xE200
+#define KS8695_INT_ENABLE	    0xE204
+#define KS8695_INT_ENABLE_MODEM	    0x0800
+#define KS8695_INT_ENABLE_ERR	    0x0400
+#define KS8695_INT_ENABLE_RX	    0x0200
+#define KS8695_INT_ENABLE_TX	    0x0100
+
+#define KS8695_INT_STATUS	    0xE208
+#define KS8695_INT_WAN_PRIORITY	    0xE20C
+#define KS8695_INT_HPNA_PRIORITY    0xE210
+#define KS8695_INT_LAN_PRIORITY	    0xE214
+#define KS8695_INT_TIMER_PRIORITY   0xE218
+#define KS8695_INT_UART_PRIORITY    0xE21C
+#define KS8695_INT_EXT_PRIORITY	    0xE220
+#define KS8695_INT_CHAN_PRIORITY    0xE224
+#define KS8695_INT_BUSERROR_PRO	    0xE228
+#define KS8695_INT_MASK_STATUS	    0xE22C
+#define KS8695_FIQ_PEND_PRIORITY    0xE230
+#define KS8695_IRQ_PEND_PRIORITY    0xE234
+
+/*timer registers offset difinitions*/
+#define KS8695_TIMER_CTRL	    0xE400
+#define KS8695_TIMER1		    0xE404
+#define KS8695_TIMER0		    0xE408
+#define KS8695_TIMER1_PCOUNT	    0xE40C
+#define KS8695_TIMER0_PCOUNT	    0xE410
+
+/*GPIO registers offset difinitions*/
+#define KS8695_GPIO_MODE	    0xE600
+#define KS8695_GPIO_CTRL	    0xE604
+#define KS8695_GPIO_DATA	    0xE608
+
+/*SWITCH registers offset difinitions*/
+#define KS8695_SWITCH_CTRL0	    0xE800
+#define KS8695_SWITCH_CTRL1	    0xE804
+#define KS8695_SWITCH_PORT1	    0xE808
+#define KS8695_SWITCH_PORT2	    0xE80C
+#define KS8695_SWITCH_PORT3	    0xE810
+#define KS8695_SWITCH_PORT4	    0xE814
+#define KS8695_SWITCH_PORT5	    0xE818
+#define KS8695_SWITCH_AUTO0	    0xE81C
+#define KS8695_SWITCH_AUTO1	    0xE820
+#define KS8695_SWITCH_LUE_CTRL	    0xE824
+#define KS8695_SWITCH_LUE_HIGH	    0xE828
+#define KS8695_SWITCH_LUE_LOW	    0xE82C
+#define KS8695_SWITCH_ADVANCED	    0xE830
+
+#define KS8695_SWITCH_LPPM12	    0xE874
+#define KS8695_SWITCH_LPPM34	    0xE878
+
+/*host communication registers difinitions*/
+#define KS8695_DSCP_HIGH	    0xE834
+#define KS8695_DSCP_LOW		    0xE838
+#define KS8695_SWITCH_MAC_HIGH	    0xE83C
+#define KS8695_SWITCH_MAC_LOW	    0xE840
+
+/*miscellaneours registers difinitions*/
+#define KS8695_MANAGE_COUNTER	    0xE844
+#define KS8695_MANAGE_DATA	    0xE848
+#define KS8695_LAN12_POWERMAGR	    0xE84C
+#define KS8695_LAN34_POWERMAGR	    0xE850
+
+#define KS8695_DEVICE_ID	    0xEA00
+#define KS8695_REVISION_ID	    0xEA04
+
+#define KS8695_MISC_CONTROL	    0xEA08
+#define KS8695_WAN_CONTROL	    0xEA0C
+#define KS8695_WAN_POWERMAGR	    0xEA10
+#define KS8695_WAN_PHY_CONTROL	    0xEA14
+#define KS8695_WAN_PHY_STATUS	    0xEA18
+
+/* bus clock definitions*/
+#define KS8695_BUS_CLOCK_125MHZ	    0x0
+#define KS8695_BUS_CLOCK_100MHZ	    0x1
+#define KS8695_BUS_CLOCK_62MHZ	    0x2
+#define KS8695_BUS_CLOCK_50MHZ	    0x3
+#define KS8695_BUS_CLOCK_41MHZ	    0x4
+#define KS8695_BUS_CLOCK_33MHZ	    0x5
+#define KS8695_BUS_CLOCK_31MHZ	    0x6
+#define KS8695_BUS_CLOCK_25MHZ	    0x7
+
+/* -------------------------------------------------------------------------------
+ *  definations for IRQ
+ * -------------------------------------------------------------------------------*/
+
+#define KS8695_INT_EXT_INT0		       2
+#define KS8695_INT_EXT_INT1		       3
+#define KS8695_INT_EXT_INT2		       4
+#define KS8695_INT_EXT_INT3		       5
+#define KS8695_INT_TIMERINT0		       6
+#define KS8695_INT_TIMERINT1		       7
+#define KS8695_INT_UART_TX		       8
+#define KS8695_INT_UART_RX		       9
+#define KS8695_INT_UART_LINE_ERR	       10
+#define KS8695_INT_UART_MODEMS		       11
+#define KS8695_INT_LAN_STOP_RX		       12
+#define KS8695_INT_LAN_STOP_TX		       13
+#define KS8695_INT_LAN_BUF_RX_STATUS	       14
+#define KS8695_INT_LAN_BUF_TX_STATUS	       15
+#define KS8695_INT_LAN_RX_STATUS	       16
+#define KS8695_INT_LAN_TX_STATUS	       17
+#define KS8695_INT_HPAN_STOP_RX		       18
+#define KS8695_INT_HPNA_STOP_TX		       19
+#define KS8695_INT_HPNA_BUF_RX_STATUS	       20
+#define KS8695_INT_HPNA_BUF_TX_STATUS	       21
+#define KS8695_INT_HPNA_RX_STATUS	       22
+#define KS8695_INT_HPNA_TX_STATUS	       23
+#define KS8695_INT_BUS_ERROR		       24
+#define KS8695_INT_WAN_STOP_RX		       25
+#define KS8695_INT_WAN_STOP_TX		       26
+#define KS8695_INT_WAN_BUF_RX_STATUS	       27
+#define KS8695_INT_WAN_BUF_TX_STATUS	       28
+#define KS8695_INT_WAN_RX_STATUS	       29
+#define KS8695_INT_WAN_TX_STATUS	       30
+
+#define KS8695_INT_UART			       KS8695_INT_UART_TX
+
+/* -------------------------------------------------------------------------------
+ *  Interrupt bit positions
+ *
+ * -------------------------------------------------------------------------------
+ */
+
+#define KS8695_INTMASK_EXT_INT0		       ( 1 << KS8695_INT_EXT_INT0 )
+#define KS8695_INTMASK_EXT_INT1		       ( 1 << KS8695_INT_EXT_INT1 )
+#define KS8695_INTMASK_EXT_INT2		       ( 1 << KS8695_INT_EXT_INT2 )
+#define KS8695_INTMASK_EXT_INT3		       ( 1 << KS8695_INT_EXT_INT3 )
+#define KS8695_INTMASK_TIMERINT0	       ( 1 << KS8695_INT_TIMERINT0 )
+#define KS8695_INTMASK_TIMERINT1	       ( 1 << KS8695_INT_TIMERINT1 )
+#define KS8695_INTMASK_UART_TX		       ( 1 << KS8695_INT_UART_TX  )
+#define KS8695_INTMASK_UART_RX		       ( 1 << KS8695_INT_UART_RX  )
+#define KS8695_INTMASK_UART_LINE_ERR	       ( 1 << KS8695_INT_UART_LINE_ERR )
+#define KS8695_INTMASK_UART_MODEMS	       ( 1 << KS8695_INT_UART_MODEMS )
+#define KS8695_INTMASK_LAN_STOP_RX	       ( 1 << KS8695_INT_LAN_STOP_RX )
+#define KS8695_INTMASK_LAN_STOP_TX	       ( 1 << KS8695_INT_LAN_STOP_TX )
+#define KS8695_INTMASK_LAN_BUF_RX_STATUS       ( 1 << KS8695_INT_LAN_BUF_RX_STATUS )
+#define KS8695_INTMASK_LAN_BUF_TX_STATUS       ( 1 << KS8695_INT_LAN_BUF_TX_STATUS )
+#define KS8695_INTMASK_LAN_RX_STATUS	       ( 1 << KS8695_INT_LAN_RX_STATUS )
+#define KS8695_INTMASK_LAN_TX_STATUS	       ( 1 << KS8695_INT_LAN_RX_STATUS )
+#define KS8695_INTMASK_HPAN_STOP_RX	       ( 1 << KS8695_INT_HPAN_STOP_RX )
+#define KS8695_INTMASK_HPNA_STOP_TX	       ( 1 << KS8695_INT_HPNA_STOP_TX )
+#define KS8695_INTMASK_HPNA_BUF_RX_STATUS      ( 1 << KS8695_INT_HPNA_BUF_RX_STATUS )
+#define KS8695_INTMAKS_HPNA_BUF_TX_STATUS      ( 1 << KS8695_INT_HPNA_BUF_TX_STATUS
+#define KS8695_INTMASK_HPNA_RX_STATUS	       ( 1 << KS8695_INT_HPNA_RX_STATUS )
+#define KS8695_INTMASK_HPNA_TX_STATUS	       ( 1 << KS8695_INT_HPNA_TX_STATUS )
+#define KS8695_INTMASK_BUS_ERROR	       ( 1 << KS8695_INT_BUS_ERROR )
+#define KS8695_INTMASK_WAN_STOP_RX	       ( 1 << KS8695_INT_WAN_STOP_RX )
+#define KS8695_INTMASK_WAN_STOP_TX	       ( 1 << KS8695_INT_WAN_STOP_TX )
+#define KS8695_INTMASK_WAN_BUF_RX_STATUS       ( 1 << KS8695_INT_WAN_BUF_RX_STATUS )
+#define KS8695_INTMASK_WAN_BUF_TX_STATUS       ( 1 << KS8695_INT_WAN_BUF_TX_STATUS )
+#define KS8695_INTMASK_WAN_RX_STATUS	       ( 1 << KS8695_INT_WAN_RX_STATUS )
+#define KS8695_INTMASK_WAN_TX_STATUS	       ( 1 << KS8695_INT_WAN_TX_STATUS )
+
+#define KS8695_SC_VALID_INT		       0xFFFFFFFF
+#define MAXIRQNUM			       31
+
+/*
+ *  Timer definitions
+ *
+ *  Use timer 1 & 2
+ *  (both run at 25MHz).
+ *
+ */
+#define TICKS_PER_uSEC			25
+#define mSEC_1				1000
+#define mSEC_10				(mSEC_1 * 10)
+
+#endif
+
+/*	END */

include/asm-ppc/immap_85xx.h

@@ -741,6 +741,8 @@ typedef struct ccsr_pic {
 	uint	frr;		/* 0x41000 - Feature Reporting Register */
 	char	res10[28];
 	uint	gcr;		/* 0x41020 - Global Configuration Register */
+#define MPC85xx_PICGCR_RST   0x80000000
+#define MPC85xx_PICGCR_M     0x20000000
 	char	res11[92];
 	uint	vir;		/* 0x41080 - Vendor Identification Register */
 	char	res12[12];

include/configs/Alaska8220.h

@@ -48,38 +48,45 @@
 /*
  * Serial console configuration
  */
-#define CONFIG_PSC_CONSOLE	1	/* console is on PSC */
+
+/* Define this for PSC console
+#define CONFIG_PSC_CONSOLE	1
+*/
+
 #define CONFIG_EXTUART_CONSOLE	1
 
 #ifdef CONFIG_EXTUART_CONSOLE
+#   define CONFIG_CONS_INDEX	1
+#   define CFG_NS16550_SERIAL
 #   define CFG_NS16550
 #   define CFG_NS16550_REG_SIZE 1
 #   define CFG_NS16550_COM1	(CFG_CPLD_BASE + 0x1008)
+#   define CFG_NS16550_CLK	18432000
 #endif
 
 #define CONFIG_BAUDRATE		115200	    /* ... at 115200 bps */
 
 #define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
-#define	CONFIG_TIMESTAMP			/* Print image info with timestamp */
+#define CONFIG_TIMESTAMP			/* Print image info with timestamp */
 
 /*
  * Supported commands
  */
-#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL  | \
-				CFG_CMD_BOOTD   | \
-				CFG_CMD_CACHE   | \
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_BOOTD	| \
+				CFG_CMD_CACHE	| \
 				CFG_CMD_DHCP	| \
-				CFG_CMD_DIAG    | \
-				CFG_CMD_EEPROM  | \
-				CFG_CMD_ELF     | \
-				CFG_CMD_I2C     | \
-				CFG_CMD_NET     | \
+				CFG_CMD_DIAG	| \
+				CFG_CMD_EEPROM	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_NET	| \
 				CFG_CMD_NFS	| \
-				CFG_CMD_PING    | \
 				CFG_CMD_PCI	| \
+				CFG_CMD_PING	| \
 				CFG_CMD_REGINFO | \
-				CFG_CMD_SDRAM   | \
+				CFG_CMD_SDRAM	| \
 				CFG_CMD_SNTP	)
 
 #define CONFIG_NET_MULTI
@@ -260,10 +267,17 @@
 #define CFG_BOOTMAPSZ		(8 << 20)   /* Initial Memory map for Linux */
 
 /* SDRAM configuration */
-#define CFG_SDRAM_TOTAL_BANKS           2
-#define CFG_SDRAM_SPD_I2C_ADDR          0x51            /* 7bit */
-#define CFG_SDRAM_SPD_SIZE              0x40
-#define CFG_SDRAM_CAS_LATENCY           4               /* (CL=2)x2 */
+#define CFG_SDRAM_TOTAL_BANKS		2
+#define CFG_SDRAM_SPD_I2C_ADDR		0x51		/* 7bit */
+#define CFG_SDRAM_SPD_SIZE		0x40
+#define CFG_SDRAM_CAS_LATENCY		4		/* (CL=2)x2 */
+
+/* SDRAM drive strength register */
+#define CFG_SDRAM_DRIVE_STRENGTH	((DRIVE_STRENGTH_LOW  << SDRAMDS_SBE_SHIFT) | \
+					 (DRIVE_STRENGTH_HIGH << SDRAMDS_SBC_SHIFT) | \
+					 (DRIVE_STRENGTH_LOW  << SDRAMDS_SBA_SHIFT) | \
+					 (DRIVE_STRENGTH_OFF  << SDRAMDS_SBS_SHIFT) | \
+					 (DRIVE_STRENGTH_LOW  << SDRAMDS_SBD_SHIFT))
 
 /*
  * Ethernet configuration

include/configs/CATcenter.h

@@ -110,8 +110,8 @@
 
 #define CONFIG_MII		1	/* MII PHY management		*/
 #ifndef	 CONFIG_EXT_PHY
-#define CONFIG_PHY_ADDR		0	/* EMAC0 PHY address		*/
-#define CONFIG_PHY1_ADDR	1	/* EMAC1 PHY address		*/
+#define CONFIG_PHY_ADDR		1	/* EMAC0 PHY address		*/
+#define CONFIG_PHY1_ADDR	16	/* EMAC1 PHY address		*/
 #else
 #define CONFIG_PHY_ADDR		2	/* PHY address			*/
 #endif

include/configs/IDS8247.h

@@ -0,0 +1,524 @@
+/*
+ * (C) Copyright 2005
+ * Heiko Schocher, DENX Software Engineering, <hs@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC8260		1	/* This is a MPC8260 CPU		*/
+#define CONFIG_MPC8272_FAMILY	1
+#define CONFIG_IDS8247		1
+#define CPU_ID_STR		"MPC8247"
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define	CONFIG_BOOTCOUNT_LIMIT
+
+#define CONFIG_PREBOOT	"echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=$(serverip):$(rootpath)\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw "			\
+	"console=ttyS0,115200\0"					\
+	"addip=setenv bootargs $(bootargs) "				\
+		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"	\
+		":$(hostname):$(netdev):off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm $(kernel_addr)\0"				\
+	"flash_self=run ramargs addip;"					\
+		"bootm $(kernel_addr) $(ramdisk_addr)\0"		\
+	"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0"	\
+	"rootpath=/opt/eldk/ppc_82xx\0"					\
+	"bootfile=/tftpboot/IDS8247/uImage\0"				\
+	"kernel_addr=ff800000\0"					\
+	"ramdisk_addr=ffa00000\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#define CONFIG_MISC_INIT_R	1
+
+/* enable I2C and select the hardware/software driver */
+#undef  CONFIG_HARD_I2C			/* I2C with hardware support	*/
+#define CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CFG_I2C_SLAVE		0x7F
+
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+
+#define I2C_PORT	0		/* Port A=0, B=1, C=2, D=3 */
+#define I2C_ACTIVE	(iop->pdir |=  0x00000080)
+#define I2C_TRISTATE	(iop->pdir &= ~0x00000080)
+#define I2C_READ	((iop->pdat & 0x00000080) != 0)
+#define I2C_SDA(bit)	if(bit) iop->pdat |=  0x00000080; \
+			else    iop->pdat &= ~0x00000080
+#define I2C_SCL(bit)	if(bit) iop->pdat |=  0x00000100; \
+			else    iop->pdat &= ~0x00000100
+#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
+
+#if 0
+#define CFG_I2C_EEPROM_ADDR	0x50
+#define CFG_I2C_EEPROM_ADDR_LEN 2
+#define CFG_EEPROM_PAGE_WRITE_BITS	4
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
+
+#define CONFIG_I2C_X
+#endif
+
+/*
+ * select serial console configuration
+ * use the extern UART for the console
+ */
+#define	CONFIG_CONS_INDEX	1
+#define CONFIG_BAUDRATE		115200
+/*
+ * NS16550 Configuration
+ */
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+
+#define CFG_NS16550_REG_SIZE    1
+
+#define CFG_NS16550_CLK         14745600
+
+#define	CFG_UART_BASE	0xE0000000
+#define CFG_UART_SIZE	0x10000
+
+#define CFG_NS16550_COM1        (CFG_UART_BASE + 0x8000)
+
+/*
+ * select ethernet configuration
+ *
+ * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
+ * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
+ * for FCC)
+ *
+ * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
+ * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
+ * from CONFIG_COMMANDS to remove support for networking.
+ *
+ */
+#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC       */
+#define	CONFIG_ETHER_ON_FCC		/* define if ether on FCC       */
+#undef	CONFIG_ETHER_NONE		/* define if ether on something else */
+#define	CONFIG_ETHER_INDEX    2		/* which SCC/FCC channel for ethernet */
+
+/*
+ * - Rx-CLK is CLK13
+ * - Tx-CLK is CLK14
+ * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
+ * - Enable Full Duplex in FSMR
+ */
+# define CFG_CMXFCR_MASK	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
+# define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
+# define CFG_CPMFCR_RAMTYPE	0
+# define CFG_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
+
+
+/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
+#define CONFIG_8260_CLKIN	66666666	/* in Hz */
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_NAND	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_SNTP	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END	0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CFG_LOAD_ADDR	0x100000	/* default load address	*/
+
+#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#define	CFG_RESET_ADDRESS 0xFDFFFFFC	/* "bad" address		*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */
+
+
+/* What should the base address of the main FLASH be and how big is
+ * it (in MBytes)? This must contain TEXT_BASE from board/ids8247/config.mk
+ * The main FLASH is whichever is connected to *CS0.
+ */
+#define CFG_FLASH0_BASE 0xFFF00000
+#define CFG_FLASH0_SIZE 8
+
+/* Flash bank size (for preliminary settings)
+ */
+#define CFG_FLASH_SIZE CFG_FLASH0_SIZE
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks      */
+#define CFG_MAX_FLASH_SECT	64	/* max num of sects on one chip */
+
+#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
+#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
+
+/* Environment in flash */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE+0x60000)
+#define CFG_ENV_SIZE		0x20000
+#define CFG_ENV_SECT_SIZE	0x20000
+
+/*-----------------------------------------------------------------------
+ * NAND-FLASH stuff
+ *-----------------------------------------------------------------------
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+
+#define CFG_NAND0_BASE 0xE1000000
+
+#define CFG_MAX_NAND_DEVICE     1       /* Max number of NAND devices           */
+#define SECTORSIZE 512
+#define NAND_NO_RB
+
+#define ADDR_COLUMN 1
+#define ADDR_PAGE 2
+#define ADDR_COLUMN_PAGE 3
+
+#define NAND_ChipID_UNKNOWN     0x00
+#define NAND_MAX_FLOORS 1
+#define NAND_MAX_CHIPS 1
+
+#define NAND_DISABLE_CE(nand) do \
+{ \
+	*(((volatile __u8 *)(nand->IO_ADDR)) + 0xc) = 0; \
+} while(0)
+
+#define NAND_ENABLE_CE(nand) do \
+{ \
+	*(((volatile __u8 *)(nand->IO_ADDR)) + 0x8) = 0; \
+} while(0)
+
+#define NAND_CTL_CLRALE(nandptr) do \
+{ \
+	*(((volatile __u8 *)nandptr) + 0x8) = 0; \
+} while(0)
+
+#define NAND_CTL_SETALE(nandptr) do \
+{ \
+	*(((volatile __u8 *)nandptr) + 0x9) = 0; \
+} while(0)
+
+#define NAND_CTL_CLRCLE(nandptr) do \
+{ \
+	*(((volatile __u8 *)nandptr) + 0x8) = 0; \
+} while(0)
+
+#define NAND_CTL_SETCLE(nandptr) do \
+{ \
+	*(((volatile __u8 *)nandptr) + 0xa) = 0; \
+} while(0)
+
+#ifdef NAND_NO_RB
+/* constant delay (see also tR in the datasheet) */
+#define NAND_WAIT_READY(nand) do { \
+	udelay(12); \
+} while (0)
+#else
+/* use the R/B pin */
+#endif
+
+#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr + 0x2)) = (__u8)(d); } while(0)
+#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr + 0x1)) = (__u8)(d); } while(0)
+#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr + 0x0)) = (__u8)d; } while(0)
+#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)(adr + 0x0)))
+
+#endif /* CFG_CMD_NAND */
+
+/*-----------------------------------------------------------------------
+ * Hard Reset Configuration Words
+ *
+ * if you change bits in the HRCW, you must also change the CFG_*
+ * defines for the various registers affected by the HRCW e.g. changing
+ * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
+ */
+#define CFG_HRCW_MASTER	(HRCW_BPS01 | HRCW_BMS | HRCW_ISB100 | HRCW_APPC10 | HRCW_MODCK_H1000)
+
+/* no slaves so just fill with zeros */
+#define CFG_HRCW_SLAVE1		0
+#define CFG_HRCW_SLAVE2		0
+#define CFG_HRCW_SLAVE3		0
+#define CFG_HRCW_SLAVE4		0
+#define CFG_HRCW_SLAVE5		0
+#define CFG_HRCW_SLAVE6		0
+#define CFG_HRCW_SLAVE7		0
+
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xF0000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define CFG_INIT_RAM_END	0x2000  /* End of used area in DPRAM    */
+#define CFG_GBL_DATA_SIZE	128 /* size in bytes reserved for initial data*/
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ *
+ * 60x SDRAM is mapped at CFG_SDRAM_BASE
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		CFG_FLASH0_BASE
+#define CFG_MONITOR_BASE	TEXT_BASE
+#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH*/
+#define BOOTFLAG_WARM		0x02	/* Software reboot                 */
+
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * HIDx - Hardware Implementation-dependent Registers                    2-11
+ *-----------------------------------------------------------------------
+ * HID0 also contains cache control - initially enable both caches and
+ * invalidate contents, then the final state leaves only the instruction
+ * cache enabled. Note that Power-On and Hard reset invalidate the caches,
+ * but Soft reset does not.
+ *
+ * HID1 has only read-only information - nothing to set.
+ */
+
+#define CFG_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI)
+#define CFG_HID0_FINAL  0
+#define CFG_HID2        0
+
+/*-----------------------------------------------------------------------
+ * RMR - Reset Mode Register                                     5-5
+ *-----------------------------------------------------------------------
+ * turn on Checkstop Reset Enable
+ */
+#define CFG_RMR         0
+
+/*-----------------------------------------------------------------------
+ * BCR - Bus Configuration                                       4-25
+ *-----------------------------------------------------------------------
+ */
+#define CFG_BCR		0
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration                             4-31
+ *-----------------------------------------------------------------------
+ */
+#define CFG_SIUMCR      (SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_BCTLC01)
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control                             4-35
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
+#else
+#define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+			 SYPCR_SWRI|SYPCR_SWP)
+#endif /* CONFIG_WATCHDOG */
+
+/*-----------------------------------------------------------------------
+ * TMCNTSC - Time Counter Status and Control                     4-40
+ *-----------------------------------------------------------------------
+ * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
+ * and enable Time Counter
+ */
+#define CFG_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control                 4-42
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
+ * Periodic timer
+ */
+#define CFG_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock Control                                   9-8
+ *-----------------------------------------------------------------------
+ * Ensure DFBRG is Divide by 16
+ */
+#define CFG_SCCR        (0x00000028 | SCCR_DFBRG01)
+
+/*-----------------------------------------------------------------------
+ * RCCR - RISC Controller Configuration                         13-7
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RCCR        0
+
+/*
+ * Init Memory Controller:
+ *
+ * Bank Bus     Machine PortSz  Device
+ * ---- ---     ------- ------  ------
+ *  0   60x     GPCM    16 bit  FLASH
+ *  1   60x     GPCM     8 bit  NAND
+ *  2   60x     SDRAM   32 bit  SDRAM
+ *  3   60x     GPCM     8 bit  UART
+ *
+ */
+
+#define SDRAM_MAX_SIZE	0x08000000	/* max. 128 MB		*/
+
+/* Minimum mask to separate preliminary
+ * address ranges for CS[0:2]
+ */
+#define CFG_GLOBAL_SDRAM_LIMIT	(32<<20)	/* less than 32 MB */
+
+#define CFG_MPTPR       0x6600
+
+/*-----------------------------------------------------------------------------
+ * Address for Mode Register Set (MRS) command
+ *-----------------------------------------------------------------------------
+ */
+#define CFG_MRS_OFFS	0x00000110
+
+
+/* Bank 0 - FLASH
+ */
+#define CFG_BR0_PRELIM  ((CFG_FLASH_BASE & BRx_BA_MSK)  |\
+			 BRx_PS_8                       |\
+			 BRx_MS_GPCM_P                  |\
+			 BRx_V)
+
+#define CFG_OR0_PRELIM  (MEG_TO_AM(CFG_FLASH_SIZE)      |\
+			 ORxG_SCY_6_CLK                 )
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+/* Bank 1 - NAND Flash
+*/
+#define	CFG_NAND_BASE		CFG_NAND0_BASE
+#define	CFG_NAND_SIZE		0x8000
+
+#define CFG_OR_TIMING_NAND	0x000036
+
+#define CFG_BR1_PRELIM  ((CFG_NAND_BASE & BRx_BA_MSK) | BRx_PS_8 | BRx_MS_GPCM_P | BRx_V  )
+#define CFG_OR1_PRELIM  (P2SZ_TO_AM(CFG_NAND_SIZE) | CFG_OR_TIMING_NAND )
+#endif
+
+/* Bank 2 - 60x bus SDRAM
+ */
+#define CFG_PSRT        0x20
+#define CFG_LSRT        0x20
+
+#define CFG_BR2_PRELIM  ((CFG_SDRAM_BASE & BRx_BA_MSK)  |\
+			 BRx_PS_32                      |\
+			 BRx_MS_SDRAM_P                 |\
+			 BRx_V)
+
+#define CFG_OR2_PRELIM	CFG_OR2
+
+
+/* SDRAM initialization values
+*/
+#define CFG_OR2    ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
+			 ORxS_BPD_4                     |\
+			 ORxS_ROWST_PBI0_A10             |\
+			 ORxS_NUMR_12)
+
+#define CFG_PSDMR  (PSDMR_SDAM_A13_IS_A5 |\
+			 PSDMR_BSMA_A15_A17           |\
+			 PSDMR_SDA10_PBI0_A11         |\
+			 PSDMR_RFRC_5_CLK               |\
+			 PSDMR_PRETOACT_2W              |\
+			 PSDMR_ACTTORW_2W               |\
+			 PSDMR_BL                       |\
+			 PSDMR_LDOTOPRE_2C              |\
+			 PSDMR_WRC_3C                   |\
+			 PSDMR_CL_3)
+
+/* Bank 3 - UART
+*/
+
+#define CFG_BR3_PRELIM  ((CFG_UART_BASE & BRx_BA_MSK) | BRx_PS_8 | BRx_MS_GPCM_P | BRx_V  )
+#define CFG_OR3_PRELIM  (((-CFG_UART_SIZE) & ORxG_AM_MSK) | ORxG_CSNT | ORxG_SCY_1_CLK | ORxG_TRLX )
+
+#endif	/* __CONFIG_H */

include/configs/PPChameleonEVB.h

@@ -106,8 +106,8 @@
 
 #define CONFIG_MII		1	/* MII PHY management		*/
 #ifndef	 CONFIG_EXT_PHY
-#define CONFIG_PHY_ADDR		0	/* EMAC0 PHY address		*/
-#define CONFIG_PHY1_ADDR	1	/* EMAC1 PHY address		*/
+#define CONFIG_PHY_ADDR		1	/* EMAC0 PHY address		*/
+#define CONFIG_PHY1_ADDR	2	/* EMAC1 PHY address		*/
 #else
 #define CONFIG_PHY_ADDR		2	/* PHY address			*/
 #endif

include/configs/TQM8540.h

@@ -279,7 +279,7 @@
 #endif
 
 #define CONFIG_MII		1	/* MII PHY management */
-#undef CONFIG_MPC85XX_TSEC1
+#define CONFIG_MPC85XX_TSEC1	1
 #define CONFIG_MPC85XX_TSEC2	1
 #define TSEC1_PHY_ADDR		0
 #define TSEC2_PHY_ADDR		1
@@ -287,9 +287,12 @@
 #define TSEC2_PHYIDX		0
 
 #define CONFIG_MPC85XX_FEC	1
-#define FEC_PHY_ADDR		0
+#define FEC_PHY_ADDR		2
 #define FEC_PHYIDX		0
 
+#define CONFIG_HAS_ETH1
+#define CONFIG_HAS_ETH2
+
 #define CONFIG_ETHPRIME		"ENET1"
 
 #endif	/* CONFIG_TSEC_ENET */

include/configs/TQM866M.h

@@ -136,13 +136,11 @@
 
 #define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
 				CFG_CMD_ASKENV	| \
-				CFG_CMD_DATE	| \
 				CFG_CMD_DHCP	| \
 				CFG_CMD_EEPROM	| \
 				CFG_CMD_I2C	| \
 				CFG_CMD_IDE	| \
-				CFG_CMD_NFS	| \
-				CFG_CMD_SNTP	)
+				CFG_CMD_NFS	)
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>

include/configs/VoVPN-GW.h

@@ -0,0 +1,406 @@
+/*
+ * (C) Copyright 2004
+ * Elmeg Communications Systems GmbH, Juergen Selent (j.selent@elmeg.de)
+ *
+ * Support for the Elmeg VoVPN Gateway Module
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* define cpu used */
+#define	CONFIG_MPC8272			1
+
+/* define busmode: 8260 */
+#undef	CONFIG_BUSMODE_60x
+
+/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
+#ifdef	CONFIG_CLKIN_66MHz
+#define	CONFIG_8260_CLKIN		66666666	/* in Hz */
+#else
+#define	CONFIG_8260_CLKIN		100000000	/* in Hz */
+#endif
+
+/* call board_early_init_f */
+#define	CONFIG_BOARD_EARLY_INIT_F	1
+
+/* have misc_init_r() function */
+#define CONFIG_MISC_INIT_R		1
+
+/* have reset_phy_r() function */
+#define CONFIG_RESET_PHY_R		1
+
+/* have special reset function */
+#define	CONFIG_HAVE_OWN_RESET		1
+
+/* allow serial and ethaddr to be overwritten */
+#define	CONFIG_ENV_OVERWRITE
+
+/* watchdog disabled */
+#undef	CONFIG_WATCHDOG
+
+/* include support for bzip2 compressed images */
+#undef	CONFIG_BZIP2
+
+/* status led */
+#undef	CONFIG_STATUS_LED		/* XXX jse */
+
+/* vendor parameter protection */
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * select serial console configuration
+ *
+ * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
+ * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
+ * for SCC).
+ */
+#define	CONFIG_CONS_ON_SMC
+#undef	CONFIG_CONS_ON_SCC
+#undef	CONFIG_CONS_NONE
+#define	CONFIG_CONS_INDEX		1
+
+/* serial port default baudrate */
+#define CONFIG_BAUDRATE			115200
+
+/* echo on for serial download	*/
+#define CONFIG_LOADS_ECHO		1
+
+/* don't allow baudrate change	*/
+#undef	CFG_LOADS_BAUD_CHANGE
+
+/* supported baudrates */
+#define CFG_BAUDRATE_TABLE		{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * select ethernet configuration
+ *
+ * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
+ * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
+ * for FCC)
+ *
+ * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
+ * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
+ * from CONFIG_COMMANDS to remove support for networking.
+ */
+#undef	CONFIG_ETHER_ON_SCC
+#define	CONFIG_ETHER_ON_FCC
+#undef	CONFIG_ETHER_NONE
+
+#ifdef	CONFIG_ETHER_ON_FCC
+
+/* which SCC/FCC channel for ethernet */
+#define	CONFIG_ETHER_INDEX		1
+
+/* Marvell Switch SMI base addr */
+#define CFG_PHY_ADDR			0x10
+
+/* FCC1 RMII REFCLK is CLK10 */
+#define CFG_CMXFCR_VALUE		CMXFCR_TF1CS_CLK10
+#define CFG_CMXFCR_MASK			(CMXFCR_FC1|CMXFCR_TF1CS_MSK)
+
+/* BDs and buffers on 60x bus */
+#define CFG_CPMFCR_RAMTYPE		0
+
+/* Local Protect, Full duplex, Flowcontrol, RMII */
+#define CFG_FCC_PSMR			(FCC_PSMR_LPB|FCC_PSMR_FDE|\
+					 FCC_PSMR_FCE|FCC_PSMR_RMII)
+
+/* bit-bang MII PHY management	*/
+#define CONFIG_BITBANGMII
+
+#define MDIO_PORT			1		/* Port B */
+#define CFG_MDIO_PIN			0x00002000	/* PB18 */
+#define CFG_MDC_PIN			0x00001000	/* PB19 */
+#define MDIO_ACTIVE			(iop->pdir |=  CFG_MDIO_PIN)
+#define MDIO_TRISTATE			(iop->pdir &= ~CFG_MDIO_PIN)
+#define MDIO_READ			((iop->pdat &  CFG_MDIO_PIN) != 0)
+#define MDIO(bit)			if(bit) iop->pdat |=  CFG_MDIO_PIN; \
+					else	iop->pdat &= ~CFG_MDIO_PIN
+#define MDC(bit)			if(bit) iop->pdat |=  CFG_MDC_PIN; \
+					else	iop->pdat &= ~CFG_MDC_PIN
+#define MIIDELAY			udelay(1)
+
+#endif
+
+/* configure commands */
+#define CONFIG_COMMANDS		(	CFG_CMD_AUTOSCRIPT	| \
+					CFG_CMD_BDI		| \
+					CFG_CMD_CONSOLE		| \
+					CFG_CMD_ECHO		| \
+					CFG_CMD_ENV		| \
+					CFG_CMD_FLASH		| \
+					CFG_CMD_IMI		| \
+					CFG_CMD_IMLS		| \
+					CFG_CMD_LOADB		| \
+					CFG_CMD_MEMORY		| \
+					CFG_CMD_MISC		| \
+					CFG_CMD_NET		| \
+					CFG_CMD_PING		| \
+					CFG_CMD_RUN	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * boot options & environment
+ */
+#define CONFIG_BOOTDELAY		3
+#define CONFIG_BOOTCOMMAND		"run flash_self"
+#undef  CONFIG_BOOTARGS
+#define	CONFIG_EXTRA_ENV_SETTINGS	\
+"clean_nv=erase fff20000 ffffffff\0" \
+"update_boss=tftp 100000 PPC/logic157.bin; protect off fff00000 ffffffff; erase fff00000 ffffffff; cp.b 100000 fff00000 $(filesize); tftp 100000 PPC/bootmon157.bin; cp.b 100000 fff20000 $(filesize)\0" \
+"update_lx=tftp 100000 $(kernel); erase $(kernel_addr) ffefffff; cp.b 100000 $(kernel_addr) $(filesize)\0" \
+"update_fs=tftp 100000 $(fs).$(fstype); erase ff840000 ffdfffff; cp.b 100000 ff840000 $(filesize)\0" \
+"update_ub=tftp 100000 $(uboot); protect off fff00000 fff1ffff; erase fff00000 fff1ffff; cp.b 100000 fff00000 $(filesize); protect off ff820000 ff83ffff; erase ff820000 ff83ffff\0" \
+"flashargs=setenv bootargs root=$(rootdev) rw rootfstype=$(fstype)\0" \
+"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath)\0" \
+"addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname):$(netdev):off\0" \
+"addmisc=setenv bootargs $(bootargs) console=$(console),$(baudrate) ethaddr=$(ethaddr) panic=1\0" \
+"net_nfs=tftpboot 400000 $(kernel); run nfsargs addip addmisc; bootm\0" \
+"net_self=tftpboot 400000 $(kernel); run flashargs addmisc; bootm\0" \
+"flash_self=run flashargs addmisc; bootm $(kernel_addr)\0" \
+"flash_nfs=run nfsargs addip addmisc; bootm $(kernel_addr)\0" \
+"fstype=cramfs\0" \
+"rootpath=/root_fs\0" \
+"uboot=PPC/u-boot.bin\0" \
+"kernel=PPC/uImage\0" \
+"kernel_addr=ffe00000\0" \
+"fs=PPC/root_fs\0" \
+"console=ttyS0\0" \
+"netdev=eth0\0" \
+"rootdev=31:3\0" \
+"ethaddr=00:09:4f:01:02:03\0" \
+"ipaddr=10.0.0.201\0" \
+"netmask=255.255.255.0\0" \
+"serverip=10.0.0.136\0" \
+"gatewayip=10.0.0.10\0" \
+"hostname=bastard\0" \
+""
+
+
+/*
+ * miscellaneous configurable options
+ */
+
+/* undef to save memory */
+#define	CFG_LONGHELP
+
+/* monitor command prompt */
+#define	CFG_PROMPT			"=> "
+
+/* console i/o buffer size */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE			1024
+#else
+#define	CFG_CBSIZE			256
+#endif
+
+/* print buffer size */
+#define	CFG_PBSIZE			(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
+
+/* max number of command args */
+#define	CFG_MAXARGS			16
+
+/* boot argument buffer size */
+#define CFG_BARGSIZE			CFG_CBSIZE
+
+/* memtest works on */
+#define CFG_MEMTEST_START		0x00100000
+/* 1 ... 15 MB in DRAM */
+#define CFG_MEMTEST_END			0x00f00000
+/* full featured memtest */
+#define CFG_ALT_MEMTEST
+
+/* default load address */
+#define	CFG_LOAD_ADDR			0x00100000
+
+/* decrementer freq: 1 ms ticks	*/
+#define	CFG_HZ				1000
+
+/* configure flash */
+#define CFG_FLASH_BASE			0xff800000
+#define CFG_MAX_FLASH_BANKS		1
+#define CFG_MAX_FLASH_SECT		64
+#define CFG_FLASH_SIZE			8
+#undef	CFG_FLASH_16BIT
+#define CFG_FLASH_ERASE_TOUT		240000
+#define CFG_FLASH_WRITE_TOUT		500
+#define CFG_FLASH_LOCK_TOUT		500
+#define CFG_FLASH_UNLOCK_TOUT		10000
+#define CFG_FLASH_PROTECTION
+
+/* monitor in flash */
+#define CFG_MONITOR_OFFSET		0x00700000
+
+/* environment in flash */
+#define CFG_ENV_IS_IN_FLASH		1
+#define CFG_ENV_ADDR			(CFG_FLASH_BASE + 0x00020000)
+#define CFG_ENV_SIZE			0x00020000
+#define CFG_ENV_SECT_SIZE		0x00020000
+
+/*
+ * Initial memory map for linux
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ			(8 << 20)
+
+/* hard reset configuration words */
+#ifdef	CONFIG_CLKIN_66MHz
+#define CFG_HRCW_MASTER			0x04643050
+#else
+#error NO HRCW FOR 100MHZ SPECIFIED !!!
+#endif
+#define CFG_HRCW_SLAVE1			0x00000000
+#define CFG_HRCW_SLAVE2			0x00000000
+#define CFG_HRCW_SLAVE3			0x00000000
+#define CFG_HRCW_SLAVE4			0x00000000
+#define CFG_HRCW_SLAVE5			0x00000000
+#define CFG_HRCW_SLAVE6			0x00000000
+#define CFG_HRCW_SLAVE7			0x00000000
+
+/* internal memory mapped register */
+#define CFG_IMMR			0xF0000000
+
+/* definitions for initial stack pointer and data area (in DPRAM) */
+#define CFG_INIT_RAM_ADDR		CFG_IMMR
+#define CFG_INIT_RAM_END		0x2000
+#define CFG_GBL_DATA_SIZE		128
+#define CFG_GBL_DATA_OFFSET		(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET		CFG_GBL_DATA_OFFSET
+
+/*
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE			0x00000000
+#define CFG_SDRAM_SIZE			(32*1024*1024)
+#define CFG_MONITOR_BASE		TEXT_BASE
+#define CFG_MONITOR_FLASH		(CFG_FLASH_BASE + CFG_MONITOR_OFFSET)
+#define CFG_MONITOR_LEN			0x00020000
+#define CFG_MALLOC_LEN			0x00020000
+
+/* boot flags */
+#define BOOTFLAG_COLD			0x01	/* normal power-on */
+#define BOOTFLAG_WARM			0x02	/* software reboot */
+
+/* cache configuration */
+#define CFG_CACHELINE_SIZE		32      /* for MPC8260 */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT		5	/* log base 2 of above */
+#endif
+
+/*
+ * HIDx - Hardware Implementation-dependent Registers
+ *-----------------------------------------------------------------------
+ * HID0 also contains cache control - initially enable both caches and
+ * invalidate contents, then the final state leaves only the instruction
+ * cache enabled. Note that Power-On and Hard reset invalidate the caches,
+ * but Soft reset does not.
+ *
+ * HID1 has only read-only information - nothing to set.
+ */
+#define CFG_HID0_INIT			(HID0_ICE|HID0_DCE|\
+					 HID0_ICFI|HID0_DCI|HID0_IFEM|HID0_ABE)
+#define CFG_HID0_FINAL			(HID0_IFEM|HID0_ABE)
+#define CFG_HID2			0
+
+/* RMR - reset mode register - turn on checkstop reset enable */
+#define CFG_RMR				RMR_CSRE
+
+/* BCR - bus configuration */
+#define CFG_BCR				0x00000000
+
+/* SIUMCR - siu module configuration */
+#define CFG_SIUMCR			0x4905c000
+
+/* SYPCR - system protection control */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR			0xffffff87
+#else
+#define CFG_SYPCR			0xffffff83
+#endif
+
+/* TMCNTSC - time counter status and control */
+/* clear interrupts XXX jse */
+/*#define CFG_TMCNTSC			(TMCNTSC_SEC|TMCNTSC_ALR) */
+#define CFG_TMCNTSC			(TMCNTSC_SEC|TMCNTSC_ALR|\
+					 TMCNTSC_TCF|TMCNTSC_TCE)
+
+/* PISCR - periodic interrupt status and control */
+/* clear interrupts XXX jse */
+/*#define CFG_PISCR			(PISCR_PS) */
+#define CFG_PISCR			(PISCR_PS|PISCR_PTF|PISCR_PTE)
+
+/* SCCR - system clock control */
+#define CFG_SCCR			0x000001a9
+
+/* RCCR - risc controller configuration */
+#define CFG_RCCR			0
+
+/*
+ * MEMORY MAP
+ * ----------
+ * CS0 - FLASH    8MB/8Bit 	base=0xff800000 (boot: 0xfe000000, 8x mirrored)
+ * CS1 - SDRAM   32MB/64Bit	base=0x00000000
+ * CS2 - DSP/SL1  1MB/16Bit	base=0xf0100000
+ * CS3 - DSP/SL2  1MB/16Bit	base=0xf0200000
+ * CS4 - DSP/SL3  1MB/16Bit	base=0xf0300000
+ * CS5 - DSP/SL4  1MB/16Bit	base=0xf0400000
+ * CS7 - DPRAM    1KB/8Bit	base=0xf0500000, size=32KB (32x mirrored)
+ *  x  - IMMR     384KB		base=0xf0000000
+ */
+/* XXX jse 100MHz TODO */
+#define CFG_BR0_PRELIM			0xff800801
+#define CFG_OR0_PRELIM			0xff801e44
+#define CFG_BR1_PRELIM			0x00000041
+#define CFG_OR1_PRELIM			0xfe002ec0
+#if 1
+#define CFG_BR2_PRELIM			0xf0101001
+#define CFG_OR2_PRELIM			0xfff00ef4
+#define CFG_BR3_PRELIM			0xf0201001
+#define CFG_OR3_PRELIM			0xfff00ef4
+#define CFG_BR4_PRELIM			0xf0301001
+#define CFG_OR4_PRELIM			0xfff00ef4
+#define CFG_BR5_PRELIM			0xf0401001
+#define CFG_OR5_PRELIM			0xfff00ef4
+#else
+#define CFG_BR2_PRELIM			0xf0101081
+#define CFG_OR2_PRELIM			0xfff00104
+#define CFG_BR3_PRELIM			0xf0201081
+#define CFG_OR3_PRELIM			0xfff00104
+#define CFG_BR4_PRELIM			0xf0301081
+#define CFG_OR4_PRELIM			0xfff00104
+#define CFG_BR5_PRELIM			0xf0401081
+#define CFG_OR5_PRELIM			0xfff00104
+#endif
+#define CFG_BR7_PRELIM			0xf0500881
+#define CFG_OR7_PRELIM			0xffff8104
+#define CFG_MPTPR			0x2700
+#define CFG_PSDMR			0x822a2452	/* optimal */
+/*#define CFG_PSDMR			0x822a48a3 */	/* relaxed */
+#define CFG_PSRT			0x1a
+
+/* "bad" address */
+#define	CFG_RESET_ADDRESS		0x40000000
+
+#endif	/* __CONFIG_H */

include/configs/cm4008.h

@@ -0,0 +1,123 @@
+/*
+ * (C) Copyright 2004
+ * Greg Ungerer <greg.ungerer@opengear.com>.
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_KS8695	1		/* it is a KS8695 CPU */
+#define CONFIG_CM4008	1		/* it is an OpenGear CM4008 boad */
+
+#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/
+
+#define CONFIG_CMDLINE_TAG	 1	/* enable passing of ATAGs	*/
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG	 1
+
+#define CONFIG_DRIVER_KS8695ETH		/* use KS8695 ethernet driver	*/
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * select serial console configuration
+ */
+#define CFG_ENV_IS_NOWHERE
+#define	CONFIG_SERIAL1
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_BAUDRATE		115200
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+#undef CONFIG_COMMANDS
+#define	CONFIG_COMMANDS		(CONFIG_CMD_DFL & ~(CFG_CMD_NONSTD | CFG_CMD_ENV))
+
+#define CONFIG_BOOTDELAY	0
+#define CONFIG_BOOTARGS		"mem=16M console=ttyAM0,115200"
+#define CONFIG_BOOTCOMMAND	"gofsk 0x02200000"
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP				/* undef to save memory		*/
+#define CFG_PROMPT		"boot > "	/* Monitor Command Prompt	*/
+#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x00800000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x01000000	/* 16 MB in DRAM	*/
+
+#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR		0x00008000	/* default load address */
+
+#define CFG_HZ			(1000)		/* 1ms resolution ticks */
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1	   /* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1		0x00000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE	0x01000000 /* 16 MB */
+
+#define PHYS_FLASH_1		0x02000000 /* Flash Bank #1 */
+#define PHYS_FLASH_SECT_SIZE    0x00020000 /* 128 KB sectors (x1) */
+#define CFG_FLASH_BASE		PHYS_FLASH_1
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CFG_MAX_FLASH_BANKS	2	/* max number of flash banks */
+#define CFG_MAX_FLASH_SECT	(128)	/* max number of sectors on one chip */
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT	(20*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT	(20*CFG_HZ) /* Timeout for Flash Write */
+
+#define CFG_ENV_SIZE		0x20000     /* Total Size of Environment */
+
+#endif	/* __CONFIG_H */

include/configs/cm41xx.h

@@ -0,0 +1,123 @@
+/*
+ * (C) Copyright 2005
+ * Greg Ungerer <greg.ungerer@opengear.com>.
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_KS8695	1		/* it is a KS8695 CPU */
+#define CONFIG_CM41xx	1		/* it is an OpenGear CM41xx boad */
+
+#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/
+
+#define CONFIG_CMDLINE_TAG	 1	/* enable passing of ATAGs	*/
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG	 1
+
+#define CONFIG_DRIVER_KS8695ETH		/* use KS8695 ethernet driver	*/
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * select serial console configuration
+ */
+#define CFG_ENV_IS_NOWHERE
+#define	CONFIG_SERIAL1
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_BAUDRATE		115200
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+#undef CONFIG_COMMANDS
+#define	CONFIG_COMMANDS		(CONFIG_CMD_DFL & ~(CFG_CMD_NONSTD | CFG_CMD_ENV))
+
+#define CONFIG_BOOTDELAY	0
+#define CONFIG_BOOTARGS		"mem=32M console=ttyAM0,115200"
+#define CONFIG_BOOTCOMMAND	"gofsk 0x02200000"
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP				/* undef to save memory		*/
+#define CFG_PROMPT		"boot > "	/* Monitor Command Prompt	*/
+#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x00800000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x01000000	/* 16 MB in DRAM	*/
+
+#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR		0x00008000	/* default load address */
+
+#define CFG_HZ			(1000)		/* 1ms resolution ticks */
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1	   /* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1		0x00000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE	0x02000000 /* 32 MB */
+
+#define PHYS_FLASH_1		0x02000000 /* Flash Bank #1 */
+#define PHYS_FLASH_SECT_SIZE    0x00020000 /* 128 KB sectors (x1) */
+#define CFG_FLASH_BASE		PHYS_FLASH_1
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CFG_MAX_FLASH_BANKS	2	/* max number of flash banks */
+#define CFG_MAX_FLASH_SECT	(128)	/* max number of sectors on one chip */
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT	(20*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT	(20*CFG_HZ) /* Timeout for Flash Write */
+
+#define CFG_ENV_SIZE		0x20000     /* Total Size of Environment */
+
+#endif	/* __CONFIG_H */

include/configs/hmi1001.h

@@ -0,0 +1,273 @@
+/*
+ * (C) Copyright 2003-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU		*/
+#define CONFIG_MPC5200		1	/* (more precisely an MPC5200 CPU)	*/
+#define CONFIG_HMI1001		1	/* HMI1001 board			*/
+
+#define CFG_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz		*/
+
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM		0x02	/* Software reboot			*/
+
+#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+#define CONFIG_BOARD_EARLY_INIT_R
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1	*/
+#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps	*/
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+/*
+ * Supported commands
+ */
+#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_EEPROM	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_SNTP)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define	CONFIG_TIMESTAMP	1	/* Print image info with timestamp */
+
+#if (TEXT_BASE == 0xFFF00000) /* Boot low */
+#   define CFG_LOWBOOT		1
+#endif
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
+
+#define CONFIG_PREBOOT	"echo;" \
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=$(serverip):$(rootpath)\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs $(bootargs) "				\
+		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"	\
+		":$(hostname):$(netdev):off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm $(kernel_addr)\0"				\
+	"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0"	\
+	"rootpath=/opt/eldk/ppc_82xx\0"					\
+	""
+
+#define CONFIG_BOOTCOMMAND	"run net_nfs"
+
+/*
+ * IPB Bus clocking configuration.
+ */
+#undef CFG_IPBSPEED_133		/* define for 133MHz speed */
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
+#define CFG_I2C_MODULE		2	/* Select I2C module #1 or #2 */
+
+#define CFG_I2C_SPEED		100000 /* 100 kHz */
+#define CFG_I2C_SLAVE		0x7F
+
+/*
+ * EEPROM configuration
+ */
+#define CFG_I2C_EEPROM_ADDR		0x58
+#define CFG_I2C_EEPROM_ADDR_LEN		1
+#define CFG_EEPROM_PAGE_WRITE_BITS	4
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10
+
+/*
+ * RTC configuration
+ */
+#define CONFIG_RTC_PCF8563
+#define CFG_I2C_RTC_ADDR		0x51
+
+/*
+ * Flash configuration
+ */
+#define CFG_FLASH_BASE		0xFF800000
+
+#define CFG_FLASH_SIZE		0x00800000 /* 8 MByte */
+#define CFG_MAX_FLASH_SECT	67	/* max num of sects on one chip */
+
+#define CFG_ENV_ADDR		(TEXT_BASE+0x40000) /* second sector */
+#define CFG_MAX_FLASH_BANKS	1	/* max num of flash banks
+					   (= chip selects) */
+#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
+
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_FLASH_CFI
+#define CFG_FLASH_EMPTY_INFO
+#define CFG_FLASH_CFI_AMD_RESET
+
+/*
+ * Environment settings
+ */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_SIZE		0x4000
+#define CFG_ENV_SECT_SIZE	0x20000
+#define CFG_ENV_OFFSET_REDUND   (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND     (CFG_ENV_SIZE)
+
+/*
+ * Memory map
+ */
+#define CFG_MBAR		0xF0000000
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_DEFAULT_MBAR	0x80000000
+
+/* Settings for XLB = 132 MHz */
+#define SDRAM_DDR	 1
+#define SDRAM_MODE      0x018D0000
+#define SDRAM_EMODE     0x40090000
+#define SDRAM_CONTROL   0x714f0f00
+#define SDRAM_CONFIG1   0x73722930
+#define SDRAM_CONFIG2   0x47770000
+#define SDRAM_TAPDELAY  0x10000000
+
+/* Use ON-Chip SRAM until RAM will be available */
+#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
+#ifdef CONFIG_POST
+/* preserve space for the post_word at end of on-chip SRAM */
+#define CFG_INIT_RAM_END	MPC5XXX_SRAM_POST_SIZE
+#else
+#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE
+#endif
+
+
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_BASE    TEXT_BASE
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#   define CFG_RAMBOOT		1
+#endif
+
+#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(512 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC	1
+#define CONFIG_PHY_ADDR		0x00
+
+/*
+ * GPIO configuration
+ */
+#define CFG_GPS_PORT_CONFIG	0x01051004
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory	    */
+#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
+#else
+#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS		16	/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+/* Enable an alternate, more extensive memory test */
+#define CFG_ALT_MEMTEST
+
+#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
+#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x100000	/* default load address */
+
+#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+
+/*
+ * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
+ * which is normally part of the default commands (CFV_CMD_DFL)
+ */
+#define CONFIG_LOOPW
+
+/*
+ * Various low-level settings
+ */
+#if defined(CONFIG_MPC5200)
+#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CFG_HID0_FINAL		HID0_ICE
+#else
+#define CFG_HID0_INIT		0
+#define CFG_HID0_FINAL		0
+#endif
+
+#define CFG_BOOTCS_START	CFG_FLASH_BASE
+#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
+#define CFG_BOOTCS_CFG		0x0004FB00
+#define CFG_CS0_START		CFG_FLASH_BASE
+#define CFG_CS0_SIZE		CFG_FLASH_SIZE
+
+/* 8Mbit SRAM @0x80100000 */
+#define CFG_CS1_START		0x80100000
+#define CFG_CS1_SIZE		0x00100000
+#define CFG_CS1_CFG		0x19B00
+
+/* FRAM 32Kbyte @0x80700000 */
+#define CFG_CS2_START		0x80700000
+#define CFG_CS2_SIZE		0x00008000
+#define CFG_CS2_CFG		0x19800
+
+/* Display H1, Status Inputs, EPLD @0x80600000 */
+#define CFG_CS3_START		0x80600000
+#define CFG_CS3_SIZE		0x00000210
+#define CFG_CS3_CFG		0x9800
+
+#define CFG_CS_BURST		0x00000000
+#define CFG_CS_DEADCYCLE	0x33333333
+
+#endif /* __CONFIG_H */

include/configs/lwmon.h

@@ -53,6 +53,8 @@
 #define CONFIG_LCD		1	/* use LCD controller ...	*/
 #define CONFIG_HLD1045		1	/* ... with a HLD1045 display	*/
 
+#define CONFIG_LCD_LOGO		1	/* print our logo on the LCD	*/
+#define CONFIG_LCD_INFO		1	/* ... and some board info	*/
 #define	CONFIG_SPLASH_SCREEN		/* ... with splashscreen support*/
 
 #define CONFIG_SERIAL_MULTI	1

include/configs/sorcery.h

@@ -53,6 +53,22 @@
 #define CONFIG_BAUDRATE		115200	    /* ... at 115200 bps */
 #define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
+/* PCI */
+#define CONFIG_PCI              1
+#define CONFIG_PCI_PNP          1
+
+#define CONFIG_PCI_MEM_BUS      0x80000000
+#define CONFIG_PCI_MEM_PHYS     CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE     0x10000000
+
+#define CONFIG_PCI_IO_BUS	0x71000000
+#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE	0x01000000
+
+#define CONFIG_PCI_CFG_BUS	0x70000000
+#define CONFIG_PCI_CFG_PHYS	CONFIG_PCI_CFG_BUS
+#define CONFIG_PCI_CFG_SIZE	0x01000000
+
 /*
  * Supported commands
  */
@@ -65,6 +81,7 @@
 				CFG_CMD_I2C	| \
 				CFG_CMD_NET	| \
 				CFG_CMD_NFS	| \
+				CFG_CMD_PCI	| \
 				CFG_CMD_PING	| \
 				CFG_CMD_REGINFO	| \
 				CFG_CMD_SDRAM	| \
@@ -72,7 +89,6 @@
 				0)
 
 /*			CFG_CMD_MII	| \ */
-/*			       CFG_CMD_PCI	| \ */
 /*			       CFG_CMD_USB	| \ */
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
@@ -113,6 +129,7 @@
 #define CONFIG_TIMESTAMP		/* Print image info with timestamp */
 
 #define CONFIG_NET_MULTI
+#define CONFIG_EEPRO100
 
 /*
  * I2C configuration
@@ -138,49 +155,38 @@
 /* Flash */
 #define CFG_CS0_BASE		0xf800
 #define CFG_CS0_MASK		0x08000000 /* 128 MB (two chips) */
-
-/* Workaround of hang-up after setting ctrl register for flash
-   After reset this register has value 0x003ffd80, which differs
-   from suggested only by the number of wait states.
-#define CFG_CS0_CTRL		0x003f1580
-*/
+#define CFG_CS0_CTRL		0x001019c0
 
 /* NVM */
-#define CFG_CS1_BASE		0xf100
-#define CFG_CS1_MASK		0x00080000  /* 512K */
-#define CFG_CS1_CTRL		0x003ffd40  /* 8bit port size? */
+#define CFG_CS1_BASE		0xf7e8
+#define CFG_CS1_MASK		0x00040000 /* 256K */
+#define CFG_CS1_CTRL		0x00101940 /* 8bit port size */
 
 /* Atlas2 + Gemini */
-/* This CS# is mandatory? */
-#define CFG_CS2_BASE		0xf10A
-#define CFG_CS2_MASK		0x00020000 /* 2x64K*/
-#define CFG_CS2_CTRL		0x003ffd00 /* 32bit port size? */
+#define CFG_CS2_BASE		0xf7e7
+#define CFG_CS2_MASK		0x00010000 /* 64K*/
+#define CFG_CS2_CTRL		0x001011c0 /* 16bit port size */
 
 /* CAN Controller */
-/* This CS# is mandatory? */
-#define CFG_CS3_BASE		0xf10C
+#define CFG_CS3_BASE		0xf7e6
 #define CFG_CS3_MASK		0x00010000 /* 64K */
-#define CFG_CS3_CTRL		0x003ffd40 /* 8Bit port size */
+#define CFG_CS3_CTRL		0x00102140 /* 8Bit port size */
 
 /* Foreign interface */
-#define CFG_CS4_BASE		0xF10D
+#define CFG_CS4_BASE		0xf7e5
 #define CFG_CS4_MASK		0x00010000 /* 64K */
-#define CFG_CS4_CTRL		0x003ffd80 /* 16bit port size */
+#define CFG_CS4_CTRL		0x00101dc0 /* 16bit port size */
 
-/* CPLD? */
-/* This CS# is mandatory? */
-#define CFG_CS5_BASE		0xF108
-#define CFG_CS5_MASK		0x00010000
-#define CFG_CS5_CTRL		0x003ffd80 /* 16bit port size */
+/* CPLD */
+#define CFG_CS5_BASE		0xf7e4
+#define CFG_CS5_MASK		0x00010000 /* 64K */
+#define CFG_CS5_CTRL		0x001000c0 /* 16bit port size */
 
 #define CFG_FLASH0_BASE		(CFG_CS0_BASE << 16)
-#define CFG_FLASH_BASE		CFG_FLASH0_BASE
+#define CFG_FLASH_BASE		(CFG_FLASH0_BASE)
 
-#define CFG_MAX_FLASH_BANKS	2	/* max num of memory banks (actually 4? (at least 2)) */
-#define CFG_MAX_FLASH_SECT	512	/* max num of sects on one chip (actually 256) */
-
-
-#define PHYS_AMD_SECT_SIZE	0x00020000 /* 128 KB sectors (x2) */
+#define CFG_MAX_FLASH_BANKS	2	/* max num of flash banks */
+#define CFG_MAX_FLASH_SECT	512	/* max num of sects on one chip */
 
 #define CFG_FLASH_CFI_DRIVER
 #define CFG_FLASH_CFI
@@ -191,9 +197,11 @@
  * Environment settings
  */
 #define CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_ADDR		(CFG_FLASH0_BASE)
-#define CFG_ENV_SIZE		PHYS_AMD_SECT_SIZE
-#define CFG_ENV_SECT_SIZE	PHYS_AMD_SECT_SIZE
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x8000000 - 0x40000)
+#define CFG_ENV_SIZE		0x4000                       /* 16K */
+#define CFG_ENV_SECT_SIZE	0x20000
+#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR + 0x20000)
+#define CFG_ENV_SIZE_REDUND	CFG_ENV_SIZE
 
 #define CONFIG_ENV_OVERWRITE	1
 
@@ -240,6 +248,13 @@
 #define CFG_SDRAM_SPD_SIZE		0x100
 #define CFG_SDRAM_CAS_LATENCY		5 		/* (CL=2.5)x2 */
 
+/* SDRAM drive strength register (for SSTL_2 class II)*/
+#define CFG_SDRAM_DRIVE_STRENGTH 	((DRIVE_STRENGTH_HIGH << SDRAMDS_SBE_SHIFT) | \
+					 (DRIVE_STRENGTH_HIGH << SDRAMDS_SBC_SHIFT) | \
+					 (DRIVE_STRENGTH_HIGH << SDRAMDS_SBA_SHIFT) | \
+					 (DRIVE_STRENGTH_HIGH << SDRAMDS_SBS_SHIFT) | \
+					 (DRIVE_STRENGTH_HIGH << SDRAMDS_SBD_SHIFT))
+
 /*
  * Ethernet configuration
  */
@@ -274,4 +289,9 @@
 #define CFG_HID0_INIT		0
 #define CFG_HID0_FINAL		0
 
+/*
+#define CFG_HID0_INIT           HID0_ICE | HID0_ICFI
+#define CFG_HID0_FINAL          HID0_ICE
+*/
+
 #endif /* __CONFIG_H */

include/jffs2/jffs2.h

@@ -72,7 +72,7 @@
 #else
 #define JFFS2_NUM_COMPR		7
 #endif
- 
+
 /* Compatibility flags. */
 #define JFFS2_COMPAT_MASK 0xc000      /* What do to if an unknown nodetype is found */
 #define JFFS2_NODE_ACCURATE 0x2000

include/lcd.h

@@ -171,13 +171,6 @@ void	lcd_printf	(const char *fmt, ...);
 # include <asm/byteorder.h>
 #endif /* (CONFIG_COMMANDS & CFG_CMD_BMP) || CONFIG_SPLASH_SCREEN */
 
-/************************************************************************/
-/* ** LOGO DATA								*/
-/************************************************************************/
-#ifdef CONFIG_LCD_LOGO
-# include <bmp_logo.h>		/* Get logo data, width and height	*/
-#endif
-
 /*
  *  Information about displays we are using. This is for configuring
  *  the LCD controller and memory allocation. Someone has to know what
@@ -193,7 +186,7 @@ void	lcd_printf	(const char *fmt, ...);
 #define LCD_COLOR16	4
 
 /*----------------------------------------------------------------------*/
-#if defined(LCD_INFO_BELOW_LOGO)
+#if defined(CONFIG_LCD_INFO_BELOW_LOGO)
 # define LCD_INFO_X		0
 # define LCD_INFO_Y		(BMP_LOGO_HEIGHT + VIDEO_FONT_HEIGHT)
 #elif defined(CONFIG_LCD_LOGO)
@@ -252,10 +245,6 @@ void	lcd_printf	(const char *fmt, ...);
 
 #endif /* color definitions */
 
-#if defined(CONFIG_LCD_LOGO) && (CONSOLE_COLOR_WHITE >= BMP_LOGO_OFFSET)
-# error Default Color Map overlaps with Logo Color Map
-#endif
-
 /************************************************************************/
 #ifndef PAGE_SIZE
 # define PAGE_SIZE	4096
@@ -264,7 +253,7 @@ void	lcd_printf	(const char *fmt, ...);
 /************************************************************************/
 /* ** CONSOLE DEFINITIONS & FUNCTIONS					*/
 /************************************************************************/
-#if defined(CONFIG_LCD_LOGO) && !defined(LCD_INFO_BELOW_LOGO)
+#if defined(CONFIG_LCD_LOGO) && !defined(CONFIG_LCD_INFO_BELOW_LOGO)
 # define CONSOLE_ROWS		((panel_info.vl_row-BMP_LOGO_HEIGHT) \
 					/ VIDEO_FONT_HEIGHT)
 #else

include/mpc8220.h

@@ -259,10 +259,12 @@
 #define PSC_TFLWFPTR(x)		(x&0x1ff)     /* last write frame pointer */
 
 /* PCI configuration (only for PLL determination)*/
-#define PCI_REG_PCIGSCR 	(MMAP_XCPCI + 0x60) /* Global status/control register */
+#define PCI_REG_PCIGSCR		(MMAP_XCPCI + 0x60) /* Global status/control register */
 #define PCI_REG_PCIGSCR_PCI2XLB_CLK_MASK	0x07000000
 #define PCI_REG_PCIGSCR_PCI2XLB_CLK_BIT		24
 
+#define PCI_REG_PCICAR		(MMAP_XCPCI + 0xF8) /* Configuration Address Register */
+
 /* ------------------------------------------------------------------------ */
 /*
  * Macro for General Purpose Timer
@@ -300,18 +302,21 @@
  */
 #define CFG_FEC1_PORT0_CONFIG	0x00000000
 #define CFG_FEC1_PORT1_CONFIG	0x00000000
-#define CFG_1284_PORT0_CONFIG	0x55555557
-#define CFG_1284_PORT1_CONFIG	0x80000000
+#define CFG_1284_PORT0_CONFIG  0x00000000
+#define CFG_1284_PORT1_CONFIG  0x00000000
 #define CFG_FEC2_PORT2_CONFIG	0x00000000
-#define CFG_PEV_PORT2_CONFIG	0x55555540
-#define CFG_GP0_PORT0_CONFIG	0xaaaaaaa0
-#define CFG_GP1_PORT2_CONFIG	0xaaaaa000
-#define CFG_PSC_PORT3_CONFIG	0x00000000
+#define CFG_PEV_PORT2_CONFIG   0x00000000
+#define CFG_GP0_PORT0_CONFIG   0x00000000
+#define CFG_GP1_PORT2_CONFIG   0xaaaaaac0
+#define CFG_PSC_PORT3_CONFIG   0x00020000
+#define CFG_CS1_PORT3_CONFIG   0x00000000
 #define CFG_CS2_PORT3_CONFIG	0x10000000
 #define CFG_CS3_PORT3_CONFIG	0x40000000
 #define CFG_CS4_PORT3_CONFIG	0x00000400
 #define CFG_CS5_PORT3_CONFIG	0x00000200
-#define CFG_I2C_PORT3_CONFIG	0x003c0000
+#define CFG_PCI_PORT3_CONFIG   0x01400180
+#define CFG_I2C_PORT3_CONFIG   0x00000000
+#define CFG_GP2_PORT3_CONFIG   0x000200a0
 
 /* ------------------------------------------------------------------------ */
 /*
@@ -527,6 +532,162 @@ struct mpc8220_dma {
     u32 EU37;		/* DMA + 0xfc */
 };
 
+/*
+ * PCI Header Registers
+ */
+typedef struct mpc8220_xcpci {
+	u32	dev_ven_id;		/* 0xb00 - device/vendor ID */
+	u32	stat_cmd_reg;		/* 0xb04 - status command register */
+	u32	class_code_rev_id;	/* 0xb08 - class code / revision ID */
+	u32	bist_htyp_lat_cshl;	/* 0xb0c - BIST/HeaderType/Latency/cache line */
+	u32	base0;			/* 0xb10 - base address 0 */
+	u32	base1;			/* 0xb14 - base address 1 */
+	u32	reserved1[4];		/* 0xb18->0xd27 - base address 2 - 5 */
+	u32	cis;			/* 0xb28 - cardBus CIS pointer */
+	u32	sub_sys_ven_id;		/* 0xb2c - sub system ID/ subsystem vendor ID */
+	u32	reserved2;		/* 0xb30 - expansion ROM base address */
+	u32	reserved3;		/* 0xb00 - reserved */
+	u32	reserved4;		/* 0xb00 - reserved */
+	u32	mlat_mgnt_ipl;		/* 0xb3c - MaxLat/MinGnt/ int pin/int line */
+	u32	reserved5[8];
+	/* MPC8220 specific - not accessible in PCI header space externally */
+	u32	glb_stat_ctl;		/* 0xb60 - Global Status Control */
+	u32	target_bar0;		/* 0xb64 - Target Base Address 0 */
+	u32	target_bar1;		/* 0xb68 - Target Base Address 1 */
+	u32	target_ctrl;		/* 0xb6c - Target Control */
+	u32	init_win0;		/* 0xb70 - Initiator Window 0 Base/Translation */
+	u32	init_win1;		/* 0xb74 - Initiator Window 1 Base/Translation */
+	u32	init_win2;		/* 0xb78 - Initiator Window 2 Base/Translation */
+	u32	reserved6;		/* 0xb7c - reserved  */
+	u32	init_win_cfg;		/* 0xb80 */
+	u32	init_ctrl;		/* 0xb84 */
+	u32	init_stat;		/* 0xb88 */
+	u32	reserved7[27];
+	u32	cfg_adr;		/* 0xbf8 */
+	u32	reserved8;
+} mpc8220_xcpci_t;
+
+/* PCI->XLB space translation (MPC8220 target), reg0 can address max 256MB,
+   reg1 - 1GB */
+#define PCI_BASE_ADDR_REG0			0x40000000
+#define PCI_BASE_ADDR_REG1			(CFG_SDRAM_BASE)
+#define PCI_TARGET_BASE_ADDR_REG0		(CFG_MBAR)
+#define PCI_TARGET_BASE_ADDR_REG1		(CFG_SDRAM_BASE)
+#define PCI_TARGET_BASE_ADDR_EN			1<<0
+
+
+/* PCI Global Status/Control Register (PCIGSCR) */
+#define PCI_GLB_STAT_CTRL_PE_SHIFT		29
+#define PCI_GLB_STAT_CTRL_SE_SHIFT		28
+#define PCI_GLB_STAT_CTRL_XLB_TO_PCI_CLK_SHIFT	24
+#define PCI_GLB_STAT_CTRL_XLB_TO_PCI_CLK_MASK	0x7
+#define PCI_GLB_STAT_CTRL_IPG_TO_PCI_CLK_SHIFT	16
+#define PCI_GLB_STAT_CTRL_IPG_TO_PCI_CLK_MASK	0x7
+#define PCI_GLB_STAT_CTRL_PEE_SHIFT		13
+#define PCI_GLB_STAT_CTRL_SEE_SHIFT		12
+#define PCI_GLB_STAT_CTRL_PR_SHIFT		0
+
+#define PCI_GLB_STAT_CTRL_PE			(1<<PCI_GLB_STAT_CTRL_PE_SHIFT)
+#define PCI_GLB_STAT_CTRL_SE			(1<<PCI_GLB_STAT_CTRL_SE_SHIFT)
+#define PCI_GLB_STAT_CTRL_PEE			(1<<PCI_GLB_STAT_CTRL_PEE_SHIFT)
+#define PCI_GLB_STAT_CTRL_SEE			(1<<PCI_GLB_STAT_CTRL_SEE_SHIFT)
+#define PCI_GLB_STAT_CTRL_PR			(1<<PCI_GLB_STAT_CTRL_PR_SHIFT)
+
+/* PCI Target Control Register (PCITCR) */
+#define PCI_TARGET_CTRL_LD_SHIFT		24
+#define PCI_TARGET_CTRL_P_SHIFT			16
+
+#define PCI_TARGET_CTRL_LD			(1<<PCI_TARGET_CTRL_LD_SHIFT)
+#define PCI_TARGET_CTRL_P			(1<<PCI_TARGET_CTRL_P_SHIFT)
+
+/* PCI Initiator Window Configuration Register (PCIIWCR) */
+#define PCI_INIT_WIN_CFG_WIN0_CTRL_IO_SHIFT	27
+#define PCI_INIT_WIN_CFG_WIN0_CTRL_PRC_SHIFT	25
+#define PCI_INIT_WIN_CFG_WIN0_CTRL_PRC_MASK	0x3
+#define PCI_INIT_WIN_CFG_WIN0_CTRL_EN_SHIFT	24
+#define PCI_INIT_WIN_CFG_WIN1_CTRL_IO_SHIFT	19
+#define PCI_INIT_WIN_CFG_WIN1_CTRL_PRC_SHIFT	17
+#define PCI_INIT_WIN_CFG_WIN1_CTRL_PRC_MASK	0x3
+#define PCI_INIT_WIN_CFG_WIN1_CTRL_EN_SHIFT	16
+#define PCI_INIT_WIN_CFG_WIN2_CTRL_IO_SHIFT	11
+#define PCI_INIT_WIN_CFG_WIN2_CTRL_PRC_SHIFT	9
+#define PCI_INIT_WIN_CFG_WIN2_CTRL_PRC_MASK	0x3
+#define PCI_INIT_WIN_CFG_WIN2_CTRL_EN_SHIFT	8
+
+#define PCI_INIT_WIN_CFG_WIN_MEM_READ		0x0
+#define PCI_INIT_WIN_CFG_WIN_MEM_READ_LINE	0x1
+#define PCI_INIT_WIN_CFG_WIN_MEM_READ_MULTIPLE	0x2
+
+#define PCI_INIT_WIN_CFG_WIN0_CTRL_IO		(1<<PCI_INIT_WIN_CFG_WIN0_CTRL_IO_SHIFT)
+#define PCI_INIT_WIN_CFG_WIN0_CTRL_EN		(1<<PCI_INIT_WIN_CFG_WIN0_CTRL_EN_SHIFT)
+#define PCI_INIT_WIN_CFG_WIN1_CTRL_IO		(1<<PCI_INIT_WIN_CFG_WIN1_CTRL_IO_SHIFT)
+#define PCI_INIT_WIN_CFG_WIN1_CTRL_EN		(1<<PCI_INIT_WIN_CFG_WIN1_CTRL_EN_SHIFT)
+#define PCI_INIT_WIN_CFG_WIN2_CTRL_IO		(1<<PCI_INIT_WIN_CFG_WIN2_CTRL_IO_SHIFT)
+#define PCI_INIT_WIN_CFG_WIN2_CTRL_EN		(1<<PCI_INIT_WIN_CFG_WIN2_CTRL_EN_SHIFT)
+
+/* PCI Initiator Control Register (PCIICR) */
+#define PCI_INIT_CTRL_REE_SHIFT			26
+#define PCI_INIT_CTRL_IAE_SHIFT			25
+#define PCI_INIT_CTRL_TAE_SHIFT			24
+#define PCI_INIT_CTRL_MAX_RETRIES_SHIFT		0
+#define PCI_INIT_CTRL_MAX_RETRIES_MASK		0xff
+
+#define PCI_INIT_CTRL_REE			(1<<PCI_INIT_CTRL_REE_SHIFT)
+#define PCI_INIT_CTRL_IAE			(1<<PCI_INIT_CTRL_IAE_SHIFT)
+#define PCI_INIT_CTRL_TAE			(1<<PCI_INIT_CTRL_TAE_SHIFT)
+
+/* PCI Status/Command Register (PCISCR) - PCI Dword 1 */
+#define PCI_STAT_CMD_PE_SHIFT			31
+#define PCI_STAT_CMD_SE_SHIFT			30
+#define PCI_STAT_CMD_MA_SHIFT			29
+#define PCI_STAT_CMD_TR_SHIFT			28
+#define PCI_STAT_CMD_TS_SHIFT			27
+#define PCI_STAT_CMD_DT_SHIFT			25
+#define PCI_STAT_CMD_DT_MASK			0x3
+#define PCI_STAT_CMD_DP_SHIFT			24
+#define PCI_STAT_CMD_FC_SHIFT			23
+#define PCI_STAT_CMD_R_SHIFT			22
+#define PCI_STAT_CMD_66M_SHIFT			21
+#define PCI_STAT_CMD_C_SHIFT			20
+#define PCI_STAT_CMD_F_SHIFT			9
+#define PCI_STAT_CMD_S_SHIFT			8
+#define PCI_STAT_CMD_ST_SHIFT			7
+#define PCI_STAT_CMD_PER_SHIFT			6
+#define PCI_STAT_CMD_V_SHIFT			5
+#define PCI_STAT_CMD_MW_SHIFT			4
+#define PCI_STAT_CMD_SP_SHIFT			3
+#define PCI_STAT_CMD_B_SHIFT			2
+#define PCI_STAT_CMD_M_SHIFT			1
+#define PCI_STAT_CMD_IO_SHIFT			0
+
+#define PCI_STAT_CMD_PE			(1<<PCI_STAT_CMD_PE_SHIFT)
+#define PCI_STAT_CMD_SE			(1<<PCI_STAT_CMD_SE_SHIFT)
+#define PCI_STAT_CMD_MA			(1<<PCI_STAT_CMD_MA_SHIFT)
+#define PCI_STAT_CMD_TR			(1<<PCI_STAT_CMD_TR_SHIFT)
+#define PCI_STAT_CMD_TS			(1<<PCI_STAT_CMD_TS_SHIFT)
+#define PCI_STAT_CMD_DP			(1<<PCI_STAT_CMD_DP_SHIFT)
+#define PCI_STAT_CMD_FC			(1<<PCI_STAT_CMD_FC_SHIFT)
+#define PCI_STAT_CMD_R				(1<<PCI_STAT_CMD_R_SHIFT)
+#define PCI_STAT_CMD_66M			(1<<PCI_STAT_CMD_66M_SHIFT)
+#define PCI_STAT_CMD_C				(1<<PCI_STAT_CMD_C_SHIFT)
+#define PCI_STAT_CMD_F				(1<<PCI_STAT_CMD_F_SHIFT)
+#define PCI_STAT_CMD_S				(1<<PCI_STAT_CMD_S_SHIFT)
+#define PCI_STAT_CMD_ST			(1<<PCI_STAT_CMD_ST_SHIFT)
+#define PCI_STAT_CMD_PER			(1<<PCI_STAT_CMD_PER_SHIFT)
+#define PCI_STAT_CMD_V				(1<<PCI_STAT_CMD_V_SHIFT)
+#define PCI_STAT_CMD_MW			(1<<PCI_STAT_CMD_MW_SHIFT)
+#define PCI_STAT_CMD_SP			(1<<PCI_STAT_CMD_SP_SHIFT)
+#define PCI_STAT_CMD_B				(1<<PCI_STAT_CMD_B_SHIFT)
+#define PCI_STAT_CMD_M				(1<<PCI_STAT_CMD_M_SHIFT)
+#define PCI_STAT_CMD_IO			(1<<PCI_STAT_CMD_IO_SHIFT)
+
+/* PCI Configuration 1 Register (PCICR1) - PCI Dword 3 */
+#define PCI_CFG1_HT_SHIFT			16
+#define PCI_CFG1_HT_MASK			0xff
+#define PCI_CFG1_LT_SHIFT			8
+#define PCI_CFG1_LT_MASK			0xff
+#define PCI_CFG1_CLS_SHIFT			0
+#define PCI_CFG1_CLS_MASK			0xf
 
 /* function prototypes */
 void loadtask(int basetask, int tasks);

lib_arm/armlinux.c

@@ -377,15 +377,30 @@ static void setup_videolfb_tag (gd_t *gd)
 }
 #endif /* CONFIG_VFD || CONFIG_LCD */
 
+#ifdef CONFIG_SERIAL_TAG
+void setup_serial_tag (struct tag **tmp)
+{
+	struct tag *params = *tmp;
+	struct tag_serialnr serialnr;
+	void get_board_serial(struct tag_serialnr *serialnr);
+
+	get_board_serial(&serialnr);
+	params->hdr.tag = ATAG_SERIAL;
+	params->hdr.size = tag_size (tag_serialnr);
+	params->u.serialnr.low = serialnr.low;
+	params->u.serialnr.high= serialnr.high;
+	params = tag_next (params);
+	*tmp = params;
+}
+#endif
+
 #ifdef CONFIG_REVISION_TAG
 void setup_revision_tag(struct tag **in_params)
 {
 	u32 rev = 0;
-#ifdef CONFIG_OMAP2420H4
 	u32 get_board_rev(void);
 
 	rev = get_board_rev();
-#endif
 	params->hdr.tag = ATAG_REVISION;
 	params->hdr.size = tag_size (tag_revision);
 	params->u.revision.rev = rev;

lib_ppc/board.c

@@ -905,7 +905,8 @@ void board_init_r (gd_t *id, ulong dest_addr)
     defined(CONFIG_PCU_E)	|| \
     defined(CONFIG_RPXSUPER)	|| \
     defined(CONFIG_STXGP3)	|| \
-    defined(CONFIG_SPD823TS)	)
+    defined(CONFIG_SPD823TS)	|| \
+    defined(CONFIG_RESET_PHY_R)	)
 
 	WATCHDOG_RESET ();
 	debug ("Reset Ethernet PHY\n");

net/eth.c

@@ -148,7 +148,7 @@ int eth_initialize(bd_t *bis)
 #if defined(CONFIG_MPC5xxx_FEC)
 	mpc5xxx_fec_initialize(bis);
 #endif
-#if defined(CONFIG_MPC8220)
+#if defined(CONFIG_MPC8220_FEC)
 	mpc8220_fec_initialize(bis);
 #endif
 #if defined(CONFIG_SK98)

post/cpu.c

@@ -120,6 +120,7 @@ int cpu_post_test (int flags)
 	WATCHDOG_RESET();
 	if (ret == 0)
 		ret = cpu_post_test_multi ();
+	WATCHDOG_RESET();
 	if (ret == 0)
 		ret = cpu_post_test_string ();
 	if (ret == 0)