* Add support for NSCU board

* Add support for TQM823M, TQM850M, TQM855M and TQM860M modules

* Add support for Am29LV160ML, Am29LV320ML, and Am29LV640ML
  mirror bit flash on TQM8xxM modules

CHANGELOG

@@ -1,3 +1,26 @@
+======================================================================
+Changes for U-Boot 0.4.2:
+======================================================================
+
+* Add support for NSCU board
+
+* Add support for TQM823M, TQM850M, TQM855M and TQM860M modules
+
+* Add support for Am29LV160ML, Am29LV320ML, and Am29LV640ML
+  mirror bit flash on TQM8xxM modules
+
+* Patch by Kenneth Johansson, 30 Jun 2003:
+  get rid of MK_CMD_ENTRY macro; update doc/README.command
+
+* Patch by Seb James, 30 Jun 2003:
+  Improve documentation of I2C configuration in README
+
+* Fix problems with previous log buffer "fixes"
+
+* Fix minor help text issues
+
+* "log append" did not append a newline
+
 ======================================================================
 Changes for U-Boot 0.4.1:
 ======================================================================

Makefile

@@ -372,6 +372,7 @@ xtract_8xx = $(subst _66MHz,,$(subst _80MHz,,$(subst _100MHz,,$(subst _LCD,,$(su
 
 FPS850L_config		\
 FPS860L_config		\
+NSCU_config		\
 TQM823L_config		\
 TQM823L_66MHz_config	\
 TQM823L_80MHz_config	\
@@ -390,6 +391,15 @@ TQM860L_80MHz_config	\
 TQM862L_config		\
 TQM862L_66MHz_config	\
 TQM862L_80MHz_config	\
+TQM855M_config		\
+TQM855M_66MHz_config	\
+TQM855M_80MHz_config	\
+TQM860M_config		\
+TQM860M_66MHz_config	\
+TQM860M_80MHz_config	\
+TQM862M_config		\
+TQM862M_66MHz_config	\
+TQM862M_80MHz_config	\
 TQM862M_100MHz_config:	unconfig
 	@ >include/config.h
 	@[ -z "$(findstring _66MHz,$@)" ] || \

README

@@ -653,6 +653,9 @@ The following options need to be configured:
 		CONFIG_RTC_DS1338	- use Maxim, Inc. DS1338 RTC
 		CONFIG_RTC_DS164x	- use Dallas DS164x RTC
 
+		Note that if the RTC uses I2C, then the I2C interface
+		must also be configured. See I2C Support, below.
+
 - Timestamp Support:
 
 		When CONFIG_TIMESTAMP is selected, the timestamp
@@ -904,29 +907,48 @@ The following options need to be configured:
 
 - I2C Support:	CONFIG_HARD_I2C | CONFIG_SOFT_I2C
 
-		Enables I2C serial bus commands.  If this is selected,
-		either CONFIG_HARD_I2C or CONFIG_SOFT_I2C must be defined
-		to include the appropriate I2C driver.
+		These enable I2C serial bus commands. Defining either of
+		(but not both of) CONFIG_HARD_I2C or CONFIG_SOFT_I2C will 
+		include the appropriate I2C driver for the selected cpu. 
 
-		See also: common/cmd_i2c.c for a description of the
+		This will allow you to use i2c commands at the u-boot 
+		command line (as long as you set CFG_CMD_I2C in 
+		CONFIG_COMMANDS) and communicate with i2c based realtime
+		clock chips. See common/cmd_i2c.c for a description of the
 		command line interface.
 
+		CONFIG_HARD_I2C	selects the CPM hardware driver for I2C. 
 
-		CONFIG_HARD_I2C
+		CONFIG_SOFT_I2C configures u-boot to use a software (aka 
+		bit-banging) driver instead of CPM or similar hardware
+		support for I2C.
 
-		Selects the CPM hardware driver for I2C.
+		There are several other quantities that must also be 
+		defined when you define CONFIG_HARD_I2C or CONFIG_SOFT_I2C.
 
-		CONFIG_SOFT_I2C
+		In both cases you will need to define CFG_I2C_SPEED
+		to be the frequency (in Hz) at which you wish your i2c bus 
+		to run and CFG_I2C_SLAVE to be the address of this node (ie 
+		the cpu's i2c node address). 
+		
+		Now, the u-boot i2c code for the mpc8xx (cpu/mpc8xx/i2c.c)
+		sets the cpu up as a master node and so its address should
+		therefore be cleared to 0 (See, eg, MPC823e User's Manual
+		p.16-473). So, set CFG_I2C_SLAVE to 0.  
 
-		Use software (aka bit-banging) driver instead of CPM
-		or similar hardware support for I2C.  This is configured
-		via the following defines.
+		That's all that's required for CONFIG_HARD_I2C. 
+
+		If you use the software i2c interface (CONFIG_SOFT_I2C)
+		then the following macros need to be defined (examples are
+		from include/configs/lwmon.h):
 
 		I2C_INIT
 
-		(Optional). Any commands necessary to enable I2C
+		(Optional). Any commands necessary to enable the I2C
 		controller or configure ports.
 
+		eg: #define I2C_INIT (immr->im_cpm.cp_pbdir |=  PB_SCL)
+
 		I2C_PORT
 
 		(Only for MPC8260 CPU). The I/O port to use (the code
@@ -939,32 +961,49 @@ The following options need to be configured:
 		(driven).  If the data line is open collector, this
 		define can be null.
 
+		eg: #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |=  PB_SDA)
+
 		I2C_TRISTATE
 
 		The code necessary to make the I2C data line tri-stated
 		(inactive).  If the data line is open collector, this
 		define can be null.
 
+		eg: #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
+
 		I2C_READ
 
 		Code that returns TRUE if the I2C data line is high,
 		FALSE if it is low.
 
+		eg: #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
+
 		I2C_SDA(bit)
 
 		If <bit> is TRUE, sets the I2C data line high. If it
 		is FALSE, it clears it (low).
 
+		eg: #define I2C_SDA(bit) \
+		         if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
+		         else    immr->im_cpm.cp_pbdat &= ~PB_SDA
+
 		I2C_SCL(bit)
 
 		If <bit> is TRUE, sets the I2C clock line high. If it
 		is FALSE, it clears it (low).
 
+		eg: #define I2C_SCL(bit) \
+		         if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
+		         else    immr->im_cpm.cp_pbdat &= ~PB_SCL 
+
 		I2C_DELAY
 
 		This delay is invoked four times per clock cycle so this
 		controls the rate of data transfer.  The data rate thus
-		is 1 / (I2C_DELAY * 4).
+		is 1 / (I2C_DELAY * 4). Often defined to be something
+		like: 
+		
+		#define I2C_DELAY  udelay(2)
 
 		CFG_I2C_INIT_BOARD
 

board/MAI/AmigaOneG3SE/cmd_boota.c

@@ -121,8 +121,8 @@ int do_boota (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 	return 0;
 }
 #if defined(CONFIG_AMIGAONEG3SE) && (CONFIG_COMMANDS & CFG_CMD_BSP)
-cmd_tbl_t U_BOOT_CMD(BOOTA) = MK_CMD_ENTRY(
-	"boota",   3,      1,      do_boota,
+U_BOOT_CMD(
+	boota,   3,      1,      do_boota,
 	"boota   - boot an Amiga kernel\n",
 	"address disk"
 );

board/MAI/menu/cmd_menu.c

@@ -8,8 +8,8 @@ int do_menu( cmd_tbl_t *cmdtp, /*bd_t *bd,*/ int flag, int argc, char *argv[] )
 }
 
 #if defined(CONFIG_AMIGAONEG3SE) && (CONFIG_COMMANDS & CFG_CMD_BSP)
-cmd_tbl_t U_BOOT_CMD(MENU) = MK_CMD_ENTRY(
-	"menu",   1,      1,      do_menu,
+U_BOOT_CMD(
+	menu,   1,      1,      do_menu,
 	"menu    - display BIOS setup menu\n",
 	""
 );

board/esd/dasa_sim/cmd_dasa_sim.c

@@ -225,8 +225,8 @@ int do_pci9054 (cmd_tbl_t * cmdtp, int flag, int argc,
 
 }
 
-cmd_tbl_t U_BOOT_CMD (pci9054) = MK_CMD_ENTRY(
-	"pci9054", 3, 1, do_pci9054,
+U_BOOT_CMD(
+	pci9054, 3, 1, do_pci9054,
 	"pci9054 - PLX PCI9054 EEPROM access\n",
 	"pci9054 info - print EEPROM values\n"
 	"pci9054 update - updates EEPROM with default values\n"

board/evb64260/zuma_pbb.c

@@ -198,20 +198,20 @@ do_zuma_init_mbox (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	return 0;
 }
 
-cmd_tbl_t U_BOOT_CMD(zuma_init_pbb) = MK_CMD_ENTRY(
-	"zinit",	 1,	 0,	 do_zuma_init_pbb,
+U_BOOT_CMD(
+	zinit,	 1,	 0,	 do_zuma_init_pbb,
 	"zinit   - init zuma pbb\n",
 	"\n"
 	"    - init zuma pbb\n"
 );
-cmd_tbl_t U_BOOT_CMD(zuma_test_dma) = MK_CMD_ENTRY(
-	"zdtest",	  3,	  1,	  do_zuma_test_dma,
+U_BOOT_CMD(
+	zdtest,	  3,	  1,	  do_zuma_test_dma,
 	"zdtest  - run dma test\n",
 	"[cmd [count]]\n"
 	"    - run dma cmd (w=0,v=1,cp=2,cmp=3,wi=4,vi=5), count bytes\n"
 );
-cmd_tbl_t U_BOOT_CMD(zuma_init_mbox) = MK_CMD_ENTRY(
-	"zminit",	  1,	  0,	  do_zuma_init_mbox,
+U_BOOT_CMD(
+	zminit,	  1,	  0,	  do_zuma_init_mbox,
 	"zminit  - init zuma mbox\n",
 	"\n"
 	"    - init zuma mbox\n"

board/hymod/bsp.c

@@ -275,8 +275,8 @@ do_fpga (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 	printf ("Usage:\n%s\n", cmdtp->usage);
 	return 1;
 }
-cmd_tbl_t U_BOOT_CMD(fpga) = MK_CMD_ENTRY(
-	"fpga",	6,	1,	do_fpga,
+U_BOOT_CMD(
+	fpga,	6,	1,	do_fpga,
 	"fpga    - FPGA sub-system\n",
 	"load [type] addr size\n"
 	"  - write the configuration data at memory address `addr',\n"
@@ -334,8 +334,8 @@ do_eecl (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 
 	return 0;
 }
-cmd_tbl_t U_BOOT_CMD(eec) = MK_CMD_ENTRY(
-	"eeclear",	1,	0,	do_eecl,
+U_BOOT_CMD(
+	eeclear,	1,	0,	do_eecl,
 	"eeclear - Clear the eeprom on a Hymod board \n",
 	"[type]\n"
 	"  - write zeroes into the EEPROM on the board of type `type'\n"

board/lwmon/lwmon.c

@@ -851,8 +851,8 @@ int do_pic (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	printf ("Usage:\n%s\n", cmdtp->usage);
 	return 1;
 }
-cmd_tbl_t U_BOOT_CMD(pic) = MK_CMD_ENTRY(
-	"pic",	4,	1,	do_pic,
+U_BOOT_CMD(
+	pic,	4,	1,	do_pic,
 	"pic     - read and write PIC registers\n",
 	"read  reg      - read PIC register `reg'\n"
 	"pic write reg val  - write value `val' to PIC register `reg'\n"
@@ -910,8 +910,8 @@ int do_kbd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	return 0;
 }
 
-cmd_tbl_t U_BOOT_CMD(kdb) = MK_CMD_ENTRY(
-	"kbd",	1,	1,	do_kbd,
+U_BOOT_CMD(
+	kbd,	1,	1,	do_kbd,
 	"kbd     - read keyboard status\n",
 	NULL
 );
@@ -982,8 +982,8 @@ int do_lsb (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	return 1;
 }
 
-cmd_tbl_t U_BOOT_CMD(lsb) = MK_CMD_ENTRY(
-	"lsb",	2,	1,	do_lsb,
+U_BOOT_CMD(
+	lsb,	2,	1,	do_lsb,
 	"lsb     - check and set LSB switch\n",
 	"on  - switch LSB on\n"
 	"lsb off - switch LSB off\n"

board/mpl/mip405/cmd_mip405.c

@@ -53,8 +53,8 @@ int do_mip405(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
    	}
 	return (do_mplcommon(cmdtp, flag, argc, argv));
 }
-cmd_tbl_t U_BOOT_CMD(mip405) = MK_CMD_ENTRY(
-	"mip405",	6,	1,	do_mip405,
+U_BOOT_CMD(
+	mip405,	6,	1,	do_mip405,
 	"mip405  - MIP405 specific Cmds\n",
 	"flash mem [SrcAddr] - updates U-Boot with image in memory\n"
 	"mip405 flash mps - updates U-Boot with image from MPS\n"

board/mpl/pip405/cmd_pip405.c

@@ -58,8 +58,8 @@ int do_pip405(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 	return (do_mplcommon(cmdtp, flag, argc, argv));
 }
-cmd_tbl_t U_BOOT_CMD(pip405) = MK_CMD_ENTRY(
-	"pip405",	6,	1,	do_pip405,
+U_BOOT_CMD(
+	pip405,	6,	1,	do_pip405,
 	"pip405  - PIP405 specific Cmds\n",
 	"flash mem [SrcAddr] - updates U-Boot with image in memory\n"
 	"pip405 flash floppy [SrcAddr] - updates U-Boot with image from floppy\n"

board/pcippc2/pcippc2.c

@@ -233,8 +233,8 @@ int do_wd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	return 1;
 }
 
-cmd_tbl_t U_BOOT_CMD(wd) = MK_CMD_ENTRY(
-	"wd",	2,	1,	do_wd,
+U_BOOT_CMD(
+	wd,	2,	1,	do_wd,
 	"wd      - check and set watchdog\n",
 	"on   - switch watchDog on\n"
 	"wd off  - switch watchdog off\n"

board/pn62/cmd_pn62.c

@@ -51,8 +51,8 @@ int do_led (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
     set_led (number, function);
     return 0;
 }
-cmd_tbl_t U_BOOT_CMD(led) = MK_CMD_ENTRY(
-	"led"    ,	3,	1,	do_led,
+U_BOOT_CMD(
+	led    ,	3,	1,	do_led,
 	"led     - set LED 0..11 on the PN62 board\n",
 	"i fun\n"
 	"    - set 'i'th LED to function 'fun'\n"
@@ -165,8 +165,8 @@ int do_loadpci (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
     return rcode;
 }
 
-cmd_tbl_t U_BOOT_CMD(loadpci) = MK_CMD_ENTRY(
-	"loadpci",	2,	1,	do_loadpci,
+U_BOOT_CMD(
+	loadpci,	2,	1,	do_loadpci,
 	"loadpci - load binary file over PCI\n",
 	"[addr]\n"
 	"    - load binary file over PCI to address 'addr'\n"

board/r360mpi/r360mpi.c

@@ -443,8 +443,8 @@ int do_kbd (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 	return 0;
 }
 
-cmd_tbl_t U_BOOT_CMD(kbd) = MK_CMD_ENTRY(
-	"kbd",	1,	1,	do_kbd,
+U_BOOT_CMD(
+	kbd,	1,	1,	do_kbd,
 	"kbd     - read keyboard status\n",
 	NULL
 );

board/siemens/common/fpga.c

@@ -291,8 +291,8 @@ int do_fpga (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
     return 1;
 }
 
-cmd_tbl_t U_BOOT_CMD(fpga) = MK_CMD_ENTRY(
-	"fpga",	4,	1,	do_fpga,
+U_BOOT_CMD(
+	fpga,	4,	1,	do_fpga,
 	"fpga    - access FPGA(s)\n",
 	"fpga status [name] - print FPGA status\n"
 	"fpga reset  [name] - reset FPGA\n"

board/siemens/pcu_e/pcu_e.c

@@ -432,8 +432,8 @@ int do_puma (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	printf ("Usage:\n%s\n", cmdtp->usage);
 	return 1;
 }
-cmd_tbl_t U_BOOT_CMD(puma) = MK_CMD_ENTRY(
-	"puma",	4,	1,	do_puma,
+U_BOOT_CMD(
+	puma,	4,	1,	do_puma,
 	"puma    - access PUMA FPGA\n",
 	"status - print PUMA status\n"
 	"puma load addr len - load PUMA configuration data\n"

board/tqm8xx/flash.c

@@ -209,6 +209,10 @@ void flash_print_info  (flash_info_t *info)
 #ifdef CONFIG_TQM8xxM	/* mirror bit flash */
 	case FLASH_AMLV128U:	printf ("AM29LV128ML (128Mbit, uniform sector size)\n");
 				break;
+	case FLASH_AMLV320U:	printf ("AM29LV320ML (32Mbit, uniform sector size)\n");
+				break;
+	case FLASH_AMLV640U:	printf ("AM29LV640ML (64Mbit, uniform sector size)\n");
+				break;
 # else	/* ! TQM8xxM */
 	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
 				break;
@@ -218,15 +222,15 @@ void flash_print_info  (flash_info_t *info)
 				break;
 	case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
 				break;
-	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
-				break;
-	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
-				break;
 	case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
 				break;
 	case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit, top boot sector)\n");
 				break;
 #endif	/* TQM8xxM */
+	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+				break;
 	default:		printf ("Unknown Chip Type\n");
 				break;
 	}
@@ -294,6 +298,14 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 	switch (value) {
 #ifdef CONFIG_TQM8xxM	/* mirror bit flash */
 	case AMD_ID_MIRROR:
+		/* Special case for AMLV320MH/L */
+		if ((addr[14] & 0x00ff00ff) == 0x001d001d &&
+			(addr[15] & 0x00ff00ff) == 0x00000000) {
+			info->flash_id += FLASH_AMLV320U;
+			info->sector_count = 64;
+			info->size = 0x00800000; /* => 8 MB */
+			break;
+		} 
 		switch(addr[14]) {
 		case AMD_ID_LV128U_2:
 			if (addr[15] != AMD_ID_LV128U_3) {
@@ -305,6 +317,16 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 				info->size = 0x02000000;
 			}
 			break;				/* => 32 MB		*/
+		case AMD_ID_LV640U_2:
+			if (addr[15] != AMD_ID_LV640U_3) {
+				info->flash_id = FLASH_UNKNOWN;
+			}
+			else {
+				info->flash_id += FLASH_AMLV640U;
+				info->sector_count = 128;
+				info->size = 0x01000000;
+			}
+			break;				/* => 16 MB		*/
 		default:
 			info->flash_id = FLASH_UNKNOWN;
 			break;
@@ -335,18 +357,6 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 		info->size = 0x00200000;
 		break;				/* => 2 MB		*/
 
-	case AMD_ID_LV160T:
-		info->flash_id += FLASH_AM160T;
-		info->sector_count = 35;
-		info->size = 0x00400000;
-		break;				/* => 4 MB		*/
-
-	case AMD_ID_LV160B:
-		info->flash_id += FLASH_AM160B;
-		info->sector_count = 35;
-		info->size = 0x00400000;
-		break;				/* => 4 MB		*/
-
 	case AMD_ID_LV320T:
 		info->flash_id += FLASH_AM320T;
 		info->sector_count = 71;
@@ -359,6 +369,19 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 		info->size = 0x00800000;
 		break;				/* => 8 MB		*/
 #endif	/* TQM8xxM */
+
+	case AMD_ID_LV160T:
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+
+	case AMD_ID_LV160B:
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+
 	default:
 		info->flash_id = FLASH_UNKNOWN;
 		return (0);			/* => no or unknown flash */
@@ -371,6 +394,8 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 		switch (info->flash_id & FLASH_TYPEMASK) {
 			/* only known types here - no default */
 		case FLASH_AMLV128U:
+		case FLASH_AMLV640U:
+		case FLASH_AMLV320U:
 			for (i = 0; i < info->sector_count; i++) {
 				info->start[i] = base;
 				base += 0x20000;
@@ -381,7 +406,6 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 # else	/* ! TQM8xxM */
 	case AMD_ID_LV400B:
 	case AMD_ID_LV800B:
-	case AMD_ID_LV160B:
 		/* set sector offsets for bottom boot block type	*/
 		info->start[0] = base + 0x00000000;
 		info->start[1] = base + 0x00008000;
@@ -393,7 +417,6 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 		break;
 	case AMD_ID_LV400T:
 	case AMD_ID_LV800T:
-	case AMD_ID_LV160T:
 		/* set sector offsets for top boot block type		*/
 		i = info->sector_count - 1;
 		info->start[i--] = base + info->size - 0x00008000;
@@ -428,6 +451,26 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 		}
 		break;
 #endif	/* TQM8xxM */
+	case AMD_ID_LV160B:
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00008000;
+		info->start[2] = base + 0x0000C000;
+		info->start[3] = base + 0x00010000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00020000) - 0x00060000;
+		}
+		break;
+	case AMD_ID_LV160T:
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00008000;
+		info->start[i--] = base + info->size - 0x0000C000;
+		info->start[i--] = base + info->size - 0x00010000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00020000;
+		}
+		break;
 	default:
 		return (0);
 		break;

board/trab/trab.c

@@ -298,8 +298,8 @@ int do_kbd (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 	return 0;
 }
 
-cmd_tbl_t U_BOOT_CMD(kbd) = MK_CMD_ENTRY(
- 	"kbd",	1,	1,	do_kbd,
+U_BOOT_CMD(
+ 	kbd,	1,	1,	do_kbd,
  	"kbd     - read keyboard status\n",
  	NULL
 );

board/w7o/cmd_vpd.c

@@ -56,8 +56,8 @@ int do_vpd (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 	return 1;
 }
 
-cmd_tbl_t U_BOOT_CMD(vpd) = MK_CMD_ENTRY(
-	  "vpd",	2,	1,	do_vpd,
+U_BOOT_CMD(
+	  vpd,	2,	1,	do_vpd,
 	  "vpd     - Read Vital Product Data\n",
 	  "[dev_addr]\n"
 	  "        - Read VPD Data from default address, or device address 'dev_addr'.\n"

common/cmd_autoscript.c

@@ -171,8 +171,8 @@ do_autoscript (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 }
 
 #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT)
-cmd_tbl_t U_BOOT_CMD(AUTOSCRIPT) = MK_CMD_ENTRY(
-	"autoscr", 2, 0,	do_autoscript,
+U_BOOT_CMD(
+	autoscr, 2, 0,	do_autoscript,
 	"autoscr - run script from memory\n",
 	"[addr] - run script starting at addr"
 	" - A valid autoscr header must be present\n"

common/cmd_bdinfo.c

@@ -172,8 +172,8 @@ static void print_str(const char *name, const char *str)
 
 /* -------------------------------------------------------------------- */
 
-cmd_tbl_t U_BOOT_CMD(BDINFO) =  MK_CMD_ENTRY(
-	"bdinfo",	1,	1,	do_bdinfo,
+U_BOOT_CMD(
+	bdinfo,	1,	1,	do_bdinfo,
 	"bdinfo  - print Board Info structure\n",
 	NULL
 );

common/cmd_bedbug.c

@@ -108,8 +108,8 @@ int do_bedbug_dis (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
   dis_last_len = len;
   return 0;
 } /* do_bedbug_dis */
-cmd_tbl_t U_BOOT_CMD(DIS) = MK_CMD_ENTRY(
-	"ds",      3,      1,      do_bedbug_dis,
+U_BOOT_CMD(
+	ds,      3,      1,      do_bedbug_dis,
 	"ds      - disassemble memory\n",
 	"ds <address> [# instructions]\n"
 );
@@ -165,8 +165,8 @@ int do_bedbug_asm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
   }
   return rcode;
 } /* do_bedbug_asm */
-cmd_tbl_t U_BOOT_CMD(ASM) = MK_CMD_ENTRY(
-	"as",      2,      0,      do_bedbug_asm,
+U_BOOT_CMD(
+	as,      2,      0,      do_bedbug_asm,
 	"as      - assemble memory\n",
 	"as <address>\n"
 );
@@ -184,8 +184,8 @@ int do_bedbug_break (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
     return 0;
 
 } /* do_bedbug_break */
-cmd_tbl_t U_BOOT_CMD(BREAK) = MK_CMD_ENTRY(
-	"break",      3,      0,      do_bedbug_break,
+U_BOOT_CMD(
+	break,      3,      0,      do_bedbug_break,
 	"break   - set or clear a breakpoint\n",
 	" - Set or clear a breakpoint\n"
 	"break <address> - Break at an address\n"
@@ -288,8 +288,8 @@ int do_bedbug_continue (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
   bug_ctx.stopped = 0;
   return 0;
 } /* do_bedbug_continue */
-cmd_tbl_t U_BOOT_CMD(CONTINUE) = MK_CMD_ENTRY(
-	"continue",      1,      0,      do_bedbug_continue,
+U_BOOT_CMD(
+	continue,      1,      0,      do_bedbug_continue,
 	"continue- continue from a breakpoint\n",
 	" - continue from a breakpoint.\n"
 );
@@ -320,8 +320,8 @@ int do_bedbug_step (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
   bug_ctx.stopped = 0;
   return 0;
 } /* do_bedbug_step */
-cmd_tbl_t U_BOOT_CMD(STEP) = MK_CMD_ENTRY(
-	"step",      1,      1,      do_bedbug_step,
+U_BOOT_CMD(
+	step,      1,      1,      do_bedbug_step,
 	"step    - single step execution.\n",
 	" - single step execution.\n"
 );
@@ -352,8 +352,8 @@ int do_bedbug_next (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
   bug_ctx.stopped = 0;
   return 0;
 } /* do_bedbug_next */
-cmd_tbl_t U_BOOT_CMD(NEXT) = MK_CMD_ENTRY(
-	"next",      1,      1,      do_bedbug_next,
+U_BOOT_CMD(
+	next,      1,      1,      do_bedbug_next,
 	"next    - single step execution, stepping over subroutines.\n",
 	" - single step execution, stepping over subroutines.\n"
 );
@@ -401,8 +401,8 @@ int do_bedbug_stack (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
   }
   return 0;
 } /* do_bedbug_stack */
-cmd_tbl_t U_BOOT_CMD(STACK) = MK_CMD_ENTRY(
-	"where",     1,      1,      do_bedbug_stack,
+U_BOOT_CMD(
+	where,     1,      1,      do_bedbug_stack,
 	"where   - Print the running stack.\n",
 	" - Print the running stack.\n"
 );
@@ -424,8 +424,8 @@ int do_bedbug_rdump (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
   show_regs( bug_ctx.regs );
   return 0;
 } /* do_bedbug_rdump */
-cmd_tbl_t U_BOOT_CMD(RDUMP) = MK_CMD_ENTRY(
-	"rdump",     1,      1,      do_bedbug_rdump,
+U_BOOT_CMD(
+	rdump,     1,      1,      do_bedbug_rdump,
 	"rdump   - Show registers.\n",
 	" - Show registers.\n"
 );

common/cmd_bmp.c

@@ -1,6 +1,6 @@
 /*
  * (C) Copyright 2002
- * Dtlev Zundel, DENX Software Engineering, dzu@denx.de.
+ * Detlev Zundel, DENX Software Engineering, dzu@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -73,8 +73,8 @@ int do_bmp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	}
 }
 
-cmd_tbl_t U_BOOT_CMD(BMP) = MK_CMD_ENTRY(
-	"bmp",	3,	1,	do_bmp,
+U_BOOT_CMD(
+	bmp,	3,	1,	do_bmp,
 	"bmp     - manipulate BMP image data\n",
 	"info <imageAddr>    - display image info\n"
 	"bmp display <imageAddr> - display image\n"

common/cmd_boot.c

@@ -59,8 +59,8 @@ int do_go (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 /* -------------------------------------------------------------------- */
 
-cmd_tbl_t U_BOOT_CMD(GO) = MK_CMD_ENTRY(
-	"go", CFG_MAXARGS, 1,	do_go,
+U_BOOT_CMD(
+	go, CFG_MAXARGS, 1,	do_go,
 	"go      - start application at address 'addr'\n",
 	"addr [arg ...]\n    - start application at address 'addr'\n"
 	"      passing 'arg' as arguments\n"
@@ -68,8 +68,8 @@ cmd_tbl_t U_BOOT_CMD(GO) = MK_CMD_ENTRY(
 
 extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
 
-cmd_tbl_t U_BOOT_CMD(RESET) = MK_CMD_ENTRY(
-	"reset", 1, 0,	do_reset,
+U_BOOT_CMD(
+	reset, 1, 0,	do_reset,
 	"reset   - Perform RESET of the CPU\n",
 	NULL
 );

common/cmd_bootm.c

@@ -381,8 +381,8 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	return 1;
 }
 
-cmd_tbl_t U_BOOT_CMD(BOOTM) =  MK_CMD_ENTRY(
- 	"bootm",	CFG_MAXARGS,	1,	do_bootm,
+U_BOOT_CMD(
+ 	bootm,	CFG_MAXARGS,	1,	do_bootm,
  	"bootm   - boot application image from memory\n",
  	"[addr [arg ...]]\n    - boot application image stored in memory\n"
  	"        passing arguments 'arg ...'; when booting a Linux kernel,\n"
@@ -872,15 +872,15 @@ int do_bootd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	return rcode;
 }
 
-cmd_tbl_t U_BOOT_CMD(BOOT) = MK_CMD_ENTRY(
- 	"boot",	1,	1,	do_bootd,
+U_BOOT_CMD(
+ 	boot,	1,	1,	do_bootd,
  	"boot    - boot default, i.e., run 'bootcmd'\n",
 	NULL
 );
 
 /* keep old command name "bootd" for backward compatibility */
-cmd_tbl_t U_BOOT_CMD(BOOTD) = MK_CMD_ENTRY(
- 	"bootd", 1,	1,	do_bootd,
+U_BOOT_CMD(
+ 	bootd, 1,	1,	do_bootd,
  	"bootd   - boot default, i.e., run 'bootcmd'\n",
 	NULL
 );
@@ -945,8 +945,9 @@ static int image_info (ulong addr)
 	printf ("OK\n");
 	return 0;
 }
-cmd_tbl_t U_BOOT_CMD(IMINFO) = MK_CMD_ENTRY(
-	"iminfo",	CFG_MAXARGS,	1,	do_iminfo,
+
+U_BOOT_CMD(
+	iminfo,	CFG_MAXARGS,	1,	do_iminfo,
 	"iminfo  - print header information for application image\n",
 	"addr [addr ...]\n"
 	"    - print header information for application image starting at\n"

common/cmd_cache.c

@@ -95,15 +95,15 @@ static int on_off (const char *s)
 }
 
 
-cmd_tbl_t U_BOOT_CMD(ICACHE) = MK_CMD_ENTRY(
-	"icache",   2,   1,     do_icache,
+U_BOOT_CMD(
+	icache,   2,   1,     do_icache,
 	"icache  - enable or disable instruction cache\n",
 	"[on, off]\n"
 	"    - enable or disable instruction cache\n"
 );
 
-cmd_tbl_t U_BOOT_CMD(DCACHE) = MK_CMD_ENTRY(
-	"dcache",   2,   1,     do_dcache,
+U_BOOT_CMD(
+	dcache,   2,   1,     do_dcache,
 	"dcache  - enable or disable data cache\n",
 	"[on, off]\n"
 	"    - enable or disable data (writethrough) cache\n"

common/cmd_console.c

@@ -62,8 +62,8 @@ int do_coninfo (cmd_tbl_t * cmd, int flag, int argc, char *argv[])
 
 /***************************************************/
 
-cmd_tbl_t U_BOOT_CMD(CONINFO) = MK_CMD_ENTRY(
-	"coninfo",	3,	1,	do_coninfo,
+U_BOOT_CMD(
+	coninfo,	3,	1,	do_coninfo,
 	"coninfo - print console devices and informations\n",
 	""
 );

common/cmd_date.c

@@ -191,8 +191,8 @@ int mk_date (char *datestr, struct rtc_time *tmp)
 
 /***************************************************/
 
-cmd_tbl_t U_BOOT_CMD(DATE) = MK_CMD_ENTRY(
-	"date",	2,	1,	do_date,
+U_BOOT_CMD(
+	date,	2,	1,	do_date,
 	"date    - get/set/reset date & time\n",
 	"[MMDDhhmm[[CC]YY][.ss]]\ndate reset\n"
 	"  - without arguments: print date & time\n"

common/cmd_dcr.c

@@ -106,13 +106,13 @@ int do_setdcr ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 /***************************************************/
 
-cmd_tbl_t U_BOOT_CMD(GETDCR) = MK_CMD_ENTRY(
-	"getdcr",	2,	1,	do_getdcr,
+U_BOOT_CMD(
+	getdcr,	2,	1,	do_getdcr,
 	"getdcr  - Get an IBM PPC 4xx DCR's value\n",
 	"dcrn - return a DCR's value.\n"
 );
-cmd_tbl_t U_BOOT_CMD(SETDCR) = MK_CMD_ENTRY(
-	"setdcr",	2,	1,	do_setdcr,
+U_BOOT_CMD(
+	setdcr,	2,	1,	do_setdcr,
 	"setdcr  - Set an IBM PPC 4xx DCR's value\n",
 	"dcrn - set a DCR's value.\n"
 );

common/cmd_diag.c

@@ -66,8 +66,8 @@ int do_diag (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 }
 /***************************************************/
 
-cmd_tbl_t U_BOOT_CMD(DIAG) = MK_CMD_ENTRY(
-	"diag",	CFG_MAXARGS,	0,	do_diag,
+U_BOOT_CMD(
+	diag,	CFG_MAXARGS,	0,	do_diag,
 	"diag    - perform board diagnostics\n",
 	     "    - print list of available tests\n"
 	"diag [test1 [test2]]\n"

common/cmd_doc.c

@@ -170,8 +170,8 @@ int do_doc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	return rcode;
     }
 }
-cmd_tbl_t U_BOOT_CMD(DOC) = MK_CMD_ENTRY(
-	"doc",	5,	1,	do_doc,
+U_BOOT_CMD(
+	doc,	5,	1,	do_doc,
 	"doc     - Disk-On-Chip sub-system\n",
 	"info  - show available DOC devices\n"
 	"doc device [dev] - show or set current device\n"
@@ -284,8 +284,8 @@ int do_docboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	return rcode;
 }
 
-cmd_tbl_t U_BOOT_CMD(DOCBOOT) = MK_CMD_ENTRY(
-	"docboot",	4,	1,	do_docboot,
+U_BOOT_CMD(
+	docboot,	4,	1,	do_docboot,
 	"docboot - boot from DOC device\n",
 	"loadAddr dev\n"
 );

common/cmd_dtt.c

@@ -47,8 +47,8 @@ int do_dtt (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 
 /***************************************************/
 
-cmd_tbl_t U_BOOT_CMD(DTT) = MK_CMD_ENTRY(
-	  "dtt",	1,	1,	do_dtt,
+U_BOOT_CMD(
+	  dtt,	1,	1,	do_dtt,
 	  "dtt     - Digital Thermometer and Themostat\n",
 	  "        - Read temperature from digital thermometer and thermostat.\n"
 );

common/cmd_eeprom.c

@@ -376,16 +376,16 @@ void eeprom_init  (void)
 #if (CONFIG_COMMANDS & CFG_CMD_EEPROM)
 
 #ifdef CFG_I2C_MULTI_EEPROMS
-cmd_tbl_t U_BOOT_CMD(EEPROM) = MK_CMD_ENTRY(
-	"eeprom",	6,	1,	do_eeprom,
+U_BOOT_CMD(
+	eeprom,	6,	1,	do_eeprom,
 	"eeprom  - EEPROM sub-system\n",
 	"read  devaddr addr off cnt\n"
 	"eeprom write devaddr addr off cnt\n"
 	"       - read/write `cnt' bytes from `devaddr` EEPROM at offset `off'\n"
 );
 #else /* One EEPROM */
-cmd_tbl_t U_BOOT_CMD(EEPROM) = MK_CMD_ENTRY(
-	"eeprom",	5,	1,	do_eeprom,
+U_BOOT_CMD(
+	eeprom,	5,	1,	do_eeprom,
 	"eeprom  - EEPROM sub-system\n",
 	"read  addr off cnt\n"
 	"eeprom write addr off cnt\n"

common/cmd_elf.c

@@ -321,14 +321,14 @@ unsigned long load_elf_image (unsigned long addr)
 }
 
 /* ====================================================================== */
-cmd_tbl_t U_BOOT_CMD(BOOTELF) = MK_CMD_ENTRY(
-	"bootelf",      2,      0,      do_bootelf,
+U_BOOT_CMD(
+	bootelf,      2,      0,      do_bootelf,
 	"bootelf - Boot from an ELF image in memory\n",
 	" [address] - load address of ELF image.\n"
 );
 
-cmd_tbl_t U_BOOT_CMD(BOOTVX) = MK_CMD_ENTRY(
-	"bootvx",      2,      0,      do_bootvx,
+U_BOOT_CMD(
+	bootvx,      2,      0,      do_bootvx,
 	"bootvx  - Boot vxWorks from an ELF image\n",
 	" [address] - load address of vxWorks ELF image.\n"
 );

common/cmd_fat.c

@@ -62,8 +62,8 @@ int do_fat_fsload (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	return size;
 }
 
-cmd_tbl_t U_BOOT_CMD(FATLOAD) = MK_CMD_ENTRY(
-	"fatload",	4,	0,	do_fat_fsload,
+U_BOOT_CMD(
+	fatload,	4,	0,	do_fat_fsload,
 	"fatload - load binary file from a dos filesystem\n",
 	"[ off ] [ filename ]\n"
 	"    - load binary file from dos filesystem\n"
@@ -83,8 +83,8 @@ int do_fat_ls (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	return (ret);
 }
 
-cmd_tbl_t U_BOOT_CMD(FATLS) = MK_CMD_ENTRY(
-	"fatls",	2,	1,	do_fat_ls,
+U_BOOT_CMD(
+	fatls,	2,	1,	do_fat_ls,
 	"fatls   - list files in a directory (default /)\n",
 	"[ directory ]\n"
 	"    - list files in a directory\n"
@@ -101,8 +101,8 @@ int do_fat_fsinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	return (ret);
 }
 
-cmd_tbl_t U_BOOT_CMD(FATINFO) = MK_CMD_ENTRY(
-	"fatinfo",	1,	1,	do_fat_fsinfo,
+U_BOOT_CMD(
+	fatinfo,	1,	1,	do_fat_fsinfo,
 	"fatinfo - print information about filesystem\n",
 	"\n"
 	"    - print information about filesystem\n"

common/cmd_fdc.c

@@ -888,8 +888,8 @@ int do_fdcboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 #if (CONFIG_COMMANDS & CFG_CMD_FDC)
 
-cmd_tbl_t U_BOOT_CMD(FDC) = MK_CMD_ENTRY(
-	"fdcboot",	3,	1,	do_fdcboot,
+U_BOOT_CMD(
+	fdcboot,	3,	1,	do_fdcboot,
 	"fdcboot - boot from floppy device\n",
 	"loadAddr drive\n"
 );

common/cmd_fdos.c

@@ -142,14 +142,14 @@ int do_fdosls(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
     return (dos_dir ());
 }
 
-cmd_tbl_t U_BOOT_CMD(FDOS_BOOT) = MK_CMD_ENTRY(
-	"fdosboot",	3,	0,	do_fdosboot,
+U_BOOT_CMD(
+	fdosboot,	3,	0,	do_fdosboot,
 	"fdosboot- boot from a dos floppy file\n",
 	"[loadAddr] [filename]\n"
 );
 
-cmd_tbl_t U_BOOT_CMD(FDOS_LS) = MK_CMD_ENTRY(
-	"fdosls",	2,	0,	do_fdosls,
+U_BOOT_CMD(
+	fdosls,	2,	0,	do_fdosls,
 	"fdosls  - list files in a directory\n",
 	"[directory]\n"
 );

common/cmd_flash.c

@@ -440,15 +440,15 @@ int flash_sect_protect (int p, ulong addr_first, ulong addr_last)
 
 /**************************************************/
 
-cmd_tbl_t U_BOOT_CMD(FLINFO) = MK_CMD_ENTRY(
-	"flinfo",    2,    1,    do_flinfo,
+U_BOOT_CMD(
+	flinfo,    2,    1,    do_flinfo,
 	"flinfo  - print FLASH memory information\n",
 	"\n    - print information for all FLASH memory banks\n"
 	"flinfo N\n    - print information for FLASH memory bank # N\n"
 );
 
-cmd_tbl_t U_BOOT_CMD(ERASE) = MK_CMD_ENTRY(
-	"erase",   3,   1,  do_flerase,
+U_BOOT_CMD(
+	erase,   3,   1,  do_flerase,
 	"erase   - erase FLASH memory\n",
 	"start end\n"
 	"    - erase FLASH from addr 'start' to addr 'end'\n"
@@ -457,8 +457,8 @@ cmd_tbl_t U_BOOT_CMD(ERASE) = MK_CMD_ENTRY(
 	"erase all\n    - erase all FLASH banks\n"
 );
 
-cmd_tbl_t U_BOOT_CMD(PROTECT) = MK_CMD_ENTRY(
-	"protect",  4,  1,   do_protect,
+U_BOOT_CMD(
+	protect,  4,  1,   do_protect,
 	"protect - enable or disable FLASH write protection\n",
 	"on  start end\n"
 	"    - protect FLASH from addr 'start' to addr 'end'\n"

common/cmd_fpga.c

@@ -154,8 +154,8 @@ static int fpga_get_op( char *opstr )
 	return op;
 }
 
-cmd_tbl_t U_BOOT_CMD(FPGA) = MK_CMD_ENTRY(
-	"fpga",    6,     1,     do_fpga,
+U_BOOT_CMD(
+	fpga,    6,     1,     do_fpga,
 	"fpga   - loadable FPGA image support\n",
 	"fpga [operation type] [device number] [image address] [image size]\n"
 	"fpga operations:\n"

common/cmd_i2c.c

@@ -867,38 +867,38 @@ int do_sdram  ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 /***************************************************/
 
-cmd_tbl_t U_BOOT_CMD(IMD) = MK_CMD_ENTRY(
-	"imd",	4,	1,	do_i2c_md,		\
+U_BOOT_CMD(
+	imd,	4,	1,	do_i2c_md,		\
 	"imd     - i2c memory display\n",				\
 	"chip address[.0, .1, .2] [# of objects]\n    - i2c memory display\n" \
 );
 
-cmd_tbl_t U_BOOT_CMD(IMM) = MK_CMD_ENTRY(
- 	"imm",	3,	1,	do_i2c_mm,
+U_BOOT_CMD(
+ 	imm,	3,	1,	do_i2c_mm,
 	"imm     - i2c memory modify (auto-incrementing)\n",
 	"chip address[.0, .1, .2]\n"
 	"    - memory modify, auto increment address\n"
 );
-cmd_tbl_t U_BOOT_CMD(INM) = MK_CMD_ENTRY(
-	"inm",	3,	1,	do_i2c_nm,
+U_BOOT_CMD(
+	inm,	3,	1,	do_i2c_nm,
 	"inm     - memory modify (constant address)\n",
 	"chip address[.0, .1, .2]\n    - memory modify, read and keep address\n"
 );
 
-cmd_tbl_t U_BOOT_CMD(IMW) = MK_CMD_ENTRY(
-	"imw",	5,	1,	do_i2c_mw,
+U_BOOT_CMD(
+	imw,	5,	1,	do_i2c_mw,
 	"imw     - memory write (fill)\n",
 	"chip address[.0, .1, .2] value [count]\n    - memory write (fill)\n"
 );
 
-cmd_tbl_t U_BOOT_CMD(ICRC) = MK_CMD_ENTRY(
-	"icrc32",	5,	1,	do_i2c_crc,
+U_BOOT_CMD(
+	icrc32,	5,	1,	do_i2c_crc,
 	"icrc32  - checksum calculation\n",
 	"chip address[.0, .1, .2] count\n    - compute CRC32 checksum\n"
 );
 
-cmd_tbl_t U_BOOT_CMD(IPROBE) = MK_CMD_ENTRY(
-	"iprobe",	1,	1,	do_i2c_probe,
+U_BOOT_CMD(
+	iprobe,	1,	1,	do_i2c_probe,
 	"iprobe  - probe to discover valid I2C chip addresses\n",
 	"\n    -discover valid I2C chip addresses\n"
 );
@@ -906,16 +906,16 @@ cmd_tbl_t U_BOOT_CMD(IPROBE) = MK_CMD_ENTRY(
 /*
  * Require full name for "iloop" because it is an infinite loop!
  */
-cmd_tbl_t U_BOOT_CMD(ILOOP) = MK_CMD_ENTRY(
-	"iloop",	5,	1,	do_i2c_loop,
+U_BOOT_CMD(
+	iloop,	5,	1,	do_i2c_loop,
 	"iloop   - infinite loop on address range\n",
 	"chip address[.0, .1, .2] [# of objects]\n"
 	"    - loop, reading a set of addresses\n"
 );
 
 #if (CONFIG_COMMANDS & CFG_CMD_SDRAM)
-cmd_tbl_t U_BOOT_CMD(ISDRAM) = MK_CMD_ENTRY(
-	"isdram",	2,	1,	do_sdram,
+U_BOOT_CMD(
+	isdram,	2,	1,	do_sdram,
 	"isdram  - print SDRAM configuration information\n",
 	"chip\n    - print SDRAM configuration information\n"
 	"      (valid chip values 50..57)\n"

common/cmd_ide.c

@@ -1810,8 +1810,8 @@ ulong atapi_read (int device, ulong blknr, ulong blkcnt, ulong *buffer)
 
 #endif /* CONFIG_ATAPI */
 
-cmd_tbl_t U_BOOT_CMD(IDE) = MK_CMD_ENTRY(
-	"ide",  5,  1,  do_ide,
+U_BOOT_CMD(
+	ide,  5,  1,  do_ide,
 	"ide     - IDE sub-system\n",
 	"reset - reset IDE controller\n"
 	"ide info  - show available IDE devices\n"
@@ -1823,8 +1823,8 @@ cmd_tbl_t U_BOOT_CMD(IDE) = MK_CMD_ENTRY(
 	"    to/from memory address `addr'\n"
 );
 
-cmd_tbl_t U_BOOT_CMD(DISK) = MK_CMD_ENTRY(
-	"diskboot",	3,	1,	do_diskboot,
+U_BOOT_CMD(
+	diskboot,	3,	1,	do_diskboot,
 	"diskboot- boot from IDE device\n",
 	"loadAddr dev:part\n"
 );

common/cmd_immap.c

@@ -594,106 +594,106 @@ do_mccinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 /***************************************************/
 
-cmd_tbl_t U_BOOT_CMD(SIUINFO) = MK_CMD_ENTRY(
-	"siuinfo",	1,	1,	do_siuinfo,
+U_BOOT_CMD(
+	siuinfo,	1,	1,	do_siuinfo,
 	"siuinfo - print System Interface Unit (SIU) registers\n",
 	NULL
 );
 
-cmd_tbl_t U_BOOT_CMD(MEMCINFO) = MK_CMD_ENTRY(
-	"memcinfo",	1,	1,	do_memcinfo,
+U_BOOT_CMD(
+	memcinfo,	1,	1,	do_memcinfo,
 	"memcinfo- print Memory Controller registers\n",
 	NULL
 );
 
-cmd_tbl_t U_BOOT_CMD(SITINFO) = MK_CMD_ENTRY(
-	"sitinfo",	1,	1,	do_sitinfo,
+U_BOOT_CMD(
+	sitinfo,	1,	1,	do_sitinfo,
 	"sitinfo - print System Integration Timers (SIT) registers\n",
 	NULL
 );
 
 #ifdef CONFIG_8260
-cmd_tbl_t U_BOOT_CMD(ICINFO) = MK_CMD_ENTRY(
-	"icinfo",	1,	1,	do_icinfo,
+U_BOOT_CMD(
+	icinfo,	1,	1,	do_icinfo,
 	"icinfo  - print Interrupt Controller registers\n",
 	NULL
 );
 #endif
 
-cmd_tbl_t U_BOOT_CMD(CARINFO) = MK_CMD_ENTRY(
-	"carinfo",	1,	1,	do_carinfo,
+U_BOOT_CMD(
+	carinfo,	1,	1,	do_carinfo,
 	"carinfo - print Clocks and Reset registers\n",
 	NULL
 );
 
-cmd_tbl_t U_BOOT_CMD(IOPINFO) = MK_CMD_ENTRY(
-	"iopinfo",	1,	1,	do_iopinfo,
+U_BOOT_CMD(
+	iopinfo,	1,	1,	do_iopinfo,
 	"iopinfo - print I/O Port registers\n",
 	NULL
 );
 
-cmd_tbl_t U_BOOT_CMD(IOPSET) = 	MK_CMD_ENTRY(
-	"iopset",	5,	0,	do_iopset,
+U_BOOT_CMD(
+	iopset,	5,	0,	do_iopset,
 	"iopset - set I/O Port registers\n",
 	"PORT PIN CMD VALUE\nPORT: A-D, PIN: 0-31, CMD: [dat|dir|odr|sor], VALUE: 0|1"
 );
 
-cmd_tbl_t U_BOOT_CMD(DMAINFO) = MK_CMD_ENTRY(
-	"dmainfo",	1,	1,	do_dmainfo,
+U_BOOT_CMD(
+	dmainfo,	1,	1,	do_dmainfo,
 	"dmainfo - print SDMA/IDMA registers\n",
 	NULL
 );
 
-cmd_tbl_t U_BOOT_CMD(FCCINFO) = MK_CMD_ENTRY(
-	"fccinfo",	1,	1,	do_fccinfo,
+U_BOOT_CMD(
+	fccinfo,	1,	1,	do_fccinfo,
 	"fccinfo - print FCC registers\n",
 	NULL
 );
 
-cmd_tbl_t U_BOOT_CMD(BRGINFO) = MK_CMD_ENTRY(
-	"brginfo",	1,	1,	do_brginfo,
+U_BOOT_CMD(
+	brginfo,	1,	1,	do_brginfo,
 	"brginfo - print Baud Rate Generator (BRG) registers\n",
 	NULL
 );
 
-cmd_tbl_t U_BOOT_CMD(I2CINFO) = MK_CMD_ENTRY(
-	"i2cinfo",	1,	1,	do_i2cinfo,
+U_BOOT_CMD(
+	i2cinfo,	1,	1,	do_i2cinfo,
 	"i2cinfo - print I2C registers\n",
 	NULL
 );
 
-cmd_tbl_t U_BOOT_CMD(SCCINFO) = MK_CMD_ENTRY(
-	"sccinfo",	1,	1,	do_sccinfo,
+U_BOOT_CMD(
+	sccinfo,	1,	1,	do_sccinfo,
 	"sccinfo - print SCC registers\n",
 	NULL
 );
 
-cmd_tbl_t U_BOOT_CMD(SMCINFO) = MK_CMD_ENTRY(
-	"smcinfo",	1,	1,	do_smcinfo,
+U_BOOT_CMD(
+	smcinfo,	1,	1,	do_smcinfo,
 	"smcinfo - print SMC registers\n",
 	NULL
 );
 
-cmd_tbl_t U_BOOT_CMD(SPIINFO) = MK_CMD_ENTRY(
-	"spiinfo",	1,	1,	do_spiinfo,
+U_BOOT_CMD(
+	spiinfo,	1,	1,	do_spiinfo,
 	"spiinfo - print Serial Peripheral Interface (SPI) registers\n",
 	NULL
 );
 
-cmd_tbl_t U_BOOT_CMD(MUXINFO) = MK_CMD_ENTRY(
-	"muxinfo",	1,	1,	do_muxinfo,
+U_BOOT_CMD(
+	muxinfo,	1,	1,	do_muxinfo,
 	"muxinfo - print CPM Multiplexing registers\n",
 	NULL
 );
 
-cmd_tbl_t U_BOOT_CMD(SIINFO) = MK_CMD_ENTRY(
-	"siinfo",	1,	1,	do_siinfo,
+U_BOOT_CMD(
+	siinfo,	1,	1,	do_siinfo,
 	"siinfo  - print Serial Interface (SI) registers\n",
 	NULL
 );
 
-cmd_tbl_t U_BOOT_CMD(MCCINFO) = MK_CMD_ENTRY(
-	"mccinfo",	1,	1,	do_mccinfo,
+U_BOOT_CMD(
+	mccinfo,	1,	1,	do_mccinfo,
 	"mccinfo - print MCC registers\n",
 	NULL
 );

common/cmd_jffs2.c

@@ -186,29 +186,29 @@ do_jffs2_chpart(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 /***************************************************/
 
-cmd_tbl_t U_BOOT_CMD(JFFS2_FSLOAD) = MK_CMD_ENTRY(
-	"fsload",	3,	0,	do_jffs2_fsload,
+U_BOOT_CMD(
+	fsload,	3,	0,	do_jffs2_fsload,
 	"fsload  - load binary file from a filesystem image\n",
 	"[ off ] [ filename ]\n"
 	"    - load binary file from flash bank\n"
 	"      with offset 'off'\n"
 );
 
-cmd_tbl_t U_BOOT_CMD(JFFS2_FSINFO) = MK_CMD_ENTRY(
-	"fsinfo",	1,	1,	do_jffs2_fsinfo,
+U_BOOT_CMD(
+	fsinfo,	1,	1,	do_jffs2_fsinfo,
 	"fsinfo  - print information about filesystems\n",
 	"    - print information about filesystems\n"
 );
 
-cmd_tbl_t U_BOOT_CMD(JFFS2_LS) = MK_CMD_ENTRY(
-	"ls",	2,	1,	do_jffs2_ls,
+U_BOOT_CMD(
+	ls,	2,	1,	do_jffs2_ls,
 	"ls      - list files in a directory (default /)\n",
 	"[ directory ]\n"
 	"    - list files in a directory.\n"
 );
 
-cmd_tbl_t U_BOOT_CMD(JFFS2_CHPART) = MK_CMD_ENTRY(
-	"chpart",	2,	0,	do_jffs2_chpart,
+U_BOOT_CMD(
+	chpart,	2,	0,	do_jffs2_chpart,
 	"chpart  - change active partition\n",
 	"    - change active partition\n"
 );

common/cmd_load.c

@@ -971,8 +971,8 @@ START:
 #if (CONFIG_COMMANDS & CFG_CMD_LOADS)
 
 #ifdef	CFG_LOADS_BAUD_CHANGE
-cmd_tbl_t U_BOOT_CMD(LOADS) =  MK_CMD_ENTRY(
-	"loads", 3, 0,	do_load_serial,
+U_BOOT_CMD(
+	loads, 3, 0,	do_load_serial,
 	"loads   - load S-Record file over serial line\n",
 	"[ off ] [ baud ]\n"
 	"    - load S-Record file over serial line"
@@ -980,8 +980,8 @@ cmd_tbl_t U_BOOT_CMD(LOADS) =  MK_CMD_ENTRY(
 );
 
 #else	/* ! CFG_LOADS_BAUD_CHANGE */
-cmd_tbl_t U_BOOT_CMD(LOADS) =  MK_CMD_ENTRY(
-	"loads", 2, 0,	do_load_serial,
+U_BOOT_CMD(
+	loads, 2, 0,	do_load_serial,
 	"loads   - load S-Record file over serial line\n",
 	"[ off ]\n"
 	"    - load S-Record file over serial line with offset 'off'\n"
@@ -995,16 +995,16 @@ cmd_tbl_t U_BOOT_CMD(LOADS) =  MK_CMD_ENTRY(
 
 #if (CONFIG_COMMANDS & CFG_CMD_SAVES)
 #ifdef	CFG_LOADS_BAUD_CHANGE
-cmd_tbl_t U_BOOT_CMD(SAVES) = MK_CMD_ENTRY(
-	"saves", 4, 0,	do_save_serial,
+U_BOOT_CMD(
+	saves, 4, 0,	do_save_serial,
 	"saves   - save S-Record file over serial line\n",
 	"[ off ] [size] [ baud ]\n"
 	"    - save S-Record file over serial line"
 	" with offset 'off', size 'size' and baudrate 'baud'\n"
 );
 #else	/* ! CFG_LOADS_BAUD_CHANGE */
-cmd_tbl_t U_BOOT_CMD(SAVES) = MK_CMD_ENTRY(
-	"saves", 3, 0,	do_save_serial,
+U_BOOT_CMD(
+	saves, 3, 0,	do_save_serial,
 	"saves   - save S-Record file over serial line\n",
 	"[ off ] [size]\n"
 	"    - save S-Record file over serial line with offset 'off' and size 'size'\n"
@@ -1015,8 +1015,8 @@ cmd_tbl_t U_BOOT_CMD(SAVES) = MK_CMD_ENTRY(
 
 
 #if (CONFIG_COMMANDS & CFG_CMD_LOADB)
-cmd_tbl_t U_BOOT_CMD(LOADB) = MK_CMD_ENTRY(
-	"loadb", 3, 0,	do_load_serial_bin,
+U_BOOT_CMD(
+	loadb, 3, 0,	do_load_serial_bin,
 	"loadb   - load binary file over serial line (kermit mode)\n",
 	"[ off ] [ baud ]\n"
 	"    - load binary file over serial line"
@@ -1047,10 +1047,10 @@ int do_hwflow (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 /* -------------------------------------------------------------------- */
 
-cmd_tbl_t U_BOOT_CMD(HWFLOW) = MK_CMD_ENTRY(
-	"hwflow [on|off]", 2, 0,	do_hwflow,
+U_BOOT_CMD(
+	hwflow, 2, 0,	do_hwflow,
 	"hwflow  - turn the harwdare flow control on/off\n",
-	"\n - change RTS/CTS hardware flow control over serial line\n"
+	"[on|off]\n - change RTS/CTS hardware flow control over serial line\n"
 );
 
 #endif /* CFG_CMD_HWFLOW */

common/cmd_log.c

@@ -74,22 +74,26 @@ static unsigned long *ext_logged_chars;
 void logbuff_init_ptrs (void)
 {
 	DECLARE_GLOBAL_DATA_PTR;
+	unsigned long *ext_tag;
 	char *s;
 
 	log_buf = (unsigned char *)(gd->bd->bi_memsize-LOGBUFF_LEN);
-	ext_log_start = (unsigned long *)(log_buf)-3;
+	ext_tag = (unsigned long *)(log_buf)-4;
+ 	ext_log_start = (unsigned long *)(log_buf)-3;
 	ext_log_size = (unsigned long *)(log_buf)-2;
 	ext_logged_chars = (unsigned long *)(log_buf)-1;
 #ifdef CONFIG_POST
 	/* The post routines have setup the word so we can simply test it */
- 	if (post_word_load () & POST_POWERON) {
+ 	if ((post_word_load () & 0xffff) == POST_POWERON) {
  		logged_chars = log_size = log_start = 0;
+		*ext_tag = LOGBUFF_MAGIC;
  	}
 #else
 	/* No post routines, so we do our own checking                    */
  	if (post_word_load () != LOGBUFF_MAGIC) {
  		logged_chars = log_size = log_start = 0;
 		post_word_store (LOGBUFF_MAGIC);
+		*ext_tag = LOGBUFF_MAGIC;
  	}
 #endif
 	/* Initialize default loglevel if present */
@@ -162,12 +166,8 @@ int do_log (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	if (strcmp(argv[1],"append") == 0) {
 		/* Log concatenation of all arguments separated by spaces */
 		for (i=2; i<argc; i++) {
-			if (i<argc-1) {
-				logbuff_printk (argv[i]);
-				logbuff_putc (' ');
-			} else {
-				logbuff_puts (argv[i]);
-			}
+			logbuff_printk (argv[i]);
+			logbuff_putc ((i<argc-1) ? ' ' : '\n');
 		}
 		return 0;
 	}
@@ -202,10 +202,10 @@ int do_log (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	}
 }
 #if defined(CONFIG_LOGBUFFER)
-cmd_tbl_t U_BOOT_CMD(LOG) = MK_CMD_ENTRY(
-	"log",     255,	1,	do_log,
+U_BOOT_CMD(
+	log,     255,	1,	do_log,
 	"log     - manipulate logbuffer\n",
-	"log info   - show pointer details\n"
+	"info   - show pointer details\n"
 	"log reset  - clear contents\n"
 	"log show   - show contents\n"
 	"log append <msg> - append <msg> to the logbuffer\n"

common/cmd_mem.c

@@ -963,66 +963,66 @@ int do_mem_crc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 /**************************************************/
 #if (CONFIG_COMMANDS & CFG_CMD_MEMORY)
-cmd_tbl_t U_BOOT_CMD(MD) = MK_CMD_ENTRY(
-	"md",     3,     1,      do_mem_md,
+U_BOOT_CMD(
+	md,     3,     1,      do_mem_md,
 	"md      - memory display\n",
 	"[.b, .w, .l] address [# of objects]\n    - memory display\n"
 );
 
 
-cmd_tbl_t U_BOOT_CMD(MM) = MK_CMD_ENTRY(
-	"mm",     2,      1,       do_mem_mm,
+U_BOOT_CMD(
+	mm,     2,      1,       do_mem_mm,
 	"mm      - memory modify (auto-incrementing)\n",
 	"[.b, .w, .l] address\n" "    - memory modify, auto increment address\n"
 );
 
 
-cmd_tbl_t U_BOOT_CMD(NM) = MK_CMD_ENTRY(
-	"nm",     2,	    1,     	do_mem_nm,
+U_BOOT_CMD(
+	nm,     2,	    1,     	do_mem_nm,
 	"nm      - memory modify (constant address)\n",
 	"[.b, .w, .l] address\n    - memory modify, read and keep address\n"
 );
 
-cmd_tbl_t U_BOOT_CMD(MW) = MK_CMD_ENTRY(
-	"mw",    4,    1,     do_mem_mw,
+U_BOOT_CMD(
+	mw,    4,    1,     do_mem_mw,
 	"mw      - memory write (fill)\n",
 	"[.b, .w, .l] address value [count]\n    - write memory\n"
 );
 
-cmd_tbl_t U_BOOT_CMD(CP) = MK_CMD_ENTRY(
-	"cp",    4,    1,    do_mem_cp,
+U_BOOT_CMD(
+	cp,    4,    1,    do_mem_cp,
 	"cp      - memory copy\n",
 	"[.b, .w, .l] source target count\n    - copy memory\n"
 );
 
-cmd_tbl_t U_BOOT_CMD(CMP) = MK_CMD_ENTRY(
-	"cmp",    4,     1,     do_mem_cmp,
+U_BOOT_CMD(
+	cmp,    4,     1,     do_mem_cmp,
 	"cmp     - memory compare\n",
 	"[.b, .w, .l] addr1 addr2 count\n    - compare memory\n"
 );
 
-cmd_tbl_t U_BOOT_CMD(CRC32) = MK_CMD_ENTRY(
-	"crc32",    4,    1,     do_mem_crc,
+U_BOOT_CMD(
+	crc32,    4,    1,     do_mem_crc,
 	"crc32   - checksum calculation\n",
 	"address count [addr]\n    - compute CRC32 checksum [save at addr]\n"
 );
 
-cmd_tbl_t U_BOOT_CMD(BASE) = MK_CMD_ENTRY(
-	"base",    2,    1,     do_mem_base,
+U_BOOT_CMD(
+	base,    2,    1,     do_mem_base,
 	"base    - print or set address offset\n",
 	"\n    - print address offset for memory commands\n"
 	"base off\n    - set address offset for memory commands to 'off'\n"
 );
 
-cmd_tbl_t U_BOOT_CMD(LOOP) = MK_CMD_ENTRY(
-	"loop",    3,    1,    do_mem_loop,
+U_BOOT_CMD(
+	loop,    3,    1,    do_mem_loop,
 	"loop    - infinite loop on address range\n",
 	"[.b, .w, .l] address number_of_objects\n"
 	"    - loop on a set of addresses\n"
 );
 
-cmd_tbl_t U_BOOT_CMD(MTEST) = MK_CMD_ENTRY(
-	"mtest",    4,    1,     do_mem_mtest,
+U_BOOT_CMD(
+	mtest,    4,    1,     do_mem_mtest,
 	"mtest   - simple RAM test\n",
 	"[start [end [pattern]]]\n"
 	"    - simple RAM read/write test\n"

common/cmd_mii.c

@@ -129,8 +129,8 @@ int do_mii (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 
 /***************************************************/
 
-cmd_tbl_t U_BOOT_CMD(MII) = MK_CMD_ENTRY(
-	"mii",	5,	1,	do_mii,
+U_BOOT_CMD(
+	mii,	5,	1,	do_mii,
 	"mii     - MII utility commands\n",
 	"info  <addr>              - display MII PHY info\n"
 	"mii read  <addr> <reg>        - read  MII PHY <addr> register <reg>\n"

common/cmd_misc.c

@@ -56,15 +56,15 @@ int do_sleep (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 #if (CONFIG_COMMANDS & CFG_CMD_IRQ)
 int do_irqinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
 
-cmd_tbl_t U_BOOT_CMD(IRQINFO) = MK_CMD_ENTRY(
-	"irqinfo",    1,    1,     do_irqinfo,
+U_BOOT_CMD(
+	irqinfo,    1,    1,     do_irqinfo,
 	"irqinfo - print information about IRQs\n",
 	NULL
 );
 #endif  /* CONFIG_COMMANDS & CFG_CMD_IRQ */
 
-cmd_tbl_t U_BOOT_CMD(MISC) = MK_CMD_ENTRY(
-	"sleep" ,    2,    2,     do_sleep,
+U_BOOT_CMD(
+	sleep ,    2,    2,     do_sleep,
 	"sleep   - delay execution for some time\n",
 	"N\n"
 	"    - delay execution for N seconds (N is _decimal_ !!!)\n"

common/cmd_mmc.c

@@ -37,8 +37,8 @@ int do_mmc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	return 0;
 }
 
-cmd_tbl_t U_BOOT_CMD(MMCINIT) = MK_CMD_ENTRY(
-	"mmcinit",	1,	0,	do_mmc,
+U_BOOT_CMD(
+	mmcinit,	1,	0,	do_mmc,
 	"mmcinit - init mmc card\n",
 	NULL
 );

common/cmd_nand.c

@@ -247,8 +247,8 @@ int do_nand (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
     }
 }
 
-cmd_tbl_t U_BOOT_CMD(NAND) = MK_CMD_ENTRY(
-	"nand",	5,	1,	do_nand,
+U_BOOT_CMD(
+	nand,	5,	1,	do_nand,
 	"nand    - NAND sub-system\n",
 	"info  - show available NAND devices\n"
 	"nand device [dev] - show or set current device\n"
@@ -363,8 +363,8 @@ int do_nandboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	return rcode;
 }
 
-cmd_tbl_t U_BOOT_CMD(NBOOT) = MK_CMD_ENTRY(
-	"nboot",	4,	1,	do_nandboot,
+U_BOOT_CMD(
+	nboot,	4,	1,	do_nandboot,
 	"nboot   - boot from NAND device\n",
 	"loadAddr dev\n"
 );

common/cmd_net.c

@@ -40,8 +40,8 @@ int do_bootp (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	return netboot_common (BOOTP, cmdtp, argc, argv);
 }
 
-cmd_tbl_t U_BOOT_CMD(BOOTP) = MK_CMD_ENTRY(
-	"bootp",	3,	1,	do_bootp,
+U_BOOT_CMD(
+	bootp,	3,	1,	do_bootp,
 	"bootp   - boot image via network using BootP/TFTP protocol\n",
 	"[loadAddress] [bootfilename]\n"
 );
@@ -51,8 +51,8 @@ int do_tftpb (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	return netboot_common (TFTP, cmdtp, argc, argv);
 }
 
-cmd_tbl_t U_BOOT_CMD(TFTPB) = MK_CMD_ENTRY(
-	"tftpboot",	3,	1,	do_tftpb,
+U_BOOT_CMD(
+	tftpboot,	3,	1,	do_tftpb,
 	"tftpboot- boot image via network using TFTP protocol\n",
 	"[loadAddress] [bootfilename]\n"
 );
@@ -62,8 +62,8 @@ int do_rarpb (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	return netboot_common (RARP, cmdtp, argc, argv);
 }
 
-cmd_tbl_t U_BOOT_CMD(RARPB) = MK_CMD_ENTRY(
-	"rarpboot",	3,	1,	do_rarpb,
+U_BOOT_CMD(
+	rarpboot,	3,	1,	do_rarpb,
 	"rarpboot- boot image via network using RARP/TFTP protocol\n",
 	"[loadAddress] [bootfilename]\n"
 );
@@ -74,8 +74,8 @@ int do_dhcp (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	return netboot_common(DHCP, cmdtp, argc, argv);
 }
 
-cmd_tbl_t U_BOOT_CMD(DHCP) = MK_CMD_ENTRY(
-	"dhcp",	3,	1,	do_dhcp,
+U_BOOT_CMD(
+	dhcp,	3,	1,	do_dhcp,
 	"dhcp    - invoke DHCP client to obtain IP/boot params\n",
 	"\n"
 );

common/cmd_nvedit.c

@@ -561,16 +561,16 @@ envmatch (uchar *s1, int i2)
 
 /**************************************************/
 
-cmd_tbl_t U_BOOT_CMD(PRINTENV) = MK_CMD_ENTRY(
-	"printenv", CFG_MAXARGS, 1,	do_printenv,
+U_BOOT_CMD(
+	printenv, CFG_MAXARGS, 1,	do_printenv,
 	"printenv- print environment variables\n",
 	"\n    - print values of all environment variables\n"
 	"printenv name ...\n"
 	"    - print value of environment variable 'name'\n"
 );
 
-cmd_tbl_t U_BOOT_CMD(SETENV) = MK_CMD_ENTRY(
-	"setenv", CFG_MAXARGS, 0,	do_setenv,
+U_BOOT_CMD(
+	setenv, CFG_MAXARGS, 0,	do_setenv,
 	"setenv  - set environment variables\n",
 	"name value ...\n"
 	"    - set environment variable 'name' to 'value ...'\n"
@@ -580,8 +580,8 @@ cmd_tbl_t U_BOOT_CMD(SETENV) = MK_CMD_ENTRY(
 
 #if ((CONFIG_COMMANDS & (CFG_CMD_ENV|CFG_CMD_FLASH)) == (CFG_CMD_ENV|CFG_CMD_FLASH))
 
-cmd_tbl_t U_BOOT_CMD(SAVEENV) = MK_CMD_ENTRY(
-	"saveenv", 1, 0,	do_saveenv,
+U_BOOT_CMD(
+	saveenv, 1, 0,	do_saveenv,
 	"saveenv - save environment variables to persistent storage\n",
 	NULL
 );
@@ -590,8 +590,8 @@ cmd_tbl_t U_BOOT_CMD(SAVEENV) = MK_CMD_ENTRY(
 
 #if (CONFIG_COMMANDS & CFG_CMD_ASKENV)
 
-cmd_tbl_t U_BOOT_CMD(ASKENV) = MK_CMD_ENTRY(
-	"askenv",	CFG_MAXARGS,	1,	do_askenv,
+U_BOOT_CMD(
+	askenv,	CFG_MAXARGS,	1,	do_askenv,
 	"askenv  - get environment variables from stdin\n",
 	"name [message] [size]\n"
 	"    - get environment variable 'name' from stdin (max 'size' chars)\n"
@@ -607,8 +607,8 @@ cmd_tbl_t U_BOOT_CMD(ASKENV) = MK_CMD_ENTRY(
 
 #if (CONFIG_COMMANDS & CFG_CMD_RUN)
 int do_run (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
-cmd_tbl_t U_BOOT_CMD(RUN) = MK_CMD_ENTRY(
-	"run",	CFG_MAXARGS,	1,	do_run,
+U_BOOT_CMD(
+	run,	CFG_MAXARGS,	1,	do_run,
 	"run     - run commands in an environment variable\n",
 	"var [...]\n"
 	"    - run the commands in the environment variable(s) 'var'\n"

common/cmd_pci.c

@@ -548,8 +548,8 @@ int do_pci (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 /***************************************************/
 
 
-cmd_tbl_t U_BOOT_CMD(PCI) = MK_CMD_ENTRY(
-	"pci",	5,	1,	do_pci,
+U_BOOT_CMD(
+	pci,	5,	1,	do_pci,
 	"pci     - list and access PCI Configuraton Space\n",
 	"[bus] [long]\n"
 	"    - short or long list of PCI devices on bus 'bus'\n"

common/cmd_pcmcia.c

@@ -2487,8 +2487,8 @@ static int identify  (volatile uchar *p)
 /**************************************************/
 
 #if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
-cmd_tbl_t U_BOOT_CMD(PINIT) = MK_CMD_ENTRY(
-	"pinit",	2,	1,	do_pinit,
+U_BOOT_CMD(
+	pinit,	2,	1,	do_pinit,
 	"pinit   - PCMCIA sub-system\n",
 	"on  - power on PCMCIA socket\n"
 	"pinit off - power off PCMCIA socket\n"

common/cmd_portio.c

@@ -95,8 +95,8 @@ int do_portio_out (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 	return 0;
 }
 
-cmd_tbl_t U_BOOT_CMD(PORTIO_OUT) = MK_CMD_ENTRY(
-	"out",	3,	1,	do_portio_out,
+U_BOOT_CMD(
+	out,	3,	1,	do_portio_out,
 	"out     - write datum to IO port\n",
 	"[.b, .w, .l] port value\n    - output to IO port\n"
 );
@@ -159,8 +159,8 @@ int do_portio_in (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 	return 0;
 }
 
-cmd_tbl_t U_BOOT_CMD(PORTIO_IN) = MK_CMD_ENTRY(
-	"in",	2,	1,	do_portio_in,
+U_BOOT_CMD(
+	in,	2,	1,	do_portio_in,
 	"in      - read data from an IO port\n",
 	"[.b, .w, .l] port\n"
 	"    - read datum from IO port\n"

common/cmd_reginfo.c

@@ -219,8 +219,8 @@ mfdcr(dmacr3), mfdcr(dmact3),mfdcr(dmada3), mfdcr(dmasa3), mfdcr(dmasb3) );
 #if (defined(CONFIG_8xx) || defined(CONFIG_405GP)) && \
      (CONFIG_COMMANDS & CFG_CMD_REGINFO)
 
-cmd_tbl_t U_BOOT_CMD(REGINFO) =	MK_CMD_ENTRY(
- 	"reginfo",	2,	1,	do_reginfo,
+U_BOOT_CMD(
+ 	reginfo,	2,	1,	do_reginfo,
 	"reginfo - print register information\n",
 );
 #endif

common/cmd_spi.c

@@ -131,8 +131,8 @@ int do_spi (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 /***************************************************/
 
-cmd_tbl_t U_BOOT_CMD(SPI) = MK_CMD_ENTRY(
-	"sspi",	5,	1,	do_spi,
+U_BOOT_CMD(
+	sspi,	5,	1,	do_spi,
 	"sspi     - SPI utility commands\n",
 	"<device> <bit_len> <dout> - Send <bit_len> bits from <dout> out the SPI\n"
 	"<device>  - Identifies the chip select of the device\n"

common/cmd_usb.c

@@ -594,8 +594,8 @@ int do_usb (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 #if (CONFIG_COMMANDS & CFG_CMD_USB)
 
 #ifdef CONFIG_USB_STORAGE
-cmd_tbl_t U_BOOT_CMD(USB) = MK_CMD_ENTRY(
-	"usb",	5,	1,	do_usb,
+U_BOOT_CMD(
+	usb,	5,	1,	do_usb,
 	"usb     - USB sub-system\n",
 	"reset - reset (rescan) USB controller\n"
 	"usb  stop [f]  - stop USB [f]=force stop\n"
@@ -609,15 +609,15 @@ cmd_tbl_t U_BOOT_CMD(USB) = MK_CMD_ENTRY(
 );
 
 
-cmd_tbl_t U_BOOT_CMD(USBBOOT) = MK_CMD_ENTRY(
-	"usbboot",	3,	1,	do_usbboot,
+U_BOOT_CMD(
+	usbboot,	3,	1,	do_usbboot,
 	"usbboot - boot from USB device\n",
 	"loadAddr dev:part\n"
 );
 
 #else
-cmd_tbl_t U_BOOT_CMD(USB) = MK_CMD_ENTRY(
-	"usb",	5,	1,	do_usb,
+U_BOOT_CMD(
+	usb,	5,	1,	do_usb,
 	"usb     - USB sub-system\n",
 	"reset - reset (rescan) USB controller\n"
 	"usb  tree  - show USB device tree\n"

common/cmd_vfd.c

@@ -65,8 +65,8 @@ int do_vfd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	return 0;
 }
 
-cmd_tbl_t U_BOOT_CMD(VFD) = MK_CMD_ENTRY(
- 	"vfd",	2,	0,	do_vfd,
+U_BOOT_CMD(
+ 	vfd,	2,	0,	do_vfd,
  	"vfd     - load a bitmap to the VFDs on TRAB\n",
  	"N\n"
  	"    - load bitmap N to the VFDs (N is _decimal_ !!!)\n"

common/command.c

@@ -36,8 +36,8 @@ do_version (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	return 0;
 }
 
-cmd_tbl_t U_BOOT_CMD(VERS) = MK_CMD_ENTRY(
-	"version",	1,		1,	do_version,
+U_BOOT_CMD(
+	version,	1,		1,	do_version,
  	"version - print monitor version\n",
 	NULL
 );
@@ -67,8 +67,8 @@ do_echo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	return 0;
 }
 
-cmd_tbl_t U_BOOT_CMD(ECHO) = MK_CMD_ENTRY(
-	"echo",	CFG_MAXARGS,	1,	do_echo,
+U_BOOT_CMD(
+	echo,	CFG_MAXARGS,	1,	do_echo,
  	"echo    - echo args to console\n",
  	"[args..]\n"
 	"    - echo args to console; \\c suppresses newline\n"
@@ -158,8 +158,8 @@ int do_help (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 }
 
 
-cmd_tbl_t U_BOOT_CMD(HELP) = MK_CMD_ENTRY(
-	"help",	CFG_MAXARGS,	1,	do_help,
+U_BOOT_CMD(
+	help,	CFG_MAXARGS,	1,	do_help,
  	"help    - print online help\n",
  	"[command ...]\n"
  	"    - show help information (for 'command')\n"
@@ -169,11 +169,19 @@ cmd_tbl_t U_BOOT_CMD(HELP) = MK_CMD_ENTRY(
   "'help' with one or more command names as arguments.\n"
 );
 
-cmd_tbl_t U_BOOT_CMD(QUES) = MK_CMD_ENTRY(
+/* This do not ust the U_BOOT_CMD macro as ? can't be used in symbol names */
+#ifdef  CFG_LONGHELP
+cmd_tbl_t __u_boot_cmd_question_mark Struct_Section = {
 	"?",	CFG_MAXARGS,	1,	do_help,
  	"?       - alias for 'help'\n",
 	NULL
-);
+};
+#else
+cmd_tbl_t __u_boot_cmd_question_mark Struct_Section = {
+	"?",	CFG_MAXARGS,	1,	do_help,
+ 	"?       - alias for 'help'\n"
+};
+#endif /* CFG_LONGHELP */
 
 /***************************************************************************
  * find command table entry for a command

common/kgdb.c

@@ -573,8 +573,8 @@ do_kgdb(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
     return 0;
 }
 
-cmd_tbl_t U_BOOT_CMD(KGDB) = MK_CMD_ENTRY(
-	"kgdb", CFG_MAXARGS, 1,	do_kgdb,
+U_BOOT_CMD(
+	kgdb, CFG_MAXARGS, 1,	do_kgdb,
 	"kgdb    - enter gdb remote debug mode\n",
 	"[arg0 arg1 .. argN]\n"
 	"    - executes a breakpoint so that kgdb mode is\n"

doc/README.commands

@@ -1,103 +1,31 @@
-#
-# The commands in this table are sorted alphabetically by the
-# command name and in descending order by the command name string
-# length. This is to prevent conflicts in command name parsing.
-# Please ensure that new commands are added according to that rule.
-# See $(TOPDIR)/common/command.c
-#
-########################
-#
-# command	length
-#
-########################
-askenv		8
-as		2
-autoscr		5
-base		2
-bdinfo		2
-bmp		3
-bootelf		7
-bootm		5
-bootp		5
-bootvx		6
-bootd		4
-break		2
-brginfo		3
-carinfo		3
-chpart		6
-cmp		3
-coninfo		5
-continue	4
-cp		2
-crc32		3
-date		3
-dcache		2
-dhcp		4
-dmainfo		3
-ds		2
-dtt		3
-echo		4
-eeprom		3
-erase		3
-fccinfo		3
-fdcboot		4
-flinfo		3
-fpga		4
-fsinfo		5
-fsload		5
-getdcr		6		# IBM 4XX DCR registers
-go		2
-help		1
-i2cinfo		4
-i2c		3
-icache		2
-icinfo		3
-ide		3
-iminfo		3
-iopinfo		3
-irqinfo		3
-kgdb		4
-loadb		5
-loads		5
-loop		4
-ls		2
-mccinfo		3
-md		2
-memcinfo	4
-mii		3
-mm		2
-mtest		5
-muxinfo		3
-mw		2
-nand		3
-nboot		4
-next		4
-nm		2
-pciinfo		3
-pinit		4
-printenv	8
-protect		4
-rarpboot	4
-rdump		5
-reginfo		3
-reset		5
-run		3
-saveenv		4
-sccinfo		3
-scsiboot	5
-scsi		4
-siiinfo		3
-sitinfo		3
-siuinfo		3
-setdcr		6		# IBM 4XX DCR registers
-setenv		6
-smcinfo		3
-spiinfo		3
-sspi		4
-stack		5
-step		4
-tftpboot	4
-usbboot		5
-usb		4
-version		4
-?		1
+
+Commands are added to U-Boot by creating a new command structure.
+This is done by first including command.h
+
+Then using the U_BOOT_CMD() macro to fill in a cmd_tbl_t struct.
+
+U_BOOT_CMD(name,maxargs,repeatable,command,"usage","help")
+
+name:	 is the name of the commad. THIS IS NOT a string.
+maxargs: the maximumn numbers of arguments this function takes
+command: Function pointer (*cmd)(struct cmd_tbl_s *, int, int, char *[]);
+usage:	 Short description. This is a string
+help:	 long description. This is a string
+
+
+**** Behinde the scene ******
+
+The structure created is named with a special prefix (__u_boot_cmd_)
+and placed by the linker in a special section.
+
+This makes it possible for the final link to extract all commands
+compiled into any object code and construct a static array so the
+command can be found in an array starting at __u_boot_cmd_start.
+
+If a new board is defined do not forget to define the command section
+by writing in u-boot.lds ($(TOPDIR)/board/boardname/u-boot.lds) these
+3 lines:
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;

include/command.h

@@ -40,7 +40,6 @@ struct cmd_tbl_s {
 	char		*name;		/* Command Name			*/
 	int		maxargs;	/* maximum number of arguments	*/
 	int		repeatable;	/* autorepeat allowed?		*/
-
 					/* Implementation function	*/
 	int		(*cmd)(struct cmd_tbl_s *, int, int, char *[]);
 	char		*usage;		/* Usage message	(short)	*/
@@ -83,17 +82,16 @@ typedef	void 	command_t (cmd_tbl_t *, int, int, char *[]);
 
 
 #define Struct_Section  __attribute__ ((unused,section (".u_boot_cmd")))
-#define U_BOOT_CMD(x)  __u_boot_cmd_##x Struct_Section
 
 #ifdef  CFG_LONGHELP
 
-#define MK_CMD_ENTRY(name,maxargs,rep,cmd,usage,help)	\
-			{ name, maxargs, rep, cmd, usage, help }
+#define U_BOOT_CMD(name,maxargs,rep,cmd,usage,help) \
+cmd_tbl_t __u_boot_cmd_##name Struct_Section = {#name, maxargs, rep, cmd, usage, help}
 
 #else	/* no long help info */
 
-#define MK_CMD_ENTRY(name,maxargs,rep,cmd,usage,help)	\
-			{ name, maxargs, rep, cmd, usage }
+#define U_BOOT_CMD(name,maxargs,rep,cmd,usage,help) \
+cmd_tbl_t __u_boot_cmd_##name Struct_Section = {#name, maxargs, rep, cmd, usage}
 
 #endif	/* CFG_LONGHELP */
 

include/configs/NSCU.h

@@ -0,0 +1,470 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC855		1	/* This is a MPC855 CPU		*/
+#define CONFIG_TQM855M		1	/* ...on a TQM8xxM module	*/
+
+#define	CONFIG_8xx_CONS_SCC1	1	/* Console is on SMC1		*/
+
+#define	CONFIG_66MHz		1	/* running at 66 MHz, 1:1 clock	*/
+
+#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#undef	CONFIG_CLOCKS_IN_MHZ		/* clocks passsed to Linux in Hz */
+
+#define CONFIG_BOARD_TYPES	1	/* support board types		*/
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=$(serverip):$(rootpath)\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs $(bootargs) "				\
+		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"	\
+		":$(hostname):$(netdev):off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm $(kernel_addr)\0"				\
+	"flash_self=run ramargs addip;"					\
+		"bootm $(kernel_addr) $(ramdisk_addr)\0"		\
+	"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0"	\
+	"rootpath=/opt/eldk/ppc_8xx\0"					\
+	"bootfile=/tftpboot/NSCU/uImage\0"				\
+	"kernel_addr=40080000\0"					\
+	"ramdisk_addr=40180000\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define	CONFIG_STATUS_LED	1	/* Status LED enabled		*/
+
+#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
+
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_ASKENV	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_IDE	| \
+				CFG_CMD_DATE	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
+
+#if 0
+#define	CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
+#endif
+#ifdef	CFG_HUSH_PARSER
+#define	CFG_PROMPT_HUSH_PS2	"> "
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE		1024	/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE		256	/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS		16	/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+
+#define	CFG_HZ			1000	/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xFFF00000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define	CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0x40000000
+#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define	CFG_ENV_IS_IN_FLASH	1
+#define	CFG_ENV_OFFSET		0x40000	/*   Offset   of Environment Sector	*/
+#define	CFG_ENV_SIZE		0x08000	/* Total Size of Environment Sector	*/
+#define	CFG_ENV_SECT_SIZE	0x20000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CFG_ENV_OFFSET_REDUND	(CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
+
+/*-----------------------------------------------------------------------
+ * Hardware Information Block
+ */
+#define CFG_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CFG_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
+#define CFG_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#ifndef	CONFIG_CAN_DRIVER
+#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#else	/* we must activate GPL5 in the SIUMCR for CAN */
+#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ *
+ * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
+ */
+#ifdef	CONFIG_80MHz	/* for 80 MHz, we use a 16 MHz clock * 5 */
+#define CFG_PLPRCR							\
+		( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
+#else			/* up to 66 MHz we use a 1:1 clock */
+#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+#endif	/* CONFIG_80MHz */
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#ifdef	CONFIG_80MHz	/* for 80 MHz, we use a 16 MHz clock * 5 */
+#define CFG_SCCR	(/* SCCR_TBS  | */ \
+			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+#else			/* up to 66 MHz we use a 1:1 clock */
+#define CFG_SCCR	(SCCR_TBS     | \
+			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+#endif	/* CONFIG_80MHz */
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
+#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O			*/
+#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers	*/
+#define CFG_ATA_ALT_OFFSET	0x0100
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_DER	0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #0	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+
+/*
+ * FLASH timing:
+ */
+#if   defined(CONFIG_80MHz)
+/* 80 MHz CPU - 40 MHz bus: ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */
+#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | 0       | OR_CSNT_SAM | \
+				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
+#elif defined(CONFIG_66MHz)
+/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
+#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
+#else		/*   50 MHz */
+/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
+#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+				 OR_SCY_2_CLK | OR_EHTR | OR_BI)
+#endif	/*CONFIG_??MHz */
+
+#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+
+#define CFG_OR1_REMAP	CFG_OR0_REMAP
+#define CFG_OR1_PRELIM	CFG_OR0_PRELIM
+#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
+
+/*
+ * BR2/3 and OR2/3 (SDRAM)
+ *
+ */
+#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
+#define SDRAM_BASE3_PRELIM	0x20000000	/* SDRAM bank #1	*/
+#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CFG_OR_TIMING_SDRAM	0x00000A00
+
+#define CFG_OR2_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
+#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+#ifndef	CONFIG_CAN_DRIVER
+#define	CFG_OR3_PRELIM	CFG_OR2_PRELIM
+#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */
+#define	CFG_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
+#define CFG_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
+#define CFG_OR3_CAN		(CFG_CAN_OR_AM | OR_G5LA | OR_BI)
+#define CFG_BR3_CAN		((CFG_CAN_BASE & BR_BA_MSK) | \
+					BR_PS_8 | BR_MS_UPMB | BR_V )
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*
+ * Memory Periodic Timer Prescaler
+ *
+ * The Divider for PTA (refresh timer) configuration is based on an
+ * example SDRAM configuration (64 MBit, one bank). The adjustment to
+ * the number of chip selects (NCS) and the actually needed refresh
+ * rate is done by setting MPTPR.
+ *
+ * PTA is calculated from
+ *	PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
+ *
+ *	gclk	  CPU clock (not bus clock!)
+ *	Trefresh  Refresh cycle * 4 (four word bursts used)
+ *
+ * 4096  Rows from SDRAM example configuration
+ * 1000  factor s -> ms
+ *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
+ *    4  Number of refresh cycles per period
+ *   64  Refresh cycle in ms per number of rows
+ * --------------------------------------------
+ * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
+ *
+ * 50 MHz => 50.000.000 / Divider =  98
+ * 66 Mhz => 66.000.000 / Divider = 129
+ * 80 Mhz => 80.000.000 / Divider = 156
+ */
+#if   defined(CONFIG_80MHz)
+#define CFG_MAMR_PTA		156
+#elif defined(CONFIG_66MHz)
+#define CFG_MAMR_PTA		129
+#else		/*   50 MHz */
+#define CFG_MAMR_PTA		 98
+#endif	/*CONFIG_??MHz */
+
+/*
+ * For 16 MBit, refresh rates could be 31.3 us
+ * (= 64 ms / 2K = 125 / quad bursts).
+ * For a simpler initialization, 15.6 us is used instead.
+ *
+ * #define CFG_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
+ * #define CFG_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
+ */
+#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#undef CONFIG_SCC1_ENET
+#define CONFIG_FEC_ENET
+/* #define CONFIG_ETHPRIME		"FEC ETHERNET" */
+
+#endif	/* __CONFIG_H */

include/configs/TQM823L.h

@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000, 2001, 2002
+ * (C) Copyright 2000-2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -261,7 +261,7 @@
 #ifdef	CONFIG_80MHz	/* for 80 MHz, we use a 16 MHz clock * 5 */
 #define CFG_PLPRCR							\
 		( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
-#else			/* up to 50 MHz we use a 1:1 clock */
+#else			/* up to 66 MHz we use a 1:1 clock */
 #define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 #endif	/* CONFIG_80MHz */
 
@@ -277,7 +277,7 @@
 			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 			 SCCR_DFALCD00)
-#else			/* up to 50 MHz we use a 1:1 clock */
+#else			/* up to 66 MHz we use a 1:1 clock */
 #define CFG_SCCR	(SCCR_TBS     | \
 			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \

include/configs/TQM823M.h

@@ -0,0 +1,474 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC823		1	/* This is a MPC823 CPU		*/
+#define CONFIG_TQM823M		1	/* ...on a TQM8xxM module	*/
+
+#ifdef	CONFIG_LCD			/* with LCD controller ?	*/
+/* #define CONFIG_NEC_NL6648BC20 1 / * use NEC NL6648BC20 display	*/
+#endif
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+
+#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
+
+#define CONFIG_BOARD_TYPES	1	/* support board types		*/
+
+#define CONFIG_PREBOOT	"echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=$(serverip):$(rootpath)\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs $(bootargs) "				\
+		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"	\
+		":$(hostname):$(netdev):off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm $(kernel_addr)\0"				\
+	"flash_self=run ramargs addip;"					\
+		"bootm $(kernel_addr) $(ramdisk_addr)\0"		\
+	"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0"	\
+	"rootpath=/opt/eldk/ppc_8xx\0"					\
+	"bootfile=/tftpboot/TQM823M/uImage\0"				\
+	"kernel_addr=40080000\0"					\
+	"ramdisk_addr=40180000\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#ifdef CONFIG_LCD
+# undef	 CONFIG_STATUS_LED		/* disturbs display		*/
+#else
+# define CONFIG_STATUS_LED	1	/* Status LED enabled		*/
+#endif	/* CONFIG_LCD */
+
+#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
+
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_ASKENV	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_IDE	| \
+				CFG_CMD_DATE	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
+
+#if 0
+#define	CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
+#endif
+#ifdef	CFG_HUSH_PARSER
+#define	CFG_PROMPT_HUSH_PS2	"> "
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE		1024	/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE		256	/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS		16	/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+
+#define	CFG_HZ			1000	/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xFFF00000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define	CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0x40000000
+#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define	CFG_ENV_IS_IN_FLASH	1
+#define	CFG_ENV_OFFSET		0x40000	/*   Offset   of Environment Sector	*/
+#define	CFG_ENV_SIZE		0x08000	/* Total Size of Environment Sector	*/
+#define	CFG_ENV_SECT_SIZE	0x20000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CFG_ENV_OFFSET_REDUND	(CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
+
+/*-----------------------------------------------------------------------
+ * Hardware Information Block
+ */
+#define CFG_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CFG_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
+#define CFG_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#ifndef	CONFIG_CAN_DRIVER
+#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#else	/* we must activate GPL5 in the SIUMCR for CAN */
+#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ *
+ * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
+ */
+#ifdef	CONFIG_80MHz	/* for 80 MHz, we use a 16 MHz clock * 5 */
+#define CFG_PLPRCR							\
+		( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
+#else			/* up to 66 MHz we use a 1:1 clock */
+#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+#endif	/* CONFIG_80MHz */
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#ifdef	CONFIG_80MHz	/* for 80 MHz, we use a 16 MHz clock * 5 */
+#define CFG_SCCR	(/* SCCR_TBS  | */ \
+			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+#else			/* up to 66 MHz we use a 1:1 clock */
+#define CFG_SCCR	(SCCR_TBS     | \
+			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+#endif	/* CONFIG_80MHz */
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
+#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O			*/
+#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers	*/
+#define CFG_ATA_ALT_OFFSET	0x0100
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_DER	0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #0	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+
+/*
+ * FLASH timing:
+ */
+#if   defined(CONFIG_80MHz)
+/* 80 MHz CPU - 40 MHz bus: ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */
+#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | 0       | OR_CSNT_SAM | \
+				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
+#elif defined(CONFIG_66MHz)
+/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
+#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
+#else		/*   50 MHz */
+/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
+#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+				 OR_SCY_2_CLK | OR_EHTR | OR_BI)
+#endif	/*CONFIG_??MHz */
+
+#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+
+#define CFG_OR1_REMAP	CFG_OR0_REMAP
+#define CFG_OR1_PRELIM	CFG_OR0_PRELIM
+#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
+
+/*
+ * BR2/3 and OR2/3 (SDRAM)
+ *
+ */
+#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
+#define SDRAM_BASE3_PRELIM	0x20000000	/* SDRAM bank #1	*/
+#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CFG_OR_TIMING_SDRAM	0x00000A00
+
+#define CFG_OR2_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
+#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+#ifndef	CONFIG_CAN_DRIVER
+#define	CFG_OR3_PRELIM	CFG_OR2_PRELIM
+#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */
+#define	CFG_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
+#define CFG_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
+#define CFG_OR3_CAN		(CFG_CAN_OR_AM | OR_G5LA | OR_BI)
+#define CFG_BR3_CAN		((CFG_CAN_BASE & BR_BA_MSK) | \
+					BR_PS_8 | BR_MS_UPMB | BR_V )
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*
+ * Memory Periodic Timer Prescaler
+ *
+ * The Divider for PTA (refresh timer) configuration is based on an
+ * example SDRAM configuration (64 MBit, one bank). The adjustment to
+ * the number of chip selects (NCS) and the actually needed refresh
+ * rate is done by setting MPTPR.
+ *
+ * PTA is calculated from
+ *	PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
+ *
+ *	gclk	  CPU clock (not bus clock!)
+ *	Trefresh  Refresh cycle * 4 (four word bursts used)
+ *
+ * 4096  Rows from SDRAM example configuration
+ * 1000  factor s -> ms
+ *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
+ *    4  Number of refresh cycles per period
+ *   64  Refresh cycle in ms per number of rows
+ * --------------------------------------------
+ * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
+ *
+ * 50 MHz => 50.000.000 / Divider =  98
+ * 66 Mhz => 66.000.000 / Divider = 129
+ * 80 Mhz => 80.000.000 / Divider = 156
+ */
+#if   defined(CONFIG_80MHz)
+#define CFG_MAMR_PTA		156
+#elif defined(CONFIG_66MHz)
+#define CFG_MAMR_PTA		129
+#else		/*   50 MHz */
+#define CFG_MAMR_PTA		 98
+#endif	/*CONFIG_??MHz */
+
+/*
+ * For 16 MBit, refresh rates could be 31.3 us
+ * (= 64 ms / 2K = 125 / quad bursts).
+ * For a simpler initialization, 15.6 us is used instead.
+ *
+ * #define CFG_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
+ * #define CFG_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
+ */
+#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#endif	/* __CONFIG_H */

include/configs/TQM8260.h

@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2001
+ * (C) Copyright 2001-2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this

include/configs/TQM850L.h

@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000, 2001, 2002
+ * (C) Copyright 2000-2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -253,7 +253,7 @@
 #ifdef	CONFIG_80MHz	/* for 80 MHz, we use a 16 MHz clock * 5 */
 #define CFG_PLPRCR							\
 		( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
-#else			/* up to 50 MHz we use a 1:1 clock */
+#else			/* up to 66 MHz we use a 1:1 clock */
 #define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 #endif	/* CONFIG_80MHz */
 
@@ -269,7 +269,7 @@
 			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 			 SCCR_DFALCD00)
-#else			/* up to 50 MHz we use a 1:1 clock */
+#else			/* up to 66 MHz we use a 1:1 clock */
 #define CFG_SCCR	(SCCR_TBS     | \
 			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \

include/configs/TQM850M.h

@@ -0,0 +1,466 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC850		1	/* This is a MPC850 CPU		*/
+#define CONFIG_TQM850M		1	/* ...on a TQM8xxM module	*/
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+
+#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
+
+#define CONFIG_BOARD_TYPES	1	/* support board types		*/
+
+#define CONFIG_PREBOOT	"echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=$(serverip):$(rootpath)\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs $(bootargs) "				\
+		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"	\
+		":$(hostname):$(netdev):off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm $(kernel_addr)\0"				\
+	"flash_self=run ramargs addip;"					\
+		"bootm $(kernel_addr) $(ramdisk_addr)\0"		\
+	"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0"	\
+	"rootpath=/opt/eldk/ppc_8xx\0"					\
+	"bootfile=/tftpboot/TQM850M/uImage\0"				\
+	"kernel_addr=40080000\0"					\
+	"ramdisk_addr=40180000\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define	CONFIG_STATUS_LED	1	/* Status LED enabled		*/
+
+#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
+
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_ASKENV	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_IDE	| \
+				CFG_CMD_DATE	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
+
+#if 0
+#define	CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
+#endif
+#ifdef	CFG_HUSH_PARSER
+#define	CFG_PROMPT_HUSH_PS2	"> "
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE		1024	/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE		256	/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS		16	/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+
+#define	CFG_HZ			1000	/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xFFF00000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define	CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0x40000000
+#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define	CFG_ENV_IS_IN_FLASH	1
+#define	CFG_ENV_OFFSET		0x40000	/*   Offset   of Environment Sector	*/
+#define	CFG_ENV_SIZE		0x08000	/* Total Size of Environment Sector	*/
+#define	CFG_ENV_SECT_SIZE	0x20000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CFG_ENV_OFFSET_REDUND	(CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
+
+/*-----------------------------------------------------------------------
+ * Hardware Information Block
+ */
+#define CFG_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CFG_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
+#define CFG_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#ifndef	CONFIG_CAN_DRIVER
+#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#else	/* we must activate GPL5 in the SIUMCR for CAN */
+#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ *
+ * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
+ */
+#ifdef	CONFIG_80MHz	/* for 80 MHz, we use a 16 MHz clock * 5 */
+#define CFG_PLPRCR							\
+		( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
+#else			/* up to 66 MHz we use a 1:1 clock */
+#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+#endif	/* CONFIG_80MHz */
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#ifdef	CONFIG_80MHz	/* for 80 MHz, we use a 16 MHz clock * 5 */
+#define CFG_SCCR	(/* SCCR_TBS  | */ \
+			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+#else			/* up to 66 MHz we use a 1:1 clock */
+#define CFG_SCCR	(SCCR_TBS     | \
+			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+#endif	/* CONFIG_80MHz */
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
+#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O			*/
+#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers	*/
+#define CFG_ATA_ALT_OFFSET	0x0100
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_DER	0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #0	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+
+/*
+ * FLASH timing:
+ */
+#if   defined(CONFIG_80MHz)
+/* 80 MHz CPU - 40 MHz bus: ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */
+#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | 0       | OR_CSNT_SAM | \
+				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
+#elif defined(CONFIG_66MHz)
+/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
+#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
+#else		/*   50 MHz */
+/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
+#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+				 OR_SCY_2_CLK | OR_EHTR | OR_BI)
+#endif	/*CONFIG_??MHz */
+
+#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+
+#define CFG_OR1_REMAP	CFG_OR0_REMAP
+#define CFG_OR1_PRELIM	CFG_OR0_PRELIM
+#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
+
+/*
+ * BR2/3 and OR2/3 (SDRAM)
+ *
+ */
+#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
+#define SDRAM_BASE3_PRELIM	0x20000000	/* SDRAM bank #1	*/
+#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CFG_OR_TIMING_SDRAM	0x00000A00
+
+#define CFG_OR2_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
+#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+#ifndef	CONFIG_CAN_DRIVER
+#define	CFG_OR3_PRELIM	CFG_OR2_PRELIM
+#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */
+#define	CFG_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
+#define CFG_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
+#define CFG_OR3_CAN		(CFG_CAN_OR_AM | OR_G5LA | OR_BI)
+#define CFG_BR3_CAN		((CFG_CAN_BASE & BR_BA_MSK) | \
+					BR_PS_8 | BR_MS_UPMB | BR_V )
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*
+ * Memory Periodic Timer Prescaler
+ *
+ * The Divider for PTA (refresh timer) configuration is based on an
+ * example SDRAM configuration (64 MBit, one bank). The adjustment to
+ * the number of chip selects (NCS) and the actually needed refresh
+ * rate is done by setting MPTPR.
+ *
+ * PTA is calculated from
+ *	PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
+ *
+ *	gclk	  CPU clock (not bus clock!)
+ *	Trefresh  Refresh cycle * 4 (four word bursts used)
+ *
+ * 4096  Rows from SDRAM example configuration
+ * 1000  factor s -> ms
+ *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
+ *    4  Number of refresh cycles per period
+ *   64  Refresh cycle in ms per number of rows
+ * --------------------------------------------
+ * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
+ *
+ * 50 MHz => 50.000.000 / Divider =  98
+ * 66 Mhz => 66.000.000 / Divider = 129
+ * 80 Mhz => 80.000.000 / Divider = 156
+ */
+#if   defined(CONFIG_80MHz)
+#define CFG_MAMR_PTA		156
+#elif defined(CONFIG_66MHz)
+#define CFG_MAMR_PTA		129
+#else		/*   50 MHz */
+#define CFG_MAMR_PTA		 98
+#endif	/*CONFIG_??MHz */
+
+/*
+ * For 16 MBit, refresh rates could be 31.3 us
+ * (= 64 ms / 2K = 125 / quad bursts).
+ * For a simpler initialization, 15.6 us is used instead.
+ *
+ * #define CFG_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
+ * #define CFG_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
+ */
+#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#endif	/* __CONFIG_H */

include/configs/TQM855L.h

@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000, 2001, 2002
+ * (C) Copyright 2000-2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -253,7 +253,7 @@
 #ifdef	CONFIG_80MHz	/* for 80 MHz, we use a 16 MHz clock * 5 */
 #define CFG_PLPRCR							\
 		( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
-#else			/* up to 50 MHz we use a 1:1 clock */
+#else			/* up to 66 MHz we use a 1:1 clock */
 #define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 #endif	/* CONFIG_80MHz */
 
@@ -269,7 +269,7 @@
 			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 			 SCCR_DFALCD00)
-#else			/* up to 50 MHz we use a 1:1 clock */
+#else			/* up to 66 MHz we use a 1:1 clock */
 #define CFG_SCCR	(SCCR_TBS     | \
 			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \

include/configs/TQM855M.h

@@ -0,0 +1,470 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC855		1	/* This is a MPC855 CPU		*/
+#define CONFIG_TQM855M		1	/* ...on a TQM8xxM module	*/
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+
+#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
+
+#define CONFIG_BOARD_TYPES	1	/* support board types		*/
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=$(serverip):$(rootpath)\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs $(bootargs) "				\
+		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"	\
+		":$(hostname):$(netdev):off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm $(kernel_addr)\0"				\
+	"flash_self=run ramargs addip;"					\
+		"bootm $(kernel_addr) $(ramdisk_addr)\0"		\
+	"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0"	\
+	"rootpath=/opt/eldk/ppc_8xx\0"					\
+	"bootfile=/tftpboot/TQM855M/uImage\0"				\
+	"kernel_addr=40080000\0"					\
+	"ramdisk_addr=40180000\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define	CONFIG_STATUS_LED	1	/* Status LED enabled		*/
+
+#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
+
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_ASKENV	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_IDE	| \
+				CFG_CMD_DATE	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
+
+#if 0
+#define	CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
+#endif
+#ifdef	CFG_HUSH_PARSER
+#define	CFG_PROMPT_HUSH_PS2	"> "
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE		1024	/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE		256	/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS		16	/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+
+#define	CFG_HZ			1000	/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xFFF00000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define	CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0x40000000
+#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define	CFG_ENV_IS_IN_FLASH	1
+#define	CFG_ENV_OFFSET		0x40000	/*   Offset   of Environment Sector	*/
+#define	CFG_ENV_SIZE		0x08000	/* Total Size of Environment Sector	*/
+#define	CFG_ENV_SECT_SIZE	0x20000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CFG_ENV_OFFSET_REDUND	(CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
+
+/*-----------------------------------------------------------------------
+ * Hardware Information Block
+ */
+#define CFG_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CFG_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
+#define CFG_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#ifndef	CONFIG_CAN_DRIVER
+#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#else	/* we must activate GPL5 in the SIUMCR for CAN */
+#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ *
+ * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
+ */
+#ifdef	CONFIG_80MHz	/* for 80 MHz, we use a 16 MHz clock * 5 */
+#define CFG_PLPRCR							\
+		( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
+#else			/* up to 66 MHz we use a 1:1 clock */
+#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+#endif	/* CONFIG_80MHz */
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#ifdef	CONFIG_80MHz	/* for 80 MHz, we use a 16 MHz clock * 5 */
+#define CFG_SCCR	(/* SCCR_TBS  | */ \
+			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+#else			/* up to 66 MHz we use a 1:1 clock */
+#define CFG_SCCR	(SCCR_TBS     | \
+			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+#endif	/* CONFIG_80MHz */
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
+#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O			*/
+#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers	*/
+#define CFG_ATA_ALT_OFFSET	0x0100
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_DER	0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #0	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+
+/*
+ * FLASH timing:
+ */
+#if   defined(CONFIG_80MHz)
+/* 80 MHz CPU - 40 MHz bus: ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */
+#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | 0       | OR_CSNT_SAM | \
+				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
+#elif defined(CONFIG_66MHz)
+/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
+#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
+#else		/*   50 MHz */
+/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
+#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+				 OR_SCY_2_CLK | OR_EHTR | OR_BI)
+#endif	/*CONFIG_??MHz */
+
+#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+
+#define CFG_OR1_REMAP	CFG_OR0_REMAP
+#define CFG_OR1_PRELIM	CFG_OR0_PRELIM
+#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
+
+/*
+ * BR2/3 and OR2/3 (SDRAM)
+ *
+ */
+#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
+#define SDRAM_BASE3_PRELIM	0x20000000	/* SDRAM bank #1	*/
+#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CFG_OR_TIMING_SDRAM	0x00000A00
+
+#define CFG_OR2_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
+#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+#ifndef	CONFIG_CAN_DRIVER
+#define	CFG_OR3_PRELIM	CFG_OR2_PRELIM
+#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */
+#define	CFG_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
+#define CFG_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
+#define CFG_OR3_CAN		(CFG_CAN_OR_AM | OR_G5LA | OR_BI)
+#define CFG_BR3_CAN		((CFG_CAN_BASE & BR_BA_MSK) | \
+					BR_PS_8 | BR_MS_UPMB | BR_V )
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*
+ * Memory Periodic Timer Prescaler
+ *
+ * The Divider for PTA (refresh timer) configuration is based on an
+ * example SDRAM configuration (64 MBit, one bank). The adjustment to
+ * the number of chip selects (NCS) and the actually needed refresh
+ * rate is done by setting MPTPR.
+ *
+ * PTA is calculated from
+ *	PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
+ *
+ *	gclk	  CPU clock (not bus clock!)
+ *	Trefresh  Refresh cycle * 4 (four word bursts used)
+ *
+ * 4096  Rows from SDRAM example configuration
+ * 1000  factor s -> ms
+ *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
+ *    4  Number of refresh cycles per period
+ *   64  Refresh cycle in ms per number of rows
+ * --------------------------------------------
+ * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
+ *
+ * 50 MHz => 50.000.000 / Divider =  98
+ * 66 Mhz => 66.000.000 / Divider = 129
+ * 80 Mhz => 80.000.000 / Divider = 156
+ */
+#if   defined(CONFIG_80MHz)
+#define CFG_MAMR_PTA		156
+#elif defined(CONFIG_66MHz)
+#define CFG_MAMR_PTA		129
+#else		/*   50 MHz */
+#define CFG_MAMR_PTA		 98
+#endif	/*CONFIG_??MHz */
+
+/*
+ * For 16 MBit, refresh rates could be 31.3 us
+ * (= 64 ms / 2K = 125 / quad bursts).
+ * For a simpler initialization, 15.6 us is used instead.
+ *
+ * #define CFG_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
+ * #define CFG_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
+ */
+#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#define CONFIG_SCC1_ENET
+#define CONFIG_FEC_ENET
+#define CONFIG_ETHPRIME		"SCC ETHERNET"
+
+#endif	/* __CONFIG_H */

include/configs/TQM860L.h

@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000, 2001, 2002
+ * (C) Copyright 2000-2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -254,7 +254,7 @@
 #ifdef	CONFIG_80MHz	/* for 80 MHz, we use a 16 MHz clock * 5 */
 #define CFG_PLPRCR							\
 		( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
-#else			/* up to 50 MHz we use a 1:1 clock */
+#else			/* up to 66 MHz we use a 1:1 clock */
 #define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 #endif	/* CONFIG_80MHz */
 
@@ -270,7 +270,7 @@
 			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 			 SCCR_DFALCD00)
-#else			/* up to 50 MHz we use a 1:1 clock */
+#else			/* up to 66 MHz we use a 1:1 clock */
 #define CFG_SCCR	(SCCR_TBS     | \
 			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \

include/configs/TQM860M.h

@@ -0,0 +1,471 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC860		1	/* This is a MPC860 CPU		*/
+#define CONFIG_TQM860M		1	/* ...on a TQM8xxM module	*/
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+
+#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
+
+#define CONFIG_BOARD_TYPES	1	/* support board types		*/
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=$(serverip):$(rootpath)\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs $(bootargs) "				\
+		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"	\
+		":$(hostname):$(netdev):off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm $(kernel_addr)\0"				\
+	"flash_self=run ramargs addip;"					\
+		"bootm $(kernel_addr) $(ramdisk_addr)\0"		\
+	"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0"	\
+	"rootpath=/opt/eldk/ppc_8xx\0"					\
+	"bootfile=/tftpboot/TQM860M/uImage\0"				\
+	"kernel_addr=40080000\0"					\
+	"ramdisk_addr=40180000\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define	CONFIG_STATUS_LED	1	/* Status LED enabled		*/
+
+#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
+
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_ASKENV	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_IDE	| \
+				CFG_CMD_DATE	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
+
+#if 0
+#define	CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
+#endif
+#ifdef	CFG_HUSH_PARSER
+#define	CFG_PROMPT_HUSH_PS2	"> "
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE		1024	/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE		256	/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS		16	/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+
+#define	CFG_HZ			1000	/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xFFF00000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define	CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0x40000000
+#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define	CFG_ENV_IS_IN_FLASH	1
+#define	CFG_ENV_OFFSET		0x40000	/*   Offset   of Environment Sector	*/
+#define	CFG_ENV_SIZE		0x08000	/* Total Size of Environment Sector	*/
+#define	CFG_ENV_SECT_SIZE	0x20000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CFG_ENV_OFFSET_REDUND	(CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
+
+/*-----------------------------------------------------------------------
+ * Hardware Information Block
+ */
+#define CFG_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CFG_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
+#define CFG_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#ifndef	CONFIG_CAN_DRIVER
+#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#else	/* we must activate GPL5 in the SIUMCR for CAN */
+#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ *
+ * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
+ */
+#ifdef	CONFIG_80MHz	/* for 80 MHz, we use a 16 MHz clock * 5 */
+#define CFG_PLPRCR							\
+		( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
+#else			/* up to 66 MHz we use a 1:1 clock */
+#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+#endif	/* CONFIG_80MHz */
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#ifdef	CONFIG_80MHz	/* for 80 MHz, we use a 16 MHz clock * 5 */
+#define CFG_SCCR	(/* SCCR_TBS  | */ \
+			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+#else			/* up to 66 MHz we use a 1:1 clock */
+#define CFG_SCCR	(SCCR_TBS     | \
+			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+#endif	/* CONFIG_80MHz */
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
+#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O			*/
+#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers	*/
+#define CFG_ATA_ALT_OFFSET	0x0100
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_DER	0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #0	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+
+/*
+ * FLASH timing:
+ */
+#if   defined(CONFIG_80MHz)
+/* 80 MHz CPU - 40 MHz bus: ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */
+#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | 0       | OR_CSNT_SAM | \
+				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
+#elif defined(CONFIG_66MHz)
+/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
+#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
+#else		/*   50 MHz */
+/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
+#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+				 OR_SCY_2_CLK | OR_EHTR | OR_BI)
+#endif	/*CONFIG_??MHz */
+
+#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+
+#define CFG_OR1_REMAP	CFG_OR0_REMAP
+#define CFG_OR1_PRELIM	CFG_OR0_PRELIM
+#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
+
+/*
+ * BR2/3 and OR2/3 (SDRAM)
+ *
+ */
+#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
+#define SDRAM_BASE3_PRELIM	0x20000000	/* SDRAM bank #1	*/
+#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CFG_OR_TIMING_SDRAM	0x00000A00
+
+#define CFG_OR2_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
+#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+#ifndef	CONFIG_CAN_DRIVER
+#define	CFG_OR3_PRELIM	CFG_OR2_PRELIM
+#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */
+#define	CFG_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
+#define CFG_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
+#define CFG_OR3_CAN		(CFG_CAN_OR_AM | OR_G5LA | OR_BI)
+#define CFG_BR3_CAN		((CFG_CAN_BASE & BR_BA_MSK) | \
+					BR_PS_8 | BR_MS_UPMB | BR_V )
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*
+ * Memory Periodic Timer Prescaler
+ *
+ * The Divider for PTA (refresh timer) configuration is based on an
+ * example SDRAM configuration (64 MBit, one bank). The adjustment to
+ * the number of chip selects (NCS) and the actually needed refresh
+ * rate is done by setting MPTPR.
+ *
+ * PTA is calculated from
+ *	PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
+ *
+ *	gclk	  CPU clock (not bus clock!)
+ *	Trefresh  Refresh cycle * 4 (four word bursts used)
+ *
+ * 4096  Rows from SDRAM example configuration
+ * 1000  factor s -> ms
+ *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
+ *    4  Number of refresh cycles per period
+ *   64  Refresh cycle in ms per number of rows
+ * --------------------------------------------
+ * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
+ *
+ * 50 MHz => 50.000.000 / Divider =  98
+ * 66 Mhz => 66.000.000 / Divider = 129
+ * 80 Mhz => 80.000.000 / Divider = 156
+ */
+#if   defined(CONFIG_80MHz)
+#define CFG_MAMR_PTA		156
+#elif defined(CONFIG_66MHz)
+#define CFG_MAMR_PTA		129
+#else		/*   50 MHz */
+#define CFG_MAMR_PTA		 98
+#endif	/*CONFIG_??MHz */
+
+/*
+ * For 16 MBit, refresh rates could be 31.3 us
+ * (= 64 ms / 2K = 125 / quad bursts).
+ * For a simpler initialization, 15.6 us is used instead.
+ *
+ * #define CFG_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
+ * #define CFG_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
+ */
+#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#define CONFIG_SCC1_ENET
+#define CONFIG_FEC_ENET
+#define CONFIG_ETHPRIME		"SCC ETHERNET"
+
+#endif	/* __CONFIG_H */

include/configs/TQM862L.h

@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000, 2001, 2002
+ * (C) Copyright 2000-2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -258,7 +258,7 @@
 #if defined(CONFIG_80MHz) || defined(CONFIG_100MHz)
 #define CFG_PLPRCR							\
 		( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
-#else			/* up to 50 MHz we use a 1:1 clock */
+#else			/* up to 66 MHz we use a 1:1 clock */
 #define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 #endif	/* CONFIG_80MHz | CONFIG_100MHz */
 
@@ -274,7 +274,7 @@
 			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 			 SCCR_DFALCD00)
-#else			/* up to 50 MHz we use a 1:1 clock */
+#else			/* up to 66 MHz we use a 1:1 clock */
 #define CFG_SCCR	(SCCR_TBS     | \
 			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \

include/configs/TQM862M.h

@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000, 2001, 2002
+ * (C) Copyright 2000-2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -260,7 +260,7 @@
 #if defined(CONFIG_80MHz) || defined(CONFIG_100MHz)
 #define CFG_PLPRCR							\
 		( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
-#else			/* up to 50 MHz we use a 1:1 clock */
+#else			/* up to 66 MHz we use a 1:1 clock */
 #define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 #endif	/* CONFIG_80MHz | CONFIG_100MHz */
 
@@ -276,7 +276,7 @@
 			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 			 SCCR_DFALCD00)
-#else			/* up to 50 MHz we use a 1:1 clock */
+#else			/* up to 66 MHz we use a 1:1 clock */
 #define CFG_SCCR	(SCCR_TBS     | \
 			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \

include/configs/lwmon.h

@@ -189,9 +189,9 @@
 #define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
 
 #define	CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
-#endif
 #ifdef	CFG_HUSH_PARSER
 #define	CFG_PROMPT_HUSH_PS2	"> "
+#endif
 
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 #define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/

include/flash.h

@@ -160,6 +160,8 @@ extern int flash_real_protect(flash_info_t *info, long sector, int prot);
 
 #define AMD_ID_DL640	0x227E227E	/* 29DL640D ID (64 M, dual boot sectors)*/
 #define AMD_ID_MIRROR	0x227E227E	/* 1st ID word for MirrorBit family */
+#define AMD_ID_LV640U_2	0x220C220C	/* 2d ID word for AM29LV640M at 0x38 */
+#define AMD_ID_LV640U_3	0x22012201	/* 3d ID word for AM29LV640M at 0x3c */
 #define AMD_ID_LV128U_2 0x22122212	/* 2d ID word for AM29LV128M at 0x38 */
 #define AMD_ID_LV128U_3 0x22002200	/* 3d ID word for AM29LV128M at 0x3c */
 
@@ -314,7 +316,9 @@ extern int flash_real_protect(flash_info_t *info, long sector, int prot);
 #define FLASH_28F320C3B 0x009F		/* Intel 28F320C3B ( 32M = 2M x 16 )	*/
 #define FLASH_28F640C3T 0x00A0		/* Intel 28F640C3T ( 64M = 4M x 16 )	*/
 #define FLASH_28F640C3B 0x00A1		/* Intel 28F640C3B ( 64M = 4M x 16 )	*/
-#define FLASH_AMLV128U		0x00A2		/* AMD 29LV128M	   ( 128M = 8M x 16 )	*/
+#define FLASH_AMLV320U	0x00A2		/* AMD 29LV128M    ( 128M = 8M x 16 )	*/
+#define FLASH_AMLV640U	0x00A4		/* AMD 29LV640M    ( 64M = 4M x 16 )	*/
+#define FLASH_AMLV128U	0x00A6		/* AMD 29LV128M	   ( 128M = 8M x 16 )	*/
 
 #define FLASH_UNKNOWN	0xFFFF		/* unknown flash type			*/
 

include/version.h

@@ -24,6 +24,6 @@
 #ifndef	__VERSION_H__
 #define	__VERSION_H__
 
-#define	U_BOOT_VERSION	"U-Boot 0.4.1"
+#define	U_BOOT_VERSION	"U-Boot 0.4.2"
 
 #endif	/* __VERSION_H__ */

lib_generic/display_options.c

@@ -54,6 +54,11 @@ void print_size (ulong size, const char *s)
 
 	m = (10 * (size - (n * d)) + (d / 2) ) / d;
 
+	if (m >= 10) {
+		m -= 10;
+		n += 1;
+	}
+
 	printf ("%2ld", n);
 	if (m) {
 		printf (".%ld", m);