Patch by Raghu Krishnaprasad, 7 Aug 2003:

add support for Adder II MPC852T module

CHANGELOG

@@ -1,3 +1,205 @@
+======================================================================
+Changes for U-Boot 0.4.7:
+======================================================================
+
+* Patch by Raghu Krishnaprasad, 7 Aug 2003:
+  add support for Adder II MPC852T module
+
+* Patch by George G. Davis, 19 Aug 2003:
+  fix TI Innovator/OMAP1510 pin configs
+
+* Patches by Kshitij, 18 Aug 2003
+  - add support for arm926ejs cpu core
+  - add support for TI OMAP 1610 Innovator Board
+
+* Patch by Yuli Barcohen, 14 Aug 2003:
+  add support for bzip2 uncompression
+
+* Add GCC library to examples/Makefile so GCC utility functions will
+  be resolved, too
+
+* Add I2C and RTC support for RMU board using software I2C driver
+  (because of better response to iprobe command); fix problem with
+  "reset" command
+
+* Patch by Matthias Fuchs, 28 Aug 2003:
+  Added CONFIG_BOOTP_DNS2 and CONFIG_BOOTP_SEND_HOSTNAME to
+  CONFIG_BOOTP_MAKS (see README).
+
+* Fix ICU862 environment problem
+
+* Fix RAM size detection for RMU board
+
+* Implement "reset" for MGT5100/MPC5200 systems
+
+======================================================================
+Changes for U-Boot 0.4.6:
+======================================================================
+
+* Make Ethernet autonegotiation on INCA-IP work for all clock rates;
+  allow selection of clock frequency as "make" target
+
+* Implement memory autosizing code for IceCube boards
+
+* Configure network port on INCA-IP for autonegotiation
+
+* Fix overflow problem in network timeout code
+
+* Patch by Richard Woodruff, 8 Aug 2003:
+  Allow crc32 to be used at address 0x000 (crc32_no_comp, too).
+
+======================================================================
+Changes for U-Boot 0.4.5:
+======================================================================
+
+* Update for TQM board defaults:
+  disable clocks_in_mhz, enable boot count limit
+
+* Removed tools/gdb from "make all" target.  Added make target "gdbtools"
+  in toplevel directory instead.  Removed astest.c from tools/gdb because
+  it is no longer relevant.
+
+* Fix PCI support for MPC5200 / IceCube Board
+
+* Map ISP1362 USB OTG controller for NSCU board
+
+* Patch by Brad Parker, 02 Aug 2003:
+  fix sc520_cdp problems
+
+* Implement Boot Cycle Detection (Req. 2.3 of OSDL CGL Reqirements)
+
+* Allow erase command to cross flash bank boundaries
+
+* Patch by Scott McNutt, 21 Jul 2003:
+  Add support for LynuxWorks Kernel Downloadable Images (KDIs).
+  Both LynxOS and BlueCat linux KDIs are supported.
+
+* Patch by Richard Woodruff, 25 Jul 2003:
+  use more reliable reset for OMAP/925T
+
+* Patch by Nye Liu, 25 Jul 2003:
+  fix typo in mpc8xx.h
+
+* Patch by Richard Woodruff, 24 Jul 2003:
+  Fixes for cmd_nand.c:
+  - Fixed null dereferece which could result in incorrect ECC values.
+  - Added support for devices with no Ready/Busy signal hooked up.
+  - Added OMAP1510 read/write protect handling.
+  - Fixed nand.h's ECCPOS. A conflict existed with POS5 and badblock
+    for non-JFFS2.
+  - Switched default ECC to be JFFS2.
+
+* Allow crc32 to be used at address 0x000
+
+* Provide consistent interface to standalone applications to access
+  the 'global_data' structure
+  Provide a doc/README.standalone more useful to users/developers.
+
+* Make IceCube MGT5100 FEC driver work
+
+* Implement new mechanism to export U-Boot's functions to standalone
+  applications: instead of using (PPC-specific) system calls we now
+  use a jump table; please see doc/README.standalone for details
+
+* Patch by Dave Westwood, 24 Jul 2003:
+  added support for Unity OS (a proprietary OS)
+
+* Patch by Detlev Zundel, 23 Jul 2003:
+  add "imls" command to print flash table of contents
+
+* Fix cold boot detection for log buffer reset
+
+* Return error for invalid length specifiers with "cp.X" etc.
+
+* Fix startup problem on MIPS
+
+* Allow for CONFIG_SPLASH_SCREEN even when no explicit
+  bitmap support is configured
+
+* Patch by Bill Hargen, 18 Jul 2003:
+  - fix endinaness problem in cpu/mpc824x/drivers/i2c/i2c1.c
+
+* Patch by Denis Peter, 18 Jul 2003:
+  - fix memory configuration for MIP405T
+  - fix printout of baudrate for "loadb <loadaddr> <baudrate>"
+
+* Cleanup of TQM82xx configurations; use "official" board types
+  to make selection easier.
+
+* Patch by Martin Krause, 17 Jul 2003:
+  add delay to get I2C working with "imm" command and s3c24x0_i2c.c
+
+* Patch by Richard Woodruff, 17 July 03:
+  - Fixed bug in OMAP1510 baud rate divisor settings.
+
+* Patch by Nye Liu, 16 July 2003:
+  MPC860FADS fixes:
+  - add MPC86xADS support (uses MPC86xADS.h)
+  - add 866P/T core support (also MPC859T/MPC859DSL/MPC852T)
+    o PLPRCR changes
+    o BRG changes (EXTAL/XTAL restricted to 10MHz)
+    o don't trust gclk() software measurement by default, depend on
+      CONFIG_8xx_GCLK_FREQ
+  - add DRAM SIMM not installed detection
+  - use more "correct" SDRAM initialization sequence
+  - allow different SDRAM sizes (8xxADS has 8M)
+  - default DER is 0
+  - remove unused MAMR defines from FADS860T.h (all done in fads.c)
+  - rename MAMR/MBMR defines to be more consistent. Should eventually
+    be merged into MxMR to better reflect the PowerQUICC datasheet.
+
+* Patch by Yuli Barcohen, 16 Jul 2003:
+  support new Motorola PQ2FADS-ZU evaluation board which replaced
+  MPC8260ADS and MPC8266ADS
+
+======================================================================
+Changes for U-Boot 0.4.4:
+======================================================================
+
+* Add support for IceCube board (with MGT5100 and MPC5200 CPUs)
+
+* Add support for MGT5100 and MPC5200 processors
+
+* Patch by Lutz Dennig, 15 Jul 2003:
+  update for R360MPI board
+
+======================================================================
+Changes for U-Boot 0.4.3:
+======================================================================
+
+* Patches by Kshitij, 04 Jul 2003
+  - added support for arm925t cpu core
+  - added support for TI OMAP 1510 Innovator Board
+
+* Patches by Martin Krause, 14 Jul 2003:
+  - add I2C support for s3c2400 systems (trab board)
+  - (re-) add "ping" to command table
+
+* Fix handling of "slow" POST routines
+
+* Patches by Yuli Barcohen, 13 Jul 2003:
+  - Correct flash and JFFS2 support for MPC8260ADS
+  - fix PVR values and clock generation for PowerQUICC II family
+    (8270/8275/8280)
+
+* Patch by Bernhard Kuhn, 08 Jul 2003:
+  - add support for M68K targets
+
+* Patch by Ken Chou, 3 Jul:
+  - Fix PCI config table for A3000
+  - Fix iobase for natsemi.c
+    (PCI_BASE_ADDRESS_0 is the IO base register for DP83815)
+
+* Allow to enable "slow" POST routines by key press on power-on
+* Fix temperature dependend switching of LCD backlight on LWMON
+* Tweak output format for LWMON
+
+* Patch by Stefan Roese, 11 Jul 2003:
+  - Fix bug in CONFIG_VERSION_VARIABLE.
+  - AR405 config updated.
+  - OCRTC/ORSG: bsp command added.
+  - ASH405 bsp update.
+
 ======================================================================
 Changes for U-Boot 0.4.2:
 ======================================================================

MAINTAINERS

@@ -52,6 +52,8 @@ Wolfgang Denk <wd@denx.de>
 	FPS850L			MPC850
 	FPS860L			MPC860
 	ICU862			MPC862
+	IceCube_5100		MGT5100
+	IceCube_5200		MPC5200
 	IP860			MPC860
 	IVML24			MPC860
 	IVML24_128		MPC860
@@ -72,7 +74,6 @@ Wolfgang Denk <wd@denx.de>
 	TQM855L			MPC855
 	TQM860L			MPC860
 	TQM860L_FEC		MPC860
-	TTTech			MPC823
 	c2mon			MPC855
 	hermes			MPC860
 	lwmon			MPC823
@@ -275,6 +276,10 @@ Gary Jennejohn <gj@denx.de>
 	smdk2400		ARM920T
 	trab			ARM920T
 
+Kshitij Gupta <kshitij@ti.com>
+	omap1510inn		ARM925T
+	omap1610inn		ARM926EJS
+
 David Müller <d.mueller@elsoft.ch>
 
 	smdk2410		ARM920T

MAKEALL

@@ -18,25 +18,34 @@ LIST_5xx="	\
 	cmi_mpc5xx							\
 "
 
+#########################################################################
+## MPC5xxx Systems
+#########################################################################
+
+LIST_5xxx="	\
+	IceCube_5100	IceCube_5200					\
+"
+
 #########################################################################
 ## MPC8xx Systems
 #########################################################################
 
 LIST_8xx="	\
-	ADS860		AMX860		c2mon		CCM		\
-	cogent_mpc8xx	ESTEEM192E	ETX094		ELPT860		\
-	FADS823		FADS850SAR	FADS860T	FLAGADM		\
-	FPS850L		GEN860T		GEN860T_SC	GENIETV		\
-	GTH		hermes		IAD210		ICU862_100MHz	\
-	IP860		IVML24		IVML24_128	IVML24_256	\
-	IVMS8		IVMS8_128	IVMS8_256	KUP4K           \
-	LANTEC	        lwmon   	MBX		MBX860T		\
-	MHPC		MVS1		NETVIA		NETVIA_V2	\
-	NX823		pcu_e		R360MPI		RBC823		\
-	rmu		RPXClassic	RPXlite		RRvision	\
-	SM850		SPD823TS	svm_sc8xx	SXNI855T	\
-	TOP860		TQM823L		TQM823L_LCD	TQM850L		\
-	TQM855L		TQM860L		TTTech		v37		\
+	AdderII		ADS860		AMX860		c2mon		\
+	CCM		cogent_mpc8xx	ESTEEM192E	ETX094		\
+	ELPT860		FADS823		FADS850SAR	FADS860T	\
+	FLAGADM		FPS850L		GEN860T		GEN860T_SC	\
+	GENIETV		GTH		hermes		IAD210		\
+	ICU862_100MHz	IP860		IVML24		IVML24_128	\
+	IVML24_256	IVMS8		IVMS8_128	IVMS8_256	\
+	KUP4K           LANTEC	        lwmon   	MBX		\
+	MBX860T		MHPC		MPC86xADS	MVS1		\
+	NETVIA		NETVIA_V2	NX823		pcu_e		\
+	R360MPI		RBC823		rmu		RPXClassic	\
+	RPXlite		RRvision	SM850		SPD823TS	\
+	svm_sc8xx	SXNI855T	TOP860		TQM823L		\
+	TQM823L_LCD	TQM850L		TQM855L		TQM860L		\
+	v37								\
 "
 
 #########################################################################
@@ -45,9 +54,9 @@ LIST_8xx="	\
 
 LIST_4xx="	\
 	ADCIOP		AR405		ASH405          BUBINGA405EP    \
-        CANBT		CPCI405		CPCI4052 	CPCI405AB       \
+	CANBT		CPCI405		CPCI4052 	CPCI405AB       \
 	CPCI440         CPCIISER4	CRAYL1  	DASA_SIM	\
-        DU405    	EBONY           ERIC  		EXBITGEN	\
+	DU405    	EBONY           ERIC  		EXBITGEN	\
 	MIP405  	MIP405T		ML2		OCRTC		\
 	ORSG		PCI405		PIP405		PMC405          \
 	W7OLMC		W7OLMG          WALNUT405			\
@@ -72,7 +81,7 @@ LIST_8260="	\
 	gw8260		hymod		IPHASE4539	MPC8260ADS	\
 	MPC8266ADS	PM826		ppmc8260	RPXsuper	\
 	rsdproto	sacsng		sbc8260		SCM		\
-	TQM8260								\
+	TQM8260_AC	TQM8260_AD	TQM8260_AE			\
 "
 
 #########################################################################
@@ -87,7 +96,8 @@ LIST_7xx="	\
 	BAB7xx		ELPPC						\
 "
 
-LIST_ppc="${LIST_5xx}  ${LIST_8xx}  \
+LIST_ppc="${LIST_5xx}  ${LIST_5xxx} \
+	  ${LIST_8xx}  \
 	  ${LIST_824x} ${LIST_8260} \
 	  ${LIST_4xx}		    \
 	  ${LIST_74xx} ${LIST_7xx}"
@@ -108,7 +118,11 @@ LIST_ARM7="ep7312 impa7"
 ## ARM9 Systems
 #########################################################################
 
-LIST_ARM9="at91rm9200dk smdk2400 smdk2410 trab VCMA9"
+LIST_ARM9="	\
+	at91rm9200dk	omap1510inn	omap1610inn			\
+	smdk2400	smdk2410	trab				\
+	VCMA9								\
+"
 
 #########################################################################
 ## Xscale Systems
@@ -159,7 +173,7 @@ build_target() {
 for arg in $@
 do
 	case "$arg" in
-	5xx|8xx|824x|8260|4xx|7xx|74xx|SA|ARM7|ARM9|ppc|arm|pxa|mips|I486|x86)
+	5xx|5xxx|8xx|824x|8260|4xx|7xx|74xx|SA|ARM7|ARM9|ppc|arm|pxa|mips|I486|x86)
 			for target in `eval echo '$LIST_'${arg}`
 			do
 				build_target ${target}

Makefile

@@ -116,13 +116,12 @@ LIBS += post/libpost.a post/cpu/libcpu.a
 LIBS += common/libcommon.a
 LIBS += lib_generic/libgeneric.a
 
+#########################################################################
 #########################################################################
 
-all:		u-boot.srec u-boot.bin System.map
+ALL = u-boot.srec u-boot.bin System.map
 
-install:	all
-		-cp u-boot.bin /tftpboot/u-boot.bin
-		-cp u-boot.bin /net/denx/tftpboot/u-boot.bin
+all:		$(ALL)
 
 u-boot.srec:	u-boot
 		$(OBJCOPY) ${OBJCFLAGS} -O srec $< $@
@@ -130,6 +129,13 @@ u-boot.srec:	u-boot
 u-boot.bin:	u-boot
 		$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
 
+u-boot.img:	u-boot.bin
+		./tools/mkimage -A $(ARCH) -T firmware -C none \
+		-a $(TEXT_BASE) -e 0 \
+		-n $(shell sed -n -e 's/.*U_BOOT_VERSION//p' include/version.h | \
+			sed -e 's/"[	 ]*$$/ for $(BOARD) board"/') \
+		-d $< $@
+
 u-boot.dis:	u-boot
 		$(OBJDUMP) -d $< > $@
 
@@ -142,6 +148,9 @@ u-boot:		depend subdirs $(OBJS) $(LIBS) $(LDSCRIPT)
 subdirs:
 		@for dir in $(SUBDIRS) ; do $(MAKE) -C $$dir || exit 1 ; done
 
+gdbtools:
+		$(MAKE) -C tools/gdb || exit 1
+
 depend dep:
 		@for dir in $(SUBDIRS) ; do $(MAKE) -C $$dir .depend ; done
 
@@ -181,10 +190,29 @@ unconfig:
 cmi_mpc5xx_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc5xx cmi
 
+#########################################################################
+## MPC5xxx Systems
+#########################################################################
+IceCube_5200_config	\
+IceCube_5100_config:		unconfig
+	@ >include/config.h
+	@[ -z "$(findstring _5200,$@)" ] || \
+		{ echo "#define CONFIG_MPC5200"		>>include/config.h ; \
+		  echo "... with MPC5200 processor" ; \
+		}
+	@[ -z "$(findstring _5100,$@)" ] || \
+		{ echo "#define CONFIG_MGT5100"		>>include/config.h ; \
+		  echo "... with MGT5100 processor" ; \
+		}
+	@./mkconfig -a IceCube ppc mpc5xxx icecube
+
 #########################################################################
 ## MPC8xx Systems
 #########################################################################
 
+AdderII_config:	unconfig
+	@./mkconfig $(@:_config=) ppc mpc8xx adderII
+
 ADS860_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx fads
 
@@ -211,6 +239,7 @@ ETX094_config	:	unconfig
 
 FADS823_config	\
 FADS850SAR_config \
+MPC86xADS_config \
 FADS860T_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx fads
 
@@ -391,6 +420,12 @@ TQM860L_80MHz_config	\
 TQM862L_config		\
 TQM862L_66MHz_config	\
 TQM862L_80MHz_config	\
+TQM823M_config		\
+TQM823M_66MHz_config	\
+TQM823M_80MHz_config	\
+TQM850M_config		\
+TQM850M_66MHz_config	\
+TQM850M_80MHz_config	\
 TQM855M_config		\
 TQM855M_66MHz_config	\
 TQM855M_80MHz_config	\
@@ -645,32 +680,48 @@ sbc8260_config:	unconfig
 SCM_config:		unconfig
 	@./mkconfig $(@:_config=) ppc mpc8260 SCM siemens
 
-TQM8255_config	\
-TQM8260_config	\
-TQM8260_L2_config	\
-TQM8255_266MHz_config	\
-TQM8260_266MHz_config	\
-TQM8260_L2_266MHz_config \
-TQM8255_300MHz_config	\
-TQM8260_300MHz_config:	unconfig
-	@ >include/config.h
-	@if [ "$(findstring _L2_,$@)" ] ; then \
+TQM8255_AA_config \
+TQM8260_AA_config \
+TQM8260_AB_config \
+TQM8260_AC_config \
+TQM8260_AD_config \
+TQM8260_AE_config \
+TQM8260_AF_config \
+TQM8260_AG_config \
+TQM8260_AH_config \
+TQM8265_AA_config:  unconfig
+	@case "$@" in \
+	TQM8255_AA_config) CTYPE=MPC8255; CFREQ=300; CACHE=no;  BMODE=8260;;  \
+	TQM8260_AA_config) CTYPE=MPC8260; CFREQ=200; CACHE=no;  BMODE=8260;; \
+	TQM8260_AB_config) CTYPE=MPC8260; CFREQ=200; CACHE=yes; BMODE=60x;;  \
+	TQM8260_AC_config) CTYPE=MPC8260; CFREQ=200; CACHE=yes; BMODE=60x;;  \
+	TQM8260_AD_config) CTYPE=MPC8260; CFREQ=300; CACHE=no;  BMODE=60x;;  \
+	TQM8260_AE_config) CTYPE=MPC8260; CFREQ=266; CACHE=no;  BMODE=8260;; \
+	TQM8260_AF_config) CTYPE=MPC8260; CFREQ=300; CACHE=no;  BMODE=60x;;  \
+	TQM8260_AG_config) CTYPE=MPC8260; CFREQ=300; CACHE=no;  BMODE=8260;; \
+	TQM8260_AH_config) CTYPE=MPC8260; CFREQ=300; CACHE=yes; BMODE=60x;;  \
+	TQM8265_AA_config) CTYPE=MPC8265; CFREQ=300; CACHE=no;  BMODE=60x;;  \
+	esac; \
+	>include/config.h ; \
+	if [ "$${CTYPE}" != "MPC8260" ] ; then \
+		echo "#define CONFIG_$${CTYPE}"	>>include/config.h ; \
+	fi; \
+	echo "#define CONFIG_$${CFREQ}MHz"	>>include/config.h ; \
+	echo "... with $${CFREQ}MHz system clock" ; \
+	if [ "$${CACHE}" == "yes" ] ; then \
 		echo "#define CONFIG_L2_CACHE"	>>include/config.h ; \
-		echo "... with L2 Cache support (60x Bus Mode)" ; \
+		echo "... with L2 Cache support" ; \
 	else \
 		echo "#undef CONFIG_L2_CACHE"	>>include/config.h ; \
 		echo "... without L2 Cache support" ; \
+	fi; \
+	if [ "$${BMODE}" == "60x" ] ; then \
+		echo "#define CONFIG_BUSMODE_60x" >>include/config.h ; \
+		echo "... with 60x Bus Mode" ; \
+	else \
+		echo "#undef CONFIG_BUSMODE_60x"  >>include/config.h ; \
+		echo "... without 60x Bus Mode" ; \
 	fi
-	@[ -z "$(findstring _266MHz,$@)" ] || \
-		{ echo "#define CONFIG_266MHz"	>>include/config.h ; \
-		  echo "... with 266MHz system clock" ; \
-		}
-	@[ -z "$(findstring _300MHz,$@)" ] || \
-		{ echo "#define CONFIG_300MHz"	>>include/config.h ; \
-		  echo "... with 300MHz system clock" ; \
-		}
-	@[ -z "$(findstring TQM8255_,$@)" ] || \
-		{ echo "#define CONFIG_MPC8255"	>>include/config.h ; }
 	@./mkconfig -a TQM8260 ppc mpc8260 tqm8260
 
 atc_config:	unconfig
@@ -720,11 +771,17 @@ shannon_config	:	unconfig
 	@./mkconfig $(@:_config=) arm sa1100 shannon
 
 #########################################################################
-## ARM920T Systems
+## ARM92xT Systems
 #########################################################################
 
 xtract_trab = $(subst _big_flash,,$(subst _config,,$1))
 
+omap1510inn_config :	unconfig
+	@./mkconfig $(@:_config=) arm arm925t omap1510inn
+
+omap1610inn_config :	unconfig
+	@./mkconfig $(@:_config=) arm arm926ejs omap1610inn
+
 smdk2400_config	:	unconfig
 	@./mkconfig $(@:_config=) arm arm920t smdk2400
 
@@ -797,8 +854,30 @@ sc520_spunk_rel_config	:	unconfig
 ## MIPS32 4Kc
 #########################################################################
 
-incaip_config :		unconfig
-	@./mkconfig $(@:_config=) mips mips incaip
+xtract_incaip = $(subst _100MHz,,$(subst _133MHz,,$(subst _150MHz,,$(subst _config,,$1))))
+
+incaip_100MHz_config	\
+incaip_133MHz_config	\
+incaip_150MHz_config	\
+incaip_config: unconfig
+	@ >include/config.h
+	@[ -z "$(findstring _100MHz,$@)" ] || \
+		{ echo "#define CPU_CLOCK_RATE 100000000" >>include/config.h ; \
+		  echo "... with 100MHz system clock" ; \
+		}
+	@[ -z "$(findstring _133MHz,$@)" ] || \
+		{ echo "#define CPU_CLOCK_RATE 133000000" >>include/config.h ; \
+		  echo "... with 133MHz system clock" ; \
+		}
+	@[ -z "$(findstring _150MHz,$@)" ] || \
+		{ echo "#define CPU_CLOCK_RATE 150000000" >>include/config.h ; \
+		  echo "... with 150MHz system clock" ; \
+		}
+	@./mkconfig -a $(call xtract_incaip,$@) mips mips incaip
+
+#########################################################################
+## MIPS64 5Kc
+#########################################################################
 
 purple_config :		unconfig
 	@./mkconfig $(@:_config=) mips mips purple
@@ -828,7 +907,7 @@ clobber:	clean
 		| xargs rm -f
 	rm -f $(OBJS) *.bak tags TAGS
 	rm -fr *.*~
-	rm -f u-boot u-boot.bin u-boot.srec u-boot.map System.map
+	rm -f u-boot u-boot.map $(ALL)
 	rm -f tools/crc32.c tools/environment.c tools/env/crc32.c
 	rm -f tools/inca-swap-bytes cpu/mpc824x/bedbug_603e.c
 	rm -f include/asm/proc include/asm/arch include/asm

README

@@ -140,12 +140,15 @@ Directory Hierarchy:
 - tools		Tools to build S-Record or U-Boot images, etc.
 
 - cpu/74xx_7xx	Files specific to Motorola MPC74xx and 7xx CPUs
+- cpu/arm925t	Files specific to ARM	   925	   CPUs
+- cpu/arm926ejs	Files specific to ARM	926	CPUs
 - cpu/mpc5xx	Files specific to Motorola MPC5xx  CPUs
 - cpu/mpc8xx	Files specific to Motorola MPC8xx  CPUs
 - cpu/mpc824x	Files specific to Motorola MPC824x CPUs
 - cpu/mpc8260	Files specific to Motorola MPC8260 CPU
 - cpu/ppc4xx	Files specific to IBM	   4xx	   CPUs
 
+
 - board/LEOX/   Files specific to boards manufactured by The LEOX team
 - board/LEOX/elpt860	Files specific to ELPT860 boards
 - board/RPXClassic
@@ -195,7 +198,7 @@ Directory Hierarchy:
 - board/lwmon	Files specific to LWMON	     boards
 - board/mbx8xx	Files specific to MBX	     boards
 - board/mpc8260ads
-		Files specific to MMPC8260ADS boards
+		Files specific to MPC8260ADS and PQ2FADS-ZU boards
 - board/mpl/	Files specific to boards manufactured by MPL
 - board/mpl/common	Common files for MPL boards
 - board/mpl/pip405	Files specific to PIP405     boards
@@ -204,6 +207,10 @@ Directory Hierarchy:
 - board/mvs1	Files specific to MVS1       boards
 - board/nx823   Files specific to NX823      boards
 - board/oxc	Files specific to OXC        boards
+- board/omap1510inn
+		Files specific to OMAP 1510 Innovator boards
+- board/omap1610inn  
+		Files specific to OMAP 1610 Innovator boards
 - board/pcippc2	Files specific to PCIPPC2/PCIPPC6 boards
 - board/pm826	Files specific to PM826      boards
 - board/ppmc8260
@@ -353,6 +360,7 @@ The following options need to be configured:
 
 		CONFIG_HHP_CRADLE,  CONFIG_DNP1110,    CONFIG_EP7312,
 		CONFIG_IMPA7,       CONFIG_LART,       CONFIG_LUBBOCK,
+		CONFIG_INNOVATOROMAP1510,	CONFIG_INNOVATOROMAP1610
 		CONFIG_SHANNON,     CONFIG_SMDK2400,   CONFIG_SMDK2410,
 		CONFIG_TRAB,	    CONFIG_AT91RM9200DK
 
@@ -378,6 +386,14 @@ The following options need to be configured:
 					  the lcd display every second with
 					  a "rotator" |\-/|\-/
 
+- Board flavour: (if CONFIG_MPC8260ADS is defined)
+		CONFIG_ADSTYPE
+		Possible values are:
+			CFG_8260ADS	- original MPC8260ADS
+			CFG_8266ADS	- MPC8266ADS (untested)
+			CFG_PQ2FADS	- PQ2FADS-ZU
+
+
 - MPC824X Family Member (if CONFIG_MPC824X is defined)
 	Define exactly one of
 	CONFIG_MPC8240, CONFIG_MPC8245
@@ -846,6 +862,16 @@ The following options need to be configured:
 		allows for a "silent" boot where a splash screen is
 		loaded very quickly after power-on.
 
+- Compression support:
+		CONFIG_BZIP2
+
+		If this option is set, support for bzip2 compressed
+		images is included. If not, only uncompressed and gzip
+		compressed images are supported.
+
+                NOTE: the bzip2 algorithm requires a lot of RAM, so
+                the malloc area (as defined by CFG_MALLOC_LEN) should
+                be at least 4MB.
 
 - Ethernet address:
 		CONFIG_ETHADDR
@@ -888,6 +914,29 @@ The following options need to be configured:
 		4th and following
 		BOOTP requests:		delay 0 ... 8 sec
 
+- DHCP Advanced Options:
+		CONFIG_BOOTP_MASK
+
+		You can fine tune the DHCP functionality by adding
+		these flags to the CONFIG_BOOTP_MASK define:
+
+		CONFIG_BOOTP_DNS2 - If a DHCP client requests the DNS
+		serverip from a DHCP server, it is possible that more
+		than one DNS serverip is offered to the client.
+		If CONFIG_BOOTP_DNS2 is enabled, the secondary DNS
+		serverip will be stored in the additional environment
+		variable "dnsip2". The first DNS serverip is always
+		stored in the variable "dnsip", when CONFIG_BOOTP_DNS
+		is added to the CONFIG_BOOTP_MASK.
+
+		CONFIG_BOOTP_SEND_HOSTNAME - Some DHCP servers are capable
+		to do a dynamic update of a DNS server. To do this, they
+		need the hostname of the DHCP requester.
+		If CONFIG_BOOP_SEND_HOSTNAME is added to the
+		CONFIG_BOOTP_MASK, the content of the "hostname"
+		environment variable is passed as option 12 to
+		the DHCP server.
+
 - Status LED:	CONFIG_STATUS_LED
 
 		Several configurations allow to display the current
@@ -908,35 +957,35 @@ The following options need to be configured:
 - I2C Support:	CONFIG_HARD_I2C | CONFIG_SOFT_I2C
 
 		These enable I2C serial bus commands. Defining either of
-		(but not both of) CONFIG_HARD_I2C or CONFIG_SOFT_I2C will 
-		include the appropriate I2C driver for the selected cpu. 
+		(but not both of) CONFIG_HARD_I2C or CONFIG_SOFT_I2C will
+		include the appropriate I2C driver for the selected cpu.
 
-		This will allow you to use i2c commands at the u-boot 
-		command line (as long as you set CFG_CMD_I2C in 
+		This will allow you to use i2c commands at the u-boot
+		command line (as long as you set CFG_CMD_I2C in
 		CONFIG_COMMANDS) and communicate with i2c based realtime
 		clock chips. See common/cmd_i2c.c for a description of the
 		command line interface.
 
-		CONFIG_HARD_I2C	selects the CPM hardware driver for I2C. 
+		CONFIG_HARD_I2C	selects the CPM hardware driver for I2C.
 
-		CONFIG_SOFT_I2C configures u-boot to use a software (aka 
+		CONFIG_SOFT_I2C configures u-boot to use a software (aka
 		bit-banging) driver instead of CPM or similar hardware
 		support for I2C.
 
-		There are several other quantities that must also be 
+		There are several other quantities that must also be
 		defined when you define CONFIG_HARD_I2C or CONFIG_SOFT_I2C.
 
 		In both cases you will need to define CFG_I2C_SPEED
-		to be the frequency (in Hz) at which you wish your i2c bus 
-		to run and CFG_I2C_SLAVE to be the address of this node (ie 
-		the cpu's i2c node address). 
-		
+		to be the frequency (in Hz) at which you wish your i2c bus
+		to run and CFG_I2C_SLAVE to be the address of this node (ie
+		the cpu's i2c node address).
+
 		Now, the u-boot i2c code for the mpc8xx (cpu/mpc8xx/i2c.c)
 		sets the cpu up as a master node and so its address should
 		therefore be cleared to 0 (See, eg, MPC823e User's Manual
-		p.16-473). So, set CFG_I2C_SLAVE to 0.  
+		p.16-473). So, set CFG_I2C_SLAVE to 0.
 
-		That's all that's required for CONFIG_HARD_I2C. 
+		That's all that's required for CONFIG_HARD_I2C.
 
 		If you use the software i2c interface (CONFIG_SOFT_I2C)
 		then the following macros need to be defined (examples are
@@ -984,8 +1033,8 @@ The following options need to be configured:
 		is FALSE, it clears it (low).
 
 		eg: #define I2C_SDA(bit) \
-		         if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
-		         else    immr->im_cpm.cp_pbdat &= ~PB_SDA
+			if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
+			else    immr->im_cpm.cp_pbdat &= ~PB_SDA
 
 		I2C_SCL(bit)
 
@@ -993,16 +1042,16 @@ The following options need to be configured:
 		is FALSE, it clears it (low).
 
 		eg: #define I2C_SCL(bit) \
-		         if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
-		         else    immr->im_cpm.cp_pbdat &= ~PB_SCL 
+			if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
+			else    immr->im_cpm.cp_pbdat &= ~PB_SCL
 
 		I2C_DELAY
 
 		This delay is invoked four times per clock cycle so this
 		controls the rate of data transfer.  The data rate thus
 		is 1 / (I2C_DELAY * 4). Often defined to be something
-		like: 
-		
+		like:
+
 		#define I2C_DELAY  udelay(2)
 
 		CFG_I2C_INIT_BOARD
@@ -1481,6 +1530,16 @@ Configuration Settings:
 - CFG_FLASH_WRITE_TOUT:
 		Timeout for Flash write operations (in ms)
 
+- CFG_FLASH_LOCK_TOUT
+		Timeout for Flash set sector lock bit operation (in ms)
+
+- CFG_FLASH_UNLOCK_TOUT
+		Timeout for Flash clear lock bits operation (in ms)
+
+- CFG_FLASH_PROTECTION
+		If defined, hardware flash sectors protection is used
+		instead of U-Boot software protection.
+
 - CFG_DIRECT_FLASH_TFTP:
 
 		Enable TFTP transfers directly to flash memory;
@@ -1672,9 +1731,10 @@ Low Level (hardware related) configuration options:
 
 - CFG_DEFAULT_IMMR:
 		Default address of the IMMR after system reset.
-		Needed on some 8260 systems (MPC8260ADS and RPXsuper)
-		to be able to adjust the position of the IMMR
-		register after a reset.
+
+                Needed on some 8260 systems (MPC8260ADS, PQ2FADS-ZU,
+                and RPXsuper) to be able to adjust the position of
+                the IMMR register after a reset.
 
 - Floppy Disk Support:
 		CFG_FDC_DRIVE_NUMBER
@@ -1847,8 +1907,8 @@ configurations; the following names are supported:
     GENIETV_config	  TQM823L_config	PIP405_config
     GEN860T_config	  EBONY_config		FPS860L_config
     ELPT860_config	  cmi_mpc5xx_config	NETVIA_config
-    at91rm9200dk_config
-
+    at91rm9200dk_config	  omap1510inn_config	MPC8260ADS_config
+    omap1610inn_config
 Note: for some board special configuration names may exist; check  if
       additional  information is available from the board vendor; for
       instance, the TQM8xxL systems run normally at 50 MHz and use  a
@@ -2094,6 +2154,7 @@ depending the information provided by your boot server:
 
   bootfile	- see above
   dnsip		- IP address of your Domain Name Server
+  dnsip2	- IP address of your secondary Domain Name Server
   gatewayip	- IP address of the Gateway (Router) to use
   hostname	- Target hostname
   ipaddr	- see above
@@ -2211,12 +2272,11 @@ defines the following image properties:
 * Target Operating System (Provisions for OpenBSD, NetBSD, FreeBSD,
   4.4BSD, Linux, SVR4, Esix, Solaris, Irix, SCO, Dell, NCR, VxWorks,
   LynxOS, pSOS, QNX, RTEMS, ARTOS;
-  Currently supported: Linux, NetBSD, VxWorks, QNX, RTEMS, ARTOS).
+  Currently supported: Linux, NetBSD, VxWorks, QNX, RTEMS, ARTOS, LynxOS).
 * Target CPU Architecture (Provisions for Alpha, ARM, Intel x86,
   IA64, MIPS, MIPS, PowerPC, IBM S390, SuperH, Sparc, Sparc 64 Bit;
   Currently supported: PowerPC).
-* Compression Type (Provisions for uncompressed, gzip, bzip2;
-  Currently supported: uncompressed, gzip).
+* Compression Type (uncompressed, gzip, bzip2)
 * Load Address
 * Entry Point
 * Image Name
@@ -3038,6 +3098,11 @@ it:
   version of diff does not support these options, then get the latest
   version of GNU diff.
 
+  The current directory when running this command shall be the top
+  level directory of the U-Boot source tree, or it's parent directory
+  (i. e. please make sure that your patch includes sufficient
+  directory information for the affected files).
+
   We accept patches as plain text, MIME attachments or as uuencoded
   gzipped text.
 

board/RRvision/video_ad7179.h

@@ -0,0 +1,68 @@
+/*
+ * (C) Copyright 2003 Wolfgang Grandegger <wg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define VIDEO_ENCODER_NAME	"Analog Devices AD7179"
+
+#define VIDEO_ENCODER_I2C_RATE	100000	/* Max rate is 100Khz	*/
+#define VIDEO_ENCODER_CB_Y_CR_Y		/* Use CB Y CR Y format...	*/
+
+#define VIDEO_MODE_YUYV		/* The only mode supported by this encoder	*/
+#undef	VIDEO_MODE_RGB
+#define VIDEO_MODE_BPP		16
+
+#ifdef	VIDEO_MODE_PAL
+#define VIDEO_ACTIVE_COLS	720
+#define VIDEO_ACTIVE_ROWS	576
+#define VIDEO_VISIBLE_COLS	640
+#define VIDEO_VISIBLE_ROWS	480
+#else
+#error "NTSC mode is not supported"
+#endif
+
+static unsigned char video_encoder_data[] = {
+				0x05, /* Mode Register 0 */
+				0x11, /* Mode Register 1 */
+				0x20, /* Mode Register 2 */
+				0x0C, /* Mode Register 3 */
+				0x01, /* Mode Register 4 */
+				0x00, /* Reserved */
+				0x00, /* Reserved */
+				0x04, /* Timing Register 0 */
+				0x00, /* Timing Register 1 */
+				0xCB, /* Subcarrier Frequency Register 0 */
+				0x0A, /* Subcarrier Frequency Register 1 */
+				0x09, /* Subcarrier Frequency Register 2 */
+				0x2A, /* Subcarrier Frequency Register 3 */
+				0x00, /* Subcarrier Phase */
+				0x00, /* Closed Captioning Ext Reg 0 */
+				0x00, /* Closed Captioning Ext Reg 1 */
+				0x00, /* Closed Captioning Reg 0 */
+				0x00, /* Closed Captioning Reg 1 */
+				0x00, /* Pedestal Control Reg 0 */
+				0x00, /* Pedestal Control Reg 1 */
+				0x00, /* Pedestal Control Reg 2 */
+				0x00, /* Pedestal Control Reg 3 */
+				0x00, /* CGMS_WSS Reg 0 */
+				0x00, /* CGMS_WSS Reg 0 */
+				0x00, /* CGMS_WSS Reg 0 */
+				0x00  /* Teletext Req. Control Reg */
+} ;

board/a3000/a3000.c

@@ -2,6 +2,9 @@
  * (C) Copyright 2001
  * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
  *
+ * Modified during 2003 by
+ * Ken Chou, kchou@ieee.org
+ *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
@@ -86,52 +89,42 @@ Done:
 /*
  * Initialize PCI Devices
  */
-#if 1
 #ifndef CONFIG_PCI_PNP
 static struct pci_config_table pci_a3000_config_table[] = {
-	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
-	  0x0, 0x0, 0x0, /* unknown eth0 divice */
+	/* vendor, device, class */
+	/* bus, dev, func */
+	{ PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_83815, PCI_ANY_ID,
+	  PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,	/* dp83815 eth0 divice */
 	  pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
 				       PCI_ENET0_MEMADDR,
 				       PCI_COMMAND_IO |
 				       PCI_COMMAND_MEMORY |
 				       PCI_COMMAND_MASTER }},
 	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
-	  0x0, 0x0, 0x0, /* unknown eth1 device */
+	  PCI_ANY_ID, 0x14, PCI_ANY_ID,		/* PCI slot1 */
 	  pci_cfgfunc_config_device, { PCI_ENET1_IOADDR,
 				       PCI_ENET1_MEMADDR,
 				       PCI_COMMAND_IO |
 				       PCI_COMMAND_MEMORY |
 				       PCI_COMMAND_MASTER }},
 	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
-	  0x0, 0x0, 0x0, /* unknown eth1 device */
+	  PCI_ANY_ID, 0x15, PCI_ANY_ID, 	/* PCI slot2 */
 	  pci_cfgfunc_config_device, { PCI_ENET2_IOADDR,
 				       PCI_ENET2_MEMADDR,
 				       PCI_COMMAND_IO |
 				       PCI_COMMAND_MEMORY |
 				       PCI_COMMAND_MASTER }},
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+	  PCI_ANY_ID, 0x16, PCI_ANY_ID,		/* PCI slot3 */
+	  pci_cfgfunc_config_device, { PCI_ENET3_IOADDR,
+				       PCI_ENET3_MEMADDR,
+				       PCI_COMMAND_IO |
+				       PCI_COMMAND_MEMORY |
+				       PCI_COMMAND_MASTER }},
 	{ }
 };
 #endif
 
-#else
-
-#ifndef CONFIG_PCI_PNP
-static struct pci_config_table pci_a3000_config_table[] = {
-	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
-	  pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
-				       PCI_ENET0_MEMADDR,
-				       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
-	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x10, PCI_ANY_ID,
-	  pci_cfgfunc_config_device, { PCI_ENET1_IOADDR,
-				       PCI_ENET1_MEMADDR,
-				       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
-	{ }
-};
-#endif
-
-#endif
-
 struct pci_controller hose = {
 #ifndef CONFIG_PCI_PNP
 	config_table: pci_a3000_config_table,

board/adderII/Makefile

@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################

board/adderII/adderII.c

@@ -0,0 +1,189 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#include <mpc8xx.h>
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard( void )
+{
+	puts("Board: ");
+	puts("AdderII(MPC852T)\n" );
+
+  	return 0;
+}
+
+#if defined( CONFIG_SDRAM_50MHZ )
+
+/******************************************************************************
+** for chip Samsung K4S643232F - T70
+** this table is for 32-50MHz operation
+*******************************************************************************/
+
+#define SDRAM_MPTPRVALUE 	0x0200
+
+#define SDRAM_MAMRVALUE0 	0x00802114   /* refresh at 32MHz */
+#define SDRAM_MAMRVALUE1 	0x00802118
+
+#define SDRAM_OR1VALUE   	0xff800e00
+#define SDRAM_BR1VALUE   	0x00000081
+
+#define SDRAM_MARVALUE		94
+
+#define SDRAM_MCRVALUE0  	0x80808105
+#define SDRAM_MCRVALUE1  	0x80808130
+
+const uint sdram_table[] = {
+
+	/* single read   (offset 0x00 in upm ram) */
+       	0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xe0bbbc00,
+       	0x10f77c44, 0xf3fffc07, 0xfffffc04, 0xfffffc04,
+
+	/* burst read    (offset 0x08 in upm ram) */
+       	0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xf0affc00,
+       	0xf0affc00, 0xf0affc00, 0xf0affc00, 0x10a77c44,
+       	0xf7bffc47, 0xfffffc35, 0xfffffc34, 0xfffffc35,
+       	0xfffffc35, 0x1ff77c35, 0xfffffc34, 0x1fb57c35,
+
+	/* single write  (offset 0x18 in upm ram) */
+       	0x1f27fc24, 0xe0aebc04, 0x00b93c00, 0x13f77c47,
+       	0xfffdfc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+
+	/* burst write   (offset 0x20 in upm ram) */
+       	0x1f07fc24, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
+       	0xf0affc00, 0xe0abbc00, 0x1fb77c47, 0xfffffc04,
+       	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+       	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+
+	/* refresh       (offset 0x30 in upm ram) */
+       	0x1ff5fca4, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+       	0xfffffc84, 0xfffffc07, 0xfffffc04, 0xfffffc04,
+       	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+
+	/* exception     (offset 0x3C in upm ram) */
+       	0xfffffc27, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+};
+
+#else
+#error SDRAM not correctly configured
+#endif
+
+int _initsdram (uint base, uint noMbytes)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	if (noMbytes != 8) {
+		return -1;
+	}
+
+	upmconfig (UPMA, (uint *) sdram_table,
+		   sizeof (sdram_table) / sizeof (uint));
+
+	memctl->memc_mptpr = SDRAM_MPTPRVALUE;
+
+	/* Configure the refresh (mostly).  This needs to be
+	 * based upon processor clock speed and optimized to provide
+	 * the highest level of performance.  For multiple banks,
+	 * this time has to be divided by the number of banks.
+	 * Although it is not clear anywhere, it appears the
+	 * refresh steps through the chip selects for this UPM
+	 * on each refresh cycle.
+	 * We have to be careful changing
+	 * UPM registers after we ask it to run these commands.
+	 */
+
+	memctl->memc_mamr = (SDRAM_MAMRVALUE0 | (SDRAM_MARVALUE << 24));
+	memctl->memc_mar = 0x0;
+	udelay (200);
+
+	/* Now run the precharge/nop/mrs commands.
+	 */
+	memctl->memc_mcr = 0x80002115;
+	udelay (200);
+
+	/* Run 8 refresh cycles */
+	memctl->memc_mcr = 0x80002380;
+	udelay (200);
+
+	memctl->memc_mar = 0x88;
+	udelay (200);
+
+	memctl->memc_mcr = 0x80002116;
+	udelay (200);
+
+	memctl->memc_or1 = SDRAM_OR1VALUE;
+	memctl->memc_br1 = SDRAM_BR1VALUE | base;
+
+	return 0;
+}
+
+void _sdramdisable( void )
+{
+	volatile immap_t     *immap = (immap_t *)CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	memctl->memc_br1 = 0x00000000;
+
+	/* maybe we should turn off upma here or something */
+}
+
+int initsdram (uint base, uint * noMbytes)
+{
+	uint m = 8;
+
+	*noMbytes = m;
+
+	if (!_initsdram (base, m)) {
+		return 0;
+	} else {
+		_sdramdisable ();
+		return -1;
+	}
+}
+
+long int initdram (int board_type)
+{
+	/* AdderII: has 8MB SDRAM */
+	uint sdramsz;
+	uint m = 0;
+
+	if (!initsdram (0x00000000, &sdramsz)) {
+		m += sdramsz;
+	} else {
+		return -1;
+	}
+	return (m << 20);
+}
+
+int testdram (void)
+{
+	/* TODO: XXX XXX XXX not an actual SDRAM test */
+	printf ("Test: 8MB SDRAM\n");
+
+	return (0);
+}

board/adderII/adderII.h

@@ -0,0 +1,45 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/****************************************************************************
+ * FLASH Memory Map as used by FADS Monitor:
+ *
+ *                          Start Address    Length
+ * +-----------------------+ 0xFE00_0000     Start of Flash -----------------
+ * | MON8xx code           | 0xFE00_0100     Reset Vector
+ * +-----------------------+ 0xFE0?_????
+ * | (unused)              |
+ * +-----------------------+
+ * | 			   |
+ * +-----------------------+
+ * | 			   |
+ * +-----------------------+
+ * | 			   |
+ * +-----------------------+
+ * | 			   |
+ * +=======================+
+ * | 			   |
+ * | ...                   |
+ *****************************************************************************/
+
+

board/adderII/config.mk

@@ -0,0 +1,29 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# AdderII board ( Analogue-Micro )
+#
+
+TEXT_BASE = 0xFE000000
+

board/adderII/flash.c

@@ -0,0 +1,501 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+/******************************************************************************
+** Notes: AM29LV320DB - 90EI ( 32 Mbit device )
+** Sectors - Eight 8 Kb sector
+** 	   - Sixty three 64 Kb sector
+** Bottom boot sector
+******************************************************************************/
+#include <common.h>
+#include <mpc8xx.h>
+
+
+/******************************************************************************
+**	Defines
+******************************************************************************/
+#ifdef CONFIG_ADDERII
+
+#define ADDR0	0x0555
+#define ADDR1	0x02AA
+#define FLASH_WORD_SIZE unsigned short
+
+#endif
+
+#if defined( CFG_ENV_IS_IN_FLASH )
+# ifndef  CFG_ENV_ADDR
+#  define CFG_ENV_ADDR  ( CFG_FLASH_BASE + CFG_ENV_OFFSET )
+# endif
+# ifndef  CFG_ENV_SIZE
+#  define CFG_ENV_SIZE  CFG_ENV_SECT_SIZE
+# endif
+# ifndef  CFG_ENV_SECT_SIZE
+#  define CFG_ENV_SECT_SIZE  CFG_ENV_SIZE
+# endif
+#endif
+
+/******************************************************************************
+**	Global Parameters
+******************************************************************************/
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+/******************************************************************************
+**	Function Prototypes
+******************************************************************************/
+static ulong flash_get_size( vu_long *addr, flash_info_t *info );
+
+static int write_word( flash_info_t *info, ulong dest, ulong data );
+
+static void flash_get_offsets( ulong base, flash_info_t *info );
+
+int wait_for_DQ7( flash_info_t *info, int sect );
+
+/******************************************************************************
+** Function :	flash_init
+** Param    :   void
+** Notes    :   Initializes the Flash Chip
+******************************************************************************/
+ulong flash_init (void)
+{
+	ulong size_b0 = -1;
+	int i;
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	/* Set Flash to unknown */
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Get the Flash Bank Size */
+
+	size_b0 = flash_get_size ((vu_long *) (CFG_FLASH_BASE),
+				  &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## UNKNOWN Flash on Bank 0 - Size = 0x%08lx = %ldMB\n",
+			size_b0, size_b0 >> 20);
+	}
+
+	/* Remap Flash according to size detected  */
+	memctl->memc_or0 = 0xFF800774;
+	memctl->memc_br0 = CFG_BR0_PRELIM;
+
+	/* Setup Flash Sector Offsets */
+
+	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+
+	/* Monitor Protection ON - default */
+
+#if ( CFG_MONITOR_BASE >= CFG_FLASH_BASE  )
+	flash_protect (FLAG_PROTECT_SET, CFG_MONITOR_BASE,
+		       (CFG_MONITOR_BASE + monitor_flash_len - 1),
+		       &flash_info[0]);
+#endif
+
+	/* Protect Environment Variables */
+#ifdef CFG_ENV_IS_IN_FLASH
+	flash_protect (FLAG_PROTECT_SET, CFG_ENV_ADDR,
+		       (CFG_ENV_ADDR + CFG_ENV_SIZE - 1), &flash_info[0]);
+#endif
+
+	return size_b0;
+}
+
+/******************************************************************************
+** Function : flash_get_offsets
+** Param    : ulong base, flash_into_t *info
+** Notes    :
+******************************************************************************/
+static void flash_get_offsets (ulong base, flash_info_t * info)
+{
+	return;
+}
+
+
+/******************************************************************************
+** Function : flash_print_info
+** Param    : flash_info_t
+** Notes    :
+******************************************************************************/
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("Missing or unknown flash type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:
+		printf ("AMD ");
+		break;
+	case FLASH_MAN_FUJ:
+		printf ("FUJITSU ");
+		break;
+	case FLASH_MAN_BM:
+		printf ("BRIGHT MICRO ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM320B:
+		printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM320T:
+		printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n", info->size >> 20,
+		info->sector_count);
+	printf ("  Sector Start Addresses:");
+
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+/******************************************************************************
+** Function : flash_get_size
+** Param    : vu_long *addr, flash_info_t *info
+** Notes    :
+******************************************************************************/
+static ulong flash_get_size (vu_long * addr, flash_info_t * info)
+{
+	short i;
+	FLASH_WORD_SIZE manu_id, dev_id;
+	ulong base = (ulong) addr;
+	volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) addr;
+
+	/* Write Auto Select Command and read Manufacturer's ID and Dev ID */
+
+	addr2[ADDR0] = (FLASH_WORD_SIZE) 0xAAAAAAAA;
+	addr2[ADDR1] = (FLASH_WORD_SIZE) 0x55555555;
+	addr2[ADDR0] = (FLASH_WORD_SIZE) 0x90909090;
+
+	manu_id = addr2[0];
+
+	switch (manu_id) {
+	case (FLASH_WORD_SIZE) AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		break;
+	}
+
+	/* Read Device Id */
+	dev_id = addr2[1];
+
+	switch (dev_id) {
+	case (FLASH_WORD_SIZE) AMD_ID_LV320B:
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 71;	/* 8 - boot sec + 63 normal */
+		info->size = 0x400000;	/* 4MByte */
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	/* Set up sector start Addresses */
+
+	if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block
+		 ** Eight 8 Kb Boot sectors
+		 ** Sixty Three 64Kb sectors
+		 */
+		for (i = 0; i < 8; i++) {
+			info->start[i] = base + (i * 0x00002000);
+		}
+		for (i = 8; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000) - 0x00070000;
+		}
+	}
+
+	/* Reset To read mode */
+
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr = (ulong *) info->start[0];
+		*addr = 0xF0F0F0F0;
+	}
+	return (info->size);
+}
+
+/*******************************************************************************
+** Function : flash_erase
+** Param    : flash_info_t *info, int s_first, int s_last
+** Notes    :
+******************************************************************************/
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]);
+	volatile FLASH_WORD_SIZE *addr2;
+	int flag, prot, sect, l_sect;
+	int i;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr2 = (FLASH_WORD_SIZE *) (info->start[sect]);
+
+			if ((info->flash_id & FLASH_VENDMASK) ==
+			    FLASH_MAN_SST) {
+				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080;
+				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+				addr2[0] = (FLASH_WORD_SIZE) 0x00500050;	/* block erase */
+				for (i = 0; i < 50; i++)
+					udelay (1000);	/* wait 1 ms */
+			} else {
+				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080;
+				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+				addr2[0] = (FLASH_WORD_SIZE) 0x00300030;	/* sector erase */
+			}
+			l_sect = sect;
+			/*
+			 * Wait for each sector to complete, it's more
+			 * reliable.  According to AMD Spec, you must
+			 * issue all erase commands within a specified
+			 * timeout.  This has been seen to fail, especially
+			 * if printf()s are included (for debug)!!
+			 */
+			wait_for_DQ7 (info, sect);
+		}
+	}
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/* reset to read mode */
+	addr = (FLASH_WORD_SIZE *) info->start[0];
+	addr[0] = (FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
+
+	printf (" done\n");
+	return 0;
+}
+
+int wait_for_DQ7 (flash_info_t * info, int sect)
+{
+	ulong start, now, last;
+	volatile FLASH_WORD_SIZE *addr =
+		(FLASH_WORD_SIZE *) (info->start[sect]);
+
+	start = get_timer (0);
+	last = start;
+	while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) !=
+	       (FLASH_WORD_SIZE) 0x00800080) {
+		if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return -1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {
+			putc ('.');
+			last = now;
+		}
+	}
+	return 0;
+}
+
+
+/******************************************************************************
+** Function : write_buff
+** Param    : flash_info_t *info, uchar *src, ulong addr, ulong cnt
+** Notes    :
+******************************************************************************/
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	/* get lower word aligned address */
+	wp = (addr & ~3);
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < 4 && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < 4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i = 0; i < 4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < 4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_word (info, wp, data));
+}
+
+
+/******************************************************************************
+** Function : write_word
+** Param    : flash_info_t *info, ulong dest, ulong data
+** Notes    :
+******************************************************************************/
+static int write_word (flash_info_t * info, ulong dest, ulong data)
+{
+	volatile FLASH_WORD_SIZE *addr2 =
+		(FLASH_WORD_SIZE *) (info->start[0]);
+	volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest;
+	volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data;
+	ulong start;
+	int i;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((volatile FLASH_WORD_SIZE *) dest) &
+	     (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
+		return (2);
+	}
+
+	for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) {
+		int flag;
+
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts ();
+
+		addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+		addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+		addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0;
+
+		dest2[i] = data2[i];
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts ();
+
+		/* data polling for D7 */
+		start = get_timer (0);
+		while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) !=
+		       (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) {
+			if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+				return (1);
+			}
+		}
+	}
+
+	return (0);
+}

board/adderII/u-boot.lds

@@ -0,0 +1,147 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o	(.text)
+/*
+    cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_ppc/ppcstring.o	(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_generic/zlib.o		(.text)
+
+    . = env_offset;
+    common/environment.o(.text)
+*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  . = ALIGN(256 * 1024);
+  .ppcenv	:
+  {
+    common/environment.o (.ppcenv)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
+

board/bmw/bmw.c

@@ -27,7 +27,6 @@
 #include <command.h>
 #include <malloc.h>
 #include <devices.h>
-#include <syscall.h>
 #include <net.h>
 #include <version.h>
 #include <dtt.h>

board/eltec/bab7xx/bab7xx.c

@@ -173,7 +173,7 @@ void after_reloc (ulong dest_addr)
     /*
      * Jump to the main U-Boot board init code
      */
-    board_init_r(gd, dest_addr);
+    board_init_r((gd_t *)gd, dest_addr);
 }
 
 /* ------------------------------------------------------------------------- */

board/eltec/elppc/elppc.c

@@ -142,7 +142,7 @@ void after_reloc (ulong dest_addr)
 	/*
 	 * Jump to the main U-Boot board init code
 	 */
-	board_init_r (gd, dest_addr);
+	board_init_r ((gd_t *)gd, dest_addr);
 }
 
 /* ------------------------------------------------------------------------- */

board/eltec/mhpc/mhpc.c

@@ -254,7 +254,7 @@ long int initdram (int board_type)
     upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
 
     memctl->memc_mamr  = CFG_MAMR & (~(MAMR_PTAE)); /* no refresh yet */
-    memctl->memc_mbmr  = MAMR_GPL_B4DIS;
+    memctl->memc_mbmr  = MBMR_GPL_B4DIS;	/* should this be mamr? - NTL */
     memctl->memc_mptpr = MPTPR_PTP_DIV64;
     memctl->memc_mar   = 0x00008800;
 

board/esd/ar405/fpgadata.c

@@ -8,7 +8,7 @@
  0x03,0x07,0x02,0x09,0x04,0x04,0x04,0x04,0x0e,0x04,0x04,0x09,0x03,0x07,0x02,0x04,
  0x03,0x03,0x03,0x07,0xe5,0x01,0x0d,0x02,0x02,0x03,0x02,0x02,0x03,0x02,0x02,0x03,
  0x19,0x03,0x02,0x02,0x03,0x02,0x08,0x09,0x07,0x13,0x03,0x11,0x02,0x06,0x03,0x05,
- 0x03,0x05,0x11,0x1d,0x1f,0x13,0x10,0x01,0x01,0xe2,0x4c,0xe5,0x01,0x0a,0x04,0x01,
+ 0x03,0x05,0x11,0x1d,0x1f,0x13,0x10,0x01,0x01,0xe3,0x4c,0xe5,0x01,0x0a,0x04,0x01,
  0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x09,0x04,0x04,0x02,0x06,0x01,0xe5,0x05,
  0x01,0x02,0x04,0x04,0x04,0x09,0x09,0x09,0x09,0x04,0x06,0x01,0x07,0x09,0x04,0x04,
  0x09,0x06,0x02,0x09,0x09,0x04,0x01,0xe7,0x03,0x04,0x07,0xe6,0x08,0x09,0x09,0x0e,
@@ -16,7 +16,7 @@
  0x03,0x05,0xe5,0x07,0xe5,0x01,0x05,0x0b,0xe5,0x07,0xe5,0x07,0x09,0x03,0x05,0xe6,
  0xe5,0x04,0xe5,0x01,0x05,0xe5,0x01,0x05,0xe5,0xe6,0x04,0x03,0x05,0xe5,0xe6,0x04,
  0xe5,0x07,0x03,0x05,0xe5,0x07,0x0b,0x01,0x0e,0x05,0x03,0x05,0x03,0x05,0x1d,0x03,
- 0x05,0x03,0x44,0xe5,0xe5,0x2e,0x1c,0x01,0x13,0x32,0x01,0xe2,0x4d,0xe5,0x0f,0x09,
+ 0x05,0x03,0x44,0xe5,0xe5,0x2e,0x1c,0x01,0x13,0x32,0x01,0xe3,0x4d,0xe5,0x0f,0x09,
  0x09,0x27,0x09,0x42,0x04,0x4a,0x44,0x01,0x01,0x01,0x12,0x09,0x09,0x01,0x06,0x01,
  0x12,0x09,0x0a,0x09,0x11,0x21,0x13,0x11,0x15,0x1d,0x1b,0x0c,0x0d,0x03,0x03,0x01,
  0x31,0x31,0x47,0x81,0xe5,0xe5,0xe5,0x77,0x3e,0xe5,0x19,0xe5,0x1b,0x3b,0xe5,0xe5,
@@ -2727,10 +2727,10 @@
  0x01,0x03,0x03,0x05,0x03,0x09,0xe5,0x07,0x09,0x09,0x01,0x07,0x09,0x07,0x01,0x09,
  0x09,0x0d,0x01,0x01,0x04,0x27,0x39,0x25,0x09,0x0b,0x09,0x09,0x02,0xe5,0x0e,0x02,
  0x07,0x0b,0x1d,0x2e,0xe5,0xe6,0x50,0xe5,0x1b,0x13,0x04,0x04,0x04,0x06,0x04,0x09,
- 0x04,0x04,0x13,0x0e,0x13,0x1d,0x27,0xe7,0x21,0xc6,0x40,0x03,0x03,0x07,0xe2,0x09,
+ 0x04,0x04,0x13,0x0e,0x13,0x1d,0x27,0xe7,0x21,0xc6,0x40,0x03,0x03,0x07,0xe3,0x09,
  0x3a,0x03,0x07,0x29,0x1f,0x25,0x0b,0x3b,0x15,0xe5,0x2d,0x01,0x27,0xe7,0x6e,0x16,
  0x05,0xe5,0x01,0x05,0x02,0x02,0x05,0x03,0x05,0xe5,0x01,0x05,0x0d,0x05,0x5c,0x06,
- 0x01,0x01,0x05,0x93,0x59,0x34,0x05,0xe5,0x01,0x04,0xe5,0xe2,0x34,0x10,0x02,0xe5,
+ 0x01,0x01,0x05,0x93,0x59,0x34,0x05,0xe5,0x01,0x04,0xe5,0xe3,0x34,0x10,0x02,0xe5,
  0x13,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x0b,0x09,
  0x09,0x09,0x09,0x09,0x09,0x09,0x09,0xe6,0x06,0x09,0x09,0x09,0x03,0x05,0x0a,0xe5,
  0xe5,0x04,0x09,0x08,0xe5,0x07,0xe5,0x08,0x08,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,
@@ -2747,4 +2747,4 @@
  0x05,0x02,0x02,0x03,0x02,0x02,0x03,0x02,0x02,0x01,0x07,0x03,0x02,0x02,0x02,0x04,
  0x02,0x01,0x04,0x02,0x01,0x02,0x01,0x02,0x01,0x01,0xe5,0x05,0x04,0x03,0x07,0xe5,
  0xe5,0x03,0x04,0x04,0x0b,0x02,0xe5,0x01,0xe5,0x01,0xe5,0xff,0xff,0xff,0xff,0xff,
- 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

board/esd/ash405/ash405.c

@@ -67,7 +67,7 @@ int board_pre_init (void)
 	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
 	mtdcr(uicer, 0x00000000);       /* disable all ints */
 	mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
-	mtdcr(uicpr, 0xFFFFFF81);       /* set int polarities */
+	mtdcr(uicpr, 0xFFFFFF9F);       /* set int polarities */
 	mtdcr(uictr, 0x10000000);       /* set int trigger levels */
 	mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
 	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */

board/esd/ocrtc/Makefile

@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= lib$(BOARD).a
 
-OBJS	= $(BOARD).o flash.o
+OBJS	= $(BOARD).o flash.o cmd_ocrtc.o
 
 $(LIB):	$(OBJS) $(SOBJS)
 	$(AR) crv $@ $(OBJS)

board/esd/ocrtc/cmd_ocrtc.c

@@ -0,0 +1,87 @@
+/*
+ * (C) Copyright 2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <405gp_pci.h>
+
+
+#if (CONFIG_COMMANDS & CFG_CMD_BSP)
+
+#define IBM_VENDOR_ID    0x1014
+#define PPC405_DEVICE_ID 0x0156
+
+
+/*
+ * Set device number on pci board
+ */
+int do_setdevice(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	int idx = 1;	  /* start at 1 (skip device 0) */
+	pci_dev_t bdf = 0;
+	u32 addr;
+
+	while (bdf >= 0) {
+		if ((bdf = pci_find_device(IBM_VENDOR_ID, PPC405_DEVICE_ID, idx++)) < 0) {
+			break;
+		}
+		printf("Found device nr %d at %x!\n", idx-1, bdf);
+		pci_read_config_dword(bdf, PCI_BASE_ADDRESS_1, &addr);
+		addr &= ~0xf;
+		*(u32 *)addr = (bdf & 0x0000f800) >> 11;
+		printf("Wrote %x at %x!\n", (bdf & 0x0000f800) >> 11, addr);
+	}
+
+	return 0;
+}
+U_BOOT_CMD(
+	setdevice,	1,	1,	do_setdevice,
+	"setdevice - Set device number on pci adapter boards\n",
+	NULL
+);
+
+
+/*
+ * Get device number on pci board
+ */
+int do_getdevice(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	u32 device;
+	char str[32];
+
+	device = *(u32 *)0x0;
+	device = 0x16 - device;      /* calculate vxworks bp slot id */
+	sprintf(str, "%d", device);
+	setenv("slot", str);
+	printf("Variabel slot set to %x\n", device);
+
+	return 0;
+}
+U_BOOT_CMD(
+	getdevice,	1,	1,	do_getdevice,
+	"getdevice - Get device number and set slot env variable\n",
+	NULL
+);
+
+#endif

board/evb64260/evb64260.c

@@ -329,7 +329,7 @@ after_reloc(ulong dest_addr)
 	}
 
 	/* now, jump to the main U-Boot board init code */
-	board_init_r (gd, dest_addr);
+	board_init_r ((gd_t *)gd, dest_addr);
 
 	/* NOTREACHED */
 }

board/exbitgen/flash.c

@@ -217,7 +217,7 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 	short i;
 	FLASH_WORD_SIZE value;
 	ulong base = (ulong)addr;
-        volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr;
+	volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr;
 
 	/* Write auto select command: read Manufacturer ID */
 	addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
@@ -247,7 +247,7 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 
 	switch (value) {
 	case (FLASH_WORD_SIZE)AMD_ID_F040B:
-	        info->flash_id += FLASH_AM040;
+		info->flash_id += FLASH_AM040;
 		info->sector_count = 8;
 		info->size = 0x0080000; /* => 512 ko */
 		break;
@@ -335,14 +335,14 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 	}
 
 	/* set up sector start address table */
-        if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
 		(info->flash_id  == FLASH_AM040) ||
 		(info->flash_id == FLASH_AMDLV033C) ||
 		(info->flash_id == FLASH_AMDLV065D)) {
 		ulong sectsize = info->size / info->sector_count;
 		for (i = 0; i < info->sector_count; i++)
 			info->start[i] = base + (i * sectsize);
-        } else {
+	} else {
 	    if (info->flash_id & FLASH_BTYPE) {
 		/* set sector offsets for bottom boot block type	*/
 		info->start[0] = base + 0x00000000;
@@ -370,9 +370,9 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 		/* D0 = 1 if protected */
 
 		addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]);
-                if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
+		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
 			info->protect[i] = 0;
-                else
+		else
 			info->protect[i] = addr2[2] & 1;
 	}
 
@@ -450,7 +450,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
 			while ((addr2[0] & 0x00800080) !=
 				(FLASH_WORD_SIZE) 0x00800080) {
 				if ((now=get_timer(start)) >
-				           CFG_FLASH_ERASE_TOUT) {
+					   CFG_FLASH_ERASE_TOUT) {
 					printf ("Timeout\n");
 					addr[0] = (FLASH_WORD_SIZE)0x00F000F0;
 					return 1;
@@ -551,12 +551,12 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
  */
 static int write_word (flash_info_t *info, ulong dest, ulong data)
 {
-        volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)(info->start[0]);
-        volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *)dest;
-        volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *)&data;
+	volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)(info->start[0]);
+	volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *)dest;
+	volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *)&data;
 	ulong start;
 	int flag;
-        int i;
+	int i;
 
 	/* Check if Flash is (sufficiently) erased */
 	if ((*((volatile ulong *)dest) & data) != data) {
@@ -565,7 +565,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data)
 		return 2;
 	}
 
-        for (i=0; i < 4/sizeof(FLASH_WORD_SIZE); i++) {
+	for (i=0; i < 4/sizeof(FLASH_WORD_SIZE); i++) {
 		/* Disable interrupts which might cause a timeout here */
 		flag = disable_interrupts();
 

board/exbitgen/init.S

@@ -34,7 +34,7 @@
 #include <asm/mmu.h>
 
 #include "exbitgen.h"
-		
+
 /* IIC declarations (This is an extract from 405gp_i2c.h, which also contains some */
 /* c-code declarations and consequently can't be included here). */
 /* (Possibly to be solved somehow else). */
@@ -100,25 +100,25 @@
 #define TIMEBASE_10PS (1000000000 / CONFIG_SYS_CLK_FREQ) * 100
 
 #define FLASH_8bit_AP   0x9B015480
-#define FLASH_8bit_CR   0xFFF18000 /* 1MB(min), 8bit, R/W */ 
+#define FLASH_8bit_CR   0xFFF18000 /* 1MB(min), 8bit, R/W */
 
 #define FLASH_32bit_AP  0x9B015480
 #define FLASH_32bit_CR  0xFFE3C000 /* 2MB, 32bit, R/W */
 
 
 #define WDCR_EBC(reg,val) addi    r4,0,reg;\
-        mtdcr   ebccfga,r4;\
-        addis   r4,0,val@h;\
-        ori     r4,r4,val@l;\
-        mtdcr   ebccfgd,r4
+	mtdcr   ebccfga,r4;\
+	addis   r4,0,val@h;\
+	ori     r4,r4,val@l;\
+	mtdcr   ebccfgd,r4
 
 /*---------------------------------------------------------------------
  * Function:     ext_bus_cntlr_init
- * Description:  Initializes the External Bus Controller for the external 
- *		peripherals. IMPORTANT: For pass1 this code must run from 
+ * Description:  Initializes the External Bus Controller for the external
+ *		peripherals. IMPORTANT: For pass1 this code must run from
  *		cache since you can not reliably change a peripheral banks
  *		timing register (pbxap) while running code from that bank.
- *		For ex., since we are running from ROM on bank 0, we can NOT 
+ *		For ex., since we are running from ROM on bank 0, we can NOT
  *		execute the code that modifies bank 0 timings from ROM, so
  *		we run it from cache.
  *	Bank 0 - Boot flash
@@ -126,63 +126,63 @@
  *	Bank 5 - CPLD
  *	Bank 6 - not used
  *	Bank 7 - Heathrow chip
- *---------------------------------------------------------------------	
+ *---------------------------------------------------------------------
  */
-     	.globl	ext_bus_cntlr_init
+	.globl	ext_bus_cntlr_init
 ext_bus_cntlr_init:
-        mflr    r4                      /* save link register */
-        bl      ..getAddr
+	mflr    r4                      /* save link register */
+	bl      ..getAddr
 ..getAddr:
-        mflr    r3                      /* get address of ..getAddr */
-        mtlr    r4                      /* restore link register */
-        addi    r4,0,14                 /* set ctr to 10; used to prefetch */
-        mtctr   r4                      /* 10 cache lines to fit this function */
-                                        /* in cache (gives us 8x10=80 instrctns) */
+	mflr    r3                      /* get address of ..getAddr */
+	mtlr    r4                      /* restore link register */
+	addi    r4,0,14                 /* set ctr to 10; used to prefetch */
+	mtctr   r4                      /* 10 cache lines to fit this function */
+					/* in cache (gives us 8x10=80 instrctns) */
 ..ebcloop:
-        icbt    r0,r3                   /* prefetch cache line for addr in r3 */
-        addi    r3,r3,32		/* move to next cache line */
-        bdnz    ..ebcloop               /* continue for 10 cache lines */
+	icbt    r0,r3                   /* prefetch cache line for addr in r3 */
+	addi    r3,r3,32		/* move to next cache line */
+	bdnz    ..ebcloop               /* continue for 10 cache lines */
 
 	mflr	r31			/* save link register */
-	
-        /*-----------------------------------------------------------
-         * Delay to ensure all accesses to ROM are complete before changing
+
+	/*-----------------------------------------------------------
+	 * Delay to ensure all accesses to ROM are complete before changing
 	 * bank 0 timings. 200usec should be enough.
-         *   200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
-         *-----------------------------------------------------------
+	 *   200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
+	 *-----------------------------------------------------------
 	 */
 
 	addis	r3,0,0x0
-        ori     r3,r3,0xA000          /* ensure 200usec have passed since reset */
-        mtctr   r3
+	ori     r3,r3,0xA000          /* ensure 200usec have passed since reset */
+	mtctr   r3
 ..spinlp:
-        bdnz    ..spinlp                /* spin loop */
+	bdnz    ..spinlp                /* spin loop */
 
-        /*---------------------------------------------------------------
-         * Memory Bank 0 (Boot Flash) initialization
-         *---------------------------------------------------------------
+	/*---------------------------------------------------------------
+	 * Memory Bank 0 (Boot Flash) initialization
+	 *---------------------------------------------------------------
 	 */
 	WDCR_EBC(pb0ap, FLASH_32bit_AP)
 	WDCR_EBC(pb0cr, 0xffe38000)
 /*pnc	WDCR_EBC(pb0cr, FLASH_32bit_CR) */
-	
-        /*---------------------------------------------------------------
-         * Memory Bank 5 (CPLD) initialization
-         *---------------------------------------------------------------
+
+	/*---------------------------------------------------------------
+	 * Memory Bank 5 (CPLD) initialization
+	 *---------------------------------------------------------------
 	 */
 	WDCR_EBC(pb5ap, 0x01010040)
 /*jsa recommendation:		WDCR_EBC(pb5ap, 0x00010040) */
 	WDCR_EBC(pb5cr, 0x10038000)
 
-        /*--------------------------------------------------------------- */
-        /* Memory Bank 6 (not used) initialization */
-        /*--------------------------------------------------------------- */
+	/*--------------------------------------------------------------- */
+	/* Memory Bank 6 (not used) initialization */
+	/*--------------------------------------------------------------- */
 	WDCR_EBC(pb6cr, 0x00000000)
 
 	/* Read HW ID to determine whether old H2 board or new generic CPU board */
 	addis	r3, 0,  HW_ID_ADDR@h
 	ori	r3, r3, HW_ID_ADDR@l
-        lbz     r3,0x0000(r3)
+	lbz     r3,0x0000(r3)
 	cmpi	0, r3, 1          /* if (HW_ID==1) */
 	beq 	setup_h2evalboard /* then jump */
 	cmpi	0, r3, 2          /* if (HW_ID==2) */
@@ -191,9 +191,9 @@ ext_bus_cntlr_init:
 	beq 	setup_genieboard  /* then jump */
 
 setup_genieboard:
-        /*--------------------------------------------------------------- */
-        /* Memory Bank 1 (Application Flash) initialization for generic CPU board */
-        /*--------------------------------------------------------------- */
+	/*--------------------------------------------------------------- */
+	/* Memory Bank 1 (Application Flash) initialization for generic CPU board */
+	/*--------------------------------------------------------------- */
 /*	WDCR_EBC(pb1ap, 0x7b015480)	/###* T.B.M. */
 /*	WDCR_EBC(pb1ap, 0x7F8FFE80)	/###* T.B.M. */
 	WDCR_EBC(pb1ap, 0x9b015480)	/* hlb-20020207: burst 8 bit 6 cycles  */
@@ -201,68 +201,68 @@ setup_genieboard:
 /*	WDCR_EBC(pb1cr, 0x20098000)	/###* 16 MB */
 	WDCR_EBC(pb1cr, 0x200B8000)	/* 32 MB */
 
-        /*--------------------------------------------------------------- */
-        /* Memory Bank 4 (Onboard FPGA) initialization for generic CPU board */
-        /*--------------------------------------------------------------- */
+	/*--------------------------------------------------------------- */
+	/* Memory Bank 4 (Onboard FPGA) initialization for generic CPU board */
+	/*--------------------------------------------------------------- */
 	WDCR_EBC(pb4ap, 0x01010000)	/*  */
 	WDCR_EBC(pb4cr, 0x1021c000)	/*  */
 
-        /*--------------------------------------------------------------- */
-        /* Memory Bank 7 (Heathrow chip on Reference board) initialization */
-        /*--------------------------------------------------------------- */
+	/*--------------------------------------------------------------- */
+	/* Memory Bank 7 (Heathrow chip on Reference board) initialization */
+	/*--------------------------------------------------------------- */
 	WDCR_EBC(pb7ap, 0x200ffe80)	/* No Ready, many wait states (let reflections die out) */
 	WDCR_EBC(pb7cr, 0X4001A000)
 
 	bl	setup_continue
 
-	
+
 setup_h2evalboard:
-        /*--------------------------------------------------------------- */
-        /* Memory Bank 1 (Application Flash) initialization */
-        /*--------------------------------------------------------------- */
+	/*--------------------------------------------------------------- */
+	/* Memory Bank 1 (Application Flash) initialization */
+	/*--------------------------------------------------------------- */
 	WDCR_EBC(pb1ap, 0x7b015480)	/* T.B.M. */
 /*3010	WDCR_EBC(pb1ap, 0x7F8FFE80)	/###* T.B.M. */
-	WDCR_EBC(pb1cr, 0x20058000) 
-
-        /*--------------------------------------------------------------- */
-        /* Memory Bank 2 (Application Flash) initialization */
-        /*--------------------------------------------------------------- */
-	WDCR_EBC(pb2ap, 0x7b015480)	/* T.B.M. */
-/*3010	WDCR_EBC(pb2ap, 0x7F8FFE80)	/###* T.B.M. */
-	WDCR_EBC(pb2cr, 0x20458000) 
+	WDCR_EBC(pb1cr, 0x20058000)
 
 	/*--------------------------------------------------------------- */
-        /* Memory Bank 3 (Application Flash) initialization */
-        /*--------------------------------------------------------------- */
+	/* Memory Bank 2 (Application Flash) initialization */
+	/*--------------------------------------------------------------- */
+	WDCR_EBC(pb2ap, 0x7b015480)	/* T.B.M. */
+/*3010	WDCR_EBC(pb2ap, 0x7F8FFE80)	/###* T.B.M. */
+	WDCR_EBC(pb2cr, 0x20458000)
+
+	/*--------------------------------------------------------------- */
+	/* Memory Bank 3 (Application Flash) initialization */
+	/*--------------------------------------------------------------- */
 	WDCR_EBC(pb3ap, 0x7b015480)	/* T.B.M. */
 /*3010	WDCR_EBC(pb3ap, 0x7F8FFE80)	/###* T.B.M. */
-	WDCR_EBC(pb3cr, 0x20858000) 
+	WDCR_EBC(pb3cr, 0x20858000)
 
-        /*--------------------------------------------------------------- */
-        /* Memory Bank 4 (Application Flash) initialization */
-        /*--------------------------------------------------------------- */
+	/*--------------------------------------------------------------- */
+	/* Memory Bank 4 (Application Flash) initialization */
+	/*--------------------------------------------------------------- */
 	WDCR_EBC(pb4ap, 0x7b015480)	/* T.B.M. */
 /*3010	WDCR_EBC(pb4ap, 0x7F8FFE80)	/###* T.B.M. */
 	WDCR_EBC(pb4cr, 0x20C58000)
 
-        /*--------------------------------------------------------------- */
-        /* Memory Bank 7 (Heathrow chip) initialization */
-        /*--------------------------------------------------------------- */
+	/*--------------------------------------------------------------- */
+	/* Memory Bank 7 (Heathrow chip) initialization */
+	/*--------------------------------------------------------------- */
 	WDCR_EBC(pb7ap, 0x02000280)	/* No Ready, 4 wait states */
 	WDCR_EBC(pb7cr, 0X4001A000)
 
 setup_continue:
 
-	
-        mtlr    r31                     /* restore lr	 */
+
+	mtlr    r31                     /* restore lr	 */
 	nop				/* pass2 DCR errata #8 */
-        blr
+	blr
 
 /*--------------------------------------------------------------------- */
 /* Function:     sdram_init */
 /* Description:  Configures SDRAM memory banks. */
 /*--------------------------------------------------------------------- */
-        .globl  sdram_init
+	.globl  sdram_init
 
 sdram_init:
 #if CFG_MONITOR_BASE < CFG_FLASH_BASE
@@ -377,12 +377,12 @@ sdram_init:
 	subf	r5, r6, r17
 	or	r4, r4, r5
 
-        /*----------------------------------------------------------- */
-        /* Set SDTR1  */
-        /*----------------------------------------------------------- */
-        addi    r5,0,mem_sdtr1
-        mtdcr   memcfga,r5
-        mtdcr   memcfgd,r4
+	/*----------------------------------------------------------- */
+	/* Set SDTR1  */
+	/*----------------------------------------------------------- */
+	addi    r5,0,mem_sdtr1
+	mtdcr   memcfga,r5
+	mtdcr   memcfgd,r4
 
 	/*----------------------------------------------------------- */
 	/* */
@@ -444,36 +444,36 @@ b1skip:	addi    r7,0,mem_mb2cf
 	addi    r7,0,mem_mb3cf
 	mtdcr   memcfga,r7
 	mtdcr   memcfgd,r6
-b3skip:	
+b3skip:
 
-        /*----------------------------------------------------------- */
-        /* Set RTR */
-        /*----------------------------------------------------------- */
+	/*----------------------------------------------------------- */
+	/* Set RTR */
+	/*----------------------------------------------------------- */
 	cmpi	0, r30, 1600
 	bge	rtr_1
-        addis   r7, 0, 0x05F0	/* RTR value for 100Mhz */
+	addis   r7, 0, 0x05F0	/* RTR value for 100Mhz */
 	bl	rtr_2
 rtr_1:	addis	r7, 0, 0x03F8
 rtr_2:	addi    r4,0,mem_rtr
 	mtdcr   memcfga,r4
 	mtdcr   memcfgd,r7
 
-        /*----------------------------------------------------------- */
-        /* Delay to ensure 200usec have elapsed since reset. Assume worst */
-        /* case that the core is running 200Mhz: */
-        /*   200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */
-        /*----------------------------------------------------------- */
-        addis   r3,0,0x0000
-        ori     r3,r3,0xA000          /* ensure 200usec have passed since reset */
-        mtctr   r3
+	/*----------------------------------------------------------- */
+	/* Delay to ensure 200usec have elapsed since reset. Assume worst */
+	/* case that the core is running 200Mhz: */
+	/*   200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */
+	/*----------------------------------------------------------- */
+	addis   r3,0,0x0000
+	ori     r3,r3,0xA000          /* ensure 200usec have passed since reset */
+	mtctr   r3
 ..spinlp2:
-        bdnz    ..spinlp2               /* spin loop */
+	bdnz    ..spinlp2               /* spin loop */
 
-        /*----------------------------------------------------------- */
-        /* Set memory controller options reg, MCOPT1. */
+	/*----------------------------------------------------------- */
+	/* Set memory controller options reg, MCOPT1. */
 	/* Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst  */
 	/* read/prefetch. */
-        /*----------------------------------------------------------- */
+	/*----------------------------------------------------------- */
 	addi    r4,0,mem_mcopt1
 	mtdcr   memcfga,r4
 	addis   r4,0,0x80C0             /* set DC_EN=1 */
@@ -481,13 +481,13 @@ rtr_2:	addi    r4,0,mem_rtr
 	mtdcr   memcfgd,r4
 
 
-        /*----------------------------------------------------------- */
-        /* Delay to ensure 10msec have elapsed since reset. This is */
-        /* required for the MPC952 to stabalize. Assume worst */
-        /* case that the core is running 200Mhz: */
-        /*   200,000,000 (cycles/sec) X .010 (sec) = 0x1E8480 cycles */
-        /* This delay should occur before accessing SDRAM. */
-        /*----------------------------------------------------------- */
+	/*----------------------------------------------------------- */
+	/* Delay to ensure 10msec have elapsed since reset. This is */
+	/* required for the MPC952 to stabalize. Assume worst */
+	/* case that the core is running 200Mhz: */
+	/*   200,000,000 (cycles/sec) X .010 (sec) = 0x1E8480 cycles */
+	/* This delay should occur before accessing SDRAM. */
+	/*----------------------------------------------------------- */
 	addis   r3,0,0x001E
 	ori     r3,r3,0x8480          /* ensure 10msec have passed since reset */
 	mtctr   r3
@@ -501,8 +501,8 @@ rtr_2:	addi    r4,0,mem_rtr
 	stb	r4,0(r5)
 	eieio
 
-        mtlr    r31                     /* restore lr */
-        blr
+	mtlr    r31                     /* restore lr */
+	blr
 
 /*--------------------------------------------------------------------- */
 /* Function:    read_spd */
@@ -512,21 +512,21 @@ rtr_2:	addi    r4,0,mem_rtr
 
 #define WRITE_I2C(reg,val) \
 	addi    r3,0,val;\
-        addis   r4, 0, 0xef60;\
-        ori     r4, r4, 0x0500 + reg;\
-        stb     r3, 0(r4);\
-        eieio
+	addis   r4, 0, 0xef60;\
+	ori     r4, r4, 0x0500 + reg;\
+	stb     r3, 0(r4);\
+	eieio
 
 #define READ_I2C(reg) \
-        addis   r3, 0, 0xef60;\
-        ori     r3, r3, 0x0500 + reg;\
-        lbz     r3, 0x0000(r3);\
-        eieio
+	addis   r3, 0, 0xef60;\
+	ori     r3, r3, 0x0500 + reg;\
+	lbz     r3, 0x0000(r3);\
+	eieio
 
 read_spd:
 
 	mflr	r5
-	
+
 	/* Initialize i2c */
 	/*--------------- */
 	WRITE_I2C(IICLMADR, 0x00)	/* clear lo master address */
@@ -558,9 +558,9 @@ read_spd:
 
 	/* Wait a little */
 	/*-------------- */
-        addis   r3,0,0x0000
-        ori     r3,r3,0xA000
-        mtctr   r3
+	addis   r3,0,0x0000
+	ori     r3,r3,0xA000
+	mtctr   r3
 in02:	bdnz    in02
 
 	/* Issue write command */
@@ -572,12 +572,12 @@ in02:	bdnz    in02
 	/*--------------- */
 	addi	r7, 0, 0	/* byte counter in r7 */
 	addi	r8, 0, 0	/* checksum in r8 */
-rdlp:	
+rdlp:
 	/* issue read command */
 	/*------------------- */
 	cmpi	0, r7, 127
 	blt	rd01
-	WRITE_I2C(IICCNTL, IIC_CNTL_READ | IIC_CNTL_PT) 
+	WRITE_I2C(IICCNTL, IIC_CNTL_READ | IIC_CNTL_PT)
 	bl	rd02
 rd01:	WRITE_I2C(IICCNTL, IIC_CNTL_READ | IIC_CNTL_CHT | IIC_CNTL_PT)
 rd02:	bl	wait_i2c_transfer_done
@@ -585,46 +585,46 @@ rd02:	bl	wait_i2c_transfer_done
 	/* Fetch byte from buffer */
 	/*----------------------- */
 	READ_I2C(IICMDBUF)
-	
+
 	/* Retrieve parameters that are going to be used during configuration. */
 	/* Save them in dedicated registers. */
 	/*------------------------------------------------------------ */
 	cmpi	0, r7, 3	/* Save byte 3 in r10 */
 	bne	rd10
-	addi	r10, r3, 0	
+	addi	r10, r3, 0
 rd10:	cmpi	0, r7, 4	/* Save byte 4 in r11 */
 	bne	rd11
-	addi	r11, r3, 0	
+	addi	r11, r3, 0
 rd11:	cmpi	0, r7, 5	/* Save byte 5 in r12 */
 	bne	rd12
-	addi	r12, r3, 0	
+	addi	r12, r3, 0
 rd12:	cmpi	0, r7, 17	/* Save byte 17 in r13 */
 	bne	rd13
-	addi	r13, r3, 0	
+	addi	r13, r3, 0
 rd13:	cmpi	0, r7, 18	/* Save byte 18 in r14 */
 	bne	rd14
-	addi	r14, r3, 0	
+	addi	r14, r3, 0
 rd14:	cmpi	0, r7, 31	/* Save byte 31 in r15 */
 	bne	rd15
-	addi	r15, r3, 0	
+	addi	r15, r3, 0
 rd15:	cmpi	0, r7, 27	/* Save byte 27 in r16 */
 	bne	rd16
-	addi	r16, r3, 0	
+	addi	r16, r3, 0
 rd16:	cmpi	0, r7, 29	/* Save byte 29 in r17 */
 	bne	rd17
-	addi	r17, r3, 0	
+	addi	r17, r3, 0
 rd17:	cmpi	0, r7, 30	/* Save byte 30 in r18 */
 	bne	rd18
-	addi	r18, r3, 0	
+	addi	r18, r3, 0
 rd18:	cmpi	0, r7, 9	/* Save byte 9 in r19 */
 	bne	rd19
-	addi	r19, r3, 0	
+	addi	r19, r3, 0
 rd19:	cmpi	0, r7, 23	/* Save byte 23 in r20 */
 	bne	rd20
-	addi	r20, r3, 0	
+	addi	r20, r3, 0
 rd20:	cmpi	0, r7, 25	/* Save byte 25 in r21 */
 	bne	rd21
-	addi	r21, r3, 0	
+	addi	r21, r3, 0
 rd21:
 
 	/* Calculate checksum of the first 63 bytes */
@@ -647,16 +647,16 @@ rd30:	andi.	r8, r8, 0xff		/* use only 8 bits */
 	eieio
 rderr:	bl	rderr
 
-rd31:	
-	
+rd31:
+
 	/* Increment byte counter and check whether all bytes have been read. */
 	/*------------------------------------------------------------------- */
 	addi	r7, r7, 1
 	cmpi	0, r7, 127
 	bgt	rd05
 	bl	rdlp
-rd05:	
-        mtlr    r5                     /* restore lr */
+rd05:
+	mtlr    r5                     /* restore lr */
 	blr
 
 wait_i2c_transfer_done:
@@ -664,8 +664,8 @@ wait_i2c_transfer_done:
 wt01:	READ_I2C(IICSTS)
 	andi.	r4, r3, IIC_STS_PT
 	cmpi	0, r4, IIC_STS_PT
-	beq	wt01	
-        mtlr    r6                     /* restore lr */
+	beq	wt01
+	mtlr    r6                     /* restore lr */
 	blr
 
 /*--------------------------------------------------------------------- */
@@ -696,7 +696,7 @@ fm01:	cmpi	0, r10, 11
 	cmpi	0, r13, 2
 	bne	fm02
 	addi	r3, 0, 1
-	bl	fmfound	
+	bl	fmfound
 
 fm02:	cmpi	0, r10, 12
 	bne	fm03
@@ -815,7 +815,7 @@ fm14:	cmpi	0, r10, 13
 	addi	r3, 0, 7
 	bl	fmfound
 
-fm15:	
+fm15:
 	/* not found, error code to be issued on LEDs */
 	addi	r7, 0, LED_SDRAM_CODE_2
 	addis	r6, 0, 0x1000
@@ -827,7 +827,7 @@ fmerr:	bl	fmerr
 fmfound:addi	r6, 0, 1
 	subf	r3, r6, r3
 
-        mtlr    r5                     /* restore lr */
+	mtlr    r5                     /* restore lr */
 	blr
 
 /*--------------------------------------------------------------------- */
@@ -838,13 +838,13 @@ fmfound:addi	r6, 0, 1
 find_size_code:
 
 	mflr	r5
-	
+
 	addi	r3, r15, 0	/* density */
 	addi	r7, 0, 0
 fs01:	andi.	r6, r3, 0x01
 	cmpi	0, r6, 1
 	beq	fs04
-	
+
 	addi	r7, r7, 1
 	cmpi	0, r7, 7
 	bge	fs02
@@ -866,7 +866,7 @@ fs04:	addi	r3, r7, 0
 	addi	r6, 0, 1
 	subf	r3, r6, r3
 fs05:
-        mtlr    r5                     /* restore lr */
+	mtlr    r5                     /* restore lr */
 	blr
 
 /*--------------------------------------------------------------------- */
@@ -895,9 +895,9 @@ fc01:	srw	r6, r14, r4	/*  */
 	addi	r7, r19, 0	/* SDRAM cycle time for highest CAS latenty */
 
 	bl	fc03
-fc02:	
+fc02:
 	addi	r7, r20, 0	/* SDRAM cycle time for next-highest CAS latenty */
-fc03:	
+fc03:
 	addi	r8, r7, 0
 	addi	r9, 0, 4
 	srw	r7, r7, r9
@@ -910,7 +910,7 @@ fc03:
 	bgt	fc05
 	addi	r3, r2, 0
 	bl	fc05
-fc04:	
+fc04:
 	addi	r7, r21, 0	/* SDRAM cycle time for third-highest CAS latenty */
 	addi	r8, r7, 0
 	addi	r9, 0, 2
@@ -933,9 +933,9 @@ fc06:	addi	r6, 0, 1
 	cmpi	0, r4, 0
 	bne	fc01
 
-fc07:	
+fc07:
 
-        mtlr    r5		/* restore lr */
+	mtlr    r5		/* restore lr */
 	blr
 #endif
 
@@ -1000,7 +1000,7 @@ fc07:
 /* Size:	2 MB */
 /* Usage:	read/write */
 /* Width:	32 bit */
-	
+
 /* Walnut fpga pb7ap */
 /* 0      1      8         1         5         2         8            0 */
 /* 0 + 00000 + 011 + 000 + 00 + 01 + 01 + 01 + 001 + 0 + 1 + 0 + 0 + 00000 */

board/exbitgen/u-boot.lds

@@ -98,7 +98,7 @@ SECTIONS
   PROVIDE (erotext = .);
   .reloc   :
   {
-    *(.got) 
+    *(.got)
     _GOT2_TABLE_ = .;
     *(.got2)
     _FIXUP_TABLE_ = .;

board/flagadm/flagadm.c

@@ -128,7 +128,7 @@ long int initdram (int board_type)
 
 	/* That should do it, just enable the periodic refresh in burst of 4*/
 	memctl->memc_mamr = CFG_MAMR_48_SDR | MAMR_TLFA_4X;
-	memctl->memc_mamr |= (MAMR_PTAE | MAMR_GPL_B4DIS);
+	memctl->memc_mamr |= (MAMR_PTAE | MAMR_GPL_A4DIS);
 
 	size_b0 = 16*1024*1024;
 
@@ -141,7 +141,7 @@ long int initdram (int board_type)
 
 	upmconfig(UPMB, (uint *)dsp_disp_table, sizeof(dsp_disp_table)/sizeof(uint));
 
-	memctl->memc_mbmr = MAMR_GPL_B4DIS;
+	memctl->memc_mbmr = MBMR_GPL_B4DIS;
 
 	memctl->memc_or4 = CFG_OR4;
 	memctl->memc_br4 = CFG_BR4;

board/gen860t/gen860t.c

@@ -302,4 +302,15 @@ board_poweroff(void)
     while (1);
 }
 
+#ifdef CONFIG_POST
+/*
+ * Returns 1 if keys pressed to start the power-on long-running tests
+ * Called from board_init_f().
+ */
+int post_hotkeys_pressed(void)
+{
+	return 0;	/* No hotkeys supported */
+}
+#endif
+
 /* vim: set ts=4 sw=4 tw=78 : */

board/genietv/genietv.c

@@ -163,7 +163,7 @@ long int initdram (int board_type)
     memctl->memc_mcr  = 0x80804105;	/* SDRAM bank 1 */
 
     /* Execute refresh 8 times */
-    memctl->memc_mbmr = (CFG_MBMR_8COL & ~MAMR_TLFB_MSK) | MAMR_TLFB_8X ;
+    memctl->memc_mbmr = (CFG_MBMR_8COL & ~MBMR_TLFB_MSK) | MBMR_TLFB_8X ;
 
     memctl->memc_mcr  = 0x80802130;	/* SDRAM bank 0 - execute twice */
 

board/gth/gth.c

@@ -218,7 +218,7 @@ int _initsdram (uint base, uint * noMbytes)
 			   sizeof (fpga_table) / sizeof (uint));
 
 	/* Enable UPWAITB */
-	mc->memc_mbmr = MAMR_GPL_B4DIS;	/* (16-13) */
+	mc->memc_mbmr = MBMR_GPL_B4DIS;	/* (16-13) */
 
 	/* CS2, base FPGA_2_BASE - 4 MByte, use UPM B 32 Bit */
 	mc->memc_or2 = 0xffc00000 | OR_BI;

board/icecube/Makefile

@@ -0,0 +1,47 @@
+
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o flash.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################

board/icecube/config.mk

@@ -0,0 +1,31 @@
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# IceCube board
+#
+
+TEXT_BASE = 0xfff00000
+# TEXT_BASE = 0x00100000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board

board/icecube/flash.c

@@ -0,0 +1,480 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it
+ *        has nothing to do with the flash chip being 8-bit or 16-bit.
+ */
+#ifdef CONFIG_FLASH_16BIT
+typedef unsigned short FLASH_PORT_WIDTH;
+typedef volatile unsigned short FLASH_PORT_WIDTHV;
+#define	FLASH_ID_MASK	0xFFFF
+#else
+typedef unsigned char FLASH_PORT_WIDTH;
+typedef volatile unsigned char FLASH_PORT_WIDTHV;
+#define	FLASH_ID_MASK	0xFF
+#endif
+
+#define FPW	FLASH_PORT_WIDTH
+#define FPWV	FLASH_PORT_WIDTHV
+
+#define ORMASK(size) ((-size) & OR_AM_MSK)
+
+#define FLASH_CYCLE1	0x0555
+#define FLASH_CYCLE2	0x02aa
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(FPWV *addr, flash_info_t *info);
+static void flash_reset(flash_info_t *info);
+static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data);
+static flash_info_t *flash_get_info(ulong base);
+
+/*-----------------------------------------------------------------------
+ * flash_init()
+ *
+ * sets up flash_info and returns size of FLASH (bytes)
+ */
+unsigned long flash_init (void)
+{
+	unsigned long size = 0;
+	int i;
+	extern void flash_preinit(void);
+
+	flash_preinit();
+
+	/* Init: no FLASHes known */
+	for (i=0; i < CFG_MAX_FLASH_BANKS; ++i) {
+		ulong flashbase = CFG_FLASH_BASE;
+
+		memset(&flash_info[i], 0, sizeof(flash_info_t));
+
+		flash_info[i].size =
+			flash_get_size((FPW *)flashbase, &flash_info[i]);
+
+		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+			printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx\n",
+			i, flash_info[i].size);
+		}
+
+		size += flash_info[i].size;
+	}
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_MONITOR_BASE,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      flash_get_info(CFG_MONITOR_BASE));
+#endif
+
+#ifdef	CFG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_ENV_ADDR,
+		      CFG_ENV_ADDR+CFG_ENV_SIZE-1,
+		      flash_get_info(CFG_ENV_ADDR));
+#endif
+
+
+	return size ? size : 1;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_reset(flash_info_t *info)
+{
+	FPWV *base = (FPWV *)(info->start[0]);
+
+	/* Put FLASH back in read mode */
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
+		*base = (FPW)0x00FF00FF;	/* Intel Read Mode */
+	else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
+		*base = (FPW)0x00F000F0;	/* AMD Read Mode */
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+static flash_info_t *flash_get_info(ulong base)
+{
+	int i;
+	flash_info_t * info;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) {
+		info = & flash_info[i];
+		if (info->start[0] <= base && base <= info->start[0] + info->size - 1)
+			break;
+	}
+
+	return i == CFG_MAX_FLASH_BANKS ? 0 : info;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+void flash_print_info (flash_info_t *info)
+{
+	int i;
+	uchar *boottype;
+	uchar *bootletter;
+	uchar *fmt;
+	uchar botbootletter[] = "B";
+	uchar topbootletter[] = "T";
+	uchar botboottype[] = "bottom boot sector";
+	uchar topboottype[] = "top boot sector";
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_BM:	printf ("BRIGHT MICRO ");	break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	case FLASH_MAN_SST:	printf ("SST ");		break;
+	case FLASH_MAN_STM:	printf ("STM ");		break;
+	case FLASH_MAN_INTEL:	printf ("INTEL ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	/* check for top or bottom boot, if it applies */
+	if (info->flash_id & FLASH_BTYPE) {
+		boottype = botboottype;
+		bootletter = botbootletter;
+	}
+	else {
+		boottype = topboottype;
+		bootletter = topbootletter;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AMDLV065D:
+		fmt = "29LV065 (64 Mbit, uniform sectors)\n";
+		break;
+	default:
+		fmt = "Unknown Chip Type\n";
+		break;
+	}
+
+	printf (fmt, bootletter, boottype);
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20,
+		info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+
+		printf (" %08lX%s", info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+
+	printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+ulong flash_get_size (FPWV *addr, flash_info_t *info)
+{
+	int i;
+	/* Write auto select command: read Manufacturer ID */
+	/* Write auto select command sequence and test FLASH answer */
+	addr[FLASH_CYCLE1] = (FPW)0x00AA00AA;	/* for AMD, Intel ignores this */
+	addr[FLASH_CYCLE2] = (FPW)0x00550055;	/* for AMD, Intel ignores this */
+	addr[FLASH_CYCLE1] = (FPW)0x00900090;	/* selects Intel or AMD */
+
+	/* The manufacturer codes are only 1 byte, so just use 1 byte.
+	 * This works for any bus width and any FLASH device width.
+	 */
+	udelay(100);
+	switch (addr[0] & 0xff) {
+
+	case (uchar)AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+
+	case (uchar)INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		break;
+	}
+
+	/* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
+	if (info->flash_id != FLASH_UNKNOWN) switch ((FPW)addr[1]) {
+
+	case (FPW)AMD_ID_LV065D:
+		info->flash_id += FLASH_AMDLV065D;
+		info->sector_count = 128;
+		info->size = 0x00800000;
+		for( i = 0; i < info->sector_count; i++ )
+			info->start[i] = (ulong)addr + (i * 0x10000);
+		break;				/* => 8 or 16 MB	*/
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* => no or unknown flash */
+	}
+
+	/* Put FLASH back in read mode */
+	flash_reset(info);
+
+	return (info->size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	FPWV *addr;
+	int flag, prot, sect;
+	int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL;
+	ulong start, now, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AMDLV065D:
+		break;
+	case FLASH_UNKNOWN:
+	default:
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	last  = get_timer(0);
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last && rcode == 0; sect++) {
+
+		if (info->protect[sect] != 0)	/* protected, skip it */
+			continue;
+
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+
+		addr = (FPWV *)(info->start[sect]);
+		if (intel) {
+			*addr = (FPW)0x00500050; /* clear status register */
+			*addr = (FPW)0x00200020; /* erase setup */
+			*addr = (FPW)0x00D000D0; /* erase confirm */
+		}
+		else {
+			/* must be AMD style if not Intel */
+			FPWV *base;		/* first address in bank */
+
+			base = (FPWV *)(info->start[0]);
+			base[FLASH_CYCLE1] = (FPW)0x00AA00AA;	/* unlock */
+			base[FLASH_CYCLE2] = (FPW)0x00550055;	/* unlock */
+			base[FLASH_CYCLE1] = (FPW)0x00800080;	/* erase mode */
+			base[FLASH_CYCLE1] = (FPW)0x00AA00AA;	/* unlock */
+			base[FLASH_CYCLE2] = (FPW)0x00550055;	/* unlock */
+			*addr = (FPW)0x00300030;	/* erase sector */
+		}
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts();
+
+		start = get_timer(0);
+
+		/* wait at least 50us for AMD, 80us for Intel.
+		 * Let's wait 1 ms.
+		 */
+		udelay (1000);
+
+		while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) {
+			if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+				printf ("Timeout\n");
+
+				if (intel) {
+					/* suspend erase	*/
+					*addr = (FPW)0x00B000B0;
+				}
+
+				flash_reset(info);	/* reset to read mode */
+				rcode = 1;		/* failed */
+				break;
+			}
+
+			/* show that we're waiting */
+			if ((get_timer(last)) > CFG_HZ) {/* every second */
+				putc ('.');
+				last = get_timer(0);
+			}
+		}
+
+		/* show that we're waiting */
+		if ((get_timer(last)) > CFG_HZ) {	/* every second */
+			putc ('.');
+			last = get_timer(0);
+		}
+
+		flash_reset(info);	/* reset to read mode	*/
+	}
+
+	printf (" done\n");
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */
+	int bytes;	  /* number of bytes to program in current word		*/
+	int left;	  /* number of bytes left to program			*/
+	int i, res;
+
+	for (left = cnt, res = 0;
+		 left > 0 && res == 0;
+		 addr += sizeof(data), left -= sizeof(data) - bytes) {
+
+		bytes = addr & (sizeof(data) - 1);
+		addr &= ~(sizeof(data) - 1);
+
+		/* combine source and destination data so can program
+		 * an entire word of 16 or 32 bits
+		 */
+		for (i = 0; i < sizeof(data); i++) {
+			data <<= 8;
+			if (i < bytes || i - bytes >= left )
+				data += *((uchar *)addr + i);
+			else
+				data += *src++;
+		}
+
+		/* write one word to the flash */
+		switch (info->flash_id & FLASH_VENDMASK) {
+		case FLASH_MAN_AMD:
+			res = write_word_amd(info, (FPWV *)addr, data);
+			break;
+		default:
+			/* unknown flash type, error! */
+			printf ("missing or unknown FLASH type\n");
+			res = 1;	/* not really a timeout, but gives error */
+			break;
+		}
+	}
+
+	return (res);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash for AMD FLASH
+ * A word is 16 or 32 bits, whichever the bus width of the flash bank
+ * (not an individual chip) is.
+ *
+ * returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data)
+{
+	ulong start;
+	int flag;
+	int res = 0;	/* result, assume success	*/
+	FPWV *base;		/* first address in flash bank	*/
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*dest & data) != data) {
+		return (2);
+	}
+
+
+	base = (FPWV *)(info->start[0]);
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	base[FLASH_CYCLE1] = (FPW)0x00AA00AA;	/* unlock */
+	base[FLASH_CYCLE2] = (FPW)0x00550055;	/* unlock */
+	base[FLASH_CYCLE1] = (FPW)0x00A000A0;	/* selects program mode */
+
+	*dest = data;		/* start programming the data	*/
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	start = get_timer (0);
+
+	/* data polling for D7 */
+	while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			*dest = (FPW)0x00F000F0;	/* reset bank */
+			res = 1;
+		}
+	}
+
+	return (res);
+}

board/icecube/icecube.c

@@ -0,0 +1,183 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+
+#ifndef CFG_RAMBOOT
+static long int dram_size(long int *base, long int maxsize)
+{
+	volatile long int *addr;
+	ulong cnt, val;
+	ulong save[32];			/* to make test non-destructive */
+	unsigned char i = 0;
+
+	for (cnt = (maxsize / sizeof (long)) >> 1; cnt > 0; cnt >>= 1) {
+		addr = base + cnt;		/* pointer arith! */
+
+		save[i++] = *addr;
+		*addr = ~cnt;
+	}
+
+	/* write 0 to base address */
+	addr = base;
+	save[i] = *addr;
+	*addr = 0;
+
+	/* check at base address */
+	if ((val = *addr) != 0) {
+		*addr = save[i];
+		return (0);
+	}
+
+	for (cnt = 1; cnt < maxsize / sizeof (long); cnt <<= 1) {
+		addr = base + cnt;		/* pointer arith! */
+
+		val = *addr;
+		*addr = save[--i];
+
+		if (val != (~cnt)) {
+			return (cnt * sizeof (long));
+		}
+	}
+	return (maxsize);
+}
+
+static void sdram_start (int hi_addr)
+{
+	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+	/* unlock mode register */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0000 | hi_addr_bit;
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0002 | hi_addr_bit;
+	/* set mode register */
+#if defined(CONFIG_MPC5200)
+	*(vu_long *)MPC5XXX_SDRAM_MODE = 0x408d0000;
+#elif defined(CONFIG_MGT5100)
+	*(vu_long *)MPC5XXX_SDRAM_MODE = 0x008d0000;
+#endif
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0002 | hi_addr_bit;
+	/* auto refresh */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0004 | hi_addr_bit;
+	/* set mode register */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = 0x008d0000;
+	/* normal operation */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = 0x504f0000 | hi_addr_bit;
+}
+#endif
+
+long int initdram (int board_type)
+{
+	ulong dramsize = 0;
+#ifndef CFG_RAMBOOT
+	ulong test1, test2;
+
+	/* configure SDRAM start/end */
+#if defined(CONFIG_MPC5200)
+	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
+
+	/* setup config registers */
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = 0xc2233a00;
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = 0x88b70004;
+
+#elif defined(CONFIG_MGT5100)
+	*(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
+	*(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
+	*(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
+
+	/* setup config registers */
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = 0xc2222600;
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = 0x88b70004;
+
+	/* address select register */
+	*(vu_long *)MPC5XXX_SDRAM_XLBSEL = 0x03000000;
+#endif
+	sdram_start(0);
+	test1 = dram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+	sdram_start(1);
+	test2 = dram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+#if defined(CONFIG_MPC5200)
+	*(vu_long *)MPC5XXX_SDRAM_CS0CFG =
+		(0x13 + __builtin_ffs(dramsize >> 20) - 1);
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
+#elif defined(CONFIG_MGT5100)
+	*(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
+#endif
+
+#else
+#ifdef CONFIG_MGT5100
+	*(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
+	dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
+#else
+	dramsize = ((1 << (*(vu_long *)MPC5XXX_SDRAM_CS0CFG - 0x13)) << 20);
+#endif
+#endif /* CFG_RAMBOOT */
+	/* return total ram size */
+	return dramsize;
+}
+
+int checkboard (void)
+{
+#if defined(CONFIG_MPC5200)
+	puts ("Board: Motorola MPC5200 (IceCube)\n");
+#elif defined(CONFIG_MGT5100)
+	puts ("Board: Motorola MGT5100 (IceCube)\n");
+#endif
+	return 0;
+}
+
+void flash_preinit(void)
+{
+	/*
+	 * Now, when we are in RAM, enable flash write
+	 * access for detection process.
+	 * Note that CS_BOOT cannot be cleared when
+	 * executing in flash.
+	 */
+#if defined(CONFIG_MGT5100)
+	*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
+	*(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
+#endif
+	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
+}
+
+#ifdef	CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+	pci_mpc5xxx_init(&hose);
+}
+#endif

board/icecube/u-boot.lds

@@ -0,0 +1,122 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc5xxx/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}

board/icu862/u-boot.lds

@@ -136,11 +136,6 @@ SECTIONS
    *(.bss)
    *(COMMON)
   }
-  . = ALIGN(256 * 1024);
-  .ppcenv	:
-  {
-    common/environment.o (.ppcenv)
-  }
   _end = . ;
   PROVIDE (end = .);
 }

board/ivm/ivm.c

@@ -246,14 +246,14 @@ initdram (int board_type)
     udelay(1);
     memctl->memc_mcr = 0x80806130;	/* autorefresh */
 
-    memctl->memc_mbmr |= MAMR_PTBE;	/* refresh enabled */
+    memctl->memc_mbmr |= MBMR_PTBE;	/* refresh enabled */
 
     /*
      * Check Bank 0 Memory Size for re-configuration
      */
     size_b0 = dram_size (CFG_MBMR_8COL, (ulong *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
 
-    memctl->memc_mbmr = CFG_MBMR_8COL | MAMR_PTBE;
+    memctl->memc_mbmr = CFG_MBMR_8COL | MBMR_PTBE;
 
     return (size_b0);
 }

board/lantec/lantec.c

@@ -149,7 +149,7 @@ long int initdram (int board_type)
 	udelay(1);		/* 0x80006106 */
 	memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x06);
 
-	memctl->memc_mamr |= MAMR_PTBE;	/* refresh enabled */
+	memctl->memc_mamr |= MAMR_PTAE;	/* refresh enabled */
 
 	udelay(200);
 
@@ -170,7 +170,7 @@ long int initdram (int board_type)
 			     (ulong *)SDRAM_BASE3_PRELIM,
 			     SDRAM_MAX_SIZE);
 
-	memctl->memc_mamr = CFG_MAMR_8COL | MAMR_PTBE;
+	memctl->memc_mamr = CFG_MAMR_8COL | MAMR_PTAE;
 
 	/*
 	 * Final mapping:

board/lwmon/lwmon.c

@@ -184,7 +184,7 @@ V* Verification: dzu@denx.de
  ***********************************************************************/
 int checkboard (void)
 {
-	puts ("Board: Litronic Monitor IV\n");
+	puts ("Board: LICCON Konsole LCD2\n");
 	return (0);
 }
 
@@ -246,7 +246,7 @@ long int initdram (int board_type)
 	udelay (1);				/* 0x80006106 */
 	memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x06);
 
-	memctl->memc_mamr |= MAMR_PTBE;	/* refresh enabled */
+	memctl->memc_mamr |= MAMR_PTAE;	/* refresh enabled */
 
 	udelay (200);
 
@@ -276,11 +276,11 @@ long int initdram (int board_type)
 
 	if (size8 < size9) {		/* leave configuration at 9 columns */
 		size_b0 = size9;
-		memctl->memc_mamr = CFG_MAMR_9COL | MAMR_PTBE;
+		memctl->memc_mamr = CFG_MAMR_9COL | MAMR_PTAE;
 		udelay (500);
 	} else {			/* back to 8 columns            */
 		size_b0 = size8;
-		memctl->memc_mamr = CFG_MAMR_8COL | MAMR_PTBE;
+		memctl->memc_mamr = CFG_MAMR_8COL | MAMR_PTAE;
 		udelay (500);
 	}
 
@@ -1071,3 +1071,22 @@ static int key_pressed(void)
 	return (compare_magic(kbd_data, CONFIG_MODEM_KEY_MAGIC) == 0);
 }
 #endif	/* CONFIG_MODEM_SUPPORT */
+
+#ifdef CONFIG_POST
+/*
+ * Returns 1 if keys pressed to start the power-on long-running tests
+ * Called from board_init_f().
+ */
+int post_hotkeys_pressed(void)
+{
+	uchar kbd_data[KEYBD_DATALEN];
+	uchar val;
+
+	/* Read keys */
+	val = KEYBD_CMD_READ_KEYS;
+	i2c_write (kbd_addr, 0, 0, &val, 1);
+	i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
+
+	return (compare_magic(kbd_data, CONFIG_POST_KEY_MAGIC) == 0);
+}
+#endif

board/mpc8260ads/flash.c

@@ -7,6 +7,11 @@
  * I started with board/ip860/flash.c and made changes I found in
  * the MTD project by David Schleef.
  *
+ * (C) Copyright 2003 Arabella Software Ltd.
+ * Yuli Barcohen <yuli@arabellasw.com>
+ * Re-written to support multi-bank flash SIMMs.
+ * Added support for real protection and JFFS2.
+ *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
@@ -28,73 +33,119 @@
 
 #include <common.h>
 
+/* Intel-compatible flash ID */
+#define INTEL_COMPAT  0x89898989
+#define INTEL_ALT     0xB0B0B0B0
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+/* Intel-compatible flash commands */
+#define INTEL_PROGRAM 0x10101010
+#define INTEL_ERASE   0x20202020
+#define INTEL_CLEAR   0x50505050
+#define INTEL_LOCKBIT 0x60606060
+#define INTEL_PROTECT 0x01010101
+#define INTEL_STATUS  0x70707070
+#define INTEL_READID  0x90909090
+#define INTEL_CONFIRM 0xD0D0D0D0
+#define INTEL_RESET   0xFFFFFFFF
 
-#if defined(CFG_ENV_IS_IN_FLASH)
-# ifndef  CFG_ENV_ADDR
-#  define CFG_ENV_ADDR	(CFG_FLASH_BASE + CFG_ENV_OFFSET)
-# endif
-# ifndef  CFG_ENV_SIZE
-#  define CFG_ENV_SIZE	CFG_ENV_SECT_SIZE
-# endif
-# ifndef  CFG_ENV_SECT_SIZE
-#  define CFG_ENV_SECT_SIZE  CFG_ENV_SIZE
-# endif
-#endif
+/* Intel-compatible flash status bits */
+#define INTEL_FINISHED 0x80808080
+#define INTEL_OK       0x80808080
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
 
 /*-----------------------------------------------------------------------
- * Functions
+ * This board supports 32-bit wide flash SIMMs (4x8-bit configuration.)
+ * Up to 32MB of flash supported (up to 4 banks.)
+ * BCSR is used for flash presence detect (page 4-65 of the User's Manual)
+ *
+ * The following code can not run from flash!
  */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info);
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-static int clear_block_lock_bit(vu_long * addr);
-
-/*-----------------------------------------------------------------------
- */
-
 unsigned long flash_init (void)
 {
-#ifndef CONFIG_MPC8260ADS
-	volatile immap_t	*immap  = (immap_t *)CFG_IMMR;
-	volatile memctl8xx_t	*memctl = &immap->im_memctl;
-	volatile ip860_bcsr_t	*bcsr   = (ip860_bcsr_t *)BCSR_BASE;
-#endif
-	unsigned long size;
-	int i;
+	ulong size = 0, sect_start, sect_size = 0, bank_size;
+	ushort sect_count = 0;
+	int i, j, nbanks;
+	vu_long *addr = (vu_long *)CFG_FLASH_BASE;
+	vu_long *bcsr = (vu_long *)CFG_BCSR;
 
-	/* Init: enable write,
-	 * or we cannot even write flash commands
-	 */
-#ifndef CONFIG_MPC8260ADS
-	bcsr->bd_ctrl |= BD_CTRL_FLWE;
-#endif
-
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
-		flash_info[i].flash_id = FLASH_UNKNOWN;
-
-		/* set the default sector offset */
+	switch (bcsr[2] & 0xF) {
+	case 0:
+		nbanks = 4;
+		break;
+	case 1:
+		nbanks = 2;
+		break;
+	case 2:
+		nbanks = 1;
+		break;
+	default:		/* Unsupported configurations */
+		nbanks = CFG_MAX_FLASH_BANKS;
 	}
 
-	/* Static FLASH Bank configuration here - FIXME XXX */
+	if (nbanks > CFG_MAX_FLASH_BANKS)
+		nbanks = CFG_MAX_FLASH_BANKS;
 
-	size = flash_get_size((vu_long *)FLASH_BASE, &flash_info[0]);
-
-	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
-		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
-			size, size<<20);
+	for (i = 0; i < nbanks; i++) {
+		*addr = INTEL_READID;	/* Read Intelligent Identifier */
+		if ((addr[0] == INTEL_COMPAT) || (addr[0] == INTEL_ALT)) {
+			switch (addr[1]) {
+			case SHARP_ID_28F016SCL:
+			case SHARP_ID_28F016SCZ:
+				flash_info[i].flash_id = FLASH_MAN_SHARP | FLASH_LH28F016SCT;
+				sect_count = 32;
+				sect_size = 0x40000;
+				break;
+			default:
+				flash_info[i].flash_id = FLASH_UNKNOWN;
+				sect_count = CFG_MAX_FLASH_SECT;
+				sect_size =
+				   CFG_FLASH_SIZE / CFG_MAX_FLASH_BANKS / CFG_MAX_FLASH_SECT;
+			}
+		}
+		else
+			flash_info[i].flash_id = FLASH_UNKNOWN;
+		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+			printf("### Unknown flash ID %08lX %08lX at address %08lX ###\n",
+			       addr[0], addr[1], (ulong)addr);
+			size = 0;
+			*addr = INTEL_RESET; /* Reset bank to Read Array mode */
+			break;
+		}
+		flash_info[i].sector_count = sect_count;
+		flash_info[i].size = bank_size = sect_size * sect_count;
+		size += bank_size;
+		sect_start = (ulong)addr;
+		for (j = 0; j < sect_count; j++) {
+			addr = (vu_long *)sect_start;
+			flash_info[i].start[j]   = sect_start;
+			flash_info[i].protect[j] = (addr[2] == 0x01010101);
+			sect_start += sect_size;
+		}
+		*addr = INTEL_RESET; /* Reset bank to Read Array mode */
+		addr = (vu_long *)sect_start;
 	}
-#ifndef CONFIG_MPC8260ADS
-	/* Remap FLASH according to real size */
-	memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size & 0xFFFF8000);
-	memctl->memc_br1 = (CFG_FLASH_BASE & BR_BA_MSK) |
-				(memctl->memc_br1 & ~(BR_BA_MSK));
-#endif
 
-	/* Re-do sizing to get full correct info */
-	size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
-
-	flash_info[0].size = size;
+	if (size == 0) {	/* Unknown flash, fill with hard-coded values */
+		sect_start = CFG_FLASH_BASE;
+		for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+			flash_info[i].flash_id = FLASH_UNKNOWN;
+			flash_info[i].size = CFG_FLASH_SIZE / CFG_MAX_FLASH_BANKS;
+			flash_info[i].sector_count = sect_count;
+			for (j = 0; j < sect_count; j++) {
+				flash_info[i].start[j]   = sect_start;
+				flash_info[i].protect[j] = 0;
+				sect_start += sect_size;
+			}
+		}
+		size = CFG_FLASH_SIZE;
+	}
+	else
+		for (i = nbanks; i < CFG_MAX_FLASH_BANKS; i++) {
+			flash_info[i].flash_id = FLASH_UNKNOWN;
+			flash_info[i].size = 0;
+			flash_info[i].sector_count = 0;
+		}
 
 #if CFG_MONITOR_BASE >= CFG_FLASH_BASE
 	/* monitor protection ON by default */
@@ -161,102 +212,6 @@ void flash_print_info  (flash_info_t *info)
 
 /*-----------------------------------------------------------------------
  */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-static ulong flash_get_size (vu_long *addr, flash_info_t *info)
-{
-	short i;
-	ulong value;
-	ulong base = (ulong)addr;
-	ulong sector_offset;
-
-	/* Write "Intelligent Identifier" command: read Manufacturer ID */
-	*addr = 0x90909090;
-
-	value = addr[0] & 0x00FF00FF;
-	switch (value) {
-	case MT_MANUFACT:	/* SHARP, MT or => Intel */
-	case INTEL_ALT_MANU:
-		info->flash_id = FLASH_MAN_INTEL;
-		break;
-	default:
-		printf("unknown manufacturer: %x\n", (unsigned int)value);
-		info->flash_id = FLASH_UNKNOWN;
-		info->sector_count = 0;
-		info->size = 0;
-		return (0);			/* no or unknown flash	*/
-	}
-
-	value = addr[1];			/* device ID		*/
-
-	switch (value) {
-	case (INTEL_ID_28F016S):
-		info->flash_id += FLASH_28F016SV;
-		info->sector_count = 32;
-		info->size = 0x00400000;
-		sector_offset = 0x20000;
-		break;				/* => 2x2 MB		*/
-
-	case (INTEL_ID_28F160S3):
-		info->flash_id += FLASH_28F160S3;
-		info->sector_count = 32;
-		info->size = 0x00400000;
-		sector_offset = 0x20000;
-		break;				/* => 2x2 MB		*/
-
-	case (INTEL_ID_28F320S3):
-		info->flash_id += FLASH_28F320S3;
-		info->sector_count = 64;
-		info->size = 0x00800000;
-		sector_offset = 0x20000;
-		break;				/* => 2x4 MB		*/
-
-	case SHARP_ID_28F016SCL:
-	case SHARP_ID_28F016SCZ:
-		info->flash_id      = FLASH_MAN_SHARP | FLASH_LH28F016SCT;
-		info->sector_count  = 32;
-		info->size          = 0x00800000;
-		sector_offset = 0x40000;
-		break;				/* => 4x2 MB		*/
-
-
-	default:
-		info->flash_id = FLASH_UNKNOWN;
-		return (0);			/* => no or unknown flash */
-
-	}
-
-	/* set up sector start address table */
-	for (i = 0; i < info->sector_count; i++) {
-		info->start[i] = base;
-		base += sector_offset;
-		/* don't know how to check sector protection */
-		info->protect[i] = 0;
-	}
-
-	/*
-	 * Prevent writes to uninitialized FLASH.
-	 */
-	if (info->flash_id != FLASH_UNKNOWN) {
-		addr = (vu_long *)info->start[0];
-
-		*addr = 0xFFFFFF;	/* reset bank to read array mode */
-	}
-
-	return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
 int	flash_erase (flash_info_t *info, int s_first, int s_last)
 {
 	int flag, prot, sect;
@@ -292,12 +247,6 @@ int	flash_erase (flash_info_t *info, int s_first, int s_last)
 		printf ("\n");
 	}
 
-	/* Make Sure Block Lock Bit is not set. */
-	if(clear_block_lock_bit((vu_long *)(info->start[s_first]))){
-		return 1;
-	}
-
-
 	/* Start erase on unprotected sectors */
 	for (sect = s_first; sect<=s_last; sect++) {
 		if (info->protect[sect] == 0) {	/* not protected */
@@ -308,36 +257,26 @@ int	flash_erase (flash_info_t *info, int s_first, int s_last)
 			/* Disable interrupts which might cause a timeout here */
 			flag = disable_interrupts();
 
-			/* Reset Array */
-			*addr = 0xffffffff;
 			/* Clear Status Register */
-			*addr = 0x50505050;
+			*addr = INTEL_CLEAR;
 			/* Single Block Erase Command */
-			*addr = 0x20202020;
+			*addr = INTEL_ERASE;
 			/* Confirm */
-			*addr = 0xD0D0D0D0;
+			*addr = INTEL_CONFIRM;
 
 			if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) {
 			    /* Resume Command, as per errata update */
-			    *addr = 0xD0D0D0D0;
+			    *addr = INTEL_CONFIRM;
 			}
 
 			/* re-enable interrupts if necessary */
 			if (flag)
 				enable_interrupts();
 
-			/* wait at least 80us - let's wait 1 ms */
-			udelay (1000);
-			while ((*addr & 0x80808080) != 0x80808080) {
-				if(*addr & 0x20202020){
-					printf("Error in Block Erase - Lock Bit may be set!\n");
-					printf("Status Register = 0x%X\n", (uint)*addr);
-					*addr = 0xFFFFFFFF;	/* reset bank */
-					return 1;
-				}
+			while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
 				if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
 					printf ("Timeout\n");
-					*addr = 0xFFFFFFFF;	/* reset bank */
+					*addr = INTEL_RESET;	/* reset bank */
 					return 1;
 				}
 				/* show that we're waiting */
@@ -347,8 +286,15 @@ int	flash_erase (flash_info_t *info, int s_first, int s_last)
 				}
 			}
 
+			if (*addr != INTEL_OK) {
+				printf("Block erase failed at %08X, CSR=%08X\n",
+				       (uint)addr, (uint)*addr);
+				*addr = INTEL_RESET;	/* reset bank */
+				return 1;
+			}
+
 			/* reset to read mode */
-			*addr = 0xFFFFFFFF;
+			*addr = INTEL_RESET;
 		}
 	}
 
@@ -356,6 +302,58 @@ int	flash_erase (flash_info_t *info, int s_first, int s_last)
 	return 0;
 }
 
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	ulong start;
+	int rc = 0;
+	int flag;
+	vu_long *addr = (vu_long *)dest;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		return (2);
+	}
+
+	*addr = INTEL_CLEAR; /* Clear status register */
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* Write Command */
+	*addr = INTEL_PROGRAM;
+
+	/* Write Data */
+	*addr = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			printf("Write timed out\n");
+			rc = 1;
+			break;
+		}
+	}
+	if (*addr != INTEL_OK) {
+		printf ("Write failed at %08X, CSR=%08X\n", (uint)addr, (uint)*addr);
+		rc = 1;
+	}
+
+	*addr = INTEL_RESET; /* Reset to read array mode */
+
+	return rc;
+}
+
 /*-----------------------------------------------------------------------
  * Copy memory to flash, returns:
  * 0 - OK
@@ -370,6 +368,8 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
 
 	wp = (addr & ~3);	/* get lower word aligned address */
 
+	*(vu_long *)wp = INTEL_RESET; /* Reset to read array mode */
+
 	/*
 	 * handle unaligned start bytes
 	 */
@@ -424,85 +424,125 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
 		data = (data << 8) | (*(uchar *)cp);
 	}
 
-	return (write_word(info, wp, data));
+	rc = write_word(info, wp, data);
+
+	return rc;
 }
 
 /*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
+ * Set/Clear sector's lock bit, returns:
  * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
+ * 1 - Error (timeout, voltage problems, etc.)
  */
-static int write_word (flash_info_t *info, ulong dest, ulong data)
+int flash_real_protect(flash_info_t *info, long sector, int prot)
 {
-	vu_long *addr = (vu_long *)dest;
-	ulong start, csr;
-	int flag;
+	ulong start;
+	int i;
+	int rc = 0;
+	vu_long *addr = (vu_long *)(info->start[sector]);
+	int flag = disable_interrupts();
 
-	/* Check if Flash is (sufficiently) erased */
-	if ((*addr & data) != data) {
-		return (2);
+	*addr = INTEL_CLEAR;	/* Clear status register */
+	if (prot) {			/* Set sector lock bit */
+		*addr = INTEL_LOCKBIT;	/* Sector lock bit */
+		*addr = INTEL_PROTECT;	/* set */
+	}
+	else {				/* Clear sector lock bit */
+		*addr = INTEL_LOCKBIT;	/* All sectors lock bits */
+		*addr = INTEL_CONFIRM;	/* clear */
 	}
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
 
-	/* Write Command */
-	*addr = 0x10101010;
-
-	/* Write Data */
-	*addr = data;
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts();
-
-	/* data polling for D7 */
-	start = get_timer (0);
-	flag  = 0;
-	while (((csr = *addr) & 0x80808080) != 0x80808080) {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
-			flag = 1;
+	start = get_timer(0);
+	while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
+		if (get_timer(start) > CFG_FLASH_UNLOCK_TOUT) {
+			printf("Flash lock bit operation timed out\n");
+			rc = 1;
 			break;
 		}
 	}
-	if (csr & 0x40404040) {
-		printf ("CSR indicates write error (%08lx) at %08lx\n", csr, (ulong)addr);
-		flag = 1;
+
+	if (*addr != INTEL_OK) {
+		printf("Flash lock bit operation failed at %08X, CSR=%08X\n",
+		       (uint)addr, (uint)*addr);
+		rc = 1;
 	}
 
-	/* Clear Status Registers Command */
-	*addr = 0x50505050;
-	/* Reset to read array mode */
-	*addr = 0xFFFFFFFF;
+	if (!rc)
+		info->protect[sector] = prot;
 
-	return (flag);
+	/*
+	 * Clear lock bit command clears all sectors lock bits, so
+	 * we have to restore lock bits of protected sectors.
+	 */
+	if (!prot)
+		for (i = 0; i < info->sector_count; i++)
+			if (info->protect[i]) {
+				addr = (vu_long *)(info->start[i]);
+				*addr = INTEL_LOCKBIT;	/* Sector lock bit */
+				*addr = INTEL_PROTECT;	/* set */
+				udelay(CFG_FLASH_LOCK_TOUT * 1000);
+			}
+
+	if (flag)
+		enable_interrupts();
+
+	*addr = INTEL_RESET;		/* Reset to read array mode */
+
+	return rc;
 }
 
 /*-----------------------------------------------------------------------
- * Clear Block Lock Bit, returns:
- * 0 - OK
- * 1 - Timeout
+ * Support for flash file system (JFFS2)
+ *
+ * We use custom partition info function because we have to fit the
+ * file system image between first sector (containing hard reset
+ * configuration word) and the sector containing U-Boot image. Standard
+ * partition info function does not allow for last sector specification
+ * and assumes that the file system occupies flash bank up to and
+ * including bank's last sector.
  */
+#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CFG_JFFS_CUSTOM_PART)
 
-static int clear_block_lock_bit(vu_long  * addr)
+#ifndef CFG_JFFS2_FIRST_SECTOR
+#define CFG_JFFS2_FIRST_SECTOR 0
+#endif
+#ifndef CFG_JFFS2_FIRST_BANK
+#define CFG_JFFS2_FIRST_BANK 0
+#endif
+#ifndef CFG_JFFS2_NUM_BANKS
+#define CFG_JFFS2_NUM_BANKS 1
+#endif
+#define CFG_JFFS2_LAST_BANK (CFG_JFFS2_FIRST_BANK + CFG_JFFS2_NUM_BANKS - 1)
+
+#include <jffs2/jffs2.h>
+
+static struct part_info partition;
+
+struct part_info *jffs2_part_info(int part_num)
 {
-	ulong start, now;
+	int i;
 
-	/* Reset Array */
-	*addr = 0xffffffff;
-	/* Clear Status Register */
-	*addr = 0x50505050;
+	if (part_num == 0) {
+		if (partition.usr_priv == 0) {
+			partition.offset =
+				(unsigned char *) flash_info[CFG_JFFS2_FIRST_BANK].start[CFG_JFFS2_FIRST_SECTOR];
+			for (i = CFG_JFFS2_FIRST_BANK; i <= CFG_JFFS2_LAST_BANK; i++)
+				partition.size += flash_info[i].size;
+			partition.size -=
+				flash_info[CFG_JFFS2_FIRST_BANK].start[CFG_JFFS2_FIRST_SECTOR] -
+				flash_info[CFG_JFFS2_FIRST_BANK].start[0];
+#ifdef CFG_JFFS2_LAST_SECTOR
+			i = flash_info[CFG_JFFS2_LAST_BANK].sector_count - 1;
+			partition.size -=
+				flash_info[CFG_JFFS2_LAST_BANK].start[i] -
+				flash_info[CFG_JFFS2_LAST_BANK].start[CFG_JFFS2_LAST_SECTOR];
+#endif
 
-	*addr = 0x60606060;
-	*addr = 0xd0d0d0d0;
-
-	start = get_timer (0);
-	while(*addr != 0x80808080){
-		if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
-			printf ("Timeout on clearing Block Lock Bit\n");
-			*addr = 0xFFFFFFFF;	/* reset bank */
-			return 1;
+			partition.usr_priv = (void *)1;
 		}
+		return &partition;
 	}
 	return 0;
 }
+
+#endif /* JFFS2 */

board/mpc8260ads/mpc8260ads.c

@@ -198,11 +198,19 @@ void reset_phy (void)
 	vu_long *bcsr = (vu_long *)CFG_BCSR;
 
 	/* reset the FEC port */
-	bcsr[1] &= ~FETH_RST;
+	bcsr[1] &= ~FETH1_RST;
 	udelay(2);
-	bcsr[1] |=  FETH_RST;
+	bcsr[1] |=  FETH1_RST;
 	udelay(1000);
 #ifdef CONFIG_MII
+#if CONFIG_ADSTYPE == CFG_PQ2FADS
+	/*
+	 * Do not bypass Rx/Tx (de)scrambler (fix configuration error)
+	 * Enable autonegotiation.
+	 */
+	miiphy_write(0, 16, 0x610);
+	miiphy_write(0, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
+#else
 	/*
 	 * Ethernet PHY is configured (by means of configuration pins)
 	 * to work at 10Mb/s only. We reconfigure it using MII
@@ -212,6 +220,7 @@ void reset_phy (void)
 	miiphy_write(0, PHY_ANAR, 0x01E1); /* Advertise all capabilities */
 	miiphy_write(0, PHY_DCR,  0x0000); /* Do not bypass Rx/Tx (de)scrambler */
 	miiphy_write(0, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
+#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
 #endif /* CONFIG_MII */
 }
 
@@ -219,7 +228,7 @@ int board_pre_init (void)
 {
 	vu_long *bcsr = (vu_long *)CFG_BCSR;
 
-	bcsr[1] = ~FETHIEN & ~RS232EN_1;
+	bcsr[1] = ~FETHIEN1 & ~RS232EN_1;
 
 	return 0;
 }
@@ -231,12 +240,10 @@ long int initdram (int board_type)
 	volatile immap_t *immap = (immap_t *) CFG_IMMR;
 	volatile memctl8260_t *memctl = &immap->im_memctl;
 	volatile uchar *ramaddr, c = 0xff;
-
-	/* Initialisation is for 16MB DIMM the board is shipped with */
-	long int msize = 16;
-	uint or    = 0xFF000CA0;
-	uint psdmr = CFG_PSDMR;
-	uint psrt  = CFG_PSRT;
+	long int msize;
+	uint or;
+	uint psdmr;
+	uint psrt;
 
 	int i;
 
@@ -246,22 +253,29 @@ long int initdram (int board_type)
 	immap->im_siu_conf.sc_tescr1   = 0x00004000;
 
 	memctl->memc_mptpr = CFG_MPTPR;
-	/* init local sdram, bank 4 */
-	memctl->memc_lsrt  = 0x00000010;
+#ifdef CFG_LSDRAM_BASE
+	/* Init local bus SDRAM */
+	memctl->memc_lsrt  = CFG_LSRT;
+#if CONFIG_ADSTYPE == CFG_PQ2FADS /* CS3 */
+	memctl->memc_or3   = 0xFF803280;
+	memctl->memc_br3   = CFG_LSDRAM_BASE | 0x00001861;
+#else  				  /* CS4 */
 	memctl->memc_or4   = 0xFFC01480;
-	memctl->memc_br4   = 0x04001861;
-	memctl->memc_lsdmr = 0x2886A522;
+	memctl->memc_br4   = CFG_LSDRAM_BASE | 0x00001861;
+#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
+	memctl->memc_lsdmr = CFG_LSDMR | 0x28000000;
 	ramaddr = (uchar *) CFG_LSDRAM_BASE;
 	*ramaddr = c;
-	memctl->memc_lsdmr = 0x0886A522;
+	memctl->memc_lsdmr = CFG_LSDMR | 0x08000000;
 	for (i = 0; i < 8; i++) {
 		*ramaddr = c;
 	}
-	memctl->memc_lsdmr = 0x1886A522;
+	memctl->memc_lsdmr = CFG_LSDMR | 0x18000000;
 	*ramaddr = c;
-	memctl->memc_lsdmr = 0x4086A522;
+	memctl->memc_lsdmr = CFG_LSDMR | 0x40000000;
+#endif /* CFG_LSDRAM_BASE */
 
-	/* init sdram dimm */
+	/* Init 60x bus SDRAM */
 #ifdef CONFIG_SPD_EEPROM
 	{
 		spd_eeprom_t spd;
@@ -398,6 +412,16 @@ long int initdram (int board_type)
 		printf ("OR=%X, PSDMR=%08X, PSRT=%0X\n", or, psdmr, psrt);
 #endif /* SPD_DEBUG */
 	}
+#else  /* !CONFIG_SPD_EEPROM */
+#if CONFIG_ADSTYPE == CFG_PQ2FADS
+	msize = 32;
+	or = 0xFE002EC0;
+#else
+	msize = 16;
+	or = 0xFF000CA0;
+#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
+	psdmr = CFG_PSDMR;
+	psrt  = CFG_PSRT;
 #endif /* CONFIG_SPD_EEPROM */
 	memctl->memc_psrt = psrt;
 	memctl->memc_or2 = or;
@@ -415,12 +439,20 @@ long int initdram (int board_type)
 	*ramaddr = c;
 #endif
 
-	/* return total ram size of DIMM */
+	/* return total 60x bus SDRAM size */
 	return (msize * 1024 * 1024);
 }
 
 int checkboard (void)
 {
+#if   CONFIG_ADSTYPE == CFG_8260ADS
 	puts ("Board: Motorola MPC8260ADS\n");
+#elif CONFIG_ADSTYPE == CFG_8266ADS
+	puts ("Board: Motorola MPC8266ADS\n");
+#elif CONFIG_ADSTYPE == CFG_PQ2FADS
+	puts ("Board: Motorola PQ2FADS-ZU\n");
+#else
+	puts ("Board: unknown\n");
+#endif
 	return 0;
 }

board/mpl/common/flash.c

@@ -105,6 +105,8 @@ unsigned long flash_init (void)
 			CFG_MONITOR_BASE+monitor_flash_len-1,
 			&flash_info[0]);
 #endif
+	/* protect reset vector */
+	flash_info[0].protect[flash_info[0].sector_count-1] = 1;
 	size_b1 = 0 ;
 	flash_info[0].size = size_b0;
 #if 0

board/mpl/common/memtst.c

@@ -494,7 +494,7 @@ void mem_test_reloc(void)
 }
 
 
-int mem_test (unsigned long start, unsigned long ramsize, int quiet, int reloc)
+int mem_test (unsigned long start, unsigned long ramsize, int quiet)
 {
 	unsigned long errors, stage;
 	unsigned long startaddr, size, i;

board/mpl/common/pci_parts.h

@@ -110,7 +110,7 @@ static struct pci_pip405_config_entry piix4_ide_cntrl_f1[] = {
 #if !defined(CONFIG_MIP405T)
 	{PCI_CFG_PIIX4_IDETIM,	0x80008000,	4}, /* enable Both IDE channels	*/
 #else
-	{PCI_CFG_PIIX4_IDETIM,	0x80000000,	4}, /* enable IDE channel0	*/
+	{PCI_CFG_PIIX4_IDETIM,	0x00008000,	4}, /* enable IDE channel0	*/
 #endif
 	{ }					    /* end of device table 	*/
 };

board/mpl/mip405/mip405.c

@@ -69,6 +69,7 @@
 #include <miiphy.h>
 #include "../common/common_util.h"
 #include <i2c.h>
+#include <rtc.h>
 extern block_dev_desc_t * scsi_get_dev(int dev);
 extern block_dev_desc_t * ide_get_dev(int dev);
 
@@ -110,14 +111,14 @@ typedef struct {
 } sdram_t;
 #if defined(CONFIG_MIP405T)
 const sdram_t sdram_table[] = {
-	{ 0x01,	/* MIP405T Rev A, 64MByte -1 Board */
+	{ 0x0F,	/* MIP405T Rev A, 64MByte -1 Board */
 		3,	/* Case Latenty = 3 */
 		3,	/* trp 20ns / 7.5 ns datain[27] */
 		3,	/* trcd 20ns /7.5 ns (datain[29]) */
 		6,	/* tras 44ns /7.5 ns  (datain[30]) */
 		4,	/* tcpt 44 - 20ns = 24ns */
-		3,	/* Address Mode = 3 (13x9x4) */
-		4,	/* size value (64MByte) */
+		2,	/* Address Mode = 2 (12x9x4) */
+		3,	/* size value (32MByte) */
 		0},	/* ECC disabled */
 	{ 0xff, /* terminator */
 	  0xff,
@@ -281,11 +282,6 @@ int init_sdram (void)
 	if((bc & 0x80)==0x80)
 		SDRAM_err ("U-Boot configured for a MIP405 not for a MIP405T!!!\n");
 #endif
-#if !defined(CONFIG_MIP405T)
-	/* since the ECC initialisation needs some time,
-	 * we show that we're alive
-	 */
-	serial_puts ("\nInitializing SDRAM, Please stand by");
 	/* set-up the chipselect machine */
 	mtdcr (ebccfga, pb0cr);		/* get cs0 config reg */
 	tmp = mfdcr (ebccfgd);
@@ -311,7 +307,6 @@ int init_sdram (void)
 	mtdcr (ebccfgd, UART1_AP);
 	mtdcr (ebccfga, pb3cr);
 	mtdcr (ebccfgd, UART1_CR);
-#endif
 	bc = in8 (PLD_BOARD_CFG_REG);
 #ifdef SDRAM_DEBUG
 	serial_puts ("\nstart SDRAM Setup\n");
@@ -333,6 +328,11 @@ int init_sdram (void)
 	write_hex (i);
 	serial_puts (" \n");
 #endif
+	/* since the ECC initialisation needs some time,
+	 * we show that we're alive
+	 */
+	if (sdram_table[i].ecc)
+		serial_puts ("\nInitializing SDRAM, Please stand by");
 	cal_val = sdram_table[i].cal - 1;	/* Cas Latency */
 	trp_clocks = sdram_table[i].trp;	/* 20ns / 7.5 ns datain[27] */
 	trcd_clocks = sdram_table[i].trcd;	/* 20ns /7.5 ns (datain[29]) */
@@ -559,7 +559,7 @@ void get_pcbrev_var(unsigned char *pcbrev, unsigned char *var)
 	unsigned char bc;
 	bc = in8 (PLD_BOARD_CFG_REG);
 	*pcbrev=(bc >> 4) & 0xf;
-	*var=bc & 0xf ;
+	*var=16-(bc & 0xf);
 #endif
 }
 
@@ -654,8 +654,6 @@ long int initdram (int board_type)
 
 /* ------------------------------------------------------------------------- */
 
-extern int mem_test (unsigned long start, unsigned long ramsize,
-					 int quiet);
 
 static int test_dram (unsigned long ramsize)
 {
@@ -666,8 +664,15 @@ static int test_dram (unsigned long ramsize)
 	return (1);
 }
 
+/* used to check if the time in RTC is valid */
+static unsigned long start;
+static struct rtc_time tm;
+
 int misc_init_r (void)
 {
+	/* check, if RTC is running */
+	rtc_get (&tm);
+	start=get_timer(0);
 	/* if MIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */
 	if (mfdcr(strap) & PSR_ROM_LOC)
 	       mtspr(ccr0, (mfspr(ccr0) & ~0x80));
@@ -688,9 +693,13 @@ void print_mip405_rev (void)
 }
 
 extern void mem_test_reloc(void);
+extern int mk_date (char *, struct rtc_time *);
 
 int last_stage_init (void)
 {
+	unsigned long stop;
+	struct rtc_time newtm;
+	unsigned char *s;
 	mem_test_reloc();
 	/* write correct LED configuration */
 	if (miiphy_write (0x1, 0x14, 0x2402) != 0) {
@@ -704,6 +713,25 @@ int last_stage_init (void)
 	print_mip405_rev ();
 	show_stdio_dev ();
 	check_env ();
+	/* check if RTC time is valid */
+	stop=get_timer(start);
+	while(stop<1200) {   /* we wait 1.2 sec to check if the RTC is running */
+		udelay(1000);
+		stop=get_timer(start);
+	}
+	rtc_get (&newtm);
+	if(tm.tm_sec==newtm.tm_sec) {
+		s=getenv("defaultdate");
+		if(!s)
+			mk_date ("010112001970", &newtm);
+		else
+			if(mk_date (s, &newtm)!=0) {
+				printf("RTC: Bad date format in defaultdate\n");
+				return 0;
+			}
+		rtc_reset ();
+		rtc_set(&newtm);
+	}
 	return 0;
 }
 
@@ -745,10 +773,10 @@ void print_mip405_info (void)
 	printf ("SER1 uses handshakes %s\n",
 			(ext & 0x80) ? "DTR/DSR" : "RTS/CTS");
 #else
-	printf ("User Config Switch %d %d %d %d %d %d %d %d %d\n",
+	printf ("User Config Switch %d %d %d %d %d %d %d %d\n",
 			(ext) & 0x1, (ext >> 1) & 0x1, (ext >> 2) & 0x1,
 			(ext >> 3) & 0x1, (ext >> 4) & 0x1, (ext >> 5) & 0x1,
-			(ext >> 6) & 0x1,(ext >> 7) & 0x1,(ext >> 8) & 0x1);
+			(ext >> 6) & 0x1,(ext >> 7) & 0x1);
 #endif
 	printf ("IDE Reset %s\n", (ext & 0x01) ? "asserted" : "not asserted");
 	printf ("IRQs:\n");

board/mvs1/u-boot.lds

@@ -57,7 +57,6 @@ SECTIONS
     /* the sector layout of our flash chips!	XXX FIXME XXX	*/
 
     cpu/mpc8xx/start.o		(.text)
-    cpu/mpc8xx/speed.o		(.text)
     common/dlmalloc.o		(.text)
     lib_ppc/ppcstring.o		(.text)
     lib_generic/vsprintf.o	(.text)
@@ -67,7 +66,6 @@ SECTIONS
     lib_generic/string.o	(.text)
     lib_ppc/extable.o		(.text)
     lib_ppc/kgdb.o		(.text)
-/*  lib_ppc/ticks.o		(.text) */
 
   . = env_offset;
     common/environment.o(.text)

board/omap1510inn/Makefile

@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= omap1510innovator.o flash.o
+SOBJS	:= platform.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################

board/omap1510inn/config.mk

@@ -0,0 +1,25 @@
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+#
+# (C) Copyright 2003
+# Texas Instruments, <www.ti.com>
+# Kshitij Gupta <Kshitij@ti.com>
+#
+# TI Innovator board with OMAP1510 (ARM925T) cpu
+# see http://www.ti.com/ for more information on Texas Insturments
+#
+# Innovator has 1 bank of 256 MB SDRAM
+# Physical Address:
+# 1000'0000 to 2000'0000
+#
+#
+# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000  (mem base + reserved)
+#
+# we load ourself to 1100'0000
+#
+#
+
+
+TEXT_BASE = 0x11000000

board/omap1510inn/flash.c

@@ -0,0 +1,428 @@
+/*
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+
+#define PHYS_FLASH_SECT_SIZE    0x00020000	/* 256 KB sectors (x2) */
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+
+/* Board support for 1 or 2 flash devices */
+#undef FLASH_PORT_WIDTH32
+#define FLASH_PORT_WIDTH16
+
+#ifdef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH	ushort
+#define FLASH_PORT_WIDTHV	vu_short
+#define SWAP(x)			__swab16(x)
+#else
+#define FLASH_PORT_WIDTH	ulong
+#define FLASH_PORT_WIDTHV	vu_long
+#define SWAP(x)			__swab32(x)
+#endif
+
+#define FPW	FLASH_PORT_WIDTH
+#define FPWV	FLASH_PORT_WIDTHV
+
+#define mb() __asm__ __volatile__ ("" : : : "memory")
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (FPW * addr, flash_info_t * info);
+static int write_data (flash_info_t * info, ulong dest, FPW data);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+void inline spin_wheel (void);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	int i;
+	ulong size = 0;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		switch (i) {
+		case 0:
+			flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
+			flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
+			break;
+		default:
+			panic ("configured to many flash banks!\n");
+			break;
+		}
+		size += flash_info[i].size;
+	}
+
+	/* Protect monitor and environment sectors
+	 */
+	flash_protect ( FLAG_PROTECT_SET,
+			CFG_FLASH_BASE,
+			CFG_FLASH_BASE + monitor_flash_len - 1,
+			&flash_info[0]);
+
+	flash_protect ( FLAG_PROTECT_SET,
+			CFG_ENV_ADDR,
+			CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+			&flash_info[0]);
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
+			info->protect[i] = 0;
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F128J3A:
+		printf ("28F128J3A\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (FPW * addr, flash_info_t * info)
+{
+	volatile FPW value;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x5555] = (FPW) 0x00AA00AA;
+	addr[0x2AAA] = (FPW) 0x00550055;
+	addr[0x5555] = (FPW) 0x00900090;
+
+	mb ();
+	value = addr[0];
+
+	switch (value) {
+
+	case (FPW) INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+		return (0);			/* no or unknown flash  */
+	}
+
+	mb ();
+	value = addr[1];			/* device ID        */
+	switch (value) {
+
+	case (FPW) INTEL_ID_28F128J3A:
+		info->flash_id += FLASH_28F128J3A;
+		info->sector_count = 128;
+		info->size = 0x02000000;
+		break;				/* => 16 MB     */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+			info->sector_count, CFG_MAX_FLASH_SECT);
+		info->sector_count = CFG_MAX_FLASH_SECT;
+	}
+
+	addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong type, start, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	/*start = get_timer (0); */
+	last = start;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			FPWV *addr = (FPWV *) (info->start[sect]);
+			FPW status;
+
+			printf ("Erasing sector %2d ... ", sect);
+
+			/* arm simple, non interrupt dependent timer */
+			reset_timer_masked ();
+
+			*addr = (FPW) 0x00500050;	/* clear status register */
+			*addr = (FPW) 0x00200020;	/* erase setup */
+			*addr = (FPW) 0x00D000D0;	/* erase confirm */
+
+			while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+				if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					*addr = (FPW) 0x00B000B0;	/* suspend erase     */
+					*addr = (FPW) 0x00FF00FF;	/* reset to read mode */
+					rcode = 1;
+					break;
+				}
+			}
+
+			*addr = (FPW) 0x00500050;	/* clear status register cmd.   */
+			*addr = (FPW) 0x00FF00FF;	/* resest to read mode          */
+
+			printf (" done\n");
+		}
+	}
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	FPW data;
+	int count, i, l, rc, port_width;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+/* get lower word aligned address */
+#ifdef FLASH_PORT_WIDTH16
+	wp = (addr & ~1);
+	port_width = 2;
+#else
+	wp = (addr & ~3);
+	port_width = 4;
+#endif
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < port_width && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < port_width; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	count = 0;
+	while (cnt >= port_width) {
+		data = 0;
+		for (i = 0; i < port_width; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+		cnt -= port_width;
+		if (count++ > 0x800) {
+			spin_wheel ();
+			count = 0;
+		}
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < port_width; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_data (info, wp, SWAP (data)));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t * info, ulong dest, FPW data)
+{
+	FPWV *addr = (FPWV *) dest;
+	ulong status;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr);
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	*addr = (FPW) 0x00400040;	/* write setup */
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();
+
+	/* wait while polling the status register */
+	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+
+		if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+			return (1);
+		}
+	}
+
+	*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (0);
+}
+
+void inline spin_wheel (void)
+{
+	static int p = 0;
+	static char w[] = "\\/-";
+
+	printf ("\010%c", w[p]);
+	(++p == 3) ? (p = 0) : 0;
+}

board/omap1510inn/omap1510innovator.c

@@ -0,0 +1,131 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+static void flash__init (void);
+static void ether__init (void);
+
+static inline void delay (unsigned long loops)
+{
+	__asm__ volatile ("1:\n"
+			  "subs %0, %1, #1\n"
+			  "bne 1b":"=r" (loops):"0" (loops));
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* arch number of OMAP 1510-Board */
+	gd->bd->bi_arch_number = 234;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0x10000100;
+
+/* kk - this speeds up your boot a quite a bit.  However to make it
+ *  work, you need make sure your kernel startup flush bug is fixed.
+ *  ... rkw ...
+ */
+	icache_enable ();
+
+	flash__init ();
+	ether__init ();
+	return 0;
+}
+
+
+int misc_init_r (void)
+{
+	/* volatile ushort *gdir = (ushort *) (GPIO_DIR_CONTROL_REG); */
+	/* volatile ushort *mdir = (ushort *) (MPUIO_DIR_CONTROL_REG); */
+
+	/* setup gpio direction to match board (no floats!) */
+	/**gdir = 0xCFF9; */
+	/**mdir = 0x103F; */
+
+	return (0);
+}
+
+/******************************
+ Routine:
+ Description:
+******************************/
+static void flash__init (void)
+{
+#define CS0_CHIP_SELECT_REG 0xfffecc10
+#define CS3_CHIP_SELECT_REG 0xfffecc1c
+#define EMIFS_GlB_Config_REG 0xfffecc0c
+
+	{
+		unsigned int regval;
+
+		regval = *((volatile unsigned int *) EMIFS_GlB_Config_REG);
+		regval = regval | 0x0001;	/* Turn off write protection for flash devices. */
+		if (regval & 0x0002) {
+			regval = regval & 0xfffd;	/* Swap CS0 and CS3 so that flash is visible at 0x0 and eeprom at 0x0c000000. */
+			/* If, instead, you want to reference flash at 0x0c000000, then it seemed the following were necessary. */
+			/* *((volatile unsigned int *)CS0_CHIP_SELECT_REG) = 0x202090; / * Overrides head.S setting of 0x212090 */
+			/* *((volatile unsigned int *)CS3_CHIP_SELECT_REG) = 0x202090; / * Let's flash chips be fully functional. */
+		}
+		*((volatile unsigned int *) EMIFS_GlB_Config_REG) = regval;
+	}
+}
+
+
+/******************************
+ Routine:
+ Description:
+******************************/
+static void ether__init (void)
+{
+#define ETH_CONTROL_REG 0x0800000b
+	/* take the Ethernet controller out of reset and wait
+	 * for the EEPROM load to complete.
+	 */
+	*((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01;
+	udelay (3);
+}
+
+
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}

board/omap1510inn/platform.S

@@ -0,0 +1,389 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ *
+ * -- Some bits of code used from rrload's head_OMAP1510.s --
+ * Copyright (C) 2002 RidgeRun, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+#if defined(CONFIG_OMAP1510)
+#include <./configs/omap1510.h>
+#endif
+
+#define OMAP1510_CLKS ((1<<EN_XORPCK)|(1<<EN_PERCK)|(1<<EN_TIMCK)|(1<<EN_GPIOCK))
+
+
+_TEXT_BASE:
+	.word	TEXT_BASE        /* sdram load addr from config.mk */
+
+.globl platformsetup
+platformsetup:
+
+	/*
+	 * Configure 1510 pins functions to match our board.
+	 */
+	ldr     r0, REG_PULL_DWN_CTRL_0
+	ldr     r1, VAL_PULL_DWN_CTRL_0
+	str     r1, [r0]
+	ldr     r0, REG_PULL_DWN_CTRL_1
+	ldr     r1, VAL_PULL_DWN_CTRL_1
+	str     r1, [r0]
+	ldr     r0, REG_PULL_DWN_CTRL_2
+	ldr     r1, VAL_PULL_DWN_CTRL_2
+	str     r1, [r0]
+	ldr     r0, REG_PULL_DWN_CTRL_3
+	ldr     r1, VAL_PULL_DWN_CTRL_3
+	str     r1, [r0]
+	ldr     r0, REG_FUNC_MUX_CTRL_4
+	ldr     r1, VAL_FUNC_MUX_CTRL_4
+	str     r1, [r0]
+	ldr     r0, REG_FUNC_MUX_CTRL_5
+	ldr     r1, VAL_FUNC_MUX_CTRL_5
+	str     r1, [r0]
+	ldr     r0, REG_FUNC_MUX_CTRL_6
+	ldr     r1, VAL_FUNC_MUX_CTRL_6
+	str     r1, [r0]
+	ldr     r0, REG_FUNC_MUX_CTRL_7
+	ldr     r1, VAL_FUNC_MUX_CTRL_7
+	str     r1, [r0]
+	ldr     r0, REG_FUNC_MUX_CTRL_8
+	ldr     r1, VAL_FUNC_MUX_CTRL_8
+	str     r1, [r0]
+	ldr     r0, REG_FUNC_MUX_CTRL_9
+	ldr     r1, VAL_FUNC_MUX_CTRL_9
+	str     r1, [r0]
+	ldr     r0, REG_FUNC_MUX_CTRL_A
+	ldr     r1, VAL_FUNC_MUX_CTRL_A
+	str     r1, [r0]
+	ldr     r0, REG_FUNC_MUX_CTRL_B
+	ldr     r1, VAL_FUNC_MUX_CTRL_B
+	str     r1, [r0]
+	ldr     r0, REG_FUNC_MUX_CTRL_C
+	ldr     r1, VAL_FUNC_MUX_CTRL_C
+	str     r1, [r0]
+	ldr     r0, REG_FUNC_MUX_CTRL_D
+	ldr     r1, VAL_FUNC_MUX_CTRL_D
+	str     r1, [r0]
+	ldr     r0, REG_VOLTAGE_CTRL_0
+	ldr     r1, VAL_VOLTAGE_CTRL_0
+	str     r1, [r0]
+	ldr     r0, REG_TEST_DBG_CTRL_0
+	ldr     r1, VAL_TEST_DBG_CTRL_0
+	str     r1, [r0]
+	ldr     r0, REG_MOD_CONF_CTRL_0
+	ldr     r1, VAL_MOD_CONF_CTRL_0
+	str     r1, [r0]
+
+	/* Move to 1510 mode */
+	ldr     r0, REG_COMP_MODE_CTRL_0
+	ldr     r1, VAL_COMP_MODE_CTRL_0
+	str     r1, [r0]
+
+	/* Set up Traffic Ctlr*/
+	ldr r0, REG_TC_IMIF_PRIO
+	mov r1, #0x0
+	str r1, [r0]
+	ldr r0, REG_TC_EMIFS_PRIO
+	str r1, [r0]
+	ldr r0, REG_TC_EMIFF_PRIO
+	str r1, [r0]
+
+	ldr r0, REG_TC_EMIFS_CONFIG
+	ldr r1, [r0]
+	bic r1, r1, #0x08   /* clear the global power-down enable PDE bit */
+	bic r1, r1, #0x01   /* write protect flash by clearing the WP bit */
+	str r1, [r0]        /* EMIFS GlB Configuration. (value 0x12 most likely) */
+
+	/* Setup some clock domains */
+	ldr r1, =OMAP1510_CLKS
+	ldr r0, REG_ARM_IDLECT2
+	strh r1, [r0]  /* CLKM, Clock domain control. */
+
+	mov r1, #0x01  /* PER_EN bit */
+	ldr r0, REG_ARM_RSTCT2
+	strh r1, [r0]  /* CLKM; Peripheral reset. */
+
+	/* Set CLKM to Sync-Scalable  */
+	/* I supposidly need to enable the dsp clock before switching */
+	mov r1, #0x1000
+	ldr r0, REG_ARM_SYSST
+	strh r1, [r0]
+	mov r0, #0x400
+1:
+	subs r0, r0, #0x1   /* wait for any bubbles to finish */
+	bne 1b
+
+	ldr r1, VAL_ARM_CKCTL  /* use 12Mhz ref, PER must be <= 50Mhz so /2 */
+	ldr r0, REG_ARM_CKCTL
+	strh r1, [r0]
+
+	/* setup DPLL 1 */
+	ldr r1, VAL_DPLL1_CTL
+	ldr r0, REG_DPLL1_CTL
+	strh r1, [r0]
+	ands r1, r1, #0x10  /* Check if PLL is enabled. */
+	beq lock_end        /* Do not look for lock if BYPASS selected */
+2:
+	ldrh r1, [r0]
+	ands r1, r1, #0x01  /* Check the LOCK bit. */
+	beq 2b              /* ...loop until bit goes hi. */
+lock_end:
+
+	/* Set memory timings corresponding to the new clock speed */
+
+	/* Check execution location to determine current execution location
+	 * and branch to appropriate initialization code.
+	 */
+	mov r0, #0x10000000                 /* Load physical SDRAM base. */
+	mov r1, pc                          /* Get current execution location. */
+	cmp r1, r0                          /* Compare. */
+	bge skip_sdram                      /* Skip over EMIF-fast initialization if running from SDRAM. */
+
+	/*
+	 * Delay for SDRAM initialization.
+	 */
+	mov r3, #0x1800                        /* value should be checked */
+3:
+	subs r3, r3, #0x1                     /* Decrement count */
+	bne 3b
+
+	/*
+	 * Set SDRAM control values. Disable refresh before MRS command.
+	 */
+	ldr r0, VAL_TC_EMIFF_SDRAM_CONFIG   /* get good value */
+	bic r3, r0, #0xC                    /* (BIT3|BIT2) ulConfig with auto-refresh disabled. */
+	orr r3, r3, #0x8000000              /* (BIT27) Disable CLK when Power down or Self-Refresh */
+	orr r3, r3, #0x4000000              /* BIT26 Power Down Enable */
+	ldr r2, REG_TC_EMIFF_SDRAM_CONFIG   /* Point to configuration register. */
+	str r3, [r2]                        /* Store the passed value with AR disabled. */
+
+	ldr r1, VAL_TC_EMIFF_MRS            /* get MRS value */
+	ldr r2, REG_TC_EMIFF_MRS            /* Point to MRS register. */
+	str r1, [r2]                        /* Store the passed value.*/
+
+	ldr r2, REG_TC_EMIFF_SDRAM_CONFIG   /* Point to configuration register. */
+	str r0, [r2]                        /* Store the passed value. */
+
+	/*
+	 * Delay for SDRAM initialization.
+	 */
+	mov r3, #0x1800
+4:
+	subs r3, r3, #1                     /* Decrement count. */
+	bne 4b
+
+skip_sdram:
+
+	/* slow interface */
+	ldr r1, VAL_TC_EMIFS_CS0_CONFIG
+	ldr r0, REG_TC_EMIFS_CS0_CONFIG
+	str r1, [r0] /* Chip Select 0 */
+	ldr r1, VAL_TC_EMIFS_CS1_CONFIG
+	ldr r0, REG_TC_EMIFS_CS1_CONFIG
+	str r1, [r0] /* Chip Select 1 */
+	ldr r1, VAL_TC_EMIFS_CS2_CONFIG
+	ldr r0, REG_TC_EMIFS_CS2_CONFIG
+	str r1, [r0] /* Chip Select 2 */
+	ldr r1, VAL_TC_EMIFS_CS3_CONFIG
+	ldr r0, REG_TC_EMIFS_CS3_CONFIG
+	str r1, [r0] /* Chip Select 3 */
+
+ /* Next, Enable the RS232 Line Drivers in the FPGA. */
+ /* Also, power on the audio CODEC's amplifier here, */
+ /* which will make a noise on the audio output. */
+ /* This is done here instead of in the kernel so there */
+ /* isn't a loud popping noise at the start of each */
+ /* song. */
+ /* Also, disable the CODEC's clocks. */
+ /* omap1510-HelenP1 [specific] */
+
+	ldr r0, REG_FPGA_POWER
+	mov r1, #0
+	ldr r2, REG_FPGA_DIP_SWITCH
+	ldrb r3, [r2]
+	cmp r3, #0x8
+	movne r1, #0x62     /* Enable the RS232 Line Drivers in the EPLD */
+	strb r1, [r0]
+	ldr r0, REG_FPGA_AUDIO
+	mov r1, #0x0     /* Disable sound driver (CODEC clocks) */
+	strb r1, [r0]
+
+	/* back to arch calling code */
+	mov	pc, lr
+
+/* the literal pools origin */
+	.ltorg
+
+/* OMAP configuration registers */
+REG_FUNC_MUX_CTRL_0:		/* 32 bits */
+	.word 0xfffe1000
+REG_FUNC_MUX_CTRL_1:		/* 32 bits */
+	.word 0xfffe1004
+REG_FUNC_MUX_CTRL_2:		/* 32 bits */
+	.word 0xfffe1008
+REG_COMP_MODE_CTRL_0:		/* 32 bits */
+	.word 0xfffe100c
+REG_FUNC_MUX_CTRL_3:		/* 32 bits */
+	.word 0xfffe1010
+REG_FUNC_MUX_CTRL_4:		/* 32 bits */
+	.word 0xfffe1014
+REG_FUNC_MUX_CTRL_5:		/* 32 bits */
+	.word 0xfffe1018
+REG_FUNC_MUX_CTRL_6:		/* 32 bits */
+	.word 0xfffe101c
+REG_FUNC_MUX_CTRL_7:		/* 32 bits */
+	.word 0xfffe1020
+REG_FUNC_MUX_CTRL_8:		/* 32 bits */
+	.word 0xfffe1024
+REG_FUNC_MUX_CTRL_9:		/* 32 bits */
+	.word 0xfffe1028
+REG_FUNC_MUX_CTRL_A:		/* 32 bits */
+	.word 0xfffe102C
+REG_FUNC_MUX_CTRL_B:		/* 32 bits */
+	.word 0xfffe1030
+REG_FUNC_MUX_CTRL_C:		/* 32 bits */
+	.word 0xfffe1034
+REG_FUNC_MUX_CTRL_D:		/* 32 bits */
+	.word 0xfffe1038
+REG_PULL_DWN_CTRL_0:		/* 32 bits */
+	.word 0xfffe1040
+REG_PULL_DWN_CTRL_1:		/* 32 bits */
+	.word 0xfffe1044
+REG_PULL_DWN_CTRL_2:		/* 32 bits */
+	.word 0xfffe1048
+REG_PULL_DWN_CTRL_3:		/* 32 bits */
+	.word 0xfffe104c
+REG_VOLTAGE_CTRL_0:		/* 32 bits */
+	.word 0xfffe1060
+REG_TEST_DBG_CTRL_0:		/* 32 bits */
+	.word 0xfffe1070
+REG_MOD_CONF_CTRL_0:		/* 32 bits */
+	.word 0xfffe1080
+REG_TC_IMIF_PRIO:		/* 32 bits */
+	.word 0xfffecc00
+REG_TC_EMIFS_PRIO:		/* 32 bits */
+	.word 0xfffecc04
+REG_TC_EMIFF_PRIO:		/* 32 bits */
+	.word 0xfffecc08
+REG_TC_EMIFS_CONFIG:		/* 32 bits */
+	.word 0xfffecc0c
+REG_TC_EMIFS_CS0_CONFIG:	/* 32 bits */
+	.word 0xfffecc10
+REG_TC_EMIFS_CS1_CONFIG:	/* 32 bits */
+	.word 0xfffecc14
+REG_TC_EMIFS_CS2_CONFIG:	/* 32 bits */
+	.word 0xfffecc18
+REG_TC_EMIFS_CS3_CONFIG:	/* 32 bits */
+	.word 0xfffecc1c
+REG_TC_EMIFF_SDRAM_CONFIG:	/* 32 bits */
+	.word 0xfffecc20
+REG_TC_EMIFF_MRS:		/* 32 bits */
+	.word 0xfffecc24
+/* MPU clock/reset/power mode control registers */
+REG_ARM_CKCTL:			/* 16 bits */
+	.word 0xfffece00
+REG_ARM_IDLECT2:		/* 16 bits */
+	.word 0xfffece08
+REG_ARM_RSTCT2:			/* 16 bits */
+	.word 0xfffece14
+REG_ARM_SYSST:			/* 16 bits */
+	.word 0xfffece18
+/* DPLL control registers */
+REG_DPLL1_CTL:			/* 16 bits */
+	.word 0xfffecf00
+/* identification code register */
+REG_IDCODE:			/* 32 bits */
+	.word 0xfffed404
+
+/* Innovator specific */
+REG_FPGA_LED_DIGIT:		/* 8 bits (not used on Innovator) */
+	.word 0x08000003
+REG_FPGA_POWER:			/* 8 bits */
+	.word 0x08000005
+REG_FPGA_AUDIO:			/* 8 bits (not used on Innovator) */
+	.word 0x0800000c
+REG_FPGA_DIP_SWITCH:		/* 8 bits (not used on Innovator) */
+	.word 0x0800000e
+
+VAL_COMP_MODE_CTRL_0:
+	.word 0x0000eaef
+VAL_FUNC_MUX_CTRL_4:
+	.word 0x00000000
+VAL_FUNC_MUX_CTRL_5:
+	.word 0x00000000
+VAL_FUNC_MUX_CTRL_6:
+	.word 0x00000001
+VAL_FUNC_MUX_CTRL_7:
+	.word 0x00000000
+VAL_FUNC_MUX_CTRL_8:
+	.word 0x10001200
+VAL_FUNC_MUX_CTRL_9:
+	.word 0x01201012
+VAL_FUNC_MUX_CTRL_A:
+	.word 0x00000248
+VAL_FUNC_MUX_CTRL_B:
+	.word 0x00000248
+VAL_FUNC_MUX_CTRL_C:
+	.word 0x09000000
+VAL_FUNC_MUX_CTRL_D:
+	.word 0x00000000
+VAL_PULL_DWN_CTRL_0:
+	.word 0x11a10000
+VAL_PULL_DWN_CTRL_1:
+	.word 0x2e047fff
+VAL_PULL_DWN_CTRL_2:
+	.word 0xffd603a6
+VAL_PULL_DWN_CTRL_3:
+	.word 0x00003e03
+VAL_VOLTAGE_CTRL_0:
+	.word 0x00000007
+VAL_TEST_DBG_CTRL_0:
+	/*  See Errata 4.13, This works around a SRAM bug, for chips below ES2.5 .
+	 *   This slows down internal SRAM accesses.
+	 */
+	.word 0x00000007
+VAL_MOD_CONF_CTRL_0:
+	.word 0x0b000008
+VAL_ARM_CKCTL:
+	.word 0x010f
+VAL_DPLL1_CTL:
+	.word 0x2710
+VAL_TC_EMIFS_CS1_CONFIG_PRELIM:
+	.word 0x00001149
+VAL_TC_EMIFS_CS2_CONFIG_PRELIM:
+	.word 0x00004158
+VAL_TC_EMIFS_CS0_CONFIG:
+	.word 0x002130b0
+VAL_TC_EMIFS_CS1_CONFIG:
+	.word 0x0000f559
+VAL_TC_EMIFS_CS2_CONFIG:
+	.word 0x000055f0
+VAL_TC_EMIFS_CS3_CONFIG:
+	.word 0x00003331
+VAL_TC_EMIFF_SDRAM_CONFIG:
+	.word 0x010290fc
+VAL_TC_EMIFF_MRS:
+	.word 0x00000027

board/omap1510inn/u-boot.lds

@@ -0,0 +1,58 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/arm925t/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+	armboot_end_data = .;
+
+	. = ALIGN(4);
+	.bss : { *(.bss) }
+
+	armboot_end = .;
+}

board/omap1610inn/Makefile

@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= omap1610innovator.o flash.o
+SOBJS	:= platform.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################

board/omap1610inn/config.mk

@@ -0,0 +1,26 @@
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+#
+# (C) Copyright 2003
+# Texas Instruments, <www.ti.com>
+# Kshitij Gupta <Kshitij@ti.com>
+#
+# TI Innovator board with OMAP1610 (ARM925EJS) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# Innovator has 1 bank of 256 MB SDRAM
+# Physical Address:
+# 1000'0000 to 2000'0000
+#
+#
+# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000
+# (mem base + reserved)
+#
+# we load ourself to 1100'0000
+#
+#
+
+
+TEXT_BASE = 0x11000000

board/omap1610inn/flash.c

@@ -0,0 +1,482 @@
+/*
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+
+#define PHYS_FLASH_SECT_SIZE	0x00020000	/* 256 KB sectors (x2) */
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+
+/* Board support for 1 or 2 flash devices */
+#undef FLASH_PORT_WIDTH32
+#define FLASH_PORT_WIDTH16
+
+#ifdef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH		ushort
+#define FLASH_PORT_WIDTHV		vu_short
+#define SWAP(x)			__swab16(x)
+#else
+#define FLASH_PORT_WIDTH		ulong
+#define FLASH_PORT_WIDTHV		vu_long
+#define SWAP(x)			__swab32(x)
+#endif
+
+#define FPW	FLASH_PORT_WIDTH
+#define FPWV	FLASH_PORT_WIDTHV
+
+#define mb() __asm__ __volatile__ ("" : : : "memory")
+
+
+
+/* Flash Organization Structure */
+typedef struct OrgDef {
+	unsigned int sector_number;
+	unsigned int sector_size;
+} OrgDef;
+
+
+/* Flash Organizations */
+OrgDef OrgIntel_28F256L18T[] = {
+	{4, 32 * 1024},				/* 4 * 32kBytes sectors */
+	{255, 128 * 1024},			/* 255 * 128kBytes sectors */
+};
+
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+unsigned long flash_init (void);
+static ulong flash_get_size (FPW * addr, flash_info_t * info);
+static int write_data (flash_info_t * info, ulong dest, FPW data);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+void inline spin_wheel (void);
+void flash_print_info (flash_info_t * info);
+void flash_unprotect_sectors (FPWV * addr);
+int flash_erase (flash_info_t * info, int s_first, int s_last);
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	int i;
+	ulong size = 0;
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		switch (i) {
+		case 0:
+			flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
+			flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
+			break;
+		default:
+			panic ("configured to many flash banks!\n");
+			break;
+		}
+		size += flash_info[i].size;
+	}
+
+	/* Protect monitor and environment sectors
+	 */
+	flash_protect (FLAG_PROTECT_SET,
+			CFG_FLASH_BASE,
+			CFG_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]);
+
+	flash_protect (FLAG_PROTECT_SET,
+			CFG_ENV_ADDR,
+			CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t * info)
+{
+	int i;
+	OrgDef *pOrgDef;
+
+	pOrgDef = OrgIntel_28F256L18T;
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			if (i > 255) {
+				info->start[i] = base + (i * 0x8000);
+				info->protect[i] = 0;
+			} else {
+				info->start[i] = base +
+						(i * PHYS_FLASH_SECT_SIZE);
+				info->protect[i] = 0;
+			}
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F256L18T:
+		printf ("FLASH 28F256L18T\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i], info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (FPW * addr, flash_info_t * info)
+{
+	volatile FPW value;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x5555] = (FPW) 0x00AA00AA;
+	addr[0x2AAA] = (FPW) 0x00550055;
+	addr[0x5555] = (FPW) 0x00900090;
+
+	mb ();
+	value = addr[0];
+
+	switch (value) {
+
+	case (FPW) INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+		return (0);		/* no or unknown flash  */
+	}
+
+	mb ();
+	value = addr[1];	/* device ID        */
+	switch (value) {
+
+	case (FPW) (INTEL_ID_28F256L18T):
+		info->flash_id += FLASH_28F256L18T;
+		info->sector_count = 259;
+		info->size = 0x02000000;
+		break;			/* => 32 MB     */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+				info->sector_count, CFG_MAX_FLASH_SECT);
+		info->sector_count = CFG_MAX_FLASH_SECT;
+	}
+
+	addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (info->size);
+}
+
+
+
+
+/* unprotects a sector for write and erase
+ * on some intel parts, this unprotects the entire chip, but it
+ * wont hurt to call this additional times per sector...
+ */
+void flash_unprotect_sectors (FPWV * addr)
+{
+#define PD_FINTEL_WSMS_READY_MASK    0x0080
+
+	*addr = (FPW) 0x00500050;	/* clear status register */
+
+	/* this sends the clear lock bit command */
+	*addr = (FPW) 0x00600060;
+	*addr = (FPW) 0x00D000D0;
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong type, start, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+				info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+				prot);
+	} else {
+		printf ("\n");
+	}
+
+
+
+
+	start = get_timer (0);
+	last = start;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			FPWV *addr = (FPWV *) (info->start[sect]);
+			FPW status;
+
+			printf ("Erasing sector %2d ... ", sect);
+
+			flash_unprotect_sectors (addr);
+
+			/* arm simple, non interrupt dependent timer */
+			reset_timer_masked ();
+
+			*addr = (FPW) 0x00500050;/* clear status register */
+			*addr = (FPW) 0x00200020;/* erase setup */
+			*addr = (FPW) 0x00D000D0;/* erase confirm */
+
+			while (((status =
+				*addr) & (FPW) 0x00800080) !=
+				(FPW) 0x00800080) {
+					if (get_timer_masked () > 
+					CFG_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					/* suspend erase     */
+					*addr = (FPW) 0x00B000B0;
+					/* reset to read mode */
+					*addr = (FPW) 0x00FF00FF;
+					rcode = 1;
+					break;
+				}
+			}
+
+			/* clear status register cmd.   */
+			*addr = (FPW) 0x00500050;
+			*addr = (FPW) 0x00FF00FF;/* resest to read mode */
+			printf (" done\n");
+		}
+	}
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	FPW data;
+	int count, i, l, rc, port_width;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+/* get lower word aligned address */
+#ifdef FLASH_PORT_WIDTH16
+	wp = (addr & ~1);
+	port_width = 2;
+#else
+	wp = (addr & ~3);
+	port_width = 4;
+#endif
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < port_width && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < port_width; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	count = 0;
+	while (cnt >= port_width) {
+		data = 0;
+		for (i = 0; i < port_width; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+		cnt -= port_width;
+		if (count++ > 0x800) {
+			spin_wheel ();
+			count = 0;
+		}
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < port_width; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_data (info, wp, SWAP (data)));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t * info, ulong dest, FPW data)
+{
+	FPWV *addr = (FPWV *) dest;
+	ulong status;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr);
+		return (2);
+	}
+	flash_unprotect_sectors (addr);
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+	*addr = (FPW) 0x00400040;	/* write setup */
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();
+
+	/* wait while polling the status register */
+	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+		if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+			return (1);
+		}
+	}
+	*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+	return (0);
+}
+
+void inline spin_wheel (void)
+{
+	static int p = 0;
+	static char w[] = "\\/-";
+
+	printf ("\010%c", w[p]);
+	(++p == 3) ? (p = 0) : 0;
+}

board/omap1610inn/omap1610innovator.c

@@ -0,0 +1,270 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#if defined(CONFIG_OMAP1610)
+#include <./configs/omap1510.h>
+#endif
+
+void flash__init (void);
+void ether__init (void);
+void set_muxconf_regs (void);
+void peripheral_power_enable (void);
+
+#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
+
+static inline void delay (unsigned long loops)
+{
+	__asm__ volatile ("1:\n"
+		"subs %0, %1, #1\n"
+		"bne 1b":"=r" (loops):"0" (loops));
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* arch number of OMAP 1510-Board */
+	/* to be changed for OMAP 1610 Board */
+	gd->bd->bi_arch_number = 234;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0x10000100;
+
+	/* Configure MUX settings */
+	set_muxconf_regs ();
+	peripheral_power_enable ();
+
+/* this speeds up your boot a quite a bit.  However to make it
+ *  work, you need make sure your kernel startup flush bug is fixed.
+ *  ... rkw ...
+ */
+	icache_enable ();
+
+	flash__init ();
+	ether__init ();
+	return 0;
+}
+
+
+int misc_init_r (void)
+{
+	/* currently empty */
+	return (0);
+}
+
+/******************************
+ Routine:
+ Description:
+******************************/
+void flash__init (void)
+{
+#define EMIFS_GlB_Config_REG 0xfffecc0c
+	unsigned int regval;
+	regval = *((volatile unsigned int *) EMIFS_GlB_Config_REG);
+	/* Turn off write protection for flash devices. */
+	regval = regval | 0x0001;
+	*((volatile unsigned int *) EMIFS_GlB_Config_REG) = regval;
+}
+/*************************************************************
+ Routine:ether__init
+ Description: take the Ethernet controller out of reset and wait
+	  		   for the EEPROM load to complete.
+*************************************************************/
+void ether__init (void)
+{
+#define ETH_CONTROL_REG 0x0400000b
+
+	*((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01;
+	udelay (3);
+}
+
+/******************************
+ Routine:
+ Description:
+******************************/
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+/******************************************************
+ Routine: set_muxconf_regs
+ Description: Setting up the configuration Mux registers
+ 			  specific to the hardware
+*******************************************************/
+void set_muxconf_regs (void)
+{
+	volatile unsigned int *MuxConfReg;
+	/* set each registers to its reset value; */
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_0);
+	/* setup for UART1 */
+	*MuxConfReg &= ~(0x02000000);	/* bit 25 */
+	/* setup for UART2 */
+	*MuxConfReg &= ~(0x01000000);	/* bit 24 */
+	/* Disable Uwire CS Hi-Z */
+	*MuxConfReg |= 0x08000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_3);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_4);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_5);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_6);
+	/*setup mux for UART3 */
+	*MuxConfReg |= 0x00000001;	/* bit3, 1, 0 (mux0 5,5,26) */
+	*MuxConfReg &= ~0x0000003e;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_7);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_8);
+	/* Disable Uwire CS Hi-Z */
+	*MuxConfReg |= 0x00001200;	/*bit 9 for CS0 12 for CS3 */
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_9);
+	/*  Need to turn on bits 21 and 12 in FUNC_MUX_CTRL_9 so the  */
+	/*  hardware will actually use TX and RTS based on bit 25 in  */
+	/*  FUNC_MUX_CTRL_0.  I told you this thing was screwy!  */
+	*MuxConfReg |= 0x00201000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_A);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_B);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_C);
+	/* setup for UART2 */
+	/*  Need to turn on bits 27 and 24 in FUNC_MUX_CTRL_C so the  */
+	/*  hardware will actually use TX and RTS based on bit 24 in  */
+	/*  FUNC_MUX_CTRL_0. */
+	*MuxConfReg |= 0x09000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_0);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_1);
+	*MuxConfReg = 0x00000000;
+	/* mux setup for SD/MMC driver */
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_2);
+	*MuxConfReg &= 0xFFFE0FFF;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_3);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0);
+	/* bit 13 for MMC2 XOR_CLK */
+	*MuxConfReg &= ~(0x00002000);
+	/* bit 29 for UART 1 */
+	*MuxConfReg &= ~(0x00002000);
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_0);
+	/* Configure for USB. Turn on VBUS_CTRL and VBUS_MODE. */
+	*MuxConfReg |= 0x000C0000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int)USB_TRANSCEIVER_CTRL);
+	*MuxConfReg &= ~(0x00000070);
+	*MuxConfReg &= ~(0x00000008);
+	*MuxConfReg |= 0x00000003;
+	*MuxConfReg |= 0x00000180;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0);
+	/* bit 17, software controls VBUS */
+	*MuxConfReg &= ~(0x00020000);
+	/* Enable USB 48 and 12M clocks */
+	*MuxConfReg |= 0x00000200;
+	*MuxConfReg &= ~(0x00000180);
+	/*2.75V for MMCSDIO1 */
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) VOLTAGE_CTRL_0);
+	*MuxConfReg = 0x00001FE7;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PU_PD_SEL_0);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PU_PD_SEL_1);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PU_PD_SEL_2);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PU_PD_SEL_3);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PU_PD_SEL_4);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_4);
+	*MuxConfReg = 0x00000000;
+	/* Turn on UART2 48 MHZ clock */
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0);
+	*MuxConfReg |= 0x40000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) USB_OTG_CTRL);
+	/* setup for USB VBus detection OMAP161x */
+	*MuxConfReg |= 0x00040000;	/* bit 18 */
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PU_PD_SEL_2);
+	/* PullUps for SD/MMC driver */
+	*MuxConfReg |= ~(0xFFFE0FFF);
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int)COMP_MODE_CTRL_0);
+	*MuxConfReg = COMP_MODE_ENABLE;
+}
+
+/******************************************************
+ Routine: peripheral_power_enable
+ Description: Enable the power for UART1
+*******************************************************/
+void peripheral_power_enable (void)
+{
+#define UART1_48MHZ_ENABLE	((unsigned short)0x0200)
+#define SW_CLOCK_REQUEST	((volatile unsigned short *)0xFFFE0834)
+
+	*SW_CLOCK_REQUEST |= UART1_48MHZ_ENABLE;
+}

board/omap1610inn/platform.S

@@ -0,0 +1,385 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+#if defined(CONFIG_OMAP1610)
+#include <./configs/omap1510.h>
+#endif
+
+
+_TEXT_BASE:
+	.word	TEXT_BASE	/* sdram load addr from config.mk */
+
+.globl platformsetup
+platformsetup:
+
+
+	/*------------------------------------------------------*
+	 * Set up ARM CLM registers (IDLECT1)                   *
+	 *------------------------------------------------------*/
+	ldr	r0,	REG_ARM_IDLECT1
+	ldr	r1,	VAL_ARM_IDLECT1
+	str	r1,	[r0]
+
+	/*------------------------------------------------------*
+	 * Set up ARM CLM registers (IDLECT2)  		        *
+	 *------------------------------------------------------*/
+	ldr	r0,	REG_ARM_IDLECT2
+	ldr	r1,	VAL_ARM_IDLECT2
+	str	r1,	[r0]
+
+	/*------------------------------------------------------*
+	 * Set up ARM CLM registers (IDLECT3)		        *
+	 *------------------------------------------------------*/
+	ldr	r0,	REG_ARM_IDLECT3
+	ldr	r1,	VAL_ARM_IDLECT3
+	str	r1,	[r0]
+
+
+	mov	r1,	#0x01		/* PER_EN bit */
+	ldr	r0,	REG_ARM_RSTCT2
+	strh	r1,	[r0]		/* CLKM; Peripheral reset. */
+
+	/* Set CLKM to Sync-Scalable	*/
+	/* I supposedly need to enable the dsp clock before switching */
+	mov	r1,	#0x0000
+	ldr	r0,	REG_ARM_SYSST
+	strh	r1,	[r0]
+	mov	r0,	#0x400
+1:
+	subs	r0,	r0,	#0x1	/* wait for any bubbles to finish */
+	bne	1b
+	ldr	r1,	VAL_ARM_CKCTL
+	ldr	r0,	REG_ARM_CKCTL
+	strh	r1,	[r0]
+
+	/* a few nops to let settle */
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+
+	/* setup DPLL 1 */
+	/* Ramp up the clock to 96Mhz */
+	ldr	r1,	VAL_DPLL1_CTL
+	ldr	r0,	REG_DPLL1_CTL
+	strh	r1,	[r0]
+	ands	r1,	r1,	#0x10	/* Check if PLL is enabled. */
+	beq	lock_end	/* Do not look for lock if BYPASS selected */
+2:
+	ldrh	r1,	[r0]
+	ands	r1,	r1,	#0x01	/*	Check the LOCK bit.*/
+	beq 2b			/*	loop until bit goes hi. */
+lock_end:
+
+
+	/*------------------------------------------------------*
+	 * Turn off the watchdog during init...			*
+ 	 *------------------------------------------------------*/
+	ldr	r0,	REG_WATCHDOG
+	ldr	r1,	WATCHDOG_VAL1
+	str	r1,	[r0]
+	ldr	r1,	WATCHDOG_VAL2
+	str	r1,	[r0]
+	ldr	r0,	REG_WSPRDOG
+	ldr	r1,	WSPRDOG_VAL1
+	str	r1,	[r0]
+	ldr	r0,	REG_WWPSDOG
+
+watch1Wait:
+	ldr	r1,	[r0]
+	tst	r1,	#0x10
+	bne	watch1Wait
+
+	ldr	r0,	REG_WSPRDOG
+	ldr	r1,	WSPRDOG_VAL2
+	str	r1,	[r0]
+	ldr	r0,	REG_WWPSDOG
+watch2Wait:
+	ldr	r1,	[r0]
+	tst	r1,	#0x10
+	bne	watch2Wait
+
+
+
+
+	/* Set memory timings corresponding to the new clock speed */
+
+	/* Check execution location to determine current execution location
+	 * and branch to appropriate initialization code.
+	 */
+	/* Load physical SDRAM base. */
+	mov 	r0, 	#0x10000000
+	/* Get current execution location. */
+	mov 	r1, 	pc
+	/* Compare. */
+	cmp 	r1, 	r0
+	/* Skip over EMIF-fast initialization if running from SDRAM. */
+	bge 	skip_sdram
+
+	/*
+	* Delay for SDRAM initialization.
+	*/
+	mov	r3,	#0x1800		/* value should be checked */
+3:
+	subs	r3,	r3,	#0x1	/* Decrement count */
+	bne 	3b
+
+
+	/*
+	 * Set SDRAM control values. Disable refresh before MRS command.
+	 */
+
+	/* mobile ddr operation */
+	ldr	r0,	REG_SDRAM_OPERATION
+	mov	r2,	#07
+	str	r2,	[r0]
+
+	/* config register */
+	ldr	r0,	REG_SDRAM_CONFIG
+	ldr	r1,	SDRAM_CONFIG_VAL
+	str	r1,	[r0]
+
+	/* manual command register */
+	ldr	r0,	REG_SDRAM_MANUAL_CMD
+	/* issue set cke high */
+	mov	r1,	#CMD_SDRAM_CKE_SET_HIGH
+	str	r1,	[r0]
+	/* issue nop */
+	mov	r1,	#CMD_SDRAM_NOP
+	str	r1,	[r0]
+
+	mov	r2,	#0x0100
+waitMDDR1:
+	subs	r2,	r2,	 #1
+	bne	waitMDDR1	/* delay loop */
+
+	/* issue precharge */
+	mov	r1,	#CMD_SDRAM_PRECHARGE
+	str	r1,	[r0]
+
+	/* issue autorefresh x 2 */
+	mov	r1,	#CMD_SDRAM_AUTOREFRESH
+	str	r1,	[r0]
+	str	r1,	[r0]
+
+	/* mrs register ddr mobile */
+	ldr	r0,	REG_SDRAM_MRS
+	mov	r1,	#0x33
+	str	r1,	[r0]
+
+	/* emrs1 low-power register */
+	ldr	r0,	REG_SDRAM_EMRS1
+	/* self refresh on all banks */
+	mov	r1,	#0
+	str	r1,	[r0]
+
+	ldr	r0,	REG_DLL_URD_CONTROL
+	ldr	r1,	DLL_URD_CONTROL_VAL
+	str	r1,	[r0]
+
+	ldr	r0,	REG_DLL_LRD_CONTROL
+	ldr	r1,	DLL_LRD_CONTROL_VAL
+	str	r1,	[r0]
+
+	ldr	r0,	REG_DLL_WRT_CONTROL
+	ldr	r1,	DLL_WRT_CONTROL_VAL
+	str	r1,	[r0]
+
+	/* delay loop */
+	mov	r2,	#0x0100
+waitMDDR2:
+	subs	r2,	r2,	#1
+	bne	waitMDDR2
+
+	/*
+	 * Delay for SDRAM initialization.
+	 */
+	mov	r3,	#0x1800
+4:
+	subs	r3,	r3,	#1	/* Decrement count. */
+	bne	4b
+	b	common_tc
+
+skip_sdram:
+
+	ldr	r0,	REG_SDRAM_CONFIG
+	ldr	r1,	SDRAM_CONFIG_VAL
+	str	r1,	[r0]
+
+common_tc:
+	/* slow interface */
+	ldr	r1,	VAL_TC_EMIFS_CS0_CONFIG
+	ldr	r0,	REG_TC_EMIFS_CS0_CONFIG
+	str	r1,	[r0] /* Chip Select 0 */
+
+	ldr	r1,	VAL_TC_EMIFS_CS1_CONFIG
+	ldr	r0,	REG_TC_EMIFS_CS1_CONFIG
+	str	r1,	[r0] /* Chip Select 1 */
+	ldr	r1,	VAL_TC_EMIFS_CS3_CONFIG
+	ldr	r0,	REG_TC_EMIFS_CS3_CONFIG
+	str	r1,	[r0] /* Chip Select 3 */
+	/* back to arch calling code */
+	mov	pc,	lr
+
+	/* the literal pools origin */
+	.ltorg
+
+
+REG_TC_EMIFS_CONFIG:		/* 32 bits */
+	.word 0xfffecc0c
+REG_TC_EMIFS_CS0_CONFIG:	/* 32 bits */
+	.word 0xfffecc10
+REG_TC_EMIFS_CS1_CONFIG:	/* 32 bits */
+	.word 0xfffecc14
+REG_TC_EMIFS_CS2_CONFIG:	/* 32 bits */
+	.word 0xfffecc18
+REG_TC_EMIFS_CS3_CONFIG:	/* 32 bits */
+	.word 0xfffecc1c
+
+/* MPU clock/reset/power mode control registers */
+REG_ARM_CKCTL:			/* 16 bits */
+	.word 0xfffece00
+
+REG_ARM_IDLECT3:		/* 16 bits */
+	.word 0xfffece24
+REG_ARM_IDLECT2:		/* 16 bits */
+	.word 0xfffece08        
+REG_ARM_IDLECT1:		/* 16 bits */
+	.word 0xfffece04
+
+REG_ARM_RSTCT2:			/* 16 bits */
+	.word 0xfffece14
+REG_ARM_SYSST:			/* 16 bits */
+	.word 0xfffece18
+/* DPLL control registers */
+REG_DPLL1_CTL:			/* 16 bits */
+	.word 0xfffecf00
+
+/* Watch Dog register */
+/* secure watchdog stop */
+REG_WSPRDOG:
+	.word 0xfffeb048
+/* watchdog write pending */
+REG_WWPSDOG:
+	.word 0xfffeb034 
+
+WSPRDOG_VAL1:
+	.word 0x0000aaaa
+WSPRDOG_VAL2:
+	.word 0x00005555
+
+/* SDRAM config is: auto refresh enabled, 16 bit 4 bank,
+ counter @8192 rows, 10 ns, 8 burst */
+REG_SDRAM_CONFIG:
+	.word 0xfffecc20
+
+/* Operation register */
+REG_SDRAM_OPERATION:
+	.word 0xfffecc80
+
+/* Manual command register */
+REG_SDRAM_MANUAL_CMD:
+	.word 0xfffecc84
+
+/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
+REG_SDRAM_MRS:
+	.word 0xfffecc70
+
+/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
+REG_SDRAM_EMRS1:
+	.word 0xfffecc78
+
+/* WRT DLL register */
+REG_DLL_WRT_CONTROL:
+	.word 0xfffecc68
+DLL_WRT_CONTROL_VAL:
+	.word 0x03f00002
+
+/* URD DLL register */
+REG_DLL_URD_CONTROL:
+	.word 0xfffeccc0
+DLL_URD_CONTROL_VAL:
+	.word 0x00800002
+
+/* LRD DLL register */
+REG_DLL_LRD_CONTROL:
+	.word 0xfffecccc
+
+REG_WATCHDOG:
+	.word 0xfffec808
+
+/* 96 MHz Samsung Mobile DDR */
+SDRAM_CONFIG_VAL:
+	.word 0x001200f4 
+
+DLL_LRD_CONTROL_VAL:
+	.word 0x00800002
+
+VAL_ARM_CKCTL:
+	.word 0x3000
+VAL_DPLL1_CTL:
+	.word 0x2830
+
+VAL_TC_EMIFS_CS0_CONFIG:
+	.word 0x002130b0
+VAL_TC_EMIFS_CS1_CONFIG:
+	.word 0x00001131
+VAL_TC_EMIFS_CS2_CONFIG:
+	.word 0x000055f0
+VAL_TC_EMIFS_CS3_CONFIG:
+	.word 0x88011131
+VAL_TC_EMIFF_SDRAM_CONFIG:
+	.word 0x010290fc
+VAL_TC_EMIFF_MRS:
+	.word 0x00000027
+
+VAL_ARM_IDLECT1:
+	.word 0x00000400
+
+VAL_ARM_IDLECT2:
+	.word 0x00000886
+VAL_ARM_IDLECT3:
+	.word 0x00000015
+
+WATCHDOG_VAL1:
+	.word 0x000000f5
+WATCHDOG_VAL2:
+	.word 0x000000a0
+
+/* command values */
+.equ CMD_SDRAM_NOP,		0x00000000
+.equ CMD_SDRAM_PRECHARGE,	0x00000001
+.equ CMD_SDRAM_AUTOREFRESH,	0x00000002
+.equ CMD_SDRAM_CKE_SET_HIGH,	0x00000007

board/omap1610inn/u-boot.lds

@@ -0,0 +1,51 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+	. = ALIGN(4);
+	.text	:
+	{
+	  cpu/arm926ejs/start.o	(.text)
+	  *(.text)
+	}
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+	. = ALIGN(4);
+	.data : { *(.data) }
+	. = ALIGN(4);
+	.got : { *(.got) }
+	
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+	
+	armboot_end_data = .;
+	. = ALIGN(4);
+	.bss : { *(.bss) }
+	armboot_end = .;
+}

board/pcippc2/pcippc2.c

@@ -112,7 +112,7 @@ void after_reloc (ulong dest_addr)
 
 	/* Jump to the main U-Boot board init code
 	 */
-	board_init_r (gd, dest_addr);
+	board_init_r ((gd_t *)gd, dest_addr);
 }
 
 int misc_init_r (void)

board/r360mpi/r360mpi.c

@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2001
+ * (C) Copyright 2001-2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -37,9 +37,9 @@
 /*
  *  Memory Controller Using
  *
- *  CS0 - Flash memory            (0x40000000)
- *  CS1 - SDRAM                   (0x00000000}
- *  CS2 -
+ *  CS0 - Flash memory		(0x40000000)
+ *  CS1 - FLASH memory		(0x????????)
+ *  CS2 - SDRAM			(0x00000000)
  *  CS3 -
  *  CS4 -
  *  CS5 -
@@ -148,7 +148,7 @@ long int initdram (int board_type)
 	udelay (1000);
 
 	/*
-	 * Check Bank 0 Memory Size for re-configuration
+	 * Check Bank 2 Memory Size for re-configuration
 	 *
 	 * try 8 column mode
 	 */
@@ -205,7 +205,7 @@ long int initdram (int board_type)
 	memctl->memc_br3 = CFG_BR3_CAN;
 
 	/* Initialize MBMR */
-	memctl->memc_mbmr = MAMR_GPL_B4DIS;	/* GPL_B4 works as UPWAITB */
+	memctl->memc_mbmr = MBMR_GPL_B4DIS;	/* GPL_B4 works as UPWAITB */
 
 	/* Initialize UPMB for CAN: single read */
 	memctl->memc_mdr = 0xFFFFC004;

board/rmu/rmu.c

@@ -96,7 +96,7 @@ long int initdram (int board_type)
 {
     volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
     volatile memctl8xx_t *memctl = &immap->im_memctl;
-    long int size10 ;
+    long int size9 ;
 
     upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
 
@@ -109,7 +109,7 @@ long int initdram (int board_type)
     memctl->memc_or1 = CFG_OR1_PRELIM;
     memctl->memc_br1 = CFG_BR1_PRELIM;
 
-    memctl->memc_mamr = CFG_MAMR_10COL & (~(MAMR_PTAE)); /* no refresh yet */
+    memctl->memc_mamr = CFG_MAMR_9COL & (~(MAMR_PTAE)); /* no refresh yet */
 
     udelay(200);
 
@@ -122,13 +122,20 @@ long int initdram (int board_type)
 
     udelay (1000);
 
-	/* Check Bank 0 Memory Size
-	 * try 10 column mode
+	/* Check Bank 0 Memory Size,
+	 * 9 column mode
 	 */
 
-	size10 = dram_size (CFG_MAMR_10COL, (ulong *)SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE) ;
+	size9 = dram_size (CFG_MAMR_9COL, (ulong *)SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE) ;
 
-    return (size10);
+	/*
+	 * Final mapping:
+	 */
+
+	memctl->memc_or1 = ((-size9) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
+	udelay (1000);
+
+    return (size9);
 }
 
 /* ------------------------------------------------------------------------- */

board/sacsng/sacsng.c

@@ -816,3 +816,15 @@ int spi_chipsel_cnt = sizeof(spi_chipsel) / sizeof(spi_chipsel[0]);
 #endif /* CFG_CMD_SPI */
 
 #endif /* CONFIG_MISC_INIT_R */
+
+#ifdef CONFIG_POST
+/*
+ * Returns 1 if keys pressed to start the power-on long-running tests
+ * Called from board_init_f().
+ */
+int post_hotkeys_pressed(void)
+{
+	return 0;	/* No hotkeys supported */
+}
+
+#endif

board/sc520_cdp/Makefile

@@ -29,7 +29,7 @@ OBJS	:= sc520_cdp.o flash.o
 SOBJS	:= sc520_cdp_asm.o sc520_cdp_asm16.o
 
 $(LIB):	$(OBJS) $(SOBJS)
-	$(AR) crv $@ $(OBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
 
 clean:
 	rm -f $(SOBJS) $(OBJS)

board/sc520_cdp/flash.c

@@ -325,7 +325,7 @@ void flash_print_info(flash_info_t *info)
 	}
 	printf ("\n");
 
-	done:
+done:	;
 }
 
 /*-----------------------------------------------------------------------

board/sc520_cdp/sc520_cdp.c

@@ -28,7 +28,7 @@
 #include <asm/pci.h>
 #include <asm/ic/sc520.h>
 #include <asm/ic/ali512x.h>
-#include <ssi.h>
+#include <spi.h>
 
 #undef SC520_CDP_DEBUG
 
@@ -557,6 +557,19 @@ void ssi_chip_select(int dev)
 	}
 }
 
+void spi_eeprom_probe(int x)
+{
+}
+
+int spi_eeprom_read(int x, int offset, char *buffer, int len)
+{
+       return 0;
+}
+
+int spi_eeprom_write(int x, int offset, char *buffer, int len)
+{
+       return 0;
+}
 
 void spi_init_f(void)
 {
@@ -585,6 +598,9 @@ ssize_t spi_read(uchar *addr, int alen, uchar *buffer, int len)
 #endif
 #ifdef CONFIG_SC520_CDP_USE_MW
 	res = mw_eeprom_read(2, offset, buffer, len);
+#endif
+#if !defined(CONFIG_SC520_CDP_USE_SPI) && !defined(CONFIG_SC520_CDP_USE_MW)
+	res = 0;
 #endif
 	return res;
 }
@@ -606,6 +622,9 @@ ssize_t spi_write(uchar *addr, int alen, uchar *buffer, int len)
 #endif
 #ifdef CONFIG_SC520_CDP_USE_MW
 	res = mw_eeprom_write(2, offset, buffer, len);
+#endif
+#if !defined(CONFIG_SC520_CDP_USE_SPI) && !defined(CONFIG_SC520_CDP_USE_MW)
+	res = 0;
 #endif
 	return res;
 }

board/sc520_cdp/u-boot.lds

@@ -31,7 +31,7 @@ SECTIONS
 	.text  : { *(.text); }
 
 	. = ALIGN(4);
-	.rodata : { *(.rodata) }
+	.rodata : { *(.rodata) *(.rodata.str1.1) *(.rodata.str1.32) }
 
 	. = 0x400000; 	                    /* Ram data segment to use */
 	_i386boot_romdata_dest = ABSOLUTE(.);

board/siemens/CCM/ccm.c

@@ -267,7 +267,7 @@ void can_driver_enable (void)
     volatile memctl8xx_t *memctl = &immap->im_memctl;
 
     /* Initialize MBMR */
-    memctl->memc_mbmr = MAMR_GPL_B4DIS;	/* GPL_B4 ouput line Disable */
+    memctl->memc_mbmr = MBMR_GPL_B4DIS;	/* GPL_B4 ouput line Disable */
 
     /* Initialize UPMB for CAN: single read */
     memctl->memc_mdr = 0xFFFFC004;

board/siemens/pcu_e/pcu_e.c

@@ -217,9 +217,9 @@ initdram (int board_type)
 #endif	/* XXX */
 
     reg  =  memctl->memc_mamr;
-    reg &= ~MAMR_TLFB_MSK;		/* switch timer loop ... */
-    reg |=  MAMR_TLFB_4X;		/* ... to 4x */
-    reg |=  MAMR_PTBE;			/* enable refresh */
+    reg &= ~MAMR_TLFA_MSK;		/* switch timer loop ... */
+    reg |=  MAMR_TLFA_4X;		/* ... to 4x */
+    reg |=  MAMR_PTAE;			/* enable refresh */
     memctl->memc_mamr = reg;
 
     udelay(200);
@@ -246,7 +246,7 @@ initdram (int board_type)
     size_b0 = dram_size (CFG_MAMR, (ulong *)SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
 #endif	/* XXX */
 
-    memctl->memc_mamr = CFG_MAMR | MAMR_PTBE;
+    memctl->memc_mamr = CFG_MAMR | MAMR_PTAE;
 
     /*
      * Final mapping:

board/sl8245/u-boot.lds

@@ -129,4 +129,3 @@ SECTIONS
   _end = . ;
   PROVIDE (end = .);
 }
-

board/spd8xx/spd8xx.c

@@ -200,14 +200,14 @@ initdram (int board_type)
     udelay(1);
     memctl->memc_mcr = 0x80806106;
 
-    memctl->memc_mbmr |= MAMR_PTBE;	/* refresh enabled */
+    memctl->memc_mbmr |= MBMR_PTBE;	/* refresh enabled */
 
     /*
      * Check Bank 0 Memory Size for re-configuration
      */
     size_b0 = dram_size (CFG_MBMR_8COL, (ulong *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
 
-    memctl->memc_mbmr = CFG_MBMR_8COL | MAMR_PTBE;
+    memctl->memc_mbmr = CFG_MBMR_8COL | MBMR_PTBE;
 
     return (size_b0);
 }

board/tqm8xx/Makefile

@@ -1,5 +1,5 @@
 #
-# (C) Copyright 2000
+# (C) Copyright 2000-2003
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # See file CREDITS for list of people who contributed to this

board/tqm8xx/flash.c

@@ -116,14 +116,15 @@ unsigned long flash_init (void)
 
 #ifdef	CFG_ENV_IS_IN_FLASH
 	/* ENV protection ON by default */
-	debug ("Protect %senvironment: %08lx ... %08lx\n",
 # ifdef CFG_ENV_ADDR_REDUND
-		"primary   ",
-# else
-		"",
-# endif
+	debug ("Protect primary   environment: %08lx ... %08lx\n",
 		(ulong)CFG_ENV_ADDR,
 		(ulong)CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1);
+# else
+	debug ("Protect environment: %08lx ... %08lx\n",
+		(ulong)CFG_ENV_ADDR,
+		(ulong)CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1);
+# endif
 
 	flash_protect(FLAG_PROTECT_SET,
 		      CFG_ENV_ADDR,
@@ -305,7 +306,7 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 			info->sector_count = 64;
 			info->size = 0x00800000; /* => 8 MB */
 			break;
-		} 
+		}
 		switch(addr[14]) {
 		case AMD_ID_LV128U_2:
 			if (addr[15] != AMD_ID_LV128U_3) {

board/tqm8xx/tqm8xx.c

@@ -363,7 +363,13 @@ long int initdram (int board_type)
 	memctl->memc_mcr = 0x011C | UPMB;
 #endif							/* CONFIG_CAN_DRIVER */
 
-
+#ifdef	CONFIG_ISP1362_USB
+	/* Initialize OR5 / BR5 */
+	memctl->memc_or5 = CFG_OR5_ISP1362;
+	memctl->memc_br5 = CFG_BR5_ISP1362;
+#endif							/* CONFIG_ISP1362_USB */
+	    
+	    
 	return (size_b0 + size_b1);
 }
 

board/trab/trab.c

@@ -130,6 +130,11 @@ int board_init ()
 	}
 #endif	/* CONFIG_MODEM_SUPPORT */
 
+#ifdef CONFIG_DRIVER_S3C24X0_I2C
+	/* Configure I/O ports PG5 und PG6 for I2C */
+ 	gpio->PGCON = (gpio->PGCON & 0x003c00) | 0x003c00;
+#endif /* CONFIG_DRIVER_S3C24X0_I2C */
+
 	return 0;
 }
 

board/v37/v37.c

@@ -140,7 +140,7 @@ long int initdram (int board_type)
     memctl->memc_br3 = CFG_BR3_CAN;
 
     /* Initialize MBMR */
-    memctl->memc_mamr = MAMR_GPL_B4DIS;	/* GPL_B4 ouput line Disable */
+    memctl->memc_mamr = MAMR_GPL_A4DIS;	/* GPL_A4 ouput line Disable */
 
     /* Initialize UPMB for CAN: single read */
     memctl->memc_mdr = 0xFFFFC004;

common/Makefile

@@ -42,9 +42,9 @@ COBJS	= main.o altera.o bedbug.o \
 	  cmd_reginfo.o cmd_scsi.o cmd_spi.o cmd_usb.o cmd_vfd.o \
 	  command.o console.o devices.o dlmalloc.o docecc.o \
 	  environment.o env_common.o \
-	  env_flash.o env_eeprom.o env_nvram.o env_nowhere.o \
+	  env_flash.o env_eeprom.o env_nvram.o env_nowhere.o exports.o \
 	  flash.o fpga.o \
-	  hush.o kgdb.o lists.o miiphybb.o miiphyutil.o \
+	  hush.o kgdb.o lists.o lynxkdi.o miiphybb.o miiphyutil.o \
 	  s_record.o soft_i2c.o soft_spi.o spartan2.o \
 	  usb.o usb_kbd.o usb_storage.o \
 	  virtex2.o xilinx.o

common/cmd_bdinfo.c

@@ -178,4 +178,3 @@ U_BOOT_CMD(
 	NULL
 );
 #endif	/* CFG_CMD_BDI */
-

common/cmd_boot.c

@@ -27,13 +27,15 @@
 #include <common.h>
 #include <command.h>
 #include <net.h>
-#include <syscall.h>
 
 
 /* -------------------------------------------------------------------- */
 
 int do_go (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
+#if defined(CONFIG_I386)
+	DECLARE_GLOBAL_DATA_PTR;
+#endif
 	ulong	addr, rc;
 	int     rcode = 0;
 
@@ -50,6 +52,13 @@ int do_go (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	 * pass address parameter as argv[0] (aka command name),
 	 * and all remaining args
 	 */
+#if defined(CONFIG_I386)
+	/*
+	 * x86 does not use a dedicated register to pass the pointer
+	 * to the global_data
+	 */
+	argv[0] = (char *)gd;
+#endif
 	rc = ((ulong (*)(int, char *[]))addr) (--argc, &argv[1]);
 	if (rc != 0) rcode = 1;
 

common/cmd_bootm.c

@@ -30,6 +30,7 @@
 #include <image.h>
 #include <malloc.h>
 #include <zlib.h>
+#include <bzlib.h>
 #include <environment.h>
 #include <asm/byteorder.h>
 
@@ -80,6 +81,13 @@ static void zfree(void *, void *, unsigned);
 #if (CONFIG_COMMANDS & CFG_CMD_IMI)
 static int image_info (unsigned long addr);
 #endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_IMLS)
+#include <flash.h>
+extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+static int do_imls (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+#endif
+
 static void print_type (image_header_t *hdr);
 
 #ifdef __I386__
@@ -120,6 +128,10 @@ int do_bootelf (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] );
 #if defined(CONFIG_ARTOS) && defined(CONFIG_PPC)
 static boot_os_Fcn do_bootm_artos;
 #endif
+#ifdef CONFIG_LYNXKDI
+static boot_os_Fcn do_bootm_lynxkdi;
+extern void lynxkdi_boot( image_header_t * );
+#endif
 
 image_header_t header;
 
@@ -131,6 +143,7 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	ulong	addr;
 	ulong	data, len, checksum;
 	ulong  *len_ptr;
+	uint	unc_len = 0x400000;
 	int	i, verify;
 	char	*name, *s;
 	int	(*appl)(cmd_tbl_t *, int, int, char *[]);
@@ -296,13 +309,26 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 		break;
 	case IH_COMP_GZIP:
 		printf ("   Uncompressing %s ... ", name);
-		if (gunzip ((void *)ntohl(hdr->ih_load), 0x400000,
+		if (gunzip ((void *)ntohl(hdr->ih_load), unc_len,
 			    (uchar *)data, (int *)&len) != 0) {
 			printf ("GUNZIP ERROR - must RESET board to recover\n");
 			SHOW_BOOT_PROGRESS (-6);
 			do_reset (cmdtp, flag, argc, argv);
 		}
 		break;
+#ifdef CONFIG_BZIP2
+	case IH_COMP_BZIP2:
+		printf ("   Uncompressing %s ... ", name);
+		i = BZ2_bzBuffToBuffDecompress ((char*)ntohl(hdr->ih_load),
+						&unc_len, (char *)data, len, 0, 0);
+		if (i != BZ_OK) {
+			printf ("BUNZIP2 ERROR %d - must RESET board to recover\n", i);
+			SHOW_BOOT_PROGRESS (-6);
+			udelay(100000);
+			do_reset (cmdtp, flag, argc, argv);
+		}
+		break;
+#endif /* CONFIG_BZIP2 */
 	default:
 		if (iflag)
 			enable_interrupts();
@@ -350,6 +376,13 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 			     addr, len_ptr, verify);
 	    break;
 
+#ifdef CONFIG_LYNXKDI
+	case IH_OS_LYNXOS:
+	    do_bootm_lynxkdi (cmdtp, flag, argc, argv,
+			     addr, len_ptr, verify);
+	    break;
+#endif
+
 	case IH_OS_RTEMS:
 	    do_bootm_rtems (cmdtp, flag, argc, argv,
 			     addr, len_ptr, verify);
@@ -481,6 +514,10 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
 		kbd->bi_sccfreq /= 1000000L;
 		kbd->bi_vco     /= 1000000L;
 #endif /* CONFIG_8260 */
+#if defined(CONFIG_MPC5XXXX)
+		kbd->bi_ipbfreq /= 1000000L;
+		kbd->bi_pcifreq /= 1000000L;
+#endif /* CONFIG_MPC5XXXX */
 	}
 
 	kernel = (void (*)(bd_t *, ulong, ulong, ulong, ulong))hdr->ih_ep;
@@ -957,6 +994,56 @@ U_BOOT_CMD(
 
 #endif	/* CFG_CMD_IMI */
 
+#if (CONFIG_COMMANDS & CFG_CMD_IMLS)
+/*-----------------------------------------------------------------------
+ * List all images found in flash.
+ */
+int do_imls (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	flash_info_t *info;
+	int i, j;
+	image_header_t *hdr;
+	ulong checksum;
+
+	for (i=0, info=&flash_info[0]; i<CFG_MAX_FLASH_BANKS; ++i, ++info) {
+		if (info->flash_id == FLASH_UNKNOWN)
+			goto next_bank;
+		for (j=0; j<CFG_MAX_FLASH_SECT; ++j) {
+
+			if (!(hdr=(image_header_t *)info->start[j]) ||
+			    (ntohl(hdr->ih_magic) != IH_MAGIC))
+				goto next_sector;
+
+			/* Copy header so we can blank CRC field for re-calculation */
+			memmove (&header, (char *)hdr, sizeof(image_header_t));
+
+			checksum = ntohl(header.ih_hcrc);
+			header.ih_hcrc = 0;
+
+			if (crc32 (0, (char *)&header, sizeof(image_header_t))
+			    != checksum)
+				goto next_sector;
+
+			printf ("Image at %08lX:\n", (ulong)hdr);
+			print_image_hdr( hdr );
+			putc ('\n');
+next_sector:		;
+		}
+next_bank:	;
+	}
+
+	return (0);
+}
+
+U_BOOT_CMD(
+	imls,	1,		1,	do_imls,
+	"imls    - list all images found in flash\n",
+	"\n"
+	"    - Prints information about all images found at sector\n"
+	"      boundaries in flash.\n"
+);
+#endif	/* CFG_CMD_IMLS */
+
 void
 print_image_hdr (image_header_t *hdr)
 {
@@ -1007,6 +1094,9 @@ print_type (image_header_t *hdr)
 	case IH_OS_RTEMS:	os = "RTEMS";			break;
 #ifdef CONFIG_ARTOS
 	case IH_OS_ARTOS:	os = "ARTOS";			break;
+#endif
+#ifdef CONFIG_LYNXKDI
+	case IH_OS_LYNXOS:	os = "LynxOS";			break;
 #endif
 	default:		os = "Unknown OS";		break;
 	}
@@ -1024,6 +1114,7 @@ print_type (image_header_t *hdr)
 	case IH_CPU_SH:		arch = "SuperH";		break;
 	case IH_CPU_SPARC:	arch = "SPARC";			break;
 	case IH_CPU_SPARC64:	arch = "SPARC 64 Bit";		break;
+	case IH_CPU_M68K:	arch = "M68K"; 			break;
 	default:		arch = "Unknown Architecture";	break;
 	}
 
@@ -1130,6 +1221,13 @@ int gunzip(void *dst, int dstlen, unsigned char *src, int *lenp)
 	return (0);
 }
 
+#ifdef CONFIG_BZIP2
+void bz_internal_error(int errcode)
+{
+	printf ("BZIP2 internal error %d\n", errcode);
+}
+#endif /* CONFIG_BZIP2 */
+
 static void
 do_bootm_rtems (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[],
 		ulong addr, ulong *len_ptr, int verify)
@@ -1180,3 +1278,17 @@ do_bootm_qnxelf (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[],
 	do_bootelf(cmdtp, 0, 2, local_args);
 }
 #endif /* CFG_CMD_ELF */
+
+#ifdef CONFIG_LYNXKDI
+static void
+do_bootm_lynxkdi (cmd_tbl_t *cmdtp, int flag,
+		 int	argc, char *argv[],
+		 ulong	addr,
+		 ulong	*len_ptr,
+		 int	verify)
+{
+	lynxkdi_boot( &header );
+}
+
+#endif /* CONFIG_LYNXKDI */
+

common/cmd_flash.c

@@ -56,45 +56,120 @@ extern flash_info_t flash_info[];	/* info for FLASH chips */
  *			  or an invalid flash bank.
  */
 static int
-abbrev_spec(char *str, flash_info_t **pinfo, int *psf, int *psl)
+abbrev_spec (char *str, flash_info_t ** pinfo, int *psf, int *psl)
 {
-    flash_info_t *fp;
-    int bank, first, last;
-    char *p, *ep;
+	flash_info_t *fp;
+	int bank, first, last;
+	char *p, *ep;
 
-    if ((p = strchr(str, ':')) == NULL)
-	return 0;
-    *p++ = '\0';
-
-    bank = simple_strtoul(str, &ep, 10);
-    if (ep == str || *ep != '\0' ||
-      bank < 1 || bank > CFG_MAX_FLASH_BANKS ||
-      (fp = &flash_info[bank - 1])->flash_id == FLASH_UNKNOWN)
-	return -1;
-
-    str = p;
-    if ((p = strchr(str, '-')) != NULL)
+	if ((p = strchr (str, ':')) == NULL)
+		return 0;
 	*p++ = '\0';
 
-    first = simple_strtoul(str, &ep, 10);
-    if (ep == str || *ep != '\0' || first >= fp->sector_count)
-	return -1;
+	bank = simple_strtoul (str, &ep, 10);
+	if (ep == str || *ep != '\0' ||
+		bank < 1 || bank > CFG_MAX_FLASH_BANKS ||
+		(fp = &flash_info[bank - 1])->flash_id == FLASH_UNKNOWN)
+		return -1;
 
-    if (p != NULL) {
-	last = simple_strtoul(p, &ep, 10);
-	if (ep == p || *ep != '\0' ||
-	  last < first || last >= fp->sector_count)
-	    return -1;
-    }
-    else
-	last = first;
+	str = p;
+	if ((p = strchr (str, '-')) != NULL)
+		*p++ = '\0';
 
-    *pinfo = fp;
-    *psf = first;
-    *psl = last;
+	first = simple_strtoul (str, &ep, 10);
+	if (ep == str || *ep != '\0' || first >= fp->sector_count)
+		return -1;
 
-    return 1;
+	if (p != NULL) {
+		last = simple_strtoul (p, &ep, 10);
+		if (ep == p || *ep != '\0' ||
+			last < first || last >= fp->sector_count)
+			return -1;
+	} else {
+		last = first;
+	}
+
+	*pinfo = fp;
+	*psf = first;
+	*psl = last;
+
+	return 1;
 }
+
+static int
+flash_fill_sect_ranges (ulong addr_first, ulong addr_last,
+			int *s_first, int *s_last,
+			int *s_count )
+{
+	flash_info_t *info;
+	ulong bank;
+	int rcode = 0;
+
+	*s_count = 0;
+
+	for (bank=0; bank < CFG_MAX_FLASH_BANKS; ++bank) {
+		s_first[bank] = -1;	/* first sector to erase	*/
+		s_last [bank] = -1;	/* last  sector to erase	*/
+	}
+
+	for (bank=0,info=&flash_info[0];
+	     (bank < CFG_MAX_FLASH_BANKS) && (addr_first <= addr_last);
+	     ++bank, ++info) {
+		ulong b_end;
+		int sect;
+		short s_end;
+
+		if (info->flash_id == FLASH_UNKNOWN) {
+			continue;
+		}
+
+		b_end = info->start[0] + info->size - 1;	/* bank end addr */
+		s_end = info->sector_count - 1;			/* last sector   */
+
+
+		for (sect=0; sect < info->sector_count; ++sect) {
+			ulong end;	/* last address in current sect	*/
+
+			end = (sect == s_end) ? b_end : info->start[sect + 1] - 1;
+
+			if (addr_first > end)
+				continue;
+			if (addr_last < info->start[sect])
+				continue;
+
+			if (addr_first == info->start[sect]) {
+				s_first[bank] = sect;
+			}
+			if (addr_last  == end) {
+				s_last[bank]  = sect;
+			}
+		}
+		if (s_first[bank] >= 0) {
+			if (s_last[bank] < 0) {
+				if (addr_last > b_end) {
+					s_last[bank] = s_end;
+				} else {
+					printf ("Error: end address"
+						" not on sector boundary\n");
+					rcode = 1;
+					break;
+				}
+			}
+			if (s_last[bank] < s_first[bank]) {
+				printf ("Error: end sector"
+					" precedes start sector\n");
+				rcode = 1;
+				break;
+			}
+			sect = s_last[bank];
+			addr_first = (sect == s_end) ? b_end + 1: info->start[sect + 1];
+			(*s_count) += s_last[bank] - s_first[bank] + 1;
+		}
+	}
+
+	return rcode;
+}
+
 int do_flinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
 	ulong bank;
@@ -180,7 +255,6 @@ int do_flerase (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 		return 1;
 	}
 
-	printf ("Erase Flash from 0x%08lx to 0x%08lx ", addr_first, addr_last);
 	rcode = flash_sect_erase(addr_first, addr_last);
 	return rcode;
 }
@@ -189,53 +263,32 @@ int flash_sect_erase (ulong addr_first, ulong addr_last)
 {
 	flash_info_t *info;
 	ulong bank;
-	int s_first, s_last;
-	int erased;
+	int s_first[CFG_MAX_FLASH_BANKS], s_last[CFG_MAX_FLASH_BANKS];
+	int erased = 0;
+	int planned;
 	int rcode = 0;
 
-	erased = 0;
+	rcode = flash_fill_sect_ranges (addr_first, addr_last,
+					s_first, s_last, &planned );
 
-	for (bank=0,info=&flash_info[0]; bank < CFG_MAX_FLASH_BANKS; ++bank, ++info) {
-		ulong b_end;
-		int sect;
-
-		if (info->flash_id == FLASH_UNKNOWN) {
-			continue;
-		}
-
-		b_end = info->start[0] + info->size - 1; /* bank end addr */
-
-		s_first = -1;		/* first sector to erase	*/
-		s_last  = -1;		/* last  sector to erase	*/
-
-		for (sect=0; sect < info->sector_count; ++sect) {
-			ulong end;		/* last address in current sect	*/
-			short s_end;
-
-			s_end = info->sector_count - 1;
-
-			end = (sect == s_end) ? b_end : info->start[sect + 1] - 1;
-
-			if (addr_first > end)
-				continue;
-			if (addr_last < info->start[sect])
-				continue;
-
-			if (addr_first == info->start[sect]) {
-				s_first = sect;
-			}
-			if (addr_last  == end) {
-				s_last  = sect;
+	if (planned && (rcode == 0)) {
+		for (bank=0,info=&flash_info[0];
+		     (bank < CFG_MAX_FLASH_BANKS) && (rcode == 0);
+		     ++bank, ++info) {
+			if (s_first[bank]>=0) {
+				erased += s_last[bank] - s_first[bank] + 1;
+				debug ("Erase Flash from 0x%08lx to 0x%08lx "
+					"in Bank # %ld ",
+					info->start[s_first[bank]],
+					(s_last[bank] == info->sector_count) ?
+						info->start[0] + info->size - 1:
+						info->start[s_last[bank]+1] - 1,
+					bank+1);
+				rcode = flash_erase (info, s_first[bank], s_last[bank]);
 			}
 		}
-		if (s_first>=0 && s_first<=s_last) {
-			erased += s_last - s_first + 1;
-			rcode = flash_erase (info, s_first, s_last);
-		}
-	}
-	if (erased) {
 		printf ("Erased %d sectors\n", erased);
-	} else {
+	} else if (rcode == 0) {
 		printf ("Error: start and/or end address"
 			" not on sector boundary\n");
 		rcode = 1;
@@ -243,7 +296,6 @@ int flash_sect_erase (ulong addr_first, ulong addr_last)
 	return rcode;
 }
 
-
 int do_protect (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
 	flash_info_t *info;
@@ -256,11 +308,11 @@ int do_protect (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 		return 1;
 	}
 
-	if (strcmp(argv[1], "off") == 0)
+	if (strcmp(argv[1], "off") == 0) {
 		p = 0;
-	else if (strcmp(argv[1], "on") == 0)
+	} else if (strcmp(argv[1], "on") == 0) {
 		p = 1;
-	else {
+	} else {
 		printf ("Usage:\n%s\n", cmdtp->usage);
 		return 1;
 	}
@@ -370,66 +422,43 @@ int flash_sect_protect (int p, ulong addr_first, ulong addr_last)
 {
 	flash_info_t *info;
 	ulong bank;
-	int s_first, s_last;
+	int s_first[CFG_MAX_FLASH_BANKS], s_last[CFG_MAX_FLASH_BANKS];
 	int protected, i;
-	int rcode = 0;
+	int planned;
+	int rcode;
+
+	rcode = flash_fill_sect_ranges( addr_first, addr_last, s_first, s_last, &planned );
 
 	protected = 0;
 
-	for (bank=0,info=&flash_info[0]; bank < CFG_MAX_FLASH_BANKS; ++bank, ++info) {
-		ulong b_end;
-		int sect;
-
-		if (info->flash_id == FLASH_UNKNOWN) {
-			continue;
-		}
-
-		b_end = info->start[0] + info->size - 1; /* bank end addr */
-
-		s_first = -1;		/* first sector to erase	*/
-		s_last  = -1;		/* last  sector to erase	*/
-
-		for (sect=0; sect < info->sector_count; ++sect) {
-			ulong end;		/* last address in current sect	*/
-			short s_end;
-
-			s_end = info->sector_count - 1;
-
-			end = (sect == s_end) ? b_end : info->start[sect + 1] - 1;
-
-			if (addr_first > end)
-				continue;
-			if (addr_last < info->start[sect])
+	if (planned && (rcode == 0)) {
+		for (bank=0,info=&flash_info[0]; bank < CFG_MAX_FLASH_BANKS; ++bank, ++info) {
+			if (info->flash_id == FLASH_UNKNOWN) {
 				continue;
+			}
 
-			if (addr_first == info->start[sect]) {
-				s_first = sect;
-			}
-			if (addr_last  == end) {
-				s_last  = sect;
-			}
-		}
-		if (s_first>=0 && s_first<=s_last) {
-			protected += s_last - s_first + 1;
-			for (i=s_first; i<=s_last; ++i) {
+			if (s_first[bank]>=0 && s_first[bank]<=s_last[bank]) {
+				debug ("Protecting sectors %d..%d in bank %ld\n",
+					s_first[bank], s_last[bank], bank+1);
+				protected += s_last[bank] - s_first[bank] + 1;
+				for (i=s_first[bank]; i<=s_last[bank]; ++i) {
 #if defined(CFG_FLASH_PROTECTION)
-				if (flash_real_protect(info, i, p))
-					rcode = 1;
-				putc ('.');
+					if (flash_real_protect(info, i, p))
+						rcode = 1;
+					putc ('.');
 #else
-				info->protect[i] = p;
+					info->protect[i] = p;
 #endif	/* CFG_FLASH_PROTECTION */
+				}
 			}
-		}
 #if defined(CFG_FLASH_PROTECTION)
-		if (!rcode) putc ('\n');
+			if (!rcode) putc ('\n');
 #endif	/* CFG_FLASH_PROTECTION */
+		}
 
-	}
-	if (protected) {
 		printf ("%sProtected %d sectors\n",
 			p ? "" : "Un-", protected);
-	} else {
+	} else if (rcode == 0) {
 		printf ("Error: start and/or end address"
 			" not on sector boundary\n");
 		rcode = 1;

common/cmd_i2c.c

@@ -507,6 +507,9 @@ mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char *argv[])
 				if(i2c_write(chip, addr, alen, (char *)&data, size) != 0) {
 					printf("Error writing the chip.\n");
 				}
+#ifdef CFG_EEPROM_PAGE_WRITE_DELAY_MS
+				udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
+#endif
 				if (incrflag)
 					addr += size;
 			}

common/cmd_load.c

@@ -28,7 +28,7 @@
 #include <command.h>
 #include <s_record.h>
 #include <net.h>
-#include <syscall.h>
+#include <exports.h>
 
 
 #if (CONFIG_COMMANDS & CFG_CMD_LOADS)
@@ -213,6 +213,7 @@ load_serial (ulong offset)
 static int
 read_record (char *buf, ulong len)
 {
+	DECLARE_GLOBAL_DATA_PTR;
 	char *p;
 	char c;
 
@@ -236,13 +237,11 @@ read_record (char *buf, ulong len)
 		}
 
 	    /* Check for the console hangup (if any different from serial) */
-#ifdef CONFIG_PPC	/* we don't have syscall_tbl anywhere else */
-	    if (syscall_tbl[SYSCALL_GETC] != serial_getc) {
+	    if (gd->jt[XF_getc] != serial_getc) {
 		if (ctrlc()) {
 		    return (-1);
 		}
 	    }
-#endif
 	}
 
 	/* line too long - truncate */
@@ -479,7 +478,7 @@ int do_load_serial_bin (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	printf ("## Ready for binary (kermit) download "
 		"to 0x%08lX at %d bps...\n",
 		offset,
-		current_baudrate);
+		load_baudrate);
 	addr = load_serial_bin (offset);
 
 	if (addr == ~0) {

common/cmd_log.c

@@ -75,6 +75,7 @@ void logbuff_init_ptrs (void)
 {
 	DECLARE_GLOBAL_DATA_PTR;
 	unsigned long *ext_tag;
+	unsigned long post_word;
 	char *s;
 
 	log_buf = (unsigned char *)(gd->bd->bi_memsize-LOGBUFF_LEN);
@@ -82,15 +83,16 @@ void logbuff_init_ptrs (void)
  	ext_log_start = (unsigned long *)(log_buf)-3;
 	ext_log_size = (unsigned long *)(log_buf)-2;
 	ext_logged_chars = (unsigned long *)(log_buf)-1;
+	post_word = post_word_load();
 #ifdef CONFIG_POST
 	/* The post routines have setup the word so we can simply test it */
- 	if ((post_word_load () & 0xffff) == POST_POWERON) {
+ 	if (post_word_load () & POST_COLDBOOT) {
  		logged_chars = log_size = log_start = 0;
 		*ext_tag = LOGBUFF_MAGIC;
  	}
 #else
 	/* No post routines, so we do our own checking                    */
- 	if (post_word_load () != LOGBUFF_MAGIC) {
+ 	if (post_word != LOGBUFF_MAGIC) {
  		logged_chars = log_size = log_start = 0;
 		post_word_store (LOGBUFF_MAGIC);
 		*ext_tag = LOGBUFF_MAGIC;

common/cmd_mem.c

@@ -53,6 +53,8 @@ int cmd_get_data_size(char* arg, int default_size)
 			return 2;
 		case 'l':
 			return 4;
+		default:
+			return -1;
 		}
 	}
 	return default_size;
@@ -86,9 +88,10 @@ static	ulong	base_address = 0;
 #define DISP_LINE_LEN	16
 int do_mem_md ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
-	ulong	addr, size, length;
+	ulong	addr, length;
 	ulong	i, nbytes, linebytes;
 	u_char	*cp;
+	int	size;
 	int rc = 0;
 
 	/* We use the last specified parameters, unless new ones are
@@ -107,7 +110,8 @@ int do_mem_md ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 		/* New command specified.  Check for a size specification.
 		 * Defaults to long if no or incorrect specification.
 		 */
-		size = cmd_get_data_size(argv[0], 4);
+		if ((size = cmd_get_data_size(argv[0], 4)) < 0)
+			return 1;
 
 		/* Address is specified since argc > 1
 		*/
@@ -199,7 +203,8 @@ int do_mem_nm ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 int do_mem_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
-	ulong	addr, size, writeval, count;
+	ulong	addr, writeval, count;
+	int	size;
 
 	if ((argc < 3) || (argc > 4)) {
 		printf ("Usage:\n%s\n", cmdtp->usage);
@@ -208,7 +213,8 @@ int do_mem_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 	/* Check for size specification.
 	*/
-	size = cmd_get_data_size(argv[0], 4);
+	if ((size = cmd_get_data_size(argv[0], 4)) < 1)
+		return 1;
 
 	/* Address is specified since argc > 1
 	*/
@@ -240,7 +246,8 @@ int do_mem_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 int do_mem_cmp (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
-	ulong	size, addr1, addr2, count, ngood;
+	ulong	addr1, addr2, count, ngood;
+	int	size;
 	int     rcode = 0;
 
 	if (argc != 4) {
@@ -250,7 +257,8 @@ int do_mem_cmp (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 	/* Check for size specification.
 	*/
-	size = cmd_get_data_size(argv[0], 4);
+	if ((size = cmd_get_data_size(argv[0], 4)) < 0)
+		return 1;
 
 	addr1 = simple_strtoul(argv[1], NULL, 16);
 	addr1 += base_address;
@@ -316,7 +324,8 @@ int do_mem_cmp (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 int do_mem_cp ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
-	ulong	addr, size, dest, count;
+	ulong	addr, dest, count;
+	int	size;
 
 	if (argc != 4) {
 		printf ("Usage:\n%s\n", cmdtp->usage);
@@ -325,7 +334,8 @@ int do_mem_cp ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 	/* Check for size specification.
 	*/
-	size = cmd_get_data_size(argv[0], 4);
+	if ((size = cmd_get_data_size(argv[0], 4)) < 0)
+		return 1;
 
 	addr = simple_strtoul(argv[1], NULL, 16);
 	addr += base_address;
@@ -458,7 +468,8 @@ int do_mem_base (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 int do_mem_loop (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
-	ulong	addr, size, length, i, junk;
+	ulong	addr, length, i, junk;
+	int	size;
 	volatile uint	*longp;
 	volatile ushort *shortp;
 	volatile u_char	*cp;
@@ -471,7 +482,8 @@ int do_mem_loop (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	/* Check for a size spefication.
 	 * Defaults to long if no or incorrect specification.
 	 */
-	size = cmd_get_data_size(argv[0], 4);
+	if ((size = cmd_get_data_size(argv[0], 4)) < 0)
+		return 1;
 
 	/* Address is always specified.
 	*/
@@ -839,8 +851,8 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 static int
 mod_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char *argv[])
 {
-	ulong	addr, size, i;
-	int	nbytes;
+	ulong	addr, i;
+	int	nbytes, size;
 	extern char console_buffer[];
 
 	if (argc != 2) {
@@ -861,7 +873,8 @@ mod_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char *argv[])
 		/* New command specified.  Check for a size specification.
 		 * Defaults to long if no or incorrect specification.
 		 */
-		size = cmd_get_data_size(argv[0], 4);
+		if ((size = cmd_get_data_size(argv[0], 4)) < 0)
+			return 1;
 
 		/* Address is specified since argc > 1
 		*/

common/cmd_nand.c

@@ -3,7 +3,6 @@
  * borrowed heavily from:
  * (c) 1999 Machine Vision Holdings, Inc.
  * (c) 1999, 2000 David Woodhouse <dwmw2@infradead.org>
- *
  */
 
 #include <common.h>
@@ -24,6 +23,12 @@
 #include <linux/mtd/nand_ids.h>
 #include <jffs2/jffs2.h>
 
+#ifdef CONFIG_OMAP1510
+void archflashwp(void *archdata, int wp);
+#endif
+
+#define ROUND_DOWN(value,boundary)      ((value) & (~((boundary)-1)))
+
 /*
  * Definition of the out of band configuration structure
  */
@@ -52,7 +57,7 @@ struct nand_oob_config {
 #define	 ALLOW_ERASE_BAD_DEBUG 0
 
 #define CONFIG_MTD_NAND_ECC  /* enable ECC */
-/* #define CONFIG_MTD_NAND_ECC_JFFS2 */
+#define CONFIG_MTD_NAND_ECC_JFFS2
 
 /* bits for nand_rw() `cmd'; or together as needed */
 #define NANDRW_READ	0x01
@@ -76,6 +81,7 @@ static int nand_read_oob(struct nand_chip* nand, size_t ofs, size_t len,
 		 size_t * retlen, u_char * buf);
 static int nand_write_oob(struct nand_chip* nand, size_t ofs, size_t len,
 		 size_t * retlen, const u_char * buf);
+static int NanD_WaitReady(struct nand_chip *nand, int ale_wait);
 #ifdef CONFIG_MTD_NAND_ECC
 static int nand_correct_data (u_char *dat, u_char *read_ecc, u_char *calc_ecc);
 static void nand_calculate_ecc (const u_char *dat, u_char *ecc_code);
@@ -218,7 +224,7 @@ int do_nand (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 		ret = nand_rw(nand_dev_desc + curr_device, cmd, off, size,
 			     &total, (u_char*)addr);
 
-		printf ("%d bytes %s: %s\n", total,
+		printf (" %d bytes %s: %s\n", total,
 			(cmd & NANDRW_READ) ? "read" : "write",
 			ret ? "ERROR" : "OK");
 
@@ -419,7 +425,7 @@ static int nand_rw (struct nand_chip* nand, int cmd,
 	    size_t start, size_t len,
 	    size_t * retlen, u_char * buf)
 {
-	int noecc, ret = 0, n, total = 0;
+	int ret = 0, n, total = 0;
 	char eccbuf[6];
 	/* eblk (once set) is the start of the erase block containing the
 	 * data being processed.
@@ -457,17 +463,18 @@ static int nand_rw (struct nand_chip* nand, int cmd,
 		}
 		/* The ECC will not be calculated correctly if
 		   less than 512 is written or read */
-		noecc = (start != (start | 0x1ff) + 1) ||	(len < 0x200);
+		/* Is request at least 512 bytes AND it starts on a proper boundry */
+		if((start != ROUND_DOWN(start, 0x200)) || (len < 0x200))
+			printf("Warning block writes should be at least 512 bytes and start on a 512 byte boundry\n");
+
 		if (cmd & NANDRW_READ)
 			ret = nand_read_ecc(nand, start,
 					   min(len, eblk + erasesize - start),
-					   &n, (u_char*)buf,
-					   noecc ? NULL : eccbuf);
+					   &n, (u_char*)buf, eccbuf);
 		else
 			ret = nand_write_ecc(nand, start,
 					    min(len, eblk + erasesize - start),
-					    &n, (u_char*)buf,
-					    noecc ? NULL : eccbuf);
+					    &n, (u_char*)buf, eccbuf);
 
 		if (ret)
 			break;
@@ -502,19 +509,19 @@ static void nand_print(struct nand_chip *nand)
 
 /* ------------------------------------------------------------------------- */
 
-/* This function is needed to avoid calls of the __ashrdi3 function. */
-#if 0
-static int shr(int val, int shift)
-{
-	return val >> shift;
-}
-#endif
-static int NanD_WaitReady(struct nand_chip *nand)
+static int NanD_WaitReady(struct nand_chip *nand, int ale_wait)
 {
 	/* This is inline, to optimise the common case, where it's ready instantly */
 	int ret = 0;
-	NAND_WAIT_READY(nand);
 
+#ifdef NAND_NO_RB	/* in config file, shorter delays currently wrap accesses */
+	if(ale_wait)
+		NAND_WAIT_READY(nand);	/* do the worst case 25us wait */
+	else
+		udelay(10);
+#else	/* has functional r/b signal */
+    NAND_WAIT_READY(nand);
+#endif
 	return ret;
 }
 
@@ -533,7 +540,16 @@ static inline int NanD_Command(struct nand_chip *nand, unsigned char command)
 	/* Lower the CLE line */
 	NAND_CTL_CLRCLE(nandptr);
 
-	return NanD_WaitReady(nand);
+#ifdef NAND_NO_RB
+	if(command == NAND_CMD_RESET){
+		u_char ret_val;
+		NanD_Command(nand, NAND_CMD_STATUS);
+		do{
+			ret_val = READ_NAND(nandptr);/* wait till ready */
+		} while((ret_val & 0x40) != 0x40);
+	}
+#endif
+	return NanD_WaitReady(nand, 0);
 }
 
 /* NanD_Address: Set the current address for the flash chip */
@@ -573,7 +589,7 @@ static int NanD_Address(struct nand_chip *nand, int numbytes, unsigned long ofs)
 	NAND_CTL_CLRALE(nandptr);
 
 	/* Wait for the chip to respond */
-	return NanD_WaitReady(nand);
+	return NanD_WaitReady(nand, 1);
 }
 
 /* NanD_SelectChip: Select a given flash chip within the current floor */
@@ -581,7 +597,7 @@ static int NanD_Address(struct nand_chip *nand, int numbytes, unsigned long ofs)
 static inline int NanD_SelectChip(struct nand_chip *nand, int chip)
 {
 	/* Wait for it to be ready */
-	return NanD_WaitReady(nand);
+	return NanD_WaitReady(nand, 0);
 }
 
 /* NanD_IdentChip: Identify a given NAND chip given {floor,chip} */
@@ -931,8 +947,8 @@ static int nand_write_page (struct nand_chip *nand,
 {
 
 	int i;
-#ifdef CONFIG_MTD_NAND_ECC
 	unsigned long nandptr = nand->IO_ADDR;
+#ifdef CONFIG_MTD_NAND_ECC
 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
 	int ecc_bytes = (nand->oobblock == 512) ? 6 : 3;
 #endif
@@ -992,12 +1008,20 @@ static int nand_write_page (struct nand_chip *nand,
 	/* Send command to actually program the data */
 	NanD_Command(nand, NAND_CMD_PAGEPROG);
 	NanD_Command(nand, NAND_CMD_STATUS);
+#ifdef NAND_NO_RB
+	{ u_char ret_val;
 
+	  do{
+		ret_val = READ_NAND(nandptr);	/* wait till ready */
+	  } while((ret_val & 0x40) != 0x40);
+	}
+#endif
 	/* See if device thinks it succeeded */
 	if (READ_NAND(nand->IO_ADDR) & 0x01) {
 		printf ("%s: Failed write, page 0x%08x, ", __FUNCTION__, page);
 		return -1;
 	}
+
 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
 	/*
 	 * The NAND device assumes that it is always writing to
@@ -1069,7 +1093,10 @@ static int nand_write_ecc (struct nand_chip* nand, size_t to, size_t len,
 	*retlen = 0;
 
 	/* Select the NAND device */
-	NAND_ENABLE_CE(nand);  /* set pin low */
+#ifdef CONFIG_OMAP1510
+	archflashwp(0,0);
+#endif
+    	NAND_ENABLE_CE(nand);  /* set pin low */
 
 	/* Check the WP bit */
 	NanD_Command(nand, NAND_CMD_STATUS);
@@ -1113,7 +1140,9 @@ static int nand_write_ecc (struct nand_chip* nand, size_t to, size_t len,
 out:
 	/* De-select the NAND device */
 	NAND_DISABLE_CE(nand);  /* set pin high */
-
+#ifdef CONFIG_OMAP1510
+    	archflashwp(0,1);
+#endif
 	return ret;
 }
 
@@ -1160,7 +1189,7 @@ static int nand_read_oob(struct nand_chip* nand, size_t ofs, size_t len,
 	 * causing the flash device to go into busy mode, so we need
 	 * to wait until ready 11.4.1 and Toshiba TC58256FT nands */
 
-	ret = NanD_WaitReady(nand);
+	ret = NanD_WaitReady(nand, 1);
 	NAND_DISABLE_CE(nand);  /* set pin high */
 
 	return ret;
@@ -1215,8 +1244,13 @@ static int nand_write_oob(struct nand_chip* nand, size_t ofs, size_t len,
 
 		NanD_Command(nand, NAND_CMD_PAGEPROG);
 		NanD_Command(nand, NAND_CMD_STATUS);
-		/* NanD_WaitReady() is implicit in NanD_Command */
-
+#ifdef NAND_NO_RB
+   		{ u_char ret_val;
+    		  do{
+		  	ret_val = READ_NAND(nandptr); /* wait till ready */
+    		  }while((ret_val & 0x40) != 0x40);
+		}
+#endif
 		if (READ_NAND(nandptr) & 1) {
 			puts ("Error programming oob data\n");
 			/* There was an error */
@@ -1233,8 +1267,13 @@ static int nand_write_oob(struct nand_chip* nand, size_t ofs, size_t len,
 
 	NanD_Command(nand, NAND_CMD_PAGEPROG);
 	NanD_Command(nand, NAND_CMD_STATUS);
-	/* NanD_WaitReady() is implicit in NanD_Command */
-
+#ifdef NAND_NO_RB
+	{ u_char ret_val;
+	  do{
+		ret_val = READ_NAND(nandptr); /* wait till ready */
+	  } while((ret_val & 0x40) != 0x40);
+	}
+#endif
 	if (READ_NAND(nandptr) & 1) {
 		puts ("Error programming oob data\n");
 		/* There was an error */
@@ -1272,7 +1311,10 @@ static int nand_erase(struct nand_chip* nand, size_t ofs, size_t len, int clean)
 	nandptr = nand->IO_ADDR;
 
 	/* Select the NAND device */
-	NAND_ENABLE_CE(nand);  /* set pin low */
+#ifdef CONFIG_OMAP1510
+	archflashwp(0,0);
+#endif
+    NAND_ENABLE_CE(nand);  /* set pin low */
 
 	/* Check the WP bit */
 	NanD_Command(nand, NAND_CMD_STATUS);
@@ -1308,6 +1350,13 @@ static int nand_erase(struct nand_chip* nand, size_t ofs, size_t len, int clean)
 
 			NanD_Command(nand, NAND_CMD_STATUS);
 
+#ifdef NAND_NO_RB
+			{ u_char ret_val;
+			  do{
+				ret_val = READ_NAND(nandptr); /* wait till ready */
+			  } while((ret_val & 0x40) != 0x40);
+			}
+#endif
 			if (READ_NAND(nandptr) & 1) {
 				printf ("%s: Error erasing at 0x%lx\n",
 					__FUNCTION__, (long)ofs);
@@ -1346,7 +1395,9 @@ static int nand_erase(struct nand_chip* nand, size_t ofs, size_t len, int clean)
 out:
 	/* De-select the NAND device */
 	NAND_DISABLE_CE(nand);  /* set pin high */
-
+#ifdef CONFIG_OMAP1510
+    	archflashwp(0,1);
+#endif
 	return ret;
 }
 
@@ -1596,5 +1647,6 @@ static int nand_correct_data (u_char *dat, u_char *read_ecc, u_char *calc_ecc)
 	/* Should never happen */
 	return -1;
 }
+
 #endif
 #endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */

common/cmd_net.c

@@ -116,6 +116,13 @@ static void netboot_update_env(void)
 	setenv("dnsip", tmp);
     }
 
+#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_DNS2)
+    if (NetOurDNS2IP) {
+	    ip_to_string (NetOurDNS2IP, tmp);
+	    setenv("dnsip2", tmp);
+    }
+#endif
+
     if (NetOurNISDomain[0])
 	setenv("domain", NetOurNISDomain);
 
@@ -210,6 +217,12 @@ int do_ping (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 	return 0;
 }
+
+U_BOOT_CMD(
+	ping,	2,	1,	do_ping,
+	"ping    - send ICMP ECHO_REQUEST to network host\n",
+	"pingAddress\n"
+);
 #endif	/* CFG_CMD_PING */
 
 #endif	/* CFG_CMD_NET */

common/cmd_nvedit.c

@@ -183,9 +183,6 @@ int _do_setenv (int flag, int argc, char *argv[])
 		 * ver is readonly.
 		 */
 		if ( (strcmp (name, "serial#") == 0) ||
-#if defined(CONFIG_VERSION_VARIABLE)
-		     (strcmp (name, "ver") == 0) ||
-#endif /* CONFIG_VERSION_VARIABLE */
 		    ((strcmp (name, "ethaddr") == 0)
 #if defined(CONFIG_OVERWRITE_ETHADDR_ONCE) && defined(CONFIG_ETHADDR)
 		     && (strcmp (env_get_addr(oldval),MK_STR(CONFIG_ETHADDR)) != 0)

common/console.c

@@ -25,9 +25,7 @@
 #include <stdarg.h>
 #include <malloc.h>
 #include <console.h>
-#include <syscall.h>
-
-void **syscall_tbl;
+#include <exports.h>
 
 #ifdef CONFIG_AMIGAONEG3SE
 int console_changed = 0;
@@ -52,6 +50,7 @@ int overwrite_console (void)
 
 static int console_setfile (int file, device_t * dev)
 {
+	DECLARE_GLOBAL_DATA_PTR;
 	int error = 0;
 
 	if (dev == NULL)
@@ -78,13 +77,13 @@ static int console_setfile (int file, device_t * dev)
 		 */
 		switch (file) {
 		case stdin:
-			syscall_tbl[SYSCALL_GETC] = dev->getc;
-			syscall_tbl[SYSCALL_TSTC] = dev->tstc;
+			gd->jt[XF_getc] = dev->getc;
+			gd->jt[XF_tstc] = dev->tstc;
 			break;
 		case stdout:
-			syscall_tbl[SYSCALL_PUTC] = dev->putc;
-			syscall_tbl[SYSCALL_PUTS] = dev->puts;
-			syscall_tbl[SYSCALL_PRINTF] = printf;
+			gd->jt[XF_putc] = dev->putc;
+			gd->jt[XF_puts] = dev->puts;
+			gd->jt[XF_printf] = printf;
 			break;
 		}
 		break;
@@ -394,15 +393,16 @@ device_t *search_device (int flags, char *name)
 /* Called after the relocation - use desired console functions */
 int console_init_r (void)
 {
+	DECLARE_GLOBAL_DATA_PTR;
 	char *stdinname, *stdoutname, *stderrname;
 	device_t *inputdev = NULL, *outputdev = NULL, *errdev = NULL;
 
 	/* set default handlers at first */
-	syscall_tbl[SYSCALL_GETC] = serial_getc;
-	syscall_tbl[SYSCALL_TSTC] = serial_tstc;
-	syscall_tbl[SYSCALL_PUTC] = serial_putc;
-	syscall_tbl[SYSCALL_PUTS] = serial_puts;
-	syscall_tbl[SYSCALL_PRINTF] = serial_printf;
+	gd->jt[XF_getc] = serial_getc;
+	gd->jt[XF_tstc] = serial_tstc;
+	gd->jt[XF_putc] = serial_putc;
+	gd->jt[XF_puts] = serial_puts;
+	gd->jt[XF_printf] = serial_printf;
 
 	/* stdin stdout and stderr are in environment */
 	/* scan for it */

common/exports.c

@@ -0,0 +1,31 @@
+#include <common.h>
+#include <exports.h>
+
+static void dummy(void)
+{
+}
+
+unsigned long get_version(void)
+{
+	return XF_VERSION;
+}
+
+void jumptable_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	int i;
+
+	gd->jt = (void **) malloc (XF_MAX * sizeof (void *));
+	for (i = 0; i < XF_MAX; i++)
+		gd->jt[i] = (void *) dummy;
+
+	gd->jt[XF_get_version] = (void *) get_version;
+	gd->jt[XF_malloc] = (void *) malloc;
+	gd->jt[XF_free] = (void *) free;
+	gd->jt[XF_get_timer] = (void *)get_timer;
+	gd->jt[XF_udelay] = (void *)udelay;
+#if defined(CONFIG_I386) || defined(CONFIG_PPC)
+	gd->jt[XF_install_hdlr] = (void *) irq_install_handler;
+	gd->jt[XF_free_hdlr] = (void *) irq_free_handler;
+#endif
+}

common/lynxkdi.c

@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) Orbacom Systems, Inc <www.orbacom.com>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are freely
+ * permitted provided that the above copyright notice and this
+ * paragraph and the following disclaimer are duplicated in all
+ * such forms.
+ *
+ * This software is provided "AS IS" and without any express or
+ * implied warranties, including, without limitation, the implied
+ * warranties of merchantability and fitness for a particular
+ * purpose.
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <image.h>
+
+#if defined(CONFIG_LYNXKDI)
+#include <lynxkdi.h>
+
+#if defined(CONFIG_MPC8260)
+void lynxkdi_boot ( image_header_t *hdr )
+{
+	void (*lynxkdi)(void) = (void(*)(void))hdr->ih_ep;
+	lynxos_bootparms_t *parms = (lynxos_bootparms_t *)0x0020;
+	bd_t *kbd;
+	DECLARE_GLOBAL_DATA_PTR;
+	u32 *psz = (u32 *)(hdr->ih_load + 0x0204);
+
+	memset( parms, 0, sizeof(*parms));
+	kbd = gd->bd;
+	parms->clock_ref = kbd->bi_busfreq;
+	parms->dramsz = kbd->bi_memsize;
+	memcpy(parms->ethaddr, kbd->bi_enetaddr, 6);
+	mtspr(SPRN_SPRG2, 0x0020);
+
+	/* Do a simple check for Bluecat so we can pass the
+	 * kernel command line parameters.
+	 */
+	if( le32_to_cpu(*psz) == hdr->ih_size ){
+	    char *args;
+	    char *cmdline = (char *)(hdr->ih_load + 0x020c);
+	    int len;
+
+	    printf("Booting Bluecat KDI ...\n");
+	    udelay(200*1000); /* Allow serial port to flush */
+	    if ((args = getenv("bootargs")) == NULL)
+		    args = "";
+	    /* Prepend the cmdline */
+	    len = strlen(args);
+	    if( len && (len + strlen(cmdline) + 2 < (0x0400 - 0x020c))) {
+		memmove( cmdline + strlen(args) + 1, cmdline, strlen(cmdline) );
+		strcpy( cmdline, args );
+		cmdline[len] = ' ';
+	    }
+	}
+	else {
+	    printf("Booting LynxOS KDI ...\n");
+	}
+
+	lynxkdi();
+}
+#else
+#error "Lynx KDI support not implemented for configured CPU"
+#endif
+
+#endif	/* CONFIG_LYNXKDI */
+

common/main.c

@@ -32,6 +32,8 @@
 #include <hush.h>
 #endif
 
+#include <post.h>
+
 #if defined(CONFIG_BOOT_RETRY_TIME) && defined(CONFIG_RESET_TO_RETRY)
 extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);		/* for do_reset() prototype */
 #endif
@@ -258,6 +260,12 @@ void main_loop (void)
 #ifdef CONFIG_PREBOOT
 	char *p;
 #endif
+#ifdef CONFIG_BOOTCOUNT_LIMIT
+	unsigned long bootcount = 0;
+	unsigned long bootlimit = 0;
+	char *bcs;
+	char bcs_set[16];
+#endif /* CONFIG_BOOTCOUNT_LIMIT */
 
 #if defined(CONFIG_VFD) && defined(VFD_TEST_LOGO)
 	ulong bmp = 0;		/* default bitmap */
@@ -270,6 +278,16 @@ void main_loop (void)
 	trab_vfd (bmp);
 #endif	/* CONFIG_VFD && VFD_TEST_LOGO */
 
+#ifdef CONFIG_BOOTCOUNT_LIMIT
+	bootcount = bootcount_load();
+	bootcount++;
+	bootcount_store (bootcount);
+	sprintf (bcs_set, "%lu", bootcount);
+	setenv ("bootcount", bcs_set);
+	bcs = getenv ("bootlimit");
+	bootlimit = bcs ? simple_strtoul (bcs, NULL, 10) : 0;
+#endif /* CONFIG_BOOTCOUNT_LIMIT */
+
 #ifdef CONFIG_MODEM_SUPPORT
 	debug ("DEBUG: main_loop:   do_mdm_init=%d\n", do_mdm_init);
 	if (do_mdm_init) {
@@ -284,10 +302,8 @@ void main_loop (void)
 #ifdef CONFIG_VERSION_VARIABLE
 	{
 		extern char version_string[];
-		char *str = getenv("ver");
 
-		if (!str)
-			setenv ("ver", version_string);  /* set version variable */
+		setenv ("ver", version_string);  /* set version variable */
 	}
 #endif /* CONFIG_VERSION_VARIABLE */
 
@@ -324,7 +340,15 @@ void main_loop (void)
 	init_cmd_timeout ();
 # endif	/* CONFIG_BOOT_RETRY_TIME */
 
-	s = getenv ("bootcmd");
+#ifdef CONFIG_BOOTCOUNT_LIMIT
+	if (bootlimit && (bootcount > bootlimit)) {
+		printf ("Warning: Bootlimit (%u) exceeded. Using altbootcmd.\n",
+		        (unsigned)bootlimit);
+		s = getenv ("altbootcmd");
+	}
+	else
+#endif /* CONFIG_BOOTCOUNT_LIMIT */
+		s = getenv ("bootcmd");
 
 	debug ("### main_loop: bootcmd=\"%s\"\n", s ? s : "<UNDEFINED>");
 

config.mk

@@ -112,8 +112,8 @@ gccincdir := $(shell $(CC) -print-file-name=include)
 CPPFLAGS := $(DBGFLAGS) $(OPTFLAGS) $(RELFLAGS)		\
 	-D__KERNEL__ -DTEXT_BASE=$(TEXT_BASE)		\
 	-I$(TOPDIR)/include				\
-	-fno-builtin -nostdinc -isystem $(gccincdir)	\
-	-pipe $(PLATFORM_CPPFLAGS)
+	-fno-builtin -ffreestanding -nostdinc -isystem	\
+	$(gccincdir) -pipe $(PLATFORM_CPPFLAGS)
 
 ifdef BUILD_TAG
 CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes \

cpu/74xx_7xx/start.S

@@ -159,75 +159,7 @@ ProgramCheck:
 	STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
 	STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
 	STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
-
-	. = 0xc00
-/*
- * r0 - SYSCALL number
- * r3-... arguments
- */
-SystemCall:
-	addis	r11,r0,0		/* get functions table addr */
-	ori	r11,r11,0		/* Note: this code is patched in trap_init */
-	addis	r12,r0,0		/* get number of functions */
-	ori	r12,r12,0
-
-	cmplw	0, r0, r12
-	bge	1f
-
-	rlwinm	r0,r0,2,0,31		/* fn_addr = fn_tbl[r0] */
-	add	r11,r11,r0
-	lwz	r11,0(r11)
-
-	li	r20,0xd00-4		/* Get stack pointer */
-	lwz	r12,0(r20)
-	subi	r12,r12,12		/* Adjust stack pointer */
-	li	r0,0xc00+_end_back-SystemCall
-	cmplw	0, r0, r12		/* Check stack overflow */
-	bgt	1f
-	stw	r12,0(r20)
-
-	mflr	r0
-	stw	r0,0(r12)
-	mfspr	r0,SRR0
-	stw	r0,4(r12)
-	mfspr	r0,SRR1
-	stw	r0,8(r12)
-
-	li	r12,0xc00+_back-SystemCall
-	mtlr	r12
-	mtspr	SRR0,r11
-
-1:	SYNC
-	rfi
-
-_back:
-
-	mfmsr	r11			/* Disable interrupts */
-	li	r12,0
-	ori	r12,r12,MSR_EE
-	andc	r11,r11,r12
-	SYNC				/* Some chip revs need this... */
-	mtmsr	r11
-	SYNC
-
-	li	r12,0xd00-4		/* restore regs */
-	lwz	r12,0(r12)
-
-	lwz	r11,0(r12)
-	mtlr	r11
-	lwz	r11,4(r12)
-	mtspr	SRR0,r11
-	lwz	r11,8(r12)
-	mtspr	SRR1,r11
-
-	addi	r12,r12,12		/* Adjust stack pointer */
-	li	r20,0xd00-4
-	stw	r12,0(r20)
-
-	SYNC
-	rfi
-_end_back:
-
+	STD_EXCEPTION(0xc00, SystemCall, UnknownException)
 	STD_EXCEPTION(0xd00, SingleStep, UnknownException)
 
 	STD_EXCEPTION(0xe00, Trap_0e, UnknownException)

cpu/arm925t/Makefile

@@ -0,0 +1,43 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(CPU).a
+
+START	= start.o
+OBJS	= interrupts.o cpu.o omap925.o
+
+all:	.depend $(START) $(LIB)
+
+$(LIB):	$(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(START:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################

cpu/arm925t/config.mk

@@ -0,0 +1,27 @@
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+PLATFORM_RELFLAGS += -fno-strict-aliasing  -fno-common -ffixed-r8 \
+	-mshort-load-bytes -msoft-float
+
+PLATFORM_CPPFLAGS += -mapcs-32 -march=armv4

cpu/arm925t/cpu.c

@@ -0,0 +1,159 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * CPU specific code
+ */
+
+#include <common.h>
+#include <command.h>
+#include <arm925t.h>
+
+/* read co-processor 15, register #1 (control register) */
+static unsigned long read_p15_c1 (void)
+{
+	unsigned long value;
+
+	__asm__ __volatile__(
+		"mrc	p15, 0, %0, c1, c0, 0   @ read control reg\n"
+		: "=r" (value)
+		:
+		: "memory");
+
+#ifdef MMU_DEBUG
+	printf ("p15/c1 is = %08lx\n", value);
+#endif
+	return value;
+}
+
+/* write to co-processor 15, register #1 (control register) */
+static void write_p15_c1 (unsigned long value)
+{
+#ifdef MMU_DEBUG
+	printf ("write %08lx to p15/c1\n", value);
+#endif
+	__asm__ __volatile__(
+		"mcr	p15, 0, %0, c1, c0, 0   @ write it back\n"
+		:
+		: "r" (value)
+		: "memory");
+
+	read_p15_c1 ();
+}
+
+static void cp_delay (void)
+{
+	volatile int i;
+
+	/* Many OMAP regs need at least 2 nops  */
+	for (i = 0; i < 100; i++);
+}
+
+/* See also ARM Ref. Man. */
+#define C1_MMU		(1<<0)		/* mmu off/on */
+#define C1_ALIGN	(1<<1)		/* alignment faults off/on */
+#define C1_DC		(1<<2)		/* dcache off/on */
+#define C1_WB		(1<<3)		/* merging write buffer on/off */
+#define C1_BIG_ENDIAN	(1<<7)	/* big endian off/on */
+#define C1_SYS_PROT	(1<<8)		/* system protection */
+#define C1_ROM_PROT	(1<<9)		/* ROM protection */
+#define C1_IC		(1<<12)		/* icache off/on */
+#define C1_HIGH_VECTORS	(1<<13)	/* location of vectors: low/high addresses */
+#define RESERVED_1	(0xf << 3)	/* must be 111b for R/W */
+
+int cpu_init (void)
+{
+	/*
+	 * setup up stack if necessary
+	 */
+#ifdef CONFIG_USE_IRQ
+	IRQ_STACK_START = _armboot_end +
+			CONFIG_STACKSIZE + CONFIG_STACKSIZE_IRQ - 4;
+	FIQ_STACK_START = IRQ_STACK_START + CONFIG_STACKSIZE_FIQ;
+	_armboot_real_end = FIQ_STACK_START + 4;
+#else
+	_armboot_real_end = _armboot_end + CONFIG_STACKSIZE;
+#endif	/* CONFIG_USE_IRQ */
+	return (0);
+}
+
+int cleanup_before_linux (void)
+{
+	/*
+	 * this function is called just before we call linux
+	 * it prepares the processor for linux
+	 *
+	 * we turn off caches etc ...
+	 */
+
+	unsigned long i;
+
+	disable_interrupts ();
+
+	/* turn off I/D-cache */
+	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+	i &= ~(C1_DC | C1_IC);
+	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+
+	/* flush I/D-cache */
+	i = 0;
+	asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));
+	return (0);
+}
+
+int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	extern void reset_cpu (ulong addr);
+
+	disable_interrupts ();
+	reset_cpu (0);
+	/*NOTREACHED*/
+	return (0);
+}
+
+void icache_enable (void)
+{
+	ulong reg;
+
+	reg = read_p15_c1 ();		/* get control reg. */
+	cp_delay ();
+	write_p15_c1 (reg | C1_IC);
+}
+
+void icache_disable (void)
+{
+	ulong reg;
+
+	reg = read_p15_c1 ();
+	cp_delay ();
+	write_p15_c1 (reg & ~C1_IC);
+}
+
+int icache_status (void)
+{
+	return (read_p15_c1 () & C1_IC) != 0;
+}

cpu/arm925t/interrupts.c

@@ -0,0 +1,300 @@
+/*
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <arm925t.h>
+#include <configs/omap1510.h>
+
+#include <asm/proc-armv/ptrace.h>
+
+extern void reset_cpu(ulong addr);
+#define TIMER_LOAD_VAL 0xffffffff
+
+/* macro to read the 32 bit timer */
+#define READ_TIMER (*(volatile ulong *)(CFG_TIMERBASE+8))
+
+#ifdef CONFIG_USE_IRQ
+/* enable IRQ interrupts */
+void enable_interrupts (void)
+{
+	unsigned long temp;
+	__asm__ __volatile__("mrs %0, cpsr\n"
+			     "bic %0, %0, #0x80\n"
+			     "msr cpsr_c, %0"
+			     : "=r" (temp)
+			     :
+			     : "memory");
+}
+
+
+/*
+ * disable IRQ/FIQ interrupts
+ * returns true if interrupts had been enabled before we disabled them
+ */
+int disable_interrupts (void)
+{
+	unsigned long old,temp;
+	__asm__ __volatile__("mrs %0, cpsr\n"
+			     "orr %1, %0, #0xc0\n"
+			     "msr cpsr_c, %1"
+			     : "=r" (old), "=r" (temp)
+			     :
+			     : "memory");
+	return (old & 0x80) == 0;
+}
+#else
+void enable_interrupts (void)
+{
+	return;
+}
+int disable_interrupts (void)
+{
+	return 0;
+}
+#endif
+
+
+void bad_mode (void)
+{
+	panic ("Resetting CPU ...\n");
+	reset_cpu (0);
+}
+
+void show_regs (struct pt_regs *regs)
+{
+	unsigned long flags;
+	const char *processor_modes[] = {
+	"USER_26",	"FIQ_26",	"IRQ_26",	"SVC_26",
+	"UK4_26",	"UK5_26",	"UK6_26",	"UK7_26",
+	"UK8_26",	"UK9_26",	"UK10_26",	"UK11_26",
+	"UK12_26",	"UK13_26",	"UK14_26",	"UK15_26",
+	"USER_32",	"FIQ_32",	"IRQ_32",	"SVC_32",
+	"UK4_32",	"UK5_32",	"UK6_32",	"ABT_32",
+	"UK8_32",	"UK9_32",	"UK10_32",	"UND_32",
+	"UK12_32",	"UK13_32",	"UK14_32",	"SYS_32",
+	};
+
+	flags = condition_codes (regs);
+
+	printf ("pc : [<%08lx>]    lr : [<%08lx>]\n"
+		"sp : %08lx  ip : %08lx  fp : %08lx\n",
+		instruction_pointer (regs),
+		regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp);
+	printf ("r10: %08lx  r9 : %08lx  r8 : %08lx\n",
+		regs->ARM_r10, regs->ARM_r9, regs->ARM_r8);
+	printf ("r7 : %08lx  r6 : %08lx  r5 : %08lx  r4 : %08lx\n",
+		regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4);
+	printf ("r3 : %08lx  r2 : %08lx  r1 : %08lx  r0 : %08lx\n",
+		regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0);
+	printf ("Flags: %c%c%c%c",
+		flags & CC_N_BIT ? 'N' : 'n',
+		flags & CC_Z_BIT ? 'Z' : 'z',
+		flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v');
+	printf ("  IRQs %s  FIQs %s  Mode %s%s\n",
+		interrupts_enabled (regs) ? "on" : "off",
+		fast_interrupts_enabled (regs) ? "on" : "off",
+		processor_modes[processor_mode (regs)],
+		thumb_mode (regs) ? " (T)" : "");
+}
+
+void do_undefined_instruction (struct pt_regs *pt_regs)
+{
+	printf ("undefined instruction\n");
+	show_regs (pt_regs);
+	bad_mode ();
+}
+
+void do_software_interrupt (struct pt_regs *pt_regs)
+{
+	printf ("software interrupt\n");
+	show_regs (pt_regs);
+	bad_mode ();
+}
+
+void do_prefetch_abort (struct pt_regs *pt_regs)
+{
+	printf ("prefetch abort\n");
+	show_regs (pt_regs);
+	bad_mode ();
+}
+
+void do_data_abort (struct pt_regs *pt_regs)
+{
+	printf ("data abort\n");
+	show_regs (pt_regs);
+	bad_mode ();
+}
+
+void do_not_used (struct pt_regs *pt_regs)
+{
+	printf ("not used\n");
+	show_regs (pt_regs);
+	bad_mode ();
+}
+
+void do_fiq (struct pt_regs *pt_regs)
+{
+	printf ("fast interrupt request\n");
+	show_regs (pt_regs);
+	bad_mode ();
+}
+
+void do_irq (struct pt_regs *pt_regs)
+{
+	printf ("interrupt request\n");
+	show_regs (pt_regs);
+	bad_mode ();
+}
+
+static ulong timestamp;
+static ulong lastdec;
+
+/* nothing really to do with interrupts, just starts up a counter. */
+int interrupt_init (void)
+{
+	int32_t val;
+
+	*((int32_t *) (CFG_TIMERBASE + LOAD_TIM)) = TIMER_LOAD_VAL;
+	val = MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE | (CFG_PVT << MPUTIM_PTV_BIT);
+	*((int32_t *) (CFG_TIMERBASE + CNTL_TIMER)) = val;
+	return (0);
+}
+
+/*
+ * timer without interrupts
+ */
+
+void reset_timer (void)
+{
+	reset_timer_masked ();
+}
+
+ulong get_timer (ulong base)
+{
+	return get_timer_masked () - base;
+}
+
+void set_timer (ulong t)
+{
+	timestamp = t;
+}
+
+/* very rough timer... */
+void udelay (unsigned long usec)
+{
+#ifdef CONFIG_INNOVATOROMAP1510
+#define LOOPS_PER_MSEC 60		/* tuned on omap1510 */
+	volatile int i, time_remaining = LOOPS_PER_MSEC * usec;
+
+	for (i = time_remaining; i > 0; i--) {
+	}
+#else
+
+	ulong tmo;
+
+	tmo = usec / 1000;
+	tmo *= CFG_HZ;
+	tmo /= 1000;
+
+	tmo += get_timer (0);
+
+	while (get_timer_masked () < tmo)
+		/*NOP*/;
+#endif
+}
+
+void reset_timer_masked (void)
+{
+	/* reset time */
+	lastdec = READ_TIMER;
+	timestamp = 0;
+}
+
+ulong get_timer_masked (void)
+{
+	ulong now = READ_TIMER;           /* current tick value */
+
+	if (lastdec >= now) {             /* did I roll (rem decrementer) */
+		/* normal mode */
+		timestamp += lastdec - now;   /* record amount of time since last check */
+	} else {
+		/* we have an overflow ... */
+		timestamp += lastdec + TIMER_LOAD_VAL - now;
+	}
+	lastdec = now;
+
+	return timestamp;
+}
+
+void udelay_masked (unsigned long usec)
+{
+#ifdef CONFIG_INNOVATOROMAP1510
+	#define LOOPS_PER_MSEC 60 /* tuned on omap1510 */
+	volatile int i, time_remaining = LOOPS_PER_MSEC*usec;
+    for (i=time_remaining; i>0; i--) { }
+#else
+
+	ulong tmo;
+
+	tmo = usec / 1000;
+	tmo *= CFG_HZ;
+	tmo /= 1000;
+
+	reset_timer_masked ();
+
+	while (get_timer_masked () < tmo)
+		/*NOP*/;
+#endif
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk (void)
+{	/* poor timer, may need to improve especiall for bootp. */
+	ulong tbclk;
+
+	tbclk = CFG_HZ;
+	return tbclk;
+}

cpu/arm925t/omap925.c

@@ -0,0 +1,73 @@
+/*
+ * (C) Copyright 2003
+ * Texas Instruments <www.ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <arm925t.h>
+
+ushort gpioreserved;
+
+void gpioreserve(ushort mask)
+{
+	gpioreserved |= mask;
+}
+
+void gpiosetdir(ushort mask, ushort in)
+{
+	*(ushort *)GPIO_DIR_CONTROL_REG = (*(ushort *)GPIO_DIR_CONTROL_REG & ~mask) | (in & mask);
+}
+
+
+void gpiosetout(ushort mask, ushort out)
+{
+	ushort *r_ptr, r_val;
+
+	r_ptr = (ushort *)GPIO_DATA_OUTPUT_REG;	/* set pointer */
+	r_val = *r_ptr & ~mask;		/* get previous val, clear bits we want to change */
+	r_val |= (out & mask);		/* set specified bits in value + plus origional ones */
+	*r_ptr = r_val;			/* write it out */
+/*
+ * gcc screwed this one up :(.
+ *
+ * *(ushort *)GPIO_DATA_OUTPUT_REG = (*(ushort *)GPIO_DATA_OUTPUT_REG & ~mask) | (out & mask);
+ */
+
+}
+
+void gpioinit(void)
+{
+}
+
+
+#define MIF_CONFIG_REG 0xFFFECC0C
+#define FLASH_GLOBAL_CTRL_NWP 1
+
+void archflashwp (void *archdata, int wp)
+{
+	ulong *fgc = (ulong *) MIF_CONFIG_REG;
+
+	if (wp == 1)
+		*fgc &= ~FLASH_GLOBAL_CTRL_NWP;
+	else
+		*fgc |= FLASH_GLOBAL_CTRL_NWP;
+}

cpu/arm925t/start.S

@@ -0,0 +1,422 @@
+/*
+ *  armboot - Startup Code for ARM925 CPU-core
+ *
+ *  Copyright (c) 2003  Texas Instruments
+ *
+ *  ----- Adapted for OMAP1510 from ARM920 code ------
+ *
+ *  Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
+ *  Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
+ *  Copyright (c) 2002	Gary Jennejohn <gj@denx.de>
+ *  Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
+ *  Copyright (c) 2003	Kshitij 	 <kshitij@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <version.h>
+
+#if defined(CONFIG_OMAP1510)
+#include <./configs/omap1510.h>
+#endif
+
+/*
+ *************************************************************************
+ *
+ * Jump vector table as in table 3.1 in [1]
+ *
+ *************************************************************************
+ */
+
+
+.globl _start
+_start:	b       reset
+	ldr	pc, _undefined_instruction
+	ldr	pc, _software_interrupt
+	ldr	pc, _prefetch_abort
+	ldr	pc, _data_abort
+	ldr	pc, _not_used
+	ldr	pc, _irq
+	ldr	pc, _fiq
+
+_undefined_instruction:	.word undefined_instruction
+_software_interrupt:	.word software_interrupt
+_prefetch_abort:	.word prefetch_abort
+_data_abort:		.word data_abort
+_not_used:		.word not_used
+_irq:			.word irq
+_fiq:			.word fiq
+
+	.balignl 16,0xdeadbeef
+
+
+/*
+ *************************************************************************
+ *
+ * Startup Code (reset vector)
+ *
+ * do important init only if we don't start from memory!
+ * setup Memory and board specific bits prior to relocation.
+ * relocate armboot to ram
+ * setup stack
+ *
+ *************************************************************************
+ */
+
+/*
+ * CFG_MEM_END is in the board dependent config-file (configs/config_BOARD.h)
+ */
+_TEXT_BASE:
+	.word	TEXT_BASE
+
+.globl _armboot_start
+_armboot_start:
+	.word _start
+
+/*
+ * Note: _armboot_end_data and _armboot_end are defined
+ * by the (board-dependent) linker script.
+ * _armboot_end_data is the first usable FLASH address after armboot
+ */
+.globl _armboot_end_data
+_armboot_end_data:
+	.word armboot_end_data
+.globl _armboot_end
+_armboot_end:
+	.word armboot_end
+
+/*
+ * _armboot_real_end is the first usable RAM address behind armboot
+ * and the various stacks
+ */
+.globl _armboot_real_end
+_armboot_real_end:
+	.word 0x0badc0de
+
+#ifdef CONFIG_USE_IRQ
+/* IRQ stack memory (calculated at run-time) */
+.globl IRQ_STACK_START
+IRQ_STACK_START:
+	.word	0x0badc0de
+
+/* IRQ stack memory (calculated at run-time) */
+.globl FIQ_STACK_START
+FIQ_STACK_START:
+	.word 0x0badc0de
+#endif
+
+
+/*
+ * the actual reset code
+ */
+
+reset:
+	/*
+	 * set the cpu to SVC32 mode
+	 */
+	mrs	r0,cpsr
+	bic	r0,r0,#0x1f
+	orr	r0,r0,#0xd3
+	msr	cpsr,r0
+
+	/*
+	 * Set up 925T mode
+	 */
+	mov r1, #0x81               /* Set ARM925T configuration. */
+	mcr p15, 0, r1, c15, c1, 0  /* Write ARM925T configuration register. */
+
+	/*
+	 * turn off the watchdog, unlock/diable sequence
+	 */
+	mov  r1, #0xF5
+	ldr  r0, =WDTIM_MODE
+	strh r1, [r0]
+	mov  r1, #0xA0
+	strh r1, [r0]
+
+	/*
+	 * mask all IRQs by setting all bits in the INTMR - default
+	 */
+	mov r1, #0xffffffff
+	ldr r0, =REG_IHL1_MIR
+	str r1, [r0]
+	ldr r0, =REG_IHL2_MIR
+	str r1, [r0]
+
+	/*
+	 * wait for dpll to lock
+	 */
+	ldr  r0, =CK_DPLL1
+	mov  r1, #0x10
+	strh r1, [r0]
+poll1:
+	ldrh r1, [r0]
+	ands r1, r1, #0x01
+	beq poll1
+	bl  cpu_init_crit
+
+relocate:
+	/*
+	 * relocate armboot to RAM
+	 */
+	adr	r0, _start		/* r0 <- current position of code */
+	ldr	r2, _armboot_start
+	ldr	r3, _armboot_end
+	sub	r2, r3, r2		/* r2 <- size of armboot */
+	ldr	r1, _TEXT_BASE		/* r1 <- destination address */
+	add	r2, r0, r2		/* r2 <- source end address */
+
+	/*
+	 * r0 = source address
+	 * r1 = target address
+	 * r2 = source end address
+	 */
+copy_loop:
+	ldmia	r0!, {r3-r10}
+	stmia	r1!, {r3-r10}
+	cmp	r0, r2
+	ble	copy_loop
+
+	/* set up the stack */
+	ldr	r0, _armboot_end
+	add	r0, r0, #CONFIG_STACKSIZE
+	sub	sp, r0, #12		/* leave 3 words for abort-stack */
+
+	ldr	pc, _start_armboot
+
+_start_armboot:	.word start_armboot
+
+
+/*
+ *************************************************************************
+ *
+ * CPU_init_critical registers
+ *
+ * setup important registers
+ * setup memory timing
+ *
+ *************************************************************************
+ */
+
+
+cpu_init_crit:
+	/*
+	 * flush v4 I/D caches
+	 */
+	mov	r0, #0
+	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
+	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */
+
+	/*
+	 * disable MMU stuff and caches
+	 */
+	mrc	p15, 0, r0, c1, c0, 0
+	bic	r0, r0, #0x00002300	@ clear bits 13, 9:8 (--V- --RS)
+	bic	r0, r0, #0x00000087	@ clear bits 7, 2:0 (B--- -CAM)
+	orr	r0, r0, #0x00000002	@ set bit 2 (A) Align
+	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-Cache
+	mcr	p15, 0, r0, c1, c0, 0
+
+	/*
+	 * Go setup Memory and board specific bits prior to relocation.
+	 */
+	mov	ip, lr          /* perserve link reg across call */
+	bl	platformsetup   /* go setup pll,mux,memory */
+	mov	lr, ip          /* restore link */
+	mov	pc, lr          /* back to my caller */
+/*
+ *************************************************************************
+ *
+ * Interrupt handling
+ *
+ *************************************************************************
+ */
+
+@
+@ IRQ stack frame.
+@
+#define S_FRAME_SIZE	72
+
+#define S_OLD_R0	68
+#define S_PSR		64
+#define S_PC		60
+#define S_LR		56
+#define S_SP		52
+
+#define S_IP		48
+#define S_FP		44
+#define S_R10		40
+#define S_R9		36
+#define S_R8		32
+#define S_R7		28
+#define S_R6		24
+#define S_R5		20
+#define S_R4		16
+#define S_R3		12
+#define S_R2		8
+#define S_R1		4
+#define S_R0		0
+
+#define MODE_SVC 0x13
+#define I_BIT	 0x80
+
+/*
+ * use bad_save_user_regs for abort/prefetch/undef/swi ...
+ * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
+ */
+
+	.macro	bad_save_user_regs
+	sub	sp, sp, #S_FRAME_SIZE           @ carve out a frame on current user stack
+	stmia	sp, {r0 - r12}			@ Save user registers (now in svc mode) r0-r12
+
+	ldr	r2, _armboot_end                @ find top of stack
+	add	r2, r2, #CONFIG_STACKSIZE       @ find base of normal stack
+	sub	r2, r2, #8                      @ set base 2 words into abort stack
+	ldmia	r2, {r2 - r3}                   @ get values for "aborted" pc and cpsr (into parm regs)
+	add	r0, sp, #S_FRAME_SIZE		@ grab pointer to old stack
+
+	add	r5, sp, #S_SP
+	mov	r1, lr
+	stmia	r5, {r0 - r3}                   @ save sp_SVC, lr_SVC, pc, cpsr
+	mov	r0, sp                          @ save current stack into r0 (param register)
+	.endm
+
+	.macro	irq_save_user_regs
+	sub	sp, sp, #S_FRAME_SIZE
+	stmia	sp, {r0 - r12}			@ Calling r0-r12
+	add     r8, sp, #S_PC                   @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
+	stmdb   r8, {sp, lr}^                   @ Calling SP, LR
+	str     lr, [r8, #0]                    @ Save calling PC
+	mrs     r6, spsr
+	str     r6, [r8, #4]                    @ Save CPSR
+	str     r0, [r8, #8]                    @ Save OLD_R0
+	mov	r0, sp
+	.endm
+
+	.macro	irq_restore_user_regs
+	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
+	mov	r0, r0
+	ldr	lr, [sp, #S_PC]			@ Get PC
+	add	sp, sp, #S_FRAME_SIZE
+	subs	pc, lr, #4			@ return & move spsr_svc into cpsr
+	.endm
+
+	.macro get_bad_stack
+	ldr	r13, _armboot_end		@ get bottom of stack (into sp by by user stack pointer).
+	add	r13, r13, #CONFIG_STACKSIZE	@ head to reserved words at the top of the stack
+	sub	r13, r13, #8                    @ reserved a couple spots in abort stack
+
+	str	lr, [r13]			@ save caller lr in position 0 of saved stack
+	mrs	lr, spsr                        @ get the spsr
+	str     lr, [r13, #4]                   @ save spsr in position 1 of saved stack
+
+	mov	r13, #MODE_SVC			@ prepare SVC-Mode
+	@ msr	spsr_c, r13
+	msr	spsr, r13                       @ switch modes, make sure moves will execute
+	mov	lr, pc                          @ capture return pc
+	movs	pc, lr                          @ jump to next instruction & switch modes.
+	.endm
+
+	.macro get_irq_stack			@ setup IRQ stack
+	ldr	sp, IRQ_STACK_START
+	.endm
+
+	.macro get_fiq_stack			@ setup FIQ stack
+	ldr	sp, FIQ_STACK_START
+	.endm
+
+/*
+ * exception handlers
+ */
+	.align  5
+undefined_instruction:
+	get_bad_stack
+	bad_save_user_regs
+	bl 	do_undefined_instruction
+
+	.align	5
+software_interrupt:
+	get_bad_stack
+	bad_save_user_regs
+	bl 	do_software_interrupt
+
+	.align	5
+prefetch_abort:
+	get_bad_stack
+	bad_save_user_regs
+	bl 	do_prefetch_abort
+
+	.align	5
+data_abort:
+	get_bad_stack
+	bad_save_user_regs
+	bl 	do_data_abort
+
+	.align	5
+not_used:
+	get_bad_stack
+	bad_save_user_regs
+	bl 	do_not_used
+
+#ifdef CONFIG_USE_IRQ
+
+	.align	5
+irq:
+	get_irq_stack
+	irq_save_user_regs
+	bl 	do_irq
+	irq_restore_user_regs
+
+	.align	5
+fiq:
+	get_fiq_stack
+	/* someone ought to write a more effiction fiq_save_user_regs */
+	irq_save_user_regs
+	bl 	do_fiq
+	irq_restore_user_regs
+
+#else
+
+	.align	5
+irq:
+	get_bad_stack
+	bad_save_user_regs
+	bl 	do_irq
+
+	.align	5
+fiq:
+	get_bad_stack
+	bad_save_user_regs
+	bl 	do_fiq
+
+#endif
+
+	.align	5
+.globl reset_cpu
+reset_cpu:
+	ldr	r1, rstctl1     /* get clkm1 reset ctl */
+	mov     r3, #0x3	/* dsp_en + arm_rst = global reset */
+	strh	r3, [r1]        /* force reset */
+	mov	r0, r0
+_loop_forever:
+	b	_loop_forever
+rstctl1:
+	.word	0xfffece10