Patch by Raghu Krishnaprasad, 7 Aug 2003:

add support for Adder II MPC852T module

CHANGELOG

@@ -1,5 +1,39 @@
 ======================================================================
-Changes for U-Boot 0.4.5:
+Changes for U-Boot 0.4.7:
+======================================================================
+
+* Patch by Raghu Krishnaprasad, 7 Aug 2003:
+  add support for Adder II MPC852T module
+
+* Patch by George G. Davis, 19 Aug 2003:
+  fix TI Innovator/OMAP1510 pin configs
+
+* Patches by Kshitij, 18 Aug 2003
+  - add support for arm926ejs cpu core
+  - add support for TI OMAP 1610 Innovator Board
+
+* Patch by Yuli Barcohen, 14 Aug 2003:
+  add support for bzip2 uncompression
+
+* Add GCC library to examples/Makefile so GCC utility functions will
+  be resolved, too
+
+* Add I2C and RTC support for RMU board using software I2C driver
+  (because of better response to iprobe command); fix problem with
+  "reset" command
+
+* Patch by Matthias Fuchs, 28 Aug 2003:
+  Added CONFIG_BOOTP_DNS2 and CONFIG_BOOTP_SEND_HOSTNAME to
+  CONFIG_BOOTP_MAKS (see README).
+
+* Fix ICU862 environment problem
+
+* Fix RAM size detection for RMU board
+
+* Implement "reset" for MGT5100/MPC5200 systems
+
+======================================================================
+Changes for U-Boot 0.4.6:
 ======================================================================
 
 * Make Ethernet autonegotiation on INCA-IP work for all clock rates;
@@ -14,6 +48,10 @@ Changes for U-Boot 0.4.5:
 * Patch by Richard Woodruff, 8 Aug 2003:
   Allow crc32 to be used at address 0x000 (crc32_no_comp, too).
 
+======================================================================
+Changes for U-Boot 0.4.5:
+======================================================================
+
 * Update for TQM board defaults:
   disable clocks_in_mhz, enable boot count limit
 
@@ -92,7 +130,7 @@ Changes for U-Boot 0.4.5:
   add delay to get I2C working with "imm" command and s3c24x0_i2c.c
 
 * Patch by Richard Woodruff, 17 July 03:
-  - Fixed bug in OMAP1510 baud rate divisor settings. 
+  - Fixed bug in OMAP1510 baud rate divisor settings.
 
 * Patch by Nye Liu, 16 July 2003:
   MPC860FADS fixes:

MAINTAINERS

@@ -278,6 +278,7 @@ Gary Jennejohn <gj@denx.de>
 
 Kshitij Gupta <kshitij@ti.com>
 	omap1510inn		ARM925T
+	omap1610inn		ARM926EJS
 
 David Müller <d.mueller@elsoft.ch>
 

MAKEALL

@@ -31,20 +31,21 @@ LIST_5xxx="	\
 #########################################################################
 
 LIST_8xx="	\
-	ADS860		AMX860		c2mon		CCM		\
-	cogent_mpc8xx	ESTEEM192E	ETX094		ELPT860		\
-	FADS823		FADS850SAR	FADS860T	FLAGADM		\
-	FPS850L		GEN860T		GEN860T_SC	GENIETV		\
-	GTH		hermes		IAD210		ICU862_100MHz	\
-	IP860		IVML24		IVML24_128	IVML24_256	\
-	IVMS8		IVMS8_128	IVMS8_256	KUP4K           \
-	LANTEC	        lwmon   	MBX		MBX860T		\
-	MHPC		MPC86xADS	MVS1		NETVIA		\
-	NETVIA_V2	NX823		pcu_e		R360MPI		\
-	RBC823		rmu		RPXClassic	RPXlite		\
-	RRvision	SM850		SPD823TS	svm_sc8xx	\
-	SXNI855T	TOP860		TQM823L		TQM823L_LCD	\
-	TQM850L		TQM855L		TQM860L		v37		\
+	AdderII		ADS860		AMX860		c2mon		\
+	CCM		cogent_mpc8xx	ESTEEM192E	ETX094		\
+	ELPT860		FADS823		FADS850SAR	FADS860T	\
+	FLAGADM		FPS850L		GEN860T		GEN860T_SC	\
+	GENIETV		GTH		hermes		IAD210		\
+	ICU862_100MHz	IP860		IVML24		IVML24_128	\
+	IVML24_256	IVMS8		IVMS8_128	IVMS8_256	\
+	KUP4K           LANTEC	        lwmon   	MBX		\
+	MBX860T		MHPC		MPC86xADS	MVS1		\
+	NETVIA		NETVIA_V2	NX823		pcu_e		\
+	R360MPI		RBC823		rmu		RPXClassic	\
+	RPXlite		RRvision	SM850		SPD823TS	\
+	svm_sc8xx	SXNI855T	TOP860		TQM823L		\
+	TQM823L_LCD	TQM850L		TQM855L		TQM860L		\
+	v37								\
 "
 
 #########################################################################
@@ -117,7 +118,11 @@ LIST_ARM7="ep7312 impa7"
 ## ARM9 Systems
 #########################################################################
 
-LIST_ARM9="at91rm9200dk omap1510inn smdk2400 smdk2410 trab VCMA9"
+LIST_ARM9="	\
+	at91rm9200dk	omap1510inn	omap1610inn			\
+	smdk2400	smdk2410	trab				\
+	VCMA9								\
+"
 
 #########################################################################
 ## Xscale Systems

Makefile

@@ -210,6 +210,9 @@ IceCube_5100_config:		unconfig
 ## MPC8xx Systems
 #########################################################################
 
+AdderII_config:	unconfig
+	@./mkconfig $(@:_config=) ppc mpc8xx adderII
+
 ADS860_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx fads
 
@@ -776,6 +779,9 @@ xtract_trab = $(subst _big_flash,,$(subst _config,,$1))
 omap1510inn_config :	unconfig
 	@./mkconfig $(@:_config=) arm arm925t omap1510inn
 
+omap1610inn_config :	unconfig
+	@./mkconfig $(@:_config=) arm arm926ejs omap1610inn
+
 smdk2400_config	:	unconfig
 	@./mkconfig $(@:_config=) arm arm920t smdk2400
 

README

@@ -141,6 +141,7 @@ Directory Hierarchy:
 
 - cpu/74xx_7xx	Files specific to Motorola MPC74xx and 7xx CPUs
 - cpu/arm925t	Files specific to ARM	   925	   CPUs
+- cpu/arm926ejs	Files specific to ARM	926	CPUs
 - cpu/mpc5xx	Files specific to Motorola MPC5xx  CPUs
 - cpu/mpc8xx	Files specific to Motorola MPC8xx  CPUs
 - cpu/mpc824x	Files specific to Motorola MPC824x CPUs
@@ -208,6 +209,8 @@ Directory Hierarchy:
 - board/oxc	Files specific to OXC        boards
 - board/omap1510inn
 		Files specific to OMAP 1510 Innovator boards
+- board/omap1610inn  
+		Files specific to OMAP 1610 Innovator boards
 - board/pcippc2	Files specific to PCIPPC2/PCIPPC6 boards
 - board/pm826	Files specific to PM826      boards
 - board/ppmc8260
@@ -357,7 +360,7 @@ The following options need to be configured:
 
 		CONFIG_HHP_CRADLE,  CONFIG_DNP1110,    CONFIG_EP7312,
 		CONFIG_IMPA7,       CONFIG_LART,       CONFIG_LUBBOCK,
-		CONFIG_INNOVATOROMAP1510,
+		CONFIG_INNOVATOROMAP1510,	CONFIG_INNOVATOROMAP1610
 		CONFIG_SHANNON,     CONFIG_SMDK2400,   CONFIG_SMDK2410,
 		CONFIG_TRAB,	    CONFIG_AT91RM9200DK
 
@@ -859,6 +862,16 @@ The following options need to be configured:
 		allows for a "silent" boot where a splash screen is
 		loaded very quickly after power-on.
 
+- Compression support:
+		CONFIG_BZIP2
+
+		If this option is set, support for bzip2 compressed
+		images is included. If not, only uncompressed and gzip
+		compressed images are supported.
+
+                NOTE: the bzip2 algorithm requires a lot of RAM, so
+                the malloc area (as defined by CFG_MALLOC_LEN) should
+                be at least 4MB.
 
 - Ethernet address:
 		CONFIG_ETHADDR
@@ -901,6 +914,29 @@ The following options need to be configured:
 		4th and following
 		BOOTP requests:		delay 0 ... 8 sec
 
+- DHCP Advanced Options:
+		CONFIG_BOOTP_MASK
+
+		You can fine tune the DHCP functionality by adding
+		these flags to the CONFIG_BOOTP_MASK define:
+
+		CONFIG_BOOTP_DNS2 - If a DHCP client requests the DNS
+		serverip from a DHCP server, it is possible that more
+		than one DNS serverip is offered to the client.
+		If CONFIG_BOOTP_DNS2 is enabled, the secondary DNS
+		serverip will be stored in the additional environment
+		variable "dnsip2". The first DNS serverip is always
+		stored in the variable "dnsip", when CONFIG_BOOTP_DNS
+		is added to the CONFIG_BOOTP_MASK.
+
+		CONFIG_BOOTP_SEND_HOSTNAME - Some DHCP servers are capable
+		to do a dynamic update of a DNS server. To do this, they
+		need the hostname of the DHCP requester.
+		If CONFIG_BOOP_SEND_HOSTNAME is added to the
+		CONFIG_BOOTP_MASK, the content of the "hostname"
+		environment variable is passed as option 12 to
+		the DHCP server.
+
 - Status LED:	CONFIG_STATUS_LED
 
 		Several configurations allow to display the current
@@ -1872,7 +1908,7 @@ configurations; the following names are supported:
     GEN860T_config	  EBONY_config		FPS860L_config
     ELPT860_config	  cmi_mpc5xx_config	NETVIA_config
     at91rm9200dk_config	  omap1510inn_config	MPC8260ADS_config
-
+    omap1610inn_config
 Note: for some board special configuration names may exist; check  if
       additional  information is available from the board vendor; for
       instance, the TQM8xxL systems run normally at 50 MHz and use  a
@@ -2118,6 +2154,7 @@ depending the information provided by your boot server:
 
   bootfile	- see above
   dnsip		- IP address of your Domain Name Server
+  dnsip2	- IP address of your secondary Domain Name Server
   gatewayip	- IP address of the Gateway (Router) to use
   hostname	- Target hostname
   ipaddr	- see above
@@ -2239,8 +2276,7 @@ defines the following image properties:
 * Target CPU Architecture (Provisions for Alpha, ARM, Intel x86,
   IA64, MIPS, MIPS, PowerPC, IBM S390, SuperH, Sparc, Sparc 64 Bit;
   Currently supported: PowerPC).
-* Compression Type (Provisions for uncompressed, gzip, bzip2;
-  Currently supported: uncompressed, gzip).
+* Compression Type (uncompressed, gzip, bzip2)
 * Load Address
 * Entry Point
 * Image Name

board/adderII/Makefile

@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################

board/adderII/adderII.c

@@ -0,0 +1,189 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#include <mpc8xx.h>
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard( void )
+{
+	puts("Board: ");
+	puts("AdderII(MPC852T)\n" );
+
+  	return 0;
+}
+
+#if defined( CONFIG_SDRAM_50MHZ )
+
+/******************************************************************************
+** for chip Samsung K4S643232F - T70
+** this table is for 32-50MHz operation
+*******************************************************************************/
+
+#define SDRAM_MPTPRVALUE 	0x0200
+
+#define SDRAM_MAMRVALUE0 	0x00802114   /* refresh at 32MHz */
+#define SDRAM_MAMRVALUE1 	0x00802118
+
+#define SDRAM_OR1VALUE   	0xff800e00
+#define SDRAM_BR1VALUE   	0x00000081
+
+#define SDRAM_MARVALUE		94
+
+#define SDRAM_MCRVALUE0  	0x80808105
+#define SDRAM_MCRVALUE1  	0x80808130
+
+const uint sdram_table[] = {
+
+	/* single read   (offset 0x00 in upm ram) */
+       	0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xe0bbbc00,
+       	0x10f77c44, 0xf3fffc07, 0xfffffc04, 0xfffffc04,
+
+	/* burst read    (offset 0x08 in upm ram) */
+       	0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xf0affc00,
+       	0xf0affc00, 0xf0affc00, 0xf0affc00, 0x10a77c44,
+       	0xf7bffc47, 0xfffffc35, 0xfffffc34, 0xfffffc35,
+       	0xfffffc35, 0x1ff77c35, 0xfffffc34, 0x1fb57c35,
+
+	/* single write  (offset 0x18 in upm ram) */
+       	0x1f27fc24, 0xe0aebc04, 0x00b93c00, 0x13f77c47,
+       	0xfffdfc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+
+	/* burst write   (offset 0x20 in upm ram) */
+       	0x1f07fc24, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
+       	0xf0affc00, 0xe0abbc00, 0x1fb77c47, 0xfffffc04,
+       	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+       	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+
+	/* refresh       (offset 0x30 in upm ram) */
+       	0x1ff5fca4, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+       	0xfffffc84, 0xfffffc07, 0xfffffc04, 0xfffffc04,
+       	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+
+	/* exception     (offset 0x3C in upm ram) */
+       	0xfffffc27, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+};
+
+#else
+#error SDRAM not correctly configured
+#endif
+
+int _initsdram (uint base, uint noMbytes)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	if (noMbytes != 8) {
+		return -1;
+	}
+
+	upmconfig (UPMA, (uint *) sdram_table,
+		   sizeof (sdram_table) / sizeof (uint));
+
+	memctl->memc_mptpr = SDRAM_MPTPRVALUE;
+
+	/* Configure the refresh (mostly).  This needs to be
+	 * based upon processor clock speed and optimized to provide
+	 * the highest level of performance.  For multiple banks,
+	 * this time has to be divided by the number of banks.
+	 * Although it is not clear anywhere, it appears the
+	 * refresh steps through the chip selects for this UPM
+	 * on each refresh cycle.
+	 * We have to be careful changing
+	 * UPM registers after we ask it to run these commands.
+	 */
+
+	memctl->memc_mamr = (SDRAM_MAMRVALUE0 | (SDRAM_MARVALUE << 24));
+	memctl->memc_mar = 0x0;
+	udelay (200);
+
+	/* Now run the precharge/nop/mrs commands.
+	 */
+	memctl->memc_mcr = 0x80002115;
+	udelay (200);
+
+	/* Run 8 refresh cycles */
+	memctl->memc_mcr = 0x80002380;
+	udelay (200);
+
+	memctl->memc_mar = 0x88;
+	udelay (200);
+
+	memctl->memc_mcr = 0x80002116;
+	udelay (200);
+
+	memctl->memc_or1 = SDRAM_OR1VALUE;
+	memctl->memc_br1 = SDRAM_BR1VALUE | base;
+
+	return 0;
+}
+
+void _sdramdisable( void )
+{
+	volatile immap_t     *immap = (immap_t *)CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	memctl->memc_br1 = 0x00000000;
+
+	/* maybe we should turn off upma here or something */
+}
+
+int initsdram (uint base, uint * noMbytes)
+{
+	uint m = 8;
+
+	*noMbytes = m;
+
+	if (!_initsdram (base, m)) {
+		return 0;
+	} else {
+		_sdramdisable ();
+		return -1;
+	}
+}
+
+long int initdram (int board_type)
+{
+	/* AdderII: has 8MB SDRAM */
+	uint sdramsz;
+	uint m = 0;
+
+	if (!initsdram (0x00000000, &sdramsz)) {
+		m += sdramsz;
+	} else {
+		return -1;
+	}
+	return (m << 20);
+}
+
+int testdram (void)
+{
+	/* TODO: XXX XXX XXX not an actual SDRAM test */
+	printf ("Test: 8MB SDRAM\n");
+
+	return (0);
+}

board/adderII/adderII.h

@@ -0,0 +1,45 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/****************************************************************************
+ * FLASH Memory Map as used by FADS Monitor:
+ *
+ *                          Start Address    Length
+ * +-----------------------+ 0xFE00_0000     Start of Flash -----------------
+ * | MON8xx code           | 0xFE00_0100     Reset Vector
+ * +-----------------------+ 0xFE0?_????
+ * | (unused)              |
+ * +-----------------------+
+ * | 			   |
+ * +-----------------------+
+ * | 			   |
+ * +-----------------------+
+ * | 			   |
+ * +-----------------------+
+ * | 			   |
+ * +=======================+
+ * | 			   |
+ * | ...                   |
+ *****************************************************************************/
+
+

board/adderII/config.mk

@@ -0,0 +1,29 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# AdderII board ( Analogue-Micro )
+#
+
+TEXT_BASE = 0xFE000000
+

board/adderII/flash.c

@@ -0,0 +1,501 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+/******************************************************************************
+** Notes: AM29LV320DB - 90EI ( 32 Mbit device )
+** Sectors - Eight 8 Kb sector
+** 	   - Sixty three 64 Kb sector
+** Bottom boot sector
+******************************************************************************/
+#include <common.h>
+#include <mpc8xx.h>
+
+
+/******************************************************************************
+**	Defines
+******************************************************************************/
+#ifdef CONFIG_ADDERII
+
+#define ADDR0	0x0555
+#define ADDR1	0x02AA
+#define FLASH_WORD_SIZE unsigned short
+
+#endif
+
+#if defined( CFG_ENV_IS_IN_FLASH )
+# ifndef  CFG_ENV_ADDR
+#  define CFG_ENV_ADDR  ( CFG_FLASH_BASE + CFG_ENV_OFFSET )
+# endif
+# ifndef  CFG_ENV_SIZE
+#  define CFG_ENV_SIZE  CFG_ENV_SECT_SIZE
+# endif
+# ifndef  CFG_ENV_SECT_SIZE
+#  define CFG_ENV_SECT_SIZE  CFG_ENV_SIZE
+# endif
+#endif
+
+/******************************************************************************
+**	Global Parameters
+******************************************************************************/
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+/******************************************************************************
+**	Function Prototypes
+******************************************************************************/
+static ulong flash_get_size( vu_long *addr, flash_info_t *info );
+
+static int write_word( flash_info_t *info, ulong dest, ulong data );
+
+static void flash_get_offsets( ulong base, flash_info_t *info );
+
+int wait_for_DQ7( flash_info_t *info, int sect );
+
+/******************************************************************************
+** Function :	flash_init
+** Param    :   void
+** Notes    :   Initializes the Flash Chip
+******************************************************************************/
+ulong flash_init (void)
+{
+	ulong size_b0 = -1;
+	int i;
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	/* Set Flash to unknown */
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Get the Flash Bank Size */
+
+	size_b0 = flash_get_size ((vu_long *) (CFG_FLASH_BASE),
+				  &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## UNKNOWN Flash on Bank 0 - Size = 0x%08lx = %ldMB\n",
+			size_b0, size_b0 >> 20);
+	}
+
+	/* Remap Flash according to size detected  */
+	memctl->memc_or0 = 0xFF800774;
+	memctl->memc_br0 = CFG_BR0_PRELIM;
+
+	/* Setup Flash Sector Offsets */
+
+	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+
+	/* Monitor Protection ON - default */
+
+#if ( CFG_MONITOR_BASE >= CFG_FLASH_BASE  )
+	flash_protect (FLAG_PROTECT_SET, CFG_MONITOR_BASE,
+		       (CFG_MONITOR_BASE + monitor_flash_len - 1),
+		       &flash_info[0]);
+#endif
+
+	/* Protect Environment Variables */
+#ifdef CFG_ENV_IS_IN_FLASH
+	flash_protect (FLAG_PROTECT_SET, CFG_ENV_ADDR,
+		       (CFG_ENV_ADDR + CFG_ENV_SIZE - 1), &flash_info[0]);
+#endif
+
+	return size_b0;
+}
+
+/******************************************************************************
+** Function : flash_get_offsets
+** Param    : ulong base, flash_into_t *info
+** Notes    :
+******************************************************************************/
+static void flash_get_offsets (ulong base, flash_info_t * info)
+{
+	return;
+}
+
+
+/******************************************************************************
+** Function : flash_print_info
+** Param    : flash_info_t
+** Notes    :
+******************************************************************************/
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("Missing or unknown flash type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:
+		printf ("AMD ");
+		break;
+	case FLASH_MAN_FUJ:
+		printf ("FUJITSU ");
+		break;
+	case FLASH_MAN_BM:
+		printf ("BRIGHT MICRO ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM320B:
+		printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM320T:
+		printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n", info->size >> 20,
+		info->sector_count);
+	printf ("  Sector Start Addresses:");
+
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+/******************************************************************************
+** Function : flash_get_size
+** Param    : vu_long *addr, flash_info_t *info
+** Notes    :
+******************************************************************************/
+static ulong flash_get_size (vu_long * addr, flash_info_t * info)
+{
+	short i;
+	FLASH_WORD_SIZE manu_id, dev_id;
+	ulong base = (ulong) addr;
+	volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) addr;
+
+	/* Write Auto Select Command and read Manufacturer's ID and Dev ID */
+
+	addr2[ADDR0] = (FLASH_WORD_SIZE) 0xAAAAAAAA;
+	addr2[ADDR1] = (FLASH_WORD_SIZE) 0x55555555;
+	addr2[ADDR0] = (FLASH_WORD_SIZE) 0x90909090;
+
+	manu_id = addr2[0];
+
+	switch (manu_id) {
+	case (FLASH_WORD_SIZE) AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		break;
+	}
+
+	/* Read Device Id */
+	dev_id = addr2[1];
+
+	switch (dev_id) {
+	case (FLASH_WORD_SIZE) AMD_ID_LV320B:
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 71;	/* 8 - boot sec + 63 normal */
+		info->size = 0x400000;	/* 4MByte */
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	/* Set up sector start Addresses */
+
+	if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block
+		 ** Eight 8 Kb Boot sectors
+		 ** Sixty Three 64Kb sectors
+		 */
+		for (i = 0; i < 8; i++) {
+			info->start[i] = base + (i * 0x00002000);
+		}
+		for (i = 8; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000) - 0x00070000;
+		}
+	}
+
+	/* Reset To read mode */
+
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr = (ulong *) info->start[0];
+		*addr = 0xF0F0F0F0;
+	}
+	return (info->size);
+}
+
+/*******************************************************************************
+** Function : flash_erase
+** Param    : flash_info_t *info, int s_first, int s_last
+** Notes    :
+******************************************************************************/
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]);
+	volatile FLASH_WORD_SIZE *addr2;
+	int flag, prot, sect, l_sect;
+	int i;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr2 = (FLASH_WORD_SIZE *) (info->start[sect]);
+
+			if ((info->flash_id & FLASH_VENDMASK) ==
+			    FLASH_MAN_SST) {
+				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080;
+				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+				addr2[0] = (FLASH_WORD_SIZE) 0x00500050;	/* block erase */
+				for (i = 0; i < 50; i++)
+					udelay (1000);	/* wait 1 ms */
+			} else {
+				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080;
+				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+				addr2[0] = (FLASH_WORD_SIZE) 0x00300030;	/* sector erase */
+			}
+			l_sect = sect;
+			/*
+			 * Wait for each sector to complete, it's more
+			 * reliable.  According to AMD Spec, you must
+			 * issue all erase commands within a specified
+			 * timeout.  This has been seen to fail, especially
+			 * if printf()s are included (for debug)!!
+			 */
+			wait_for_DQ7 (info, sect);
+		}
+	}
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/* reset to read mode */
+	addr = (FLASH_WORD_SIZE *) info->start[0];
+	addr[0] = (FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
+
+	printf (" done\n");
+	return 0;
+}
+
+int wait_for_DQ7 (flash_info_t * info, int sect)
+{
+	ulong start, now, last;
+	volatile FLASH_WORD_SIZE *addr =
+		(FLASH_WORD_SIZE *) (info->start[sect]);
+
+	start = get_timer (0);
+	last = start;
+	while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) !=
+	       (FLASH_WORD_SIZE) 0x00800080) {
+		if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return -1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {
+			putc ('.');
+			last = now;
+		}
+	}
+	return 0;
+}
+
+
+/******************************************************************************
+** Function : write_buff
+** Param    : flash_info_t *info, uchar *src, ulong addr, ulong cnt
+** Notes    :
+******************************************************************************/
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	/* get lower word aligned address */
+	wp = (addr & ~3);
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < 4 && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < 4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i = 0; i < 4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < 4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_word (info, wp, data));
+}
+
+
+/******************************************************************************
+** Function : write_word
+** Param    : flash_info_t *info, ulong dest, ulong data
+** Notes    :
+******************************************************************************/
+static int write_word (flash_info_t * info, ulong dest, ulong data)
+{
+	volatile FLASH_WORD_SIZE *addr2 =
+		(FLASH_WORD_SIZE *) (info->start[0]);
+	volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest;
+	volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data;
+	ulong start;
+	int i;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((volatile FLASH_WORD_SIZE *) dest) &
+	     (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
+		return (2);
+	}
+
+	for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) {
+		int flag;
+
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts ();
+
+		addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+		addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+		addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0;
+
+		dest2[i] = data2[i];
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts ();
+
+		/* data polling for D7 */
+		start = get_timer (0);
+		while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) !=
+		       (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) {
+			if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+				return (1);
+			}
+		}
+	}
+
+	return (0);
+}

board/adderII/u-boot.lds

@@ -0,0 +1,147 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o	(.text)
+/*
+    cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_ppc/ppcstring.o	(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_generic/zlib.o		(.text)
+
+    . = env_offset;
+    common/environment.o(.text)
+*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  . = ALIGN(256 * 1024);
+  .ppcenv	:
+  {
+    common/environment.o (.ppcenv)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
+

board/icecube/icecube.c

@@ -25,6 +25,7 @@
 #include <mpc5xxx.h>
 #include <pci.h>
 
+#ifndef CFG_RAMBOOT
 static long int dram_size(long int *base, long int maxsize)
 {
 	volatile long int *addr;
@@ -86,11 +87,14 @@ static void sdram_start (int hi_addr)
 	/* normal operation */
 	*(vu_long *)MPC5XXX_SDRAM_CTRL = 0x504f0000 | hi_addr_bit;
 }
+#endif
 
 long int initdram (int board_type)
 {
-	ulong test1, test2, dramsize = 0;
+	ulong dramsize = 0;
 #ifndef CFG_RAMBOOT
+	ulong test1, test2;
+
 	/* configure SDRAM start/end */
 #if defined(CONFIG_MPC5200)
 	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
@@ -133,8 +137,11 @@ long int initdram (int board_type)
 #else
 #ifdef CONFIG_MGT5100
 	*(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
+	dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
+#else
+	dramsize = ((1 << (*(vu_long *)MPC5XXX_SDRAM_CS0CFG - 0x13)) << 20);
 #endif
-#endif
+#endif /* CFG_RAMBOOT */
 	/* return total ram size */
 	return dramsize;
 }

board/icu862/u-boot.lds

@@ -136,11 +136,6 @@ SECTIONS
    *(.bss)
    *(COMMON)
   }
-  . = ALIGN(256 * 1024);
-  .ppcenv	:
-  {
-    common/environment.o (.ppcenv)
-  }
   _end = . ;
   PROVIDE (end = .);
 }

board/omap1510inn/platform.S

@@ -84,6 +84,9 @@ platformsetup:
 	ldr     r0, REG_FUNC_MUX_CTRL_C
 	ldr     r1, VAL_FUNC_MUX_CTRL_C
 	str     r1, [r0]
+	ldr     r0, REG_FUNC_MUX_CTRL_D
+	ldr     r1, VAL_FUNC_MUX_CTRL_D
+	str     r1, [r0]
 	ldr     r0, REG_VOLTAGE_CTRL_0
 	ldr     r1, VAL_VOLTAGE_CTRL_0
 	str     r1, [r0]
@@ -352,9 +355,9 @@ VAL_PULL_DWN_CTRL_0:
 VAL_PULL_DWN_CTRL_1:
 	.word 0x2e047fff
 VAL_PULL_DWN_CTRL_2:
-	.word 0xffd7d3e6
+	.word 0xffd603a6
 VAL_PULL_DWN_CTRL_3:
-	.word 0x00003f03
+	.word 0x00003e03
 VAL_VOLTAGE_CTRL_0:
 	.word 0x00000007
 VAL_TEST_DBG_CTRL_0:

board/omap1610inn/Makefile

@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= omap1610innovator.o flash.o
+SOBJS	:= platform.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################

board/omap1610inn/config.mk

@@ -0,0 +1,26 @@
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+#
+# (C) Copyright 2003
+# Texas Instruments, <www.ti.com>
+# Kshitij Gupta <Kshitij@ti.com>
+#
+# TI Innovator board with OMAP1610 (ARM925EJS) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# Innovator has 1 bank of 256 MB SDRAM
+# Physical Address:
+# 1000'0000 to 2000'0000
+#
+#
+# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000
+# (mem base + reserved)
+#
+# we load ourself to 1100'0000
+#
+#
+
+
+TEXT_BASE = 0x11000000

board/omap1610inn/flash.c

@@ -0,0 +1,482 @@
+/*
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+
+#define PHYS_FLASH_SECT_SIZE	0x00020000	/* 256 KB sectors (x2) */
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+
+/* Board support for 1 or 2 flash devices */
+#undef FLASH_PORT_WIDTH32
+#define FLASH_PORT_WIDTH16
+
+#ifdef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH		ushort
+#define FLASH_PORT_WIDTHV		vu_short
+#define SWAP(x)			__swab16(x)
+#else
+#define FLASH_PORT_WIDTH		ulong
+#define FLASH_PORT_WIDTHV		vu_long
+#define SWAP(x)			__swab32(x)
+#endif
+
+#define FPW	FLASH_PORT_WIDTH
+#define FPWV	FLASH_PORT_WIDTHV
+
+#define mb() __asm__ __volatile__ ("" : : : "memory")
+
+
+
+/* Flash Organization Structure */
+typedef struct OrgDef {
+	unsigned int sector_number;
+	unsigned int sector_size;
+} OrgDef;
+
+
+/* Flash Organizations */
+OrgDef OrgIntel_28F256L18T[] = {
+	{4, 32 * 1024},				/* 4 * 32kBytes sectors */
+	{255, 128 * 1024},			/* 255 * 128kBytes sectors */
+};
+
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+unsigned long flash_init (void);
+static ulong flash_get_size (FPW * addr, flash_info_t * info);
+static int write_data (flash_info_t * info, ulong dest, FPW data);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+void inline spin_wheel (void);
+void flash_print_info (flash_info_t * info);
+void flash_unprotect_sectors (FPWV * addr);
+int flash_erase (flash_info_t * info, int s_first, int s_last);
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	int i;
+	ulong size = 0;
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		switch (i) {
+		case 0:
+			flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
+			flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
+			break;
+		default:
+			panic ("configured to many flash banks!\n");
+			break;
+		}
+		size += flash_info[i].size;
+	}
+
+	/* Protect monitor and environment sectors
+	 */
+	flash_protect (FLAG_PROTECT_SET,
+			CFG_FLASH_BASE,
+			CFG_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]);
+
+	flash_protect (FLAG_PROTECT_SET,
+			CFG_ENV_ADDR,
+			CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t * info)
+{
+	int i;
+	OrgDef *pOrgDef;
+
+	pOrgDef = OrgIntel_28F256L18T;
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			if (i > 255) {
+				info->start[i] = base + (i * 0x8000);
+				info->protect[i] = 0;
+			} else {
+				info->start[i] = base +
+						(i * PHYS_FLASH_SECT_SIZE);
+				info->protect[i] = 0;
+			}
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F256L18T:
+		printf ("FLASH 28F256L18T\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i], info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (FPW * addr, flash_info_t * info)
+{
+	volatile FPW value;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x5555] = (FPW) 0x00AA00AA;
+	addr[0x2AAA] = (FPW) 0x00550055;
+	addr[0x5555] = (FPW) 0x00900090;
+
+	mb ();
+	value = addr[0];
+
+	switch (value) {
+
+	case (FPW) INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+		return (0);		/* no or unknown flash  */
+	}
+
+	mb ();
+	value = addr[1];	/* device ID        */
+	switch (value) {
+
+	case (FPW) (INTEL_ID_28F256L18T):
+		info->flash_id += FLASH_28F256L18T;
+		info->sector_count = 259;
+		info->size = 0x02000000;
+		break;			/* => 32 MB     */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+				info->sector_count, CFG_MAX_FLASH_SECT);
+		info->sector_count = CFG_MAX_FLASH_SECT;
+	}
+
+	addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (info->size);
+}
+
+
+
+
+/* unprotects a sector for write and erase
+ * on some intel parts, this unprotects the entire chip, but it
+ * wont hurt to call this additional times per sector...
+ */
+void flash_unprotect_sectors (FPWV * addr)
+{
+#define PD_FINTEL_WSMS_READY_MASK    0x0080
+
+	*addr = (FPW) 0x00500050;	/* clear status register */
+
+	/* this sends the clear lock bit command */
+	*addr = (FPW) 0x00600060;
+	*addr = (FPW) 0x00D000D0;
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong type, start, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+				info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+				prot);
+	} else {
+		printf ("\n");
+	}
+
+
+
+
+	start = get_timer (0);
+	last = start;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			FPWV *addr = (FPWV *) (info->start[sect]);
+			FPW status;
+
+			printf ("Erasing sector %2d ... ", sect);
+
+			flash_unprotect_sectors (addr);
+
+			/* arm simple, non interrupt dependent timer */
+			reset_timer_masked ();
+
+			*addr = (FPW) 0x00500050;/* clear status register */
+			*addr = (FPW) 0x00200020;/* erase setup */
+			*addr = (FPW) 0x00D000D0;/* erase confirm */
+
+			while (((status =
+				*addr) & (FPW) 0x00800080) !=
+				(FPW) 0x00800080) {
+					if (get_timer_masked () > 
+					CFG_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					/* suspend erase     */
+					*addr = (FPW) 0x00B000B0;
+					/* reset to read mode */
+					*addr = (FPW) 0x00FF00FF;
+					rcode = 1;
+					break;
+				}
+			}
+
+			/* clear status register cmd.   */
+			*addr = (FPW) 0x00500050;
+			*addr = (FPW) 0x00FF00FF;/* resest to read mode */
+			printf (" done\n");
+		}
+	}
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	FPW data;
+	int count, i, l, rc, port_width;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+/* get lower word aligned address */
+#ifdef FLASH_PORT_WIDTH16
+	wp = (addr & ~1);
+	port_width = 2;
+#else
+	wp = (addr & ~3);
+	port_width = 4;
+#endif
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < port_width && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < port_width; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	count = 0;
+	while (cnt >= port_width) {
+		data = 0;
+		for (i = 0; i < port_width; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+		cnt -= port_width;
+		if (count++ > 0x800) {
+			spin_wheel ();
+			count = 0;
+		}
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < port_width; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_data (info, wp, SWAP (data)));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t * info, ulong dest, FPW data)
+{
+	FPWV *addr = (FPWV *) dest;
+	ulong status;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr);
+		return (2);
+	}
+	flash_unprotect_sectors (addr);
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+	*addr = (FPW) 0x00400040;	/* write setup */
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();
+
+	/* wait while polling the status register */
+	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+		if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+			return (1);
+		}
+	}
+	*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+	return (0);
+}
+
+void inline spin_wheel (void)
+{
+	static int p = 0;
+	static char w[] = "\\/-";
+
+	printf ("\010%c", w[p]);
+	(++p == 3) ? (p = 0) : 0;
+}

board/omap1610inn/omap1610innovator.c

@@ -0,0 +1,270 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#if defined(CONFIG_OMAP1610)
+#include <./configs/omap1510.h>
+#endif
+
+void flash__init (void);
+void ether__init (void);
+void set_muxconf_regs (void);
+void peripheral_power_enable (void);
+
+#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
+
+static inline void delay (unsigned long loops)
+{
+	__asm__ volatile ("1:\n"
+		"subs %0, %1, #1\n"
+		"bne 1b":"=r" (loops):"0" (loops));
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* arch number of OMAP 1510-Board */
+	/* to be changed for OMAP 1610 Board */
+	gd->bd->bi_arch_number = 234;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0x10000100;
+
+	/* Configure MUX settings */
+	set_muxconf_regs ();
+	peripheral_power_enable ();
+
+/* this speeds up your boot a quite a bit.  However to make it
+ *  work, you need make sure your kernel startup flush bug is fixed.
+ *  ... rkw ...
+ */
+	icache_enable ();
+
+	flash__init ();
+	ether__init ();
+	return 0;
+}
+
+
+int misc_init_r (void)
+{
+	/* currently empty */
+	return (0);
+}
+
+/******************************
+ Routine:
+ Description:
+******************************/
+void flash__init (void)
+{
+#define EMIFS_GlB_Config_REG 0xfffecc0c
+	unsigned int regval;
+	regval = *((volatile unsigned int *) EMIFS_GlB_Config_REG);
+	/* Turn off write protection for flash devices. */
+	regval = regval | 0x0001;
+	*((volatile unsigned int *) EMIFS_GlB_Config_REG) = regval;
+}
+/*************************************************************
+ Routine:ether__init
+ Description: take the Ethernet controller out of reset and wait
+	  		   for the EEPROM load to complete.
+*************************************************************/
+void ether__init (void)
+{
+#define ETH_CONTROL_REG 0x0400000b
+
+	*((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01;
+	udelay (3);
+}
+
+/******************************
+ Routine:
+ Description:
+******************************/
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+/******************************************************
+ Routine: set_muxconf_regs
+ Description: Setting up the configuration Mux registers
+ 			  specific to the hardware
+*******************************************************/
+void set_muxconf_regs (void)
+{
+	volatile unsigned int *MuxConfReg;
+	/* set each registers to its reset value; */
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_0);
+	/* setup for UART1 */
+	*MuxConfReg &= ~(0x02000000);	/* bit 25 */
+	/* setup for UART2 */
+	*MuxConfReg &= ~(0x01000000);	/* bit 24 */
+	/* Disable Uwire CS Hi-Z */
+	*MuxConfReg |= 0x08000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_3);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_4);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_5);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_6);
+	/*setup mux for UART3 */
+	*MuxConfReg |= 0x00000001;	/* bit3, 1, 0 (mux0 5,5,26) */
+	*MuxConfReg &= ~0x0000003e;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_7);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_8);
+	/* Disable Uwire CS Hi-Z */
+	*MuxConfReg |= 0x00001200;	/*bit 9 for CS0 12 for CS3 */
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_9);
+	/*  Need to turn on bits 21 and 12 in FUNC_MUX_CTRL_9 so the  */
+	/*  hardware will actually use TX and RTS based on bit 25 in  */
+	/*  FUNC_MUX_CTRL_0.  I told you this thing was screwy!  */
+	*MuxConfReg |= 0x00201000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_A);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_B);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_C);
+	/* setup for UART2 */
+	/*  Need to turn on bits 27 and 24 in FUNC_MUX_CTRL_C so the  */
+	/*  hardware will actually use TX and RTS based on bit 24 in  */
+	/*  FUNC_MUX_CTRL_0. */
+	*MuxConfReg |= 0x09000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_0);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_1);
+	*MuxConfReg = 0x00000000;
+	/* mux setup for SD/MMC driver */
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_2);
+	*MuxConfReg &= 0xFFFE0FFF;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_3);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0);
+	/* bit 13 for MMC2 XOR_CLK */
+	*MuxConfReg &= ~(0x00002000);
+	/* bit 29 for UART 1 */
+	*MuxConfReg &= ~(0x00002000);
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_0);
+	/* Configure for USB. Turn on VBUS_CTRL and VBUS_MODE. */
+	*MuxConfReg |= 0x000C0000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int)USB_TRANSCEIVER_CTRL);
+	*MuxConfReg &= ~(0x00000070);
+	*MuxConfReg &= ~(0x00000008);
+	*MuxConfReg |= 0x00000003;
+	*MuxConfReg |= 0x00000180;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0);
+	/* bit 17, software controls VBUS */
+	*MuxConfReg &= ~(0x00020000);
+	/* Enable USB 48 and 12M clocks */
+	*MuxConfReg |= 0x00000200;
+	*MuxConfReg &= ~(0x00000180);
+	/*2.75V for MMCSDIO1 */
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) VOLTAGE_CTRL_0);
+	*MuxConfReg = 0x00001FE7;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PU_PD_SEL_0);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PU_PD_SEL_1);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PU_PD_SEL_2);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PU_PD_SEL_3);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PU_PD_SEL_4);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_4);
+	*MuxConfReg = 0x00000000;
+	/* Turn on UART2 48 MHZ clock */
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0);
+	*MuxConfReg |= 0x40000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) USB_OTG_CTRL);
+	/* setup for USB VBus detection OMAP161x */
+	*MuxConfReg |= 0x00040000;	/* bit 18 */
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PU_PD_SEL_2);
+	/* PullUps for SD/MMC driver */
+	*MuxConfReg |= ~(0xFFFE0FFF);
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int)COMP_MODE_CTRL_0);
+	*MuxConfReg = COMP_MODE_ENABLE;
+}
+
+/******************************************************
+ Routine: peripheral_power_enable
+ Description: Enable the power for UART1
+*******************************************************/
+void peripheral_power_enable (void)
+{
+#define UART1_48MHZ_ENABLE	((unsigned short)0x0200)
+#define SW_CLOCK_REQUEST	((volatile unsigned short *)0xFFFE0834)
+
+	*SW_CLOCK_REQUEST |= UART1_48MHZ_ENABLE;
+}

board/omap1610inn/platform.S

@@ -0,0 +1,385 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+#if defined(CONFIG_OMAP1610)
+#include <./configs/omap1510.h>
+#endif
+
+
+_TEXT_BASE:
+	.word	TEXT_BASE	/* sdram load addr from config.mk */
+
+.globl platformsetup
+platformsetup:
+
+
+	/*------------------------------------------------------*
+	 * Set up ARM CLM registers (IDLECT1)                   *
+	 *------------------------------------------------------*/
+	ldr	r0,	REG_ARM_IDLECT1
+	ldr	r1,	VAL_ARM_IDLECT1
+	str	r1,	[r0]
+
+	/*------------------------------------------------------*
+	 * Set up ARM CLM registers (IDLECT2)  		        *
+	 *------------------------------------------------------*/
+	ldr	r0,	REG_ARM_IDLECT2
+	ldr	r1,	VAL_ARM_IDLECT2
+	str	r1,	[r0]
+
+	/*------------------------------------------------------*
+	 * Set up ARM CLM registers (IDLECT3)		        *
+	 *------------------------------------------------------*/
+	ldr	r0,	REG_ARM_IDLECT3
+	ldr	r1,	VAL_ARM_IDLECT3
+	str	r1,	[r0]
+
+
+	mov	r1,	#0x01		/* PER_EN bit */
+	ldr	r0,	REG_ARM_RSTCT2
+	strh	r1,	[r0]		/* CLKM; Peripheral reset. */
+
+	/* Set CLKM to Sync-Scalable	*/
+	/* I supposedly need to enable the dsp clock before switching */
+	mov	r1,	#0x0000
+	ldr	r0,	REG_ARM_SYSST
+	strh	r1,	[r0]
+	mov	r0,	#0x400
+1:
+	subs	r0,	r0,	#0x1	/* wait for any bubbles to finish */
+	bne	1b
+	ldr	r1,	VAL_ARM_CKCTL
+	ldr	r0,	REG_ARM_CKCTL
+	strh	r1,	[r0]
+
+	/* a few nops to let settle */
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+
+	/* setup DPLL 1 */
+	/* Ramp up the clock to 96Mhz */
+	ldr	r1,	VAL_DPLL1_CTL
+	ldr	r0,	REG_DPLL1_CTL
+	strh	r1,	[r0]
+	ands	r1,	r1,	#0x10	/* Check if PLL is enabled. */
+	beq	lock_end	/* Do not look for lock if BYPASS selected */
+2:
+	ldrh	r1,	[r0]
+	ands	r1,	r1,	#0x01	/*	Check the LOCK bit.*/
+	beq 2b			/*	loop until bit goes hi. */
+lock_end:
+
+
+	/*------------------------------------------------------*
+	 * Turn off the watchdog during init...			*
+ 	 *------------------------------------------------------*/
+	ldr	r0,	REG_WATCHDOG
+	ldr	r1,	WATCHDOG_VAL1
+	str	r1,	[r0]
+	ldr	r1,	WATCHDOG_VAL2
+	str	r1,	[r0]
+	ldr	r0,	REG_WSPRDOG
+	ldr	r1,	WSPRDOG_VAL1
+	str	r1,	[r0]
+	ldr	r0,	REG_WWPSDOG
+
+watch1Wait:
+	ldr	r1,	[r0]
+	tst	r1,	#0x10
+	bne	watch1Wait
+
+	ldr	r0,	REG_WSPRDOG
+	ldr	r1,	WSPRDOG_VAL2
+	str	r1,	[r0]
+	ldr	r0,	REG_WWPSDOG
+watch2Wait:
+	ldr	r1,	[r0]
+	tst	r1,	#0x10
+	bne	watch2Wait
+
+
+
+
+	/* Set memory timings corresponding to the new clock speed */
+
+	/* Check execution location to determine current execution location
+	 * and branch to appropriate initialization code.
+	 */
+	/* Load physical SDRAM base. */
+	mov 	r0, 	#0x10000000
+	/* Get current execution location. */
+	mov 	r1, 	pc
+	/* Compare. */
+	cmp 	r1, 	r0
+	/* Skip over EMIF-fast initialization if running from SDRAM. */
+	bge 	skip_sdram
+
+	/*
+	* Delay for SDRAM initialization.
+	*/
+	mov	r3,	#0x1800		/* value should be checked */
+3:
+	subs	r3,	r3,	#0x1	/* Decrement count */
+	bne 	3b
+
+
+	/*
+	 * Set SDRAM control values. Disable refresh before MRS command.
+	 */
+
+	/* mobile ddr operation */
+	ldr	r0,	REG_SDRAM_OPERATION
+	mov	r2,	#07
+	str	r2,	[r0]
+
+	/* config register */
+	ldr	r0,	REG_SDRAM_CONFIG
+	ldr	r1,	SDRAM_CONFIG_VAL
+	str	r1,	[r0]
+
+	/* manual command register */
+	ldr	r0,	REG_SDRAM_MANUAL_CMD
+	/* issue set cke high */
+	mov	r1,	#CMD_SDRAM_CKE_SET_HIGH
+	str	r1,	[r0]
+	/* issue nop */
+	mov	r1,	#CMD_SDRAM_NOP
+	str	r1,	[r0]
+
+	mov	r2,	#0x0100
+waitMDDR1:
+	subs	r2,	r2,	 #1
+	bne	waitMDDR1	/* delay loop */
+
+	/* issue precharge */
+	mov	r1,	#CMD_SDRAM_PRECHARGE
+	str	r1,	[r0]
+
+	/* issue autorefresh x 2 */
+	mov	r1,	#CMD_SDRAM_AUTOREFRESH
+	str	r1,	[r0]
+	str	r1,	[r0]
+
+	/* mrs register ddr mobile */
+	ldr	r0,	REG_SDRAM_MRS
+	mov	r1,	#0x33
+	str	r1,	[r0]
+
+	/* emrs1 low-power register */
+	ldr	r0,	REG_SDRAM_EMRS1
+	/* self refresh on all banks */
+	mov	r1,	#0
+	str	r1,	[r0]
+
+	ldr	r0,	REG_DLL_URD_CONTROL
+	ldr	r1,	DLL_URD_CONTROL_VAL
+	str	r1,	[r0]
+
+	ldr	r0,	REG_DLL_LRD_CONTROL
+	ldr	r1,	DLL_LRD_CONTROL_VAL
+	str	r1,	[r0]
+
+	ldr	r0,	REG_DLL_WRT_CONTROL
+	ldr	r1,	DLL_WRT_CONTROL_VAL
+	str	r1,	[r0]
+
+	/* delay loop */
+	mov	r2,	#0x0100
+waitMDDR2:
+	subs	r2,	r2,	#1
+	bne	waitMDDR2
+
+	/*
+	 * Delay for SDRAM initialization.
+	 */
+	mov	r3,	#0x1800
+4:
+	subs	r3,	r3,	#1	/* Decrement count. */
+	bne	4b
+	b	common_tc
+
+skip_sdram:
+
+	ldr	r0,	REG_SDRAM_CONFIG
+	ldr	r1,	SDRAM_CONFIG_VAL
+	str	r1,	[r0]
+
+common_tc:
+	/* slow interface */
+	ldr	r1,	VAL_TC_EMIFS_CS0_CONFIG
+	ldr	r0,	REG_TC_EMIFS_CS0_CONFIG
+	str	r1,	[r0] /* Chip Select 0 */
+
+	ldr	r1,	VAL_TC_EMIFS_CS1_CONFIG
+	ldr	r0,	REG_TC_EMIFS_CS1_CONFIG
+	str	r1,	[r0] /* Chip Select 1 */
+	ldr	r1,	VAL_TC_EMIFS_CS3_CONFIG
+	ldr	r0,	REG_TC_EMIFS_CS3_CONFIG
+	str	r1,	[r0] /* Chip Select 3 */
+	/* back to arch calling code */
+	mov	pc,	lr
+
+	/* the literal pools origin */
+	.ltorg
+
+
+REG_TC_EMIFS_CONFIG:		/* 32 bits */
+	.word 0xfffecc0c
+REG_TC_EMIFS_CS0_CONFIG:	/* 32 bits */
+	.word 0xfffecc10
+REG_TC_EMIFS_CS1_CONFIG:	/* 32 bits */
+	.word 0xfffecc14
+REG_TC_EMIFS_CS2_CONFIG:	/* 32 bits */
+	.word 0xfffecc18
+REG_TC_EMIFS_CS3_CONFIG:	/* 32 bits */
+	.word 0xfffecc1c
+
+/* MPU clock/reset/power mode control registers */
+REG_ARM_CKCTL:			/* 16 bits */
+	.word 0xfffece00
+
+REG_ARM_IDLECT3:		/* 16 bits */
+	.word 0xfffece24
+REG_ARM_IDLECT2:		/* 16 bits */
+	.word 0xfffece08        
+REG_ARM_IDLECT1:		/* 16 bits */
+	.word 0xfffece04
+
+REG_ARM_RSTCT2:			/* 16 bits */
+	.word 0xfffece14
+REG_ARM_SYSST:			/* 16 bits */
+	.word 0xfffece18
+/* DPLL control registers */
+REG_DPLL1_CTL:			/* 16 bits */
+	.word 0xfffecf00
+
+/* Watch Dog register */
+/* secure watchdog stop */
+REG_WSPRDOG:
+	.word 0xfffeb048
+/* watchdog write pending */
+REG_WWPSDOG:
+	.word 0xfffeb034 
+
+WSPRDOG_VAL1:
+	.word 0x0000aaaa
+WSPRDOG_VAL2:
+	.word 0x00005555
+
+/* SDRAM config is: auto refresh enabled, 16 bit 4 bank,
+ counter @8192 rows, 10 ns, 8 burst */
+REG_SDRAM_CONFIG:
+	.word 0xfffecc20
+
+/* Operation register */
+REG_SDRAM_OPERATION:
+	.word 0xfffecc80
+
+/* Manual command register */
+REG_SDRAM_MANUAL_CMD:
+	.word 0xfffecc84
+
+/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
+REG_SDRAM_MRS:
+	.word 0xfffecc70
+
+/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
+REG_SDRAM_EMRS1:
+	.word 0xfffecc78
+
+/* WRT DLL register */
+REG_DLL_WRT_CONTROL:
+	.word 0xfffecc68
+DLL_WRT_CONTROL_VAL:
+	.word 0x03f00002
+
+/* URD DLL register */
+REG_DLL_URD_CONTROL:
+	.word 0xfffeccc0
+DLL_URD_CONTROL_VAL:
+	.word 0x00800002
+
+/* LRD DLL register */
+REG_DLL_LRD_CONTROL:
+	.word 0xfffecccc
+
+REG_WATCHDOG:
+	.word 0xfffec808
+
+/* 96 MHz Samsung Mobile DDR */
+SDRAM_CONFIG_VAL:
+	.word 0x001200f4 
+
+DLL_LRD_CONTROL_VAL:
+	.word 0x00800002
+
+VAL_ARM_CKCTL:
+	.word 0x3000
+VAL_DPLL1_CTL:
+	.word 0x2830
+
+VAL_TC_EMIFS_CS0_CONFIG:
+	.word 0x002130b0
+VAL_TC_EMIFS_CS1_CONFIG:
+	.word 0x00001131
+VAL_TC_EMIFS_CS2_CONFIG:
+	.word 0x000055f0
+VAL_TC_EMIFS_CS3_CONFIG:
+	.word 0x88011131
+VAL_TC_EMIFF_SDRAM_CONFIG:
+	.word 0x010290fc
+VAL_TC_EMIFF_MRS:
+	.word 0x00000027
+
+VAL_ARM_IDLECT1:
+	.word 0x00000400
+
+VAL_ARM_IDLECT2:
+	.word 0x00000886
+VAL_ARM_IDLECT3:
+	.word 0x00000015
+
+WATCHDOG_VAL1:
+	.word 0x000000f5
+WATCHDOG_VAL2:
+	.word 0x000000a0
+
+/* command values */
+.equ CMD_SDRAM_NOP,		0x00000000
+.equ CMD_SDRAM_PRECHARGE,	0x00000001
+.equ CMD_SDRAM_AUTOREFRESH,	0x00000002
+.equ CMD_SDRAM_CKE_SET_HIGH,	0x00000007

board/omap1610inn/u-boot.lds

@@ -0,0 +1,51 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+	. = ALIGN(4);
+	.text	:
+	{
+	  cpu/arm926ejs/start.o	(.text)
+	  *(.text)
+	}
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+	. = ALIGN(4);
+	.data : { *(.data) }
+	. = ALIGN(4);
+	.got : { *(.got) }
+	
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+	
+	armboot_end_data = .;
+	. = ALIGN(4);
+	.bss : { *(.bss) }
+	armboot_end = .;
+}

board/rmu/rmu.c

@@ -96,7 +96,7 @@ long int initdram (int board_type)
 {
     volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
     volatile memctl8xx_t *memctl = &immap->im_memctl;
-    long int size10 ;
+    long int size9 ;
 
     upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
 
@@ -109,7 +109,7 @@ long int initdram (int board_type)
     memctl->memc_or1 = CFG_OR1_PRELIM;
     memctl->memc_br1 = CFG_BR1_PRELIM;
 
-    memctl->memc_mamr = CFG_MAMR_10COL & (~(MAMR_PTAE)); /* no refresh yet */
+    memctl->memc_mamr = CFG_MAMR_9COL & (~(MAMR_PTAE)); /* no refresh yet */
 
     udelay(200);
 
@@ -122,13 +122,20 @@ long int initdram (int board_type)
 
     udelay (1000);
 
-	/* Check Bank 0 Memory Size
-	 * try 10 column mode
+	/* Check Bank 0 Memory Size,
+	 * 9 column mode
 	 */
 
-	size10 = dram_size (CFG_MAMR_10COL, (ulong *)SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE) ;
+	size9 = dram_size (CFG_MAMR_9COL, (ulong *)SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE) ;
 
-    return (size10);
+	/*
+	 * Final mapping:
+	 */
+
+	memctl->memc_or1 = ((-size9) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
+	udelay (1000);
+
+    return (size9);
 }
 
 /* ------------------------------------------------------------------------- */

board/tqm8xx/Makefile

@@ -1,5 +1,5 @@
 #
-# (C) Copyright 2000
+# (C) Copyright 2000-2003
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # See file CREDITS for list of people who contributed to this

common/cmd_bootm.c

@@ -30,6 +30,7 @@
 #include <image.h>
 #include <malloc.h>
 #include <zlib.h>
+#include <bzlib.h>
 #include <environment.h>
 #include <asm/byteorder.h>
 
@@ -142,6 +143,7 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	ulong	addr;
 	ulong	data, len, checksum;
 	ulong  *len_ptr;
+	uint	unc_len = 0x400000;
 	int	i, verify;
 	char	*name, *s;
 	int	(*appl)(cmd_tbl_t *, int, int, char *[]);
@@ -307,13 +309,26 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 		break;
 	case IH_COMP_GZIP:
 		printf ("   Uncompressing %s ... ", name);
-		if (gunzip ((void *)ntohl(hdr->ih_load), 0x400000,
+		if (gunzip ((void *)ntohl(hdr->ih_load), unc_len,
 			    (uchar *)data, (int *)&len) != 0) {
 			printf ("GUNZIP ERROR - must RESET board to recover\n");
 			SHOW_BOOT_PROGRESS (-6);
 			do_reset (cmdtp, flag, argc, argv);
 		}
 		break;
+#ifdef CONFIG_BZIP2
+	case IH_COMP_BZIP2:
+		printf ("   Uncompressing %s ... ", name);
+		i = BZ2_bzBuffToBuffDecompress ((char*)ntohl(hdr->ih_load),
+						&unc_len, (char *)data, len, 0, 0);
+		if (i != BZ_OK) {
+			printf ("BUNZIP2 ERROR %d - must RESET board to recover\n", i);
+			SHOW_BOOT_PROGRESS (-6);
+			udelay(100000);
+			do_reset (cmdtp, flag, argc, argv);
+		}
+		break;
+#endif /* CONFIG_BZIP2 */
 	default:
 		if (iflag)
 			enable_interrupts();
@@ -1206,6 +1221,13 @@ int gunzip(void *dst, int dstlen, unsigned char *src, int *lenp)
 	return (0);
 }
 
+#ifdef CONFIG_BZIP2
+void bz_internal_error(int errcode)
+{
+	printf ("BZIP2 internal error %d\n", errcode);
+}
+#endif /* CONFIG_BZIP2 */
+
 static void
 do_bootm_rtems (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[],
 		ulong addr, ulong *len_ptr, int verify)

common/cmd_net.c

@@ -116,6 +116,13 @@ static void netboot_update_env(void)
 	setenv("dnsip", tmp);
     }
 
+#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_DNS2)
+    if (NetOurDNS2IP) {
+	    ip_to_string (NetOurDNS2IP, tmp);
+	    setenv("dnsip2", tmp);
+    }
+#endif
+
     if (NetOurNISDomain[0])
 	setenv("domain", NetOurNISDomain);
 

cpu/arm926ejs/Makefile

@@ -0,0 +1,43 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(CPU).a
+
+START	= start.o
+OBJS	= interrupts.o cpu.o
+
+all:	.depend $(START) $(LIB)
+
+$(LIB):	$(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(START:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################

cpu/arm926ejs/config.mk

@@ -0,0 +1,27 @@
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+PLATFORM_RELFLAGS += -fno-strict-aliasing  -fno-common -ffixed-r8 \
+	-mshort-load-bytes -msoft-float
+
+PLATFORM_CPPFLAGS += -mapcs-32 -march=armv4

cpu/arm926ejs/cpu.c

@@ -0,0 +1,159 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * CPU specific code
+ */
+
+#include <common.h>
+#include <command.h>
+#include <arm926ejs.h>
+
+/* read co-processor 15, register #1 (control register) */
+static unsigned long read_p15_c1 (void)
+{
+	unsigned long value;
+
+	__asm__ __volatile__(
+		"mrc	p15, 0, %0, c1, c0, 0   @ read control reg\n"
+		: "=r" (value)
+		:
+		: "memory");
+
+#ifdef MMU_DEBUG
+	printf ("p15/c1 is = %08lx\n", value);
+#endif
+	return value;
+}
+
+/* write to co-processor 15, register #1 (control register) */
+static void write_p15_c1 (unsigned long value)
+{
+#ifdef MMU_DEBUG
+	printf ("write %08lx to p15/c1\n", value);
+#endif
+	__asm__ __volatile__(
+		"mcr	p15, 0, %0, c1, c0, 0   @ write it back\n"
+		:
+		: "r" (value)
+		: "memory");
+
+	read_p15_c1 ();
+}
+
+static void cp_delay (void)
+{
+	volatile int i;
+
+	/* Many OMAP regs need at least 2 nops  */
+	for (i = 0; i < 100; i++);
+}
+
+/* See also ARM Ref. Man. */
+#define C1_MMU		(1<<0)		/* mmu off/on */
+#define C1_ALIGN	(1<<1)		/* alignment faults off/on */
+#define C1_DC		(1<<2)		/* dcache off/on */
+#define C1_WB		(1<<3)		/* merging write buffer on/off */
+#define C1_BIG_ENDIAN	(1<<7)	/* big endian off/on */
+#define C1_SYS_PROT	(1<<8)		/* system protection */
+#define C1_ROM_PROT	(1<<9)		/* ROM protection */
+#define C1_IC		(1<<12)		/* icache off/on */
+#define C1_HIGH_VECTORS	(1<<13)	/* location of vectors: low/high addresses */
+#define RESERVED_1	(0xf << 3)	/* must be 111b for R/W */
+
+int cpu_init (void)
+{
+	/*
+	 * setup up stack if necessary
+	 */
+#ifdef CONFIG_USE_IRQ
+	IRQ_STACK_START = _armboot_end +
+			CONFIG_STACKSIZE + CONFIG_STACKSIZE_IRQ - 4;
+	FIQ_STACK_START = IRQ_STACK_START + CONFIG_STACKSIZE_FIQ;
+	_armboot_real_end = FIQ_STACK_START + 4;
+#else
+	_armboot_real_end = _armboot_end + CONFIG_STACKSIZE;
+#endif	/* CONFIG_USE_IRQ */
+	return (0);
+}
+
+int cleanup_before_linux (void)
+{
+	/*
+	 * this function is called just before we call linux
+	 * it prepares the processor for linux
+	 *
+	 * we turn off caches etc ...
+	 */
+
+	unsigned long i;
+
+	disable_interrupts ();
+
+	/* turn off I/D-cache */
+	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+	i &= ~(C1_DC | C1_IC);
+	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+
+	/* flush I/D-cache */
+	i = 0;
+	asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));
+	return (0);
+}
+
+int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	extern void reset_cpu (ulong addr);
+
+	disable_interrupts ();
+	reset_cpu (0);
+	/*NOTREACHED*/
+	return (0);
+}
+
+void icache_enable (void)
+{
+	ulong reg;
+
+	reg = read_p15_c1 ();		/* get control reg. */
+	cp_delay ();
+	write_p15_c1 (reg | C1_IC);
+}
+
+void icache_disable (void)
+{
+	ulong reg;
+
+	reg = read_p15_c1 ();
+	cp_delay ();
+	write_p15_c1 (reg & ~C1_IC);
+}
+
+int icache_status (void)
+{
+	return (read_p15_c1 () & C1_IC) != 0;
+}

cpu/arm926ejs/interrupts.c

@@ -0,0 +1,293 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <arm925t.h>
+#include <configs/omap1510.h>
+
+#include <asm/proc-armv/ptrace.h>
+
+extern void reset_cpu(ulong addr);
+#define TIMER_LOAD_VAL 0xffffffff
+
+/* macro to read the 32 bit timer */
+#define READ_TIMER (*(volatile ulong *)(CFG_TIMERBASE+8))
+
+#ifdef CONFIG_USE_IRQ
+/* enable IRQ interrupts */
+void enable_interrupts (void)
+{
+	unsigned long temp;
+	__asm__ __volatile__("mrs %0, cpsr\n"
+		"bic %0, %0, #0x80\n"
+		"msr cpsr_c, %0"
+		: "=r" (temp)
+		: "memory");
+}
+
+/*
+ * disable IRQ/FIQ interrupts
+ * returns true if interrupts had been enabled before we disabled them
+ */
+int disable_interrupts (void)
+{
+	unsigned long old,temp;
+	__asm__ __volatile__("mrs %0, cpsr\n"
+		"orr %1, %0, #0xc0\n"
+		"msr cpsr_c, %1"
+		: "=r" (old), "=r" (temp)
+		: "memory");
+	return (old & 0x80) == 0;
+}
+#else
+void enable_interrupts (void)
+{
+	return;
+}
+int disable_interrupts (void)
+{
+	return 0;
+}
+#endif
+
+
+
+void bad_mode (void)
+{
+	panic ("Resetting CPU ...\n");
+	reset_cpu (0);
+}
+
+void show_regs (struct pt_regs *regs)
+{
+	unsigned long flags;
+	const char *processor_modes[] = {
+	"USER_26",	"FIQ_26",	"IRQ_26",	"SVC_26",
+	"UK4_26",	"UK5_26",	"UK6_26",	"UK7_26",
+	"UK8_26",	"UK9_26",	"UK10_26",	"UK11_26",
+	"UK12_26",	"UK13_26",	"UK14_26",	"UK15_26",
+	"USER_32",	"FIQ_32",	"IRQ_32",	"SVC_32",
+	"UK4_32",	"UK5_32",	"UK6_32",	"ABT_32",
+	"UK8_32",	"UK9_32",	"UK10_32",	"UND_32",
+	"UK12_32",	"UK13_32",	"UK14_32",	"SYS_32",
+	};
+
+	flags = condition_codes (regs);
+
+	printf ("pc : [<%08lx>]    lr : [<%08lx>]\n"
+		"sp : %08lx  ip : %08lx  fp : %08lx\n",
+		instruction_pointer (regs),
+		regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp);
+	printf ("r10: %08lx  r9 : %08lx  r8 : %08lx\n",
+		regs->ARM_r10, regs->ARM_r9, regs->ARM_r8);
+	printf ("r7 : %08lx  r6 : %08lx  r5 : %08lx  r4 : %08lx\n",
+		regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4);
+	printf ("r3 : %08lx  r2 : %08lx  r1 : %08lx  r0 : %08lx\n",
+		regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0);
+	printf ("Flags: %c%c%c%c",
+		flags & CC_N_BIT ? 'N' : 'n',
+		flags & CC_Z_BIT ? 'Z' : 'z',
+		flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v');
+	printf ("  IRQs %s  FIQs %s  Mode %s%s\n",
+		interrupts_enabled (regs) ? "on" : "off",
+		fast_interrupts_enabled (regs) ? "on" : "off",
+		processor_modes[processor_mode (regs)],
+		thumb_mode (regs) ? " (T)" : "");
+}
+
+void do_undefined_instruction (struct pt_regs *pt_regs)
+{
+	printf ("undefined instruction\n");
+	show_regs (pt_regs);
+	bad_mode ();
+}
+
+void do_software_interrupt (struct pt_regs *pt_regs)
+{
+	printf ("software interrupt\n");
+	show_regs (pt_regs);
+	bad_mode ();
+}
+
+void do_prefetch_abort (struct pt_regs *pt_regs)
+{
+	printf ("prefetch abort\n");
+	show_regs (pt_regs);
+	bad_mode ();
+}
+
+void do_data_abort (struct pt_regs *pt_regs)
+{
+	printf ("data abort\n");
+	show_regs (pt_regs);
+	bad_mode ();
+}
+
+void do_not_used (struct pt_regs *pt_regs)
+{
+	printf ("not used\n");
+	show_regs (pt_regs);
+	bad_mode ();
+}
+
+void do_fiq (struct pt_regs *pt_regs)
+{
+	printf ("fast interrupt request\n");
+	show_regs (pt_regs);
+	bad_mode ();
+}
+
+void do_irq (struct pt_regs *pt_regs)
+{
+	printf ("interrupt request\n");
+	show_regs (pt_regs);
+	bad_mode ();
+}
+
+static ulong timestamp;
+static ulong lastdec;
+
+/* nothing really to do with interrupts, just starts up a counter. */
+int interrupt_init (void)
+{
+	int32_t val;
+
+	*((int32_t *) (CFG_TIMERBASE + LOAD_TIM)) = TIMER_LOAD_VAL;
+	val = MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE |
+			(CFG_PVT << MPUTIM_PTV_BIT);
+	*((int32_t *) (CFG_TIMERBASE + CNTL_TIMER)) = val;
+	return (0);
+}
+
+/*
+ * timer without interrupts
+ */
+
+void reset_timer (void)
+{
+	reset_timer_masked ();
+}
+
+ulong get_timer (ulong base)
+{
+	return get_timer_masked () - base;
+}
+
+void set_timer (ulong t)
+{
+	timestamp = t;
+}
+
+/* very rough timer... */
+void udelay (unsigned long usec)
+{
+#ifdef CONFIG_INNOVATOROMAP1610
+#define LOOPS_PER_MSEC 100		/* tuned on omap1610 */
+	volatile int i, time_remaining = LOOPS_PER_MSEC * usec;
+
+	for (i = time_remaining; i > 0; i--) {
+	}
+#else
+
+	ulong tmo;
+	tmo = usec / 1000;
+	tmo *= CFG_HZ;
+	tmo /= 1000;
+	tmo += get_timer (0);
+	while (get_timer_masked () < tmo)
+		/*NOP*/;
+#endif
+}
+
+void reset_timer_masked (void)
+{
+	/* reset time */
+	lastdec = READ_TIMER;
+	timestamp = 0;
+}
+
+ulong get_timer_masked (void)
+{
+	ulong now = READ_TIMER;		/* current tick value */
+
+	if (lastdec >= now) {		/* did I roll (rem decrementer) */
+		/* normal mode */
+		/* record amount of time since last check */
+		timestamp += lastdec - now;
+	} else {
+		/* we have an overflow ... */
+		timestamp += lastdec + TIMER_LOAD_VAL - now;
+	}
+	lastdec = now;
+
+	return timestamp;
+}
+
+void udelay_masked (unsigned long usec)
+{
+#ifdef CONFIG_INNOVATOROMAP1610
+	#define LOOPS_PER_MSEC 100 /* tuned on omap1610 */
+	volatile int i, time_remaining = LOOPS_PER_MSEC*usec;
+	for (i=time_remaining; i>0; i--) { }
+#else
+
+	ulong tmo;
+
+	tmo = usec / 1000;
+	tmo *= CFG_HZ;
+	tmo /= 1000;
+
+	reset_timer_masked ();
+
+	while (get_timer_masked () < tmo)
+		/*NOP*/;
+#endif
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk (void)
+{
+	ulong tbclk;
+	tbclk = CFG_HZ;
+	return tbclk;
+}

cpu/arm926ejs/start.S

@@ -0,0 +1,426 @@
+/*
+ *  armboot - Startup Code for ARM926EJS CPU-core
+ *
+ *  Copyright (c) 2003  Texas Instruments
+ *
+ *  ----- Adapted for OMAP1610 from ARM925t code ------
+ *
+ *  Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
+ *  Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
+ *  Copyright (c) 2002	Gary Jennejohn <gj@denx.de>
+ *  Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
+ *  Copyright (c) 2003	Kshitij <kshitij@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+
+#include <config.h>
+#include <version.h>
+
+#if defined(CONFIG_OMAP1610)
+#include <./configs/omap1510.h>
+#endif
+
+/*
+ *************************************************************************
+ *
+ * Jump vector table as in table 3.1 in [1]
+ *
+ *************************************************************************
+ */
+
+
+.globl _start
+_start:
+	b	reset
+	ldr	pc, _undefined_instruction
+	ldr	pc, _software_interrupt
+	ldr	pc, _prefetch_abort
+	ldr	pc, _data_abort
+	ldr	pc, _not_used
+	ldr	pc, _irq
+	ldr	pc, _fiq
+
+_undefined_instruction:
+	.word undefined_instruction
+_software_interrupt:
+	.word software_interrupt
+_prefetch_abort:
+	.word prefetch_abort
+_data_abort:
+	.word data_abort
+_not_used:
+	.word not_used
+_irq:
+	.word irq
+_fiq:
+	.word fiq
+
+	.balignl 16,0xdeadbeef
+
+
+/*
+ *************************************************************************
+ *
+ * Startup Code (reset vector)
+ *
+ * do important init only if we don't start from memory!
+ * setup Memory and board specific bits prior to relocation.
+ * relocate armboot to ram
+ * setup stack
+ *
+ *************************************************************************
+ */
+
+/*
+ * CFG_MEM_END is in the board dependent config-file (configs/config_BOARD.h)
+ */
+_TEXT_BASE:
+	.word	TEXT_BASE
+
+.globl _armboot_start
+_armboot_start:
+	.word _start
+
+/*
+ * Note: _armboot_end_data and _armboot_end are defined
+ * by the (board-dependent) linker script.
+ * _armboot_end_data is the first usable FLASH address after armboot
+ */
+.globl _armboot_end_data
+_armboot_end_data:
+	.word armboot_end_data
+.globl _armboot_end
+_armboot_end:
+	.word armboot_end
+
+/*
+ * _armboot_real_end is the first usable RAM address behind armboot
+ * and the various stacks
+ */
+.globl _armboot_real_end
+_armboot_real_end:
+	.word 0x0badc0de
+
+#ifdef CONFIG_USE_IRQ
+/* IRQ stack memory (calculated at run-time) */
+.globl IRQ_STACK_START
+IRQ_STACK_START:
+	.word	0x0badc0de
+
+/* IRQ stack memory (calculated at run-time) */
+.globl FIQ_STACK_START
+FIQ_STACK_START:
+	.word 0x0badc0de
+#endif
+
+
+/*
+ * the actual reset code
+ */
+
+reset:
+	/*
+	 * set the cpu to SVC32 mode
+	 */
+	mrs	r0,cpsr
+	bic	r0,r0,#0x1f
+	orr	r0,r0,#0xd3
+	msr	cpsr,r0
+
+
+	/* 
+	 * turn off the watchdog, unlock/diable sequence
+	 */
+	mov	r1, #0xF5
+	ldr	r0, =WDTIM_MODE
+	strh	r1, [r0]
+	mov	r1, #0xA0
+	strh	r1, [r0]
+
+
+
+
+
+	/*
+	 * mask all IRQs by setting all bits in the INTMR - default
+	 */
+
+	mov	r1, #0xffffffff
+	ldr	r0, =REG_IHL1_MIR
+	str	r1, [r0]
+	ldr	r0, =REG_IHL2_MIR
+	str	r1, [r0]
+	bl	cpu_init_crit
+
+relocate:
+	/*
+	 * relocate armboot to RAM
+	 */
+	adr	r0, _start		/* r0 <- current position of code */
+	ldr	r2, _armboot_start
+	ldr	r3, _armboot_end
+	sub	r2, r3, r2		/* r2 <- size of armboot */
+	ldr	r1, _TEXT_BASE		/* r1 <- destination address */
+	add	r2, r0, r2		/* r2 <- source end address */
+
+	/*
+	 * r0 = source address
+	 * r1 = target address
+	 * r2 = source end address
+	 */
+copy_loop:
+	ldmia	r0!, {r3-r10}
+	stmia	r1!, {r3-r10}
+	cmp	r0, r2
+	ble	copy_loop
+
+	/* set up the stack */
+	ldr	r0, _armboot_end
+	add	r0, r0, #CONFIG_STACKSIZE
+	sub	sp, r0, #12		/* leave 3 words for abort-stack */
+
+	ldr	pc, _start_armboot
+
+_start_armboot:
+	.word start_armboot
+
+
+/*
+ *************************************************************************
+ *
+ * CPU_init_critical registers
+ *
+ * setup important registers
+ * setup memory timing
+ *
+ *************************************************************************
+ */
+
+
+cpu_init_crit:
+	/*
+	 * flush v4 I/D caches
+	 */
+	mov	r0, #0
+	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
+	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */
+
+	/*
+	 * disable MMU stuff and caches
+	 */
+	mrc	p15, 0, r0, c1, c0, 0
+	bic	r0, r0, #0x00002300	/* clear bits 13, 9:8 (--V- --RS) */
+	bic	r0, r0, #0x00000087	/* clear bits 7, 2:0 (B--- -CAM) */
+	orr	r0, r0, #0x00000002	/* set bit 2 (A) Align */
+	orr	r0, r0, #0x00001000	/* set bit 12 (I) I-Cache */
+	mcr	p15, 0, r0, c1, c0, 0
+
+	/*
+	 * Go setup Memory and board specific bits prior to relocation.
+	 */
+	mov	ip, lr		/* perserve link reg across call */
+	bl	platformsetup	/* go setup pll,mux,memory */
+	mov	lr, ip		/* restore link */
+	mov	pc, lr		/* back to my caller */
+/*
+ *************************************************************************
+ *
+ * Interrupt handling
+ *
+ *************************************************************************
+ */
+
+@
+@ IRQ stack frame.
+@
+#define S_FRAME_SIZE	72
+
+#define S_OLD_R0	68
+#define S_PSR		64
+#define S_PC		60
+#define S_LR		56
+#define S_SP		52
+
+#define S_IP		48
+#define S_FP		44
+#define S_R10		40
+#define S_R9		36
+#define S_R8		32
+#define S_R7		28
+#define S_R6		24
+#define S_R5		20
+#define S_R4		16
+#define S_R3		12
+#define S_R2		8
+#define S_R1		4
+#define S_R0		0
+
+#define MODE_SVC 0x13
+#define I_BIT	 0x80
+
+/*
+ * use bad_save_user_regs for abort/prefetch/undef/swi ...
+ * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
+ */
+
+	.macro	bad_save_user_regs
+	@ carve out a frame on current user stack
+	sub	sp, sp, #S_FRAME_SIZE
+	stmia	sp, {r0 - r12}	@ Save user registers (now in svc mode) r0-r12
+	ldr	r2, _armboot_end	@ find top of stack
+	add	r2, r2, #CONFIG_STACKSIZE	@ find base of normal stack
+	sub	r2, r2, #8	@ set base 2 words into abort stack
+	@ get values for "aborted" pc and cpsr (into parm regs)
+	ldmia	r2, {r2 - r3}
+	add	r0, sp, #S_FRAME_SIZE		@ grab pointer to old stack
+	add	r5, sp, #S_SP
+	mov	r1, lr
+	stmia	r5, {r0 - r3}	@ save sp_SVC, lr_SVC, pc, cpsr
+	mov	r0, sp		@ save current stack into r0 (param register)
+	.endm
+
+	.macro	irq_save_user_regs
+	sub	sp, sp, #S_FRAME_SIZE
+	stmia	sp, {r0 - r12}			@ Calling r0-r12
+	@ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
+	add	r8, sp, #S_PC
+	stmdb	r8, {sp, lr}^		@ Calling SP, LR
+	str	lr, [r8, #0]		@ Save calling PC
+	mrs	r6, spsr
+	str	r6, [r8, #4]		@ Save CPSR
+	str	r0, [r8, #8]		@ Save OLD_R0
+	mov	r0, sp
+	.endm
+
+	.macro	irq_restore_user_regs
+	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
+	mov	r0, r0
+	ldr	lr, [sp, #S_PC]			@ Get PC
+	add	sp, sp, #S_FRAME_SIZE
+	subs	pc, lr, #4		@ return & move spsr_svc into cpsr
+	.endm
+
+	.macro get_bad_stack
+	@ get bottom of stack (into sp by by user stack pointer).
+	ldr	r13, _armboot_end
+	@ head to reserved words at the top of the stack
+	add	r13, r13, #CONFIG_STACKSIZE
+	sub	r13, r13, #8	@ reserved a couple spots in abort stack
+
+	str	lr, [r13]	@ save caller lr in position 0 of saved stack
+	mrs	lr, spsr	@ get the spsr
+	str	lr, [r13, #4]	@ save spsr in position 1 of saved stack
+	mov	r13, #MODE_SVC	@ prepare SVC-Mode
+	@ msr	spsr_c, r13
+	msr	spsr, r13	@ switch modes, make sure moves will execute
+	mov	lr, pc		@ capture return pc
+	movs	pc, lr		@ jump to next instruction & switch modes.
+	.endm
+
+	.macro get_irq_stack			@ setup IRQ stack
+	ldr	sp, IRQ_STACK_START
+	.endm
+
+	.macro get_fiq_stack			@ setup FIQ stack
+	ldr	sp, FIQ_STACK_START
+	.endm
+
+/*
+ * exception handlers
+ */
+	.align  5
+undefined_instruction:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_undefined_instruction
+
+	.align	5
+software_interrupt:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_software_interrupt
+
+	.align	5
+prefetch_abort:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_prefetch_abort
+
+	.align	5
+data_abort:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_data_abort
+
+	.align	5
+not_used:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_not_used
+
+#ifdef CONFIG_USE_IRQ
+
+	.align	5
+irq:
+	get_irq_stack
+	irq_save_user_regs
+	bl 	do_irq
+	irq_restore_user_regs
+
+	.align	5
+fiq:
+	get_fiq_stack
+	/* someone ought to write a more effiction fiq_save_user_regs */
+	irq_save_user_regs
+	bl 	do_fiq
+	irq_restore_user_regs
+
+#else
+
+	.align	5
+irq:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_irq
+
+	.align	5
+fiq:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_fiq
+
+#endif
+
+	.align	5
+.globl reset_cpu
+reset_cpu:
+	ldr	r1, rstctl1	/* get clkm1 reset ctl */
+	mov	r3, #0x0	
+	strh	r3, [r1]	/* clear it */
+	mov	r3, #0x8
+	strh	r3, [r1]	/* force dsp+arm reset */
+_loop_forever:
+	b	_loop_forever
+
+
+rstctl1:
+	.word	0xfffece10

cpu/mpc5xxx/cpu.c

@@ -54,31 +54,17 @@ int checkcpu (void)
 int
 do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 {
-	ulong msr, addr;
-
-	*(vu_long *)MPC5XXX_CDM_SRESET &= ~(1 << 16);	/* Checkstop Reset enable */
-
+	ulong msr;
 	/* Interrupts and MMU off */
 	__asm__ __volatile__ ("mfmsr    %0":"=r" (msr):);
 
 	msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
 	__asm__ __volatile__ ("mtmsr    %0"::"r" (msr));
 
-	/*
-	 * Trying to execute the next instruction at a non-existing address
-	 * should cause a machine check, resulting in reset
-	 */
-#ifdef CFG_RESET_ADDRESS
-	addr = CFG_RESET_ADDRESS;
-#else
-	/*
-	 * note: when CFG_MONITOR_BASE points to a RAM address, CFG_MONITOR_BASE
-	 * - sizeof (ulong) is usually a valid address. Better pick an address
-	 * known to be invalid on your system and assign it to CFG_RESET_ADDRESS.
-	 */
-	addr = CFG_MONITOR_BASE - sizeof (ulong);
-#endif
-	((void (*)(void)) addr) ();
+	/* Charge the watchdog timer */
+	*(vu_long *)(MPC5XXX_GPT0_COUNTER) = 0xf;
+	*(vu_long *)(MPC5XXX_GPT0_ENABLE) = 0x9004; /* wden|ce|timer_ms */
+
 	return 1;
 
 }

cpu/mpc8xx/cpu.c

@@ -98,6 +98,7 @@ static int check_CPU (long clock, uint pvr, uint immr)
 	case 0x00310065: mid = "SR"; suf = "C1"; m = 1; break;
 	case 0x05010000: suf = "D3"; m = 1; break;
 	case 0x05020000: suf = "D4"; m = 1; break;
+	case 0x08000003: suf = ""; m = 1; break;
 		/* this value is not documented anywhere */
 	case 0x40000000: pre = 'P'; suf = "D"; m = 1; break;
 #endif

cpu/mpc8xx/cpu_init.c

@@ -132,7 +132,8 @@ void cpu_init_f (volatile immap_t * immr)
 	 *  I owe him a free beer. - wd]
 	 */
 
-#if defined(CONFIG_GTH)	        || \
+#if defined(CONFIG_ADDERII)	|| \
+    defined(CONFIG_GTH)	        || \
     defined(CONFIG_HERMES)	|| \
     defined(CONFIG_ICU862)	|| \
     defined(CONFIG_IP860)	|| \

cpu/mpc8xx/start.S

@@ -76,9 +76,6 @@
 	GOT_ENTRY(__init_end)
 	GOT_ENTRY(_end)
 	GOT_ENTRY(__bss_start)
-#if defined(CONFIG_ICU862)
-	GOT_ENTRY(environment)
-#endif
 	END_GOT
 
 /*
@@ -617,16 +614,7 @@ clear_bss:
 	 * Now clear BSS segment
 	 */
 	lwz	r3,GOT(__bss_start)
-#if defined(CONFIG_ICU862)
-	/*
-	 * For the FADS - the environment is the very last item in flash.
-	 * The real .bss stops just before environment starts, so only
-	 * clear up to that point.
-	 */
-	lwz	r4,GOT(environment)
-#else
 	lwz	r4,GOT(_end)
-#endif
 
 	cmplw	0, r3, r4
 	beq	6f

drivers/ns16550.c

@@ -26,10 +26,9 @@ void NS16550_init (NS16550_t com_port, int baud_divisor)
 	com_port->lcr = LCRVAL;
 	com_port->mcr = MCRVAL;
 	com_port->fcr = FCRVAL;
-#ifdef CONFIG_OMAP1510
-	com_port->mdr1 = 0; /* select uart mode */
+#if defined(CONFIG_OMAP1510) || defined(CONFIG_OMAP1610)
+	com_port->mdr1 = 0;	/* select uart mode */
 #endif
-
 }
 
 void NS16550_reinit (NS16550_t com_port, int baud_divisor)

drivers/serial.c

@@ -52,6 +52,12 @@ static int calc_divisor (void)
 		return (1);				/* return 1 for base divisor */
 	}
 	console->osc_12m_sel = 0;			/* clear if previsouly set */
+#endif
+#ifdef CONFIG_OMAP1610
+	/* If can't cleanly clock 115200 set div to 1 */
+	if ((CFG_NS16550_CLK == 48000000) && (gd->baudrate == 115200)) {
+		return (26);		/* return 26 for base divisor */
+	}
 #endif
 	return (CFG_NS16550_CLK / 16 / gd->baudrate);
 }

examples/Makefile

@@ -79,6 +79,8 @@ endif
 LIBCOBJS= stubs.o
 LIBOBJS	= $(LIBAOBJS) $(LIBCOBJS)
 
+gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
+
 CPPFLAGS += -I..
 
 all:	.depend $(LIB) $(SREC) $(BIN)
@@ -88,7 +90,8 @@ $(LIB): .depend $(LIBOBJS)
 	$(AR) crv $@ $(LIBOBJS)
 
 %.srec:	%.o $(LIB)
-	$(LD) -g -Ttext $(LOAD_ADDR) -o $(<:.o=) -e $(<:.o=) $< $(LIB)
+	$(LD) -g -Ttext $(LOAD_ADDR) -o $(<:.o=) -e $(<:.o=) $< $(LIB) \
+		-L$(gcclibdir) -lgcc
 	$(OBJCOPY) -O srec $(<:.o=) $@
 
 %.bin:	%.srec

include/arm926ejs.h

@@ -0,0 +1,8 @@
+/************************************************
+ * NAME                 arm926ejs.h             *
+ * Version      :       23 June 2003            *
+ ************************************************/
+/* Currently empty */
+#ifndef __ARM926EJS_H__
+#define __ARM926EJS_H__
+#endif /*__ARM926EJS_H__*/

include/asm-arm/arch-arm926ejs/sizes.h

@@ -0,0 +1,51 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA0 2111-1307
+ * USA
+ */
+/* DO NOT EDIT!! - this file automatically generated
+ *		   from .s file by awk -f s2h.awk
+ */
+/*  Size defintions
+ *  Copyright (C) ARM Limited 1998. All rights reserved.
+ */
+
+#ifndef __sizes_h
+#define __sizes_h			1
+
+/* handy sizes */
+#define SZ_1K		0x00000400
+#define SZ_4K		0x00001000
+#define SZ_8K		0x00002000
+#define SZ_16K		0x00004000
+#define SZ_64K		0x00010000
+#define SZ_128K	0x00020000
+#define SZ_256K	0x00040000
+#define SZ_512K	0x00080000
+
+#define SZ_1M		0x00100000
+#define SZ_2M		0x00200000
+#define SZ_4M		0x00400000
+#define SZ_8M		0x00800000
+#define SZ_16M		0x01000000
+#define SZ_32M		0x02000000
+#define SZ_64M		0x04000000
+#define SZ_128M	0x08000000
+#define SZ_256M	0x10000000
+#define SZ_512M	0x20000000
+
+#define SZ_1G		0x40000000
+#define SZ_2G		0x80000000
+
+#endif	/* __sizes_h */

include/bzlib.h

@@ -0,0 +1,330 @@
+/*
+ * This file is a modified version of bzlib.h from the bzip2-1.0.2
+ * distribution which can be found at http://sources.redhat.com/bzip2/
+ */
+
+/*-------------------------------------------------------------*/
+/*--- Public header file for the library.                   ---*/
+/*---                                               bzlib.h ---*/
+/*-------------------------------------------------------------*/
+
+/*--
+  This file is a part of bzip2 and/or libbzip2, a program and
+  library for lossless, block-sorting data compression.
+
+  Copyright (C) 1996-2002 Julian R Seward.  All rights reserved.
+
+  Redistribution and use in source and binary forms, with or without
+  modification, are permitted provided that the following conditions
+  are met:
+
+  1. Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+
+  2. The origin of this software must not be misrepresented; you must
+     not claim that you wrote the original software.  If you use this
+     software in a product, an acknowledgment in the product
+     documentation would be appreciated but is not required.
+
+  3. Altered source versions must be plainly marked as such, and must
+     not be misrepresented as being the original software.
+
+  4. The name of the author may not be used to endorse or promote
+     products derived from this software without specific prior written
+     permission.
+
+  THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+  OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+  DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+  GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+  WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+  Julian Seward, Cambridge, UK.
+  jseward@acm.org
+  bzip2/libbzip2 version 1.0 of 21 March 2000
+
+  This program is based on (at least) the work of:
+     Mike Burrows
+     David Wheeler
+     Peter Fenwick
+     Alistair Moffat
+     Radford Neal
+     Ian H. Witten
+     Robert Sedgewick
+     Jon L. Bentley
+
+  For more information on these sources, see the manual.
+--*/
+
+
+#ifndef _BZLIB_H
+#define _BZLIB_H
+
+/* Configure for U-Boot environment */
+#define BZ_NO_STDIO
+#define BZ_NO_COMPRESS
+/* End of configuration for U-Boot environment */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define BZ_RUN               0
+#define BZ_FLUSH             1
+#define BZ_FINISH            2
+
+#define BZ_OK                0
+#define BZ_RUN_OK            1
+#define BZ_FLUSH_OK          2
+#define BZ_FINISH_OK         3
+#define BZ_STREAM_END        4
+#define BZ_SEQUENCE_ERROR    (-1)
+#define BZ_PARAM_ERROR       (-2)
+#define BZ_MEM_ERROR         (-3)
+#define BZ_DATA_ERROR        (-4)
+#define BZ_DATA_ERROR_MAGIC  (-5)
+#define BZ_IO_ERROR          (-6)
+#define BZ_UNEXPECTED_EOF    (-7)
+#define BZ_OUTBUFF_FULL      (-8)
+#define BZ_CONFIG_ERROR      (-9)
+
+typedef
+   struct {
+      char *next_in;
+      unsigned int avail_in;
+      unsigned int total_in_lo32;
+      unsigned int total_in_hi32;
+
+      char *next_out;
+      unsigned int avail_out;
+      unsigned int total_out_lo32;
+      unsigned int total_out_hi32;
+
+      void *state;
+
+      void *(*bzalloc)(void *,int,int);
+      void (*bzfree)(void *,void *);
+      void *opaque;
+   }
+   bz_stream;
+
+
+#ifndef BZ_IMPORT
+#define BZ_EXPORT
+#endif
+
+#ifdef _WIN32
+#   include <windows.h>
+#   ifdef small
+      /* windows.h define small to char */
+#      undef small
+#   endif
+#   ifdef BZ_EXPORT
+#   define BZ_API(func) WINAPI func
+#   define BZ_EXTERN extern
+#   else
+   /* import windows dll dynamically */
+#   define BZ_API(func) (WINAPI * func)
+#   define BZ_EXTERN
+#   endif
+#else
+#   define BZ_API(func) func
+#   define BZ_EXTERN extern
+#endif
+
+
+/*-- Core (low-level) library functions --*/
+
+BZ_EXTERN int BZ_API(BZ2_bzCompressInit) (
+      bz_stream* strm,
+      int        blockSize100k,
+      int        verbosity,
+      int        workFactor
+   );
+
+BZ_EXTERN int BZ_API(BZ2_bzCompress) (
+      bz_stream* strm,
+      int action
+   );
+
+BZ_EXTERN int BZ_API(BZ2_bzCompressEnd) (
+      bz_stream* strm
+   );
+
+BZ_EXTERN int BZ_API(BZ2_bzDecompressInit) (
+      bz_stream *strm,
+      int       verbosity,
+      int       small
+   );
+
+BZ_EXTERN int BZ_API(BZ2_bzDecompress) (
+      bz_stream* strm
+   );
+
+BZ_EXTERN int BZ_API(BZ2_bzDecompressEnd) (
+      bz_stream *strm
+   );
+
+
+
+/*-- High(er) level library functions --*/
+
+#ifndef BZ_NO_STDIO
+#define BZ_MAX_UNUSED 5000
+
+/* Need a definitition for FILE */
+#include <stdio.h>
+
+typedef void BZFILE;
+
+BZ_EXTERN BZFILE* BZ_API(BZ2_bzReadOpen) (
+      int*  bzerror,
+      FILE* f,
+      int   verbosity,
+      int   small,
+      void* unused,
+      int   nUnused
+   );
+
+BZ_EXTERN void BZ_API(BZ2_bzReadClose) (
+      int*    bzerror,
+      BZFILE* b
+   );
+
+BZ_EXTERN void BZ_API(BZ2_bzReadGetUnused) (
+      int*    bzerror,
+      BZFILE* b,
+      void**  unused,
+      int*    nUnused
+   );
+
+BZ_EXTERN int BZ_API(BZ2_bzRead) (
+      int*    bzerror,
+      BZFILE* b,
+      void*   buf,
+      int     len
+   );
+
+BZ_EXTERN BZFILE* BZ_API(BZ2_bzWriteOpen) (
+      int*  bzerror,
+      FILE* f,
+      int   blockSize100k,
+      int   verbosity,
+      int   workFactor
+   );
+
+BZ_EXTERN void BZ_API(BZ2_bzWrite) (
+      int*    bzerror,
+      BZFILE* b,
+      void*   buf,
+      int     len
+   );
+
+BZ_EXTERN void BZ_API(BZ2_bzWriteClose) (
+      int*          bzerror,
+      BZFILE*       b,
+      int           abandon,
+      unsigned int* nbytes_in,
+      unsigned int* nbytes_out
+   );
+
+BZ_EXTERN void BZ_API(BZ2_bzWriteClose64) (
+      int*          bzerror,
+      BZFILE*       b,
+      int           abandon,
+      unsigned int* nbytes_in_lo32,
+      unsigned int* nbytes_in_hi32,
+      unsigned int* nbytes_out_lo32,
+      unsigned int* nbytes_out_hi32
+   );
+#endif
+
+
+/*-- Utility functions --*/
+
+BZ_EXTERN int BZ_API(BZ2_bzBuffToBuffCompress) (
+      char*         dest,
+      unsigned int* destLen,
+      char*         source,
+      unsigned int  sourceLen,
+      int           blockSize100k,
+      int           verbosity,
+      int           workFactor
+   );
+
+BZ_EXTERN int BZ_API(BZ2_bzBuffToBuffDecompress) (
+      char*         dest,
+      unsigned int* destLen,
+      char*         source,
+      unsigned int  sourceLen,
+      int           small,
+      int           verbosity
+   );
+
+
+/*--
+   Code contributed by Yoshioka Tsuneo
+   (QWF00133@niftyserve.or.jp/tsuneo-y@is.aist-nara.ac.jp),
+   to support better zlib compatibility.
+   This code is not _officially_ part of libbzip2 (yet);
+   I haven't tested it, documented it, or considered the
+   threading-safeness of it.
+   If this code breaks, please contact both Yoshioka and me.
+--*/
+
+BZ_EXTERN const char * BZ_API(BZ2_bzlibVersion) (
+      void
+   );
+
+#ifndef BZ_NO_STDIO
+BZ_EXTERN BZFILE * BZ_API(BZ2_bzopen) (
+      const char *path,
+      const char *mode
+   );
+
+BZ_EXTERN BZFILE * BZ_API(BZ2_bzdopen) (
+      int        fd,
+      const char *mode
+   );
+
+BZ_EXTERN int BZ_API(BZ2_bzread) (
+      BZFILE* b,
+      void* buf,
+      int len
+   );
+
+BZ_EXTERN int BZ_API(BZ2_bzwrite) (
+      BZFILE* b,
+      void*   buf,
+      int     len
+   );
+
+BZ_EXTERN int BZ_API(BZ2_bzflush) (
+      BZFILE* b
+   );
+
+BZ_EXTERN void BZ_API(BZ2_bzclose) (
+      BZFILE* b
+   );
+
+BZ_EXTERN const char * BZ_API(BZ2_bzerror) (
+      BZFILE *b,
+      int    *errnum
+   );
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/*-------------------------------------------------------------*/
+/*--- end                                           bzlib.h ---*/
+/*-------------------------------------------------------------*/

include/cmd_confdefs.h

@@ -148,6 +148,8 @@
 #define CONFIG_BOOTP_BOOTPATH		0x00000010
 #define CONFIG_BOOTP_BOOTFILESIZE	0x00000020
 #define CONFIG_BOOTP_DNS		0x00000040
+#define CONFIG_BOOTP_DNS2		0x00000080
+#define CONFIG_BOOTP_SEND_HOSTNAME      0x00000100
 
 #define CONFIG_BOOTP_VENDOREX		0x80000000
 

include/configs/AdderII.h

@@ -0,0 +1,226 @@
+/******************************************************************************
+* A collection of structures, addresses, and values associated with
+* the Motorola 850T AdderIIF board.  Copied from the FADS stuff.
+* Magnus Damm added defines for 8xxrom and extended bd_info.
+* Helmut Buchsbaum added bitvalues for BCSRx
+*
+* Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
+*******************************************************************************
+* 2003-JUL: The AdderII is using the following physical memorymap:
+*******************************************************************************
+* FA200000 -> FA20FFFF : IMAP   internal in the cpu
+* FE000000 -> FE400000 : flash  connected to CS0, setup by 8xxrom
+* 00000000 -> 00800000 : sdram  setup by 8xxrom
+*******************************************************************************/
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <mpc8xx_irq.h>
+
+#define	CONFIG_MPC860		1
+#define	CONFIG_MPC860T		1
+#define CONFIG_ADDERII		1
+
+/* CPU Clock speed */
+#define MPC8XX_FACT		12		/* Multilpy by 12 */
+#define MPC8XX_XIN		4000000		/* 4MHz */
+#define MPC8XX_HZ		( MPC8XX_FACT * MPC8XX_XIN )
+
+#define CONFIG_8xx_GCLK_FREQ	MPC8XX_HZ
+#define CONFIG_SDRAM_50MHZ      1
+
+
+/* Default Serial Console, baudrate */
+#define CONFIG_8xx_CONS_SMC1	1		/* Console is on SMC1 */
+#define CONFIG_BAUDRATE		38400
+#define CONFIG_LOADS_ECHO	1
+
+/* FEC Ethernet controller configurations */
+#define CONFIG_FEC_ETH		1
+#define CONFIG_NET_MULTI	1
+#define FEC_ENET		1
+
+/* Interrupt level assignments.
+*/
+#define FEC_INTERRUPT   	SIU_LEVEL3      /* FEC interrupt */
+
+/* Older kernels need clock in MHz newer in Hz */
+#define CONFIG_CLOCKS_IN_MHZ	1
+
+/* Monitor Functions */
+#define CONFIG_COMMANDS		( CFG_CMD_FLASH | \
+				  CFG_CMD_MEMORY| \
+				  CFG_CMD_NET   | \
+				  CFG_CMD_ENV	| \
+				  CFG_CMD_PING  | \
+				  CFG_CMD_SDRAM )
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/* Configuration Settings */
+#define CFG_PROMPT		"=>"		/* Monitor Command Prompt */
+
+#if ( CONFIG_COMMANDS & CFG_CMD_KGDB )
+#define CFG_CBSIZE		1024		/* Console I/P buffer size */
+#else
+#define CFG_CBSIZE		256
+#endif
+
+#define CFG_PBSIZE		( CFG_CBSIZE + sizeof( CFG_PROMPT ) + 16 )
+						/* Print buffer size */
+
+#define CFG_MAXARGS		16		/* Max number of cmd args */
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot args buffer size */
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#define CFG_MEMTEST_START	0x00100000	/* Mem test works on  */
+#define CFG_MEMTEST_END		0x00800000	/* 1 ... 8MB in SDRAM */
+
+#define CFG_LOAD_ADDR		0x00100000
+#define CFG_HZ          	1000
+
+/******************************************************************************
+** Low level configuration settings.
+** ( adderss mappings, register init values, etc. )
+** You should know what you are doing if you make changes here.
+******************************************************************************/
+/* Start address  for the final memory configuration set up by startup code
+** Please note that CFG_SDRAM_BASE must start at 0
+*/
+
+#define CFG_SDRAM_BASE		0x00000000
+
+#define CFG_FLASH_BASE		0xFE000000
+#define CFG_FLASH_SIZE		(( uint ) ( 4 * 1024 * 1024 ))	/* 4MB */
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define CFG_MONITOR_LEN		( 256 << 10 )	/* 256 KByte */
+#define CFG_MALLOC_LEN		( 384 << 10 )	/* 384 KByte SDRAM rsvd */
+						/* malloc() usage 	*/
+/**
+** For booting Linux, the board info and command line data
+** have to be in the first 8 MB of memory, since this is
+** the maximum mapped by the Linux kernel during initialization.
+**/
+#define CFG_BOOTMAPSZ		( 8 << 20 )    /* Initial Memory map for Linux */
+
+/******************************************************************************
+** Flash Organization
+******************************************************************************/
+
+#define CFG_MAX_FLASH_BANKS	1		/* Max no of flash mem banks */
+#define CFG_MAX_FLASH_SECT	71		/* Max no of sec on 1 chip   */
+
+#define CFG_FLASH_ERASE_TOUT	120000		/* Erase flash timeout (ms)  */
+#define CFG_FLASH_WRITE_TOUT	500		/* Write flash timeout (ms)  */
+
+/******************************************************************************
+**	U-BOOT Environment variables in Flash
+******************************************************************************/
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_OFFSET		0x00040000
+#define CFG_ENV_SIZE		0x10000		/* 64KBytes env space */
+#define CFG_ENV_SECT_SIZE	0x10000
+
+/******************************************************************************
+**	Cache Configuration
+******************************************************************************/
+#define CFG_CACHELINE_SIZE      16      /* For all MPC8xx CPUs        */
+#if ( CONFIG_COMMANDS & CFG_CMD_KGDB )
+#define CFG_CACHELINE_SHIFT     4       /* log base 2 of the above value */
+#endif
+
+/******************************************************************************
+** Internal memory mapped register
+******************************************************************************/
+#define CFG_IMMR		0xFA200000
+#define CFG_IMMR_SIZE		(( uint) ( 62 * 1024 ))	/* 64 KByte res */
+
+/* Definitions for initial stack pointer and data area ( in DPRAM ) */
+
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define CFG_INIT_RAM_END	0x2F00		/* end of used area in DPRAM */
+#define CFG_GBL_DATA_SIZE	64
+#define CFG_GBL_DATA_OFFSET	( CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE )
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+
+
+/* SIU Module Configuration Register */
+#define CFG_SIUMCR		( SIUMCR_AEME | SIUMCR_MLRC01 | SIUMCR_DBGC10 )
+
+/******************************************************************************
+**	SYPCR - System protection and control
+**	SYPCR - can be written only once after reset
+******************************************************************************/
+#if defined( CONFIG_WATCHDOG )
+#define CFG_SYPCR		( SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | \
+				  SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | \
+				  SYPCR_SWP )
+#else
+#define CFG_SYPCR		( SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | \
+				  SYPCR_SWF | SYPCR_SWP )
+#endif
+
+/* TBSCR - Time Base Status and Control Register */
+#define CFG_TBSCR		( TBSCR_REFA | TBSCR_REFB | TBSCR_TBE )
+
+/* PISCR - Periodic Interrupt Status and Control */
+#define CFG_PISCR       	( PISCR_PS | PISCR_PITF )
+
+/* PLPRCR - PLL, Low-Power, and Reset Control Register */
+#define CFG_PLPRCR      	((( MPC8XX_FACT - 1 ) << PLPRCR_MF_SHIFT ) | \
+                                PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST )
+
+/* SCCR - System Clock and reset Control Register */
+#define SCCR_MASK       	SCCR_EBDF11
+#define CFG_SCCR		( SCCR_TBS | SCCR_COM00 | SCCR_DFSYNC00 | \
+				  SCCR_DFBRG00 | SCCR_DFNL000| SCCR_DFNH000 | \
+				  SCCR_DFLCD000 | SCCR_DFALCD00 )
+#define CFG_DER         	0
+
+/******************************************************************************
+** Because of the way the 860 starts up and assigns CS0 the
+** entire address space, we have to set the memory controller
+** differently.  Normally, you write the option register
+** first, and then enable the chip select by writing the
+** base register.  For CS0, you must write the base register
+** first, followed by the option register.
+******************************************************************************/
+/**
+ ** Memory Controller Definitions
+ ** BR0/1/2... and OR0/1/2...
+*/
+/* For AdderII BR0 FLASH */
+
+#define CFG_REMAP_OR_AM		0xFF800000		/* OR addr mask */
+#define CFG_PRELIM_OR_AM	0xFF800000		/* OR addr mask */
+
+/* Flash Timings: ACS = 11, TRLX = 1, CSNT = 0, SCY = 7 */
+#define CFG_OR_TIMING_FLASH 	( OR_ACS_DIV2 | OR_BI | OR_SCY_7_CLK | OR_TRLX )
+
+#define CFG_OR0_REMAP		( CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH )
+
+#define CFG_OR0_PRELIM		CFG_OR0_REMAP
+#define CFG_BR0_PRELIM		(( CFG_FLASH_BASE & BR_BA_MSK ) | \
+				   BR_PS_16 | BR_V )
+
+/* For AdderII BR1 SDRAM */
+
+#define CFG_PRELIM_OR1_AM 	0xFF800000
+#define CFG_OR1_REMAP		( CFG_PRELIM_OR1_AM | OR_CSNT_SAM | OR_ACS_DIV2 )
+#define CFG_OR1_PRELIM  	( CFG_PRELIM_OR1_AM | OR_CSNT_SAM | OR_ACS_DIV2 )
+#define CFG_BR1_PRELIM  	( CFG_SDRAM_BASE | BR_MS_UPMA | BR_V )
+
+
+/*******************************************************************************
+* Internal Definitions Boot Flags
+*******************************************************************************/
+#define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH  */
+#define BOOTFLAG_WARM   0x02            /* Software reboot                   */
+
+
+#endif
+/* __CONFIG_H */
+

include/configs/CPCI405.h

@@ -69,12 +69,10 @@
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define	CONFIG_PHY_ADDR		0	/* PHY address			*/
 
-#if 0 /* test-only */
-#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT |  \
-				 CONFIG_BOOTP_VENDOREX)
-#else
-#define CONFIG_BOOTP_MASK       (CONFIG_BOOTP_DEFAULT)
-#endif
+#define CONFIG_BOOTP_MASK       (CONFIG_BOOTP_DEFAULT | \
+				 CONFIG_BOOTP_DNS | \
+				 CONFIG_BOOTP_DNS2 | \
+				 CONFIG_BOOTP_SEND_HOSTNAME )
 
 #define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
 				CFG_CMD_DHCP	| \

include/configs/CPCI4052.h

@@ -72,12 +72,10 @@
 
 #define CONFIG_RTC_M48T35A	1		/* ST Electronics M48 timekeeper */
 
-#if 0 /* test-only */
-#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT |  \
-				 CONFIG_BOOTP_VENDOREX)
-#else
-#define CONFIG_BOOTP_MASK       (CONFIG_BOOTP_DEFAULT)
-#endif
+#define CONFIG_BOOTP_MASK       (CONFIG_BOOTP_DEFAULT | \
+				 CONFIG_BOOTP_DNS | \
+				 CONFIG_BOOTP_DNS2 | \
+				 CONFIG_BOOTP_SEND_HOSTNAME )
 
 #define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
 				CFG_CMD_DHCP	| \

include/configs/CPCI405AB.h

@@ -65,7 +65,10 @@
 
 #define CONFIG_RTC_M48T35A	1		/* ST Electronics M48 timekeeper */
 
-#define CONFIG_BOOTP_MASK       (CONFIG_BOOTP_DEFAULT)
+#define CONFIG_BOOTP_MASK       (CONFIG_BOOTP_DEFAULT | \
+				 CONFIG_BOOTP_DNS | \
+				 CONFIG_BOOTP_DNS2 | \
+				 CONFIG_BOOTP_SEND_HOSTNAME )
 
 #define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
 				CFG_CMD_DHCP	| \

include/configs/ICU862.h

@@ -196,7 +196,7 @@
 #define	CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
 #endif
 #else
-#define CFG_MONITOR_LEN (272 << 10) /* Reserve 272 kB for Monitor */
+#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
 #endif
 #define CFG_MONITOR_BASE	TEXT_BASE
 #define	CFG_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc()	*/

include/configs/IceCube.h

@@ -131,9 +131,7 @@
  */
 #define CFG_MBAR		0xf0000000
 #define CFG_SDRAM_BASE		0x00000000
-#ifdef CONFIG_MPC5200
 #define CFG_DEFAULT_MBAR	0x80000000
-#endif
 
 /* Use SRAM until RAM will be available */
 #define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM

include/configs/omap1510.h

@@ -175,6 +175,18 @@
 
 #define MOD_CONF_CTRL_0		0xfffe1080
 
+#ifdef CONFIG_OMAP1610 /* 1610 Configuration Register */
+
+#define USB_OTG_CTRL			0xFFFB040C
+#define USB_TRANSCEIVER_CTRL	0xFFFE1064
+#define PULL_DWN_CTRL_4	0xFFFE10AC
+#define PU_PD_SEL_0		0xFFFE10B4
+#define PU_PD_SEL_1		0xFFFE10B8
+#define PU_PD_SEL_2		0xFFFE10BC
+#define PU_PD_SEL_3		0xFFFE10C0
+#define PU_PD_SEL_4		0xFFFE10C4
+
+#endif
 /*
  * Traffic Controller Memory Interface Registers
  */
@@ -521,6 +533,7 @@ typedef struct {
 #define WDTIM_CONTROL_ST	BIT7
 
 
+
 /* ---------------------------------------------------------------------------
  *  Differentiating processor versions for those who care.
  * ---------------------------------------------------------------------------

include/configs/omap1610inn.h

@@ -0,0 +1,169 @@
+/*
+ * (C) Copyright 2003
+ * Texas Instruments.
+ * Kshitij Gupta <kshitij@ti.com>
+ * Configuation settings for the TI OMAP Innovator board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_ARM926EJS	1	/* This is an arm926ejs CPU core  */
+#define CONFIG_OMAP	1			/* in a TI OMAP core    */
+#define CONFIG_OMAP1610	1		/* which is in a 1610  */
+#define CONFIG_INNOVATOROMAP1610	1	/*  a Innovator Board  */
+
+/* input clock of PLL */
+/* the OMAP1610 Innovator has 12MHz input clock */
+#define CONFIG_SYS_CLK_FREQ	12000000
+
+#undef CONFIG_USE_IRQ	/* we don't need IRQ/FIQ stuff */
+
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs  */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN	(CFG_ENV_SIZE + 128*1024)
+
+/*
+ * Hardware drivers
+ */
+/*
+*/
+#define CONFIG_DRIVER_LAN91C96
+#define CONFIG_LAN91C96_BASE 0x04000300
+#define CONFIG_LAN91C96_EXT_PHY
+
+/*
+ * NS16550 Configuration
+ */
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE	(-4)
+#define CFG_NS16550_CLK	(48000000)	/* can be 12M/32Khz or 48Mhz */
+#define CFG_NS16550_COM1	0xfffb0000	/* uart1, bluetooth uart 
+						on helen */
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_SERIAL1	1	/* we use SERIAL 1 on OMAP1610 Innovator */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_BAUDRATE	115200
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#define CONFIG_COMMANDS	(CONFIG_CMD_DFL | CFG_CMD_DHCP)
+#define CONFIG_BOOTP_MASK	CONFIG_BOOTP_DEFAULT
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+#include <configs/omap1510.h>
+
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTARGS	"mem=32M console=ttyS0,115200n8 noinitrd \
+				root=/dev/nfs rw nfsroot=157.87.82.48:\
+				/home/a0875451/mwd/myfs/target ip=dhcp"
+#define CONFIG_NETMASK	255.255.254.0	/* talk on MY local net */
+#define CONFIG_IPADDR	156.117.97.156	/* static IP I currently own */
+#define CONFIG_SERVERIP	156.117.97.139	/* current IP of my dev pc */
+#define CONFIG_BOOTFILE	"uImage"	/* file to load */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	115200	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	1	/* which serial port to use */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP	/* undef to save memory     */
+#define CFG_PROMPT	"OMAP1610 Innovator # "	/* Monitor Command Prompt   */
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size  */
+/* Print Buffer Size */
+#define CFG_PBSIZE	(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+#define CFG_MAXARGS	16		/* max number of command args   */
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size    */
+
+#define CFG_MEMTEST_START	0x10000000	/* memtest works on */
+#define CFG_MEMTEST_END	0x12000000	/* 32 MB in DRAM    */
+
+#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR	0x10000000	/* default load address */
+
+/* The 1610 has 6 timers, they can be driven by the RefClk (12Mhz) or by 
+ * DPLL1. This time is further subdivided by a local divisor.
+ */
+#define CFG_TIMERBASE	0xFFFEC500	/* use timer 1 */
+#define CFG_PVT	7	/* 2^(pvt+1), divide by 256 */
+#define CFG_HZ	((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT))
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1	/* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1	0x10000000	/* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE	0x02000000	/* 32 MB */
+
+#define PHYS_FLASH_1	0x00000000	/* Flash Bank #1 */
+
+#define CFG_FLASH_BASE	PHYS_FLASH_1
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define PHYS_FLASH_SIZE	0x02000000	/* 32MB */
+#define CFG_MAX_FLASH_SECT	(259)	/* max number of sectors on one chip */
+/* addr of environment */
+#define CFG_ENV_ADDR	(CFG_FLASH_BASE + 0x020000)
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT	(20*CFG_HZ)	/* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT	(20*CFG_HZ)	/* Timeout for Flash Write */
+
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_SIZE	0x20000	/* Total Size of Environment Sector */
+#define CFG_ENV_OFFSET	0x20000	/* environment starts here  */
+
+#endif							/* __CONFIG_H */

include/configs/rmu.h

@@ -61,8 +61,39 @@
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
 #undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 
+/* enable I2C and select the hardware/software driver */
+#undef	CONFIG_HARD_I2C			/* I2C with hardware support	*/
+#define CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
+
+#define CFG_I2C_SPEED		40000	/* 40 kHz is supposed to work	*/
+#define CFG_I2C_SLAVE		0xFE
+
+/* Software (bit-bang) I2C driver configuration */
+#define PB_SCL		0x00000020	/* PB 26 */
+#define PB_SDA		0x00000010	/* PB 27 */
+
+#define I2C_INIT	(immr->im_cpm.cp_pbdir |=  PB_SCL)
+#define I2C_ACTIVE	(immr->im_cpm.cp_pbdir |=  PB_SDA)
+#define I2C_TRISTATE	(immr->im_cpm.cp_pbdir &= ~PB_SDA)
+#define I2C_READ	((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
+#define I2C_SDA(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
+			else    immr->im_cpm.cp_pbdat &= ~PB_SDA
+#define I2C_SCL(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
+			else    immr->im_cpm.cp_pbdat &= ~PB_SCL
+#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
+
+/* M41T11 Serial Access Timekeeper(R) SRAM */
+#define CONFIG_RTC_M41T11 1
+#define CFG_I2C_RTC_ADDR 0x68
+#define CFG_M41T11_BASE_YEAR 1900	/* play along with the linux driver */
+
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_I2C	)
+
 #define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
@@ -152,6 +183,11 @@
 #define CFG_ENV_OFFSET_REDUND	(CFG_ENV_OFFSET+CFG_ENV_SIZE)
 #define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
 
+/*-----------------------------------------------------------------------
+ * Reset address
+ */
+#define	CFG_RESET_ADDRESS	((ulong)((((immap_t *)CFG_IMMR)->im_clkrst.res)))
+
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
@@ -291,12 +327,12 @@
  *
  */
 #define SDRAM_BASE_PRELIM	0x00000000	/* SDRAM base	*/
-#define	SDRAM_MAX_SIZE		0x01000000	/* max 16 MB */
+#define	SDRAM_MAX_SIZE		0x08000000	/* max 128 MB */
 
 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
 #define CFG_OR_TIMING_SDRAM	0x00000E00
 
-#define CFG_OR1_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
+#define CFG_OR1_PRELIM	(0xF0000000 | CFG_OR_TIMING_SDRAM ) /* map 256 MB */
 #define CFG_BR1_PRELIM	((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 
 /* RPXLITE mem setting */
@@ -321,8 +357,8 @@
  * MAMR settings for SDRAM
  */
 
-/* 10 column SDRAM */
-#define CFG_MAMR_10COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+/* 9 column SDRAM */
+#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
 			 MAMR_RLFA_16X | MAMR_WLFA_16X | MAMR_TLFA_16X)
 

include/flash.h

@@ -213,6 +213,7 @@ extern int flash_real_protect(flash_info_t *info, long sector, int prot);
 #define INTEL_ID_28F320J3A  0x00160016	/*  32M = 128K x  32	*/
 #define INTEL_ID_28F640J3A  0x00170017	/*  64M = 128K x  64	*/
 #define INTEL_ID_28F128J3A  0x00180018	/* 128M = 128K x 128	*/
+#define INTEL_ID_28F256L18T 0x880D880D	/* 256M = 128K x 255 + 32k x 4 */
 
 #define INTEL_ID_28F160S3   0x00D000D0	/*  16M = 512K x  32 (64kB x 32)	*/
 #define INTEL_ID_28F320S3   0x00D400D4	/*  32M = 512K x  64 (64kB x 64)	*/
@@ -319,6 +320,8 @@ extern int flash_real_protect(flash_info_t *info, long sector, int prot);
 #define FLASH_AMLV320U	0x00A2		/* AMD 29LV128M    ( 128M = 8M x 16 )	*/
 #define FLASH_AMLV640U	0x00A4		/* AMD 29LV640M    ( 64M = 4M x 16 )	*/
 #define FLASH_AMLV128U	0x00A6		/* AMD 29LV128M	   ( 128M = 8M x 16 )	*/
+/* Intel 28F256L18T 256M = 128K x 255 + 32k x 4	*/
+#define FLASH_28F256L18T 0x00A8
 
 #define FLASH_UNKNOWN	0xFFFF		/* unknown flash type			*/
 

include/mpc5xxx.h

@@ -78,6 +78,7 @@
 #define MPC5XXX_CDM		(CFG_MBAR + 0x0200)
 #define MPC5XXX_LPB		(CFG_MBAR + 0x0300)
 #define MPC5XXX_ICTL		(CFG_MBAR + 0x0500)
+#define MPC5XXX_GPT		(CFG_MBAR + 0x0600)
 #define MPC5XXX_GPIO		(CFG_MBAR + 0x0b00)
 #define MPC5XXX_PCI		(CFG_MBAR + 0x0d00)
 #define MPC5XXX_SDMA		(CFG_MBAR + 0x1200)
@@ -183,6 +184,10 @@
 #define MPC5XXX_ICTL_PER_STS	(MPC5XXX_ICTL + 0x0030)
 #define MPC5XXX_ICTL_BUS_STS	(MPC5XXX_ICTL + 0x0038)
 
+/* General Purpose Timers registers */
+#define MPC5XXX_GPT0_ENABLE		(MPC5XXX_GPT + 0x0)
+#define MPC5XXX_GPT0_COUNTER		(MPC5XXX_GPT + 0x4)
+
 /* Programmable Serial Controller (PSC) status register bits */
 #define PSC_SR_CDE		0x0080
 #define PSC_SR_RXRDY		0x0100

include/net.h

@@ -275,6 +275,9 @@ typedef struct icmphdr {
 extern IPaddr_t		NetOurGatewayIP;	/* Our gateway IP addresse	*/
 extern IPaddr_t		NetOurSubnetMask;	/* Our subnet mask (0 = unknown)*/
 extern IPaddr_t		NetOurDNSIP;	 /* Our Domain Name Server (0 = unknown)*/
+#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_DNS2)
+extern IPaddr_t		NetOurDNS2IP;	 /* Our 2nd Domain Name Server (0 = unknown)*/
+#endif
 extern char		NetOurNISDomain[32];	/* Our NIS domain		*/
 extern char		NetOurHostName[32];	/* Our hostname			*/
 extern char		NetOurRootPath[64];	/* Our root path		*/

include/ns16550.h

@@ -60,8 +60,10 @@ struct NS16550 {
 	int pad7:24;
 	unsigned char scr;		/* 7 */
 	int pad8:24;
-#ifdef CONFIG_OMAP1510
+#if defined(CONFIG_OMAP1510) || defined(CONFIG_OMAP1610)
 	unsigned char mdr1;		/* mode select reset TL16C750*/
+#endif
+#ifdef CONFIG_OMAP1510
 	int pad9:24;
 	unsigned long pad[10];
 	unsigned char osc_12m_sel;

include/version.h

@@ -24,6 +24,6 @@
 #ifndef	__VERSION_H__
 #define	__VERSION_H__
 
-#define	U_BOOT_VERSION	"U-Boot 0.4.6"
+#define	U_BOOT_VERSION	"U-Boot 0.4.7"
 
 #endif	/* __VERSION_H__ */

include/watchdog.h

@@ -85,16 +85,4 @@
 	void reset_4xx_watchdog(void);
 #endif
 
-/* MPC 8260 */
-#if defined(CONFIG_MPC8260) && !defined(__ASSEMBLY__)
-#if defined(CONFIG_WATCHDOG)
-extern __inline__ void
-reset_8260_watchdog(volatile immap_t *immr)
-{
-	immr->im_siu_conf.sc_swsr = 0x556c;
-	immr->im_siu_conf.sc_swsr = 0xaa39;
-}
-#endif /* !__ASSEMBLY__ && CONFIG_WATCHDOG */
-#endif /* CONFIG_MPC8260 && !__ASSEMBLY__ */
-
 #endif /* _WATCHDOG_H_ */

lib_generic/Makefile

@@ -25,7 +25,10 @@ include $(TOPDIR)/config.mk
 
 LIB	= libgeneric.a
 
-OBJS	= crc32.o ctype.o display_options.o ldiv.o string.o vsprintf.o zlib.o
+OBJS	= bzlib.o bzlib_crctable.o bzlib_decompress.o \
+	  bzlib_randtable.o bzlib_huffman.o \
+	  crc32.o ctype.o display_options.o ldiv.o \
+	  string.o vsprintf.o zlib.o
 
 $(LIB):	.depend $(OBJS)
 	$(AR) crv $@ $(OBJS)

lib_generic/bzlib_crctable.c

@@ -0,0 +1,148 @@
+#include <config.h>
+#ifdef CONFIG_BZIP2
+
+/*-------------------------------------------------------------*/
+/*--- Table for doing CRCs                                  ---*/
+/*---                                            crctable.c ---*/
+/*-------------------------------------------------------------*/
+
+/*--
+  This file is a part of bzip2 and/or libbzip2, a program and
+  library for lossless, block-sorting data compression.
+
+  Copyright (C) 1996-2002 Julian R Seward.  All rights reserved.
+
+  Redistribution and use in source and binary forms, with or without
+  modification, are permitted provided that the following conditions
+  are met:
+
+  1. Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+
+  2. The origin of this software must not be misrepresented; you must
+     not claim that you wrote the original software.  If you use this
+     software in a product, an acknowledgment in the product
+     documentation would be appreciated but is not required.
+
+  3. Altered source versions must be plainly marked as such, and must
+     not be misrepresented as being the original software.
+
+  4. The name of the author may not be used to endorse or promote
+     products derived from this software without specific prior written
+     permission.
+
+  THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+  OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+  DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+  GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+  WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+  Julian Seward, Cambridge, UK.
+  jseward@acm.org
+  bzip2/libbzip2 version 1.0 of 21 March 2000
+
+  This program is based on (at least) the work of:
+     Mike Burrows
+     David Wheeler
+     Peter Fenwick
+     Alistair Moffat
+     Radford Neal
+     Ian H. Witten
+     Robert Sedgewick
+     Jon L. Bentley
+
+  For more information on these sources, see the manual.
+--*/
+
+
+#include "bzlib_private.h"
+
+/*--
+  I think this is an implementation of the AUTODIN-II,
+  Ethernet & FDDI 32-bit CRC standard.  Vaguely derived
+  from code by Rob Warnock, in Section 51 of the
+  comp.compression FAQ.
+--*/
+
+UInt32 BZ2_crc32Table[256] = {
+
+   /*-- Ugly, innit? --*/
+
+   0x00000000L, 0x04c11db7L, 0x09823b6eL, 0x0d4326d9L,
+   0x130476dcL, 0x17c56b6bL, 0x1a864db2L, 0x1e475005L,
+   0x2608edb8L, 0x22c9f00fL, 0x2f8ad6d6L, 0x2b4bcb61L,
+   0x350c9b64L, 0x31cd86d3L, 0x3c8ea00aL, 0x384fbdbdL,
+   0x4c11db70L, 0x48d0c6c7L, 0x4593e01eL, 0x4152fda9L,
+   0x5f15adacL, 0x5bd4b01bL, 0x569796c2L, 0x52568b75L,
+   0x6a1936c8L, 0x6ed82b7fL, 0x639b0da6L, 0x675a1011L,
+   0x791d4014L, 0x7ddc5da3L, 0x709f7b7aL, 0x745e66cdL,
+   0x9823b6e0L, 0x9ce2ab57L, 0x91a18d8eL, 0x95609039L,
+   0x8b27c03cL, 0x8fe6dd8bL, 0x82a5fb52L, 0x8664e6e5L,
+   0xbe2b5b58L, 0xbaea46efL, 0xb7a96036L, 0xb3687d81L,
+   0xad2f2d84L, 0xa9ee3033L, 0xa4ad16eaL, 0xa06c0b5dL,
+   0xd4326d90L, 0xd0f37027L, 0xddb056feL, 0xd9714b49L,
+   0xc7361b4cL, 0xc3f706fbL, 0xceb42022L, 0xca753d95L,
+   0xf23a8028L, 0xf6fb9d9fL, 0xfbb8bb46L, 0xff79a6f1L,
+   0xe13ef6f4L, 0xe5ffeb43L, 0xe8bccd9aL, 0xec7dd02dL,
+   0x34867077L, 0x30476dc0L, 0x3d044b19L, 0x39c556aeL,
+   0x278206abL, 0x23431b1cL, 0x2e003dc5L, 0x2ac12072L,
+   0x128e9dcfL, 0x164f8078L, 0x1b0ca6a1L, 0x1fcdbb16L,
+   0x018aeb13L, 0x054bf6a4L, 0x0808d07dL, 0x0cc9cdcaL,
+   0x7897ab07L, 0x7c56b6b0L, 0x71159069L, 0x75d48ddeL,
+   0x6b93dddbL, 0x6f52c06cL, 0x6211e6b5L, 0x66d0fb02L,
+   0x5e9f46bfL, 0x5a5e5b08L, 0x571d7dd1L, 0x53dc6066L,
+   0x4d9b3063L, 0x495a2dd4L, 0x44190b0dL, 0x40d816baL,
+   0xaca5c697L, 0xa864db20L, 0xa527fdf9L, 0xa1e6e04eL,
+   0xbfa1b04bL, 0xbb60adfcL, 0xb6238b25L, 0xb2e29692L,
+   0x8aad2b2fL, 0x8e6c3698L, 0x832f1041L, 0x87ee0df6L,
+   0x99a95df3L, 0x9d684044L, 0x902b669dL, 0x94ea7b2aL,
+   0xe0b41de7L, 0xe4750050L, 0xe9362689L, 0xedf73b3eL,
+   0xf3b06b3bL, 0xf771768cL, 0xfa325055L, 0xfef34de2L,
+   0xc6bcf05fL, 0xc27dede8L, 0xcf3ecb31L, 0xcbffd686L,
+   0xd5b88683L, 0xd1799b34L, 0xdc3abdedL, 0xd8fba05aL,
+   0x690ce0eeL, 0x6dcdfd59L, 0x608edb80L, 0x644fc637L,
+   0x7a089632L, 0x7ec98b85L, 0x738aad5cL, 0x774bb0ebL,
+   0x4f040d56L, 0x4bc510e1L, 0x46863638L, 0x42472b8fL,
+   0x5c007b8aL, 0x58c1663dL, 0x558240e4L, 0x51435d53L,
+   0x251d3b9eL, 0x21dc2629L, 0x2c9f00f0L, 0x285e1d47L,
+   0x36194d42L, 0x32d850f5L, 0x3f9b762cL, 0x3b5a6b9bL,
+   0x0315d626L, 0x07d4cb91L, 0x0a97ed48L, 0x0e56f0ffL,
+   0x1011a0faL, 0x14d0bd4dL, 0x19939b94L, 0x1d528623L,
+   0xf12f560eL, 0xf5ee4bb9L, 0xf8ad6d60L, 0xfc6c70d7L,
+   0xe22b20d2L, 0xe6ea3d65L, 0xeba91bbcL, 0xef68060bL,
+   0xd727bbb6L, 0xd3e6a601L, 0xdea580d8L, 0xda649d6fL,
+   0xc423cd6aL, 0xc0e2d0ddL, 0xcda1f604L, 0xc960ebb3L,
+   0xbd3e8d7eL, 0xb9ff90c9L, 0xb4bcb610L, 0xb07daba7L,
+   0xae3afba2L, 0xaafbe615L, 0xa7b8c0ccL, 0xa379dd7bL,
+   0x9b3660c6L, 0x9ff77d71L, 0x92b45ba8L, 0x9675461fL,
+   0x8832161aL, 0x8cf30badL, 0x81b02d74L, 0x857130c3L,
+   0x5d8a9099L, 0x594b8d2eL, 0x5408abf7L, 0x50c9b640L,
+   0x4e8ee645L, 0x4a4ffbf2L, 0x470cdd2bL, 0x43cdc09cL,
+   0x7b827d21L, 0x7f436096L, 0x7200464fL, 0x76c15bf8L,
+   0x68860bfdL, 0x6c47164aL, 0x61043093L, 0x65c52d24L,
+   0x119b4be9L, 0x155a565eL, 0x18197087L, 0x1cd86d30L,
+   0x029f3d35L, 0x065e2082L, 0x0b1d065bL, 0x0fdc1becL,
+   0x3793a651L, 0x3352bbe6L, 0x3e119d3fL, 0x3ad08088L,
+   0x2497d08dL, 0x2056cd3aL, 0x2d15ebe3L, 0x29d4f654L,
+   0xc5a92679L, 0xc1683bceL, 0xcc2b1d17L, 0xc8ea00a0L,
+   0xd6ad50a5L, 0xd26c4d12L, 0xdf2f6bcbL, 0xdbee767cL,
+   0xe3a1cbc1L, 0xe760d676L, 0xea23f0afL, 0xeee2ed18L,
+   0xf0a5bd1dL, 0xf464a0aaL, 0xf9278673L, 0xfde69bc4L,
+   0x89b8fd09L, 0x8d79e0beL, 0x803ac667L, 0x84fbdbd0L,
+   0x9abc8bd5L, 0x9e7d9662L, 0x933eb0bbL, 0x97ffad0cL,
+   0xafb010b1L, 0xab710d06L, 0xa6322bdfL, 0xa2f33668L,
+   0xbcb4666dL, 0xb8757bdaL, 0xb5365d03L, 0xb1f740b4L
+};
+
+
+/*-------------------------------------------------------------*/
+/*--- end                                        crctable.c ---*/
+/*-------------------------------------------------------------*/
+
+#endif /* CONFIG_BZIP2 */

lib_generic/bzlib_decompress.c

@@ -0,0 +1,664 @@
+#include <config.h>
+#ifdef CONFIG_BZIP2
+
+/*-------------------------------------------------------------*/
+/*--- Decompression machinery                               ---*/
+/*---                                          decompress.c ---*/
+/*-------------------------------------------------------------*/
+
+/*--
+  This file is a part of bzip2 and/or libbzip2, a program and
+  library for lossless, block-sorting data compression.
+
+  Copyright (C) 1996-2002 Julian R Seward.  All rights reserved.
+
+  Redistribution and use in source and binary forms, with or without
+  modification, are permitted provided that the following conditions
+  are met:
+
+  1. Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+
+  2. The origin of this software must not be misrepresented; you must
+     not claim that you wrote the original software.  If you use this
+     software in a product, an acknowledgment in the product
+     documentation would be appreciated but is not required.
+
+  3. Altered source versions must be plainly marked as such, and must
+     not be misrepresented as being the original software.
+
+  4. The name of the author may not be used to endorse or promote
+     products derived from this software without specific prior written
+     permission.
+
+  THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+  OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+  DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+  GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+  WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+  Julian Seward, Cambridge, UK.
+  jseward@acm.org
+  bzip2/libbzip2 version 1.0 of 21 March 2000
+
+  This program is based on (at least) the work of:
+     Mike Burrows
+     David Wheeler
+     Peter Fenwick
+     Alistair Moffat
+     Radford Neal
+     Ian H. Witten
+     Robert Sedgewick
+     Jon L. Bentley
+
+  For more information on these sources, see the manual.
+--*/
+
+
+#include "bzlib_private.h"
+
+
+/*---------------------------------------------------*/
+static
+void makeMaps_d ( DState* s )
+{
+   Int32 i;
+   s->nInUse = 0;
+   for (i = 0; i < 256; i++)
+      if (s->inUse[i]) {
+         s->seqToUnseq[s->nInUse] = i;
+         s->nInUse++;
+      }
+}
+
+
+/*---------------------------------------------------*/
+#define RETURN(rrr)                               \
+   { retVal = rrr; goto save_state_and_return; };
+
+#define GET_BITS(lll,vvv,nnn)                     \
+   case lll: s->state = lll;                      \
+   while (True) {                                 \
+      if (s->bsLive >= nnn) {                     \
+         UInt32 v;                                \
+         v = (s->bsBuff >>                        \
+             (s->bsLive-nnn)) & ((1 << nnn)-1);   \
+         s->bsLive -= nnn;                        \
+         vvv = v;                                 \
+         break;                                   \
+      }                                           \
+      if (s->strm->avail_in == 0) RETURN(BZ_OK);  \
+      s->bsBuff                                   \
+         = (s->bsBuff << 8) |                     \
+           ((UInt32)                              \
+              (*((UChar*)(s->strm->next_in))));   \
+      s->bsLive += 8;                             \
+      s->strm->next_in++;                         \
+      s->strm->avail_in--;                        \
+      s->strm->total_in_lo32++;                   \
+      if (s->strm->total_in_lo32 == 0)            \
+         s->strm->total_in_hi32++;                \
+   }
+
+#define GET_UCHAR(lll,uuu)                        \
+   GET_BITS(lll,uuu,8)
+
+#define GET_BIT(lll,uuu)                          \
+   GET_BITS(lll,uuu,1)
+
+/*---------------------------------------------------*/
+#define GET_MTF_VAL(label1,label2,lval)           \
+{                                                 \
+   if (groupPos == 0) {                           \
+      groupNo++;                                  \
+      if (groupNo >= nSelectors)                  \
+         RETURN(BZ_DATA_ERROR);                   \
+      groupPos = BZ_G_SIZE;                       \
+      gSel = s->selector[groupNo];                \
+      gMinlen = s->minLens[gSel];                 \
+      gLimit = &(s->limit[gSel][0]);              \
+      gPerm = &(s->perm[gSel][0]);                \
+      gBase = &(s->base[gSel][0]);                \
+   }                                              \
+   groupPos--;                                    \
+   zn = gMinlen;                                  \
+   GET_BITS(label1, zvec, zn);                    \
+   while (1) {                                    \
+      if (zn > 20 /* the longest code */)         \
+         RETURN(BZ_DATA_ERROR);                   \
+      if (zvec <= gLimit[zn]) break;              \
+      zn++;                                       \
+      GET_BIT(label2, zj);                        \
+      zvec = (zvec << 1) | zj;                    \
+   };                                             \
+   if (zvec - gBase[zn] < 0                       \
+       || zvec - gBase[zn] >= BZ_MAX_ALPHA_SIZE)  \
+      RETURN(BZ_DATA_ERROR);                      \
+   lval = gPerm[zvec - gBase[zn]];                \
+}
+
+
+/*---------------------------------------------------*/
+Int32 BZ2_decompress ( DState* s )
+{
+   UChar      uc;
+   Int32      retVal;
+   Int32      minLen, maxLen;
+   bz_stream* strm = s->strm;
+
+   /* stuff that needs to be saved/restored */
+   Int32  i;
+   Int32  j;
+   Int32  t;
+   Int32  alphaSize;
+   Int32  nGroups;
+   Int32  nSelectors;
+   Int32  EOB;
+   Int32  groupNo;
+   Int32  groupPos;
+   Int32  nextSym;
+   Int32  nblockMAX;
+   Int32  nblock;
+   Int32  es;
+   Int32  N;
+   Int32  curr;
+   Int32  zt;
+   Int32  zn;
+   Int32  zvec;
+   Int32  zj;
+   Int32  gSel;
+   Int32  gMinlen;
+   Int32* gLimit;
+   Int32* gBase;
+   Int32* gPerm;
+
+   if (s->state == BZ_X_MAGIC_1) {
+      /*initialise the save area*/
+      s->save_i           = 0;
+      s->save_j           = 0;
+      s->save_t           = 0;
+      s->save_alphaSize   = 0;
+      s->save_nGroups     = 0;
+      s->save_nSelectors  = 0;
+      s->save_EOB         = 0;
+      s->save_groupNo     = 0;
+      s->save_groupPos    = 0;
+      s->save_nextSym     = 0;
+      s->save_nblockMAX   = 0;
+      s->save_nblock      = 0;
+      s->save_es          = 0;
+      s->save_N           = 0;
+      s->save_curr        = 0;
+      s->save_zt          = 0;
+      s->save_zn          = 0;
+      s->save_zvec        = 0;
+      s->save_zj          = 0;
+      s->save_gSel        = 0;
+      s->save_gMinlen     = 0;
+      s->save_gLimit      = NULL;
+      s->save_gBase       = NULL;
+      s->save_gPerm       = NULL;
+   }
+
+   /*restore from the save area*/
+   i           = s->save_i;
+   j           = s->save_j;
+   t           = s->save_t;
+   alphaSize   = s->save_alphaSize;
+   nGroups     = s->save_nGroups;
+   nSelectors  = s->save_nSelectors;
+   EOB         = s->save_EOB;
+   groupNo     = s->save_groupNo;
+   groupPos    = s->save_groupPos;
+   nextSym     = s->save_nextSym;
+   nblockMAX   = s->save_nblockMAX;
+   nblock      = s->save_nblock;
+   es          = s->save_es;
+   N           = s->save_N;
+   curr        = s->save_curr;
+   zt          = s->save_zt;
+   zn          = s->save_zn;
+   zvec        = s->save_zvec;
+   zj          = s->save_zj;
+   gSel        = s->save_gSel;
+   gMinlen     = s->save_gMinlen;
+   gLimit      = s->save_gLimit;
+   gBase       = s->save_gBase;
+   gPerm       = s->save_gPerm;
+
+   retVal = BZ_OK;
+
+   switch (s->state) {
+
+      GET_UCHAR(BZ_X_MAGIC_1, uc);
+      if (uc != BZ_HDR_B) RETURN(BZ_DATA_ERROR_MAGIC);
+
+      GET_UCHAR(BZ_X_MAGIC_2, uc);
+      if (uc != BZ_HDR_Z) RETURN(BZ_DATA_ERROR_MAGIC);
+
+      GET_UCHAR(BZ_X_MAGIC_3, uc)
+      if (uc != BZ_HDR_h) RETURN(BZ_DATA_ERROR_MAGIC);
+
+      GET_BITS(BZ_X_MAGIC_4, s->blockSize100k, 8)
+      if (s->blockSize100k < (BZ_HDR_0 + 1) ||
+          s->blockSize100k > (BZ_HDR_0 + 9)) RETURN(BZ_DATA_ERROR_MAGIC);
+      s->blockSize100k -= BZ_HDR_0;
+
+      if (s->smallDecompress) {
+         s->ll16 = BZALLOC( s->blockSize100k * 100000 * sizeof(UInt16) );
+         s->ll4  = BZALLOC(
+                      ((1 + s->blockSize100k * 100000) >> 1) * sizeof(UChar)
+                   );
+         if (s->ll16 == NULL || s->ll4 == NULL) RETURN(BZ_MEM_ERROR);
+      } else {
+         s->tt  = BZALLOC( s->blockSize100k * 100000 * sizeof(Int32) );
+         if (s->tt == NULL) RETURN(BZ_MEM_ERROR);
+      }
+
+      GET_UCHAR(BZ_X_BLKHDR_1, uc);
+
+      if (uc == 0x17) goto endhdr_2;
+      if (uc != 0x31) RETURN(BZ_DATA_ERROR);
+      GET_UCHAR(BZ_X_BLKHDR_2, uc);
+      if (uc != 0x41) RETURN(BZ_DATA_ERROR);
+      GET_UCHAR(BZ_X_BLKHDR_3, uc);
+      if (uc != 0x59) RETURN(BZ_DATA_ERROR);
+      GET_UCHAR(BZ_X_BLKHDR_4, uc);
+      if (uc != 0x26) RETURN(BZ_DATA_ERROR);
+      GET_UCHAR(BZ_X_BLKHDR_5, uc);
+      if (uc != 0x53) RETURN(BZ_DATA_ERROR);
+      GET_UCHAR(BZ_X_BLKHDR_6, uc);
+      if (uc != 0x59) RETURN(BZ_DATA_ERROR);
+
+      s->currBlockNo++;
+      if (s->verbosity >= 2)
+         VPrintf1 ( "\n    [%d: huff+mtf ", s->currBlockNo );
+
+      s->storedBlockCRC = 0;
+      GET_UCHAR(BZ_X_BCRC_1, uc);
+      s->storedBlockCRC = (s->storedBlockCRC << 8) | ((UInt32)uc);
+      GET_UCHAR(BZ_X_BCRC_2, uc);
+      s->storedBlockCRC = (s->storedBlockCRC << 8) | ((UInt32)uc);
+      GET_UCHAR(BZ_X_BCRC_3, uc);
+      s->storedBlockCRC = (s->storedBlockCRC << 8) | ((UInt32)uc);
+      GET_UCHAR(BZ_X_BCRC_4, uc);
+      s->storedBlockCRC = (s->storedBlockCRC << 8) | ((UInt32)uc);
+
+      GET_BITS(BZ_X_RANDBIT, s->blockRandomised, 1);
+
+      s->origPtr = 0;
+      GET_UCHAR(BZ_X_ORIGPTR_1, uc);
+      s->origPtr = (s->origPtr << 8) | ((Int32)uc);
+      GET_UCHAR(BZ_X_ORIGPTR_2, uc);
+      s->origPtr = (s->origPtr << 8) | ((Int32)uc);
+      GET_UCHAR(BZ_X_ORIGPTR_3, uc);
+      s->origPtr = (s->origPtr << 8) | ((Int32)uc);
+
+      if (s->origPtr < 0)
+         RETURN(BZ_DATA_ERROR);
+      if (s->origPtr > 10 + 100000*s->blockSize100k)
+         RETURN(BZ_DATA_ERROR);
+
+      /*--- Receive the mapping table ---*/
+      for (i = 0; i < 16; i++) {
+         GET_BIT(BZ_X_MAPPING_1, uc);
+         if (uc == 1)
+            s->inUse16[i] = True; else
+            s->inUse16[i] = False;
+      }
+
+      for (i = 0; i < 256; i++) s->inUse[i] = False;
+
+      for (i = 0; i < 16; i++)
+         if (s->inUse16[i])
+            for (j = 0; j < 16; j++) {
+               GET_BIT(BZ_X_MAPPING_2, uc);
+               if (uc == 1) s->inUse[i * 16 + j] = True;
+            }
+      makeMaps_d ( s );
+      if (s->nInUse == 0) RETURN(BZ_DATA_ERROR);
+      alphaSize = s->nInUse+2;
+
+      /*--- Now the selectors ---*/
+      GET_BITS(BZ_X_SELECTOR_1, nGroups, 3);
+      if (nGroups < 2 || nGroups > 6) RETURN(BZ_DATA_ERROR);
+      GET_BITS(BZ_X_SELECTOR_2, nSelectors, 15);
+      if (nSelectors < 1) RETURN(BZ_DATA_ERROR);
+      for (i = 0; i < nSelectors; i++) {
+         j = 0;
+         while (True) {
+            GET_BIT(BZ_X_SELECTOR_3, uc);
+            if (uc == 0) break;
+            j++;
+            if (j >= nGroups) RETURN(BZ_DATA_ERROR);
+         }
+         s->selectorMtf[i] = j;
+      }
+
+      /*--- Undo the MTF values for the selectors. ---*/
+      {
+         UChar pos[BZ_N_GROUPS], tmp, v;
+         for (v = 0; v < nGroups; v++) pos[v] = v;
+
+         for (i = 0; i < nSelectors; i++) {
+            v = s->selectorMtf[i];
+            tmp = pos[v];
+            while (v > 0) { pos[v] = pos[v-1]; v--; }
+            pos[0] = tmp;
+            s->selector[i] = tmp;
+         }
+      }
+
+      /*--- Now the coding tables ---*/
+      for (t = 0; t < nGroups; t++) {
+         GET_BITS(BZ_X_CODING_1, curr, 5);
+         for (i = 0; i < alphaSize; i++) {
+            while (True) {
+               if (curr < 1 || curr > 20) RETURN(BZ_DATA_ERROR);
+               GET_BIT(BZ_X_CODING_2, uc);
+               if (uc == 0) break;
+               GET_BIT(BZ_X_CODING_3, uc);
+               if (uc == 0) curr++; else curr--;
+            }
+            s->len[t][i] = curr;
+         }
+      }
+
+      /*--- Create the Huffman decoding tables ---*/
+      for (t = 0; t < nGroups; t++) {
+         minLen = 32;
+         maxLen = 0;
+         for (i = 0; i < alphaSize; i++) {
+            if (s->len[t][i] > maxLen) maxLen = s->len[t][i];
+            if (s->len[t][i] < minLen) minLen = s->len[t][i];
+         }
+         BZ2_hbCreateDecodeTables (
+            &(s->limit[t][0]),
+            &(s->base[t][0]),
+            &(s->perm[t][0]),
+            &(s->len[t][0]),
+            minLen, maxLen, alphaSize
+         );
+         s->minLens[t] = minLen;
+      }
+
+      /*--- Now the MTF values ---*/
+
+      EOB      = s->nInUse+1;
+      nblockMAX = 100000 * s->blockSize100k;
+      groupNo  = -1;
+      groupPos = 0;
+
+      for (i = 0; i <= 255; i++) s->unzftab[i] = 0;
+
+      /*-- MTF init --*/
+      {
+         Int32 ii, jj, kk;
+         kk = MTFA_SIZE-1;
+         for (ii = 256 / MTFL_SIZE - 1; ii >= 0; ii--) {
+            for (jj = MTFL_SIZE-1; jj >= 0; jj--) {
+               s->mtfa[kk] = (UChar)(ii * MTFL_SIZE + jj);
+               kk--;
+            }
+            s->mtfbase[ii] = kk + 1;
+         }
+      }
+      /*-- end MTF init --*/
+
+      nblock = 0;
+      GET_MTF_VAL(BZ_X_MTF_1, BZ_X_MTF_2, nextSym);
+
+      while (True) {
+
+         if (nextSym == EOB) break;
+
+         if (nextSym == BZ_RUNA || nextSym == BZ_RUNB) {
+
+            es = -1;
+            N = 1;
+            do {
+               if (nextSym == BZ_RUNA) es = es + (0+1) * N; else
+               if (nextSym == BZ_RUNB) es = es + (1+1) * N;
+               N = N * 2;
+               GET_MTF_VAL(BZ_X_MTF_3, BZ_X_MTF_4, nextSym);
+            }
+               while (nextSym == BZ_RUNA || nextSym == BZ_RUNB);
+
+            es++;
+            uc = s->seqToUnseq[ s->mtfa[s->mtfbase[0]] ];
+            s->unzftab[uc] += es;
+
+            if (s->smallDecompress)
+               while (es > 0) {
+                  if (nblock >= nblockMAX) RETURN(BZ_DATA_ERROR);
+                  s->ll16[nblock] = (UInt16)uc;
+                  nblock++;
+                  es--;
+               }
+            else
+               while (es > 0) {
+                  if (nblock >= nblockMAX) RETURN(BZ_DATA_ERROR);
+                  s->tt[nblock] = (UInt32)uc;
+                  nblock++;
+                  es--;
+               };
+
+            continue;
+
+         } else {
+
+            if (nblock >= nblockMAX) RETURN(BZ_DATA_ERROR);
+
+            /*-- uc = MTF ( nextSym-1 ) --*/
+            {
+               Int32 ii, jj, kk, pp, lno, off;
+               UInt32 nn;
+               nn = (UInt32)(nextSym - 1);
+
+               if (nn < MTFL_SIZE) {
+                  /* avoid general-case expense */
+                  pp = s->mtfbase[0];
+                  uc = s->mtfa[pp+nn];
+                  while (nn > 3) {
+                     Int32 z = pp+nn;
+                     s->mtfa[(z)  ] = s->mtfa[(z)-1];
+                     s->mtfa[(z)-1] = s->mtfa[(z)-2];
+                     s->mtfa[(z)-2] = s->mtfa[(z)-3];
+                     s->mtfa[(z)-3] = s->mtfa[(z)-4];
+                     nn -= 4;
+                  }
+                  while (nn > 0) {
+                     s->mtfa[(pp+nn)] = s->mtfa[(pp+nn)-1]; nn--;
+                  };
+                  s->mtfa[pp] = uc;
+               } else {
+                  /* general case */
+                  lno = nn / MTFL_SIZE;
+                  off = nn % MTFL_SIZE;
+                  pp = s->mtfbase[lno] + off;
+                  uc = s->mtfa[pp];
+                  while (pp > s->mtfbase[lno]) {
+                     s->mtfa[pp] = s->mtfa[pp-1]; pp--;
+                  };
+                  s->mtfbase[lno]++;
+                  while (lno > 0) {
+                     s->mtfbase[lno]--;
+                     s->mtfa[s->mtfbase[lno]]
+                        = s->mtfa[s->mtfbase[lno-1] + MTFL_SIZE - 1];
+                     lno--;
+                  }
+                  s->mtfbase[0]--;
+                  s->mtfa[s->mtfbase[0]] = uc;
+                  if (s->mtfbase[0] == 0) {
+                     kk = MTFA_SIZE-1;
+                     for (ii = 256 / MTFL_SIZE-1; ii >= 0; ii--) {
+                        for (jj = MTFL_SIZE-1; jj >= 0; jj--) {
+                           s->mtfa[kk] = s->mtfa[s->mtfbase[ii] + jj];
+                           kk--;
+                        }
+                        s->mtfbase[ii] = kk + 1;
+                     }
+                  }
+               }
+            }
+            /*-- end uc = MTF ( nextSym-1 ) --*/
+
+            s->unzftab[s->seqToUnseq[uc]]++;
+            if (s->smallDecompress)
+               s->ll16[nblock] = (UInt16)(s->seqToUnseq[uc]); else
+               s->tt[nblock]   = (UInt32)(s->seqToUnseq[uc]);
+            nblock++;
+
+            GET_MTF_VAL(BZ_X_MTF_5, BZ_X_MTF_6, nextSym);
+            continue;
+         }
+      }
+
+      /* Now we know what nblock is, we can do a better sanity
+         check on s->origPtr.
+      */
+      if (s->origPtr < 0 || s->origPtr >= nblock)
+         RETURN(BZ_DATA_ERROR);
+
+      s->state_out_len = 0;
+      s->state_out_ch  = 0;
+      BZ_INITIALISE_CRC ( s->calculatedBlockCRC );
+      s->state = BZ_X_OUTPUT;
+      if (s->verbosity >= 2) VPrintf0 ( "rt+rld" );
+
+      /*-- Set up cftab to facilitate generation of T^(-1) --*/
+      s->cftab[0] = 0;
+      for (i = 1; i <= 256; i++) s->cftab[i] = s->unzftab[i-1];
+      for (i = 1; i <= 256; i++) s->cftab[i] += s->cftab[i-1];
+
+      if (s->smallDecompress) {
+
+         /*-- Make a copy of cftab, used in generation of T --*/
+         for (i = 0; i <= 256; i++) s->cftabCopy[i] = s->cftab[i];
+
+         /*-- compute the T vector --*/
+         for (i = 0; i < nblock; i++) {
+            uc = (UChar)(s->ll16[i]);
+            SET_LL(i, s->cftabCopy[uc]);
+            s->cftabCopy[uc]++;
+         }
+
+         /*-- Compute T^(-1) by pointer reversal on T --*/
+         i = s->origPtr;
+         j = GET_LL(i);
+         do {
+            Int32 tmp = GET_LL(j);
+            SET_LL(j, i);
+            i = j;
+            j = tmp;
+         }
+            while (i != s->origPtr);
+
+         s->tPos = s->origPtr;
+         s->nblock_used = 0;
+         if (s->blockRandomised) {
+            BZ_RAND_INIT_MASK;
+            BZ_GET_SMALL(s->k0); s->nblock_used++;
+            BZ_RAND_UPD_MASK; s->k0 ^= BZ_RAND_MASK;
+         } else {
+            BZ_GET_SMALL(s->k0); s->nblock_used++;
+         }
+
+      } else {
+
+         /*-- compute the T^(-1) vector --*/
+         for (i = 0; i < nblock; i++) {
+            uc = (UChar)(s->tt[i] & 0xff);
+            s->tt[s->cftab[uc]] |= (i << 8);
+            s->cftab[uc]++;
+         }
+
+         s->tPos = s->tt[s->origPtr] >> 8;
+         s->nblock_used = 0;
+         if (s->blockRandomised) {
+            BZ_RAND_INIT_MASK;
+            BZ_GET_FAST(s->k0); s->nblock_used++;
+            BZ_RAND_UPD_MASK; s->k0 ^= BZ_RAND_MASK;
+         } else {
+            BZ_GET_FAST(s->k0); s->nblock_used++;
+         }
+
+      }
+
+      RETURN(BZ_OK);
+
+
+
+    endhdr_2:
+
+      GET_UCHAR(BZ_X_ENDHDR_2, uc);
+      if (uc != 0x72) RETURN(BZ_DATA_ERROR);
+      GET_UCHAR(BZ_X_ENDHDR_3, uc);
+      if (uc != 0x45) RETURN(BZ_DATA_ERROR);
+      GET_UCHAR(BZ_X_ENDHDR_4, uc);
+      if (uc != 0x38) RETURN(BZ_DATA_ERROR);
+      GET_UCHAR(BZ_X_ENDHDR_5, uc);
+      if (uc != 0x50) RETURN(BZ_DATA_ERROR);
+      GET_UCHAR(BZ_X_ENDHDR_6, uc);
+      if (uc != 0x90) RETURN(BZ_DATA_ERROR);
+
+      s->storedCombinedCRC = 0;
+      GET_UCHAR(BZ_X_CCRC_1, uc);
+      s->storedCombinedCRC = (s->storedCombinedCRC << 8) | ((UInt32)uc);
+      GET_UCHAR(BZ_X_CCRC_2, uc);
+      s->storedCombinedCRC = (s->storedCombinedCRC << 8) | ((UInt32)uc);
+      GET_UCHAR(BZ_X_CCRC_3, uc);
+      s->storedCombinedCRC = (s->storedCombinedCRC << 8) | ((UInt32)uc);
+      GET_UCHAR(BZ_X_CCRC_4, uc);
+      s->storedCombinedCRC = (s->storedCombinedCRC << 8) | ((UInt32)uc);
+
+      s->state = BZ_X_IDLE;
+      RETURN(BZ_STREAM_END);
+
+      default: AssertH ( False, 4001 );
+   }
+
+   AssertH ( False, 4002 );
+
+   save_state_and_return:
+
+   s->save_i           = i;
+   s->save_j           = j;
+   s->save_t           = t;
+   s->save_alphaSize   = alphaSize;
+   s->save_nGroups     = nGroups;
+   s->save_nSelectors  = nSelectors;
+   s->save_EOB         = EOB;
+   s->save_groupNo     = groupNo;
+   s->save_groupPos    = groupPos;
+   s->save_nextSym     = nextSym;
+   s->save_nblockMAX   = nblockMAX;
+   s->save_nblock      = nblock;
+   s->save_es          = es;
+   s->save_N           = N;
+   s->save_curr        = curr;
+   s->save_zt          = zt;
+   s->save_zn          = zn;
+   s->save_zvec        = zvec;
+   s->save_zj          = zj;
+   s->save_gSel        = gSel;
+   s->save_gMinlen     = gMinlen;
+   s->save_gLimit      = gLimit;
+   s->save_gBase       = gBase;
+   s->save_gPerm       = gPerm;
+
+   return retVal;
+}
+
+
+/*-------------------------------------------------------------*/
+/*--- end                                      decompress.c ---*/
+/*-------------------------------------------------------------*/
+
+#endif /* CONFIG_BZIP2 */

lib_generic/bzlib_huffman.c

@@ -0,0 +1,232 @@
+#include <config.h>
+#ifdef CONFIG_BZIP2
+
+/*-------------------------------------------------------------*/
+/*--- Huffman coding low-level stuff                        ---*/
+/*---                                             huffman.c ---*/
+/*-------------------------------------------------------------*/
+
+/*--
+  This file is a part of bzip2 and/or libbzip2, a program and
+  library for lossless, block-sorting data compression.
+
+  Copyright (C) 1996-2002 Julian R Seward.  All rights reserved.
+
+  Redistribution and use in source and binary forms, with or without
+  modification, are permitted provided that the following conditions
+  are met:
+
+  1. Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+
+  2. The origin of this software must not be misrepresented; you must
+     not claim that you wrote the original software.  If you use this
+     software in a product, an acknowledgment in the product
+     documentation would be appreciated but is not required.
+
+  3. Altered source versions must be plainly marked as such, and must
+     not be misrepresented as being the original software.
+
+  4. The name of the author may not be used to endorse or promote
+     products derived from this software without specific prior written
+     permission.
+
+  THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+  OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+  DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+  GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+  WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+  Julian Seward, Cambridge, UK.
+  jseward@acm.org
+  bzip2/libbzip2 version 1.0 of 21 March 2000
+
+  This program is based on (at least) the work of:
+     Mike Burrows
+     David Wheeler
+     Peter Fenwick
+     Alistair Moffat
+     Radford Neal
+     Ian H. Witten
+     Robert Sedgewick
+     Jon L. Bentley
+
+  For more information on these sources, see the manual.
+--*/
+
+
+#include "bzlib_private.h"
+
+/*---------------------------------------------------*/
+#define WEIGHTOF(zz0)  ((zz0) & 0xffffff00)
+#define DEPTHOF(zz1)   ((zz1) & 0x000000ff)
+#define MYMAX(zz2,zz3) ((zz2) > (zz3) ? (zz2) : (zz3))
+
+#define ADDWEIGHTS(zw1,zw2)                           \
+   (WEIGHTOF(zw1)+WEIGHTOF(zw2)) |                    \
+   (1 + MYMAX(DEPTHOF(zw1),DEPTHOF(zw2)))
+
+#define UPHEAP(z)                                     \
+{                                                     \
+   Int32 zz, tmp;                                     \
+   zz = z; tmp = heap[zz];                            \
+   while (weight[tmp] < weight[heap[zz >> 1]]) {      \
+      heap[zz] = heap[zz >> 1];                       \
+      zz >>= 1;                                       \
+   }                                                  \
+   heap[zz] = tmp;                                    \
+}
+
+#define DOWNHEAP(z)                                   \
+{                                                     \
+   Int32 zz, yy, tmp;                                 \
+   zz = z; tmp = heap[zz];                            \
+   while (True) {                                     \
+      yy = zz << 1;                                   \
+      if (yy > nHeap) break;                          \
+      if (yy < nHeap &&                               \
+          weight[heap[yy+1]] < weight[heap[yy]])      \
+         yy++;                                        \
+      if (weight[tmp] < weight[heap[yy]]) break;      \
+      heap[zz] = heap[yy];                            \
+      zz = yy;                                        \
+   }                                                  \
+   heap[zz] = tmp;                                    \
+}
+
+
+/*---------------------------------------------------*/
+void BZ2_hbMakeCodeLengths ( UChar *len,
+                             Int32 *freq,
+                             Int32 alphaSize,
+                             Int32 maxLen )
+{
+   /*--
+      Nodes and heap entries run from 1.  Entry 0
+      for both the heap and nodes is a sentinel.
+   --*/
+   Int32 nNodes, nHeap, n1, n2, i, j, k;
+   Bool  tooLong;
+
+   Int32 heap   [ BZ_MAX_ALPHA_SIZE + 2 ];
+   Int32 weight [ BZ_MAX_ALPHA_SIZE * 2 ];
+   Int32 parent [ BZ_MAX_ALPHA_SIZE * 2 ];
+
+   for (i = 0; i < alphaSize; i++)
+      weight[i+1] = (freq[i] == 0 ? 1 : freq[i]) << 8;
+
+   while (True) {
+
+      nNodes = alphaSize;
+      nHeap = 0;
+
+      heap[0] = 0;
+      weight[0] = 0;
+      parent[0] = -2;
+
+      for (i = 1; i <= alphaSize; i++) {
+         parent[i] = -1;
+         nHeap++;
+         heap[nHeap] = i;
+         UPHEAP(nHeap);
+      }
+
+      AssertH( nHeap < (BZ_MAX_ALPHA_SIZE+2), 2001 );
+
+      while (nHeap > 1) {
+         n1 = heap[1]; heap[1] = heap[nHeap]; nHeap--; DOWNHEAP(1);
+         n2 = heap[1]; heap[1] = heap[nHeap]; nHeap--; DOWNHEAP(1);
+         nNodes++;
+         parent[n1] = parent[n2] = nNodes;
+         weight[nNodes] = ADDWEIGHTS(weight[n1], weight[n2]);
+         parent[nNodes] = -1;
+         nHeap++;
+         heap[nHeap] = nNodes;
+         UPHEAP(nHeap);
+      }
+
+      AssertH( nNodes < (BZ_MAX_ALPHA_SIZE * 2), 2002 );
+
+      tooLong = False;
+      for (i = 1; i <= alphaSize; i++) {
+         j = 0;
+         k = i;
+         while (parent[k] >= 0) { k = parent[k]; j++; }
+         len[i-1] = j;
+         if (j > maxLen) tooLong = True;
+      }
+
+      if (! tooLong) break;
+
+      for (i = 1; i < alphaSize; i++) {
+         j = weight[i] >> 8;
+         j = 1 + (j / 2);
+         weight[i] = j << 8;
+      }
+   }
+}
+
+
+/*---------------------------------------------------*/
+void BZ2_hbAssignCodes ( Int32 *code,
+                         UChar *length,
+                         Int32 minLen,
+                         Int32 maxLen,
+                         Int32 alphaSize )
+{
+   Int32 n, vec, i;
+
+   vec = 0;
+   for (n = minLen; n <= maxLen; n++) {
+      for (i = 0; i < alphaSize; i++)
+         if (length[i] == n) { code[i] = vec; vec++; };
+      vec <<= 1;
+   }
+}
+
+
+/*---------------------------------------------------*/
+void BZ2_hbCreateDecodeTables ( Int32 *limit,
+                                Int32 *base,
+                                Int32 *perm,
+                                UChar *length,
+                                Int32 minLen,
+                                Int32 maxLen,
+                                Int32 alphaSize )
+{
+   Int32 pp, i, j, vec;
+
+   pp = 0;
+   for (i = minLen; i <= maxLen; i++)
+      for (j = 0; j < alphaSize; j++)
+         if (length[j] == i) { perm[pp] = j; pp++; };
+
+   for (i = 0; i < BZ_MAX_CODE_LEN; i++) base[i] = 0;
+   for (i = 0; i < alphaSize; i++) base[length[i]+1]++;
+
+   for (i = 1; i < BZ_MAX_CODE_LEN; i++) base[i] += base[i-1];
+
+   for (i = 0; i < BZ_MAX_CODE_LEN; i++) limit[i] = 0;
+   vec = 0;
+
+   for (i = minLen; i <= maxLen; i++) {
+      vec += (base[i+1] - base[i]);
+      limit[i] = vec-1;
+      vec <<= 1;
+   }
+   for (i = minLen + 1; i <= maxLen; i++)
+      base[i] = ((limit[i-1] + 1) << 1) - base[i];
+}
+
+
+/*-------------------------------------------------------------*/
+/*--- end                                         huffman.c ---*/
+/*-------------------------------------------------------------*/
+
+#endif /* CONFIG_BZIP2 */

lib_generic/bzlib_private.h

@@ -0,0 +1,541 @@
+/*
+ * This file is a modified version of bzlib_private.h from the bzip2-1.0.2
+ * distribution which can be found at http://sources.redhat.com/bzip2/
+ */
+
+/*-------------------------------------------------------------*/
+/*--- Private header file for the library.                  ---*/
+/*---                                       bzlib_private.h ---*/
+/*-------------------------------------------------------------*/
+
+/*--
+  This file is a part of bzip2 and/or libbzip2, a program and
+  library for lossless, block-sorting data compression.
+
+  Copyright (C) 1996-2002 Julian R Seward.  All rights reserved.
+
+  Redistribution and use in source and binary forms, with or without
+  modification, are permitted provided that the following conditions
+  are met:
+
+  1. Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+
+  2. The origin of this software must not be misrepresented; you must
+     not claim that you wrote the original software.  If you use this
+     software in a product, an acknowledgment in the product
+     documentation would be appreciated but is not required.
+
+  3. Altered source versions must be plainly marked as such, and must
+     not be misrepresented as being the original software.
+
+  4. The name of the author may not be used to endorse or promote
+     products derived from this software without specific prior written
+     permission.
+
+  THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+  OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+  DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+  GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+  WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+  Julian Seward, Cambridge, UK.
+  jseward@acm.org
+  bzip2/libbzip2 version 1.0 of 21 March 2000
+
+  This program is based on (at least) the work of:
+     Mike Burrows
+     David Wheeler
+     Peter Fenwick
+     Alistair Moffat
+     Radford Neal
+     Ian H. Witten
+     Robert Sedgewick
+     Jon L. Bentley
+
+  For more information on these sources, see the manual.
+--*/
+
+
+#ifndef _BZLIB_PRIVATE_H
+#define _BZLIB_PRIVATE_H
+
+#include <malloc.h>
+
+#include "bzlib.h"
+
+#ifndef BZ_NO_STDIO
+#include <stdio.h>
+#include <ctype.h>
+#include <string.h>
+#endif
+
+
+
+/*-- General stuff. --*/
+
+#define BZ_VERSION  "1.0.2, 30-Dec-2001"
+
+typedef char            Char;
+typedef unsigned char   Bool;
+typedef unsigned char   UChar;
+typedef int             Int32;
+typedef unsigned int    UInt32;
+typedef short           Int16;
+typedef unsigned short  UInt16;
+
+#define True  ((Bool)1)
+#define False ((Bool)0)
+
+#ifndef __GNUC__
+#define __inline__  /* */
+#endif
+
+#ifndef BZ_NO_STDIO
+extern void BZ2_bz__AssertH__fail ( int errcode );
+#define AssertH(cond,errcode) \
+   { if (!(cond)) BZ2_bz__AssertH__fail ( errcode ); }
+#if BZ_DEBUG
+#define AssertD(cond,msg) \
+   { if (!(cond)) {       \
+      fprintf ( stderr,   \
+        "\n\nlibbzip2(debug build): internal error\n\t%s\n", msg );\
+      exit(1); \
+   }}
+#else
+#define AssertD(cond,msg) /* */
+#endif
+#define VPrintf0(zf) \
+   fprintf(stderr,zf)
+#define VPrintf1(zf,za1) \
+   fprintf(stderr,zf,za1)
+#define VPrintf2(zf,za1,za2) \
+   fprintf(stderr,zf,za1,za2)
+#define VPrintf3(zf,za1,za2,za3) \
+   fprintf(stderr,zf,za1,za2,za3)
+#define VPrintf4(zf,za1,za2,za3,za4) \
+   fprintf(stderr,zf,za1,za2,za3,za4)
+#define VPrintf5(zf,za1,za2,za3,za4,za5) \
+   fprintf(stderr,zf,za1,za2,za3,za4,za5)
+#else
+extern void bz_internal_error ( int errcode );
+#define AssertH(cond,errcode) \
+   { if (!(cond)) bz_internal_error ( errcode ); }
+#define AssertD(cond,msg) /* */
+#define VPrintf0(zf) /* */
+#define VPrintf1(zf,za1) /* */
+#define VPrintf2(zf,za1,za2) /* */
+#define VPrintf3(zf,za1,za2,za3) /* */
+#define VPrintf4(zf,za1,za2,za3,za4) /* */
+#define VPrintf5(zf,za1,za2,za3,za4,za5) /* */
+#endif
+
+
+#define BZALLOC(nnn) (strm->bzalloc)(strm->opaque,(nnn),1)
+#define BZFREE(ppp)  (strm->bzfree)(strm->opaque,(ppp))
+
+
+/*-- Header bytes. --*/
+
+#define BZ_HDR_B 0x42   /* 'B' */
+#define BZ_HDR_Z 0x5a   /* 'Z' */
+#define BZ_HDR_h 0x68   /* 'h' */
+#define BZ_HDR_0 0x30   /* '0' */
+
+/*-- Constants for the back end. --*/
+
+#define BZ_MAX_ALPHA_SIZE 258
+#define BZ_MAX_CODE_LEN    23
+
+#define BZ_RUNA 0
+#define BZ_RUNB 1
+
+#define BZ_N_GROUPS 6
+#define BZ_G_SIZE   50
+#define BZ_N_ITERS  4
+
+#define BZ_MAX_SELECTORS (2 + (900000 / BZ_G_SIZE))
+
+
+
+/*-- Stuff for randomising repetitive blocks. --*/
+
+extern Int32 BZ2_rNums[512];
+
+#define BZ_RAND_DECLS                          \
+   Int32 rNToGo;                               \
+   Int32 rTPos                                 \
+
+#define BZ_RAND_INIT_MASK                      \
+   s->rNToGo = 0;                              \
+   s->rTPos  = 0                               \
+
+#define BZ_RAND_MASK ((s->rNToGo == 1) ? 1 : 0)
+
+#define BZ_RAND_UPD_MASK                       \
+   if (s->rNToGo == 0) {                       \
+      s->rNToGo = BZ2_rNums[s->rTPos];         \
+      s->rTPos++;                              \
+      if (s->rTPos == 512) s->rTPos = 0;       \
+   }                                           \
+   s->rNToGo--;
+
+
+
+/*-- Stuff for doing CRCs. --*/
+
+extern UInt32 BZ2_crc32Table[256];
+
+#define BZ_INITIALISE_CRC(crcVar)              \
+{                                              \
+   crcVar = 0xffffffffL;                       \
+}
+
+#define BZ_FINALISE_CRC(crcVar)                \
+{                                              \
+   crcVar = ~(crcVar);                         \
+}
+
+#define BZ_UPDATE_CRC(crcVar,cha)              \
+{                                              \
+   crcVar = (crcVar << 8) ^                    \
+            BZ2_crc32Table[(crcVar >> 24) ^    \
+                           ((UChar)cha)];      \
+}
+
+
+
+/*-- States and modes for compression. --*/
+
+#define BZ_M_IDLE      1
+#define BZ_M_RUNNING   2
+#define BZ_M_FLUSHING  3
+#define BZ_M_FINISHING 4
+
+#define BZ_S_OUTPUT    1
+#define BZ_S_INPUT     2
+
+#define BZ_N_RADIX 2
+#define BZ_N_QSORT 12
+#define BZ_N_SHELL 18
+#define BZ_N_OVERSHOOT (BZ_N_RADIX + BZ_N_QSORT + BZ_N_SHELL + 2)
+
+
+
+
+/*-- Structure holding all the compression-side stuff. --*/
+
+typedef
+   struct {
+      /* pointer back to the struct bz_stream */
+      bz_stream* strm;
+
+      /* mode this stream is in, and whether inputting */
+      /* or outputting data */
+      Int32    mode;
+      Int32    state;
+
+      /* remembers avail_in when flush/finish requested */
+      UInt32   avail_in_expect;
+
+      /* for doing the block sorting */
+      UInt32*  arr1;
+      UInt32*  arr2;
+      UInt32*  ftab;
+      Int32    origPtr;
+
+      /* aliases for arr1 and arr2 */
+      UInt32*  ptr;
+      UChar*   block;
+      UInt16*  mtfv;
+      UChar*   zbits;
+
+      /* for deciding when to use the fallback sorting algorithm */
+      Int32    workFactor;
+
+      /* run-length-encoding of the input */
+      UInt32   state_in_ch;
+      Int32    state_in_len;
+      BZ_RAND_DECLS;
+
+      /* input and output limits and current posns */
+      Int32    nblock;
+      Int32    nblockMAX;
+      Int32    numZ;
+      Int32    state_out_pos;
+
+      /* map of bytes used in block */
+      Int32    nInUse;
+      Bool     inUse[256];
+      UChar    unseqToSeq[256];
+
+      /* the buffer for bit stream creation */
+      UInt32   bsBuff;
+      Int32    bsLive;
+
+      /* block and combined CRCs */
+      UInt32   blockCRC;
+      UInt32   combinedCRC;
+
+      /* misc administratium */
+      Int32    verbosity;
+      Int32    blockNo;
+      Int32    blockSize100k;
+
+      /* stuff for coding the MTF values */
+      Int32    nMTF;
+      Int32    mtfFreq    [BZ_MAX_ALPHA_SIZE];
+      UChar    selector   [BZ_MAX_SELECTORS];
+      UChar    selectorMtf[BZ_MAX_SELECTORS];
+
+      UChar    len     [BZ_N_GROUPS][BZ_MAX_ALPHA_SIZE];
+      Int32    code    [BZ_N_GROUPS][BZ_MAX_ALPHA_SIZE];
+      Int32    rfreq   [BZ_N_GROUPS][BZ_MAX_ALPHA_SIZE];
+      /* second dimension: only 3 needed; 4 makes index calculations faster */
+      UInt32   len_pack[BZ_MAX_ALPHA_SIZE][4];
+
+   }
+   EState;
+
+
+
+/*-- externs for compression. --*/
+
+extern void
+BZ2_blockSort ( EState* );
+
+extern void
+BZ2_compressBlock ( EState*, Bool );
+
+extern void
+BZ2_bsInitWrite ( EState* );
+
+extern void
+BZ2_hbAssignCodes ( Int32*, UChar*, Int32, Int32, Int32 );
+
+extern void
+BZ2_hbMakeCodeLengths ( UChar*, Int32*, Int32, Int32 );
+
+
+
+/*-- states for decompression. --*/
+
+#define BZ_X_IDLE        1
+#define BZ_X_OUTPUT      2
+
+#define BZ_X_MAGIC_1     10
+#define BZ_X_MAGIC_2     11
+#define BZ_X_MAGIC_3     12
+#define BZ_X_MAGIC_4     13
+#define BZ_X_BLKHDR_1    14
+#define BZ_X_BLKHDR_2    15
+#define BZ_X_BLKHDR_3    16
+#define BZ_X_BLKHDR_4    17
+#define BZ_X_BLKHDR_5    18
+#define BZ_X_BLKHDR_6    19
+#define BZ_X_BCRC_1      20
+#define BZ_X_BCRC_2      21
+#define BZ_X_BCRC_3      22
+#define BZ_X_BCRC_4      23
+#define BZ_X_RANDBIT     24
+#define BZ_X_ORIGPTR_1   25
+#define BZ_X_ORIGPTR_2   26
+#define BZ_X_ORIGPTR_3   27
+#define BZ_X_MAPPING_1   28
+#define BZ_X_MAPPING_2   29
+#define BZ_X_SELECTOR_1  30
+#define BZ_X_SELECTOR_2  31
+#define BZ_X_SELECTOR_3  32
+#define BZ_X_CODING_1    33
+#define BZ_X_CODING_2    34
+#define BZ_X_CODING_3    35
+#define BZ_X_MTF_1       36
+#define BZ_X_MTF_2       37
+#define BZ_X_MTF_3       38
+#define BZ_X_MTF_4       39
+#define BZ_X_MTF_5       40
+#define BZ_X_MTF_6       41
+#define BZ_X_ENDHDR_2    42
+#define BZ_X_ENDHDR_3    43
+#define BZ_X_ENDHDR_4    44
+#define BZ_X_ENDHDR_5    45
+#define BZ_X_ENDHDR_6    46
+#define BZ_X_CCRC_1      47
+#define BZ_X_CCRC_2      48
+#define BZ_X_CCRC_3      49
+#define BZ_X_CCRC_4      50
+
+
+
+/*-- Constants for the fast MTF decoder. --*/
+
+#define MTFA_SIZE 4096
+#define MTFL_SIZE 16
+
+
+
+/*-- Structure holding all the decompression-side stuff. --*/
+
+typedef
+   struct {
+      /* pointer back to the struct bz_stream */
+      bz_stream* strm;
+
+      /* state indicator for this stream */
+      Int32    state;
+
+      /* for doing the final run-length decoding */
+      UChar    state_out_ch;
+      Int32    state_out_len;
+      Bool     blockRandomised;
+      BZ_RAND_DECLS;
+
+      /* the buffer for bit stream reading */
+      UInt32   bsBuff;
+      Int32    bsLive;
+
+      /* misc administratium */
+      Int32    blockSize100k;
+      Bool     smallDecompress;
+      Int32    currBlockNo;
+      Int32    verbosity;
+
+      /* for undoing the Burrows-Wheeler transform */
+      Int32    origPtr;
+      UInt32   tPos;
+      Int32    k0;
+      Int32    unzftab[256];
+      Int32    nblock_used;
+      Int32    cftab[257];
+      Int32    cftabCopy[257];
+
+      /* for undoing the Burrows-Wheeler transform (FAST) */
+      UInt32   *tt;
+
+      /* for undoing the Burrows-Wheeler transform (SMALL) */
+      UInt16   *ll16;
+      UChar    *ll4;
+
+      /* stored and calculated CRCs */
+      UInt32   storedBlockCRC;
+      UInt32   storedCombinedCRC;
+      UInt32   calculatedBlockCRC;
+      UInt32   calculatedCombinedCRC;
+
+      /* map of bytes used in block */
+      Int32    nInUse;
+      Bool     inUse[256];
+      Bool     inUse16[16];
+      UChar    seqToUnseq[256];
+
+      /* for decoding the MTF values */
+      UChar    mtfa   [MTFA_SIZE];
+      Int32    mtfbase[256 / MTFL_SIZE];
+      UChar    selector   [BZ_MAX_SELECTORS];
+      UChar    selectorMtf[BZ_MAX_SELECTORS];
+      UChar    len  [BZ_N_GROUPS][BZ_MAX_ALPHA_SIZE];
+
+      Int32    limit  [BZ_N_GROUPS][BZ_MAX_ALPHA_SIZE];
+      Int32    base   [BZ_N_GROUPS][BZ_MAX_ALPHA_SIZE];
+      Int32    perm   [BZ_N_GROUPS][BZ_MAX_ALPHA_SIZE];
+      Int32    minLens[BZ_N_GROUPS];
+
+      /* save area for scalars in the main decompress code */
+      Int32    save_i;
+      Int32    save_j;
+      Int32    save_t;
+      Int32    save_alphaSize;
+      Int32    save_nGroups;
+      Int32    save_nSelectors;
+      Int32    save_EOB;
+      Int32    save_groupNo;
+      Int32    save_groupPos;
+      Int32    save_nextSym;
+      Int32    save_nblockMAX;
+      Int32    save_nblock;
+      Int32    save_es;
+      Int32    save_N;
+      Int32    save_curr;
+      Int32    save_zt;
+      Int32    save_zn;
+      Int32    save_zvec;
+      Int32    save_zj;
+      Int32    save_gSel;
+      Int32    save_gMinlen;
+      Int32*   save_gLimit;
+      Int32*   save_gBase;
+      Int32*   save_gPerm;
+
+   }
+   DState;
+
+
+
+/*-- Macros for decompression. --*/
+
+#define BZ_GET_FAST(cccc)                     \
+    s->tPos = s->tt[s->tPos];                 \
+    cccc = (UChar)(s->tPos & 0xff);           \
+    s->tPos >>= 8;
+
+#define BZ_GET_FAST_C(cccc)                   \
+    c_tPos = c_tt[c_tPos];                    \
+    cccc = (UChar)(c_tPos & 0xff);            \
+    c_tPos >>= 8;
+
+#define SET_LL4(i,n)                                          \
+   { if (((i) & 0x1) == 0)                                    \
+        s->ll4[(i) >> 1] = (s->ll4[(i) >> 1] & 0xf0) | (n); else    \
+        s->ll4[(i) >> 1] = (s->ll4[(i) >> 1] & 0x0f) | ((n) << 4);  \
+   }
+
+#define GET_LL4(i)                             \
+   ((((UInt32)(s->ll4[(i) >> 1])) >> (((i) << 2) & 0x4)) & 0xF)
+
+#define SET_LL(i,n)                          \
+   { s->ll16[i] = (UInt16)(n & 0x0000ffff);  \
+     SET_LL4(i, n >> 16);                    \
+   }
+
+#define GET_LL(i) \
+   (((UInt32)s->ll16[i]) | (GET_LL4(i) << 16))
+
+#define BZ_GET_SMALL(cccc)                            \
+      cccc = BZ2_indexIntoF ( s->tPos, s->cftab );    \
+      s->tPos = GET_LL(s->tPos);
+
+
+/*-- externs for decompression. --*/
+
+extern Int32
+BZ2_indexIntoF ( Int32, Int32* );
+
+extern Int32
+BZ2_decompress ( DState* );
+
+extern void
+BZ2_hbCreateDecodeTables ( Int32*, Int32*, Int32*, UChar*,
+                           Int32,  Int32, Int32 );
+
+
+#endif
+
+
+/*-- BZ_NO_STDIO seems to make NULL disappear on some platforms. --*/
+
+#ifdef BZ_NO_STDIO
+#ifndef NULL
+#define NULL 0
+#endif
+#endif
+
+
+/*-------------------------------------------------------------*/
+/*--- end                                   bzlib_private.h ---*/
+/*-------------------------------------------------------------*/

lib_generic/bzlib_randtable.c

@@ -0,0 +1,128 @@
+#include <config.h>
+#ifdef CONFIG_BZIP2
+
+/*-------------------------------------------------------------*/
+/*--- Table for randomising repetitive blocks               ---*/
+/*---                                           randtable.c ---*/
+/*-------------------------------------------------------------*/
+
+/*--
+  This file is a part of bzip2 and/or libbzip2, a program and
+  library for lossless, block-sorting data compression.
+
+  Copyright (C) 1996-2002 Julian R Seward.  All rights reserved.
+
+  Redistribution and use in source and binary forms, with or without
+  modification, are permitted provided that the following conditions
+  are met:
+
+  1. Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+
+  2. The origin of this software must not be misrepresented; you must
+     not claim that you wrote the original software.  If you use this
+     software in a product, an acknowledgment in the product
+     documentation would be appreciated but is not required.
+
+  3. Altered source versions must be plainly marked as such, and must
+     not be misrepresented as being the original software.
+
+  4. The name of the author may not be used to endorse or promote
+     products derived from this software without specific prior written
+     permission.
+
+  THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+  OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+  DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+  GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+  WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+  Julian Seward, Cambridge, UK.
+  jseward@acm.org
+  bzip2/libbzip2 version 1.0 of 21 March 2000
+
+  This program is based on (at least) the work of:
+     Mike Burrows
+     David Wheeler
+     Peter Fenwick
+     Alistair Moffat
+     Radford Neal
+     Ian H. Witten
+     Robert Sedgewick
+     Jon L. Bentley
+
+  For more information on these sources, see the manual.
+--*/
+
+
+#include "bzlib_private.h"
+
+
+/*---------------------------------------------*/
+Int32 BZ2_rNums[512] = {
+   619, 720, 127, 481, 931, 816, 813, 233, 566, 247,
+   985, 724, 205, 454, 863, 491, 741, 242, 949, 214,
+   733, 859, 335, 708, 621, 574, 73, 654, 730, 472,
+   419, 436, 278, 496, 867, 210, 399, 680, 480, 51,
+   878, 465, 811, 169, 869, 675, 611, 697, 867, 561,
+   862, 687, 507, 283, 482, 129, 807, 591, 733, 623,
+   150, 238, 59, 379, 684, 877, 625, 169, 643, 105,
+   170, 607, 520, 932, 727, 476, 693, 425, 174, 647,
+   73, 122, 335, 530, 442, 853, 695, 249, 445, 515,
+   909, 545, 703, 919, 874, 474, 882, 500, 594, 612,
+   641, 801, 220, 162, 819, 984, 589, 513, 495, 799,
+   161, 604, 958, 533, 221, 400, 386, 867, 600, 782,
+   382, 596, 414, 171, 516, 375, 682, 485, 911, 276,
+   98, 553, 163, 354, 666, 933, 424, 341, 533, 870,
+   227, 730, 475, 186, 263, 647, 537, 686, 600, 224,
+   469, 68, 770, 919, 190, 373, 294, 822, 808, 206,
+   184, 943, 795, 384, 383, 461, 404, 758, 839, 887,
+   715, 67, 618, 276, 204, 918, 873, 777, 604, 560,
+   951, 160, 578, 722, 79, 804, 96, 409, 713, 940,
+   652, 934, 970, 447, 318, 353, 859, 672, 112, 785,
+   645, 863, 803, 350, 139, 93, 354, 99, 820, 908,
+   609, 772, 154, 274, 580, 184, 79, 626, 630, 742,
+   653, 282, 762, 623, 680, 81, 927, 626, 789, 125,
+   411, 521, 938, 300, 821, 78, 343, 175, 128, 250,
+   170, 774, 972, 275, 999, 639, 495, 78, 352, 126,
+   857, 956, 358, 619, 580, 124, 737, 594, 701, 612,
+   669, 112, 134, 694, 363, 992, 809, 743, 168, 974,
+   944, 375, 748, 52, 600, 747, 642, 182, 862, 81,
+   344, 805, 988, 739, 511, 655, 814, 334, 249, 515,
+   897, 955, 664, 981, 649, 113, 974, 459, 893, 228,
+   433, 837, 553, 268, 926, 240, 102, 654, 459, 51,
+   686, 754, 806, 760, 493, 403, 415, 394, 687, 700,
+   946, 670, 656, 610, 738, 392, 760, 799, 887, 653,
+   978, 321, 576, 617, 626, 502, 894, 679, 243, 440,
+   680, 879, 194, 572, 640, 724, 926, 56, 204, 700,
+   707, 151, 457, 449, 797, 195, 791, 558, 945, 679,
+   297, 59, 87, 824, 713, 663, 412, 693, 342, 606,
+   134, 108, 571, 364, 631, 212, 174, 643, 304, 329,
+   343, 97, 430, 751, 497, 314, 983, 374, 822, 928,
+   140, 206, 73, 263, 980, 736, 876, 478, 430, 305,
+   170, 514, 364, 692, 829, 82, 855, 953, 676, 246,
+   369, 970, 294, 750, 807, 827, 150, 790, 288, 923,
+   804, 378, 215, 828, 592, 281, 565, 555, 710, 82,
+   896, 831, 547, 261, 524, 462, 293, 465, 502, 56,
+   661, 821, 976, 991, 658, 869, 905, 758, 745, 193,
+   768, 550, 608, 933, 378, 286, 215, 979, 792, 961,
+   61, 688, 793, 644, 986, 403, 106, 366, 905, 644,
+   372, 567, 466, 434, 645, 210, 389, 550, 919, 135,
+   780, 773, 635, 389, 707, 100, 626, 958, 165, 504,
+   920, 176, 193, 713, 857, 265, 203, 50, 668, 108,
+   645, 990, 626, 197, 510, 357, 358, 850, 858, 364,
+   936, 638
+};
+
+
+/*-------------------------------------------------------------*/
+/*--- end                                       randtable.c ---*/
+/*-------------------------------------------------------------*/
+
+#endif /* CONFIG_BZIP2 */

lib_ppc/board.c

@@ -632,7 +632,7 @@ void board_init_r (gd_t *id, ulong dest_addr)
 	puts ("FLASH: ");
 
 	if ((flash_size = flash_init ()) > 0) {
-#ifdef CFG_FLASH_CHECKSUM
+# ifdef CFG_FLASH_CHECKSUM
 		print_size (flash_size, "");
 		/*
 		 * Compute and print flash CRC if flashchecksum is set to 'y'
@@ -648,9 +648,9 @@ void board_init_r (gd_t *id, ulong dest_addr)
 					);
 		}
 		putc ('\n');
-#else
+# else	/* !CFG_FLASH_CHECKSUM */
 		print_size (flash_size, "\n");
-#endif /* CFG_FLASH_CHECKSUM */
+# endif /* CFG_FLASH_CHECKSUM */
 	} else {
 		puts (failed);
 		hang ();
@@ -658,14 +658,14 @@ void board_init_r (gd_t *id, ulong dest_addr)
 
 	bd->bi_flashstart = CFG_FLASH_BASE;	/* update start of FLASH memory    */
 	bd->bi_flashsize = flash_size;	/* size of FLASH memory (final value) */
-#if defined(CONFIG_PCU_E) || defined(CONFIG_OXC)
+# if defined(CONFIG_PCU_E) || defined(CONFIG_OXC)
 	bd->bi_flashoffset = 0;
-#elif CFG_MONITOR_BASE == CFG_FLASH_BASE
+# elif CFG_MONITOR_BASE == CFG_FLASH_BASE
 	bd->bi_flashoffset = monitor_flash_len;	/* reserved area for startup monitor  */
-#else
+# else
 	bd->bi_flashoffset = 0;
-#endif
-#else
+# endif
+#else	/* CFG_NO_FLASH */
 
 	bd->bi_flashsize = 0;
 	bd->bi_flashstart = 0;

net/bootp.c

@@ -174,6 +174,11 @@ static void BootpVendorFieldProcess(u8 *ext)
 		if (NetOurDNSIP == 0) {
 			NetCopyIP(&NetOurDNSIP, (IPaddr_t*)(ext+2));
 		}
+#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_DNS2)
+		if ((NetOurDNS2IP == 0) && (size > 4)) {
+			NetCopyIP(&NetOurDNS2IP, (IPaddr_t*)(ext+2+4));
+		}
+#endif
 		break;
 	case 7:		/* Log server - Not yet supported		*/
 		break;
@@ -365,6 +370,9 @@ static int DhcpExtended(u8 *e, int message_type, IPaddr_t ServerID, IPaddr_t Req
 #if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_VENDOREX)
     u8 *x;
 #endif
+#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_SEND_HOSTNAME)
+    uchar *hostname;
+#endif
 
     *e++ =  99;		/* RFC1048 Magic Cookie */
     *e++ = 130;
@@ -402,6 +410,16 @@ static int DhcpExtended(u8 *e, int message_type, IPaddr_t ServerID, IPaddr_t Req
 	    *e++ = tmp & 0xff;
     }
 
+#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_SEND_HOSTNAME)
+    if ( (hostname = getenv("hostname")) ) {
+	    int hostnamelen = strlen(hostname);
+	    *e++ = 12;        /* Hostname */
+	    *e++ = hostnamelen;
+	    memcpy(e,hostname,hostnamelen);
+	    e += hostnamelen;
+    }
+#endif
+
 #if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_VENDOREX)
     if ((x = dhcp_vendorex_prep (e)))
 	return x - start ;
@@ -690,6 +708,11 @@ static void DhcpOptionsProcess(uchar *popt)
 				break;
 			case  6:
 				NetCopyIP(&NetOurDNSIP, (popt+2));
+#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_DNS2)
+				if ( *(popt+1) > 4 ) {
+					NetCopyIP(&NetOurDNS2IP, (popt+2+4));
+				}
+#endif
 				break;
 			case 12:
 				size = truncate_sz ("Host Name",

net/net.c

@@ -84,6 +84,9 @@
 IPaddr_t	NetOurSubnetMask=0;		/* Our subnet mask (0=unknown)	*/
 IPaddr_t	NetOurGatewayIP=0;		/* Our gateways IP address	*/
 IPaddr_t	NetOurDNSIP=0;			/* Our DNS IP address		*/
+#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_DNS2)
+IPaddr_t	NetOurDNS2IP=0;			/* Our 2nd DNS IP address	*/
+#endif
 char		NetOurNISDomain[32]={0,};	/* Our NIS domain		*/
 char		NetOurHostName[32]={0,};	/* Our hostname			*/
 char		NetOurRootPath[64]={0,};	/* Our bootpath			*/