Prepare v2008.10 release: update CHANGELOG & Makefile

Signed-off-by: Wolfgang Denk <wd@denx.de>

MAINTAINERS

@@ -594,6 +594,10 @@ Greg Ungerer <greg.ungerer@opengear.com>
 	cm4116		ks8695p
 	cm4148		ks8695p
 
+Hugo Villeneuve <hugo.villeneuve@lyrtech.com>
+
+	SFFSDR		ARM926EJS
+
 Richard Woodruff <r-woodruff2@ti.com>
 
 	omap2420h4	ARM1136EJS

Makefile

@@ -24,7 +24,7 @@
 VERSION = 2008
 PATCHLEVEL = 10
 SUBLEVEL =
-EXTRAVERSION = -rc2
+EXTRAVERSION =
 ifneq "$(SUBLEVEL)" ""
 U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
 else

README.imx31

@@ -1,13 +0,0 @@
-i.MX31 specific Configuration Options:
---------------------------------------
-
-- Timer precision:
-		CONFIG_MX31_TIMER_HIGH_PRECISION
-
-		Enable higher precision timer. The low-precision timer
-		(default) provides approximately 4% error, whereas the
-		high-precision timer is about 0.4% accurate. The extra
-		accuracy is achieved at the cost of higher computational
-		overhead, which, in places where time is measured, should
-		not be critical, so, it should be safe to enable this
-		option.

api/api_platform-ppc.c

@@ -66,7 +66,7 @@ int platform_sys_info(struct sys_info *si)
 	si->bar = gd->bd->bi_bar;
 #undef bi_bar
 #else
-	si->bar = NULL;
+	si->bar = 0;
 #endif
 
 	platform_set_mr(si, gd->bd->bi_memstart, gd->bd->bi_memsize, MR_ATTR_DRAM);

api/api_storage.c

@@ -30,6 +30,10 @@
 #include <common.h>
 #include <api_public.h>
 
+#if defined(CONFIG_CMD_USB) && defined(CONFIG_USB_STORAGE)
+#include <usb.h>
+#endif
+
 #define DEBUG
 #undef DEBUG
 

board/amcc/canyonlands/canyonlands.c

@@ -460,12 +460,8 @@ void ft_board_setup(void *blob, bd_t *bd)
 		 * node in the device tree, so that Linux doesn't initialize
 		 * it.
 		 */
-		rc = fdt_find_and_setprop(blob, "/plb/pciex@d00000000", "status",
-					  "disabled", sizeof("disabled"), 1);
-		if (rc) {
-			printf("Unable to update property status in PCIe node, err=%s\n",
-			       fdt_strerror(rc));
-		}
+		fdt_find_and_setprop(blob, "/plb/pciex@d00000000", "status",
+				     "disabled", sizeof("disabled"), 1);
 	}
 
 	if (gd->board_type == BOARD_CANYONLANDS_PCIE) {
@@ -474,12 +470,8 @@ void ft_board_setup(void *blob, bd_t *bd)
 		 * node in the device tree, so that Linux doesn't initialize
 		 * it.
 		 */
-		rc = fdt_find_and_setprop(blob, "/plb/sata@bffd1000", "status",
-					  "disabled", sizeof("disabled"), 1);
-		if (rc) {
-			printf("Unable to update property status in PCIe node, err=%s\n",
-			       fdt_strerror(rc));
-		}
+		fdt_find_and_setprop(blob, "/plb/sata@bffd1000", "status",
+				     "disabled", sizeof("disabled"), 1);
 	}
 }
 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */

board/davinci/sffsdr/sffsdr.c

@@ -170,9 +170,5 @@ int misc_init_r(void)
 	if (!eth_hw_init())
 		printf("Ethernet init failed\n");
 
-	/* On this platform, U-Boot is copied in RAM by the UBL,
-	 * so we are always in the relocated state. */
-	gd->flags |= GD_FLG_RELOC;
-
 	return(0);
 }

board/esd/du440/du440.c

@@ -52,15 +52,15 @@ int board_early_init_f(void)
 	 * Setup the GPIO pins
 	 */
 	out_be32((void*)GPIO0_OR, 0x00000000 | CFG_GPIO0_EP_EEP);
-	out_be32((void*)GPIO0_TCR, 0x0000000f | CFG_GPIO0_EP_EEP);
+	out_be32((void*)GPIO0_TCR, 0x0000001f | CFG_GPIO0_EP_EEP);
 	out_be32((void*)GPIO0_OSRL, 0x50055400);
-	out_be32((void*)GPIO0_OSRH, 0x550050aa);
+	out_be32((void*)GPIO0_OSRH, 0x55005000);
 	out_be32((void*)GPIO0_TSRL, 0x50055400);
 	out_be32((void*)GPIO0_TSRH, 0x55005000);
 	out_be32((void*)GPIO0_ISR1L, 0x50000000);
 	out_be32((void*)GPIO0_ISR1H, 0x00000000);
 	out_be32((void*)GPIO0_ISR2L, 0x00000000);
-	out_be32((void*)GPIO0_ISR2H, 0x00000100);
+	out_be32((void*)GPIO0_ISR2H, 0x00000000);
 	out_be32((void*)GPIO0_ISR3L, 0x00000000);
 	out_be32((void*)GPIO0_ISR3H, 0x00000000);
 
@@ -73,9 +73,9 @@ int board_early_init_f(void)
 		 CFG_GPIO1_LEDPOST |
 		 CFG_GPIO1_LEDDU);
 	out_be32((void*)GPIO1_ODR, CFG_GPIO1_LEDDU);
-	out_be32((void*)GPIO1_OSRL, 0x5c280000);
+	out_be32((void*)GPIO1_OSRL, 0x0c280000);
 	out_be32((void*)GPIO1_OSRH, 0x00000000);
-	out_be32((void*)GPIO1_TSRL, 0x0c000000);
+	out_be32((void*)GPIO1_TSRL, 0xcc000000);
 	out_be32((void*)GPIO1_TSRH, 0x00000000);
 	out_be32((void*)GPIO1_ISR1L, 0x00005550);
 	out_be32((void*)GPIO1_ISR1H, 0x00000000);
@@ -169,6 +169,7 @@ int misc_init_r(void)
 	unsigned long usb2d0cr = 0;
 	unsigned long usb2phy0cr, usb2h0cr = 0;
 	unsigned long sdr0_pfc1;
+	unsigned long sdr0_srst0, sdr0_srst1;
 	int i, j;
 
 	/* adjust flash start and offset */
@@ -223,10 +224,38 @@ int misc_init_r(void)
 	mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 	mtsdr(SDR0_USB2H0CR, usb2h0cr);
 
-	/* clear resets */
-	udelay (1000);
+	/*
+	 * Take USB out of reset:
+	 * -Initial status = all cores are in reset
+	 * -deassert reset to OPB1, P4OPB0, OPB2, PLB42OPB1 OPB2PLB40 cores
+	 * -wait 1 ms
+	 * -deassert reset to PHY
+	 * -wait 1 ms
+	 * -deassert  reset to HOST
+	 * -wait 4 ms
+	 * -deassert all other resets
+	 */
+	mfsdr(SDR0_SRST1, sdr0_srst1);
+	sdr0_srst1 &= ~(SDR0_SRST1_OPBA1 |		\
+			SDR0_SRST1_P4OPB0 |		\
+			SDR0_SRST1_OPBA2 |		\
+			SDR0_SRST1_PLB42OPB1 |		\
+			SDR0_SRST1_OPB2PLB40);
+	mtsdr(SDR0_SRST1, sdr0_srst1);
+	udelay(1000);
+
+	mfsdr(SDR0_SRST1, sdr0_srst1);
+	sdr0_srst1 &= ~SDR0_SRST1_USB20PHY;
+	mtsdr(SDR0_SRST1, sdr0_srst1);
+	udelay(1000);
+
+	mfsdr(SDR0_SRST0, sdr0_srst0);
+	sdr0_srst0 &= ~SDR0_SRST0_USB2H;
+	mtsdr(SDR0_SRST0, sdr0_srst0);
+	udelay(4000);
+
+	/* finally all the other resets */
 	mtsdr(SDR0_SRST1, 0x00000000);
-	udelay (1000);
 	mtsdr(SDR0_SRST0, 0x00000000);
 
 	printf("USB:   Host(int phy)\n");
@@ -733,6 +762,12 @@ int do_setup_boot_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 			/* sdsdp[1]=0x095fa030; */
 			sdsdp[2] = 0x40082350;
 			sdsdp[3] = 0x0d050000;
+		} else if (!strcmp(argv[1], "667-166")) {
+			printf("Bootstrapping for 667-166MHz\n");
+			sdsdp[0] = 0x8778a252;
+			sdsdp[1] = 0x09d7a030;
+			sdsdp[2] = 0x40082350;
+			sdsdp[3] = 0x0d050000;
 		}
 	} else {
 		printf("Bootstrapping for 533MHz (default)\n");

board/freescale/common/fsl_diu_fb.c

@@ -242,10 +242,10 @@ int fsl_diu_init(int xres,
 			printf("Unable to allocate fb memory 1\n");
 			return -1;
 		}
-	} else {
-		memset(info->screen_base, 0, info->smem_len);
 	}
 
+	memset(info->screen_base, 0, info->smem_len);
+
 	dr.diu_reg->desc[0] = (unsigned int) &dummy_ad;
 	dr.diu_reg->desc[1] = (unsigned int) &dummy_ad;
 	dr.diu_reg->desc[2] = (unsigned int) &dummy_ad;
@@ -403,7 +403,7 @@ static int map_video_memory(struct fb_info *info, unsigned long bytes_align)
 	mask = bytes_align - 1;
 	offset = (unsigned long)info->screen_base & mask;
 	if (offset) {
-		info->screen_base += offset;
+		info->screen_base += (bytes_align - offset);
 		info->smem_len = info->smem_len - (bytes_align - offset);
 	} else
 		info->smem_len = info->smem_len - bytes_align;

board/freescale/common/sys_eeprom.c

@@ -463,6 +463,6 @@ unsigned int get_cpu_board_revision(void)
 	if ((be.major == 0xff) && (be.minor == 0xff))
 		return MPC85XX_CPU_BOARD_REV(0, 0);
 
-	return MPC85XX_CPU_BOARD_REV(e.major, e.minor);
+	return MPC85XX_CPU_BOARD_REV(be.major, be.minor);
 }
 #endif

board/freescale/mpc8313erdb/sdram.c

@@ -64,7 +64,7 @@ static long fixed_sdram(void)
 	volatile immap_t *im = (volatile immap_t *)CFG_IMMR;
 	u32 msize_log2 = __ilog2(msize);
 
-	im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE >> 12;
+	im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE & 0xfffff000;
 	im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
 	im->sysconf.ddrcdr = CFG_DDRCDR_VALUE;
 

board/freescale/mpc8315erdb/sdram.c

@@ -60,7 +60,7 @@ static long fixed_sdram(void)
 	u32 msize = CFG_DDR_SIZE * 1024 * 1024;
 	u32 msize_log2 = __ilog2(msize);
 
-	im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE >> 12;
+	im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE  & 0xfffff000;
 	im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
 	im->sysconf.ddrcdr = CFG_DDRCDR_VALUE;
 

board/freescale/mpc8349emds/mpc8349emds.c

@@ -109,7 +109,7 @@ int fixed_sdram(void)
 			return -1;
 		}
 	}
-	im->sysconf.ddrlaw[0].bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
+	im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE & 0xfffff000;
 	im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
 
 #if (CFG_DDR_SIZE != 256)

board/freescale/mpc8349itx/mpc8349itx.c

@@ -55,7 +55,7 @@ int fixed_sdram(void)
 
 	im->sysconf.ddrlaw[0].ar =
 	    LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
-	im->sysconf.ddrlaw[0].bar = (CFG_DDR_SDRAM_BASE >> 12) & 0xfffff;
+	im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE & 0xfffff000;
 
 	/* Only one CS0 for DDR */
 	im->ddr.csbnds[0].csbnds = 0x0000000f;

board/freescale/mpc837xemds/mpc837xemds.c

@@ -108,7 +108,7 @@ int fixed_sdram(void)
 	u32 msize = CFG_DDR_SIZE * 1024 * 1024;
 	u32 msize_log2 = __ilog2(msize);
 
-	im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE >> 12;
+	im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE & 0xfffff000;
 	im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
 
 #if (CFG_DDR_SIZE != 512)

board/freescale/mpc837xerdb/mpc837xerdb.c

@@ -96,7 +96,7 @@ int fixed_sdram(void)
 	u32 msize = CFG_DDR_SIZE * 1024 * 1024;
 	u32 msize_log2 = __ilog2(msize);
 
-	im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE >> 12;
+	im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE & 0xfffff000;
 	im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
 
 	im->sysconf.ddrcdr = CFG_DDRCDR_VALUE;

board/freescale/mpc8536ds/mpc8536ds.c

@@ -608,6 +608,17 @@ get_board_ddr_clk(ulong dummy)
 }
 #endif
 
+int is_sata_supported(void)
+{
+	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+	uint sdrs2_io_sel =
+		(gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27;
+	if (sdrs2_io_sel & 0x04)
+		return 0;
+
+	return 1;
+}
+
 #if defined(CONFIG_OF_BOARD_SETUP)
 void
 ft_board_setup(void *blob, bd_t *bd)

board/matrix_vision/mvblm7/mvblm7.c

@@ -50,7 +50,7 @@ int fixed_sdram(void)
 		if (ddr_size & 1)
 			return -1;
 	}
-	im->sysconf.ddrlaw[0].bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
+	im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE & 0xfffff000;
 	im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) &
 		LAWAR_SIZE);
 

board/ms7722se/lowlevel_init.S

@@ -43,48 +43,61 @@
 
 lowlevel_init:
 
-	mov.l	CCR_A, r1	! Address of Cache Control Register
-	mov.l	CCR_D, r0	! Instruction Cache Invalidate
+	/* Address of Cache Control Register */
+	mov.l	CCR_A, r1
+	/*Instruction Cache Invalidate */
+	mov.l	CCR_D, r0
 	mov.l	r0, @r1
 
-	mov.l	MMUCR_A, r1	! Address of MMU Control Register
-	mov.l	MMUCR_D, r0	! TI == TLB Invalidate bit
+	/* Address of MMU Control Register */
+	mov.l	MMUCR_A, r1
+	/* TI == TLB Invalidate bit */
+	mov.l	MMUCR_D, r0
 	mov.l	r0, @r1
 
-	mov.l	MSTPCR0_A, r1	! Address of Power Control Register 0
-	mov.l	MSTPCR0_D, r0	!
+	/* Address of Power Control Register 0 */
+	mov.l	MSTPCR0_A, r1
+	mov.l	MSTPCR0_D, r0
 	mov.l	r0, @r1
 
-	mov.l	MSTPCR2_A, r1	! Address of Power Control Register 2
-	mov.l	MSTPCR2_D, r0	!
+	/* Address of Power Control Register 2 */
+	mov.l	MSTPCR2_A, r1
+	mov.l	MSTPCR2_D, r0
 	mov.l	r0, @r1
 
-	mov.l	SBSCR_A, r1	!
-	mov.w	SBSCR_D, r0	!
+	mov.l	SBSCR_A, r1
+	mov.w	SBSCR_D, r0
 	mov.w	r0, @r1
 
-	mov.l	PSCR_A, r1	!
-	mov.w	PSCR_D, r0	!
+	mov.l	PSCR_A, r1
+	mov.w	PSCR_D, r0
 	mov.w	r0, @r1
 
-!	mov.l	RWTCSR_A, r1	! 0xA4520004 (Watchdog Control / Status Register)
-!	mov.w	RWTCSR_D_1, r0	! 0xA507 -> timer_STOP/WDT_CLK=max
+	/* 0xA4520004 (Watchdog Control / Status Register) */
+!	mov.l	RWTCSR_A, r1
+	/* 0xA507 -> timer_STOP/WDT_CLK=max */
+!	mov.w	RWTCSR_D_1, r0
 !	mov.w	r0, @r1
 
-	mov.l	RWTCNT_A, r1	! 0xA4520000 (Watchdog Count Register)
-	mov.w	RWTCNT_D, r0	! 0x5A00 -> Clear
+	/* 0xA4520000 (Watchdog Count Register) */
+	mov.l	RWTCNT_A, r1
+	/*0x5A00 -> Clear */
+	mov.w	RWTCNT_D, r0
 	mov.w	r0, @r1
 
-	mov.l	RWTCSR_A, r1	! 0xA4520004 (Watchdog Control / Status Register)
-	mov.w	RWTCSR_D_2, r0	! 0xA504 -> timer_STOP/CLK=500ms
+	/* 0xA4520004 (Watchdog Control / Status Register) */
+	mov.l	RWTCSR_A, r1
+	/* 0xA504 -> timer_STOP/CLK=500ms */
+	mov.w	RWTCSR_D_2, r0
 	mov.w	r0, @r1
 
-	mov.l	FRQCR_A, r1		! 0xA4150000 Frequency control register
+	/* 0xA4150000 Frequency control register */
+	mov.l	FRQCR_A, r1
 	mov.l	FRQCR_D, r0	!
 	mov.l	r0, @r1
 
-	mov.l	CCR_A, r1		! Address of Cache Control Register
-	mov.l	CCR_D_2, r0	! ??
+	mov.l	CCR_A, r1
+	mov.l	CCR_D_2, r0
 	mov.l	r0, @r1
 
 bsc_init:
@@ -290,5 +303,6 @@ PSCR_D:		.word	0x0000
 RWTCSR_D_1:	.word	0xA507
 RWTCSR_D_2:	.word	0xA507
 RWTCNT_D:	.word	0x5A00
+	.align	2
 
 SR_MASK_D:	.long	0xEFFFFF0F

board/r7780mp/lowlevel_init.S

@@ -325,8 +325,9 @@ repeat2:
 RWTCSR_D_1:				.word	0xA507
 RWTCSR_D_2:				.word	0xA507
 RWTCNT_D:				.word	0x5A00
+	.align	2
 
-BBG_PMMR_A:			.long	0xFF800010
+BBG_PMMR_A:				.long	0xFF800010
 BBG_PMSR1_A:			.long	0xFF800014
 BBG_PMSR2_A:			.long	0xFF800018
 BBG_PMSR3_A:			.long	0xFF80001C

board/rsk7203/rsk7203.c

@@ -48,3 +48,24 @@ int dram_init(void)
 void led_set_state(unsigned short value)
 {
 }
+
+/*
+ * The RSK board has the SMSC9118 wired up 'incorrectly'.
+ * Byte-swapping is necessary, and so poor performance is inevitable.
+ * This problem cannot evade by the swap function of CHIP, this can
+ * evade by software Byte-swapping.
+ * And this has problem by FIFO access only. pkt_data_pull/pkt_data_push
+ * functions necessary to solve this problem.
+ */
+u32 pkt_data_pull(u32 addr)
+{
+	volatile u16 *addr_16 = (u16 *)addr;
+	return (u32)((swab16(*addr_16) << 16) & 0xFFFF0000)\
+				| swab16(*(addr_16 + 1));
+}
+
+void pkt_data_push(u32 addr, u32 val)
+{
+	*(volatile u16 *)(addr + 2) = swab16((u16)val);
+	*(volatile u16 *)(addr) = swab16((u16)(val >> 16));
+}

board/sbc8349/sbc8349.c

@@ -101,7 +101,7 @@ int fixed_sdram(void)
 			return -1;
 		}
 	}
-	im->sysconf.ddrlaw[0].bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
+	im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE & 0xfffff000;
 	im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
 
 #if (CFG_DDR_SIZE != 256)

board/sh7785lcr/selfcheck.c

@@ -84,7 +84,7 @@ static void test_net(void)
 	if (data == 0x816910ec)
 		printf("Ethernet OK\n");
 	else
-		printf("Ethernet NG, data = %08x\n", data);
+		printf("Ethernet NG, data = %08x\n", (unsigned int)data);
 }
 
 static void test_sata(void)
@@ -96,7 +96,7 @@ static void test_sata(void)
 	if (data == 0x35121095)
 		printf("SATA OK\n");
 	else
-		printf("SATA NG, data = %08x\n", data);
+		printf("SATA NG, data = %08x\n", (unsigned int)data);
 }
 
 static void test_pci(void)

board/socrates/ddr.c

@@ -57,7 +57,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num)
 	 *	- frequency
 	 *	- ddr1 vs. ddr2
 	 */
-	popts->cpo_override = 10;
+	popts->cpo_override = 0;
 
 	/*
 	 * Factors to consider for write data delay:

board/tqc/tqm8xx/Makefile

@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	= $(BOARD).o flash.o load_sernum_ethaddr.o
+COBJS	= $(BOARD).o load_sernum_ethaddr.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))

board/tqc/tqm8xx/flash.c

@@ -1,834 +0,0 @@
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#if 0
-#define DEBUG
-#endif
-
-#include <common.h>
-#include <mpc8xx.h>
-#include <environment.h>
-
-#include <asm/processor.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if !defined(CONFIG_FLASH_CFI_DRIVER) /* do not use if CFI driver is configured */
-
-#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \
-    && !defined(CONFIG_TQM885D)
-# ifndef CFG_OR_TIMING_FLASH_AT_50MHZ
-#  define CFG_OR_TIMING_FLASH_AT_50MHZ	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
-					 OR_SCY_2_CLK | OR_EHTR | OR_BI)
-# endif
-#endif /* CONFIG_TQM8xxL/M, !TQM866M, !TQM885D */
-
-#ifndef	CONFIG_ENV_ADDR
-#define CONFIG_ENV_ADDR	(CFG_FLASH_BASE + CONFIG_ENV_OFFSET)
-#endif
-
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info);
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
-	volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
-	volatile memctl8xx_t *memctl = &immap->im_memctl;
-	unsigned long size_b0, size_b1;
-	int i;
-
-#ifdef	CFG_OR_TIMING_FLASH_AT_50MHZ
-	int scy, trlx, flash_or_timing, clk_diff;
-
-	scy = (CFG_OR_TIMING_FLASH_AT_50MHZ & OR_SCY_MSK) >> 4;
-	if (CFG_OR_TIMING_FLASH_AT_50MHZ & OR_TRLX) {
-		trlx = OR_TRLX;
-		scy *= 2;
-	} else
-		trlx = 0;
-
-		/* We assume that each 10MHz of bus clock require 1-clk SCY
-		 * adjustment.
-		 */
-	clk_diff = (gd->bus_clk / 1000000) - 50;
-
-		/* We need proper rounding here. This is what the "+5" and "-5"
-		 * are here for.
-		 */
-	if (clk_diff >= 0)
-		scy += (clk_diff + 5) / 10;
-	else
-		scy += (clk_diff - 5) / 10;
-
-		/* For bus frequencies above 50MHz, we want to use relaxed timing
-		 * (OR_TRLX).
-		 */
-	if (gd->bus_clk >= 50000000)
-		trlx = OR_TRLX;
-	else
-		trlx = 0;
-
-	if (trlx)
-		scy /= 2;
-
-	if (scy > 0xf)
-		scy = 0xf;
-	if (scy < 1)
-		scy = 1;
-
-	flash_or_timing = (scy << 4) | trlx |
-	                  (CFG_OR_TIMING_FLASH_AT_50MHZ & ~(OR_TRLX | OR_SCY_MSK));
-#endif
-	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
-		flash_info[i].flash_id = FLASH_UNKNOWN;
-	}
-
-	/* Static FLASH Bank configuration here - FIXME XXX */
-
-	debug ("\n## Get flash bank 1 size @ 0x%08x\n",FLASH_BASE0_PRELIM);
-
-	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
-
-	debug ("## Get flash bank 2 size @ 0x%08x\n",FLASH_BASE1_PRELIM);
-
-	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
-		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
-			size_b0, size_b0<<20);
-	}
-
-	size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]);
-
-	debug ("## Prelim. Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1);
-
-	if (size_b1 > size_b0) {
-		printf ("## ERROR: "
-			"Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n",
-			size_b1, size_b1<<20,
-			size_b0, size_b0<<20
-		);
-		flash_info[0].flash_id	= FLASH_UNKNOWN;
-		flash_info[1].flash_id	= FLASH_UNKNOWN;
-		flash_info[0].sector_count	= -1;
-		flash_info[1].sector_count	= -1;
-		flash_info[0].size		= 0;
-		flash_info[1].size		= 0;
-		return (0);
-	}
-
-	debug  ("## Before remap: "
-		"BR0: 0x%08x    OR0: 0x%08x    "
-		"BR1: 0x%08x    OR1: 0x%08x\n",
-		memctl->memc_br0, memctl->memc_or0,
-		memctl->memc_br1, memctl->memc_or1);
-
-	/* Remap FLASH according to real size */
-#ifndef	CFG_OR_TIMING_FLASH_AT_50MHZ
-	memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK);
-#else
-	memctl->memc_or0 = flash_or_timing | (-size_b0 & OR_AM_MSK);
-#endif
-	memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
-
-	debug ("## BR0: 0x%08x    OR0: 0x%08x\n",
-		memctl->memc_br0, memctl->memc_or0);
-
-	/* Re-do sizing to get full correct info */
-	size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
-
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
-	/* monitor protection ON by default */
-	debug ("Protect monitor: %08lx ... %08lx\n",
-		(ulong)CFG_MONITOR_BASE,
-		(ulong)CFG_MONITOR_BASE + monitor_flash_len - 1);
-
-	flash_protect(FLAG_PROTECT_SET,
-		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE + monitor_flash_len - 1,
-		      &flash_info[0]);
-#endif
-
-#ifdef	CONFIG_ENV_IS_IN_FLASH
-	/* ENV protection ON by default */
-# ifdef CONFIG_ENV_ADDR_REDUND
-	debug ("Protect primary   environment: %08lx ... %08lx\n",
-		(ulong)CONFIG_ENV_ADDR,
-		(ulong)CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1);
-# else
-	debug ("Protect environment: %08lx ... %08lx\n",
-		(ulong)CONFIG_ENV_ADDR,
-		(ulong)CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1);
-# endif
-
-	flash_protect(FLAG_PROTECT_SET,
-		      CONFIG_ENV_ADDR,
-		      CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
-		      &flash_info[0]);
-#endif
-
-#ifdef CONFIG_ENV_ADDR_REDUND
-	debug ("Protect redundand environment: %08lx ... %08lx\n",
-		(ulong)CONFIG_ENV_ADDR_REDUND,
-		(ulong)CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1);
-
-	flash_protect(FLAG_PROTECT_SET,
-		      CONFIG_ENV_ADDR_REDUND,
-		      CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
-		      &flash_info[0]);
-#endif
-
-	if (size_b1) {
-#ifndef	CFG_OR_TIMING_FLASH_AT_50MHZ
-		memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000);
-#else
-		memctl->memc_or1 = flash_or_timing | (-size_b1 & 0xFFFF8000);
-#endif
-		memctl->memc_br1 = ((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) |
-				    BR_MS_GPCM | BR_V;
-
-		debug ("## BR1: 0x%08x    OR1: 0x%08x\n",
-			memctl->memc_br1, memctl->memc_or1);
-
-		/* Re-do sizing to get full correct info */
-		size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + size_b0),
-					  &flash_info[1]);
-
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
-		/* monitor protection ON by default */
-		flash_protect(FLAG_PROTECT_SET,
-			      CFG_MONITOR_BASE,
-			      CFG_MONITOR_BASE+monitor_flash_len-1,
-			      &flash_info[1]);
-#endif
-
-#ifdef	CONFIG_ENV_IS_IN_FLASH
-		/* ENV protection ON by default */
-		flash_protect(FLAG_PROTECT_SET,
-			      CONFIG_ENV_ADDR,
-			      CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1,
-			      &flash_info[1]);
-#endif
-	} else {
-		memctl->memc_br1 = 0;		/* invalidate bank */
-
-		flash_info[1].flash_id = FLASH_UNKNOWN;
-		flash_info[1].sector_count = -1;
-		flash_info[1].size = 0;
-
-		debug ("## DISABLE BR1: 0x%08x    OR1: 0x%08x\n",
-			memctl->memc_br1, memctl->memc_or1);
-	}
-
-	debug ("## Final Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1);
-
-	flash_info[0].size = size_b0;
-	flash_info[1].size = size_b1;
-
-	return (size_b0 + size_b1);
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info  (flash_info_t *info)
-{
-	int i;
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf ("missing or unknown FLASH type\n");
-		return;
-	}
-
-	switch (info->flash_id & FLASH_VENDMASK) {
-	case FLASH_MAN_AMD:	printf ("AMD ");		break;
-	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
-	default:		printf ("Unknown Vendor ");	break;
-	}
-
-	switch (info->flash_id & FLASH_TYPEMASK) {
-#ifdef CONFIG_TQM8xxM	/* mirror bit flash */
-	case FLASH_AMLV128U:	printf ("AM29LV128ML (128Mbit, uniform sector size)\n");
-				break;
-	case FLASH_AMLV320U:	printf ("AM29LV320ML (32Mbit, uniform sector size)\n");
-				break;
-	case FLASH_AMLV640U:	printf ("AM29LV640ML (64Mbit, uniform sector size)\n");
-				break;
-	case FLASH_AMLV320B:	printf ("AM29LV320MB (32Mbit, bottom boot sect)\n");
-				break;
-# else	/* ! TQM8xxM */
-	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
-				break;
-	case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
-				break;
-	case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
-				break;
-	case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
-				break;
-	case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
-				break;
-	case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit, top boot sector)\n");
-				break;
-#endif	/* TQM8xxM */
-	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
-				break;
-	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
-				break;
-	case FLASH_AMDL163B:	printf ("AM29DL163B (16 Mbit, bottom boot sect)\n");
-				break;
-	default:		printf ("Unknown Chip Type\n");
-				break;
-	}
-
-	printf ("  Size: %ld MB in %d Sectors\n",
-		info->size >> 20, info->sector_count);
-
-	printf ("  Sector Start Addresses:");
-	for (i=0; i<info->sector_count; ++i) {
-		if ((i % 5) == 0)
-			printf ("\n   ");
-		printf (" %08lX%s",
-			info->start[i],
-			info->protect[i] ? " (RO)" : "     "
-		);
-	}
-	printf ("\n");
-	return;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-static ulong flash_get_size (vu_long *addr, flash_info_t *info)
-{
-	short i;
-	ulong value;
-	ulong base = (ulong)addr;
-
-	/* Write auto select command: read Manufacturer ID */
-	addr[0x0555] = 0x00AA00AA;
-	addr[0x02AA] = 0x00550055;
-	addr[0x0555] = 0x00900090;
-
-	value = addr[0];
-
-	debug ("Manuf. ID @ 0x%08lx: 0x%08lx\n", (ulong)addr, value);
-
-	switch (value) {
-	case AMD_MANUFACT:
-		debug ("Manufacturer: AMD\n");
-		info->flash_id = FLASH_MAN_AMD;
-		break;
-	case FUJ_MANUFACT:
-		debug ("Manufacturer: FUJITSU\n");
-		info->flash_id = FLASH_MAN_FUJ;
-		break;
-	default:
-		debug ("Manufacturer: *** unknown ***\n");
-		info->flash_id = FLASH_UNKNOWN;
-		info->sector_count = 0;
-		info->size = 0;
-		return (0);			/* no or unknown flash	*/
-	}
-
-	value = addr[1];			/* device ID		*/
-
-	debug ("Device ID @ 0x%08lx: 0x%08lx\n", (ulong)(&addr[1]), value);
-
-	switch (value) {
-#ifdef CONFIG_TQM8xxM	/* mirror bit flash */
-	case AMD_ID_MIRROR:
-		debug ("Mirror Bit flash: addr[14] = %08lX  addr[15] = %08lX\n",
-			addr[14], addr[15]);
-		/* Special case for AMLV320MH/L */
-		if ((addr[14] & 0x00ff00ff) == 0x001d001d &&
-		    (addr[15] & 0x00ff00ff) == 0x00000000) {
-			debug ("Chip: AMLV320MH/L\n");
-			info->flash_id += FLASH_AMLV320U;
-			info->sector_count = 64;
-			info->size = 0x00800000;	/* => 8 MB */
-			break;
-		}
-		switch(addr[14]) {
-		case AMD_ID_LV128U_2:
-			if (addr[15] != AMD_ID_LV128U_3) {
-				debug ("Chip: AMLV128U -> unknown\n");
-				info->flash_id = FLASH_UNKNOWN;
-			} else {
-				debug ("Chip: AMLV128U\n");
-				info->flash_id += FLASH_AMLV128U;
-				info->sector_count = 256;
-				info->size = 0x02000000;
-			}
-			break;				/* => 32 MB	*/
-		case AMD_ID_LV640U_2:
-			if (addr[15] != AMD_ID_LV640U_3) {
-				debug ("Chip: AMLV640U -> unknown\n");
-				info->flash_id = FLASH_UNKNOWN;
-			} else {
-				debug ("Chip: AMLV640U\n");
-				info->flash_id += FLASH_AMLV640U;
-				info->sector_count = 128;
-				info->size = 0x01000000;
-			}
-			break;				/* => 16 MB	*/
-		case AMD_ID_LV320B_2:
-			if (addr[15] != AMD_ID_LV320B_3) {
-				debug ("Chip: AMLV320B -> unknown\n");
-				info->flash_id = FLASH_UNKNOWN;
-			} else {
-				debug ("Chip: AMLV320B\n");
-				info->flash_id += FLASH_AMLV320B;
-				info->sector_count = 71;
-				info->size = 0x00800000;
-			}
-			break;				/* =>  8 MB	*/
-		default:
-			debug ("Chip: *** unknown ***\n");
-			info->flash_id = FLASH_UNKNOWN;
-			break;
-		}
-		break;
-# else	/* ! TQM8xxM */
-	case AMD_ID_LV400T:
-		info->flash_id += FLASH_AM400T;
-		info->sector_count = 11;
-		info->size = 0x00100000;
-		break;					/* => 1 MB		*/
-
-	case AMD_ID_LV400B:
-		info->flash_id += FLASH_AM400B;
-		info->sector_count = 11;
-		info->size = 0x00100000;
-		break;					/* => 1 MB		*/
-
-	case AMD_ID_LV800T:
-		info->flash_id += FLASH_AM800T;
-		info->sector_count = 19;
-		info->size = 0x00200000;
-		break;					/* => 2 MB	*/
-
-	case AMD_ID_LV800B:
-		info->flash_id += FLASH_AM800B;
-		info->sector_count = 19;
-		info->size = 0x00200000;
-		break;					/* => 2 MB	*/
-
-	case AMD_ID_LV320T:
-		info->flash_id += FLASH_AM320T;
-		info->sector_count = 71;
-		info->size = 0x00800000;
-		break;					/* => 8 MB	*/
-
-	case AMD_ID_LV320B:
-		info->flash_id += FLASH_AM320B;
-		info->sector_count = 71;
-		info->size = 0x00800000;
-		break;					/* => 8 MB	*/
-#endif	/* TQM8xxM */
-
-	case AMD_ID_LV160T:
-		info->flash_id += FLASH_AM160T;
-		info->sector_count = 35;
-		info->size = 0x00400000;
-		break;					/* => 4 MB	*/
-
-	case AMD_ID_LV160B:
-		info->flash_id += FLASH_AM160B;
-		info->sector_count = 35;
-		info->size = 0x00400000;
-		break;					/* => 4 MB	*/
-
-	case AMD_ID_DL163B:
-		info->flash_id += FLASH_AMDL163B;
-		info->sector_count = 39;
-		info->size = 0x00400000;
-		break;					/* => 4 MB	*/
-
-	default:
-		info->flash_id = FLASH_UNKNOWN;
-		return (0);			/* => no or unknown flash */
-	}
-
-	/* set up sector start address table */
-	switch (value) {
-#ifdef CONFIG_TQM8xxM	/* mirror bit flash */
-	case AMD_ID_MIRROR:
-		switch (info->flash_id & FLASH_TYPEMASK) {
-			/* only known types here - no default */
-		case FLASH_AMLV128U:
-		case FLASH_AMLV640U:
-		case FLASH_AMLV320U:
-			for (i = 0; i < info->sector_count; i++) {
-				info->start[i] = base;
-				base += 0x20000;
-			}
-			break;
-		case FLASH_AMLV320B:
-			for (i = 0; i < info->sector_count; i++) {
-				info->start[i] = base;
-				/*
-				 * The first 8 sectors are 8 kB,
-				 * all the other ones  are 64 kB
-				 */
-				base += (i < 8)
-					?  2 * ( 8 << 10)
-					:  2 * (64 << 10);
-			}
-			break;
-		}
-		break;
-# else	/* ! TQM8xxM */
-	case AMD_ID_LV400B:
-	case AMD_ID_LV800B:
-		/* set sector offsets for bottom boot block type	*/
-		info->start[0] = base + 0x00000000;
-		info->start[1] = base + 0x00008000;
-		info->start[2] = base + 0x0000C000;
-		info->start[3] = base + 0x00010000;
-		for (i = 4; i < info->sector_count; i++) {
-			info->start[i] = base + (i * 0x00020000) - 0x00060000;
-		}
-		break;
-	case AMD_ID_LV400T:
-	case AMD_ID_LV800T:
-		/* set sector offsets for top boot block type		*/
-		i = info->sector_count - 1;
-		info->start[i--] = base + info->size - 0x00008000;
-		info->start[i--] = base + info->size - 0x0000C000;
-		info->start[i--] = base + info->size - 0x00010000;
-		for (; i >= 0; i--) {
-			info->start[i] = base + i * 0x00020000;
-		}
-		break;
-	case AMD_ID_LV320B:
-		for (i = 0; i < info->sector_count; i++) {
-			info->start[i] = base;
-			/*
-			 * The first 8 sectors are 8 kB,
-			 * all the other ones  are 64 kB
-			 */
-			base += (i < 8)
-				?  2 * ( 8 << 10)
-				:  2 * (64 << 10);
-		}
-		break;
-	case AMD_ID_LV320T:
-		for (i = 0; i < info->sector_count; i++) {
-			info->start[i] = base;
-			/*
-			 * The last 8 sectors are 8 kB,
-			 * all the other ones  are 64 kB
-			 */
-			base += (i < (info->sector_count - 8))
-				?  2 * (64 << 10)
-				:  2 * ( 8 << 10);
-		}
-		break;
-#endif	/* TQM8xxM */
-	case AMD_ID_LV160B:
-		/* set sector offsets for bottom boot block type	*/
-		info->start[0] = base + 0x00000000;
-		info->start[1] = base + 0x00008000;
-		info->start[2] = base + 0x0000C000;
-		info->start[3] = base + 0x00010000;
-		for (i = 4; i < info->sector_count; i++) {
-			info->start[i] = base + (i * 0x00020000) - 0x00060000;
-		}
-		break;
-	case AMD_ID_LV160T:
-		/* set sector offsets for top boot block type		*/
-		i = info->sector_count - 1;
-		info->start[i--] = base + info->size - 0x00008000;
-		info->start[i--] = base + info->size - 0x0000C000;
-		info->start[i--] = base + info->size - 0x00010000;
-		for (; i >= 0; i--) {
-			info->start[i] = base + i * 0x00020000;
-		}
-		break;
-	case AMD_ID_DL163B:
-		for (i = 0; i < info->sector_count; i++) {
-			info->start[i] = base;
-			/*
-			 * The first 8 sectors are 8 kB,
-			 * all the other ones  are 64 kB
-			 */
-			base += (i < 8)
-				?  2 * ( 8 << 10)
-				:  2 * (64 << 10);
-		}
-		break;
-	default:
-		return (0);
-		break;
-	}
-
-#if 0
-	/* check for protected sectors */
-	for (i = 0; i < info->sector_count; i++) {
-		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
-		/* D0 = 1 if protected */
-		addr = (volatile unsigned long *)(info->start[i]);
-		info->protect[i] = addr[2] & 1;
-	}
-#endif
-
-	/*
-	 * Prevent writes to uninitialized FLASH.
-	 */
-	if (info->flash_id != FLASH_UNKNOWN) {
-		addr = (volatile unsigned long *)info->start[0];
-
-		*addr = 0x00F000F0;	/* reset bank */
-	}
-
-	return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int	flash_erase (flash_info_t *info, int s_first, int s_last)
-{
-	vu_long *addr = (vu_long*)(info->start[0]);
-	int flag, prot, sect, l_sect;
-	ulong start, now, last;
-
-	debug ("flash_erase: first: %d last: %d\n", s_first, s_last);
-
-	if ((s_first < 0) || (s_first > s_last)) {
-		if (info->flash_id == FLASH_UNKNOWN) {
-			printf ("- missing\n");
-		} else {
-			printf ("- no sectors to erase\n");
-		}
-		return 1;
-	}
-
-	if ((info->flash_id == FLASH_UNKNOWN) ||
-	    (info->flash_id > FLASH_AMD_COMP)) {
-		printf ("Can't erase unknown flash type %08lx - aborted\n",
-			info->flash_id);
-		return 1;
-	}
-
-	prot = 0;
-	for (sect=s_first; sect<=s_last; ++sect) {
-		if (info->protect[sect]) {
-			prot++;
-		}
-	}
-
-	if (prot) {
-		printf ("- Warning: %d protected sectors will not be erased!\n",
-			prot);
-	} else {
-		printf ("\n");
-	}
-
-	l_sect = -1;
-
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
-
-	addr[0x0555] = 0x00AA00AA;
-	addr[0x02AA] = 0x00550055;
-	addr[0x0555] = 0x00800080;
-	addr[0x0555] = 0x00AA00AA;
-	addr[0x02AA] = 0x00550055;
-
-	/* Start erase on unprotected sectors */
-	for (sect = s_first; sect<=s_last; sect++) {
-		if (info->protect[sect] == 0) {	/* not protected */
-			addr = (vu_long*)(info->start[sect]);
-			addr[0] = 0x00300030;
-			l_sect = sect;
-		}
-	}
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts();
-
-	/* wait at least 80us - let's wait 1 ms */
-	udelay (1000);
-
-	/*
-	 * We wait for the last triggered sector
-	 */
-	if (l_sect < 0)
-		goto DONE;
-
-	start = get_timer (0);
-	last  = start;
-	addr = (vu_long*)(info->start[l_sect]);
-	while ((addr[0] & 0x00800080) != 0x00800080) {
-		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
-			printf ("Timeout\n");
-			return 1;
-		}
-		/* show that we're waiting */
-		if ((now - last) > 1000) {	/* every second */
-			putc ('.');
-			last = now;
-		}
-	}
-
-DONE:
-	/* reset to read mode */
-	addr = (volatile unsigned long *)info->start[0];
-	addr[0] = 0x00F000F0;	/* reset bank */
-
-	printf (" done\n");
-	return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
-	ulong cp, wp, data;
-	int i, l, rc;
-
-	wp = (addr & ~3);	/* get lower word aligned address */
-
-	/*
-	 * handle unaligned start bytes
-	 */
-	if ((l = addr - wp) != 0) {
-		data = 0;
-		for (i=0, cp=wp; i<l; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *)cp);
-		}
-		for (; i<4 && cnt>0; ++i) {
-			data = (data << 8) | *src++;
-			--cnt;
-			++cp;
-		}
-		for (; cnt==0 && i<4; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *)cp);
-		}
-
-		if ((rc = write_word(info, wp, data)) != 0) {
-			return (rc);
-		}
-		wp += 4;
-	}
-
-	/*
-	 * handle word aligned part
-	 */
-	while (cnt >= 4) {
-		data = 0;
-		for (i=0; i<4; ++i) {
-			data = (data << 8) | *src++;
-		}
-		if ((rc = write_word(info, wp, data)) != 0) {
-			return (rc);
-		}
-		wp  += 4;
-		cnt -= 4;
-	}
-
-	if (cnt == 0) {
-		return (0);
-	}
-
-	/*
-	 * handle unaligned tail bytes
-	 */
-	data = 0;
-	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
-		data = (data << 8) | *src++;
-		--cnt;
-	}
-	for (; i<4; ++i, ++cp) {
-		data = (data << 8) | (*(uchar *)cp);
-	}
-
-	return (write_word(info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t *info, ulong dest, ulong data)
-{
-	vu_long *addr = (vu_long*)(info->start[0]);
-	ulong start;
-	int flag;
-
-	/* Check if Flash is (sufficiently) erased */
-	if ((*((vu_long *)dest) & data) != data) {
-		return (2);
-	}
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
-
-	addr[0x0555] = 0x00AA00AA;
-	addr[0x02AA] = 0x00550055;
-	addr[0x0555] = 0x00A000A0;
-
-	*((vu_long *)dest) = data;
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts();
-
-	/* data polling for D7 */
-	start = get_timer (0);
-	while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
-			return (1);
-		}
-	}
-	return (0);
-}
-
-/*-----------------------------------------------------------------------
- */
-
-#endif /* !defined(CONFIG_FLASH_CFI_DRIVER) */

board/tqc/tqm8xx/tqm8xx.c

@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000-2006
+ * (C) Copyright 2000-2008
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -21,16 +21,14 @@
  * MA 02111-1307 USA
  */
 
-#if 0
-#define DEBUG
-#endif
-
 #include <common.h>
 #include <mpc8xx.h>
 #ifdef CONFIG_PS2MULT
 #include <ps2mult.h>
 #endif
 
+extern flash_info_t flash_info[];	/* FLASH chips info */
+
 DECLARE_GLOBAL_DATA_PTR;
 
 static long int dram_size (long int, long int *, long int);
@@ -402,8 +400,6 @@ phys_size_t initdram (int board_type)
 	memctl->memc_or5 = CFG_OR5_ISP1362;
 	memctl->memc_br5 = CFG_BR5_ISP1362;
 #endif							/* CONFIG_ISP1362_USB */
-
-
 	return (size_b0 + size_b1);
 }
 
@@ -451,24 +447,112 @@ int board_early_init_r (void)
 
 #endif /* CONFIG_PS2MULT */
 
-/* ---------------------------------------------------------------------------- */
-/* HMI10 specific stuff								*/
-/* ---------------------------------------------------------------------------- */
-#ifdef CONFIG_HMI10
 
+#ifdef CONFIG_MISC_INIT_R
 int misc_init_r (void)
 {
-# ifdef CONFIG_IDE_LED
 	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
 
+#ifdef	CFG_OR_TIMING_FLASH_AT_50MHZ
+	int scy, trlx, flash_or_timing, clk_diff;
+
+	scy = (CFG_OR_TIMING_FLASH_AT_50MHZ & OR_SCY_MSK) >> 4;
+	if (CFG_OR_TIMING_FLASH_AT_50MHZ & OR_TRLX) {
+		trlx = OR_TRLX;
+		scy *= 2;
+	} else {
+		trlx = 0;
+	}
+
+	/*
+	 * We assume that each 10MHz of bus clock require 1-clk SCY
+	 * adjustment.
+	 */
+	clk_diff = (gd->bus_clk / 1000000) - 50;
+
+	/*
+	 * We need proper rounding here. This is what the "+5" and "-5"
+	 * are here for.
+	 */
+	if (clk_diff >= 0)
+		scy += (clk_diff + 5) / 10;
+	else
+		scy += (clk_diff - 5) / 10;
+
+	/*
+	 * For bus frequencies above 50MHz, we want to use relaxed timing
+	 * (OR_TRLX).
+	 */
+	if (gd->bus_clk >= 50000000)
+		trlx = OR_TRLX;
+	else
+		trlx = 0;
+
+	if (trlx)
+		scy /= 2;
+
+	if (scy > 0xf)
+		scy = 0xf;
+	if (scy < 1)
+		scy = 1;
+
+	flash_or_timing = (scy << 4) | trlx |
+		(CFG_OR_TIMING_FLASH_AT_50MHZ & ~(OR_TRLX | OR_SCY_MSK));
+
+	memctl->memc_or0 =
+		flash_or_timing | (-flash_info[0].size & OR_AM_MSK);
+#else
+	memctl->memc_or0 =
+		CFG_OR_TIMING_FLASH | (-flash_info[0].size & OR_AM_MSK);
+#endif
+	memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
+
+	debug ("## BR0: 0x%08x    OR0: 0x%08x\n",
+	       memctl->memc_br0, memctl->memc_or0);
+
+	if (flash_info[1].size) {
+#ifdef	CFG_OR_TIMING_FLASH_AT_50MHZ
+		memctl->memc_or1 = flash_or_timing |
+			(-flash_info[1].size & 0xFFFF8000);
+#else
+		memctl->memc_or1 = CFG_OR_TIMING_FLASH |
+			(-flash_info[1].size & 0xFFFF8000);
+#endif
+		memctl->memc_br1 =
+			((CFG_FLASH_BASE +
+			  flash_info[0].
+			  size) & BR_BA_MSK) | BR_MS_GPCM | BR_V;
+
+		debug ("## BR1: 0x%08x    OR1: 0x%08x\n",
+		       memctl->memc_br1, memctl->memc_or1);
+	} else {
+		memctl->memc_br1 = 0;	/* invalidate bank */
+
+		debug ("## DISABLE BR1: 0x%08x    OR1: 0x%08x\n",
+		       memctl->memc_br1, memctl->memc_or1);
+	}
+
+# ifdef CONFIG_IDE_LED
 	/* Configure PA15 as output port */
 	immap->im_ioport.iop_padir |= 0x0001;
 	immap->im_ioport.iop_paodr |= 0x0001;
 	immap->im_ioport.iop_papar &= ~0x0001;
 	immap->im_ioport.iop_padat &= ~0x0001;	/* turn it off */
 # endif
+
+#ifdef CONFIG_NSCU
+	/* wake up ethernet module */
+	immap->im_ioport.iop_pcpar &= ~0x0004;	/* GPIO pin      */
+	immap->im_ioport.iop_pcdir |= 0x0004;	/* output        */
+	immap->im_ioport.iop_pcso &= ~0x0004;	/* for clarity   */
+	immap->im_ioport.iop_pcdat |= 0x0004;	/* enable        */
+#endif /* CONFIG_NSCU */
+
 	return (0);
 }
+#endif	/* CONFIG_MISC_INIT_R */
+
 
 # ifdef CONFIG_IDE_LED
 void ide_led (uchar led, uchar status)
@@ -483,26 +567,6 @@ void ide_led (uchar led, uchar status)
 	}
 }
 # endif
-#endif	/* CONFIG_HMI10 */
-
-/* ---------------------------------------------------------------------------- */
-/* NSCU specific stuff								*/
-/* ---------------------------------------------------------------------------- */
-#ifdef CONFIG_NSCU
-
-int misc_init_r (void)
-{
-	volatile immap_t *immr = (immap_t *) CFG_IMMR;
-
-	/* wake up ethernet module */
-	immr->im_ioport.iop_pcpar &= ~0x0004; /* GPIO pin	*/
-	immr->im_ioport.iop_pcdir |=  0x0004; /* output		*/
-	immr->im_ioport.iop_pcso  &= ~0x0004; /* for clarity	*/
-	immr->im_ioport.iop_pcdat |=  0x0004; /* enable		*/
-
-	return (0);
-}
-#endif	/* CONFIG_NSCU */
 
 /* ---------------------------------------------------------------------------- */
 /* TK885D specific initializaion						*/
@@ -548,7 +612,4 @@ int last_stage_init(void)
 
 	return 0;
 }
-
 #endif
-
-/* ------------------------------------------------------------------------- */

common/cmd_bootm.c

@@ -347,7 +347,7 @@ static int bootm_load_os(image_info_t os, ulong *load_end, int boot_progress)
 
 		int ret = lzmaBuffToBuffDecompress(
 			(unsigned char *)load, &unc_len,
-			(unsigned char *)image_start, image_start);
+			(unsigned char *)image_start, image_len);
 		if (ret != LZMA_RESULT_OK) {
 			printf ("LZMA: uncompress or overwrite error %d "
 				"- must RESET board to recover\n", ret);

common/cmd_i2c.c

@@ -1220,12 +1220,12 @@ int do_i2c_bus_speed(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 
 int do_i2c(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 {
+	if (!strncmp(argv[1], "sp", 2))
+		return do_i2c_bus_speed(cmdtp, flag, --argc, ++argv);
 #if defined(CONFIG_I2C_MULTI_BUS)
 	if (!strncmp(argv[1], "de", 2))
 		return do_i2c_bus_num(cmdtp, flag, --argc, ++argv);
 #endif  /* CONFIG_I2C_MULTI_BUS */
-	if (!strncmp(argv[1], "sp", 2))
-		return do_i2c_bus_speed(cmdtp, flag, --argc, ++argv);
 	if (!strncmp(argv[1], "md", 2))
 		return do_i2c_md(cmdtp, flag, --argc, ++argv);
 	if (!strncmp(argv[1], "mm", 2))
@@ -1256,10 +1256,10 @@ int do_i2c(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 U_BOOT_CMD(
 	i2c, 6, 1, do_i2c,
 	"i2c     - I2C sub-system\n",
+	"speed [speed] - show or set I2C bus speed\n"
 #if defined(CONFIG_I2C_MULTI_BUS)
-	"dev [dev] - show or set current I2C bus\n"
+	"i2c dev [dev] - show or set current I2C bus\n"
 #endif  /* CONFIG_I2C_MULTI_BUS */
-	"i2c speed [speed] - show or set I2C bus speed\n"
 	"i2c md chip address[.0, .1, .2] [# of objects] - read from I2C device\n"
 	"i2c mm chip address[.0, .1, .2] - write to I2C device (auto-incrementing)\n"
 	"i2c mw chip address[.0, .1, .2] value [count] - write to I2C device (fill)\n"

common/cmd_spi.c

@@ -123,9 +123,8 @@ int do_spi (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 		printf("Error with the SPI transaction.\n");
 		rcode = 1;
 	} else {
-		cp = (char *)din;
 		for(j = 0; j < ((bitlen + 7) / 8); j++) {
-			printf("%02X", *cp++);
+			printf("%02X", din[j]);
 		}
 		printf("\n");
 	}

common/cmd_strings.c

@@ -10,8 +10,6 @@
 #include <common.h>
 #include <command.h>
 
-#ifdef CONFIG_CFG_STRINGS
-
 static char *start_addr, *last_addr;
 
 int do_strings(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
@@ -45,5 +43,3 @@ U_BOOT_CMD(strings, 3, 1, do_strings,
 	"strings - display strings\n",
 	"<addr> [byte count]\n"
 	"    - display strings at <addr> for at least [byte count] or first double NUL\n");
-
-#endif

cpu/arm1136/mx31/interrupts.c

@@ -27,30 +27,49 @@
 #define TIMER_BASE 0x53f90000 /* General purpose timer 1 */
 
 /* General purpose timers registers */
-#define GPTCR   __REG(TIMER_BASE) /* Control register */
-#define GPTPR  __REG(TIMER_BASE + 0x4) /* Prescaler register */
-#define GPTSR   __REG(TIMER_BASE + 0x8) /* Status register */
-#define GPTCNT __REG(TIMER_BASE + 0x24) /* Counter register */
+#define GPTCR	__REG(TIMER_BASE)		/* Control register	*/
+#define GPTPR	__REG(TIMER_BASE + 0x4)		/* Prescaler register	*/
+#define GPTSR	__REG(TIMER_BASE + 0x8)		/* Status register	*/
+#define GPTCNT	__REG(TIMER_BASE + 0x24)	/* Counter register	*/
 
 /* General purpose timers bitfields */
-#define GPTCR_SWR       (1<<15) /* Software reset */
-#define GPTCR_FRR       (1<<9)  /* Freerun / restart */
-#define GPTCR_CLKSOURCE_32 (4<<6)  /* Clock source */
-#define GPTCR_TEN       (1)     /* Timer enable */
+#define GPTCR_SWR		(1 << 15)	/* Software reset	*/
+#define GPTCR_FRR		(1 << 9)	/* Freerun / restart	*/
+#define GPTCR_CLKSOURCE_32	(4 << 6)	/* Clock source		*/
+#define GPTCR_TEN		1		/* Timer enable		*/
+
+/* "time" is measured in 1 / CFG_HZ seconds, "tick" is internal timer period */
+#ifdef CONFIG_MX31_TIMER_HIGH_PRECISION
+/* ~0.4% error - measured with stop-watch on 100s boot-delay */
+#define TICK_TO_TIME(t)	((t) * CFG_HZ / CONFIG_MX31_CLK32)
+#define TIME_TO_TICK(t)	((unsigned long long)(t) * CONFIG_MX31_CLK32 / CFG_HZ)
+#define US_TO_TICK(t)	(((unsigned long long)(t) * CONFIG_MX31_CLK32 + \
+			999999) / 1000000)
+#else
+/* ~2% error */
+#define TICK_PER_TIME	((CONFIG_MX31_CLK32 + CFG_HZ / 2) / CFG_HZ)
+#define US_PER_TICK	(1000000 / CONFIG_MX31_CLK32)
+#define TICK_TO_TIME(t)	((t) / TICK_PER_TIME)
+#define TIME_TO_TICK(t)	((unsigned long long)(t) * TICK_PER_TIME)
+#define US_TO_TICK(t)	(((t) + US_PER_TICK - 1) / US_PER_TICK)
+#endif
 
 static ulong timestamp;
 static ulong lastinc;
 
 /* nothing really to do with interrupts, just starts up a counter. */
+/* The 32768Hz 32-bit timer overruns in 131072 seconds */
 int interrupt_init (void)
 {
 	int i;
 
 	/* setup GP Timer 1 */
 	GPTCR = GPTCR_SWR;
-	for ( i=0; i<100; i++) GPTCR = 0; /* We have no udelay by now */
+	for (i = 0; i < 100; i++)
+		GPTCR = 0; /* We have no udelay by now */
 	GPTPR = 0; /* 32Khz */
-	GPTCR |= GPTCR_CLKSOURCE_32 | GPTCR_TEN; /* Freerun Mode, PERCLK1 input */
+	/* Freerun Mode, PERCLK1 input */
+	GPTCR |= GPTCR_CLKSOURCE_32 | GPTCR_TEN;
 
 	return 0;
 }
@@ -67,7 +86,7 @@ void reset_timer(void)
 	reset_timer_masked();
 }
 
-ulong get_timer_masked (void)
+unsigned long long get_ticks (void)
 {
 	ulong now = GPTCNT; /* current tick value */
 
@@ -80,6 +99,17 @@ ulong get_timer_masked (void)
 	return timestamp;
 }
 
+ulong get_timer_masked (void)
+{
+	/*
+	 * get_ticks() returns a long long (64 bit), it wraps in
+	 * 2^64 / CONFIG_MX31_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
+	 * 5 * 10^9 days... and get_ticks() * CFG_HZ wraps in
+	 * 5 * 10^6 days - long enough.
+	 */
+	return TICK_TO_TIME(get_ticks());
+}
+
 ulong get_timer (ulong base)
 {
 	return get_timer_masked () - base;
@@ -87,29 +117,20 @@ ulong get_timer (ulong base)
 
 void set_timer (ulong t)
 {
+	timestamp = TIME_TO_TICK(t);
 }
 
 /* delay x useconds AND perserve advance timstamp value */
 void udelay (unsigned long usec)
 {
-	ulong tmo, tmp;
+	unsigned long long tmp;
+	ulong tmo;
 
-	if (usec >= 1000) {			/* if "big" number, spread normalization to seconds */
-		tmo = usec / 1000;		/* start to normalize for usec to ticks per sec */
-		tmo *= CFG_HZ;			/* find number of "ticks" to wait to achieve target */
-		tmo /= 1000;			/* finish normalize. */
-	} else {					/* else small number, don't kill it prior to HZ multiply */
-		tmo = usec * CFG_HZ;
-		tmo /= (1000*1000);
-	}
+	tmo = US_TO_TICK(usec);
+	tmp = get_ticks() + tmo;	/* get current timestamp */
 
-	tmp = get_timer (0);		/* get current timestamp */
-	if ( (tmo + tmp + 1) < tmp )/* if setting this forward will roll time stamp */
-		reset_timer_masked ();	/* reset "advancing" timestamp to 0, set lastinc value */
-	else
-		tmo	+= tmp;				/* else, set advancing stamp wake up time */
-	while (get_timer_masked () < tmo)/* loop till event */
-		/*NOP*/;
+	while (get_ticks() < tmp)	/* loop till event */
+		 /*NOP*/;
 }
 
 void reset_cpu (ulong addr)

cpu/mpc83xx/cpu.c

@@ -124,8 +124,8 @@ int checkcpu(void)
  * The 'dummy' variable is used to increment the MAD. 'dummy' is
  * supposed to be a pointer to the memory of the device being
  * programmed by the UPM.  The data in the MDR is written into
- * memory and the MAD is incremented every time there's a read
- * from 'dummy'. Unfortunately, the current prototype for this
+ * memory and the MAD is incremented every time there's a write
+ * to 'dummy'. Unfortunately, the current prototype for this
  * function doesn't allow for passing the address of this
  * device, and changing the prototype will break a number lots
  * of other code, so we need to use a round-about way of finding
@@ -174,8 +174,9 @@ void upmconfig (uint upm, uint *table, uint size)
 	for (i = 0; i < size; i++) {
 		lbus->mdr = table[i];
 		__asm__ __volatile__ ("sync");
-		*dummy;	/* Write the value to memory and increment MAD */
+		*dummy = 0;	/* Write the value to memory and increment MAD */
 		__asm__ __volatile__ ("sync");
+		while(((*mxmr & 0x3f) != ((i + 1) & 0x3f)));
 	}
 
 	/* Set the OP field in the MxMR to "normal" and the MAD field to 000000 */

cpu/mpc83xx/spd_sdram.c

@@ -274,7 +274,7 @@ long int spd_sdram()
 	/*
 	 * Set up LAWBAR for all of DDR.
 	 */
-	ecm->bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
+	ecm->bar = CFG_DDR_SDRAM_BASE & 0xfffff000;
 	ecm->ar  = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & law_size));
 	debug("DDR:bar=0x%08x\n", ecm->bar);
 	debug("DDR:ar=0x%08x\n", ecm->ar);

cpu/mpc83xx/start.S

@@ -167,6 +167,18 @@ boot_warm: /* time t 5 */
 	/* Initialise the E300 processor core		*/
 	/*------------------------------------------*/
 
+#ifdef CONFIG_NAND_SPL
+	/* The FCM begins execution after only the first page
+	 * is loaded.  Wait for the rest before branching
+	 * to another flash page.
+	 */
+	addi	r7, r3, 0x50b0
+1:	dcbi	0, r7
+	lwz	r6, 0(r7)
+	andi.	r6, r6, 1
+	beq	1b
+#endif
+
 	bl	init_e300_core
 
 #ifdef CFG_FLASHBOOT

cpu/mpc85xx/cpu.c

@@ -85,7 +85,8 @@ int checkcpu (void)
 	struct cpu_type *cpu;
 #ifdef CONFIG_DDR_CLK_FREQ
 	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
-	u32 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9;
+	u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
+		>> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
 #else
 	u32 ddr_ratio = 0;
 #endif

cpu/mpc85xx/fdt.c

@@ -152,7 +152,6 @@ static inline void ft_fixup_l2cache(void *blob)
 	}
 	fdt_setprop(blob, off, "cache-unified", NULL, 0);
 	fdt_setprop_cell(blob, off, "cache-block-size", line_size);
-	fdt_setprop_cell(blob, off, "cache-line-size", line_size);
 	fdt_setprop_cell(blob, off, "cache-size", size);
 	fdt_setprop_cell(blob, off, "cache-sets", num_sets);
 	fdt_setprop_cell(blob, off, "cache-level", 2);
@@ -181,7 +180,6 @@ static inline void ft_fixup_cache(void *blob)
 		dnum_sets = dsize / (dline_size * dnum_ways);
 
 		fdt_setprop_cell(blob, off, "d-cache-block-size", dline_size);
-		fdt_setprop_cell(blob, off, "d-cache-line-size", dline_size);
 		fdt_setprop_cell(blob, off, "d-cache-size", dsize);
 		fdt_setprop_cell(blob, off, "d-cache-sets", dnum_sets);
 
@@ -192,7 +190,6 @@ static inline void ft_fixup_cache(void *blob)
 		inum_sets = isize / (iline_size * inum_ways);
 
 		fdt_setprop_cell(blob, off, "i-cache-block-size", iline_size);
-		fdt_setprop_cell(blob, off, "i-cache-line-size", iline_size);
 		fdt_setprop_cell(blob, off, "i-cache-size", isize);
 		fdt_setprop_cell(blob, off, "i-cache-sets", inum_sets);
 

cpu/mpc85xx/speed.c

@@ -54,7 +54,8 @@ void get_sys_info (sys_info_t * sysInfo)
 
 #ifdef CONFIG_DDR_CLK_FREQ
 	{
-		u32 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9;
+		u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
+			>> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
 		if (ddr_ratio != 0x7)
 			sysInfo->freqDDRBus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
 	}

cpu/mpc86xx/interrupts.c

@@ -35,78 +35,23 @@
 #include <mpc86xx.h>
 #include <command.h>
 #include <asm/processor.h>
-#include <ppc_asm.tmpl>
-#include <watchdog.h>
 
-unsigned long decrementer_count;    /* count value for 1e6/HZ microseconds */
-unsigned long timestamp;
-
-
-static __inline__ unsigned long get_msr(void)
-{
-	unsigned long msr;
-
-	asm volatile ("mfmsr %0":"=r" (msr):);
-
-	return msr;
-}
-
-static __inline__ void set_msr(unsigned long msr)
-{
-	asm volatile ("mtmsr %0"::"r" (msr));
-}
-
-static __inline__ unsigned long get_dec(void)
-{
-	unsigned long val;
-
-	asm volatile ("mfdec %0":"=r" (val):);
-
-	return val;
-}
-
-static __inline__ void set_dec(unsigned long val)
-{
-	if (val)
-		asm volatile ("mtdec %0"::"r" (val));
-}
-
-/* interrupt is not supported yet */
 int interrupt_init_cpu(unsigned long *decrementer_count)
 {
-	return 0;
-}
-
-int interrupt_init(void)
-{
-	int ret;
-
 	volatile immap_t *immr = (immap_t *)CFG_IMMR;
-	immr->im_pic.gcr = MPC86xx_PICGCR_RST;
-	while (immr->im_pic.gcr & MPC86xx_PICGCR_RST);
-	immr->im_pic.gcr = MPC86xx_PICGCR_MODE;
+	volatile ccsr_pic_t *pic = &immr->im_pic;
 
-	/* call cpu specific function from $(CPU)/interrupts.c */
-	ret = interrupt_init_cpu(&decrementer_count);
+	pic->gcr = MPC86xx_PICGCR_RST;
+	while (pic->gcr & MPC86xx_PICGCR_RST)
+		;
+	pic->gcr = MPC86xx_PICGCR_MODE;
 
-	if (ret)
-		return ret;
-
-	decrementer_count = get_tbclk() / CFG_HZ;
+	*decrementer_count = get_tbclk() / CFG_HZ;
 	debug("interrupt init: tbclk() = %d MHz, decrementer_count = %ld\n",
 	      (get_tbclk() / 1000000),
-	      decrementer_count);
-
-	set_dec(decrementer_count);
-
-	set_msr(get_msr() | MSR_EE);
-
-	debug("MSR = 0x%08lx, Decrementer reg = 0x%08lx\n",
-	      get_msr(),
-	      get_dec());
+	      *decrementer_count);
 
 #ifdef CONFIG_INTERRUPTS
-	volatile ccsr_pic_t *pic = &immr->im_pic;
 
 	pic->iivpr1 = 0x810001;	/* 50220 enable mcm interrupts */
 	debug("iivpr1@%x = %x\n", &pic->iivpr1, pic->iivpr1);
@@ -132,25 +77,6 @@ int interrupt_init(void)
 	return 0;
 }
 
-void enable_interrupts(void)
-{
-	set_msr(get_msr() | MSR_EE);
-}
-
-/* returns flag if MSR_EE was set before */
-int disable_interrupts(void)
-{
-	ulong msr = get_msr();
-
-	set_msr(msr & ~MSR_EE);
-	return (msr & MSR_EE) != 0;
-}
-
-void increment_timestamp(void)
-{
-	timestamp++;
-}
-
 /*
  * timer_interrupt - gets called when the decrementer overflows,
  * with interrupts disabled.
@@ -161,50 +87,9 @@ void timer_interrupt_cpu(struct pt_regs *regs)
 	/* nothing to do here */
 }
 
-void timer_interrupt(struct pt_regs *regs)
-{
-	/* call cpu specific function from $(CPU)/interrupts.c */
-	timer_interrupt_cpu(regs);
-
-	timestamp++;
-
-	/* Restore Decrementer Count */
-	set_dec(decrementer_count);
-
-#if defined(CONFIG_WATCHDOG) || defined (CONFIG_HW_WATCHDOG)
-	if ((timestamp % (CFG_WATCHDOG_FREQ)) == 0)
-		WATCHDOG_RESET();
-#endif /* CONFIG_WATCHDOG || CONFIG_HW_WATCHDOG */
-
-#ifdef CONFIG_STATUS_LED
-	status_led_tick(timestamp);
-#endif /* CONFIG_STATUS_LED */
-
-#ifdef CONFIG_SHOW_ACTIVITY
-	board_show_activity(timestamp);
-#endif /* CONFIG_SHOW_ACTIVITY */
-
-}
-
-void reset_timer(void)
-{
-	timestamp = 0;
-}
-
-ulong get_timer(ulong base)
-{
-	return timestamp - base;
-}
-
-void set_timer(ulong t)
-{
-	timestamp = t;
-}
-
 /*
  * Install and free a interrupt handler. Not implemented yet.
  */
-
 void irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)
 {
 }
@@ -218,8 +103,6 @@ void irq_free_handler(int vec)
  */
 int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
-	printf("\nInterrupt-unsupported:\n");
-
 	return 0;
 }
 

cpu/mpc86xx/start.S

@@ -895,9 +895,9 @@ lock_ram_in_cache:
 	 */
 	lis	r3, (CFG_INIT_RAM_ADDR & ~31)@h
 	ori	r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l
-	li	r2, ((CFG_INIT_RAM_END & ~31) + \
+	li	r4, ((CFG_INIT_RAM_END & ~31) + \
 		     (CFG_INIT_RAM_ADDR & 31) + 31) / 32
-	mtctr	r2
+	mtctr	r4
 1:
 	dcbz	r0, r3
 	addi	r3, r3, 32
@@ -930,9 +930,9 @@ unlock_ram_in_cache:
 	/* invalidate the INIT_RAM section */
 	lis	r3, (CFG_INIT_RAM_ADDR & ~31)@h
 	ori	r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l
-	li	r2, ((CFG_INIT_RAM_END & ~31) + \
+	li	r4, ((CFG_INIT_RAM_END & ~31) + \
 		     (CFG_INIT_RAM_ADDR & 31) + 31) / 32
-	mtctr	r2
+	mtctr	r4
 1:	icbi	r0, r3
 	addi	r3, r3, 32
 	bdnz	1b

cpu/mpc8xx/scc.c

@@ -215,12 +215,14 @@ static int scc_init (struct eth_device *dev, bd_t * bis)
 	rxIdx = 0;
 	txIdx = 0;
 
+	if (!rtx) {
 #ifdef CFG_ALLOC_DPRAM
-	rtx = (RTXBD *) (immr->im_cpm.cp_dpmem +
-			 dpram_alloc_align (sizeof (RTXBD), 8));
+		rtx = (RTXBD *) (immr->im_cpm.cp_dpmem +
+				 dpram_alloc_align (sizeof (RTXBD), 8));
 #else
-	rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + CPM_SCC_BASE);
-#endif /* 0 */
+		rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + CPM_SCC_BASE);
+#endif
+	}
 
 #if (defined(PA_ENET_RXD) && defined(PA_ENET_TXD))
 	/* Configure port A pins for Txd and Rxd.

cpu/ppc4xx/44x_spd_ddr2.c

@@ -2261,10 +2261,12 @@ static void program_memory_queue(unsigned long *dimm_populated,
 	/*
 	 * Set optimal value for Memory Queue HB/LL Configuration registers
 	 */
-	mtdcr(SDRAM_CONF1HB, mfdcr(SDRAM_CONF1HB) | SDRAM_CONF1HB_AAFR |
-	      SDRAM_CONF1HB_RPEN | SDRAM_CONF1HB_RFTE);
-	mtdcr(SDRAM_CONF1LL, mfdcr(SDRAM_CONF1LL) | SDRAM_CONF1LL_AAFR |
-	      SDRAM_CONF1LL_RPEN | SDRAM_CONF1LL_RFTE);
+	mtdcr(SDRAM_CONF1HB, (mfdcr(SDRAM_CONF1HB) & ~SDRAM_CONF1HB_MASK) |
+	      SDRAM_CONF1HB_AAFR | SDRAM_CONF1HB_RPEN | SDRAM_CONF1HB_RFTE |
+	      SDRAM_CONF1HB_RPLM | SDRAM_CONF1HB_WRCL);
+	mtdcr(SDRAM_CONF1LL, (mfdcr(SDRAM_CONF1LL) & ~SDRAM_CONF1LL_MASK) |
+	      SDRAM_CONF1LL_AAFR | SDRAM_CONF1LL_RPEN | SDRAM_CONF1LL_RFTE |
+	      SDRAM_CONF1LL_RPLM);
 	mtdcr(SDRAM_CONFPATHB, mfdcr(SDRAM_CONFPATHB) | SDRAM_CONFPATHB_TPEN);
 #endif
 }

cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c

@@ -174,6 +174,23 @@ static inline void ecc_clear_status_reg(void)
 #endif
 }
 
+/*
+ * Reset and relock memory DLL after SDRAM_CLKTR change
+ */
+static inline void relock_memory_DLL(void)
+{
+	u32 reg;
+
+	mtsdram(SDRAM_MCOPT2, SDRAM_MCOPT2_IPTR_EXECUTE);
+
+	do {
+		mfsdram(SDRAM_MCSTAT, reg);
+	} while (!(reg & SDRAM_MCSTAT_MIC_COMP));
+
+	mfsdram(SDRAM_MCOPT2, reg);
+	mtsdram(SDRAM_MCOPT2, reg | SDRAM_MCOPT2_DCEN_ENABLE);
+}
+
 static int ecc_check_status_reg(void)
 {
 	u32 ecc_status;
@@ -981,6 +998,8 @@ u32 DQS_autocalibration(void)
 
 		mtsdram(SDRAM_CLKTR, clkp << 30);
 
+		relock_memory_DLL();
+
 		putc('\b');
 		putc(slash[loopi++ % 8]);
 
@@ -1170,6 +1189,8 @@ u32 DQS_autocalibration(void)
 
 		mtsdram(SDRAM_CLKTR, tcal.clocks.clktr << 30);
 
+		relock_memory_DLL();
+
 		mfsdram(SDRAM_RQDC, rqdc_reg);
 		rqdc_reg &= ~(SDRAM_RQDC_RQFD_MASK);
 		mtsdram(SDRAM_RQDC, rqdc_reg |

cpu/sh4/watchdog.c

@@ -17,34 +17,55 @@
 
 #include <common.h>
 #include <asm/processor.h>
+#include <asm/io.h>
 
 #define WDT_BASE	WTCNT
 
-static unsigned char cnt_read (void){
-	return *((volatile unsigned char *)(WDT_BASE + 0x00));
-}
+#define WDT_WD		(1 << 6)
+#define WDT_RST_P	(0)
+#define WDT_RST_M	(1 << 5)
+#define WDT_ENABLE	(1 << 7)
 
-static unsigned char csr_read (void){
-	return *((volatile unsigned char *)(WDT_BASE + 0x04));
-}
-
-static void cnt_write (unsigned char value){
-	while (csr_read() & (1 << 5)) {
-		/* delay */
-	}
-	*((volatile unsigned short *)(WDT_BASE + 0x00))
-		= ((unsigned short) value) | 0x5A00;
-}
-
-static void csr_write (unsigned char value){
-	*((volatile unsigned short *)(WDT_BASE + 0x04))
-		= ((unsigned short) value) | 0xA500;
-}
-
-
-int watchdog_init (void){ return 0; }
-
-void reset_cpu (unsigned long ignored)
+#if defined(CONFIG_WATCHDOG)
+static unsigned char csr_read(void)
 {
-	while(1);
+	return inb(WDT_BASE + 0x04);
+}
+
+static void cnt_write(unsigned char value)
+{
+	outl((unsigned short)value | 0x5A00, WDT_BASE + 0x00);
+}
+
+static void csr_write(unsigned char value)
+{
+	outl((unsigned short)value | 0xA500, WDT_BASE + 0x04);
+}
+
+void watchdog_reset(void)
+{
+	outl(0x55000000, WDT_BASE + 0x08);
+}
+
+int watchdog_init(void)
+{
+	/* Set overflow time*/
+	cnt_write(0);
+	/* Power on reset */
+	csr_write(WDT_WD|WDT_RST_P|WDT_ENABLE);
+
+	return 0;
+}
+
+int watchdog_disable(void)
+{
+	csr_write(csr_read() & ~WDT_ENABLE);
+	return 0;
+}
+#endif
+
+void reset_cpu(unsigned long ignored)
+{
+	while (1)
+		;
 }

disk/part.c

@@ -117,6 +117,7 @@ void dev_print (block_dev_desc_t *dev_desc)
 			dev_desc->product,
 			dev_desc->revision);
 		break;
+	case IF_TYPE_ATAPI:
 	case IF_TYPE_IDE:
 	case IF_TYPE_SATA:
 		printf ("Model: %s Firm: %s Ser#: %s\n",
@@ -124,15 +125,22 @@ void dev_print (block_dev_desc_t *dev_desc)
 			dev_desc->revision,
 			dev_desc->product);
 		break;
+	case IF_TYPE_SD:
+	case IF_TYPE_MMC:
 	case IF_TYPE_USB:
 		printf ("Vendor: %s Rev: %s Prod: %s\n",
 			dev_desc->vendor,
 			dev_desc->revision,
 			dev_desc->product);
 		break;
+	case IF_TYPE_DOC:
+		puts("device type DOC\n");
+		return;
 	case IF_TYPE_UNKNOWN:
+		puts("device type unknown\n");
+		return;
 	default:
-		puts ("not available\n");
+		printf("Unhandled device type: %i\n", dev_desc->if_type);
 		return;
 	}
 	puts ("            Type: ");

doc/README.PIP405

@@ -132,14 +132,6 @@ Identify:
 ---------
 CONFIG_IDENT_STRING		added to the U_BOOT_VERSION String
 
-
-I2C stuff:
-----------
-CFG_EEPROM_PAGE_WRITE_ENABLE	enables page write of the I2C EEPROM
-				CFG_EEPROM_PAGE_WRITE_BITS _must_ be
-				defined.
-
-
 Environment / Console:
 ----------------------
 

doc/README.imx31

@@ -0,0 +1,29 @@
+U-Boot for Freescale i.MX31
+
+This file contains information for the port of U-Boot to the Freescale
+i.MX31 SoC.
+
+1. CONFIGURATION OPTIONS/SETTINGS
+---------------------------------
+
+1.1 Configuration of MC13783 SPI bus
+------------------------------------
+	The power management companion chip MC13783 is connected to the
+	i.MX31 via an SPI bus. Use the following configuration options
+	to setup the bus and chip select used for a particular board.
+
+	CONFIG_MC13783_SPI_BUS	-- defines the SPI bus the MC13783 is connected to.
+			   Note that 0 is CSPI1, 1 is CSPI2 and 2 is CSPI3.
+	CONFIG_MC13783_SPI_CS	-- define the chip select the MC13783 s connected to.
+
+1.2 Timer precision
+-------------------
+	CONFIG_MX31_TIMER_HIGH_PRECISION
+
+	Enable higher precision timer. The low-precision timer
+	(default) provides approximately 4% error, whereas the
+	high-precision timer is about 0.4% accurate. The extra
+	accuracy is achieved at the cost of higher computational
+	overhead, which, in places where time is measured, should
+	not be critical, so, it should be safe to enable this
+	option.

doc/README.mx31

@@ -1,17 +0,0 @@
-U-Boot for Freescale i.MX31
-
-This file contains information for the port of U-Boot to the Freescale
-i.MX31 SoC.
-
-1. CONFIGURATION OPTIONS/SETTINGS
----------------------------------
-
-1.1 Configuration of MC13783 SPI bus
-------------------------------------
-The power management companion chip MC13783 is connected to the
-i.MX31 via an SPI bus. Use the following configuration options
-to setup the bus and chip select used for a particular board.
-
-CONFIG_MC13783_SPI_BUS	-- defines the SPI bus the MC13783 is connected to.
-			   Note that 0 is CSPI1, 1 is CSPI2 and 2 is CSPI3.
-CONFIG_MC13783_SPI_CS	-- define the chip select the MC13783 s connected to.

doc/uImage.FIT/multi.its

@@ -56,6 +56,7 @@
 			data = /incbin/("./eldk-4.2-ramdisk");
 			type = "ramdisk";
 			arch = "ppc";
+			os = "linux";
 			compression = "gzip";
 			hash@1 {
 				algo = "sha1";
@@ -67,6 +68,7 @@
 			data = /incbin/("./eldk-3.1-ramdisk");
 			type = "ramdisk";
 			arch = "ppc";
+			os = "linux";
 			compression = "gzip";
 			hash@1 {
 				algo = "crc32";

drivers/bios_emulator/x86emu/debug.c

@@ -50,7 +50,7 @@
 
 static void print_encoded_bytes(u16 s, u16 o);
 static void print_decoded_instruction(void);
-static int parse_line(char *s, int *ps, int *n);
+static int x86emu_parse_line(char *s, int *ps, int *n);
 
 /* should look something like debug's output. */
 void X86EMU_trace_regs(void)
@@ -257,7 +257,7 @@ void x86emu_single_step(void)
 	offset = M.x86.saved_ip;
 	while (!done) {
 		printk("-");
-		cmd = parse_line(s, ps, &ntok);
+		cmd = x86emu_parse_line(s, ps, &ntok);
 		switch (cmd) {
 		case 'u':
 			disassemble_forward(M.x86.saved_cs, (u16) offset, 10);
@@ -331,7 +331,7 @@ int X86EMU_trace_off(void)
 	return M.x86.debug &= ~(DEBUG_STEP_F | DEBUG_DECODE_F | DEBUG_TRACE_F);
 }
 
-static int parse_line(char *s, int *ps, int *n)
+static int x86emu_parse_line(char *s, int *ps, int *n)
 {
 	int cmd;
 

drivers/hwmon/ds1621.c

@@ -26,11 +26,6 @@
  */
 
 #include <common.h>
-
-#if !defined(CFG_EEPROM_PAGE_WRITE_ENABLE) || \
-	(CFG_EEPROM_PAGE_WRITE_BITS < 1)
-# error "CFG_EEPROM_PAGE_WRITE_ENABLE must be defined and CFG_EEPROM_PAGE_WRITE_BITS must be greater than 1 to use CONFIG_DTT_DS1621"
-#endif
 #include <i2c.h>
 #include <dtt.h>
 

drivers/hwmon/lm75.c

@@ -26,12 +26,6 @@
  */
 
 #include <common.h>
-
-#if !defined(CFG_EEPROM_PAGE_WRITE_ENABLE) || \
-	(CFG_EEPROM_PAGE_WRITE_BITS < 1)
-# error "CFG_EEPROM_PAGE_WRITE_ENABLE must be defined and CFG_EEPROM_PAGE_WRITE_BITS must be greater than  1 to use CONFIG_DTT_LM75"
-#endif
-
 #include <i2c.h>
 #include <dtt.h>
 

drivers/hwmon/lm81.c

@@ -31,12 +31,6 @@
  */
 
 #include <common.h>
-
-#if !defined(CFG_EEPROM_PAGE_WRITE_ENABLE) || \
-	(CFG_EEPROM_PAGE_WRITE_BITS < 1)
-# error "CFG_EEPROM_PAGE_WRITE_ENABLE must be defined and CFG_EEPROM_PAGE_WRITE_BITS must be greater than  1 to use CONFIG_DTT_LM81"
-#endif
-
 #include <i2c.h>
 #include <dtt.h>
 

drivers/mtd/cfi_flash.c

@@ -681,7 +681,7 @@ static int flash_full_status_check (flash_info_t * info, flash_sect_t sector,
 	case CFI_CMDSET_INTEL_PROG_REGIONS:
 	case CFI_CMDSET_INTEL_EXTENDED:
 	case CFI_CMDSET_INTEL_STANDARD:
-		if ((retcode == ERR_OK)
+		if ((retcode != ERR_OK)
 		    && !flash_isequal (info, sector, 0, FLASH_STATUS_DONE)) {
 			retcode = ERR_INVAL;
 			printf ("Flash %s error at address %lx\n", prompt,
@@ -777,6 +777,7 @@ static int flash_write_cfiword (flash_info_t * info, ulong dest,
 {
 	void *dstaddr;
 	int flag;
+	flash_sect_t sect;
 
 	dstaddr = map_physmem(dest, info->portwidth, MAP_NOCACHE);
 
@@ -818,8 +819,9 @@ static int flash_write_cfiword (flash_info_t * info, ulong dest,
 #ifdef CONFIG_FLASH_CFI_LEGACY
 	case CFI_CMDSET_AMD_LEGACY:
 #endif
-		flash_unlock_seq (info, 0);
-		flash_write_cmd (info, 0, info->addr_unlock1, AMD_CMD_WRITE);
+		sect = find_sector(info, dest);
+		flash_unlock_seq (info, sect);
+		flash_write_cmd (info, sect, info->addr_unlock1, AMD_CMD_WRITE);
 		break;
 	}
 
@@ -1932,9 +1934,10 @@ ulong flash_get_size (ulong base, int banknum)
 			/* XXX - Need to test on x8/x16 in parallel. */
 			info->portwidth >>= 1;
 		}
+
+		flash_write_cmd (info, 0, 0, info->cmd_reset);
 	}
 
-	flash_write_cmd (info, 0, 0, info->cmd_reset);
 	return (info->size);
 }
 

drivers/mtd/nand/nand.c

@@ -63,11 +63,11 @@ void nand_init(void)
 	unsigned int size = 0;
 	for (i = 0; i < CFG_MAX_NAND_DEVICE; i++) {
 		nand_init_chip(&nand_info[i], &nand_chip[i], base_address[i]);
-		size += nand_info[i].size;
+		size += nand_info[i].size / 1024;
 		if (nand_curr_device == -1)
 			nand_curr_device = i;
 	}
-	printf("%u MiB\n", size / (1024 * 1024));
+	printf("%u MiB\n", size / 1024);
 
 #ifdef CFG_NAND_SELECT_DEVICE
 	/*

drivers/net/Makefile

@@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk
 LIB	:= $(obj)libnet.a
 
 COBJS-$(CONFIG_DRIVER_3C589) += 3c589.o
+COBJS-$(CONFIG_DRIVER_AX88180) += ax88180.o
 COBJS-$(CONFIG_BCM570x) += bcm570x.o bcm570x_autoneg.o 5701rls.o
 COBJS-$(CONFIG_BFIN_MAC) += bfin_mac.o
 COBJS-$(CONFIG_DRIVER_CS8900) += cs8900.o
@@ -44,10 +45,8 @@ COBJS-$(CONFIG_MCFFEC) += mcffec.o
 COBJS-$(CONFIG_MPC5xxx_FEC) += mpc5xxx_fec.o
 COBJS-$(CONFIG_MPC512x_FEC) += mpc512x_fec.o
 COBJS-$(CONFIG_NATSEMI) += natsemi.o
-ifeq ($(CONFIG_DRIVER_NE2000),y)
-COBJS-y += ne2000.o
-COBJS-$(CONFIG_DRIVER_AX88796L) += ax88796.o
-endif
+COBJS-$(CONFIG_DRIVER_NE2000) += ne2000.o ne2000_base.o
+COBJS-$(CONFIG_DRIVER_AX88796L) += ax88796.o ne2000_base.o
 COBJS-$(CONFIG_DRIVER_NETARMETH) += netarm_eth.o
 COBJS-$(CONFIG_NETCONSOLE) += netconsole.o
 COBJS-$(CONFIG_DRIVER_NS7520_ETHERNET) += ns7520_eth.o

drivers/net/ax88180.c

@@ -0,0 +1,727 @@
+/*
+ * ax88180: ASIX AX88180 Non-PCI Gigabit Ethernet u-boot driver
+ *
+ * This program is free software; you can distribute it and/or modify
+ * it under the terms of the GNU General Public License (Version 2) as
+ * published by the Free Software Foundation.
+ * This program is distributed in the hope it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307,
+ * USA.
+ */
+
+/*
+ * ========================================================================
+ * ASIX AX88180 Non-PCI 16/32-bit Gigabit Ethernet Linux Driver
+ *
+ * The AX88180 Ethernet controller is a high performance and highly
+ * integrated local CPU bus Ethernet controller with embedded 40K bytes
+ * SRAM and supports both 16-bit and 32-bit SRAM-Like interfaces for any
+ * embedded systems.
+ * The AX88180 is a single chip 10/100/1000Mbps Gigabit Ethernet
+ * controller that supports both MII and RGMII interfaces and is
+ * compliant to IEEE 802.3, IEEE 802.3u and IEEE 802.3z standards.
+ *
+ * Please visit ASIX's web site (http://www.asix.com.tw) for more
+ * details.
+ *
+ * Module Name	: ax88180.c
+ * Date		: 2008-07-07
+ * History
+ * 09/06/2006	: New release for AX88180 US2 chip.
+ * 07/07/2008	: Fix up the coding style and using inline functions
+ *		  instead of macros
+ * ========================================================================
+ */
+#include <common.h>
+#include <command.h>
+#include <net.h>
+#include <malloc.h>
+#include "ax88180.h"
+
+/*
+ * ===========================================================================
+ * Local SubProgram Declaration
+ * ===========================================================================
+ */
+static void ax88180_rx_handler (struct eth_device *dev);
+static int ax88180_phy_initial (struct eth_device *dev);
+static void ax88180_meidia_config (struct eth_device *dev);
+static unsigned long get_CicadaPHY_meida_mode (struct eth_device *dev);
+static unsigned long get_MarvellPHY_meida_mode (struct eth_device *dev);
+static unsigned short ax88180_mdio_read (struct eth_device *dev,
+					 unsigned long regaddr);
+static void ax88180_mdio_write (struct eth_device *dev,
+				unsigned long regaddr, unsigned short regdata);
+
+/*
+ * ===========================================================================
+ * Local SubProgram Bodies
+ * ===========================================================================
+ */
+static int ax88180_mdio_check_complete (struct eth_device *dev)
+{
+	int us_cnt = 10000;
+	unsigned short tmpval;
+
+	/* MDIO read/write should not take more than 10 ms */
+	while (--us_cnt) {
+		tmpval = INW (dev, MDIOCTRL);
+		if (((tmpval & READ_PHY) == 0) && ((tmpval & WRITE_PHY) == 0))
+			break;
+	}
+
+	return us_cnt;
+}
+
+static unsigned short
+ax88180_mdio_read (struct eth_device *dev, unsigned long regaddr)
+{
+	struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
+	unsigned long tmpval = 0;
+
+	OUTW (dev, (READ_PHY | (regaddr << 8) | priv->PhyAddr), MDIOCTRL);
+
+	if (ax88180_mdio_check_complete (dev))
+		tmpval = INW (dev, MDIODP);
+	else
+		printf ("Failed to read PHY register!\n");
+
+	return (unsigned short)(tmpval & 0xFFFF);
+}
+
+static void
+ax88180_mdio_write (struct eth_device *dev, unsigned long regaddr,
+		    unsigned short regdata)
+{
+	struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
+
+	OUTW (dev, regdata, MDIODP);
+
+	OUTW (dev, (WRITE_PHY | (regaddr << 8) | priv->PhyAddr), MDIOCTRL);
+
+	if (!ax88180_mdio_check_complete (dev))
+		printf ("Failed to write PHY register!\n");
+}
+
+static int ax88180_phy_reset (struct eth_device *dev)
+{
+	unsigned short delay_cnt = 500;
+
+	ax88180_mdio_write (dev, BMCR, (PHY_RESET | AUTONEG_EN));
+
+	/* Wait for the reset to complete, or time out (500 ms) */
+	while (ax88180_mdio_read (dev, BMCR) & PHY_RESET) {
+		udelay (1000);
+		if (--delay_cnt == 0) {
+			printf ("Failed to reset PHY!\n");
+			return -1;
+		}
+	}
+
+	return 0;
+}
+
+static void ax88180_mac_reset (struct eth_device *dev)
+{
+	unsigned long tmpval;
+	unsigned char i;
+
+	struct {
+		unsigned short offset, value;
+	} program_seq[] = {
+		{
+		MISC, MISC_NORMAL}, {
+		RXINDICATOR, DEFAULT_RXINDICATOR}, {
+		TXCMD, DEFAULT_TXCMD}, {
+		TXBS, DEFAULT_TXBS}, {
+		TXDES0, DEFAULT_TXDES0}, {
+		TXDES1, DEFAULT_TXDES1}, {
+		TXDES2, DEFAULT_TXDES2}, {
+		TXDES3, DEFAULT_TXDES3}, {
+		TXCFG, DEFAULT_TXCFG}, {
+		MACCFG2, DEFAULT_MACCFG2}, {
+		MACCFG3, DEFAULT_MACCFG3}, {
+		TXLEN, DEFAULT_TXLEN}, {
+		RXBTHD0, DEFAULT_RXBTHD0}, {
+		RXBTHD1, DEFAULT_RXBTHD1}, {
+		RXFULTHD, DEFAULT_RXFULTHD}, {
+		DOGTHD0, DEFAULT_DOGTHD0}, {
+	DOGTHD1, DEFAULT_DOGTHD1},};
+
+	OUTW (dev, MISC_RESET_MAC, MISC);
+	tmpval = INW (dev, MISC);
+
+	for (i = 0; i < (sizeof (program_seq) / sizeof (program_seq[0])); i++)
+		OUTW (dev, program_seq[i].value, program_seq[i].offset);
+}
+
+static int ax88180_poll_tx_complete (struct eth_device *dev)
+{
+	struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
+	unsigned long tmpval, txbs_txdp;
+	int TimeOutCnt = 10000;
+
+	txbs_txdp = 1 << priv->NextTxDesc;
+
+	while (TimeOutCnt--) {
+
+		tmpval = INW (dev, TXBS);
+
+		if ((tmpval & txbs_txdp) == 0)
+			break;
+
+		udelay (100);
+	}
+
+	if (TimeOutCnt)
+		return 0;
+	else
+		return -TimeOutCnt;
+}
+
+static void ax88180_rx_handler (struct eth_device *dev)
+{
+	struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
+	unsigned long data_size;
+	unsigned short rxcurt_ptr, rxbound_ptr, next_ptr;
+	int i;
+#if defined (CONFIG_DRIVER_AX88180_16BIT)
+	unsigned short *rxdata = (unsigned short *)NetRxPackets[0];
+#else
+	unsigned long *rxdata = (unsigned long *)NetRxPackets[0];
+#endif
+	unsigned short count;
+
+	rxcurt_ptr = INW (dev, RXCURT);
+	rxbound_ptr = INW (dev, RXBOUND);
+	next_ptr = (rxbound_ptr + 1) & RX_PAGE_NUM_MASK;
+
+	debug ("ax88180: RX original RXBOUND=0x%04x,"
+	       " RXCURT=0x%04x\n", rxbound_ptr, rxcurt_ptr);
+
+	while (next_ptr != rxcurt_ptr) {
+
+		OUTW (dev, RX_START_READ, RXINDICATOR);
+
+		data_size = READ_RXBUF (dev) & 0xFFFF;
+
+		if ((data_size == 0) || (data_size > MAX_RX_SIZE)) {
+
+			OUTW (dev, RX_STOP_READ, RXINDICATOR);
+
+			ax88180_mac_reset (dev);
+			printf ("ax88180: Invalid Rx packet length!"
+				" (len=0x%04lx)\n", data_size);
+
+			debug ("ax88180: RX RXBOUND=0x%04x,"
+			       "RXCURT=0x%04x\n", rxbound_ptr, rxcurt_ptr);
+			return;
+		}
+
+		rxbound_ptr += (((data_size + 0xF) & 0xFFF0) >> 4) + 1;
+		rxbound_ptr &= RX_PAGE_NUM_MASK;
+
+		/* Comput access times */
+		count = (data_size + priv->PadSize) >> priv->BusWidth;
+
+		for (i = 0; i < count; i++) {
+			*(rxdata + i) = READ_RXBUF (dev);
+		}
+
+		OUTW (dev, RX_STOP_READ, RXINDICATOR);
+
+		/* Pass the packet up to the protocol layers. */
+		NetReceive (NetRxPackets[0], data_size);
+
+		OUTW (dev, rxbound_ptr, RXBOUND);
+
+		rxcurt_ptr = INW (dev, RXCURT);
+		rxbound_ptr = INW (dev, RXBOUND);
+		next_ptr = (rxbound_ptr + 1) & RX_PAGE_NUM_MASK;
+
+		debug ("ax88180: RX updated RXBOUND=0x%04x,"
+		       "RXCURT=0x%04x\n", rxbound_ptr, rxcurt_ptr);
+	}
+
+	return;
+}
+
+static int ax88180_phy_initial (struct eth_device *dev)
+{
+	struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
+	unsigned long tmp_regval;
+
+	/* Check avaliable PHY chipset  */
+	priv->PhyAddr = MARVELL_88E1111_PHYADDR;
+	priv->PhyID0 = ax88180_mdio_read (dev, PHYIDR0);
+
+	if (priv->PhyID0 == MARVELL_88E1111_PHYIDR0) {
+
+		debug ("ax88180: Found Marvell 88E1111 PHY."
+		       " (PHY Addr=0x%x)\n", priv->PhyAddr);
+
+		tmp_regval = ax88180_mdio_read (dev, M88_EXT_SSR);
+		if ((tmp_regval & HWCFG_MODE_MASK) == RGMII_COPPER_MODE) {
+
+			ax88180_mdio_write (dev, M88_EXT_SCR, DEFAULT_EXT_SCR);
+			if (ax88180_phy_reset (dev) < 0)
+				return 0;
+			ax88180_mdio_write (dev, M88_IER, LINK_CHANGE_INT);
+		}
+	} else {
+
+		priv->PhyAddr = CICADA_CIS8201_PHYADDR;
+		priv->PhyID0 = ax88180_mdio_read (dev, PHYIDR0);
+
+		if (priv->PhyID0 == CICADA_CIS8201_PHYIDR0) {
+
+			debug ("ax88180: Found CICADA CIS8201 PHY"
+			       " chipset. (PHY Addr=0x%x)\n", priv->PhyAddr);
+			ax88180_mdio_write (dev, CIS_IMR,
+					    (CIS_INT_ENABLE | LINK_CHANGE_INT));
+
+			/* Set CIS_SMI_PRIORITY bit before force the media mode */
+			tmp_regval =
+			    ax88180_mdio_read (dev, CIS_AUX_CTRL_STATUS);
+			tmp_regval &= ~CIS_SMI_PRIORITY;
+			ax88180_mdio_write (dev, CIS_AUX_CTRL_STATUS,
+					    tmp_regval);
+		} else {
+			printf ("ax88180: Unknown PHY chipset!!\n");
+			return 0;
+		}
+	}
+
+	return 1;
+}
+
+static void ax88180_meidia_config (struct eth_device *dev)
+{
+	struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
+	unsigned long bmcr_val, bmsr_val;
+	unsigned long rxcfg_val, maccfg0_val, maccfg1_val;
+	unsigned long RealMediaMode;
+	int i;
+
+	/* Waiting 2 seconds for PHY link stable */
+	for (i = 0; i < 20000; i++) {
+		bmsr_val = ax88180_mdio_read (dev, BMSR);
+		if (bmsr_val & LINKOK) {
+			break;
+		}
+		udelay (100);
+	}
+
+	bmsr_val = ax88180_mdio_read (dev, BMSR);
+	debug ("ax88180: BMSR=0x%04x\n", (unsigned int)bmsr_val);
+
+	if (bmsr_val & LINKOK) {
+		bmcr_val = ax88180_mdio_read (dev, BMCR);
+
+		if (bmcr_val & AUTONEG_EN) {
+
+			/*
+			 * Waiting for Auto-negotiation completion, this may
+			 * take up to 5 seconds.
+			 */
+			debug ("ax88180: Auto-negotiation is "
+			       "enabled. Waiting for NWay completion..\n");
+			for (i = 0; i < 50000; i++) {
+				bmsr_val = ax88180_mdio_read (dev, BMSR);
+				if (bmsr_val & AUTONEG_COMPLETE) {
+					break;
+				}
+				udelay (100);
+			}
+		} else
+			debug ("ax88180: Auto-negotiation is disabled.\n");
+
+		debug ("ax88180: BMCR=0x%04x, BMSR=0x%04x\n",
+		       (unsigned int)bmcr_val, (unsigned int)bmsr_val);
+
+		/* Get real media mode here */
+		if (priv->PhyID0 == MARVELL_88E1111_PHYIDR0) {
+			RealMediaMode = get_MarvellPHY_meida_mode (dev);
+		} else if (priv->PhyID0 == CICADA_CIS8201_PHYIDR0) {
+			RealMediaMode = get_CicadaPHY_meida_mode (dev);
+		} else {
+			RealMediaMode = MEDIA_1000FULL;
+		}
+
+		priv->LinkState = INS_LINK_UP;
+
+		switch (RealMediaMode) {
+		case MEDIA_1000FULL:
+			debug ("ax88180: 1000Mbps Full-duplex mode.\n");
+			rxcfg_val = RXFLOW_ENABLE | DEFAULT_RXCFG;
+			maccfg0_val = TXFLOW_ENABLE | DEFAULT_MACCFG0;
+			maccfg1_val = GIGA_MODE_EN | RXFLOW_EN |
+			    FULLDUPLEX | DEFAULT_MACCFG1;
+			break;
+
+		case MEDIA_1000HALF:
+			debug ("ax88180: 1000Mbps Half-duplex mode.\n");
+			rxcfg_val = DEFAULT_RXCFG;
+			maccfg0_val = DEFAULT_MACCFG0;
+			maccfg1_val = GIGA_MODE_EN | DEFAULT_MACCFG1;
+			break;
+
+		case MEDIA_100FULL:
+			debug ("ax88180: 100Mbps Full-duplex mode.\n");
+			rxcfg_val = RXFLOW_ENABLE | DEFAULT_RXCFG;
+			maccfg0_val = SPEED100 | TXFLOW_ENABLE
+			    | DEFAULT_MACCFG0;
+			maccfg1_val = RXFLOW_EN | FULLDUPLEX | DEFAULT_MACCFG1;
+			break;
+
+		case MEDIA_100HALF:
+			debug ("ax88180: 100Mbps Half-duplex mode.\n");
+			rxcfg_val = DEFAULT_RXCFG;
+			maccfg0_val = SPEED100 | DEFAULT_MACCFG0;
+			maccfg1_val = DEFAULT_MACCFG1;
+			break;
+
+		case MEDIA_10FULL:
+			debug ("ax88180: 10Mbps Full-duplex mode.\n");
+			rxcfg_val = RXFLOW_ENABLE | DEFAULT_RXCFG;
+			maccfg0_val = TXFLOW_ENABLE | DEFAULT_MACCFG0;
+			maccfg1_val = RXFLOW_EN | FULLDUPLEX | DEFAULT_MACCFG1;
+			break;
+
+		case MEDIA_10HALF:
+			debug ("ax88180: 10Mbps Half-duplex mode.\n");
+			rxcfg_val = DEFAULT_RXCFG;
+			maccfg0_val = DEFAULT_MACCFG0;
+			maccfg1_val = DEFAULT_MACCFG1;
+			break;
+		default:
+			debug ("ax88180: Unknow media mode.\n");
+			rxcfg_val = DEFAULT_RXCFG;
+			maccfg0_val = DEFAULT_MACCFG0;
+			maccfg1_val = DEFAULT_MACCFG1;
+
+			priv->LinkState = INS_LINK_DOWN;
+			break;
+		}
+
+	} else {
+		rxcfg_val = DEFAULT_RXCFG;
+		maccfg0_val = DEFAULT_MACCFG0;
+		maccfg1_val = DEFAULT_MACCFG1;
+
+		priv->LinkState = INS_LINK_DOWN;
+	}
+
+	OUTW (dev, rxcfg_val, RXCFG);
+	OUTW (dev, maccfg0_val, MACCFG0);
+	OUTW (dev, maccfg1_val, MACCFG1);
+
+	return;
+}
+
+static unsigned long get_MarvellPHY_meida_mode (struct eth_device *dev)
+{
+	unsigned long m88_ssr;
+	unsigned long MediaMode;
+
+	m88_ssr = ax88180_mdio_read (dev, M88_SSR);
+	switch (m88_ssr & SSR_MEDIA_MASK) {
+	case SSR_1000FULL:
+		MediaMode = MEDIA_1000FULL;
+		break;
+	case SSR_1000HALF:
+		MediaMode = MEDIA_1000HALF;
+		break;
+	case SSR_100FULL:
+		MediaMode = MEDIA_100FULL;
+		break;
+	case SSR_100HALF:
+		MediaMode = MEDIA_100HALF;
+		break;
+	case SSR_10FULL:
+		MediaMode = MEDIA_10FULL;
+		break;
+	case SSR_10HALF:
+		MediaMode = MEDIA_10HALF;
+		break;
+	default:
+		MediaMode = MEDIA_UNKNOWN;
+		break;
+	}
+
+	return MediaMode;
+}
+
+static unsigned long get_CicadaPHY_meida_mode (struct eth_device *dev)
+{
+	unsigned long tmp_regval;
+	unsigned long MediaMode;
+
+	tmp_regval = ax88180_mdio_read (dev, CIS_AUX_CTRL_STATUS);
+	switch (tmp_regval & CIS_MEDIA_MASK) {
+	case CIS_1000FULL:
+		MediaMode = MEDIA_1000FULL;
+		break;
+	case CIS_1000HALF:
+		MediaMode = MEDIA_1000HALF;
+		break;
+	case CIS_100FULL:
+		MediaMode = MEDIA_100FULL;
+		break;
+	case CIS_100HALF:
+		MediaMode = MEDIA_100HALF;
+		break;
+	case CIS_10FULL:
+		MediaMode = MEDIA_10FULL;
+		break;
+	case CIS_10HALF:
+		MediaMode = MEDIA_10HALF;
+		break;
+	default:
+		MediaMode = MEDIA_UNKNOWN;
+		break;
+	}
+
+	return MediaMode;
+}
+
+static void ax88180_halt (struct eth_device *dev)
+{
+	/* Disable AX88180 TX/RX functions */
+	OUTW (dev, WAKEMOD, CMD);
+}
+
+static int ax88180_init (struct eth_device *dev, bd_t * bd)
+{
+	struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
+	unsigned short tmp_regval;
+
+	ax88180_mac_reset (dev);
+
+	/* Disable interrupt */
+	OUTW (dev, CLEAR_IMR, IMR);
+
+	/* Disable AX88180 TX/RX functions */
+	OUTW (dev, WAKEMOD, CMD);
+
+	/* Fill the MAC address */
+	tmp_regval =
+	    dev->enetaddr[0] | (((unsigned short)dev->enetaddr[1]) << 8);
+	OUTW (dev, tmp_regval, MACID0);
+
+	tmp_regval =
+	    dev->enetaddr[2] | (((unsigned short)dev->enetaddr[3]) << 8);
+	OUTW (dev, tmp_regval, MACID1);
+
+	tmp_regval =
+	    dev->enetaddr[4] | (((unsigned short)dev->enetaddr[5]) << 8);
+	OUTW (dev, tmp_regval, MACID2);
+
+	ax88180_meidia_config (dev);
+
+	OUTW (dev, DEFAULT_RXFILTER, RXFILTER);
+
+	/* Initial variables here */
+	priv->FirstTxDesc = TXDP0;
+	priv->NextTxDesc = TXDP0;
+
+	/* Check if there is any invalid interrupt status and clear it. */
+	OUTW (dev, INW (dev, ISR), ISR);
+
+	/* Start AX88180 TX/RX functions */
+	OUTW (dev, (RXEN | TXEN | WAKEMOD), CMD);
+
+	return 0;
+}
+
+/* Get a data block via Ethernet */
+static int ax88180_recv (struct eth_device *dev)
+{
+	unsigned short ISR_Status;
+	unsigned short tmp_regval;
+
+	/* Read and check interrupt status here. */
+	ISR_Status = INW (dev, ISR);
+
+	while (ISR_Status) {
+		/* Clear the interrupt status */
+		OUTW (dev, ISR_Status, ISR);
+
+		debug ("\nax88180: The interrupt status = 0x%04x\n",
+		       ISR_Status);
+
+		if (ISR_Status & ISR_PHY) {
+			/* Read ISR register once to clear PHY interrupt bit */
+			tmp_regval = ax88180_mdio_read (dev, M88_ISR);
+			ax88180_meidia_config (dev);
+		}
+
+		if ((ISR_Status & ISR_RX) || (ISR_Status & ISR_RXBUFFOVR)) {
+			ax88180_rx_handler (dev);
+		}
+
+		/* Read and check interrupt status again */
+		ISR_Status = INW (dev, ISR);
+	}
+
+	return 0;
+}
+
+/* Send a data block via Ethernet. */
+static int
+ax88180_send (struct eth_device *dev, volatile void *packet, int length)
+{
+	struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
+	unsigned short TXDES_addr;
+	unsigned short txcmd_txdp, txbs_txdp;
+	unsigned short tmp_data;
+	int i;
+#if defined (CONFIG_DRIVER_AX88180_16BIT)
+	volatile unsigned short *txdata = (volatile unsigned short *)packet;
+#else
+	volatile unsigned long *txdata = (volatile unsigned long *)packet;
+#endif
+	unsigned short count;
+
+	if (priv->LinkState != INS_LINK_UP) {
+		return 0;
+	}
+
+	priv->FirstTxDesc = priv->NextTxDesc;
+	txbs_txdp = 1 << priv->FirstTxDesc;
+
+	debug ("ax88180: TXDP%d is available\n", priv->FirstTxDesc);
+
+	txcmd_txdp = priv->FirstTxDesc << 13;
+	TXDES_addr = TXDES0 + (priv->FirstTxDesc << 2);
+
+	OUTW (dev, (txcmd_txdp | length | TX_START_WRITE), TXCMD);
+
+	/* Comput access times */
+	count = (length + priv->PadSize) >> priv->BusWidth;
+
+	for (i = 0; i < count; i++) {
+		WRITE_TXBUF (dev, *(txdata + i));
+	}
+
+	OUTW (dev, txcmd_txdp | length, TXCMD);
+	OUTW (dev, txbs_txdp, TXBS);
+	OUTW (dev, (TXDPx_ENABLE | length), TXDES_addr);
+
+	priv->NextTxDesc = (priv->NextTxDesc + 1) & TXDP_MASK;
+
+	/*
+	 * Check the available transmit descriptor, if we had exhausted all
+	 * transmit descriptor ,then we have to wait for at least one free
+	 * descriptor
+	 */
+	txbs_txdp = 1 << priv->NextTxDesc;
+	tmp_data = INW (dev, TXBS);
+
+	if (tmp_data & txbs_txdp) {
+		if (ax88180_poll_tx_complete (dev) < 0) {
+			ax88180_mac_reset (dev);
+			priv->FirstTxDesc = TXDP0;
+			priv->NextTxDesc = TXDP0;
+			printf ("ax88180: Transmit time out occurred!\n");
+		}
+	}
+
+	return 0;
+}
+
+static void ax88180_read_mac_addr (struct eth_device *dev)
+{
+	unsigned short macid0_val, macid1_val, macid2_val;
+	unsigned short tmp_regval;
+	unsigned short i;
+
+	/* Reload MAC address from EEPROM */
+	OUTW (dev, RELOAD_EEPROM, PROMCTRL);
+
+	/* Waiting for reload eeprom completion */
+	for (i = 0; i < 500; i++) {
+		tmp_regval = INW (dev, PROMCTRL);
+		if ((tmp_regval & RELOAD_EEPROM) == 0)
+			break;
+		udelay (1000);
+	}
+
+	/* Get MAC addresses */
+	macid0_val = INW (dev, MACID0);
+	macid1_val = INW (dev, MACID1);
+	macid2_val = INW (dev, MACID2);
+
+	if (((macid0_val | macid1_val | macid2_val) != 0) &&
+	    ((macid0_val & 0x01) == 0)) {
+		dev->enetaddr[0] = (unsigned char)macid0_val;
+		dev->enetaddr[1] = (unsigned char)(macid0_val >> 8);
+		dev->enetaddr[2] = (unsigned char)macid1_val;
+		dev->enetaddr[3] = (unsigned char)(macid1_val >> 8);
+		dev->enetaddr[4] = (unsigned char)macid2_val;
+		dev->enetaddr[5] = (unsigned char)(macid2_val >> 8);
+	}
+}
+
+/*
+===========================================================================
+<<<<<<			Exported SubProgram Bodies		>>>>>>
+===========================================================================
+*/
+int ax88180_initialize (bd_t * bis)
+{
+	struct eth_device *dev;
+	struct ax88180_private *priv;
+
+	dev = (struct eth_device *)malloc (sizeof *dev);
+
+	if (NULL == dev)
+		return 0;
+
+	memset (dev, 0, sizeof *dev);
+
+	priv = (struct ax88180_private *)malloc (sizeof (*priv));
+
+	if (NULL == priv)
+		return 0;
+
+	memset (priv, 0, sizeof *priv);
+
+	sprintf (dev->name, "ax88180");
+	dev->iobase = AX88180_BASE;
+	dev->priv = priv;
+	dev->init = ax88180_init;
+	dev->halt = ax88180_halt;
+	dev->send = ax88180_send;
+	dev->recv = ax88180_recv;
+
+	priv->BusWidth = BUS_WIDTH_32;
+	priv->PadSize = 3;
+#if defined (CONFIG_DRIVER_AX88180_16BIT)
+	OUTW (dev, (START_BASE >> 8), BASE);
+	OUTW (dev, DECODE_EN, DECODE);
+
+	priv->BusWidth = BUS_WIDTH_16;
+	priv->PadSize = 1;
+#endif
+
+	ax88180_mac_reset (dev);
+
+	/* Disable interrupt */
+	OUTW (dev, CLEAR_IMR, IMR);
+
+	/* Disable AX88180 TX/RX functions */
+	OUTW (dev, WAKEMOD, CMD);
+
+	ax88180_read_mac_addr (dev);
+
+	eth_register (dev);
+
+	return ax88180_phy_initial (dev);
+
+}

drivers/net/ax88180.h

@@ -0,0 +1,412 @@
+/* ax88180.h: ASIX AX88180 Non-PCI Gigabit Ethernet u-boot driver */
+/*
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ */
+
+#ifndef _AX88180_H_
+#define _AX88180_H_
+
+#include <asm/types.h>
+#include <config.h>
+
+typedef enum _ax88180_link_state {
+	INS_LINK_DOWN,
+	INS_LINK_UP,
+	INS_LINK_UNKNOWN
+} ax88180_link_state;
+
+struct ax88180_private {
+	unsigned char BusWidth;
+	unsigned char PadSize;
+	unsigned short PhyAddr;
+	unsigned short PhyID0;
+	unsigned short FirstTxDesc;
+	unsigned short NextTxDesc;
+	ax88180_link_state LinkState;
+};
+
+#define BUS_WIDTH_16			1
+#define BUS_WIDTH_32			2
+
+#define ENABLE_JUMBO			1
+#define DISABLE_JUMBO			0
+
+#define ENABLE_BURST			1
+#define DISABLE_BURST			0
+
+#define NORMAL_RX_MODE		0
+#define RX_LOOPBACK_MODE		1
+#define RX_INIFINIT_LOOP_MODE		2
+#define TX_INIFINIT_LOOP_MODE		3
+
+#define DEFAULT_ETH_MTU		1500
+
+/* Jumbo packet size 4086 bytes included 4 bytes CRC*/
+#define MAX_JUMBO_MTU		4072
+
+/* Max Tx Jumbo size 4086 bytes included 4 bytes CRC */
+#define MAX_TX_JUMBO_SIZE		4086
+
+/* Max Rx Jumbo size is 15K Bytes */
+#define MAX_RX_SIZE			0x3C00
+
+#define MARVELL_88E1111_PHYADDR	0x18
+#define MARVELL_88E1111_PHYIDR0	0x0141
+
+#define CICADA_CIS8201_PHYADDR	0x01
+#define CICADA_CIS8201_PHYIDR0		0x000F
+
+#define MEDIA_AUTO			0
+#define MEDIA_1000FULL			1
+#define MEDIA_1000HALF			2
+#define MEDIA_100FULL			3
+#define MEDIA_100HALF			4
+#define MEDIA_10FULL			5
+#define MEDIA_10HALF			6
+#define MEDIA_UNKNOWN		7
+
+#define AUTO_MEDIA			0
+#define FORCE_MEDIA			1
+
+#define TXDP_MASK			3
+#define TXDP0				0
+#define TXDP1				1
+#define TXDP2				2
+#define TXDP3				3
+
+#define CMD_MAP_SIZE			0x100
+
+#if defined (CONFIG_DRIVER_AX88180_16BIT)
+  #define AX88180_MEMORY_SIZE		0x00004000
+  #define START_BASE			0x1000
+
+  #define RX_BUF_SIZE			0x1000
+  #define TX_BUF_SIZE			0x0F00
+
+  #define TX_BASE			START_BASE
+  #define CMD_BASE			(TX_BASE + TX_BUF_SIZE)
+  #define RX_BASE			(CMD_BASE + CMD_MAP_SIZE)
+#else
+  #define AX88180_MEMORY_SIZE	0x00010000
+
+  #define RX_BUF_SIZE			0x8000
+  #define TX_BUF_SIZE			0x7C00
+
+  #define RX_BASE			0x0000
+  #define TX_BASE			(RX_BASE + RX_BUF_SIZE)
+  #define CMD_BASE			(TX_BASE + TX_BUF_SIZE)
+#endif
+
+/* AX88180 Memory Mapping Definition */
+#define RXBUFFER_START			RX_BASE
+  #define RX_PACKET_LEN_OFFSET	0
+  #define RX_PAGE_NUM_MASK		0x7FF	/* RX pages 0~7FFh */
+#define TXBUFFER_START			TX_BASE
+
+/* AX88180 MAC Register Definition */
+#define DECODE		(0)
+  #define DECODE_EN		0x00000001
+#define BASE		(6)
+#define CMD		(CMD_BASE + 0x0000)
+  #define WAKEMOD		0x00000001
+  #define TXEN			0x00000100
+  #define RXEN			0x00000200
+  #define DEFAULT_CMD		WAKEMOD
+#define IMR		(CMD_BASE + 0x0004)
+  #define IMR_RXBUFFOVR	0x00000001
+  #define IMR_WATCHDOG	0x00000002
+  #define IMR_TX		0x00000008
+  #define IMR_RX		0x00000010
+  #define IMR_PHY		0x00000020
+  #define CLEAR_IMR		0x00000000
+  #define DEFAULT_IMR		(IMR_PHY | IMR_RX | IMR_TX |\
+					 IMR_RXBUFFOVR | IMR_WATCHDOG)
+#define ISR		(CMD_BASE + 0x0008)
+  #define ISR_RXBUFFOVR	0x00000001
+  #define ISR_WATCHDOG	0x00000002
+  #define ISR_TX			0x00000008
+  #define ISR_RX			0x00000010
+  #define ISR_PHY		0x00000020
+#define TXCFG		(CMD_BASE + 0x0010)
+  #define AUTOPAD_CRC		0x00000050
+  #define DEFAULT_TXCFG	AUTOPAD_CRC
+#define TXCMD		(CMD_BASE + 0x0014)
+  #define TXCMD_TXDP_MASK	0x00006000
+  #define TXCMD_TXDP0		0x00000000
+  #define TXCMD_TXDP1		0x00002000
+  #define TXCMD_TXDP2		0x00004000
+  #define TXCMD_TXDP3		0x00006000
+  #define TX_START_WRITE	0x00008000
+  #define TX_STOP_WRITE		0x00000000
+  #define DEFAULT_TXCMD	0x00000000
+#define TXBS		(CMD_BASE + 0x0018)
+  #define TXDP0_USED		0x00000001
+  #define TXDP1_USED		0x00000002
+  #define TXDP2_USED		0x00000004
+  #define TXDP3_USED		0x00000008
+  #define DEFAULT_TXBS		0x00000000
+#define TXDES0		(CMD_BASE + 0x0020)
+  #define TXDPx_ENABLE		0x00008000
+  #define TXDPx_LEN_MASK	0x00001FFF
+  #define DEFAULT_TXDES0	0x00000000
+#define TXDES1		(CMD_BASE + 0x0024)
+  #define TXDPx_ENABLE		0x00008000
+  #define TXDPx_LEN_MASK	0x00001FFF
+  #define DEFAULT_TXDES1	0x00000000
+#define TXDES2		(CMD_BASE + 0x0028)
+  #define TXDPx_ENABLE		0x00008000
+  #define TXDPx_LEN_MASK	0x00001FFF
+  #define DEFAULT_TXDES2	0x00000000
+#define TXDES3		(CMD_BASE + 0x002C)
+  #define TXDPx_ENABLE		0x00008000
+  #define TXDPx_LEN_MASK	0x00001FFF
+  #define DEFAULT_TXDES3	0x00000000
+#define RXCFG		(CMD_BASE + 0x0030)
+  #define RXBUFF_PROTECT	0x00000001
+  #define RXTCPCRC_CHECK	0x00000010
+  #define RXFLOW_ENABLE	0x00000100
+  #define DEFAULT_RXCFG	RXBUFF_PROTECT
+#define RXCURT		(CMD_BASE + 0x0034)
+  #define DEFAULT_RXCURT	0x00000000
+#define RXBOUND	(CMD_BASE + 0x0038)
+  #define DEFAULT_RXBOUND	0x7FF		/* RX pages 0~7FFh */
+#define MACCFG0	(CMD_BASE + 0x0040)
+  #define MACCFG0_BIT3_0	0x00000007
+  #define IPGT_VAL		0x00000150
+  #define TXFLOW_ENABLE	0x00001000
+  #define SPEED100		0x00008000
+  #define DEFAULT_MACCFG0	(IPGT_VAL | MACCFG0_BIT3_0)
+#define MACCFG1	(CMD_BASE + 0x0044)
+  #define RGMII_EN		0x00000002
+  #define RXFLOW_EN		0x00000020
+  #define FULLDUPLEX		0x00000040
+  #define MAX_JUMBO_LEN	0x00000780
+  #define RXJUMBO_EN		0x00000800
+  #define GIGA_MODE_EN	0x00001000
+  #define RXCRC_CHECK		0x00002000
+  #define RXPAUSE_DA_CHECK	0x00004000
+
+  #define JUMBO_LEN_4K		0x00000200
+  #define JUMBO_LEN_15K	0x00000780
+  #define DEFAULT_MACCFG1	(RXCRC_CHECK | RXPAUSE_DA_CHECK | \
+				 RGMII_EN)
+  #define CICADA_DEFAULT_MACCFG1	(RXCRC_CHECK | RXPAUSE_DA_CHECK)
+#define MACCFG2		(CMD_BASE + 0x0048)
+  #define MACCFG2_BIT15_8	0x00000100
+  #define JAM_LIMIT_MASK	0x000000FC
+  #define DEFAULT_JAM_LIMIT	0x00000064
+  #define DEFAULT_MACCFG2	MACCFG2_BIT15_8
+#define MACCFG3		(CMD_BASE + 0x004C)
+  #define IPGR2_VAL		0x0000000E
+  #define IPGR1_VAL		0x00000600
+  #define NOABORT		0x00008000
+  #define DEFAULT_MACCFG3	(IPGR1_VAL | IPGR2_VAL)
+#define TXPAUT		(CMD_BASE + 0x0054)
+  #define DEFAULT_TXPAUT	0x001FE000
+#define RXBTHD0		(CMD_BASE + 0x0058)
+  #define DEFAULT_RXBTHD0	0x00000300
+#define RXBTHD1		(CMD_BASE + 0x005C)
+  #define DEFAULT_RXBTHD1	0x00000600
+#define RXFULTHD	(CMD_BASE + 0x0060)
+  #define DEFAULT_RXFULTHD	0x00000100
+#define MISC		(CMD_BASE + 0x0068)
+  /* Normal operation mode */
+  #define MISC_NORMAL		0x00000003
+  /* Clear bit 0 to reset MAC */
+  #define MISC_RESET_MAC	0x00000002
+  /* Clear bit 1 to reset PHY */
+  #define MISC_RESET_PHY	0x00000001
+  /* Clear bit 0 and 1 to reset MAC and PHY */
+  #define MISC_RESET_MAC_PHY	0x00000000
+  #define DEFAULT_MISC		MISC_NORMAL
+#define MACID0		(CMD_BASE + 0x0070)
+#define MACID1		(CMD_BASE + 0x0074)
+#define MACID2		(CMD_BASE + 0x0078)
+#define TXLEN		(CMD_BASE + 0x007C)
+  #define DEFAULT_TXLEN	0x000005FC
+#define RXFILTER	(CMD_BASE + 0x0080)
+  #define RX_RXANY		0x00000001
+  #define RX_MULTICAST		0x00000002
+  #define RX_UNICAST		0x00000004
+  #define RX_BROADCAST	0x00000008
+  #define RX_MULTI_HASH	0x00000010
+  #define DISABLE_RXFILTER	0x00000000
+  #define DEFAULT_RXFILTER	(RX_BROADCAST + RX_UNICAST)
+#define MDIOCTRL	(CMD_BASE + 0x0084)
+  #define PHY_ADDR_MASK	0x0000001F
+  #define REG_ADDR_MASK	0x00001F00
+  #define READ_PHY		0x00004000
+  #define WRITE_PHY		0x00008000
+#define MDIODP		(CMD_BASE + 0x0088)
+#define GPIOCTRL	(CMD_BASE + 0x008C)
+#define RXINDICATOR	(CMD_BASE + 0x0090)
+  #define RX_START_READ	0x00000001
+  #define RX_STOP_READ		0x00000000
+  #define DEFAULT_RXINDICATOR	RX_STOP_READ
+#define TXST		(CMD_BASE + 0x0094)
+#define MDCCLKPAT	(CMD_BASE + 0x00A0)
+#define RXIPCRCCNT	(CMD_BASE + 0x00A4)
+#define RXCRCCNT	(CMD_BASE + 0x00A8)
+#define TXFAILCNT	(CMD_BASE + 0x00AC)
+#define PROMDP		(CMD_BASE + 0x00B0)
+#define PROMCTRL	(CMD_BASE + 0x00B4)
+  #define RELOAD_EEPROM	0x00000200
+#define MAXRXLEN	(CMD_BASE + 0x00B8)
+#define HASHTAB0	(CMD_BASE + 0x00C0)
+#define HASHTAB1	(CMD_BASE + 0x00C4)
+#define HASHTAB2	(CMD_BASE + 0x00C8)
+#define HASHTAB3	(CMD_BASE + 0x00CC)
+#define DOGTHD0	(CMD_BASE + 0x00E0)
+  #define DEFAULT_DOGTHD0	0x0000FFFF
+#define DOGTHD1	(CMD_BASE + 0x00E4)
+  #define START_WATCHDOG_TIMER	0x00008000
+  #define DEFAULT_DOGTHD1		0x00000FFF
+#define SOFTRST		(CMD_BASE + 0x00EC)
+  #define SOFTRST_NORMAL	0x00000003
+  #define SOFTRST_RESET_MAC	0x00000002
+
+/* External PHY Register Definition */
+#define BMCR		0x0000
+  #define LINE_SPEED_MSB	0x0040
+  #define DUPLEX_MODE		0x0100
+  #define RESTART_AUTONEG	0x0200
+  #define POWER_DOWN		0x0800
+  #define AUTONEG_EN		0x1000
+  #define LINE_SPEED_LSB	0x2000
+  #define PHY_RESET		0x8000
+
+  #define MEDIAMODE_MASK	(LINE_SPEED_MSB | LINE_SPEED_LSB |\
+				 DUPLEX_MODE)
+  #define BMCR_SPEED_1000	LINE_SPEED_MSB
+  #define BMCR_SPEED_100	LINE_SPEED_LSB
+  #define BMCR_SPEED_10	0x0000
+
+  #define BMCR_1000FULL	(BMCR_SPEED_1000 | DUPLEX_MODE)
+  #define BMCR_100FULL		(BMCR_SPEED_100 | DUPLEX_MODE)
+  #define BMCR_100HALF		BMCR_SPEED_100
+  #define BMCR_10FULL		DUPLEX_MODE
+  #define BMCR_10HALF		0x0000
+#define BMSR		0x0001
+  #define LINKOK		0x0004
+  #define AUTONEG_ENABLE_STS	0x0008
+  #define AUTONEG_COMPLETE	0x0020
+#define PHYIDR0		0x0002
+#define PHYIDR1		0x0003
+#define ANAR		0x0004
+  #define ANAR_PAUSE		0x0400
+  #define ANAR_100FULL		0x0100
+  #define ANAR_100HALF		0x0080
+  #define ANAR_10FULL		0x0040
+  #define ANAR_10HALF		0x0020
+  #define ANAR_8023BIT		0x0001
+#define ANLPAR		0x0005
+#define ANER		0x0006
+#define AUX_1000_CTRL	0x0009
+  #define ENABLE_1000HALF	0x0100
+  #define ENABLE_1000FULL	0x0200
+  #define DEFAULT_AUX_1000_CTRL	(ENABLE_1000HALF | ENABLE_1000FULL)
+#define AUX_1000_STATUS	0x000A
+  #define LP_1000HALF		0x0400
+  #define LP_1000FULL		0x0800
+
+/* Marvell 88E1111 Gigabit PHY Register Definition */
+#define M88_SSR		0x0011
+  #define SSR_SPEED_MASK	0xC000
+  #define SSR_SPEED_1000		0x8000
+  #define SSR_SPEED_100		0x4000
+  #define SSR_SPEED_10		0x0000
+  #define SSR_DUPLEX		0x2000
+  #define SSR_MEDIA_RESOLVED_OK	0x0800
+
+  #define SSR_MEDIA_MASK	(SSR_SPEED_MASK | SSR_DUPLEX)
+  #define SSR_1000FULL		(SSR_SPEED_1000 | SSR_DUPLEX)
+  #define SSR_1000HALF		SSR_SPEED_1000
+  #define SSR_100FULL		(SSR_SPEED_100 | SSR_DUPLEX)
+  #define SSR_100HALF		SSR_SPEED_100
+  #define SSR_10FULL		(SSR_SPEED_10 | SSR_DUPLEX)
+  #define SSR_10HALF		SSR_SPEED_10
+#define M88_IER		0x0012
+  #define LINK_CHANGE_INT	0x0400
+#define M88_ISR		0x0013
+  #define LINK_CHANGE_STATUS	0x0400
+#define M88_EXT_SCR	0x0014
+  #define RGMII_RXCLK_DELAY	0x0080
+  #define RGMII_TXCLK_DELAY	0x0002
+  #define DEFAULT_EXT_SCR	(RGMII_TXCLK_DELAY | RGMII_RXCLK_DELAY)
+#define M88_EXT_SSR	0x001B
+  #define HWCFG_MODE_MASK	0x000F
+  #define RGMII_COPPER_MODE	0x000B
+
+/* CICADA CIS8201 Gigabit PHY Register Definition */
+#define CIS_IMR		0x0019
+  #define CIS_INT_ENABLE	0x8000
+  #define CIS_LINK_CHANGE_INT	0x2000
+#define CIS_ISR		0x001A
+  #define CIS_INT_PENDING	0x8000
+  #define CIS_LINK_CHANGE_STATUS	0x2000
+#define CIS_AUX_CTRL_STATUS	0x001C
+  #define CIS_AUTONEG_COMPLETE	0x8000
+  #define CIS_SPEED_MASK	0x0018
+  #define CIS_SPEED_1000		0x0010
+  #define CIS_SPEED_100		0x0008
+  #define CIS_SPEED_10		0x0000
+  #define CIS_DUPLEX		0x0020
+
+  #define CIS_MEDIA_MASK	(CIS_SPEED_MASK | CIS_DUPLEX)
+  #define CIS_1000FULL		(CIS_SPEED_1000 | CIS_DUPLEX)
+  #define CIS_1000HALF		CIS_SPEED_1000
+  #define CIS_100FULL		(CIS_SPEED_100 | CIS_DUPLEX)
+  #define CIS_100HALF		CIS_SPEED_100
+  #define CIS_10FULL		(CIS_SPEED_10 | CIS_DUPLEX)
+  #define CIS_10HALF		CIS_SPEED_10
+  #define CIS_SMI_PRIORITY	0x0004
+
+static inline unsigned short INW (struct eth_device *dev, unsigned long addr)
+{
+	return le16_to_cpu (*(volatile unsigned short *) (addr + dev->iobase));
+}
+
+static inline void OUTW (struct eth_device *dev, unsigned short command, unsigned long addr)
+{
+	*(volatile unsigned short *) ((addr + dev->iobase)) = cpu_to_le16 (command);
+}
+
+/*
+ Access RXBUFFER_START/TXBUFFER_START to read RX buffer/write TX buffer
+*/
+#if defined (CONFIG_DRIVER_AX88180_16BIT)
+static inline unsigned short READ_RXBUF (struct eth_device *dev)
+{
+	return le16_to_cpu (*(volatile unsigned short *) (RXBUFFER_START + dev->iobase));
+}
+
+static inline void WRITE_TXBUF (struct eth_device *dev, unsigned short data)
+{
+	*(volatile unsigned short *) ((TXBUFFER_START + dev->iobase)) = cpu_to_le16 (data);
+}
+#else
+static inline unsigned long READ_RXBUF (struct eth_device *dev)
+{
+	return le32_to_cpu (*(volatile unsigned long *) (RXBUFFER_START + dev->iobase));
+}
+
+static inline void WRITE_TXBUF (struct eth_device *dev, unsigned long data)
+{
+	*(volatile unsigned long *) ((TXBUFFER_START + dev->iobase)) = cpu_to_le32 (data);
+}
+#endif
+
+#endif /* _AX88180_H_ */

drivers/net/ax88796.c

@@ -143,7 +143,7 @@ static void ax88796_mac_read(u8 *buff)
 	}
 }
 
-int get_prom(u8* mac_addr)
+int get_prom(u8* mac_addr, u8* base_addr)
 {
 	u8 prom[32];
 	int i;

drivers/net/ne2000.c

@@ -74,600 +74,11 @@ Add SNMP
 
 #include <common.h>
 #include <command.h>
-#include <net.h>
-#include <malloc.h>
-
-#define mdelay(n)	udelay((n)*1000)
-/* forward definition of function used for the uboot interface */
-void uboot_push_packet_len(int len);
-void uboot_push_tx_done(int key, int val);
-
-/*
- * Debugging details
- *
- * Set to perms of:
- * 0 disables all debug output
- * 1 for process debug output
- * 2 for added data IO output: get_reg, put_reg
- * 4 for packet allocation/free output
- * 8 for only startup status, so we can tell we're installed OK
- */
-#if 0
-#define DEBUG 0xf
-#else
-#define DEBUG 0
-#endif
-
-#if DEBUG & 1
-#define DEBUG_FUNCTION() do { printf("%s\n", __FUNCTION__); } while (0)
-#define DEBUG_LINE() do { printf("%d\n", __LINE__); } while (0)
-#define PRINTK(args...) printf(args)
-#else
-#define DEBUG_FUNCTION() do {} while(0)
-#define DEBUG_LINE() do {} while(0)
-#define PRINTK(args...)
-#endif
 
 /* NE2000 base header file */
 #include "ne2000_base.h"
 
-#if defined(CONFIG_DRIVER_AX88796L)
-/* AX88796L support */
-#include "ax88796.h"
-#else
-/* Basic NE2000 chip support */
-#include "ne2000.h"
-#endif
-
-static dp83902a_priv_data_t nic; /* just one instance of the card supported */
-
-static bool
-dp83902a_init(void)
-{
-	dp83902a_priv_data_t *dp = &nic;
-	u8* base;
-#if defined(NE2000_BASIC_INIT)
-	int i;
-#endif
-
-	DEBUG_FUNCTION();
-
-	base = dp->base;
-	if (!base)
-		return false;	/* No device found */
-
-	DEBUG_LINE();
-
-#if defined(NE2000_BASIC_INIT)
-	/* AX88796L doesn't need */
-	/* Prepare ESA */
-	DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE1);	/* Select page 1 */
-	/* Use the address from the serial EEPROM */
-	for (i = 0; i < 6; i++)
-		DP_IN(base, DP_P1_PAR0+i, dp->esa[i]);
-	DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE0);	/* Select page 0 */
-
-	printf("NE2000 - %s ESA: %02x:%02x:%02x:%02x:%02x:%02x\n",
-		"eeprom",
-		dp->esa[0],
-		dp->esa[1],
-		dp->esa[2],
-		dp->esa[3],
-		dp->esa[4],
-		dp->esa[5] );
-
-#endif	/* NE2000_BASIC_INIT */
-	return true;
-}
-
-static void
-dp83902a_stop(void)
-{
-	dp83902a_priv_data_t *dp = &nic;
-	u8 *base = dp->base;
-
-	DEBUG_FUNCTION();
-
-	DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_STOP);	/* Brutal */
-	DP_OUT(base, DP_ISR, 0xFF);		/* Clear any pending interrupts */
-	DP_OUT(base, DP_IMR, 0x00);		/* Disable all interrupts */
-
-	dp->running = false;
-}
-
-/*
- * This function is called to "start up" the interface. It may be called
- * multiple times, even when the hardware is already running. It will be
- * called whenever something "hardware oriented" changes and should leave
- * the hardware ready to send/receive packets.
- */
-static void
-dp83902a_start(u8 * enaddr)
-{
-	dp83902a_priv_data_t *dp = &nic;
-	u8 *base = dp->base;
-	int i;
-
-	DEBUG_FUNCTION();
-
-	DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_STOP); /* Brutal */
-	DP_OUT(base, DP_DCR, DP_DCR_INIT);
-	DP_OUT(base, DP_RBCH, 0);		/* Remote byte count */
-	DP_OUT(base, DP_RBCL, 0);
-	DP_OUT(base, DP_RCR, DP_RCR_MON);	/* Accept no packets */
-	DP_OUT(base, DP_TCR, DP_TCR_LOCAL);	/* Transmitter [virtually] off */
-	DP_OUT(base, DP_TPSR, dp->tx_buf1);	/* Transmitter start page */
-	dp->tx1 = dp->tx2 = 0;
-	dp->tx_next = dp->tx_buf1;
-	dp->tx_started = false;
-	dp->running = true;
-	DP_OUT(base, DP_PSTART, dp->rx_buf_start); /* Receive ring start page */
-	DP_OUT(base, DP_BNDRY, dp->rx_buf_end - 1); /* Receive ring boundary */
-	DP_OUT(base, DP_PSTOP, dp->rx_buf_end);	/* Receive ring end page */
-	dp->rx_next = dp->rx_buf_start - 1;
-	dp->running = true;
-	DP_OUT(base, DP_ISR, 0xFF);		/* Clear any pending interrupts */
-	DP_OUT(base, DP_IMR, DP_IMR_All);	/* Enable all interrupts */
-	DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE1 | DP_CR_STOP);	/* Select page 1 */
-	DP_OUT(base, DP_P1_CURP, dp->rx_buf_start);	/* Current page - next free page for Rx */
-	dp->running = true;
-	for (i = 0; i < ETHER_ADDR_LEN; i++) {
-		/* FIXME */
-		/*((vu_short*)( base + ((DP_P1_PAR0 + i) * 2) +
-		 * 0x1400)) = enaddr[i];*/
-		DP_OUT(base, DP_P1_PAR0+i, enaddr[i]);
-	}
-	/* Enable and start device */
-	DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START);
-	DP_OUT(base, DP_TCR, DP_TCR_NORMAL); /* Normal transmit operations */
-	DP_OUT(base, DP_RCR, DP_RCR_AB); /* Accept broadcast, no errors, no multicast */
-	dp->running = true;
-}
-
-/*
- * This routine is called to start the transmitter. It is split out from the
- * data handling routine so it may be called either when data becomes first
- * available or when an Tx interrupt occurs
- */
-
-static void
-dp83902a_start_xmit(int start_page, int len)
-{
-	dp83902a_priv_data_t *dp = (dp83902a_priv_data_t *) &nic;
-	u8 *base = dp->base;
-
-	DEBUG_FUNCTION();
-
-#if DEBUG & 1
-	printf("Tx pkt %d len %d\n", start_page, len);
-	if (dp->tx_started)
-		printf("TX already started?!?\n");
-#endif
-
-	DP_OUT(base, DP_ISR, (DP_ISR_TxP | DP_ISR_TxE));
-	DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START);
-	DP_OUT(base, DP_TBCL, len & 0xFF);
-	DP_OUT(base, DP_TBCH, len >> 8);
-	DP_OUT(base, DP_TPSR, start_page);
-	DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_TXPKT | DP_CR_START);
-
-	dp->tx_started = true;
-}
-
-/*
- * This routine is called to send data to the hardware. It is known a-priori
- * that there is free buffer space (dp->tx_next).
- */
-static void
-dp83902a_send(u8 *data, int total_len, u32 key)
-{
-	struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic;
-	u8 *base = dp->base;
-	int len, start_page, pkt_len, i, isr;
-#if DEBUG & 4
-	int dx;
-#endif
-
-	DEBUG_FUNCTION();
-
-	len = pkt_len = total_len;
-	if (pkt_len < IEEE_8023_MIN_FRAME)
-		pkt_len = IEEE_8023_MIN_FRAME;
-
-	start_page = dp->tx_next;
-	if (dp->tx_next == dp->tx_buf1) {
-		dp->tx1 = start_page;
-		dp->tx1_len = pkt_len;
-		dp->tx1_key = key;
-		dp->tx_next = dp->tx_buf2;
-	} else {
-		dp->tx2 = start_page;
-		dp->tx2_len = pkt_len;
-		dp->tx2_key = key;
-		dp->tx_next = dp->tx_buf1;
-	}
-
-#if DEBUG & 5
-	printf("TX prep page %d len %d\n", start_page, pkt_len);
-#endif
-
-	DP_OUT(base, DP_ISR, DP_ISR_RDC);	/* Clear end of DMA */
-	{
-		/*
-		 * Dummy read. The manual sez something slightly different,
-		 * but the code is extended a bit to do what Hitachi's monitor
-		 * does (i.e., also read data).
-		 */
-
-		u16 tmp;
-		int len = 1;
-
-		DP_OUT(base, DP_RSAL, 0x100 - len);
-		DP_OUT(base, DP_RSAH, (start_page - 1) & 0xff);
-		DP_OUT(base, DP_RBCL, len);
-		DP_OUT(base, DP_RBCH, 0);
-		DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_RDMA | DP_CR_START);
-		DP_IN_DATA(dp->data, tmp);
-	}
-
-#ifdef CYGHWR_NS_DP83902A_PLF_BROKEN_TX_DMA
-	/*
-	 * Stall for a bit before continuing to work around random data
-	 * corruption problems on some platforms.
-	 */
-	CYGACC_CALL_IF_DELAY_US(1);
-#endif
-
-	/* Send data to device buffer(s) */
-	DP_OUT(base, DP_RSAL, 0);
-	DP_OUT(base, DP_RSAH, start_page);
-	DP_OUT(base, DP_RBCL, pkt_len & 0xFF);
-	DP_OUT(base, DP_RBCH, pkt_len >> 8);
-	DP_OUT(base, DP_CR, DP_CR_WDMA | DP_CR_START);
-
-	/* Put data into buffer */
-#if DEBUG & 4
-	printf(" sg buf %08lx len %08x\n ", (u32)data, len);
-	dx = 0;
-#endif
-	while (len > 0) {
-#if DEBUG & 4
-		printf(" %02x", *data);
-		if (0 == (++dx % 16)) printf("\n ");
-#endif
-
-		DP_OUT_DATA(dp->data, *data++);
-		len--;
-	}
-#if DEBUG & 4
-	printf("\n");
-#endif
-	if (total_len < pkt_len) {
-#if DEBUG & 4
-		printf("  + %d bytes of padding\n", pkt_len - total_len);
-#endif
-		/* Padding to 802.3 length was required */
-		for (i = total_len; i < pkt_len;) {
-			i++;
-			DP_OUT_DATA(dp->data, 0);
-		}
-	}
-
-#ifdef CYGHWR_NS_DP83902A_PLF_BROKEN_TX_DMA
-	/*
-	 * After last data write, delay for a bit before accessing the
-	 * device again, or we may get random data corruption in the last
-	 * datum (on some platforms).
-	 */
-	CYGACC_CALL_IF_DELAY_US(1);
-#endif
-
-	/* Wait for DMA to complete */
-	do {
-		DP_IN(base, DP_ISR, isr);
-	} while ((isr & DP_ISR_RDC) == 0);
-
-	/* Then disable DMA */
-	DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START);
-
-	/* Start transmit if not already going */
-	if (!dp->tx_started) {
-		if (start_page == dp->tx1) {
-			dp->tx_int = 1; /* Expecting interrupt from BUF1 */
-		} else {
-			dp->tx_int = 2; /* Expecting interrupt from BUF2 */
-		}
-		dp83902a_start_xmit(start_page, pkt_len);
-	}
-}
-
-/*
- * This function is called when a packet has been received. It's job is
- * to prepare to unload the packet from the hardware. Once the length of
- * the packet is known, the upper layer of the driver can be told. When
- * the upper layer is ready to unload the packet, the internal function
- * 'dp83902a_recv' will be called to actually fetch it from the hardware.
- */
-static void
-dp83902a_RxEvent(void)
-{
-	struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic;
-	u8 *base = dp->base;
-	u8 rsr;
-	u8 rcv_hdr[4];
-	int i, len, pkt, cur;
-
-	DEBUG_FUNCTION();
-
-	DP_IN(base, DP_RSR, rsr);
-	while (true) {
-		/* Read incoming packet header */
-		DP_OUT(base, DP_CR, DP_CR_PAGE1 | DP_CR_NODMA | DP_CR_START);
-		DP_IN(base, DP_P1_CURP, cur);
-		DP_OUT(base, DP_P1_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START);
-		DP_IN(base, DP_BNDRY, pkt);
-
-		pkt += 1;
-		if (pkt == dp->rx_buf_end)
-			pkt = dp->rx_buf_start;
-
-		if (pkt == cur) {
-			break;
-		}
-		DP_OUT(base, DP_RBCL, sizeof(rcv_hdr));
-		DP_OUT(base, DP_RBCH, 0);
-		DP_OUT(base, DP_RSAL, 0);
-		DP_OUT(base, DP_RSAH, pkt);
-		if (dp->rx_next == pkt) {
-			if (cur == dp->rx_buf_start)
-				DP_OUT(base, DP_BNDRY, dp->rx_buf_end - 1);
-			else
-				DP_OUT(base, DP_BNDRY, cur - 1); /* Update pointer */
-			return;
-		}
-		dp->rx_next = pkt;
-		DP_OUT(base, DP_ISR, DP_ISR_RDC); /* Clear end of DMA */
-		DP_OUT(base, DP_CR, DP_CR_RDMA | DP_CR_START);
-#ifdef CYGHWR_NS_DP83902A_PLF_BROKEN_RX_DMA
-		CYGACC_CALL_IF_DELAY_US(10);
-#endif
-
-		/* read header (get data size)*/
-		for (i = 0; i < sizeof(rcv_hdr);) {
-			DP_IN_DATA(dp->data, rcv_hdr[i++]);
-		}
-
-#if DEBUG & 5
-		printf("rx hdr %02x %02x %02x %02x\n",
-			rcv_hdr[0], rcv_hdr[1], rcv_hdr[2], rcv_hdr[3]);
-#endif
-		len = ((rcv_hdr[3] << 8) | rcv_hdr[2]) - sizeof(rcv_hdr);
-
-		/* data read */
-		uboot_push_packet_len(len);
-
-		if (rcv_hdr[1] == dp->rx_buf_start)
-			DP_OUT(base, DP_BNDRY, dp->rx_buf_end - 1);
-		else
-			DP_OUT(base, DP_BNDRY, rcv_hdr[1] - 1); /* Update pointer */
-	}
-}
-
-/*
- * This function is called as a result of the "eth_drv_recv()" call above.
- * It's job is to actually fetch data for a packet from the hardware once
- * memory buffers have been allocated for the packet. Note that the buffers
- * may come in pieces, using a scatter-gather list. This allows for more
- * efficient processing in the upper layers of the stack.
- */
-static void
-dp83902a_recv(u8 *data, int len)
-{
-	struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic;
-	u8 *base = dp->base;
-	int i, mlen;
-	u8 saved_char = 0;
-	bool saved;
-#if DEBUG & 4
-	int dx;
-#endif
-
-	DEBUG_FUNCTION();
-
-#if DEBUG & 5
-	printf("Rx packet %d length %d\n", dp->rx_next, len);
-#endif
-
-	/* Read incoming packet data */
-	DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START);
-	DP_OUT(base, DP_RBCL, len & 0xFF);
-	DP_OUT(base, DP_RBCH, len >> 8);
-	DP_OUT(base, DP_RSAL, 4);		/* Past header */
-	DP_OUT(base, DP_RSAH, dp->rx_next);
-	DP_OUT(base, DP_ISR, DP_ISR_RDC); /* Clear end of DMA */
-	DP_OUT(base, DP_CR, DP_CR_RDMA | DP_CR_START);
-#ifdef CYGHWR_NS_DP83902A_PLF_BROKEN_RX_DMA
-	CYGACC_CALL_IF_DELAY_US(10);
-#endif
-
-	saved = false;
-	for (i = 0; i < 1; i++) {
-		if (data) {
-			mlen = len;
-#if DEBUG & 4
-			printf(" sg buf %08lx len %08x \n", (u32) data, mlen);
-			dx = 0;
-#endif
-			while (0 < mlen) {
-				/* Saved byte from previous loop? */
-				if (saved) {
-					*data++ = saved_char;
-					mlen--;
-					saved = false;
-					continue;
-				}
-
-				{
-					u8 tmp;
-					DP_IN_DATA(dp->data, tmp);
-#if DEBUG & 4
-					printf(" %02x", tmp);
-					if (0 == (++dx % 16)) printf("\n ");
-#endif
-					*data++ = tmp;;
-					mlen--;
-				}
-			}
-#if DEBUG & 4
-			printf("\n");
-#endif
-		}
-	}
-}
-
-static void
-dp83902a_TxEvent(void)
-{
-	struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic;
-	u8 *base = dp->base;
-	u8 tsr;
-	u32 key;
-
-	DEBUG_FUNCTION();
-
-	DP_IN(base, DP_TSR, tsr);
-	if (dp->tx_int == 1) {
-		key = dp->tx1_key;
-		dp->tx1 = 0;
-	} else {
-		key = dp->tx2_key;
-		dp->tx2 = 0;
-	}
-	/* Start next packet if one is ready */
-	dp->tx_started = false;
-	if (dp->tx1) {
-		dp83902a_start_xmit(dp->tx1, dp->tx1_len);
-		dp->tx_int = 1;
-	} else if (dp->tx2) {
-		dp83902a_start_xmit(dp->tx2, dp->tx2_len);
-		dp->tx_int = 2;
-	} else {
-		dp->tx_int = 0;
-	}
-	/* Tell higher level we sent this packet */
-	uboot_push_tx_done(key, 0);
-}
-
-/*
- * Read the tally counters to clear them. Called in response to a CNT
- * interrupt.
- */
-static void
-dp83902a_ClearCounters(void)
-{
-	struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic;
-	u8 *base = dp->base;
-	u8 cnt1, cnt2, cnt3;
-
-	DP_IN(base, DP_FER, cnt1);
-	DP_IN(base, DP_CER, cnt2);
-	DP_IN(base, DP_MISSED, cnt3);
-	DP_OUT(base, DP_ISR, DP_ISR_CNT);
-}
-
-/*
- * Deal with an overflow condition. This code follows the procedure set
- * out in section 7.0 of the datasheet.
- */
-static void
-dp83902a_Overflow(void)
-{
-	struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *)&nic;
-	u8 *base = dp->base;
-	u8 isr;
-
-	/* Issue a stop command and wait 1.6ms for it to complete. */
-	DP_OUT(base, DP_CR, DP_CR_STOP | DP_CR_NODMA);
-	CYGACC_CALL_IF_DELAY_US(1600);
-
-	/* Clear the remote byte counter registers. */
-	DP_OUT(base, DP_RBCL, 0);
-	DP_OUT(base, DP_RBCH, 0);
-
-	/* Enter loopback mode while we clear the buffer. */
-	DP_OUT(base, DP_TCR, DP_TCR_LOCAL);
-	DP_OUT(base, DP_CR, DP_CR_START | DP_CR_NODMA);
-
-	/*
-	 * Read in as many packets as we can and acknowledge any and receive
-	 * interrupts. Since the buffer has overflowed, a receive event of
-	 * some kind will have occured.
-	 */
-	dp83902a_RxEvent();
-	DP_OUT(base, DP_ISR, DP_ISR_RxP|DP_ISR_RxE);
-
-	/* Clear the overflow condition and leave loopback mode. */
-	DP_OUT(base, DP_ISR, DP_ISR_OFLW);
-	DP_OUT(base, DP_TCR, DP_TCR_NORMAL);
-
-	/*
-	 * If a transmit command was issued, but no transmit event has occured,
-	 * restart it here.
-	 */
-	DP_IN(base, DP_ISR, isr);
-	if (dp->tx_started && !(isr & (DP_ISR_TxP|DP_ISR_TxE))) {
-		DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_TXPKT | DP_CR_START);
-	}
-}
-
-static void
-dp83902a_poll(void)
-{
-	struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic;
-	u8 *base = dp->base;
-	u8 isr;
-
-	DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE0 | DP_CR_START);
-	DP_IN(base, DP_ISR, isr);
-	while (0 != isr) {
-		/*
-		 * The CNT interrupt triggers when the MSB of one of the error
-		 * counters is set. We don't much care about these counters, but
-		 * we should read their values to reset them.
-		 */
-		if (isr & DP_ISR_CNT) {
-			dp83902a_ClearCounters();
-		}
-		/*
-		 * Check for overflow. It's a special case, since there's a
-		 * particular procedure that must be followed to get back into
-		 * a running state.a
-		 */
-		if (isr & DP_ISR_OFLW) {
-			dp83902a_Overflow();
-		} else {
-			/*
-			 * Other kinds of interrupts can be acknowledged simply by
-			 * clearing the relevant bits of the ISR. Do that now, then
-			 * handle the interrupts we care about.
-			 */
-			DP_OUT(base, DP_ISR, isr);	/* Clear set bits */
-			if (!dp->running) break;	/* Is this necessary? */
-			/*
-			 * Check for tx_started on TX event since these may happen
-			 * spuriously it seems.
-			 */
-			if (isr & (DP_ISR_TxP|DP_ISR_TxE) && dp->tx_started) {
-				dp83902a_TxEvent();
-			}
-			if (isr & (DP_ISR_RxP|DP_ISR_RxE)) {
-				dp83902a_RxEvent();
-			}
-		}
-		DP_IN(base, DP_ISR, isr);
-	}
-}
-
+#define mdelay(n) udelay((n)*1000)
 /* find prom (taken from pc_net_cs.c from Linux) */
 
 #include "8390.h"
@@ -763,18 +174,16 @@ static hw_info_t hw_info[] = {
 #define PCNET_RESET	0x1f	/* Issue a read to reset, a write to clear. */
 #define PCNET_MISC	0x18	/* For IBM CCAE and Socket EA cards */
 
-static void pcnet_reset_8390(void)
+static void pcnet_reset_8390(u8* addr)
 {
 	int i, r;
 
-	PRINTK("nic base is %lx\n", nic.base);
-
 	n2k_outb(E8390_NODMA + E8390_PAGE0+E8390_STOP, E8390_CMD);
-	PRINTK("cmd (at %lx) is %x\n", nic.base + E8390_CMD, n2k_inb(E8390_CMD));
+	PRINTK("cmd (at %lx) is %x\n", addr + E8390_CMD, n2k_inb(E8390_CMD));
 	n2k_outb(E8390_NODMA+E8390_PAGE1+E8390_STOP, E8390_CMD);
-	PRINTK("cmd (at %lx) is %x\n", nic.base + E8390_CMD, n2k_inb(E8390_CMD));
+	PRINTK("cmd (at %lx) is %x\n", addr + E8390_CMD, n2k_inb(E8390_CMD));
 	n2k_outb(E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD);
-	PRINTK("cmd (at %lx) is %x\n", nic.base + E8390_CMD, n2k_inb(E8390_CMD));
+	PRINTK("cmd (at %lx) is %x\n", addr + E8390_CMD, n2k_inb(E8390_CMD));
 	n2k_outb(E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD);
 
 	n2k_outb(n2k_inb(PCNET_RESET), PCNET_RESET);
@@ -791,8 +200,7 @@ static void pcnet_reset_8390(void)
 		printf("pcnet_reset_8390() did not complete.\n");
 } /* pcnet_reset_8390 */
 
-int get_prom(u8* mac_addr) __attribute__ ((weak, alias ("__get_prom")));
-int __get_prom(u8* mac_addr)
+int get_prom(u8* mac_addr, u8* base_addr)
 {
 	u8 prom[32];
 	int i, j;
@@ -816,7 +224,7 @@ int __get_prom(u8* mac_addr)
 
 	PRINTK ("trying to get MAC via prom reading\n");
 
-	pcnet_reset_8390 ();
+	pcnet_reset_8390 (base_addr);
 
 	mdelay (10);
 
@@ -849,116 +257,3 @@ int __get_prom(u8* mac_addr)
 	}
 	return 0;
 }
-
-/* U-boot specific routines */
-static u8 *pbuf = NULL;
-
-static int pkey = -1;
-static int initialized = 0;
-
-void uboot_push_packet_len(int len) {
-	PRINTK("pushed len = %d\n", len);
-	if (len >= 2000) {
-		printf("NE2000: packet too big\n");
-		return;
-	}
-	dp83902a_recv(&pbuf[0], len);
-
-	/*Just pass it to the upper layer*/
-	NetReceive(&pbuf[0], len);
-}
-
-void uboot_push_tx_done(int key, int val) {
-	PRINTK("pushed key = %d\n", key);
-	pkey = key;
-}
-
-int eth_init(bd_t *bd) {
-	int r;
-	u8 dev_addr[6];
-	char ethaddr[20];
-
-	PRINTK("### eth_init\n");
-
-	if (!pbuf) {
-		pbuf = malloc(2000);
-		if (!pbuf) {
-			printf("Cannot allocate rx buffer\n");
-			return -1;
-		}
-	}
-
-#ifdef CONFIG_DRIVER_NE2000_CCR
-	{
-		vu_char *p = (vu_char *) CONFIG_DRIVER_NE2000_CCR;
-
-		PRINTK("CCR before is %x\n", *p);
-		*p = CONFIG_DRIVER_NE2000_VAL;
-		PRINTK("CCR after is %x\n", *p);
-	}
-#endif
-
-	nic.base = (u8 *) CONFIG_DRIVER_NE2000_BASE;
-
-	r = get_prom(dev_addr);
-	if (!r)
-		return -1;
-
-	sprintf (ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X",
-		 dev_addr[0], dev_addr[1],
-		 dev_addr[2], dev_addr[3],
-		 dev_addr[4], dev_addr[5]) ;
-	PRINTK("Set environment from HW MAC addr = \"%s\"\n", ethaddr);
-	setenv ("ethaddr", ethaddr);
-
-	nic.data = nic.base + DP_DATA;
-	nic.tx_buf1 = START_PG;
-	nic.tx_buf2 = START_PG2;
-	nic.rx_buf_start = RX_START;
-	nic.rx_buf_end = RX_END;
-
-	if (dp83902a_init() == false)
-		return -1;
-
-	dp83902a_start(dev_addr);
-	initialized = 1;
-
-	return 0;
-}
-
-void eth_halt() {
-
-	PRINTK("### eth_halt\n");
-	if(initialized)
-		dp83902a_stop();
-	initialized = 0;
-}
-
-int eth_rx() {
-	dp83902a_poll();
-	return 1;
-}
-
-int eth_send(volatile void *packet, int length) {
-	int tmo;
-
-	PRINTK("### eth_send\n");
-
-	pkey = -1;
-
-	dp83902a_send((u8 *) packet, length, 666);
-	tmo = get_timer (0) + TOUT * CFG_HZ;
-	while(1) {
-		dp83902a_poll();
-		if (pkey != -1) {
-			PRINTK("Packet sucesfully sent\n");
-			return 0;
-		}
-		if (get_timer (0) >= tmo) {
-			printf("transmission error (timoeut)\n");
-			return 0;
-		}
-
-	}
-	return 0;
-}

drivers/net/ne2000_base.c

@@ -0,0 +1,757 @@
+/*
+Ported to U-Boot by Christian Pellegrin <chri@ascensit.com>
+
+Based on sources from the Linux kernel (pcnet_cs.c, 8390.h) and
+eCOS(if_dp83902a.c, if_dp83902a.h). Both of these 2 wonderful world
+are GPL, so this is, of course, GPL.
+
+==========================================================================
+
+dev/if_dp83902a.c
+
+Ethernet device driver for NS DP83902a ethernet controller
+
+==========================================================================
+####ECOSGPLCOPYRIGHTBEGIN####
+-------------------------------------------
+This file is part of eCos, the Embedded Configurable Operating System.
+Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+
+eCos is free software; you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free
+Software Foundation; either version 2 or (at your option) any later version.
+
+eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or
+FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+for more details.
+
+You should have received a copy of the GNU General Public License along
+with eCos; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+
+As a special exception, if other files instantiate templates or use macros
+or inline functions from this file, or you compile this file and link it
+with other works to produce a work based on this file, this file does not
+by itself cause the resulting work to be covered by the GNU General Public
+License. However the source code for this file must still be made available
+in accordance with section (3) of the GNU General Public License.
+
+This exception does not invalidate any other reasons why a work based on
+this file might be covered by the GNU General Public License.
+
+Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+at http://sources.redhat.com/ecos/ecos-license/
+-------------------------------------------
+####ECOSGPLCOPYRIGHTEND####
+####BSDCOPYRIGHTBEGIN####
+
+-------------------------------------------
+
+Portions of this software may have been derived from OpenBSD or other sources,
+and are covered by the appropriate copyright disclaimers included herein.
+
+-------------------------------------------
+
+####BSDCOPYRIGHTEND####
+==========================================================================
+#####DESCRIPTIONBEGIN####
+
+Author(s):	gthomas
+Contributors:	gthomas, jskov, rsandifo
+Date:		2001-06-13
+Purpose:
+Description:
+
+FIXME:		Will fail if pinged with large packets (1520 bytes)
+Add promisc config
+Add SNMP
+
+####DESCRIPTIONEND####
+
+==========================================================================
+*/
+
+#include <common.h>
+#include <command.h>
+#include <net.h>
+#include <malloc.h>
+
+#define mdelay(n)	udelay((n)*1000)
+/* forward definition of function used for the uboot interface */
+void uboot_push_packet_len(int len);
+void uboot_push_tx_done(int key, int val);
+
+/* NE2000 base header file */
+#include "ne2000_base.h"
+
+#if defined(CONFIG_DRIVER_AX88796L)
+/* AX88796L support */
+#include "ax88796.h"
+#else
+/* Basic NE2000 chip support */
+#include "ne2000.h"
+#endif
+
+static dp83902a_priv_data_t nic; /* just one instance of the card supported */
+
+static bool
+dp83902a_init(void)
+{
+	dp83902a_priv_data_t *dp = &nic;
+	u8* base;
+#if defined(NE2000_BASIC_INIT)
+	int i;
+#endif
+
+	DEBUG_FUNCTION();
+
+	base = dp->base;
+	if (!base)
+		return false;	/* No device found */
+
+	DEBUG_LINE();
+
+#if defined(NE2000_BASIC_INIT)
+	/* AX88796L doesn't need */
+	/* Prepare ESA */
+	DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE1);	/* Select page 1 */
+	/* Use the address from the serial EEPROM */
+	for (i = 0; i < 6; i++)
+		DP_IN(base, DP_P1_PAR0+i, dp->esa[i]);
+	DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE0);	/* Select page 0 */
+
+	printf("NE2000 - %s ESA: %02x:%02x:%02x:%02x:%02x:%02x\n",
+		"eeprom",
+		dp->esa[0],
+		dp->esa[1],
+		dp->esa[2],
+		dp->esa[3],
+		dp->esa[4],
+		dp->esa[5] );
+
+#endif	/* NE2000_BASIC_INIT */
+	return true;
+}
+
+static void
+dp83902a_stop(void)
+{
+	dp83902a_priv_data_t *dp = &nic;
+	u8 *base = dp->base;
+
+	DEBUG_FUNCTION();
+
+	DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_STOP);	/* Brutal */
+	DP_OUT(base, DP_ISR, 0xFF);		/* Clear any pending interrupts */
+	DP_OUT(base, DP_IMR, 0x00);		/* Disable all interrupts */
+
+	dp->running = false;
+}
+
+/*
+ * This function is called to "start up" the interface. It may be called
+ * multiple times, even when the hardware is already running. It will be
+ * called whenever something "hardware oriented" changes and should leave
+ * the hardware ready to send/receive packets.
+ */
+static void
+dp83902a_start(u8 * enaddr)
+{
+	dp83902a_priv_data_t *dp = &nic;
+	u8 *base = dp->base;
+	int i;
+
+	DEBUG_FUNCTION();
+
+	DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_STOP); /* Brutal */
+	DP_OUT(base, DP_DCR, DP_DCR_INIT);
+	DP_OUT(base, DP_RBCH, 0);		/* Remote byte count */
+	DP_OUT(base, DP_RBCL, 0);
+	DP_OUT(base, DP_RCR, DP_RCR_MON);	/* Accept no packets */
+	DP_OUT(base, DP_TCR, DP_TCR_LOCAL);	/* Transmitter [virtually] off */
+	DP_OUT(base, DP_TPSR, dp->tx_buf1);	/* Transmitter start page */
+	dp->tx1 = dp->tx2 = 0;
+	dp->tx_next = dp->tx_buf1;
+	dp->tx_started = false;
+	dp->running = true;
+	DP_OUT(base, DP_PSTART, dp->rx_buf_start); /* Receive ring start page */
+	DP_OUT(base, DP_BNDRY, dp->rx_buf_end - 1); /* Receive ring boundary */
+	DP_OUT(base, DP_PSTOP, dp->rx_buf_end);	/* Receive ring end page */
+	dp->rx_next = dp->rx_buf_start - 1;
+	dp->running = true;
+	DP_OUT(base, DP_ISR, 0xFF);		/* Clear any pending interrupts */
+	DP_OUT(base, DP_IMR, DP_IMR_All);	/* Enable all interrupts */
+	DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE1 | DP_CR_STOP);	/* Select page 1 */
+	DP_OUT(base, DP_P1_CURP, dp->rx_buf_start);	/* Current page - next free page for Rx */
+	dp->running = true;
+	for (i = 0; i < ETHER_ADDR_LEN; i++) {
+		/* FIXME */
+		/*((vu_short*)( base + ((DP_P1_PAR0 + i) * 2) +
+		 * 0x1400)) = enaddr[i];*/
+		DP_OUT(base, DP_P1_PAR0+i, enaddr[i]);
+	}
+	/* Enable and start device */
+	DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START);
+	DP_OUT(base, DP_TCR, DP_TCR_NORMAL); /* Normal transmit operations */
+	DP_OUT(base, DP_RCR, DP_RCR_AB); /* Accept broadcast, no errors, no multicast */
+	dp->running = true;
+}
+
+/*
+ * This routine is called to start the transmitter. It is split out from the
+ * data handling routine so it may be called either when data becomes first
+ * available or when an Tx interrupt occurs
+ */
+
+static void
+dp83902a_start_xmit(int start_page, int len)
+{
+	dp83902a_priv_data_t *dp = (dp83902a_priv_data_t *) &nic;
+	u8 *base = dp->base;
+
+	DEBUG_FUNCTION();
+
+#if DEBUG & 1
+	printf("Tx pkt %d len %d\n", start_page, len);
+	if (dp->tx_started)
+		printf("TX already started?!?\n");
+#endif
+
+	DP_OUT(base, DP_ISR, (DP_ISR_TxP | DP_ISR_TxE));
+	DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START);
+	DP_OUT(base, DP_TBCL, len & 0xFF);
+	DP_OUT(base, DP_TBCH, len >> 8);
+	DP_OUT(base, DP_TPSR, start_page);
+	DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_TXPKT | DP_CR_START);
+
+	dp->tx_started = true;
+}
+
+/*
+ * This routine is called to send data to the hardware. It is known a-priori
+ * that there is free buffer space (dp->tx_next).
+ */
+static void
+dp83902a_send(u8 *data, int total_len, u32 key)
+{
+	struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic;
+	u8 *base = dp->base;
+	int len, start_page, pkt_len, i, isr;
+#if DEBUG & 4
+	int dx;
+#endif
+
+	DEBUG_FUNCTION();
+
+	len = pkt_len = total_len;
+	if (pkt_len < IEEE_8023_MIN_FRAME)
+		pkt_len = IEEE_8023_MIN_FRAME;
+
+	start_page = dp->tx_next;
+	if (dp->tx_next == dp->tx_buf1) {
+		dp->tx1 = start_page;
+		dp->tx1_len = pkt_len;
+		dp->tx1_key = key;
+		dp->tx_next = dp->tx_buf2;
+	} else {
+		dp->tx2 = start_page;
+		dp->tx2_len = pkt_len;
+		dp->tx2_key = key;
+		dp->tx_next = dp->tx_buf1;
+	}
+
+#if DEBUG & 5
+	printf("TX prep page %d len %d\n", start_page, pkt_len);
+#endif
+
+	DP_OUT(base, DP_ISR, DP_ISR_RDC);	/* Clear end of DMA */
+	{
+		/*
+		 * Dummy read. The manual sez something slightly different,
+		 * but the code is extended a bit to do what Hitachi's monitor
+		 * does (i.e., also read data).
+		 */
+
+		u16 tmp;
+		int len = 1;
+
+		DP_OUT(base, DP_RSAL, 0x100 - len);
+		DP_OUT(base, DP_RSAH, (start_page - 1) & 0xff);
+		DP_OUT(base, DP_RBCL, len);
+		DP_OUT(base, DP_RBCH, 0);
+		DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_RDMA | DP_CR_START);
+		DP_IN_DATA(dp->data, tmp);
+	}
+
+#ifdef CYGHWR_NS_DP83902A_PLF_BROKEN_TX_DMA
+	/*
+	 * Stall for a bit before continuing to work around random data
+	 * corruption problems on some platforms.
+	 */
+	CYGACC_CALL_IF_DELAY_US(1);
+#endif
+
+	/* Send data to device buffer(s) */
+	DP_OUT(base, DP_RSAL, 0);
+	DP_OUT(base, DP_RSAH, start_page);
+	DP_OUT(base, DP_RBCL, pkt_len & 0xFF);
+	DP_OUT(base, DP_RBCH, pkt_len >> 8);
+	DP_OUT(base, DP_CR, DP_CR_WDMA | DP_CR_START);
+
+	/* Put data into buffer */
+#if DEBUG & 4
+	printf(" sg buf %08lx len %08x\n ", (u32)data, len);
+	dx = 0;
+#endif
+	while (len > 0) {
+#if DEBUG & 4
+		printf(" %02x", *data);
+		if (0 == (++dx % 16)) printf("\n ");
+#endif
+
+		DP_OUT_DATA(dp->data, *data++);
+		len--;
+	}
+#if DEBUG & 4
+	printf("\n");
+#endif
+	if (total_len < pkt_len) {
+#if DEBUG & 4
+		printf("  + %d bytes of padding\n", pkt_len - total_len);
+#endif
+		/* Padding to 802.3 length was required */
+		for (i = total_len; i < pkt_len;) {
+			i++;
+			DP_OUT_DATA(dp->data, 0);
+		}
+	}
+
+#ifdef CYGHWR_NS_DP83902A_PLF_BROKEN_TX_DMA
+	/*
+	 * After last data write, delay for a bit before accessing the
+	 * device again, or we may get random data corruption in the last
+	 * datum (on some platforms).
+	 */
+	CYGACC_CALL_IF_DELAY_US(1);
+#endif
+
+	/* Wait for DMA to complete */
+	do {
+		DP_IN(base, DP_ISR, isr);
+	} while ((isr & DP_ISR_RDC) == 0);
+
+	/* Then disable DMA */
+	DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START);
+
+	/* Start transmit if not already going */
+	if (!dp->tx_started) {
+		if (start_page == dp->tx1) {
+			dp->tx_int = 1; /* Expecting interrupt from BUF1 */
+		} else {
+			dp->tx_int = 2; /* Expecting interrupt from BUF2 */
+		}
+		dp83902a_start_xmit(start_page, pkt_len);
+	}
+}
+
+/*
+ * This function is called when a packet has been received. It's job is
+ * to prepare to unload the packet from the hardware. Once the length of
+ * the packet is known, the upper layer of the driver can be told. When
+ * the upper layer is ready to unload the packet, the internal function
+ * 'dp83902a_recv' will be called to actually fetch it from the hardware.
+ */
+static void
+dp83902a_RxEvent(void)
+{
+	struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic;
+	u8 *base = dp->base;
+	u8 rsr;
+	u8 rcv_hdr[4];
+	int i, len, pkt, cur;
+
+	DEBUG_FUNCTION();
+
+	DP_IN(base, DP_RSR, rsr);
+	while (true) {
+		/* Read incoming packet header */
+		DP_OUT(base, DP_CR, DP_CR_PAGE1 | DP_CR_NODMA | DP_CR_START);
+		DP_IN(base, DP_P1_CURP, cur);
+		DP_OUT(base, DP_P1_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START);
+		DP_IN(base, DP_BNDRY, pkt);
+
+		pkt += 1;
+		if (pkt == dp->rx_buf_end)
+			pkt = dp->rx_buf_start;
+
+		if (pkt == cur) {
+			break;
+		}
+		DP_OUT(base, DP_RBCL, sizeof(rcv_hdr));
+		DP_OUT(base, DP_RBCH, 0);
+		DP_OUT(base, DP_RSAL, 0);
+		DP_OUT(base, DP_RSAH, pkt);
+		if (dp->rx_next == pkt) {
+			if (cur == dp->rx_buf_start)
+				DP_OUT(base, DP_BNDRY, dp->rx_buf_end - 1);
+			else
+				DP_OUT(base, DP_BNDRY, cur - 1); /* Update pointer */
+			return;
+		}
+		dp->rx_next = pkt;
+		DP_OUT(base, DP_ISR, DP_ISR_RDC); /* Clear end of DMA */
+		DP_OUT(base, DP_CR, DP_CR_RDMA | DP_CR_START);
+#ifdef CYGHWR_NS_DP83902A_PLF_BROKEN_RX_DMA
+		CYGACC_CALL_IF_DELAY_US(10);
+#endif
+
+		/* read header (get data size)*/
+		for (i = 0; i < sizeof(rcv_hdr);) {
+			DP_IN_DATA(dp->data, rcv_hdr[i++]);
+		}
+
+#if DEBUG & 5
+		printf("rx hdr %02x %02x %02x %02x\n",
+			rcv_hdr[0], rcv_hdr[1], rcv_hdr[2], rcv_hdr[3]);
+#endif
+		len = ((rcv_hdr[3] << 8) | rcv_hdr[2]) - sizeof(rcv_hdr);
+
+		/* data read */
+		uboot_push_packet_len(len);
+
+		if (rcv_hdr[1] == dp->rx_buf_start)
+			DP_OUT(base, DP_BNDRY, dp->rx_buf_end - 1);
+		else
+			DP_OUT(base, DP_BNDRY, rcv_hdr[1] - 1); /* Update pointer */
+	}
+}
+
+/*
+ * This function is called as a result of the "eth_drv_recv()" call above.
+ * It's job is to actually fetch data for a packet from the hardware once
+ * memory buffers have been allocated for the packet. Note that the buffers
+ * may come in pieces, using a scatter-gather list. This allows for more
+ * efficient processing in the upper layers of the stack.
+ */
+static void
+dp83902a_recv(u8 *data, int len)
+{
+	struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic;
+	u8 *base = dp->base;
+	int i, mlen;
+	u8 saved_char = 0;
+	bool saved;
+#if DEBUG & 4
+	int dx;
+#endif
+
+	DEBUG_FUNCTION();
+
+#if DEBUG & 5
+	printf("Rx packet %d length %d\n", dp->rx_next, len);
+#endif
+
+	/* Read incoming packet data */
+	DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START);
+	DP_OUT(base, DP_RBCL, len & 0xFF);
+	DP_OUT(base, DP_RBCH, len >> 8);
+	DP_OUT(base, DP_RSAL, 4);		/* Past header */
+	DP_OUT(base, DP_RSAH, dp->rx_next);
+	DP_OUT(base, DP_ISR, DP_ISR_RDC); /* Clear end of DMA */
+	DP_OUT(base, DP_CR, DP_CR_RDMA | DP_CR_START);
+#ifdef CYGHWR_NS_DP83902A_PLF_BROKEN_RX_DMA
+	CYGACC_CALL_IF_DELAY_US(10);
+#endif
+
+	saved = false;
+	for (i = 0; i < 1; i++) {
+		if (data) {
+			mlen = len;
+#if DEBUG & 4
+			printf(" sg buf %08lx len %08x \n", (u32) data, mlen);
+			dx = 0;
+#endif
+			while (0 < mlen) {
+				/* Saved byte from previous loop? */
+				if (saved) {
+					*data++ = saved_char;
+					mlen--;
+					saved = false;
+					continue;
+				}
+
+				{
+					u8 tmp;
+					DP_IN_DATA(dp->data, tmp);
+#if DEBUG & 4
+					printf(" %02x", tmp);
+					if (0 == (++dx % 16)) printf("\n ");
+#endif
+					*data++ = tmp;;
+					mlen--;
+				}
+			}
+#if DEBUG & 4
+			printf("\n");
+#endif
+		}
+	}
+}
+
+static void
+dp83902a_TxEvent(void)
+{
+	struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic;
+	u8 *base = dp->base;
+	u8 tsr;
+	u32 key;
+
+	DEBUG_FUNCTION();
+
+	DP_IN(base, DP_TSR, tsr);
+	if (dp->tx_int == 1) {
+		key = dp->tx1_key;
+		dp->tx1 = 0;
+	} else {
+		key = dp->tx2_key;
+		dp->tx2 = 0;
+	}
+	/* Start next packet if one is ready */
+	dp->tx_started = false;
+	if (dp->tx1) {
+		dp83902a_start_xmit(dp->tx1, dp->tx1_len);
+		dp->tx_int = 1;
+	} else if (dp->tx2) {
+		dp83902a_start_xmit(dp->tx2, dp->tx2_len);
+		dp->tx_int = 2;
+	} else {
+		dp->tx_int = 0;
+	}
+	/* Tell higher level we sent this packet */
+	uboot_push_tx_done(key, 0);
+}
+
+/*
+ * Read the tally counters to clear them. Called in response to a CNT
+ * interrupt.
+ */
+static void
+dp83902a_ClearCounters(void)
+{
+	struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic;
+	u8 *base = dp->base;
+	u8 cnt1, cnt2, cnt3;
+
+	DP_IN(base, DP_FER, cnt1);
+	DP_IN(base, DP_CER, cnt2);
+	DP_IN(base, DP_MISSED, cnt3);
+	DP_OUT(base, DP_ISR, DP_ISR_CNT);
+}
+
+/*
+ * Deal with an overflow condition. This code follows the procedure set
+ * out in section 7.0 of the datasheet.
+ */
+static void
+dp83902a_Overflow(void)
+{
+	struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *)&nic;
+	u8 *base = dp->base;
+	u8 isr;
+
+	/* Issue a stop command and wait 1.6ms for it to complete. */
+	DP_OUT(base, DP_CR, DP_CR_STOP | DP_CR_NODMA);
+	CYGACC_CALL_IF_DELAY_US(1600);
+
+	/* Clear the remote byte counter registers. */
+	DP_OUT(base, DP_RBCL, 0);
+	DP_OUT(base, DP_RBCH, 0);
+
+	/* Enter loopback mode while we clear the buffer. */
+	DP_OUT(base, DP_TCR, DP_TCR_LOCAL);
+	DP_OUT(base, DP_CR, DP_CR_START | DP_CR_NODMA);
+
+	/*
+	 * Read in as many packets as we can and acknowledge any and receive
+	 * interrupts. Since the buffer has overflowed, a receive event of
+	 * some kind will have occured.
+	 */
+	dp83902a_RxEvent();
+	DP_OUT(base, DP_ISR, DP_ISR_RxP|DP_ISR_RxE);
+
+	/* Clear the overflow condition and leave loopback mode. */
+	DP_OUT(base, DP_ISR, DP_ISR_OFLW);
+	DP_OUT(base, DP_TCR, DP_TCR_NORMAL);
+
+	/*
+	 * If a transmit command was issued, but no transmit event has occured,
+	 * restart it here.
+	 */
+	DP_IN(base, DP_ISR, isr);
+	if (dp->tx_started && !(isr & (DP_ISR_TxP|DP_ISR_TxE))) {
+		DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_TXPKT | DP_CR_START);
+	}
+}
+
+static void
+dp83902a_poll(void)
+{
+	struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic;
+	u8 *base = dp->base;
+	u8 isr;
+
+	DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE0 | DP_CR_START);
+	DP_IN(base, DP_ISR, isr);
+	while (0 != isr) {
+		/*
+		 * The CNT interrupt triggers when the MSB of one of the error
+		 * counters is set. We don't much care about these counters, but
+		 * we should read their values to reset them.
+		 */
+		if (isr & DP_ISR_CNT) {
+			dp83902a_ClearCounters();
+		}
+		/*
+		 * Check for overflow. It's a special case, since there's a
+		 * particular procedure that must be followed to get back into
+		 * a running state.a
+		 */
+		if (isr & DP_ISR_OFLW) {
+			dp83902a_Overflow();
+		} else {
+			/*
+			 * Other kinds of interrupts can be acknowledged simply by
+			 * clearing the relevant bits of the ISR. Do that now, then
+			 * handle the interrupts we care about.
+			 */
+			DP_OUT(base, DP_ISR, isr);	/* Clear set bits */
+			if (!dp->running) break;	/* Is this necessary? */
+			/*
+			 * Check for tx_started on TX event since these may happen
+			 * spuriously it seems.
+			 */
+			if (isr & (DP_ISR_TxP|DP_ISR_TxE) && dp->tx_started) {
+				dp83902a_TxEvent();
+			}
+			if (isr & (DP_ISR_RxP|DP_ISR_RxE)) {
+				dp83902a_RxEvent();
+			}
+		}
+		DP_IN(base, DP_ISR, isr);
+	}
+}
+
+
+/* U-boot specific routines */
+static u8 *pbuf = NULL;
+
+static int pkey = -1;
+static int initialized = 0;
+
+void uboot_push_packet_len(int len) {
+	PRINTK("pushed len = %d\n", len);
+	if (len >= 2000) {
+		printf("NE2000: packet too big\n");
+		return;
+	}
+	dp83902a_recv(&pbuf[0], len);
+
+	/*Just pass it to the upper layer*/
+	NetReceive(&pbuf[0], len);
+}
+
+void uboot_push_tx_done(int key, int val) {
+	PRINTK("pushed key = %d\n", key);
+	pkey = key;
+}
+
+int eth_init(bd_t *bd) {
+	int r;
+	u8 dev_addr[6];
+	char ethaddr[20];
+
+	PRINTK("### eth_init\n");
+
+	if (!pbuf) {
+		pbuf = malloc(2000);
+		if (!pbuf) {
+			printf("Cannot allocate rx buffer\n");
+			return -1;
+		}
+	}
+
+#ifdef CONFIG_DRIVER_NE2000_CCR
+	{
+		vu_char *p = (vu_char *) CONFIG_DRIVER_NE2000_CCR;
+
+		PRINTK("CCR before is %x\n", *p);
+		*p = CONFIG_DRIVER_NE2000_VAL;
+		PRINTK("CCR after is %x\n", *p);
+	}
+#endif
+
+	nic.base = (u8 *) CONFIG_DRIVER_NE2000_BASE;
+
+	r = get_prom(dev_addr, nic.base);
+	if (!r)
+		return -1;
+
+	sprintf (ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X",
+		 dev_addr[0], dev_addr[1],
+		 dev_addr[2], dev_addr[3],
+		 dev_addr[4], dev_addr[5]) ;
+	PRINTK("Set environment from HW MAC addr = \"%s\"\n", ethaddr);
+	setenv ("ethaddr", ethaddr);
+
+	nic.data = nic.base + DP_DATA;
+	nic.tx_buf1 = START_PG;
+	nic.tx_buf2 = START_PG2;
+	nic.rx_buf_start = RX_START;
+	nic.rx_buf_end = RX_END;
+
+	if (dp83902a_init() == false)
+		return -1;
+
+	dp83902a_start(dev_addr);
+	initialized = 1;
+
+	return 0;
+}
+
+void eth_halt() {
+
+	PRINTK("### eth_halt\n");
+	if(initialized)
+		dp83902a_stop();
+	initialized = 0;
+}
+
+int eth_rx() {
+	dp83902a_poll();
+	return 1;
+}
+
+int eth_send(volatile void *packet, int length) {
+	int tmo;
+
+	PRINTK("### eth_send\n");
+
+	pkey = -1;
+
+	dp83902a_send((u8 *) packet, length, 666);
+	tmo = get_timer (0) + TOUT * CFG_HZ;
+	while(1) {
+		dp83902a_poll();
+		if (pkey != -1) {
+			PRINTK("Packet sucesfully sent\n");
+			return 0;
+		}
+		if (get_timer (0) >= tmo) {
+			printf("transmission error (timoeut)\n");
+			return 0;
+		}
+
+	}
+	return 0;
+}

drivers/net/ne2000_base.h

@@ -80,10 +80,35 @@ are GPL, so this is, of course, GPL.
 #define __NE2000_BASE_H__
 
 #define bool int
-
 #define false 0
 #define true 1
 
+/*
+ * Debugging details
+ *
+ * Set to perms of:
+ * 0 disables all debug output
+ * 1 for process debug output
+ * 2 for added data IO output: get_reg, put_reg
+ * 4 for packet allocation/free output
+ * 8 for only startup status, so we can tell we're installed OK
+ */
+#if 0
+#define DEBUG 0xf
+#else
+#define DEBUG 0
+#endif
+
+#if DEBUG & 1
+#define DEBUG_FUNCTION() do { printf("%s\n", __FUNCTION__); } while (0)
+#define DEBUG_LINE() do { printf("%d\n", __LINE__); } while (0)
+#define PRINTK(args...) printf(args)
+#else
+#define DEBUG_FUNCTION() do {} while(0)
+#define DEBUG_LINE() do {} while(0)
+#define PRINTK(args...)
+#endif
+
 /* timeout for tx/rx in s */
 #define TOUT 5
 /* Ether MAC address size */
@@ -119,11 +144,6 @@ typedef struct dp83902a_priv_data {
 	int rx_buf_start, rx_buf_end;
 } dp83902a_priv_data_t;
 
-/*
- * Some forward declarations
- */
-static void dp83902a_poll(void);
-
 /* ------------------------------------------------------------------------ */
 /* Register offsets */
 
@@ -281,4 +301,8 @@ static void dp83902a_poll(void);
 
 #define IEEE_8023_MAX_FRAME	1518	/* Largest possible ethernet frame */
 #define IEEE_8023_MIN_FRAME	64	/* Smallest possible ethernet frame */
+
+/* Functions */
+int get_prom(u8* mac_addr, u8* base_addr);
+
 #endif /* __NE2000_BASE_H__ */

drivers/net/tsec.c

@@ -283,11 +283,13 @@ uint tsec_local_mdio_read(volatile tsec_t *phyregs, uint phyid, uint regnum)
 /* Configure the TBI for SGMII operation */
 static void tsec_configure_serdes(struct tsec_private *priv)
 {
-	tsec_local_mdio_write(priv->phyregs, CFG_TBIPA_VALUE, TBI_ANA,
+	/* Access TBI PHY registers at given TSEC register offset as opposed to the
+	 * register offset used for external PHY accesses */
+	tsec_local_mdio_write(priv->regs, priv->regs->tbipa, TBI_ANA,
 			TBIANA_SETTINGS);
-	tsec_local_mdio_write(priv->phyregs, CFG_TBIPA_VALUE, TBI_TBICON,
+	tsec_local_mdio_write(priv->regs, priv->regs->tbipa, TBI_TBICON,
 			TBICON_CLK_SELECT);
-	tsec_local_mdio_write(priv->phyregs, CFG_TBIPA_VALUE, TBI_CR,
+	tsec_local_mdio_write(priv->regs, priv->regs->tbipa, TBI_CR,
 			TBICR_SETTINGS);
 }
 
@@ -1364,6 +1366,8 @@ struct phy_info phy_info_VSC8601 = {
 				{MIIM_EXT_PAGE_ACCESS,0,NULL},
 #endif
 #endif
+				{MIIM_ANAR, MIIM_ANAR_INIT, NULL},
+				{MIIM_CONTROL, MIIM_CONTROL_RESTART, &mii_cr_init},
 				{miim_end,}
 				 },
 		(struct phy_cmd[]){     /* startup */

drivers/pci/fsl_pci_init.c

@@ -168,8 +168,21 @@ fsl_pci_init(struct pci_controller *hose)
 	}
 
 #ifndef CONFIG_PCI_NOSCAN
-	printf ("               Scanning PCI bus %02x\n", hose->current_busno);
-	hose->last_busno = pci_hose_scan_bus(hose,hose->current_busno);
+	pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &temp8);
+
+	/* Programming Interface (PCI_CLASS_PROG)
+	 * 0 == pci host or pcie root-complex,
+	 * 1 == pci agent or pcie end-point
+	 */
+	if (!temp8) {
+		printf("               Scanning PCI bus %02x\n",
+			hose->current_busno);
+		hose->last_busno = pci_hose_scan_bus(hose, hose->current_busno);
+	} else {
+		debug("               Not scanning PCI bus %02x. PI=%x\n",
+			hose->current_busno, temp8);
+		hose->last_busno = hose->current_busno;
+	}
 
 	if ( bridge ) { /* update limit regs and subordinate busno */
 		pciauto_postscan_setup_bridge(hose, dev, hose->last_busno);

drivers/pci/pci_sh7751.c

@@ -23,18 +23,19 @@
  */
 
 #include <common.h>
+#include <pci.h>
 #include <asm/processor.h>
 #include <asm/io.h>
-#include <pci.h>
+#include <asm/pci.h>
 
 /* Register addresses and such */
 #define SH7751_BCR1	(vu_long *)0xFF800000
-#define SH7751_BCR2	(vu_short*)0xFF800004
+#define SH7751_BCR2	(vu_short *)0xFF800004
 #define SH7751_WCR1	(vu_long *)0xFF800008
 #define SH7751_WCR2	(vu_long *)0xFF80000C
 #define SH7751_WCR3	(vu_long *)0xFF800010
 #define SH7751_MCR	(vu_long *)0xFF800014
-#define SH7751_BCR3	(vu_short*)0xFF800050
+#define SH7751_BCR3	(vu_short *)0xFF800050
 #define SH7751_PCICONF0 (vu_long *)0xFE200000
 #define SH7751_PCICONF1 (vu_long *)0xFE200004
 #define SH7751_PCICONF2 (vu_long *)0xFE200008
@@ -87,12 +88,12 @@
 #define SH7751_PCIPAR   (vu_long *)0xFE2001C0
 #define SH7751_PCIPDR   (vu_long *)0xFE200220
 
-#define p4_in(addr)     *(addr)
-#define p4_out(data,addr) *(addr) = (data)
+#define p4_in(addr)	(*addr)
+#define p4_out(data, addr) (*addr) = (data)
 
 /* Double word */
 int pci_sh4_read_config_dword(struct pci_controller *hose,
-			      pci_dev_t dev, int offset, u32 * value)
+			      pci_dev_t dev, int offset, u32 *value)
 {
 	u32 par_data = 0x80000000 | dev;
 
@@ -103,7 +104,7 @@ int pci_sh4_read_config_dword(struct pci_controller *hose,
 }
 
 int pci_sh4_write_config_dword(struct pci_controller *hose,
-			       pci_dev_t dev, int offset, u32 * value)
+			       pci_dev_t dev, int offset, u32 value)
 {
 	u32 par_data = 0x80000000 | dev;
 
@@ -126,15 +127,18 @@ int pci_sh7751_init(struct pci_controller *hose)
 	/* Double-check some BSC config settings */
 	/* (Area 3 non-MPX 32-bit, PCI bus pins) */
 	if ((p4_in(SH7751_BCR1) & 0x20008) == 0x20000) {
-		printf("SH7751_BCR1 0x%08X\n", p4_in(SH7751_BCR1));
+		printf("SH7751_BCR1 value is wrong(0x%08X)\n",
+			(unsigned int)p4_in(SH7751_BCR1));
 		return 2;
 	}
 	if ((p4_in(SH7751_BCR2) & 0xC0) != 0xC0) {
-		printf("SH7751_BCR2 0x%08X\n", p4_in(SH7751_BCR2));
+		printf("SH7751_BCR2 value is wrong(0x%08X)\n",
+			(unsigned int)p4_in(SH7751_BCR2));
 		return 3;
 	}
 	if (p4_in(SH7751_BCR2) & 0x01) {
-		printf("SH7751_BCR2 0x%08X\n", p4_in(SH7751_BCR2));
+		printf("SH7751_BCR2 value is wrong(0x%08X)\n",
+			(unsigned int)p4_in(SH7751_BCR2));
 		return 4;
 	}
 

drivers/pci/pci_sh7780.c

@@ -25,9 +25,10 @@
 
 #include <common.h>
 
-#include <asm/processor.h>
-#include <asm/io.h>
 #include <pci.h>
+#include <asm/processor.h>
+#include <asm/pci.h>
+#include <asm/io.h>
 
 #define SH7780_VENDOR_ID	0x1912
 #define SH7780_DEVICE_ID	0x0002
@@ -41,10 +42,10 @@
 #define SH7780_PCICR_PRST	0x00000002
 #define SH7780_PCICR_CFIN	0x00000001
 
-#define p4_in(addr)			*((vu_long *)addr)
-#define p4_out(data,addr)	*(vu_long *)(addr) = (data)
-#define p4_inw(addr)		*((vu_short *)addr)
-#define p4_outw(data,addr)	*(vu_short *)(addr) = (data)
+#define p4_in(addr)			(*(vu_long *)addr)
+#define p4_out(data, addr)	(*(vu_long *)addr) = (data)
+#define p4_inw(addr)		(*(vu_short *)addr)
+#define p4_outw(data, addr)	(*(vu_short *)addr) = (data)
 
 int pci_sh4_read_config_dword(struct pci_controller *hose,
 				    pci_dev_t dev, int offset, u32 *value)
@@ -72,9 +73,9 @@ int pci_sh7780_init(struct pci_controller *hose)
 	p4_out(0x01, SH7780_PCIECR);
 
 	if (p4_inw(SH7780_PCIVID) != SH7780_VENDOR_ID
-	    && p4_inw(SH7780_PCIDID) != SH7780_DEVICE_ID){
+	    && p4_inw(SH7780_PCIDID) != SH7780_DEVICE_ID) {
 		printf("PCI: Unknown PCI host bridge.\n");
-		return;
+		return -1;
 	}
 	printf("PCI: SH7780 PCI host bridge found.\n");
 

drivers/serial/serial_sh.c

@@ -76,7 +76,7 @@
 # define FIFOLEVEL_MASK	0xFF
 # endif
 #elif defined(CONFIG_CPU_SH7723)
-# if defined(CONIFG_SCIF_A)
+# if defined(CONFIG_SCIF_A)
 # define SCLSR	SCFSR
 # define LSR_ORER	0x0200
 # define FIFOLEVEL_MASK	0x3F

examples/stubs.c

@@ -162,11 +162,13 @@ gd_t *global_data;
 		#x ":\n"				\
 		"	mov	r13, r1\n"		\
 		"	add	%0, r1\n"		\
-		"	add	%1, r1\n"		\
+		"	mov.l @r1, r2\n"	\
+		"	add	%1, r2\n"		\
+		"	mov.l @r2, r1\n"	\
 		"	jmp	@r1\n"			\
 		"	nop\n"				\
 		"	nop\n"				\
-		: : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "r1");
+		: : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "r1", "r2");
 #elif defined(CONFIG_SPARC)
 /*
  * g7 holds the pointer to the global_data. g1 is call clobbered.

include/asm-ppc/immap_85xx.h

@@ -1552,6 +1552,13 @@ typedef struct par_io {
  */
 typedef struct ccsr_gur {
 	uint	porpllsr;	/* 0xe0000 - POR PLL ratio status register */
+#ifdef CONFIG_MPC8536
+#define MPC85xx_PORPLLSR_DDR_RATIO	0x3e000000
+#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT	25
+#else
+#define MPC85xx_PORPLLSR_DDR_RATIO	0x00003e00
+#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT	9
+#endif
 	uint	porbmsr;	/* 0xe0004 - POR boot mode status register */
 #define MPC85xx_PORBMSR_HA		0x00070000
 	uint	porimpscr;	/* 0xe0008 - POR I/O impedance status and control register */
@@ -1572,7 +1579,7 @@ typedef struct ccsr_gur {
 #define MPC85xx_PORDEVSR_RIO_DEV_ID	0x00000007
 	uint	pordbgmsr;	/* 0xe0010 - POR debug mode status register */
 	uint	pordevsr2;	/* 0xe0014 - POR I/O device status regsiter 2 */
-#define MPC85xx_PORDEVSR2_SEC_CFG	0x00000020
+#define MPC85xx_PORDEVSR2_SEC_CFG	0x00000080
 	char	res1[8];
 	uint	gpporcr;	/* 0xe0020 - General-purpose POR configuration register */
 	char	res2[12];

include/asm-ppc/ppc4xx-sdram.h

@@ -272,8 +272,11 @@
 #define SDRAM_CONF1HB_PRPD	0x00080000	/* PLB Read pipeline Disable - Bit 12 */
 #define SDRAM_CONF1HB_PWPD	0x00040000	/* PLB Write pipeline Disable - Bit 13 */
 #define SDRAM_CONF1HB_PRW	0x00020000	/* PLB Read Wait - Bit 14 */
+#define SDRAM_CONF1HB_RPLM	0x00001000	/* Read Passing Limit 1 - Bits 16..19 */
 #define SDRAM_CONF1HB_RPEN	0x00000800	/* Read Passing Enable - Bit 20 */
 #define SDRAM_CONF1HB_RFTE	0x00000400	/* Read Flow Through Enable - Bit 21 */
+#define SDRAM_CONF1HB_WRCL	0x00000080	/* MCIF Cycle Limit 1 - Bits 22..24 */
+#define SDRAM_CONF1HB_MASK	0x0000F380	/* RPLM & WRCL mask */
 
 #define SDRAM_ERRSTATHB		(SDRAMQ_DCR_BASE+0x7)	/* error status HB             */
 #define SDRAM_ERRADDUHB		(SDRAMQ_DCR_BASE+0x8)	/* error address upper 32 HB   */
@@ -284,8 +287,10 @@
 #define SDRAM_CONF1LL_PRPD	0x00080000		/* PLB Read pipeline Disable - Bit 12 */
 #define SDRAM_CONF1LL_PWPD	0x00040000		/* PLB Write pipeline Disable - Bit 13 */
 #define SDRAM_CONF1LL_PRW	0x00020000		/* PLB Read Wait - Bit 14 */
+#define SDRAM_CONF1LL_RPLM	0x00001000		/* Read Passing Limit 1 - Bits 16..19 */
 #define SDRAM_CONF1LL_RPEN	0x00000800		/* Read Passing Enable - Bit 20 */
 #define SDRAM_CONF1LL_RFTE	0x00000400		/* Read Flow Through Enable - Bit 21 */
+#define SDRAM_CONF1LL_MASK	0x0000F000		/* RPLM mask */
 
 #define SDRAM_ERRSTATLL		(SDRAMQ_DCR_BASE+0xC)	/* error status LL             */
 #define SDRAM_ERRADDULL		(SDRAMQ_DCR_BASE+0xD)	/* error address upper 32 LL   */

include/asm-sh/cache.h

@@ -3,29 +3,31 @@
 
 #if defined(CONFIG_SH4) || defined(CONFIG_SH4A)
 
+int cache_control(unsigned int cmd);
+
 #define L1_CACHE_BYTES 32
 struct __large_struct { unsigned long buf[100]; };
 #define __m(x) (*(struct __large_struct *)(x))
 
-void dcache_wback_range (u32 start, u32 end)
+void dcache_wback_range(u32 start, u32 end)
 {
 	u32 v;
 
 	start &= ~(L1_CACHE_BYTES - 1);
 	for (v = start; v < end; v += L1_CACHE_BYTES) {
-		asm volatile ("ocbwb     %0":	/* no output */
-			      :"m" (__m (v)));
+		asm volatile ("ocbwb     %0" :	/* no output */
+			      : "m" (__m(v)));
 	}
 }
 
-void dcache_invalid_range (u32 start, u32 end)
+void dcache_invalid_range(u32 start, u32 end)
 {
 	u32 v;
 
 	start &= ~(L1_CACHE_BYTES - 1);
 	for (v = start; v < end; v += L1_CACHE_BYTES) {
-		asm volatile ("ocbi     %0":	/* no output */
-			      :"m" (__m (v)));
+		asm volatile ("ocbi     %0" :	/* no output */
+			      : "m" (__m(v)));
 	}
 }
 #endif /* CONFIG_SH4 || CONFIG_SH4A */

include/asm-sh/io.h

@@ -34,9 +34,9 @@
 #define __arch_getw(a)			(*(volatile unsigned short *)(a))
 #define __arch_getl(a)			(*(volatile unsigned int *)(a))
 
-#define __arch_putb(v,a)		(*(volatile unsigned char *)(a) = (v))
-#define __arch_putw(v,a)		(*(volatile unsigned short *)(a) = (v))
-#define __arch_putl(v,a)		(*(volatile unsigned int *)(a) = (v))
+#define __arch_putb(v, a)		(*(volatile unsigned char *)(a) = (v))
+#define __arch_putw(v, a)		(*(volatile unsigned short *)(a) = (v))
+#define __arch_putl(v, a)		(*(volatile unsigned int *)(a) = (v))
 
 extern void __raw_writesb(unsigned int addr, const void *data, int bytelen);
 extern void __raw_writesw(unsigned int addr, const void *data, int wordlen);
@@ -46,9 +46,9 @@ extern void __raw_readsb(unsigned int addr, void *data, int bytelen);
 extern void __raw_readsw(unsigned int addr, void *data, int wordlen);
 extern void __raw_readsl(unsigned int addr, void *data, int longlen);
 
-#define __raw_writeb(v,a)		__arch_putb(v,a)
-#define __raw_writew(v,a)		__arch_putw(v,a)
-#define __raw_writel(v,a)		__arch_putl(v,a)
+#define __raw_writeb(v, a)		__arch_putb(v, a)
+#define __raw_writew(v, a)		__arch_putw(v, a)
+#define __raw_writel(v, a)		__arch_putl(v, a)
 
 #define __raw_readb(a)			__arch_getb(a)
 #define __raw_readw(a)			__arch_getw(a)
@@ -59,13 +59,13 @@ extern void __raw_readsl(unsigned int addr, void *data, int longlen);
  * properly.  Spell it out to the compiler in some cases.
  * These are only valid for small values of "off" (< 1<<12)
  */
-#define __raw_base_writeb(val,base,off)	__arch_base_putb(val,base,off)
-#define __raw_base_writew(val,base,off)	__arch_base_putw(val,base,off)
-#define __raw_base_writel(val,base,off)	__arch_base_putl(val,base,off)
+#define __raw_base_writeb(val, base, off)	__arch_base_putb(val, base, off)
+#define __raw_base_writew(val, base, off)	__arch_base_putw(val, base, off)
+#define __raw_base_writel(val, base, off)	__arch_base_putl(val, base, off)
 
-#define __raw_base_readb(base,off)	__arch_base_getb(base,off)
-#define __raw_base_readw(base,off)	__arch_base_getw(base,off)
-#define __raw_base_readl(base,off)	__arch_base_getl(base,off)
+#define __raw_base_readb(base, off)	__arch_base_getb(base, off)
+#define __raw_base_readw(base, off)	__arch_base_getw(base, off)
+#define __raw_base_readl(base, off)	__arch_base_getl(base, off)
 
 /*
  * Now, pick up the machine-defined IO definitions
@@ -91,36 +91,43 @@ extern void __raw_readsl(unsigned int addr, void *data, int longlen);
  *
  * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
  */
-#define outb(v,p)               __raw_writeb(v, p)
-#define outw(v,p)               __raw_writew(cpu_to_le16(v),p)
-#define outl(v,p)               __raw_writel(cpu_to_le32(v),p)
+#define outb(v, p)               __raw_writeb(v, p)
+#define outw(v, p)               __raw_writew(cpu_to_le16(v), p)
+#define outl(v, p)               __raw_writel(cpu_to_le32(v), p)
 
 #define inb(p)  ({ unsigned int __v = __raw_readb(p); __v; })
 #define inw(p)  ({ unsigned int __v = __le16_to_cpu(__raw_readw(p)); __v; })
 #define inl(p)  ({ unsigned int __v = __le32_to_cpu(__raw_readl(p)); __v; })
 
-#define outsb(p,d,l)			__raw_writesb(p,d,l)
-#define outsw(p,d,l)			__raw_writesw(p,d,l)
-#define outsl(p,d,l)			__raw_writesl(p,d,l)
+#define outsb(p, d, l)			__raw_writesb(p, d, l)
+#define outsw(p, d, l)			__raw_writesw(p, d, l)
+#define outsl(p, d, l)			__raw_writesl(p, d, l)
 
-#define insb(p,d,l)			__raw_readsb(p,d,l)
-#define insw(p,d,l)			__raw_readsw(p,d,l)
-#define insl(p,d,l)			__raw_readsl(p,d,l)
+#define insb(p, d, l)			__raw_readsb(p, d, l)
+#define insw(p, d, l)			__raw_readsw(p, d, l)
+#define insl(p, d, l)			__raw_readsl(p, d, l)
 
-#define outb_p(val,port)		outb((val),(port))
-#define outw_p(val,port)		outw((val),(port))
-#define outl_p(val,port)		outl((val),(port))
+#define outb_p(val, port)		outb((val), (port))
+#define outw_p(val, port)		outw((val), (port))
+#define outl_p(val, port)		outl((val), (port))
 #define inb_p(port)			inb((port))
 #define inw_p(port)			inw((port))
 #define inl_p(port)			inl((port))
 
-#define outsb_p(port,from,len)		outsb(port,from,len)
-#define outsw_p(port,from,len)		outsw(port,from,len)
-#define outsl_p(port,from,len)		outsl(port,from,len)
-#define insb_p(port,to,len)		insb(port,to,len)
-#define insw_p(port,to,len)		insw(port,to,len)
-#define insl_p(port,to,len)		insl(port,to,len)
+#define outsb_p(port, from, len)		outsb(port, from, len)
+#define outsw_p(port, from, len)		outsw(port, from, len)
+#define outsl_p(port, from, len)		outsl(port, from, len)
+#define insb_p(port, to, len)		insb(port, to, len)
+#define insw_p(port, to, len)		insw(port, to, len)
+#define insl_p(port, to, len)		insl(port, to, len)
 
+/* for U-Boot PCI */
+#define out_8(port, val)	outb(val, port)
+#define out_le16(port, val)	outw(val, port)
+#define out_le32(port, val)	outl(val, port)
+#define in_8(port)			inb(port)
+#define in_le16(port)		inw(port)
+#define in_le32(port)		inl(port)
 /*
  * ioremap and friends.
  *
@@ -128,7 +135,7 @@ extern void __raw_readsl(unsigned int addr, void *data, int longlen);
  * linux/Documentation/IO-mapping.txt.  If you want a
  * physical address, use __ioremap instead.
  */
-extern void * __ioremap(unsigned long offset, size_t size, unsigned long flags);
+extern void *__ioremap(unsigned long offset, size_t size, unsigned long flags);
 extern void __iounmap(void *addr);
 
 /*
@@ -139,20 +146,20 @@ extern void __iounmap(void *addr);
  *  iomem_to_phys(off)
  */
 #ifdef iomem_valid_addr
-#define __arch_ioremap(off,sz,nocache)				\
+#define __arch_ioremap(off, sz, nocache)				\
  ({								\
 	unsigned long _off = (off), _size = (sz);		\
 	void *_ret = (void *)0;					\
 	if (iomem_valid_addr(_off, _size))			\
-		_ret = __ioremap(iomem_to_phys(_off),_size,0);	\
+		_ret = __ioremap(iomem_to_phys(_off), _size, 0);	\
 	_ret;							\
  })
 
 #define __arch_iounmap __iounmap
 #endif
 
-#define ioremap(off,sz)			__arch_ioremap((off),(sz),0)
-#define ioremap_nocache(off,sz)		__arch_ioremap((off),(sz),1)
+#define ioremap(off, sz)			__arch_ioremap((off), (sz), 0)
+#define ioremap_nocache(off, sz)		__arch_ioremap((off), (sz), 1)
 #define iounmap(_addr)			__arch_iounmap(_addr)
 
 /*
@@ -180,19 +187,21 @@ extern void _memset_io(unsigned long, int, size_t);
 #ifdef __mem_pci
 
 #define readb(c) ({ unsigned int __v = __raw_readb(__mem_pci(c)); __v; })
-#define readw(c) ({ unsigned int __v = le16_to_cpu(__raw_readw(__mem_pci(c))); __v; })
-#define readl(c) ({ unsigned int __v = le32_to_cpu(__raw_readl(__mem_pci(c))); __v; })
+#define readw(c)\
+	({ unsigned int __v = le16_to_cpu(__raw_readw(__mem_pci(c))); __v; })
+#define readl(c)\
+	({ unsigned int __v = le32_to_cpu(__raw_readl(__mem_pci(c))); __v; })
 
-#define writeb(v,c)		__raw_writeb(v,__mem_pci(c))
-#define writew(v,c)		__raw_writew(cpu_to_le16(v),__mem_pci(c))
-#define writel(v,c)		__raw_writel(cpu_to_le32(v),__mem_pci(c))
+#define writeb(v, c)		__raw_writeb(v, __mem_pci(c))
+#define writew(v, c)		__raw_writew(cpu_to_le16(v), __mem_pci(c))
+#define writel(v, c)		__raw_writel(cpu_to_le32(v), __mem_pci(c))
 
-#define memset_io(c,v,l)		_memset_io(__mem_pci(c),(v),(l))
-#define memcpy_fromio(a,c,l)		_memcpy_fromio((a),__mem_pci(c),(l))
-#define memcpy_toio(c,a,l)		_memcpy_toio(__mem_pci(c),(a),(l))
+#define memset_io(c, v, l)		_memset_io(__mem_pci(c), (v), (l))
+#define memcpy_fromio(a, c, l)	_memcpy_fromio((a), __mem_pci(c), (l))
+#define memcpy_toio(c, a, l)	_memcpy_toio(__mem_pci(c), (a), (l))
 
-#define eth_io_copy_and_sum(s,c,l,b) \
-				eth_copy_and_sum((s),__mem_pci(c),(l),(b))
+#define eth_io_copy_and_sum(s, c, l, b) \
+				eth_copy_and_sum((s), __mem_pci(c), (l), (b))
 
 static inline int
 check_signature(unsigned long io_addr, const unsigned char *signature,
@@ -216,11 +225,11 @@ out:
 #define readb(addr)	__raw_readb(addr)
 #define readw(addr)	__raw_readw(addr)
 #define readl(addr)	__raw_readl(addr)
-#define writeb(v,addr)	__raw_writeb(v, addr)
-#define writew(v,addr)	__raw_writew(v, addr)
-#define writel(v,addr)	__raw_writel(v, addr)
+#define writeb(v, addr)	__raw_writeb(v, addr)
+#define writew(v, addr)	__raw_writew(v, addr)
+#define writel(v, addr)	__raw_writel(v, addr)
 
-#define check_signature(io,sig,len)	(0)
+#define check_signature(io, sig, len)	(0)
 
 #endif	/* __mem_pci */
 

include/asm-sh/pci.h

@@ -36,6 +36,7 @@ int pci_sh7780_init(struct pci_controller *hose);
 #error "Not support PCI."
 #endif
 
+int pci_sh4_init(struct pci_controller *hose);
 /* PCI dword read for sh4 */
 int pci_sh4_read_config_dword(struct pci_controller *hose,
 		pci_dev_t dev, int offset, u32 *value);

include/configs/APC405.h

@@ -315,7 +315,6 @@ extern int flash_banks;
 					/* 16 byte page write mode using*/
 					/* last	4 bits of the address */
 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10 /* and takes up to 10 msec */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
 
 /*
  * External Bus Controller (EBC) Setup

include/configs/ASH405.h

@@ -256,7 +256,6 @@
 					/* 16 byte page write mode using*/
 					/* last 4 bits of the address	*/
 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
 
 /*
  * Init Memory Controller:

include/configs/B2.h

@@ -194,7 +194,6 @@
 					/* 16 byte page write mode using*/
 					/* last 4 bits of the address	*/
 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
 
 /* Flash banks JFFS2 should use */
 /*

include/configs/CATcenter.h

@@ -419,7 +419,6 @@
 					/* 16 byte page write mode using*/
 					/* last 4 bits of the address	*/
 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
 
 /*-----------------------------------------------------------------------
  * Cache Configuration

include/configs/CMS700.h

@@ -268,7 +268,6 @@
 					/* 16 byte page write mode using*/
 					/* last 4 bits of the address	*/
 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
 
 #define CFG_EEPROM_WREN         1
 

include/configs/CPCI2DP.h

@@ -219,7 +219,6 @@
 					/* 16 byte page write mode using*/
 					/* last 4 bits of the address	*/
 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
 
 #define CFG_EEPROM_WREN         1
 

include/configs/CPCI405.h

@@ -264,7 +264,6 @@
 					/* 16 byte page write mode using*/
 					/* last 4 bits of the address	*/
 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
 
 /*
  * Init Memory Controller:

include/configs/CPCI4052.h

@@ -283,7 +283,6 @@
 					/* 16 byte page write mode using*/
 					/* last 4 bits of the address	*/
 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
 
 /*
  * Init Memory Controller:

include/configs/CPCI405AB.h

@@ -259,7 +259,6 @@
 					/* 32 byte page write mode using*/
 					/* last 5 bits of the address	*/
 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
 
 /* Use EEPROM for environment variables */
 

include/configs/CPCI405DT.h

@@ -286,7 +286,6 @@
 					/* 16 byte page write mode using*/
 					/* last 4 bits of the address	*/
 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
 
 /*
  * Init Memory Controller:

include/configs/CPCIISER4.h

@@ -198,7 +198,6 @@
 					/* 16 byte page write mode using*/
 					/* last 4 bits of the address	*/
 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
 
 #define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
 #define CONFIG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */

include/configs/DP405.h

@@ -239,7 +239,6 @@
 					/* 16 byte page write mode using*/
 					/* last 4 bits of the address	*/
 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
 
 /*-----------------------------------------------------------------------
  * External Bus Controller (EBC) Setup

include/configs/DU405.h

@@ -225,7 +225,6 @@
 					/* 16 byte page write mode using*/
 					/* last 4 bits of the address	*/
 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
 
 #define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
 #define CONFIG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */

include/configs/DU440.h

@@ -85,8 +85,7 @@
 /*
  * Serial Port
  */
-/* TODO: external clock oscillator will be removed */
-#define CFG_EXT_SERIAL_CLOCK	11059200	/* ext. 11.059MHz clk	*/
+#undef CFG_EXT_SERIAL_CLOCK
 #define CONFIG_BAUDRATE		115200
 #define CONFIG_SERIAL_MULTI     1
 #undef CONFIG_UART1_CONSOLE
@@ -183,7 +182,6 @@
 #define CFG_I2C_MULTI_EEPROMS
 #define CFG_I2C_EEPROM_ADDR	0x54
 #define CFG_I2C_EEPROM_ADDR_LEN 2
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
 #define CFG_EEPROM_PAGE_WRITE_BITS 5
 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
 #define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01
@@ -432,4 +430,7 @@ int du440_phy_addr(int devnum);
 
 #define CONFIG_AUTOSCRIPT	1
 
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+
 #endif	/* __CONFIG_H */

include/configs/EB+MCF-EV123.h

@@ -252,7 +252,7 @@
 #define CFG_PEHLPAR		0xC0
 #define CFG_PUAPAR		0x0F		/* UA0..UA3 = Uart 0 +1 */
 #define CFG_DDRUA		0x05
-#define CFG_PJPAR		0xFF;
+#define CFG_PJPAR		0xFF
 
 /*-----------------------------------------------------------------------
  * CCM configuration

include/configs/FPS850L.h

@@ -211,6 +211,8 @@
 
 #define	CFG_USE_PPCENV			/* Environment embedded in sect .ppcenv */
 
+#define CONFIG_MISC_INIT_R		/* Make sure to remap flashes correctly */
+
 /*-----------------------------------------------------------------------
  * Dynamic MTD partition support
  */

include/configs/FPS860L.h

@@ -211,6 +211,8 @@
 
 #define	CFG_USE_PPCENV			/* Environment embedded in sect .ppcenv */
 
+#define CONFIG_MISC_INIT_R		/* Make sure to remap flashes correctly */
+
 /*-----------------------------------------------------------------------
  * Dynamic MTD partition support
  */

include/configs/G2000.h

@@ -328,7 +328,6 @@
 					/* 16 byte page write mode using*/
 					/* last 4 bits of the address	*/
 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
 
 /*-----------------------------------------------------------------------
  * External Bus Controller (EBC) Setup

include/configs/HH405.h

@@ -360,7 +360,6 @@
 					/* last	5 bits of the address	*/
 #endif
 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
 
 /*-----------------------------------------------------------------------
  * External Bus Controller (EBC) Setup

include/configs/HMI10.h

@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000-2005
+ * (C) Copyright 2000-2008
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this

include/configs/HUB405.h

@@ -255,7 +255,6 @@
 					/* 16 byte page write mode using*/
 					/* last 4 bits of the address	*/
 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
 
 /*
  * Init Memory Controller:

include/configs/M5272C3.h

@@ -156,8 +156,8 @@
  * You should know what you are doing if you make changes here.
  */
 #define CFG_MBAR		0x10000000	/* Register Base Addrs */
-#define CFG_SCR			0x0003;
-#define CFG_SPR			0xffff;
+#define CFG_SCR			0x0003
+#define CFG_SPR			0xffff
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)

include/configs/M5282EVB.h

@@ -246,6 +246,6 @@
 #define CFG_PEHLPAR		0xC0
 #define CFG_PUAPAR		0x0F	/* UA0..UA3 = Uart 0 +1 */
 #define CFG_DDRUA		0x05
-#define CFG_PJPAR		0xFF;
+#define CFG_PJPAR		0xFF
 
 #endif				/* _CONFIG_M5282EVB_H */

include/configs/MIP405.h

@@ -110,7 +110,6 @@
 #define CFG_EEPROM_PAGE_WRITE_BITS 6	/* The Atmel 24C128/256 has	*/
 					/* 64 byte page write mode using*/
 					/* last	6 bits of the address	*/
-#define CFG_EEPROM_PAGE_WRITE_ENABLE	/* enable Page write */
 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
 
 

include/configs/MPC8313ERDB.h

@@ -153,12 +153,12 @@
 				| SDRAM_CFG_32_BE )
 				/* 0x43080000 */
 #endif
-#define CFG_SDRAM_CFG2		0x00401000;
+#define CFG_SDRAM_CFG2		0x00401000
 /* set burst length to 8 for 32-bit data path */
 #define CFG_DDR_MODE		( ( 0x4448 << SDRAM_MODE_ESD_SHIFT ) \
 				| ( 0x0632 << SDRAM_MODE_SD_SHIFT ) )
 				/* 0x44480632 */
-#define CFG_DDR_MODE_2		0x8000C000;
+#define CFG_DDR_MODE_2		0x8000C000
 
 #define CFG_DDR_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 				/*0x02000000*/
@@ -174,6 +174,7 @@
 #define CONFIG_FLASH_CFI_DRIVER			/* use the CFI driver */
 #define CFG_FLASH_BASE		0xFE000000	/* start of FLASH   */
 #define CFG_FLASH_SIZE		8		/* flash size in MB */
+#define CFG_FLASH_PROTECTION	1		/* Use h/w Flash protection. */
 #define CFG_FLASH_EMPTY_INFO			/* display empty sectors */
 #define CFG_FLASH_USE_BUFFER_WRITE		/* buffer up multiple bytes */
 
@@ -596,7 +597,7 @@
 #define CONFIG_FDTFILE		mpc8313erdb.dtb
 
 #define CONFIG_LOADADDR		500000	/* default location for tftp and bootm */
-#define CONFIG_BOOTDELAY	-1	/* -1 disables auto-boot */
+#define CONFIG_BOOTDELAY	6	/* -1 disables auto-boot */
 #define CONFIG_BAUDRATE		115200
 
 #define XMK_STR(x)	#x

include/configs/MPC8315ERDB.h

@@ -193,6 +193,7 @@
 
 #define CFG_FLASH_BASE		0xFE000000 /* FLASH base address */
 #define CFG_FLASH_SIZE		8 /* FLASH size is 8M */
+#define CFG_FLASH_PROTECTION	1		/* Use h/w Flash protection. */
 
 #define CFG_LBLAWBAR0_PRELIM	CFG_FLASH_BASE /* Window base at flash base */
 #define CFG_LBLAWAR0_PRELIM	0x80000016 /* 8MB window size */