Prepare 2009.03

Update CHANGELOG

Signed-off-by: Wolfgang Denk <wd@denx.de>

MAINTAINERS

@@ -380,6 +380,7 @@ Heiko Schocher <hs@denx.de>
 	ids8247		MPC8247
 	jupiter		MPC5200
 	kmeter1		MPC8360
+	kmsupx4		MPC852T
 	mgcoge		MPC8247
 	mgsuvd		MPC852
 	mucmc52		MPC5200

MAKEALL

@@ -117,6 +117,7 @@ LIST_8xx="		\
 	KUP4X		\
 	LANTEC		\
 	lwmon		\
+	kmsupx4		\
 	MBX		\
 	MBX860T		\
 	mgsuvd		\

Makefile

@@ -24,7 +24,7 @@
 VERSION = 2009
 PATCHLEVEL = 03
 SUBLEVEL =
-EXTRAVERSION = -rc1
+EXTRAVERSION =
 ifneq "$(SUBLEVEL)" ""
 U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
 else
@@ -921,6 +921,9 @@ IVMS8_config:	unconfig
 		 }
 	@$(MKCONFIG) -a IVMS8 ppc mpc8xx ivm
 
+kmsupx4_config:		unconfig
+	@$(MKCONFIG) $(@:_config=) ppc mpc8xx km8xx keymile
+
 KUP4K_config	:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc mpc8xx kup4k kup
 
@@ -938,7 +941,7 @@ MBX860T_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc mpc8xx mbx8xx
 
 mgsuvd_config:		unconfig
-	@$(MKCONFIG) $(@:_config=) ppc mpc8xx mgsuvd keymile
+	@$(MKCONFIG) $(@:_config=) ppc mpc8xx km8xx keymile
 
 MHPC_config:		unconfig
 	@$(MKCONFIG) $(@:_config=) ppc mpc8xx mhpc eltec
@@ -3029,8 +3032,12 @@ apollon_config		: unconfig
 imx31_litekit_config	: unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm1136 imx31_litekit NULL mx31
 
+imx31_phycore_eet_config \
 imx31_phycore_config	: unconfig
-	@$(MKCONFIG) $(@:_config=) arm arm1136 imx31_phycore NULL mx31
+	@if [ -n "$(findstring _eet_,$@)" ]; then			\
+		echo "#define CONFIG_IMX31_PHYCORE_EET" >> $(obj)include/config.h;	\
+	fi
+	@$(MKCONFIG) -a imx31_phycore arm arm1136 imx31_phycore NULL mx31
 
 mx31ads_config		: unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm1136 mx31ads freescale mx31
@@ -3394,10 +3401,23 @@ sh7763rdp_config  :   unconfig
 	@echo "#define CONFIG_SH7763RDP 1" > $(obj)include/config.h
 	@$(MKCONFIG) -a $(@:_config=) sh sh4 sh7763rdp renesas
 
+xtract_sh7785lcr = $(subst _32bit,,$(subst _config,,$1))
+sh7785lcr_32bit_config \
 sh7785lcr_config  :   unconfig
 	@ >include/config.h
 	@echo "#define CONFIG_SH7785LCR 1" >> include/config.h
-	@$(MKCONFIG) -a $(@:_config=) sh sh4 sh7785lcr renesas
+	@if [ "$(findstring 32bit, $@)" ] ; then \
+		echo "#define CONFIG_SH_32BIT 1" >> $(obj)include/config.h ; \
+		cp $(obj)board/renesas/sh7785lcr/u-boot_32bit \
+			$(obj)board/renesas/sh7785lcr/u-boot.lds ; \
+		echo "TEXT_BASE = 0x8ff80000" > \
+			$(obj)board/renesas/sh7785lcr/config.tmp ; \
+		  $(XECHO) " ... enable 32-Bit Address Extended Mode" ; \
+	else \
+		cp $(obj)board/renesas/sh7785lcr/u-boot_29bit \
+			$(obj)board/renesas/sh7785lcr/u-boot.lds ; \
+	fi
+	@$(MKCONFIG) -a $(call xtract_sh7785lcr,$@) sh sh4 sh7785lcr renesas
 
 ap325rxa_config  :   unconfig
 	@mkdir -p $(obj)include

README

@@ -318,6 +318,11 @@ The following options need to be configured:
 		that this requires a (stable) reference clock (32 kHz
 		RTC clock or CONFIG_SYS_8XX_XIN)
 
+		CONFIG_SYS_DELAYED_ICACHE
+
+		Define this option if you want to enable the
+		ICache only when Code runs from RAM.
+
 - Intel Monahans options:
 		CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO
 

api_examples/.gitignore

@@ -0,0 +1,7 @@
+crc32.c
+ctype.c
+demo
+demo.bin
+ppcstring.S
+string.c
+vsprintf.c

board/amcc/sequoia/sdram.c

@@ -72,7 +72,7 @@ phys_size_t initdram (int board_type)
 	mtsdram(DDR0_07, 0x000D0100);
 	mtsdram(DDR0_08, 0x02430001);
 	mtsdram(DDR0_09, 0x00011D5F);
-	mtsdram(DDR0_10, 0x00000300);
+	mtsdram(DDR0_10, 0x00000100);
 	mtsdram(DDR0_11, 0x0027C800);
 	mtsdram(DDR0_12, 0x00000003);
 	mtsdram(DDR0_14, 0x00000000);

board/esd/pmc440/sdram.c

@@ -70,7 +70,7 @@ phys_size_t initdram (int board_type)
 	mtsdram(DDR0_07, 0x000D0100);
 	mtsdram(DDR0_08, 0x02430001);
 	mtsdram(DDR0_09, 0x00011D5F);
-	mtsdram(DDR0_10, 0x00000300);
+	mtsdram(DDR0_10, 0x00000100);
 	mtsdram(DDR0_11, 0x0027C800);
 	mtsdram(DDR0_12, 0x00000003);
 	mtsdram(DDR0_14, 0x00000000);

board/freescale/common/sgmii_riser.c

@@ -47,7 +47,6 @@ void fsl_sgmii_riser_fdt_fixup(void *fdt)
 		const char *model;
 		const char *path;
 
-		printf("Updating PHY address for %s\n", dev->name);
 		if (!strstr(dev->name, "eTSEC"))
 			continue;
 
@@ -64,7 +63,6 @@ void fsl_sgmii_riser_fdt_fixup(void *fdt)
 
 		model = fdt_getprop(fdt, enet_node, "model", NULL);
 
-		printf("%s's model is %s\n", enet, model);
 		/*
 		 * We only want to do this to eTSECs.  On some platforms
 		 * there are more than one type of gianfar-style ethernet
@@ -84,7 +82,6 @@ void fsl_sgmii_riser_fdt_fixup(void *fdt)
 
 		priv = dev->priv;
 
-		printf("Device flags are %x\n", priv->flags);
 		if (priv->flags & TSEC_SGMII)
 			fdt_setprop_cell(fdt, phynode, "reg", priv->phyaddr);
 	}

board/freescale/m5329evb/nand.c

@@ -47,10 +47,12 @@ static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
 		ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
 
 		IO_ADDR_W &= ~(SET_ALE | SET_CLE);
-		*nCE &= 0xFFFB;
 
 		if (ctrl & NAND_NCE)
+			*nCE &= 0xFFFB;
+		else
 			*nCE |= 0x0004;
+
 		if (ctrl & NAND_CLE)
 			IO_ADDR_W |= SET_CLE;
 		if (ctrl & NAND_ALE)
@@ -78,7 +80,7 @@ int board_nand_init(struct nand_chip *nand)
 	gpio->pclrr_timer = 0;
 	gpio->podr_timer = 0;
 
-	nand->chip_delay = 50;
+	nand->chip_delay = 60;
 	nand->ecc.mode = NAND_ECC_SOFT;
 	nand->cmd_ctrl = nand_hwcontrol;
 

board/freescale/m5373evb/nand.c

@@ -47,10 +47,12 @@ static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
 		ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
 
 		IO_ADDR_W &= ~(SET_ALE | SET_CLE);
-		*nCE &= 0xFFFB;
 
 		if (ctrl & NAND_NCE)
+			*nCE &= 0xFFFB;
+		else
 			*nCE |= 0x0004;
+
 		if (ctrl & NAND_CLE)
 			IO_ADDR_W |= SET_CLE;
 		if (ctrl & NAND_ALE)
@@ -82,7 +84,7 @@ int board_nand_init(struct nand_chip *nand)
 	gpio->pclrr_timer = 0;
 	gpio->podr_timer = 0;
 
-	nand->chip_delay = 50;
+	nand->chip_delay = 60;
 	nand->ecc.mode = NAND_ECC_SOFT;
 	nand->cmd_ctrl = nand_hwcontrol;
 

board/freescale/mpc837xemds/pci.c

@@ -115,6 +115,13 @@ skip_pci:
 	if (PARTID_NO_E(spridr) == SPR_8379)
 		return;
 
+	if (pex2)
+		fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX_X2,
+				 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
+	else
+		fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
+				 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
+
 	/* Configure the clock for PCIE controller */
 	clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM,
 				    SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1);
@@ -132,13 +139,6 @@ skip_pci:
 	out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
 	out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
 
-	if (pex2)
-		fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX_X2,
-				 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
-	else
-		fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
-				 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
-
 	mpc83xx_pcie_init(pex2 ? 1 : 2, pcie_reg, 0);
 }
 

board/freescale/mpc837xerdb/pci.c

@@ -13,6 +13,7 @@
 #include <common.h>
 #include <mpc83xx.h>
 #include <pci.h>
+#include <asm/io.h>
 
 #if defined(CONFIG_PCI)
 static struct pci_region pci_regions[] = {
@@ -36,12 +37,46 @@ static struct pci_region pci_regions[] = {
 	}
 };
 
+static struct pci_region pcie_regions_0[] = {
+	{
+		.bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
+		.phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
+		.size = CONFIG_SYS_PCIE1_MEM_SIZE,
+		.flags = PCI_REGION_MEM,
+	},
+	{
+		.bus_start = CONFIG_SYS_PCIE1_IO_BASE,
+		.phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
+		.size = CONFIG_SYS_PCIE1_IO_SIZE,
+		.flags = PCI_REGION_IO,
+	},
+};
+
+static struct pci_region pcie_regions_1[] = {
+	{
+		.bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
+		.phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
+		.size = CONFIG_SYS_PCIE2_MEM_SIZE,
+		.flags = PCI_REGION_MEM,
+	},
+	{
+		.bus_start = CONFIG_SYS_PCIE2_IO_BASE,
+		.phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
+		.size = CONFIG_SYS_PCIE2_IO_SIZE,
+		.flags = PCI_REGION_IO,
+	},
+};
+
 void pci_init_board(void)
 {
 	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+	volatile sysconf83xx_t *sysconf = &immr->sysconf;
 	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
 	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+	volatile law83xx_t *pcie_law = sysconf->pcielaw;
 	struct pci_region *reg[] = { pci_regions };
+	struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
+	u32 spridr = in_be32(&immr->sysconf.spridr);
 
 	/* Enable all 5 PCI_CLK_OUTPUTS */
 	clk->occr |= 0xf8000000;
@@ -55,5 +90,27 @@ void pci_init_board(void)
 	pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
 
 	mpc83xx_pci_init(1, reg, 0);
+
+	/* There is no PEX in MPC8379 parts. */
+	if (PARTID_NO_E(spridr) == SPR_8379)
+		return;
+
+	/* Configure the clock for PCIE controller */
+	clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM,
+				    SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1);
+
+	/* Deassert the resets in the control register */
+	out_be32(&sysconf->pecr1, 0xE0008000);
+	out_be32(&sysconf->pecr2, 0xE0008000);
+	udelay(2000);
+
+	/* Configure PCI Express Local Access Windows */
+	out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
+	out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
+
+	out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
+	out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
+
+	mpc83xx_pcie_init(2, pcie_reg, 0);
 }
 #endif	/* CONFIG_PCI */

board/freescale/mpc8641hpcn/mpc8641hpcn.c

@@ -46,6 +46,9 @@ int checkboard(void)
 		"System Version: 0x%02x, FPGA Version: 0x%02x\n",
 		in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
 		in8(PIXIS_BASE + PIXIS_PVER));
+#ifdef CONFIG_PHYS_64BIT
+	printf ("       36-bit physical address map\n");
+#endif
 	return 0;
 }
 

board/imx31_phycore/imx31_phycore.c

@@ -23,6 +23,7 @@
 
 
 #include <common.h>
+#include <s6e63d6.h>
 #include <asm/arch/mx31.h>
 #include <asm/arch/mx31-regs.h>
 
@@ -66,6 +67,62 @@ int board_init (void)
 	return 0;
 }
 
+#ifdef BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef CONFIG_S6E63D6
+	struct s6e63d6 data = {
+		/*
+		 * See comment in mxc_spi.c::decode_cs() for .cs field format.
+		 * We use GPIO 57 as a chipselect for the S6E63D6 and chipselect
+		 * 2 of the SPI controller #1, since it is unused.
+		 */
+		.cs = 2 | (57 << 8),
+		.bus = 0,
+		.id = 0,
+	};
+	int ret;
+
+	/* SPI1 */
+	mx31_gpio_mux(MUX_CSPI1_SCLK__CSPI1_CLK);
+	mx31_gpio_mux(MUX_CSPI1_SPI_RDY__CSPI1_DATAREADY_B);
+	mx31_gpio_mux(MUX_CSPI1_MOSI__CSPI1_MOSI);
+	mx31_gpio_mux(MUX_CSPI1_MISO__CSPI1_MISO);
+	mx31_gpio_mux(MUX_CSPI1_SS0__CSPI1_SS0_B);
+	mx31_gpio_mux(MUX_CSPI1_SS1__CSPI1_SS1_B);
+	mx31_gpio_mux(MUX_CSPI1_SS2__CSPI1_SS2_B);
+
+	/* start SPI1 clock */
+	__REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 2);
+
+	/* GPIO 57 */
+	/* sw_mux_ctl_key_col4_key_col5_key_col6_key_col7 */
+	mx31_gpio_mux(IOMUX_MODE(0x63, MUX_CTL_GPIO));
+
+	/* SPI1 CS2 is free */
+	ret = s6e63d6_init(&data);
+	if (ret)
+		return ret;
+
+	/*
+	 * This is a "magic" sequence to initialise a C0240QGLA / C0283QGLC
+	 * OLED display connected to a S6E63D6 SPI display controller in the
+	 * 18 bit RGB mode
+	 */
+	s6e63d6_index(&data, 2);
+	s6e63d6_param(&data, 0x0182);
+	s6e63d6_index(&data, 3);
+	s6e63d6_param(&data, 0x8130);
+	s6e63d6_index(&data, 0x10);
+	s6e63d6_param(&data, 0x0000);
+	s6e63d6_index(&data, 5);
+	s6e63d6_param(&data, 0x0001);
+	s6e63d6_index(&data, 0x22);
+#endif
+	return 0;
+}
+#endif
+
 int checkboard (void)
 {
 	printf("Board: Phytec phyCore i.MX31\n");

board/keymile/common/common.c

@@ -295,11 +295,14 @@ int ivm_analyze_eeprom (unsigned char *buf, int len)
 
 int ivm_read_eeprom (void)
 {
+#if defined(CONFIG_I2C_MUX)
 	I2C_MUX_DEVICE *dev = NULL;
+#endif
 	uchar i2c_buffer[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
 	uchar	*buf;
 	unsigned dev_addr = CONFIG_SYS_IVM_EEPROM_ADR;
 
+#if defined(CONFIG_I2C_MUX)
 	/* First init the Bus, select the Bus */
 #if defined(CONFIG_SYS_I2C_IVM_BUS)
 	dev = i2c_mux_ident_muxstring ((uchar *)CONFIG_SYS_I2C_IVM_BUS);
@@ -313,12 +316,13 @@ int ivm_read_eeprom (void)
 		return -1;
 	}
 	i2c_set_bus_num (dev->busid);
+#endif
 
 	buf = (unsigned char *) getenv ("EEprom_ivm_addr");
 	if (buf != NULL)
 		dev_addr = simple_strtoul ((char *)buf, NULL, 16);
 
-	if (eeprom_read (dev_addr, 0, i2c_buffer, CONFIG_SYS_IVM_EEPROM_MAX_LEN) != 0) {
+	if (i2c_read(dev_addr, 0, 1, i2c_buffer, CONFIG_SYS_IVM_EEPROM_MAX_LEN) != 0) {
 		printf ("Error reading EEprom\n");
 		return -2;
 	}
@@ -390,7 +394,7 @@ static void setports (int gpio)
 #endif
 #endif
 
-#if defined(CONFIG_MGSUVD)
+#if defined(CONFIG_KM8XX)
 static void set_sda (int state)
 {
 	I2C_SDA(state);

board/keymile/common/keymile_hdlc_enet.h

@@ -25,7 +25,7 @@
 #define _KEYMILE_HDLC_ENET_H_
 
 /* Unfortuantely, we have do this to get the flag defines in the cbd_t */
-#ifdef CONFIG_MGSUVD
+#ifdef CONFIG_KM8XX
 #include <commproc.h>
 #endif
 #ifdef CONFIG_MGCOGE

board/keymile/km8xx/Makefile

@@ -29,7 +29,7 @@ endif
 LIB	= $(obj)lib$(BOARD).a
 
 COBJS	= $(BOARD).o ../common/common.o ../common/keymile_hdlc_enet.o \
-		mgsuvd_hdlc_enet.o
+		km8xx_hdlc_enet.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))

board/keymile/km8xx/km8xx.c

@@ -61,7 +61,12 @@ const uint sdram_table[] =
 
 int checkboard (void)
 {
-	puts ("Board: Keymile mgsuvd");
+	puts ("Board: Keymile ");
+#if defined(CONFIG_KMSUPX4)
+	puts ("kmsupx4");
+#else
+	puts ("mgsuvd");
+#endif
 	if (ethernet_present ())
 		puts (" with PIGGY.");
 	puts ("\n");

board/keymile/kmeter1/kmeter1.c

@@ -24,11 +24,14 @@
 #include <miiphy.h>
 #include <asm/io.h>
 #include <asm/mmu.h>
+#include <asm/processor.h>
 #include <pci.h>
 #include <libfdt.h>
 
 #include "../common/common.h"
 
+extern void disable_addr_trans (void);
+extern void enable_addr_trans (void);
 const qe_iop_conf_t qe_iop_conf_tab[] = {
 	/* port pin dir open_drain assign */
 
@@ -59,27 +62,54 @@ const qe_iop_conf_t qe_iop_conf_tab[] = {
 	{0,  0, 0, 0, QE_IOP_TAB_END},
 };
 
+static int board_init_i2c_busses (void)
+{
+	I2C_MUX_DEVICE *dev = NULL;
+	uchar	*buf;
+
+	/* Set up the Bus for the DTTs */
+	buf = (unsigned char *) getenv ("dtt_bus");
+	if (buf != NULL)
+		dev = i2c_mux_ident_muxstring (buf);
+	if (dev == NULL) {
+		printf ("Error couldn't add Bus for DTT\n");
+		printf ("please setup dtt_bus to where your\n");
+		printf ("DTT is found.\n");
+	}
+	return 0;
+}
+
 int board_early_init_r (void)
 {
-	void *reg = (void *)(CONFIG_SYS_IMMR + 0x14a8);
-	u32 val;
+	unsigned short	svid;
 
 	/*
 	 * Because of errata in the UCCs, we have to write to the reserved
 	 * registers to slow the clocks down.
 	 */
-	val = in_be32 (reg);
-	/* UCC1 */
-	val |= 0x00003000;
-	/* UCC2 */
-	val |= 0x0c000000;
-	out_be32 (reg, val);
+	svid =  SVR_REV(mfspr (SVR));
+	switch (svid) {
+	case 0x0020:
+		setbits_be32((void *)(CONFIG_SYS_IMMR + 0x14a8), 0x0c003000);
+		break;
+	case 0x0021:
+		clrsetbits_be32((void *)(CONFIG_SYS_IMMR + 0x14ac),
+			0x00000050, 0x000000a0);
+		break;
+	}
 	/* enable the PHY on the PIGGY */
 	setbits (8, (void *)(CONFIG_SYS_PIGGY_BASE + 0x10003), 0x01);
 
 	return 0;
 }
 
+int misc_init_r (void)
+{
+	/* add board specific i2c busses */
+	board_init_i2c_busses ();
+	return 0;
+}
+
 int fixed_sdram(void)
 {
 	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
@@ -87,16 +117,7 @@ int fixed_sdram(void)
 	u32 ddr_size;
 	u32 ddr_size_log2;
 
-	msize = CONFIG_SYS_DDR_SIZE;
-	for (ddr_size = msize << 20, ddr_size_log2 = 0;
-	     (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
-		if (ddr_size & 1)
-			return -1;
-	}
-
-	im->sysconf.ddrlaw[0].ar =
-	    LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
-
+	im->sysconf.ddrlaw[0].ar = LAWAR_EN | 0x1e;
 	im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
 	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
 	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
@@ -112,6 +133,21 @@ int fixed_sdram(void)
 	udelay (200);
 	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
 
+	msize = CONFIG_SYS_DDR_SIZE << 20;
+	disable_addr_trans ();
+	msize = get_ram_size (CONFIG_SYS_DDR_BASE, msize);
+	enable_addr_trans ();
+	msize /= (1024 * 1024);
+	if (CONFIG_SYS_DDR_SIZE != msize) {
+		for (ddr_size = msize << 20, ddr_size_log2 = 0;
+		     (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++)
+			if (ddr_size & 1)
+				return -1;
+		im->sysconf.ddrlaw[0].ar =
+		    LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
+		im->ddr.csbnds[0].csbnds = (((msize / 16) - 1) & 0xff);
+	}
+
 	return msize;
 }
 
@@ -156,3 +192,12 @@ void ft_board_setup (void *blob, bd_t *bd)
 	ft_cpu_setup (blob, bd);
 }
 #endif
+
+#if defined(CONFIG_HUSH_INIT_VAR)
+extern int ivm_read_eeprom (void);
+int hush_init_var (void)
+{
+	ivm_read_eeprom ();
+	return 0;
+}
+#endif

board/lwmon5/sdram.c

@@ -160,49 +160,6 @@ static void program_ecc(u32 start_address,
  ************************************************************************/
 phys_size_t initdram (int board_type)
 {
-#if 0 /* test-only: will remove this define later, when ECC problems are solved! */
-	/* CL=3 */
-	mtsdram(DDR0_02, 0x00000000);
-
-	mtsdram(DDR0_00, 0x0000190A);
-	mtsdram(DDR0_01, 0x01000000);
-	mtsdram(DDR0_03, 0x02030603); /* A suitable burst length was taken. CAS is right for our board */
-
-	mtsdram(DDR0_04, 0x0A030300);
-	mtsdram(DDR0_05, 0x02020308);
-	mtsdram(DDR0_06, 0x0103C812);
-	mtsdram(DDR0_07, 0x00090100);
-	mtsdram(DDR0_08, 0x02c80001);
-	mtsdram(DDR0_09, 0x00011D5F);
-	mtsdram(DDR0_10, 0x00000300);
-	mtsdram(DDR0_11, 0x000CC800);
-	mtsdram(DDR0_12, 0x00000003);
-	mtsdram(DDR0_14, 0x00000000);
-	mtsdram(DDR0_17, 0x1e000000);
-	mtsdram(DDR0_18, 0x1e1e1e1e);
-	mtsdram(DDR0_19, 0x1e1e1e1e);
-	mtsdram(DDR0_20, 0x0B0B0B0B);
-	mtsdram(DDR0_21, 0x0B0B0B0B);
-#ifdef CONFIG_DDR_ECC
-	mtsdram(DDR0_22, 0x00267F0B | DDR0_22_CTRL_RAW_ECC_ENABLE); /* enable ECC	*/
-#else
-	mtsdram(DDR0_22, 0x00267F0B);
-#endif
-
-	mtsdram(DDR0_23, 0x01000000);
-	mtsdram(DDR0_24, 0x01010001);
-
-	mtsdram(DDR0_26, 0x2D93028A);
-	mtsdram(DDR0_27, 0x0784682B);
-
-	mtsdram(DDR0_28, 0x00000080);
-	mtsdram(DDR0_31, 0x00000000);
-	mtsdram(DDR0_42, 0x01000006);
-
-	mtsdram(DDR0_43, 0x030A0200);
-	mtsdram(DDR0_44, 0x00000003);
-	mtsdram(DDR0_02, 0x00000001); /* Activate the denali core */
-#else
 	/* CL=4 */
 	mtsdram(DDR0_02, 0x00000000);
 
@@ -216,7 +173,7 @@ phys_size_t initdram (int board_type)
 	mtsdram(DDR0_07, 0x00090100);
 	mtsdram(DDR0_08, 0x03c80001);
 	mtsdram(DDR0_09, 0x00011D5F);
-	mtsdram(DDR0_10, 0x00000300);
+	mtsdram(DDR0_10, 0x00000100);
 	mtsdram(DDR0_11, 0x000CC800);
 	mtsdram(DDR0_12, 0x00000003);
 	mtsdram(DDR0_14, 0x00000000);
@@ -244,7 +201,6 @@ phys_size_t initdram (int board_type)
 	mtsdram(DDR0_43, 0x050A0200);
 	mtsdram(DDR0_44, 0x00000005);
 	mtsdram(DDR0_02, 0x00000001); /* Activate the denali core */
-#endif
 
 	denali_wait_for_dlllock();
 

board/ms7720se/lowlevel_init.S

@@ -18,6 +18,8 @@
  * MA 02111-1307 USA
  */
 
+#include <asm/macro.h>
+
 	.global	lowlevel_init
 
 	.text
@@ -25,157 +27,83 @@
 
 lowlevel_init:
 
-	mov.l	WTCSR_A,r1
-	mov.l	WTCSR_D,r0
-	mov.w	r0,@r1
+	write16	WTCSR_A, WTCSR_D
 
-	mov.l	WTCNT_A,r1
-	mov.l	WTCNT_D,r0
-	mov.w	r0,@r1
+	write16	WTCNT_A, WTCNT_D
 
-	mov.l	FRQCR_A,r1
-	mov.l	FRQCR_D,r0
-	mov.w	r0,@r1
+	write16	FRQCR_A, FRQCR_D
 
-	mov.l	UCLKCR_A,r1
-	mov.l	UCLKCR_D,r0
-	mov.w	r0,@r1
+	write16	UCLKCR_A, UCLKCR_D
 
-	mov.l	CMNCR_A, r1
-	mov.l	CMNCR_D, r0
-	mov.l	r0, @r1
+	write32	CMNCR_A, CMNCR_D
 
-	mov.l	CS0BCR_A, r1
-	mov.l	CS0BCR_D, r0
-	mov.l	r0, @r1
+	write32	CMNCR_A, CMNCR_D
 
-	mov.l	CS2BCR_A, r1
-	mov.l	CS2BCR_D, r0
-	mov.l	r0, @r1
+	write32	CS0BCR_A, CS0BCR_D
 
-	mov.l	CS3BCR_A, r1
-	mov.l	CS3BCR_D, r0
-	mov.l	r0, @r1
+	write32	CS2BCR_A, CS2BCR_D
 
-	mov.l	CS4BCR_A, r1
-	mov.l	CS4BCR_D, r0
-	mov.l	r0, @r1
+	write32	CS3BCR_A, CS3BCR_D
 
-	mov.l	CS5ABCR_A, r1
-	mov.l	CS5ABCR_D, r0
-	mov.l	r0, @r1
+	write32	CS4BCR_A, CS4BCR_D
 
-	mov.l	CS5BBCR_A, r1
-	mov.l	CS5BBCR_D, r0
-	mov.l	r0, @r1
+	write32	CS5ABCR_A, CS5ABCR_D
 
-	mov.l	CS6ABCR_A, r1
-	mov.l	CS6ABCR_D, r0
-	mov.l	r0, @r1
+	write32	CS5BBCR_A, CS5BBCR_D
 
-	mov.l	CS6BBCR_A, r1
-	mov.l	CS6BBCR_D, r0
-	mov.l	r0, @r1
+	write32	CS6ABCR_A, CS6ABCR_D
 
-	mov.l	CS0WCR_A, r1
-	mov.l	CS0WCR_D, r0
-	mov.l	r0, @r1
+	write32	CS6BBCR_A, CS6BBCR_D
 
-	mov.l	CS2WCR_A, r1
-	mov.l	CS2WCR_D, r0
-	mov.l	r0, @r1
+	write32	CS0WCR_A, CS0WCR_D
 
-	mov.l	CS3WCR_A, r1
-	mov.l	CS3WCR_D, r0
-	mov.l	r0, @r1
+	write32	CS2WCR_A, CS2WCR_D
 
-	mov.l	CS4WCR_A, r1
-	mov.l	CS4WCR_D, r0
-	mov.l	r0, @r1
+	write32	CS3WCR_A, CS3WCR_D
 
-	mov.l	CS5AWCR_A, r1
-	mov.l	CS5AWCR_D, r0
-	mov.l	r0, @r1
+	write32	CS4WCR_A, CS4WCR_D
 
-	mov.l	CS5BWCR_A, r1
-	mov.l	CS5BWCR_D, r0
-	mov.l	r0, @r1
+	write32	CS5AWCR_A, CS5AWCR_D
 
-	mov.l	CS6AWCR_A, r1
-	mov.l	CS6AWCR_D, r0
-	mov.l	r0, @r1
+	write32	CS5BWCR_A, CS5BWCR_D
 
-	mov.l	CS6BWCR_A, r1
-	mov.l	CS6BWCR_D, r0
-	mov.l	r0, @r1
+	write32	CS6AWCR_A, CS6AWCR_D
 
-	mov.l	SDCR_A, r1
-	mov.l	SDCR_D1, r0
-	mov.l	r0, @r1
+	write32	CS6BWCR_A, CS6BWCR_D
 
-	mov.l	RTCSR_A, r1
-	mov.l	RTCSR_D, r0
-	mov.l	r0, @r1
+	write32	SDCR_A, SDCR_D1
 
-	mov.l	RTCNT_A, r1
-	mov.l	RTCNT_D, r0
-	mov.l	r0, @r1
+	write32	RTCSR_A, RTCSR_D
 
-	mov.l	RTCOR_A, r1
-	mov.l	RTCOR_D, r0
-	mov.l	r0, @r1
+	write32	RTCNT_A RTCNT_D
 
-	mov.l	SDCR_A, r1
-	mov.l	SDCR_D2, r0
-	mov.l	r0, @r1
+	write32	RTCOR_A, RTCOR_D
 
-	mov.l	SDMR3_A, r1
-	mov.l	SDMR3_D, r0
-	mov.w	r0, @r1
+	write32	SDCR_A, SDCR_D2
 
-	mov.l	PCCR_A, r1
-	mov.l	PCCR_D, r0
-	mov.w	r0, @r1
+	write16	SDMR3_A, SDMR3_D
 
-	mov.l	PDCR_A, r1
-	mov.l	PDCR_D, r0
-	mov.w	r0, @r1
+	write16	PCCR_A, PCCR_D
 
-	mov.l	PECR_A, r1
-	mov.l	PECR_D, r0
-	mov.w	r0, @r1
+	write16	PDCR_A, PDCR_D
 
-	mov.l	PGCR_A, r1
-	mov.l	PGCR_D, r0
-	mov.w	r0, @r1
+	write16	PECR_A, PECR_D
 
-	mov.l	PHCR_A, r1
-	mov.l	PHCR_D, r0
-	mov.w	r0, @r1
+	write16	PGCR_A, PGCR_D
 
-	mov.l	PPCR_A, r1
-	mov.l	PPCR_D, r0
-	mov.w	r0, @r1
+	write16	PHCR_A, PHCR_D
 
-	mov.l	PTCR_A, r1
-	mov.l	PTCR_D, r0
-	mov.w	r0, @r1
+	write16	PPCR_A, PPCR_D
 
-	mov.l	PVCR_A, r1
-	mov.l	PVCR_D, r0
-	mov.w	r0, @r1
+	write16	PTCR_A, PTCR_D
 
-	mov.l	PSELA_A, r1
-	mov.l	PSELA_D, r0
-	mov.w	r0, @r1
+	write16	PVCR_A, PVCR_D
 
-	mov.l	CCR_A, r1
-	mov.l	CCR_D, r0
-	mov.l	r0, @r1
+	write16	PSELA_A, PSELA_D
 
-	mov.l	LED_A, r1
-	mov.l	LED_D, r0
-	mov.b	r0, @r1
+	write32	CCR_A, CCR_D
+
+	write8	LED_A, LED_D
 
 	rts
 	 nop

board/omap3/beagle/beagle.c

@@ -116,6 +116,8 @@ int misc_init_r(void)
 
 	beagle_identify();
 
+	dieid_num_r();
+
 	return 0;
 }
 

board/omap3/evm/evm.c

@@ -68,6 +68,8 @@ int misc_init_r(void)
 	setup_net_chip();
 #endif
 
+	dieid_num_r();
+
 	return 0;
 }
 

board/omap3/overo/overo.c

@@ -60,6 +60,8 @@ int misc_init_r(void)
 {
 	power_init_r();
 
+	dieid_num_r();
+
 	return 0;
 }
 

board/omap3/pandora/pandora.c

@@ -77,6 +77,8 @@ int misc_init_r(void)
 	writel(GPIO28, &gpio5_base->setdataout);
 	writel(GPIO4, &gpio6_base->setdataout);
 
+	dieid_num_r();
+
 	return 0;
 }
 

board/omap3/zoom1/zoom1.c

@@ -61,6 +61,7 @@ int board_init(void)
 int misc_init_r(void)
 {
 	power_init_r();
+	dieid_num_r();
 	return 0;
 }
 

board/renesas/ap325rxa/lowlevel_init.S

@@ -173,7 +173,7 @@ CS6BBCR_D:	.long	0x24920600
 CS0WCR_D:	.long	0x00000480
 CS4WCR_D:	.long	0x00000480
 CS5AWCR_D:	.long	0x00000380
-CS5BWCR_D:	.long	0x00000600
+CS5BWCR_D:	.long	0x00000080
 CS6AWCR_D:	.long	0x00000300
 CS6BWCR_D:	.long	0x00000540
 

board/renesas/sh7785lcr/config.mk

@@ -22,4 +22,8 @@
 #
 # NOTE: Must match value used in u-boot.lds (in this directory).
 #
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
+
+ifndef TEXT_BASE
 TEXT_BASE = 0x0ff80000
+endif

board/renesas/sh7785lcr/lowlevel_init.S

@@ -130,6 +130,46 @@ lbsc_29bit:
 	write32	CS6WCR_A,	CS_SD_WCR_D
 
 lbsc_end:
+#if defined(CONFIG_SH_32BIT)
+	/*------- set PMB -------*/
+	write32	PASCR_A,	PASCR_29BIT_D
+	write32	MMUCR_A,	MMUCR_D
+
+	/*****************************************************************
+	 * ent	virt		phys		v	sz	c	wt
+	 * 0	0xa0000000	0x00000000	1	64M	0	0
+	 * 1	0xa4000000	0x04000000	1	16M	0	0
+	 * 2	0xa6000000	0x08000000	1	16M	0	0
+	 * 9	0x88000000	0x48000000	1	128M	1	1
+	 * 10	0x90000000	0x50000000	1	128M	1	1
+	 * 11	0x98000000	0x58000000	1	128M	1	1
+	 * 13	0xa8000000	0x48000000	1	128M	0	0
+	 * 14	0xb0000000	0x50000000	1	128M	0	0
+	 * 15	0xb8000000	0x58000000	1	128M	0	0
+	 */
+	write32	PMB_ADDR_FLASH_A,	PMB_ADDR_FLASH_D
+	write32	PMB_DATA_FLASH_A,	PMB_DATA_FLASH_D
+	write32	PMB_ADDR_CPLD_A,	PMB_ADDR_CPLD_D
+	write32	PMB_DATA_CPLD_A,	PMB_DATA_CPLD_D
+	write32	PMB_ADDR_USB_A,		PMB_ADDR_USB_D
+	write32	PMB_DATA_USB_A,		PMB_DATA_USB_D
+	write32	PMB_ADDR_DDR_C1_A,	PMB_ADDR_DDR_C1_D
+	write32	PMB_DATA_DDR_C1_A,	PMB_DATA_DDR_C1_D
+	write32	PMB_ADDR_DDR_C2_A,	PMB_ADDR_DDR_C2_D
+	write32	PMB_DATA_DDR_C2_A,	PMB_DATA_DDR_C2_D
+	write32	PMB_ADDR_DDR_C3_A,	PMB_ADDR_DDR_C3_D
+	write32	PMB_DATA_DDR_C3_A,	PMB_DATA_DDR_C3_D
+	write32	PMB_ADDR_DDR_N1_A,	PMB_ADDR_DDR_N1_D
+	write32	PMB_DATA_DDR_N1_A,	PMB_DATA_DDR_N1_D
+	write32	PMB_ADDR_DDR_N2_A,	PMB_ADDR_DDR_N2_D
+	write32	PMB_DATA_DDR_N2_A,	PMB_DATA_DDR_N2_D
+	write32	PMB_ADDR_DDR_N3_A,	PMB_ADDR_DDR_N3_D
+	write32	PMB_DATA_DDR_N3_A,	PMB_DATA_DDR_N3_D
+
+	write32	PASCR_A,	PASCR_INIT
+	mov.l	DUMMY_ADDR, r0
+	icbi	@r0
+#endif
 
 	write32	CCR_A,	CCR_D
 
@@ -140,7 +180,11 @@ lbsc_end:
 
 /*------- LBSC -------*/
 MMSELR_A:	.long	0xfc400020
+#if defined(CONFIG_SH_32BIT)
+MMSELR_D:	.long	0xa5a50005
+#else
 MMSELR_D:	.long	0xa5a50002
+#endif
 
 /*------- DBSC2 -------*/
 #define DBSC2_BASE	0xfe800000
@@ -287,5 +331,55 @@ CS_SD_WCR_D:	.long	0x00030108
 CS_I2C_BCR_D:	.long	0x11111100
 CS_I2C_WCR_D:	.long	0x00000003
 
+#if defined(CONFIG_SH_32BIT)
+/*------- set PMB -------*/
+PMB_ADDR_FLASH_A:	.long	PMB_ADDR_BASE(0)
+PMB_ADDR_CPLD_A:	.long	PMB_ADDR_BASE(1)
+PMB_ADDR_USB_A:		.long	PMB_ADDR_BASE(2)
+PMB_ADDR_DDR_C1_A:	.long	PMB_ADDR_BASE(9)
+PMB_ADDR_DDR_C2_A:	.long	PMB_ADDR_BASE(10)
+PMB_ADDR_DDR_C3_A:	.long	PMB_ADDR_BASE(11)
+PMB_ADDR_DDR_N1_A:	.long	PMB_ADDR_BASE(13)
+PMB_ADDR_DDR_N2_A:	.long	PMB_ADDR_BASE(14)
+PMB_ADDR_DDR_N3_A:	.long	PMB_ADDR_BASE(15)
+
+PMB_ADDR_FLASH_D:	.long	mk_pmb_addr_val(0xa0)
+PMB_ADDR_CPLD_D:	.long	mk_pmb_addr_val(0xa4)
+PMB_ADDR_USB_D:		.long	mk_pmb_addr_val(0xa6)
+PMB_ADDR_DDR_C1_D:	.long	mk_pmb_addr_val(0x88)
+PMB_ADDR_DDR_C2_D:	.long	mk_pmb_addr_val(0x90)
+PMB_ADDR_DDR_C3_D:	.long	mk_pmb_addr_val(0x98)
+PMB_ADDR_DDR_N1_D:	.long	mk_pmb_addr_val(0xa8)
+PMB_ADDR_DDR_N2_D:	.long	mk_pmb_addr_val(0xb0)
+PMB_ADDR_DDR_N3_D:	.long	mk_pmb_addr_val(0xb8)
+
+PMB_DATA_FLASH_A:	.long	PMB_DATA_BASE(0)
+PMB_DATA_CPLD_A:	.long	PMB_DATA_BASE(1)
+PMB_DATA_USB_A:		.long	PMB_DATA_BASE(2)
+PMB_DATA_DDR_C1_A:	.long	PMB_DATA_BASE(9)
+PMB_DATA_DDR_C2_A:	.long	PMB_DATA_BASE(10)
+PMB_DATA_DDR_C3_A:	.long	PMB_DATA_BASE(11)
+PMB_DATA_DDR_N1_A:	.long	PMB_DATA_BASE(13)
+PMB_DATA_DDR_N2_A:	.long	PMB_DATA_BASE(14)
+PMB_DATA_DDR_N3_A:	.long	PMB_DATA_BASE(15)
+
+/*						ppn   ub v s1 s0  c  wt */
+PMB_DATA_FLASH_D:	.long	mk_pmb_data_val(0x00, 1, 1, 0, 1, 0, 1)
+PMB_DATA_CPLD_D:	.long	mk_pmb_data_val(0x04, 1, 1, 0, 0, 0, 1)
+PMB_DATA_USB_D:		.long	mk_pmb_data_val(0x08, 1, 1, 0, 0, 0, 1)
+PMB_DATA_DDR_C1_D:	.long	mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1)
+PMB_DATA_DDR_C2_D:	.long	mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1)
+PMB_DATA_DDR_C3_D:	.long	mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1)
+PMB_DATA_DDR_N1_D:	.long	mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1)
+PMB_DATA_DDR_N2_D:	.long	mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1)
+PMB_DATA_DDR_N3_D:	.long	mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1)
+
+DUMMY_ADDR:	.long	0xa0000000
+PASCR_29BIT_D:	.long	0x00000000
+PASCR_INIT:	.long	0x80000080	/* check booting mode */
+MMUCR_A:	.long	0xff000010
+MMUCR_D:	.long	0x00000004	/* clear ITLB */
+#endif	/* CONFIG_SH_32BIT */
+
 CCR_A:		.long	0xff00001c
 CCR_D:		.long	0x0000090b

board/renesas/sh7785lcr/sh7785lcr.c

@@ -54,3 +54,34 @@ int board_eth_init(bd_t *bis)
 {
 	return pci_eth_init(bis);
 }
+
+#if defined(CONFIG_SH_32BIT)
+int do_pmb(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	/* clear ITLB */
+	writel(0x00000004, 0xff000010);
+
+	/* delete PMB for peripheral */
+	writel(0, PMB_ADDR_BASE(0));
+	writel(0, PMB_DATA_BASE(0));
+	writel(0, PMB_ADDR_BASE(1));
+	writel(0, PMB_DATA_BASE(1));
+	writel(0, PMB_ADDR_BASE(2));
+	writel(0, PMB_DATA_BASE(2));
+
+	/* add PMB for SDRAM(0x40000000 - 0x47ffffff) */
+	writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(8));
+	writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(8));
+	writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(12));
+	writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(12));
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	pmb,	1,	1,	do_pmb,
+	"pmb     - PMB setting\n",
+	"\n"
+	"    - PMB setting for all SDRAM mapping\n"
+);
+#endif

board/renesas/sh7785lcr/u-boot.lds

@@ -1,7 +1,7 @@
 /*
  * Copyrigth (c) 2007
  * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- * Copyrigth (c) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+ * Copyrigth (c) 2008-2009 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -28,7 +28,7 @@ ENTRY(_start)
 
 SECTIONS
 {
-	. = 0x08000000 + (128 * 1024 * 1024) - (512 * 1024);
+	. = 0x88000000 + (128 * 1024 * 1024) - (512 * 1024);
 
 	PROVIDE (reloc_dst = .);
 

board/renesas/sh7785lcr/u-boot_29bit

@@ -0,0 +1,96 @@
+/*
+ * Copyrigth (c) 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ * Copyrigth (c) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
+OUTPUT_ARCH(sh)
+ENTRY(_start)
+
+SECTIONS
+{
+	. = 0x08000000 + (128 * 1024 * 1024) - (512 * 1024);
+
+	PROVIDE (reloc_dst = .);
+
+	PROVIDE (_ftext = .);
+	PROVIDE (_fcode = .);
+	PROVIDE (_start = .);
+
+	.text :
+	{
+		cpu/sh4/start.o		(.text)
+		. = ALIGN(8192);
+		common/env_embedded.o	(.ppcenv)
+		. = ALIGN(8192);
+		common/env_embedded.o	(.ppcenvr)
+		. = ALIGN(8192);
+		*(.text)
+		. = ALIGN(4);
+	} =0xFF
+	PROVIDE (_ecode = .);
+	.rodata :
+	{
+		*(.rodata)
+		. = ALIGN(4);
+	}
+	PROVIDE (_etext = .);
+
+
+	PROVIDE (_fdata = .);
+	.data :
+	{
+		*(.data)
+		. = ALIGN(4);
+	}
+	PROVIDE (_edata = .);
+
+	PROVIDE (_fgot = .);
+	.got :
+	{
+		*(.got)
+		. = ALIGN(4);
+	}
+	PROVIDE (_egot = .);
+
+	PROVIDE (__u_boot_cmd_start = .);
+	.u_boot_cmd :
+	{
+		*(.u_boot_cmd)
+		. = ALIGN(4);
+	}
+	PROVIDE (__u_boot_cmd_end = .);
+
+	PROVIDE (reloc_dst_end = .);
+	/* _reloc_dst_end = .; */
+
+	PROVIDE (bss_start = .);
+	PROVIDE (__bss_start = .);
+	.bss :
+	{
+		*(.bss)
+		. = ALIGN(4);
+	}
+	PROVIDE (bss_end = .);
+
+	PROVIDE (_end = .);
+}

board/renesas/sh7785lcr/u-boot_32bit

@@ -0,0 +1,96 @@
+/*
+ * Copyrigth (c) 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ * Copyrigth (c) 2008-2009 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
+OUTPUT_ARCH(sh)
+ENTRY(_start)
+
+SECTIONS
+{
+	. = 0x88000000 + (128 * 1024 * 1024) - (512 * 1024);
+
+	PROVIDE (reloc_dst = .);
+
+	PROVIDE (_ftext = .);
+	PROVIDE (_fcode = .);
+	PROVIDE (_start = .);
+
+	.text :
+	{
+		cpu/sh4/start.o		(.text)
+		. = ALIGN(8192);
+		common/env_embedded.o	(.ppcenv)
+		. = ALIGN(8192);
+		common/env_embedded.o	(.ppcenvr)
+		. = ALIGN(8192);
+		*(.text)
+		. = ALIGN(4);
+	} =0xFF
+	PROVIDE (_ecode = .);
+	.rodata :
+	{
+		*(.rodata)
+		. = ALIGN(4);
+	}
+	PROVIDE (_etext = .);
+
+
+	PROVIDE (_fdata = .);
+	.data :
+	{
+		*(.data)
+		. = ALIGN(4);
+	}
+	PROVIDE (_edata = .);
+
+	PROVIDE (_fgot = .);
+	.got :
+	{
+		*(.got)
+		. = ALIGN(4);
+	}
+	PROVIDE (_egot = .);
+
+	PROVIDE (__u_boot_cmd_start = .);
+	.u_boot_cmd :
+	{
+		*(.u_boot_cmd)
+		. = ALIGN(4);
+	}
+	PROVIDE (__u_boot_cmd_end = .);
+
+	PROVIDE (reloc_dst_end = .);
+	/* _reloc_dst_end = .; */
+
+	PROVIDE (bss_start = .);
+	PROVIDE (__bss_start = .);
+	.bss :
+	{
+		*(.bss)
+		. = ALIGN(4);
+	}
+	PROVIDE (bss_end = .);
+
+	PROVIDE (_end = .);
+}

common/cmd_nand.c

@@ -502,7 +502,7 @@ static int nand_load_image(cmd_tbl_t *cmdtp, nand_info_t *nand,
 
 	s = strchr(cmd, '.');
 	if (s != NULL &&
-	    (strcmp(s, ".jffs2") && !strcmp(s, ".e") && !strcmp(s, ".i"))) {
+	    (strcmp(s, ".jffs2") && strcmp(s, ".e") && strcmp(s, ".i"))) {
 		printf("Unknown nand load suffix '%s'\n", s);
 		show_boot_progress(-53);
 		return 1;
@@ -511,7 +511,7 @@ static int nand_load_image(cmd_tbl_t *cmdtp, nand_info_t *nand,
 	printf("\nLoading from %s, offset 0x%lx\n", nand->name, offset);
 
 	cnt = nand->writesize;
-	r = nand_read(nand, offset, &cnt, (u_char *) addr);
+	r = nand_read_skip_bad(nand, offset, &cnt, (u_char *) addr);
 	if (r) {
 		puts("** Read error\n");
 		show_boot_progress (-56);
@@ -543,8 +543,7 @@ static int nand_load_image(cmd_tbl_t *cmdtp, nand_info_t *nand,
 	}
 	show_boot_progress (57);
 
-	/* FIXME: skip bad blocks */
-	r = nand_read(nand, offset, &cnt, (u_char *) addr);
+	r = nand_read_skip_bad(nand, offset, &cnt, (u_char *) addr);
 	if (r) {
 		puts("** Read error\n");
 		show_boot_progress (-58);

common/cmd_nvedit.c

@@ -75,7 +75,12 @@ DECLARE_GLOBAL_DATA_PTR;
 static const unsigned long baudrate_table[] = CONFIG_SYS_BAUDRATE_TABLE;
 #define	N_BAUDRATES (sizeof(baudrate_table) / sizeof(baudrate_table[0]))
 
+static int env_id = 1;
 
+int get_env_id (void)
+{
+	return env_id;
+}
 /************************************************************************
  * Command interface: print one or all environment variables
  */
@@ -160,6 +165,7 @@ int _do_setenv (int flag, int argc, char *argv[])
 		return 1;
 	}
 
+	env_id++;
 	/*
 	 * search if variable with this name already exists
 	 */

common/lcd.c

@@ -84,7 +84,7 @@ extern void lcd_enable (void);
 static void *lcd_logo (void);
 
 
-#if LCD_BPP == LCD_COLOR8
+#if (LCD_BPP == LCD_COLOR8) || (LCD_BPP == LCD_COLOR16)
 extern void lcd_setcolreg (ushort regno,
 				ushort red, ushort green, ushort blue);
 #endif
@@ -622,19 +622,18 @@ void bitmap_plot (int x, int y)
  */
 int lcd_display_bitmap(ulong bmp_image, int x, int y)
 {
-#ifdef CONFIG_ATMEL_LCD
-	uint *cmap;
-#elif !defined(CONFIG_MCC200)
-	ushort *cmap;
+#if !defined(CONFIG_MCC200)
+	ushort *cmap = NULL;
 #endif
+	ushort *cmap_base = NULL;
 	ushort i, j;
 	uchar *fb;
 	bmp_image_t *bmp=(bmp_image_t *)bmp_image;
 	uchar *bmap;
 	ushort padded_line;
-	unsigned long width, height;
+	unsigned long width, height, byte_width;
 	unsigned long pwidth = panel_info.vl_col;
-	unsigned colors,bpix;
+	unsigned colors, bpix, bmp_bpix;
 	unsigned long compression;
 #if defined(CONFIG_PXA250)
 	struct pxafb_info *fbi = &panel_info.pxa;
@@ -647,22 +646,24 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
 		(bmp->header.signature[1]=='M'))) {
 		printf ("Error: no valid bmp image at %lx\n", bmp_image);
 		return 1;
-}
+	}
 
 	width = le32_to_cpu (bmp->header.width);
 	height = le32_to_cpu (bmp->header.height);
-	colors = 1<<le16_to_cpu (bmp->header.bit_count);
+	bmp_bpix = le16_to_cpu(bmp->header.bit_count);
+	colors = 1 << bmp_bpix;
 	compression = le32_to_cpu (bmp->header.compression);
 
 	bpix = NBITS(panel_info.vl_bpix);
 
-	if ((bpix != 1) && (bpix != 8)) {
-		printf ("Error: %d bit/pixel mode not supported by U-Boot\n",
-			bpix);
+	if ((bpix != 1) && (bpix != 8) && (bpix != 16)) {
+		printf ("Error: %d bit/pixel mode, but BMP has %d bit/pixel\n",
+			bpix, bmp_bpix);
 		return 1;
 	}
 
-	if (bpix != le16_to_cpu(bmp->header.bit_count)) {
+	/* We support displaying 8bpp BMPs on 16bpp LCDs */
+	if (bpix != bmp_bpix && (bmp_bpix != 8 || bpix != 16)) {
 		printf ("Error: %d bit/pixel mode, but BMP has %d bit/pixel\n",
 			bpix,
 			le16_to_cpu(bmp->header.bit_count));
@@ -674,17 +675,17 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
 
 #if !defined(CONFIG_MCC200)
 	/* MCC200 LCD doesn't need CMAP, supports 1bpp b&w only */
-	if (bpix==8) {
+	if (bmp_bpix == 8) {
 #if defined(CONFIG_PXA250)
 		cmap = (ushort *)fbi->palette;
 #elif defined(CONFIG_MPC823)
 		cmap = (ushort *)&(cp->lcd_cmap[255*sizeof(ushort)]);
-#elif defined(CONFIG_ATMEL_LCD)
-		cmap = (uint *) (panel_info.mmio + ATMEL_LCDC_LUT(0));
-#else
-# error "Don't know location of color map"
+#elif !defined(CONFIG_ATMEL_LCD)
+		cmap = panel_info.cmap;
 #endif
 
+		cmap_base = cmap;
+
 		/* Set color map */
 		for (i=0; i<colors; ++i) {
 			bmp_color_table_entry_t cte = bmp->color_table[i];
@@ -698,10 +699,10 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
 #else
 			*cmap = colreg;
 #endif
-#if defined(CONFIG_PXA250)
-			cmap++;
-#elif defined(CONFIG_MPC823)
+#if defined(CONFIG_MPC823)
 			cmap--;
+#else
+			cmap++;
 #endif
 #else /* CONFIG_ATMEL_LCD */
 			lcd_setcolreg(i, cte.red, cte.green, cte.blue);
@@ -738,17 +739,59 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
 	bmap = (uchar *)bmp + le32_to_cpu (bmp->header.data_offset);
 	fb   = (uchar *) (lcd_base +
 		(y + height - 1) * lcd_line_length + x);
-	for (i = 0; i < height; ++i) {
-		WATCHDOG_RESET();
-		for (j = 0; j < width ; j++)
+
+	switch (bmp_bpix) {
+	case 1: /* pass through */
+	case 8:
+		if (bpix != 16)
+			byte_width = width;
+		else
+			byte_width = width * 2;
+
+		for (i = 0; i < height; ++i) {
+			WATCHDOG_RESET();
+			for (j = 0; j < width; j++) {
+				if (bpix != 16) {
 #if defined(CONFIG_PXA250) || defined(CONFIG_ATMEL_LCD)
-			*(fb++) = *(bmap++);
+					*(fb++) = *(bmap++);
 #elif defined(CONFIG_MPC823) || defined(CONFIG_MCC200)
-			*(fb++)=255-*(bmap++);
+					*(fb++) = 255 - *(bmap++);
 #endif
-		bmap += (width - padded_line);
-		fb   -= (width + lcd_line_length);
-	}
+				} else {
+					*(uint16_t *)fb = cmap_base[*(bmap++)];
+					fb += sizeof(uint16_t) / sizeof(*fb);
+				}
+			}
+			bmap += (width - padded_line);
+			fb   -= (byte_width + lcd_line_length);
+		}
+		break;
+
+#if defined(CONFIG_BMP_16BPP)
+	case 16:
+		for (i = 0; i < height; ++i) {
+			WATCHDOG_RESET();
+			for (j = 0; j < width; j++) {
+#if defined(CONFIG_ATMEL_LCD_BGR555)
+				*(fb++) = ((bmap[0] & 0x1f) << 2) |
+					(bmap[1] & 0x03);
+				*(fb++) = (bmap[0] & 0xe0) |
+					((bmap[1] & 0x7c) >> 2);
+				bmap += 2;
+#else
+				*(fb++) = *(bmap++);
+				*(fb++) = *(bmap++);
+#endif
+			}
+			bmap += (padded_line - width) * 2;
+			fb   -= (width * 2 + lcd_line_length);
+		}
+		break;
+#endif /* CONFIG_BMP_16BPP */
+
+	default:
+		break;
+	};
 
 	return (0);
 }

cpu/arm_cortexa8/omap3/sys_info.c

@@ -36,6 +36,32 @@ static gpmc_csx_t *gpmc_cs_base = (gpmc_csx_t *)GPMC_CONFIG_CS0_BASE;
 static sdrc_t *sdrc_base = (sdrc_t *)OMAP34XX_SDRC_BASE;
 static ctrl_t *ctrl_base = (ctrl_t *)OMAP34XX_CTRL_BASE;
 
+/*****************************************************************
+ * dieid_num_r(void) - read and set die ID
+ *****************************************************************/
+void dieid_num_r(void)
+{
+	ctrl_id_t *id_base = (ctrl_id_t *)OMAP34XX_ID_L4_IO_BASE;
+	char *uid_s, die_id[34];
+	u32 id[4];
+
+	memset(die_id, 0, sizeof(die_id));
+
+	uid_s = getenv("dieid#");
+
+	if (uid_s == NULL) {
+		id[3] = readl(&id_base->die_id_0);
+		id[2] = readl(&id_base->die_id_1);
+		id[1] = readl(&id_base->die_id_2);
+		id[0] = readl(&id_base->die_id_3);
+		sprintf(die_id, "%08x%08x%08x%08x", id[0], id[1], id[2], id[3]);
+		setenv("dieid#", die_id);
+		uid_s = die_id;
+	}
+
+	printf("Die ID #%s\n", uid_s);
+}
+
 /******************************************
  * get_cpu_type(void) - extract cpu info
  ******************************************/

cpu/i386/Makefile

@@ -29,8 +29,7 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(CPU).a
 
 START	= start.o start16.o resetvec.o
-COBJS	= serial.o interrupts.o cpu.o timer.o sc520.o
-SOBJS	= sc520_asm.o
+COBJS	= serial.o interrupts.o cpu.o timer.o
 
 SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))

cpu/i386/sc520/Makefile

@@ -0,0 +1,52 @@
+#
+# (C) Copyright 2008
+# Graeme Russ, graeme.russ@gmail.com.
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2002
+# Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	:= $(obj)lib$(SOC).a
+
+COBJS-$(CONFIG_SYS_SC520) += sc520.o
+SOBJS-$(CONFIG_SYS_SC520) += sc520_asm.o
+
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
+
+all: $(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

cpu/i386/sc520/sc520_asm.S

@@ -105,7 +105,6 @@
  */
 
 #include <config.h>
-#ifdef CONFIG_SC520
 
 .section .text
 .equ            DRCCTL,     0x0fffef010   /* DRAM control register */
@@ -580,5 +579,3 @@ set_ecc:
 out:
 	movl	%ebx, %eax
 	jmp	*%ebp
-
-#endif /* CONFIG_SC520 */

cpu/mcf5227x/config.mk

@@ -24,8 +24,8 @@
 #
 
 PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
-ifeq ($(findstring 4.2,$(shell $(CC) --version)),4.2)
-PLATFORM_CPPFLAGS += -mcpu=5208 -fPIC
+ifneq ($(findstring 4.1,$(shell $(CC) --version)),4.1)
+PLATFORM_CPPFLAGS += -mcpu=52277 -fPIC
 else
 PLATFORM_CPPFLAGS += -m5307 -fPIC
 endif

cpu/mcf523x/config.mk

@@ -24,7 +24,7 @@
 #
 
 PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
-ifeq ($(findstring 4.2,$(shell $(CC) --version)),4.2)
+ifneq ($(findstring 4.1,$(shell $(CC) --version)),4.1)
 PLATFORM_CPPFLAGS += -mcpu=5235 -fPIC
 else
 PLATFORM_CPPFLAGS += -m5307 -fPIC

cpu/mcf52x2/config.mk

@@ -34,7 +34,7 @@ is5275:=$(shell grep CONFIG_M5275 $(TOPDIR)/include/$(cfg))
 is5282:=$(shell grep CONFIG_M5282 $(TOPDIR)/include/$(cfg))
 
 
-ifeq ($(findstring 4.2,$(shell $(CC) --version)),4.2)
+ifneq ($(findstring 4.1,$(shell $(CC) --version)),4.1)
 
 ifneq (,$(findstring CONFIG_M5249,$(is5249)))
 PLATFORM_CPPFLAGS += -mcpu=5249

cpu/mcf532x/config.mk

@@ -24,7 +24,7 @@
 #
 
 PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
-ifeq ($(findstring 4.2,$(shell $(CC) --version)),4.2)
+ifneq ($(findstring 4.1,$(shell $(CC) --version)),4.1)
 PLATFORM_CPPFLAGS += -mcpu=5329 -fPIC
 else
 PLATFORM_CPPFLAGS += -m5307 -fPIC

cpu/mcf5445x/config.mk

@@ -24,7 +24,7 @@
 #
 
 PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
-ifeq ($(findstring 4.2,$(shell $(CC) --version)),4.2)
+ifneq ($(findstring 4.1,$(shell $(CC) --version)),4.1)
 PLATFORM_CPPFLAGS += -mcpu=54455 -fPIC
 else
 PLATFORM_CPPFLAGS += -m5407 -fPIC

cpu/mcf5445x/start.S

@@ -243,9 +243,9 @@ wait1000:
 	nop
 #elif defined(CONFIG_M54451EVB)
 	/* Issue LEMR */
-	move.l	#(CONFIG_SYS_SDRAM_MODE), (%a2)
+	move.l	#(CONFIG_SYS_SDRAM_MODE), (%a1)
 	nop
-	move.l	#(CONFIG_SYS_SDRAM_EMOD), (%a2)
+	move.l	#(CONFIG_SYS_SDRAM_EMOD), (%a1)
 	nop
 #endif
 

cpu/mcf547x_8x/config.mk

@@ -24,7 +24,7 @@
 #
 
 PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
-ifeq ($(findstring 4.2,$(shell $(CC) --version)),4.2)
+ifneq ($(findstring 4.1,$(shell $(CC) --version)),4.1)
 PLATFORM_CPPFLAGS += -mcpu=5485 -fPIC
 else
 PLATFORM_CPPFLAGS += -m5407 -fPIC

cpu/mcf547x_8x/cpu_init.c

@@ -49,14 +49,14 @@ void cpu_init_f(void)
 	volatile xlbarb_t *xlbarb = (volatile xlbarb_t *) MMAP_XARB;
 
 	xlbarb->adrto = 0x2000;
-	xlbarb->datto = 0x2000;
+	xlbarb->datto = 0x2500;
 	xlbarb->busto = 0x3000;
 
-	xlbarb->cfg = XARB_SR_AT | XARB_SR_DT;
+	xlbarb->cfg = XARB_CFG_AT | XARB_CFG_DT;
 
 	/* Master Priority Enable */
-	xlbarb->pri = 0;
 	xlbarb->prien = 0xff;
+	xlbarb->pri = 0;
 
 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
 	fbcs->csar0 = CONFIG_SYS_CS0_BASE;

cpu/mpc5xxx/ide.c

@@ -42,7 +42,7 @@ int ide_preinit (void)
 	struct mpc5xxx_sdma *psdma = (struct mpc5xxx_sdma *) MPC5XXX_SDMA;
 
 	reg = *(vu_long *) MPC5XXX_GPS_PORT_CONFIG;
-#if defined(CONFIG_TOTAL5200)
+#if defined(CONFIG_SYS_ATA_CS_ON_I2C2)
 	/* ATA cs0/1 on i2c2 clk/io */
 	reg = (reg & ~0x03000000ul) | 0x02000000ul;
 #else

cpu/mpc83xx/cpu.c

@@ -35,6 +35,10 @@
 #include <tsec.h>
 #include <netdev.h>
 #include <fsl_esdhc.h>
+#ifdef CONFIG_BOOTCOUNT_LIMIT
+#include <asm/immap_qe.h>
+#include <asm/io.h>
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -399,3 +403,33 @@ int cpu_mmc_init(bd_t *bis)
 	return 0;
 #endif
 }
+
+#ifdef CONFIG_BOOTCOUNT_LIMIT
+
+#if !defined(CONFIG_MPC8360)
+#error "CONFIG_BOOTCOUNT_LIMIT only for MPC8360 implemented"
+#endif
+
+#if !defined(CONFIG_BOOTCOUNT_ADDR)
+#define CONFIG_BOOTCOUNT_ADDR	(0x110000 + QE_MURAM_SIZE - 2 * sizeof(unsigned long))
+#endif
+
+#include <asm/io.h>
+
+void bootcount_store (ulong a)
+{
+	void *reg = (void *)(CONFIG_SYS_IMMR + CONFIG_BOOTCOUNT_ADDR);
+	out_be32 (reg, a);
+	out_be32 (reg + 4, BOOTCOUNT_MAGIC);
+}
+
+ulong bootcount_load (void)
+{
+	void *reg = (void *)(CONFIG_SYS_IMMR + CONFIG_BOOTCOUNT_ADDR);
+
+	if (in_be32 (reg + 4) != BOOTCOUNT_MAGIC)
+		return 0;
+	else
+		return in_be32 (reg);
+}
+#endif /* CONFIG_BOOTCOUNT_LIMIT */

cpu/mpc83xx/cpu_init.c

@@ -106,7 +106,7 @@ void cpu_init_f (volatile immap_t * im)
 #ifdef CONFIG_SYS_SCCR_ENCCM
 	/* Encryption clock mode */
 	im->clk.sccr = (im->clk.sccr & ~SCCR_ENCCM) |
-		       (CONFIG_SYS_SCCR_ENCCM << SCCR_PCICM_SHIFT);
+		       (CONFIG_SYS_SCCR_ENCCM << SCCR_ENCCM_SHIFT);
 #endif
 
 #ifdef CONFIG_SYS_SCCR_PCICM

cpu/mpc83xx/fdt.c

@@ -32,6 +32,20 @@ extern void ft_qe_setup(void *blob);
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if defined(CONFIG_BOOTCOUNT_LIMIT) && defined(CONFIG_MPC8360)
+#include <asm/immap_qe.h>
+
+void fdt_fixup_muram (void *blob)
+{
+	ulong data[2];
+
+	data[0] = 0;
+	data[1] = QE_MURAM_SIZE - 2 * sizeof(unsigned long);
+	do_fixup_by_path(blob, "/qe/muram/data-only", "reg",
+		      data, sizeof (data), 0);
+}
+#endif
+
 void ft_cpu_setup(void *blob, bd_t *bd)
 {
 	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
@@ -83,4 +97,8 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 #endif
 
 	fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
+
+#if defined(CONFIG_BOOTCOUNT_LIMIT)
+	fdt_fixup_muram (blob);
+#endif
 }

cpu/mpc83xx/pci.c

@@ -91,7 +91,7 @@ static void pci_init_bus(int bus, struct pci_region *reg)
 	hose->regions[i].size = gd->ram_size;
 	hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_SYS_MEMORY;
 
-	hose->first_busno = 0;
+	hose->first_busno = pci_last_busno() + 1;
 	hose->last_busno = 0xff;
 
 	pci_setup_indirect(hose, CONFIG_SYS_IMMR + 0x8300 + bus * 0x80,
@@ -227,8 +227,8 @@ void ft_pci_setup(void *blob, bd_t *bd)
 
 		path = fdt_getprop(blob, nodeoffset, "pci1", NULL);
 		if (path) {
-			tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
-			tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
+			tmp[0] = cpu_to_be32(pci_hose[1].first_busno);
+			tmp[1] = cpu_to_be32(pci_hose[1].last_busno);
 			do_fixup_by_path(blob, path, "bus-range",
 				&tmp, sizeof(tmp), 1);
 

cpu/mpc83xx/pcie.c

@@ -60,6 +60,9 @@ static int mpc83xx_pcie_remap_cfg(struct pci_controller *hose, pci_dev_t dev)
 #define cfg_write(val, addr, type, op) \
 	do { op((type *)(addr), (val)); } while (0)
 
+#define cfg_read_err(val) do { *val = -1; } while (0)
+#define cfg_write_err(val) do { } while (0)
+
 #define PCIE_OP(rw, size, type, op)					\
 static int pcie_##rw##_config_##size(struct pci_controller *hose,	\
 				     pci_dev_t dev, int offset,		\
@@ -68,8 +71,10 @@ static int pcie_##rw##_config_##size(struct pci_controller *hose,	\
 	int ret;							\
 									\
 	ret = mpc83xx_pcie_remap_cfg(hose, dev);			\
-	if (ret)							\
-		return ret;						\
+	if (ret) {							\
+		cfg_##rw##_err(val); 					\
+		return ret; 						\
+	}								\
 	cfg_##rw(val, (void *)hose->cfg_addr + offset, type, op);	\
 	return 0;							\
 }
@@ -86,7 +91,6 @@ static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg,
 {
 	extern void disable_addr_trans(void); /* start.S */
 	static struct pci_controller pcie_hose[PCIE_MAX_BUSES];
-	static int max_bus;
 	struct pci_controller *hose = &pcie_hose[bus];
 	int i;
 
@@ -117,7 +121,7 @@ static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg,
 	hose->regions[i].size = 0x100000;
 	hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_SYS_MEMORY;
 
-	hose->first_busno = max_bus;
+	hose->first_busno = pci_last_busno() + 1;
 	hose->last_busno = 0xff;
 
 	if (bus == 0)
@@ -145,7 +149,6 @@ static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg,
 	 * Hose scan.
 	 */
 	hose->last_busno = pci_hose_scan(hose);
-	max_bus = hose->last_busno + 1;
 }
 
 #else

cpu/mpc83xx/spd_sdram.c

@@ -219,7 +219,8 @@ long int spd_sdram()
 	ddr->cs_config[0] = ( 1 << 31
 			    | (odt_rd_cfg << 20)
 			    | (odt_wr_cfg << 16)
-			    | (spd.nrow_addr - 12) << 8
+			    | ((spd.nbanks == 8 ? 1 : 0) << 14)
+			    | ((spd.nrow_addr - 12) << 8)
 			    | (spd.ncol_addr - 8) );
 	debug("\n");
 	debug("cs0_bnds = 0x%08x\n",ddr->csbnds[0].csbnds);
@@ -231,8 +232,9 @@ long int spd_sdram()
 		ddr->cs_config[1] = ( 1<<31
 				    | (odt_rd_cfg << 20)
 				    | (odt_wr_cfg << 16)
-				    | (spd.nrow_addr-12) << 8
-				    | (spd.ncol_addr-8) );
+				    | ((spd.nbanks == 8 ? 1 : 0) << 14)
+				    | ((spd.nrow_addr - 12) << 8)
+				    | (spd.ncol_addr - 8) );
 		debug("cs1_bnds = 0x%08x\n",ddr->csbnds[1].csbnds);
 		debug("cs1_config = 0x%08x\n",ddr->cs_config[1]);
 	}
@@ -242,7 +244,8 @@ long int spd_sdram()
 	ddr->cs_config[2] = ( 1 << 31
 			    | (odt_rd_cfg << 20)
 			    | (odt_wr_cfg << 16)
-			    | (spd.nrow_addr - 12) << 8
+			    | ((spd.nbanks == 8 ? 1 : 0) << 14)
+			    | ((spd.nrow_addr - 12) << 8)
 			    | (spd.ncol_addr - 8) );
 	debug("\n");
 	debug("cs2_bnds = 0x%08x\n",ddr->csbnds[2].csbnds);
@@ -254,8 +257,9 @@ long int spd_sdram()
 		ddr->cs_config[3] = ( 1<<31
 				    | (odt_rd_cfg << 20)
 				    | (odt_wr_cfg << 16)
-				    | (spd.nrow_addr-12) << 8
-				    | (spd.ncol_addr-8) );
+				    | ((spd.nbanks == 8 ? 1 : 0) << 14)
+				    | ((spd.nrow_addr - 12) << 8)
+				    | (spd.ncol_addr - 8) );
 		debug("cs3_bnds = 0x%08x\n",ddr->csbnds[3].csbnds);
 		debug("cs3_config = 0x%08x\n",ddr->cs_config[3]);
 	}
@@ -319,7 +323,20 @@ long int spd_sdram()
 	ddrc_clk = gd->mem_clk / 1000000;
 	effective_data_rate = 0;
 
-	if (max_data_rate >= 390 && max_data_rate < 460) { /* it is DDR 400 */
+	if (max_data_rate >= 460) { /* it is DDR2-800, 667, 533 */
+		if (spd.cas_lat & 0x08)
+			caslat = 3;
+		else
+			caslat = 4;
+		if (ddrc_clk <= 460 && ddrc_clk > 350)
+			effective_data_rate = 400;
+		else if (ddrc_clk <=350 && ddrc_clk > 280)
+			effective_data_rate = 333;
+		else if (ddrc_clk <= 280 && ddrc_clk > 230)
+			effective_data_rate = 266;
+		else
+			effective_data_rate = 200;
+	} else if (max_data_rate >= 390 && max_data_rate < 460) { /* it is DDR 400 */
 		if (ddrc_clk <= 460 && ddrc_clk > 350) {
 			/* DDR controller clk at 350~460 */
 			effective_data_rate = 400; /* 5ns */
@@ -466,6 +483,8 @@ long int spd_sdram()
 	} else {
 		twr_clk = picos_to_clk(spd.twr * 250);
 		twtr_clk = picos_to_clk(spd.twtr * 250);
+		if (twtr_clk < 2)
+			twtr_clk = 2;
 	}
 
 	/*
@@ -529,7 +548,7 @@ long int spd_sdram()
 	if (spd.mem_type == SPD_MEMTYPE_DDR2
 	    && (odt_wr_cfg || odt_rd_cfg)
 	    && (caslat < 4)) {
-		add_lat = trcd_clk - 1;
+		add_lat = 4 - caslat;
 		if ((add_lat + caslat) < 4) {
 			add_lat = 0;
 		}
@@ -566,6 +585,9 @@ long int spd_sdram()
 
 		/* Convert SPD value from quarter nanos to picos. */
 		trtp_clk = picos_to_clk(spd.trtp * 250);
+		if (trtp_clk < 2)
+			trtp_clk = 2;
+		trtp_clk += add_lat;
 
 		cke_min_clk = 3;	/* By the book. */
 		four_act = picos_to_clk(37500);	/* By the book. 1k pages? */
@@ -579,7 +601,9 @@ long int spd_sdram()
 	if (spd.mem_type == SPD_MEMTYPE_DDR2) {
 		if (effective_data_rate == 266) {
 			cpo = 0x4;		/* READ_LAT + 1/2 */
-		} else if (effective_data_rate == 333 || effective_data_rate == 400) {
+		} else if (effective_data_rate == 333) {
+			cpo = 0x6;		/* READ_LAT + 1 */
+		} else if (effective_data_rate == 400) {
 			cpo = 0x7;		/* READ_LAT + 5/4 */
 		} else {
 			/* Automatic calibration */

cpu/mpc85xx/ddr-gen3.c

@@ -79,8 +79,8 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 	out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
 	out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
 
-	/* Do not enable the memory */
-	temp_sdram_cfg = in_be32(&ddr->sdram_cfg);
+	/* Set, but do not enable the memory */
+	temp_sdram_cfg = regs->ddr_sdram_cfg;
 	temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);
 	out_be32(&ddr->sdram_cfg, temp_sdram_cfg);
 	/*

cpu/mpc8xx/start.S

@@ -142,7 +142,7 @@ boot_warm:
 	lis	r3, IDC_DISABLE@h	/* Disable data cache */
 	mtspr	DC_CST, r3
 
-#if !(defined(CONFIG_IP860) || defined(CONFIG_PCU_E) || defined (CONFIG_FLAGADM))
+#if !defined(CONFIG_SYS_DELAYED_ICACHE)
 					/* On IP860 and PCU E,
 					 * we cannot enable IC yet
 					 */

cpu/ppc4xx/4xx_pci.c

@@ -550,10 +550,12 @@ int pci_440_init (struct pci_controller *hose)
 	out32r( PCIX0_POM0SA, 0 ); /* disable */
 	out32r( PCIX0_POM1SA, 0 ); /* disable */
 	out32r( PCIX0_POM2SA, 0 ); /* disable */
-#if defined(CONFIG_440SPE) || \
-    defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#if defined(CONFIG_440SPE)
 	out32r( PCIX0_POM0LAL, 0x10000000 );
 	out32r( PCIX0_POM0LAH, 0x0000000c );
+#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
+	out32r( PCIX0_POM0LAL, 0x20000000 );
+	out32r( PCIX0_POM0LAH, 0x0000000c );
 #else
 	out32r( PCIX0_POM0LAL, 0x00000000 );
 	out32r( PCIX0_POM0LAH, 0x00000003 );

cpu/pxa/interrupts.c

@@ -28,6 +28,7 @@
 
 #include <common.h>
 #include <asm/arch/pxa-regs.h>
+#include <div64.h>
 
 #ifdef CONFIG_USE_IRQ
 #error: interrupts not implemented yet
@@ -41,6 +42,20 @@
 #error "Timer frequency unknown - please config PXA CPU type"
 #endif
 
+static inline unsigned long long tick_to_time(unsigned long long tick)
+{
+	tick *= CONFIG_SYS_HZ;
+	do_div(tick, TIMER_FREQ_HZ);
+	return tick;
+}
+
+static inline unsigned long long us_to_tick(unsigned long long us)
+{
+	us = us * TIMER_FREQ_HZ + 999999;
+	do_div(us, 1000000);
+	return us;
+}
+
 int interrupt_init (void)
 {
 	/* nothing happens here - we don't setup any IRQs */
@@ -75,33 +90,20 @@ void reset_timer_masked (void)
 
 ulong get_timer_masked (void)
 {
-	unsigned long long ticks = get_ticks();
-
-	return (((ticks / TIMER_FREQ_HZ) * 1000) +
-	        ((ticks % TIMER_FREQ_HZ) * 1000) / TIMER_FREQ_HZ);
+	return tick_to_time(get_ticks());
 }
 
 void udelay_masked (unsigned long usec)
 {
+	unsigned long long tmp;
 	ulong tmo;
-	ulong endtime;
-	signed long diff;
 
-	if (usec >= 1000) {
-		tmo = usec / 1000;
-		tmo *= TIMER_FREQ_HZ;
-		tmo /= 1000;
-	} else {
-		tmo = usec * TIMER_FREQ_HZ;
-		tmo /= (1000*1000);
-	}
+	tmo = us_to_tick(usec);
+	tmp = get_ticks() + tmo;	/* get current timestamp */
 
-	endtime = get_ticks() + tmo;
+	while (get_ticks() < tmp)	/* loop till event */
+		 /*NOP*/;
 
-	do {
-		ulong now = get_ticks();
-		diff = endtime - now;
-	} while (diff >= 0);
 }
 
 /*

cpu/sh4/cpu.c

@@ -23,6 +23,7 @@
 
 #include <common.h>
 #include <command.h>
+#include <netdev.h>
 #include <asm/processor.h>
 #include <asm/cache.h>
 

doc/README.sh7785lcr

@@ -33,6 +33,38 @@ This board has 2 physical memory maps. It can be changed with DIP switch(S2-5).
  0x40000000 - 0x5fffffff	| DDR SDRAM	| (cannot use)
 
 
+configuration for This board:
+=============================
+
+You can choose configuration as follows:
+
+ - make sh7785lcr_config
+ - make sh7785lcr_32bit_config
+
+When you use "make sh7785lcr_config", there is build U-Boot for 29-bit
+address mode. This mode can use 128MB DDR-SDRAM.
+
+When you use "make sh7785lcr_32bit_config", there is build U-Boot for 32-bit
+extended address mode. This mode can use 384MB DDR-SDRAM. And if you run
+"pmb" command, this mode can use 512MB DDR-SDRAM.
+
+ * 32-bit extended address mode PMB mapping *
+  a) on start-up
+   virt		| phys		| size		| device
+   -------------+---------------+---------------+---------------
+   0x88000000	| 0x48000000	| 384MB		| DDR-SDRAM (Cacheable)
+   0xa0000000	| 0x00000000	| 64MB		| NOR Flash
+   0xa4000000	| 0x04000000	| 16MB		| PLD
+   0xa6000000	| 0x08000000	| 16MB		| USB
+   0xa8000000	| 0x48000000	| 384MB		| DDR-SDRAM (Non-cacheable)
+
+  b) after "pmb" command
+   virt		| phys		| size		| device
+   -------------+---------------+---------------+---------------
+   0x80000000	| 0x40000000	| 512MB		| DDR-SDRAM (Cacheable)
+   0xa0000000	| 0x40000000	| 512MB		| DDR-SDRAM (Non-cacheable)
+
+
 This board specific command:
 ============================
 
@@ -41,6 +73,7 @@ This board has the following its specific command:
  - hwtest
  - printmac
  - setmac
+ - pmb (sh7785lcr_32bit_config only)
 
 
 1. hwtest
@@ -80,3 +113,11 @@ This command writes MAC address of this board.
 
 i.e)
 => setmac 00:00:87:**:**:**
+
+
+4. pmb
+
+This command change PMB for DDR-SDRAM all mapping. However you cannot use
+NOR Flash and USB Host on U-Boot when you run this command.
+i.e)
+=> pmb

drivers/gpio/Makefile

@@ -25,7 +25,8 @@ include $(TOPDIR)/config.mk
 
 LIB 	:= $(obj)libgpio.a
 
-COBJS-$(CONFIG_PCA953X)	+= pca953x.o
+COBJS-$(CONFIG_MX31_GPIO)	+= mx31_gpio.o
+COBJS-$(CONFIG_PCA953X)		+= pca953x.o
 
 COBJS	:= $(COBJS-y)
 SRCS 	:= $(COBJS:.o=.c)

drivers/gpio/mx31_gpio.c

@@ -0,0 +1,73 @@
+/*
+ * Copyright (C) 2009
+ * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/arch/mx31.h>
+#include <asm/arch/mx31-regs.h>
+
+/* GPIO port description */
+static unsigned long gpio_ports[] = {
+	[0] = GPIO1_BASE,
+	[1] = GPIO2_BASE,
+	[2] = GPIO3_BASE,
+};
+
+int mx31_gpio_direction(unsigned int gpio, enum mx31_gpio_direction direction)
+{
+	unsigned int port = gpio >> 5;
+	u32 l;
+
+	if (port >= ARRAY_SIZE(gpio_ports))
+		return 1;
+
+	gpio &= 0x1f;
+
+	l = __REG(gpio_ports[port] + GPIO_GDIR);
+	switch (direction) {
+	case MX31_GPIO_DIRECTION_OUT:
+		l |= 1 << gpio;
+		break;
+	case MX31_GPIO_DIRECTION_IN:
+		l &= ~(1 << gpio);
+	}
+	__REG(gpio_ports[port] + GPIO_GDIR) = l;
+
+	return 0;
+}
+
+void mx31_gpio_set(unsigned int gpio, unsigned int value)
+{
+	unsigned int port = gpio >> 5;
+	u32 l;
+
+	if (port >= ARRAY_SIZE(gpio_ports))
+		return;
+
+	gpio &= 0x1f;
+
+	l = __REG(gpio_ports[port] + GPIO_DR);
+	if (value)
+		l |= 1 << gpio;
+	else
+		l &= ~(1 << gpio);
+	__REG(gpio_ports[port] + GPIO_DR) = l;
+}

drivers/i2c/fsl_i2c.c

@@ -42,6 +42,9 @@ DECLARE_GLOBAL_DATA_PTR;
 #define CONFIG_SYS_SPD_BUS_NUM 0
 #endif
 static unsigned int i2c_bus_num __attribute__ ((section (".data"))) = CONFIG_SYS_SPD_BUS_NUM;
+#if defined(CONFIG_I2C_MUX)
+static unsigned int i2c_bus_num_mux __attribute__ ((section ("data"))) = 0;
+#endif
 
 static unsigned int i2c_bus_speed[2] = {CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SPEED};
 
@@ -369,6 +372,19 @@ i2c_probe(uchar chip)
 
 int i2c_set_bus_num(unsigned int bus)
 {
+#if defined(CONFIG_I2C_MUX)
+	if (bus < CONFIG_SYS_MAX_I2C_BUS) {
+		i2c_bus_num = bus;
+	} else {
+		int	ret;
+
+		ret = i2x_mux_select_mux(bus);
+		if (ret)
+			return ret;
+		i2c_bus_num = 0;
+	}
+	i2c_bus_num_mux = bus;
+#else
 #ifdef CONFIG_SYS_I2C2_OFFSET
 	if (bus > 1) {
 #else
@@ -378,7 +394,7 @@ int i2c_set_bus_num(unsigned int bus)
 	}
 
 	i2c_bus_num = bus;
-
+#endif
 	return 0;
 }
 
@@ -396,7 +412,11 @@ int i2c_set_bus_speed(unsigned int speed)
 
 unsigned int i2c_get_bus_num(void)
 {
+#if defined(CONFIG_I2C_MUX)
+	return i2c_bus_num_mux;
+#else
 	return i2c_bus_num;
+#endif
 }
 
 unsigned int i2c_get_bus_speed(void)

drivers/i2c/soft_i2c.c

@@ -40,7 +40,7 @@
 #ifdef CONFIG_LPC2292
 #include <asm/arch/hardware.h>
 #endif
-#ifdef	CONFIG_MPC866			/* only valid for MPC866 */
+#if defined(CONFIG_MPC852T) || defined(CONFIG_MPC866)
 #include <asm/io.h>
 #endif
 #include <i2c.h>

drivers/mtd/cfi_flash.c

@@ -1806,8 +1806,9 @@ static void flash_fixup_stm(flash_info_t *info, struct cfi_qry *qry)
 	if (qry->num_erase_regions > 1) {
 		/* reverse geometry if top boot part */
 		if (info->cfi_version < 0x3131) {
-			/* CFI < 1.1, guess by device id (only M29W320ET now) */
-			if (info->device_id == 0x2256) {
+			/* CFI < 1.1, guess by device id (M29W320{DT,ET} only) */
+			if (info->device_id == 0x22CA ||
+			    info->device_id == 0x2256) {
 				cfi_reverse_geometry(qry);
 			}
 		}

drivers/net/mpc5xxx_fec.c

@@ -281,13 +281,6 @@ static int mpc5xxx_fec_init(struct eth_device *dev, bd_t * bis)
 	}
 
 	fec->eth->x_cntrl = 0x00000000;	/* half-duplex, heartbeat disabled */
-	if (fec->xcv_type != SEVENWIRE) {
-		/*
-		 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
-		 * and do not drop the Preamble.
-		 */
-		fec->eth->mii_speed = (((gd->ipb_clk >> 20) / 5) << 1); /* No MII for 7-wire mode */
-	}
 
 	/*
 	 * Set Opcode/Pause Duration Register
@@ -640,6 +633,15 @@ static void mpc5xxx_fec_halt(struct eth_device *dev)
 	 */
 	udelay(10);
 
+	/* don't leave the MII speed set to zero */
+	if (fec->xcv_type != SEVENWIRE) {
+		/*
+		 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
+		 * and do not drop the Preamble.
+		 */
+		fec->eth->mii_speed = (((gd->ipb_clk >> 20) / 5) << 1); /* No MII for 7-wire mode */
+	}
+
 #if (DEBUG & 0x3)
 	printf("Ethernet task stopped\n");
 #endif
@@ -897,6 +899,13 @@ int mpc5xxx_fec_initialize(bd_t * bis)
 #else
 #error fec->xcv_type not initialized.
 #endif
+	if (fec->xcv_type != SEVENWIRE) {
+		/*
+		 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
+		 * and do not drop the Preamble.
+		 */
+		fec->eth->mii_speed = (((gd->ipb_clk >> 20) / 5) << 1); /* No MII for 7-wire mode */
+	}
 
 	dev->priv = (void *)fec;
 	dev->iobase = MPC5XXX_FEC;

drivers/net/sh_eth.c

@@ -639,8 +639,6 @@ err:
 void sh_eth_halt(struct eth_device *dev)
 {
 	struct sh_eth_dev *eth = dev->priv;
-
-	sh_eth_reset(eth);
 	sh_eth_stop(eth);
 }
 

drivers/net/smc911x.c

@@ -27,38 +27,7 @@
 #include <net.h>
 #include <miiphy.h>
 
-#if defined (CONFIG_DRIVER_SMC911X_32_BIT) && \
-	defined (CONFIG_DRIVER_SMC911X_16_BIT)
-#error "SMC911X: Only one of CONFIG_DRIVER_SMC911X_32_BIT and \
-	CONFIG_DRIVER_SMC911X_16_BIT shall be set"
-#endif
-
-#if defined (CONFIG_DRIVER_SMC911X_32_BIT)
-static inline u32 __smc911x_reg_read(u32 addr)
-{
-	return *(volatile u32*)addr;
-}
-u32 smc911x_reg_read(u32 addr) __attribute__((weak, alias("__smc911x_reg_read")));
-
-static inline void __smc911x_reg_write(u32 addr, u32 val)
-{
-	*(volatile u32*)addr = val;
-}
-void smc911x_reg_write(u32 addr, u32 val) __attribute__((weak, alias("__smc911x_reg_write")));
-#elif defined (CONFIG_DRIVER_SMC911X_16_BIT)
-static inline u32 smc911x_reg_read(u32 addr)
-{
-	volatile u16 *addr_16 = (u16 *)addr;
-	return ((*addr_16 & 0x0000ffff) | (*(addr_16 + 1) << 16));
-}
-static inline void smc911x_reg_write(u32 addr, u32 val)
-{
-	*(volatile u16*)addr = (u16)val;
-	*(volatile u16*)(addr + 2) = (u16)(val >> 16);
-}
-#else
-#error "SMC911X: undefined bus width"
-#endif /* CONFIG_DRIVER_SMC911X_16_BIT */
+#include "smc911x.h"
 
 u32 pkt_data_pull(u32 addr) \
 	__attribute__ ((weak, alias ("smc911x_reg_read")));
@@ -67,370 +36,6 @@ void pkt_data_push(u32 addr, u32 val) \
 
 #define mdelay(n)       udelay((n)*1000)
 
-/* Below are the register offsets and bit definitions
- * of the Lan911x memory space
- */
-#define RX_DATA_FIFO		 (CONFIG_DRIVER_SMC911X_BASE + 0x00)
-
-#define TX_DATA_FIFO		 (CONFIG_DRIVER_SMC911X_BASE + 0x20)
-#define	TX_CMD_A_INT_ON_COMP			0x80000000
-#define	TX_CMD_A_INT_BUF_END_ALGN		0x03000000
-#define	TX_CMD_A_INT_4_BYTE_ALGN		0x00000000
-#define	TX_CMD_A_INT_16_BYTE_ALGN		0x01000000
-#define	TX_CMD_A_INT_32_BYTE_ALGN		0x02000000
-#define	TX_CMD_A_INT_DATA_OFFSET		0x001F0000
-#define	TX_CMD_A_INT_FIRST_SEG			0x00002000
-#define	TX_CMD_A_INT_LAST_SEG			0x00001000
-#define	TX_CMD_A_BUF_SIZE			0x000007FF
-#define	TX_CMD_B_PKT_TAG			0xFFFF0000
-#define	TX_CMD_B_ADD_CRC_DISABLE		0x00002000
-#define	TX_CMD_B_DISABLE_PADDING		0x00001000
-#define	TX_CMD_B_PKT_BYTE_LENGTH		0x000007FF
-
-#define RX_STATUS_FIFO		(CONFIG_DRIVER_SMC911X_BASE + 0x40)
-#define	RX_STS_PKT_LEN				0x3FFF0000
-#define	RX_STS_ES				0x00008000
-#define	RX_STS_BCST				0x00002000
-#define	RX_STS_LEN_ERR				0x00001000
-#define	RX_STS_RUNT_ERR				0x00000800
-#define	RX_STS_MCAST				0x00000400
-#define	RX_STS_TOO_LONG				0x00000080
-#define	RX_STS_COLL				0x00000040
-#define	RX_STS_ETH_TYPE				0x00000020
-#define	RX_STS_WDOG_TMT				0x00000010
-#define	RX_STS_MII_ERR				0x00000008
-#define	RX_STS_DRIBBLING			0x00000004
-#define	RX_STS_CRC_ERR				0x00000002
-#define RX_STATUS_FIFO_PEEK	(CONFIG_DRIVER_SMC911X_BASE + 0x44)
-#define TX_STATUS_FIFO		(CONFIG_DRIVER_SMC911X_BASE + 0x48)
-#define	TX_STS_TAG				0xFFFF0000
-#define	TX_STS_ES				0x00008000
-#define	TX_STS_LOC				0x00000800
-#define	TX_STS_NO_CARR				0x00000400
-#define	TX_STS_LATE_COLL			0x00000200
-#define	TX_STS_MANY_COLL			0x00000100
-#define	TX_STS_COLL_CNT				0x00000078
-#define	TX_STS_MANY_DEFER			0x00000004
-#define	TX_STS_UNDERRUN				0x00000002
-#define	TX_STS_DEFERRED				0x00000001
-#define TX_STATUS_FIFO_PEEK	(CONFIG_DRIVER_SMC911X_BASE + 0x4C)
-#define ID_REV			(CONFIG_DRIVER_SMC911X_BASE + 0x50)
-#define	ID_REV_CHIP_ID				0xFFFF0000  /* RO */
-#define	ID_REV_REV_ID				0x0000FFFF  /* RO */
-
-#define INT_CFG			(CONFIG_DRIVER_SMC911X_BASE + 0x54)
-#define	INT_CFG_INT_DEAS			0xFF000000  /* R/W */
-#define	INT_CFG_INT_DEAS_CLR			0x00004000
-#define	INT_CFG_INT_DEAS_STS			0x00002000
-#define	INT_CFG_IRQ_INT				0x00001000  /* RO */
-#define	INT_CFG_IRQ_EN				0x00000100  /* R/W */
-#define	INT_CFG_IRQ_POL				0x00000010  /* R/W Not Affected by SW Reset */
-#define	INT_CFG_IRQ_TYPE			0x00000001  /* R/W Not Affected by SW Reset */
-
-#define INT_STS			(CONFIG_DRIVER_SMC911X_BASE + 0x58)
-#define	INT_STS_SW_INT				0x80000000  /* R/WC */
-#define	INT_STS_TXSTOP_INT			0x02000000  /* R/WC */
-#define	INT_STS_RXSTOP_INT			0x01000000  /* R/WC */
-#define	INT_STS_RXDFH_INT			0x00800000  /* R/WC */
-#define	INT_STS_RXDF_INT			0x00400000  /* R/WC */
-#define	INT_STS_TX_IOC				0x00200000  /* R/WC */
-#define	INT_STS_RXD_INT				0x00100000  /* R/WC */
-#define	INT_STS_GPT_INT				0x00080000  /* R/WC */
-#define	INT_STS_PHY_INT				0x00040000  /* RO */
-#define	INT_STS_PME_INT				0x00020000  /* R/WC */
-#define	INT_STS_TXSO				0x00010000  /* R/WC */
-#define	INT_STS_RWT				0x00008000  /* R/WC */
-#define	INT_STS_RXE				0x00004000  /* R/WC */
-#define	INT_STS_TXE				0x00002000  /* R/WC */
-/*#define	INT_STS_ERX		0x00001000*/  /* R/WC */
-#define	INT_STS_TDFU				0x00000800  /* R/WC */
-#define	INT_STS_TDFO				0x00000400  /* R/WC */
-#define	INT_STS_TDFA				0x00000200  /* R/WC */
-#define	INT_STS_TSFF				0x00000100  /* R/WC */
-#define	INT_STS_TSFL				0x00000080  /* R/WC */
-/*#define	INT_STS_RXDF		0x00000040*/  /* R/WC */
-#define	INT_STS_RDFO				0x00000040  /* R/WC */
-#define	INT_STS_RDFL				0x00000020  /* R/WC */
-#define	INT_STS_RSFF				0x00000010  /* R/WC */
-#define	INT_STS_RSFL				0x00000008  /* R/WC */
-#define	INT_STS_GPIO2_INT			0x00000004  /* R/WC */
-#define	INT_STS_GPIO1_INT			0x00000002  /* R/WC */
-#define	INT_STS_GPIO0_INT			0x00000001  /* R/WC */
-#define INT_EN			(CONFIG_DRIVER_SMC911X_BASE + 0x5C)
-#define	INT_EN_SW_INT_EN			0x80000000  /* R/W */
-#define	INT_EN_TXSTOP_INT_EN			0x02000000  /* R/W */
-#define	INT_EN_RXSTOP_INT_EN			0x01000000  /* R/W */
-#define	INT_EN_RXDFH_INT_EN			0x00800000  /* R/W */
-/*#define	INT_EN_RXDF_INT_EN		0x00400000*/  /* R/W */
-#define	INT_EN_TIOC_INT_EN			0x00200000  /* R/W */
-#define	INT_EN_RXD_INT_EN			0x00100000  /* R/W */
-#define	INT_EN_GPT_INT_EN			0x00080000  /* R/W */
-#define	INT_EN_PHY_INT_EN			0x00040000  /* R/W */
-#define	INT_EN_PME_INT_EN			0x00020000  /* R/W */
-#define	INT_EN_TXSO_EN				0x00010000  /* R/W */
-#define	INT_EN_RWT_EN				0x00008000  /* R/W */
-#define	INT_EN_RXE_EN				0x00004000  /* R/W */
-#define	INT_EN_TXE_EN				0x00002000  /* R/W */
-/*#define	INT_EN_ERX_EN			0x00001000*/  /* R/W */
-#define	INT_EN_TDFU_EN				0x00000800  /* R/W */
-#define	INT_EN_TDFO_EN				0x00000400  /* R/W */
-#define	INT_EN_TDFA_EN				0x00000200  /* R/W */
-#define	INT_EN_TSFF_EN				0x00000100  /* R/W */
-#define	INT_EN_TSFL_EN				0x00000080  /* R/W */
-/*#define	INT_EN_RXDF_EN			0x00000040*/  /* R/W */
-#define	INT_EN_RDFO_EN				0x00000040  /* R/W */
-#define	INT_EN_RDFL_EN				0x00000020  /* R/W */
-#define	INT_EN_RSFF_EN				0x00000010  /* R/W */
-#define	INT_EN_RSFL_EN				0x00000008  /* R/W */
-#define	INT_EN_GPIO2_INT			0x00000004  /* R/W */
-#define	INT_EN_GPIO1_INT			0x00000002  /* R/W */
-#define	INT_EN_GPIO0_INT			0x00000001  /* R/W */
-
-#define BYTE_TEST		(CONFIG_DRIVER_SMC911X_BASE + 0x64)
-#define FIFO_INT		(CONFIG_DRIVER_SMC911X_BASE + 0x68)
-#define	FIFO_INT_TX_AVAIL_LEVEL			0xFF000000  /* R/W */
-#define	FIFO_INT_TX_STS_LEVEL			0x00FF0000  /* R/W */
-#define	FIFO_INT_RX_AVAIL_LEVEL			0x0000FF00  /* R/W */
-#define	FIFO_INT_RX_STS_LEVEL			0x000000FF  /* R/W */
-
-#define RX_CFG			(CONFIG_DRIVER_SMC911X_BASE + 0x6C)
-#define	RX_CFG_RX_END_ALGN			0xC0000000  /* R/W */
-#define		RX_CFG_RX_END_ALGN4		0x00000000  /* R/W */
-#define		RX_CFG_RX_END_ALGN16		0x40000000  /* R/W */
-#define		RX_CFG_RX_END_ALGN32		0x80000000  /* R/W */
-#define	RX_CFG_RX_DMA_CNT			0x0FFF0000  /* R/W */
-#define	RX_CFG_RX_DUMP				0x00008000  /* R/W */
-#define	RX_CFG_RXDOFF				0x00001F00  /* R/W */
-/*#define	RX_CFG_RXBAD			0x00000001*/  /* R/W */
-
-#define TX_CFG			(CONFIG_DRIVER_SMC911X_BASE + 0x70)
-/*#define	TX_CFG_TX_DMA_LVL		0xE0000000*/	 /* R/W */
-/*#define	TX_CFG_TX_DMA_CNT		0x0FFF0000*/	 /* R/W Self Clearing */
-#define	TX_CFG_TXS_DUMP				0x00008000  /* Self Clearing */
-#define	TX_CFG_TXD_DUMP				0x00004000  /* Self Clearing */
-#define	TX_CFG_TXSAO				0x00000004  /* R/W */
-#define	TX_CFG_TX_ON				0x00000002  /* R/W */
-#define	TX_CFG_STOP_TX				0x00000001  /* Self Clearing */
-
-#define HW_CFG			(CONFIG_DRIVER_SMC911X_BASE + 0x74)
-#define	HW_CFG_TTM				0x00200000  /* R/W */
-#define	HW_CFG_SF				0x00100000  /* R/W */
-#define	HW_CFG_TX_FIF_SZ			0x000F0000  /* R/W */
-#define	HW_CFG_TR				0x00003000  /* R/W */
-#define	HW_CFG_PHY_CLK_SEL			0x00000060  /* R/W */
-#define	HW_CFG_PHY_CLK_SEL_INT_PHY		0x00000000 /* R/W */
-#define	HW_CFG_PHY_CLK_SEL_EXT_PHY		0x00000020 /* R/W */
-#define	HW_CFG_PHY_CLK_SEL_CLK_DIS		0x00000040 /* R/W */
-#define	HW_CFG_SMI_SEL				0x00000010  /* R/W */
-#define	HW_CFG_EXT_PHY_DET			0x00000008  /* RO */
-#define	HW_CFG_EXT_PHY_EN			0x00000004  /* R/W */
-#define	HW_CFG_32_16_BIT_MODE			0x00000004  /* RO */
-#define	HW_CFG_SRST_TO				0x00000002  /* RO */
-#define	HW_CFG_SRST				0x00000001  /* Self Clearing */
-
-#define RX_DP_CTRL		(CONFIG_DRIVER_SMC911X_BASE + 0x78)
-#define	RX_DP_CTRL_RX_FFWD			0x80000000  /* R/W */
-#define	RX_DP_CTRL_FFWD_BUSY			0x80000000  /* RO */
-
-#define RX_FIFO_INF		(CONFIG_DRIVER_SMC911X_BASE + 0x7C)
-#define	 RX_FIFO_INF_RXSUSED			0x00FF0000  /* RO */
-#define	 RX_FIFO_INF_RXDUSED			0x0000FFFF  /* RO */
-
-#define TX_FIFO_INF		(CONFIG_DRIVER_SMC911X_BASE + 0x80)
-#define	TX_FIFO_INF_TSUSED			0x00FF0000  /* RO */
-#define	TX_FIFO_INF_TDFREE			0x0000FFFF  /* RO */
-
-#define PMT_CTRL		(CONFIG_DRIVER_SMC911X_BASE + 0x84)
-#define	PMT_CTRL_PM_MODE			0x00003000  /* Self Clearing */
-#define	PMT_CTRL_PHY_RST			0x00000400  /* Self Clearing */
-#define	PMT_CTRL_WOL_EN				0x00000200  /* R/W */
-#define	PMT_CTRL_ED_EN				0x00000100  /* R/W */
-#define	PMT_CTRL_PME_TYPE			0x00000040  /* R/W Not Affected by SW Reset */
-#define	PMT_CTRL_WUPS				0x00000030  /* R/WC */
-#define	PMT_CTRL_WUPS_NOWAKE			0x00000000  /* R/WC */
-#define	PMT_CTRL_WUPS_ED			0x00000010  /* R/WC */
-#define	PMT_CTRL_WUPS_WOL			0x00000020  /* R/WC */
-#define	PMT_CTRL_WUPS_MULTI			0x00000030  /* R/WC */
-#define	PMT_CTRL_PME_IND			0x00000008  /* R/W */
-#define	PMT_CTRL_PME_POL			0x00000004  /* R/W */
-#define	PMT_CTRL_PME_EN				0x00000002  /* R/W Not Affected by SW Reset */
-#define	PMT_CTRL_READY				0x00000001  /* RO */
-
-#define GPIO_CFG		(CONFIG_DRIVER_SMC911X_BASE + 0x88)
-#define	GPIO_CFG_LED3_EN			0x40000000  /* R/W */
-#define	GPIO_CFG_LED2_EN			0x20000000  /* R/W */
-#define	GPIO_CFG_LED1_EN			0x10000000  /* R/W */
-#define	GPIO_CFG_GPIO2_INT_POL			0x04000000  /* R/W */
-#define	GPIO_CFG_GPIO1_INT_POL			0x02000000  /* R/W */
-#define	GPIO_CFG_GPIO0_INT_POL			0x01000000  /* R/W */
-#define	GPIO_CFG_EEPR_EN			0x00700000  /* R/W */
-#define	GPIO_CFG_GPIOBUF2			0x00040000  /* R/W */
-#define	GPIO_CFG_GPIOBUF1			0x00020000  /* R/W */
-#define	GPIO_CFG_GPIOBUF0			0x00010000  /* R/W */
-#define	GPIO_CFG_GPIODIR2			0x00000400  /* R/W */
-#define	GPIO_CFG_GPIODIR1			0x00000200  /* R/W */
-#define	GPIO_CFG_GPIODIR0			0x00000100  /* R/W */
-#define	GPIO_CFG_GPIOD4				0x00000010  /* R/W */
-#define	GPIO_CFG_GPIOD3				0x00000008  /* R/W */
-#define	GPIO_CFG_GPIOD2				0x00000004  /* R/W */
-#define	GPIO_CFG_GPIOD1				0x00000002  /* R/W */
-#define	GPIO_CFG_GPIOD0				0x00000001  /* R/W */
-
-#define GPT_CFG			(CONFIG_DRIVER_SMC911X_BASE + 0x8C)
-#define	GPT_CFG_TIMER_EN			0x20000000  /* R/W */
-#define	GPT_CFG_GPT_LOAD			0x0000FFFF  /* R/W */
-
-#define GPT_CNT			(CONFIG_DRIVER_SMC911X_BASE + 0x90)
-#define	GPT_CNT_GPT_CNT				0x0000FFFF  /* RO */
-
-#define ENDIAN			(CONFIG_DRIVER_SMC911X_BASE + 0x98)
-#define FREE_RUN		(CONFIG_DRIVER_SMC911X_BASE + 0x9C)
-#define RX_DROP			(CONFIG_DRIVER_SMC911X_BASE + 0xA0)
-#define MAC_CSR_CMD		(CONFIG_DRIVER_SMC911X_BASE + 0xA4)
-#define	 MAC_CSR_CMD_CSR_BUSY			0x80000000  /* Self Clearing */
-#define	 MAC_CSR_CMD_R_NOT_W			0x40000000  /* R/W */
-#define	 MAC_CSR_CMD_CSR_ADDR			0x000000FF  /* R/W */
-
-#define MAC_CSR_DATA		(CONFIG_DRIVER_SMC911X_BASE + 0xA8)
-#define AFC_CFG			(CONFIG_DRIVER_SMC911X_BASE + 0xAC)
-#define		AFC_CFG_AFC_HI			0x00FF0000  /* R/W */
-#define		AFC_CFG_AFC_LO			0x0000FF00  /* R/W */
-#define		AFC_CFG_BACK_DUR		0x000000F0  /* R/W */
-#define		AFC_CFG_FCMULT			0x00000008  /* R/W */
-#define		AFC_CFG_FCBRD			0x00000004  /* R/W */
-#define		AFC_CFG_FCADD			0x00000002  /* R/W */
-#define		AFC_CFG_FCANY			0x00000001  /* R/W */
-
-#define E2P_CMD			(CONFIG_DRIVER_SMC911X_BASE + 0xB0)
-#define		E2P_CMD_EPC_BUSY		0x80000000  /* Self Clearing */
-#define		E2P_CMD_EPC_CMD			0x70000000  /* R/W */
-#define		E2P_CMD_EPC_CMD_READ		0x00000000  /* R/W */
-#define		E2P_CMD_EPC_CMD_EWDS		0x10000000  /* R/W */
-#define		E2P_CMD_EPC_CMD_EWEN		0x20000000  /* R/W */
-#define		E2P_CMD_EPC_CMD_WRITE		0x30000000  /* R/W */
-#define		E2P_CMD_EPC_CMD_WRAL		0x40000000  /* R/W */
-#define		E2P_CMD_EPC_CMD_ERASE		0x50000000  /* R/W */
-#define		E2P_CMD_EPC_CMD_ERAL		0x60000000  /* R/W */
-#define		E2P_CMD_EPC_CMD_RELOAD		0x70000000  /* R/W */
-#define		E2P_CMD_EPC_TIMEOUT		0x00000200  /* RO */
-#define		E2P_CMD_MAC_ADDR_LOADED		0x00000100  /* RO */
-#define		E2P_CMD_EPC_ADDR		0x000000FF  /* R/W */
-
-#define E2P_DATA		(CONFIG_DRIVER_SMC911X_BASE + 0xB4)
-#define	E2P_DATA_EEPROM_DATA			0x000000FF  /* R/W */
-/* end of LAN register offsets and bit definitions */
-
-/* MAC Control and Status registers */
-#define MAC_CR			0x01  /* R/W */
-
-/* MAC_CR - MAC Control Register */
-#define MAC_CR_RXALL			0x80000000
-/* TODO: delete this bit? It is not described in the data sheet. */
-#define MAC_CR_HBDIS			0x10000000
-#define MAC_CR_RCVOWN			0x00800000
-#define MAC_CR_LOOPBK			0x00200000
-#define MAC_CR_FDPX			0x00100000
-#define MAC_CR_MCPAS			0x00080000
-#define MAC_CR_PRMS			0x00040000
-#define MAC_CR_INVFILT			0x00020000
-#define MAC_CR_PASSBAD			0x00010000
-#define MAC_CR_HFILT			0x00008000
-#define MAC_CR_HPFILT			0x00002000
-#define MAC_CR_LCOLL			0x00001000
-#define MAC_CR_BCAST			0x00000800
-#define MAC_CR_DISRTY			0x00000400
-#define MAC_CR_PADSTR			0x00000100
-#define MAC_CR_BOLMT_MASK		0x000000C0
-#define MAC_CR_DFCHK			0x00000020
-#define MAC_CR_TXEN			0x00000008
-#define MAC_CR_RXEN			0x00000004
-
-#define ADDRH			0x02	  /* R/W mask 0x0000FFFFUL */
-#define ADDRL			0x03	  /* R/W mask 0xFFFFFFFFUL */
-#define HASHH			0x04	  /* R/W */
-#define HASHL			0x05	  /* R/W */
-
-#define MII_ACC			0x06	  /* R/W */
-#define MII_ACC_PHY_ADDR		0x0000F800
-#define MII_ACC_MIIRINDA		0x000007C0
-#define MII_ACC_MII_WRITE		0x00000002
-#define MII_ACC_MII_BUSY		0x00000001
-
-#define MII_DATA		0x07	  /* R/W mask 0x0000FFFFUL */
-
-#define FLOW			0x08	  /* R/W */
-#define FLOW_FCPT			0xFFFF0000
-#define FLOW_FCPASS			0x00000004
-#define FLOW_FCEN			0x00000002
-#define FLOW_FCBSY			0x00000001
-
-#define VLAN1			0x09	  /* R/W mask 0x0000FFFFUL */
-#define VLAN1_VTI1			0x0000ffff
-
-#define VLAN2			0x0A	  /* R/W mask 0x0000FFFFUL */
-#define VLAN2_VTI2			0x0000ffff
-
-#define WUFF			0x0B	  /* WO */
-
-#define WUCSR			0x0C	  /* R/W */
-#define WUCSR_GUE			0x00000200
-#define WUCSR_WUFR			0x00000040
-#define WUCSR_MPR			0x00000020
-#define WUCSR_WAKE_EN			0x00000004
-#define WUCSR_MPEN			0x00000002
-
-/* Chip ID values */
-#define CHIP_9115	0x115
-#define CHIP_9116	0x116
-#define CHIP_9117	0x117
-#define CHIP_9118	0x118
-#define CHIP_9211	0x9211
-#define CHIP_9215	0x115a
-#define CHIP_9216	0x116a
-#define CHIP_9217	0x117a
-#define CHIP_9218	0x118a
-
-struct chip_id {
-	u16 id;
-	char *name;
-};
-
-static const struct chip_id chip_ids[] =  {
-	{ CHIP_9115, "LAN9115" },
-	{ CHIP_9116, "LAN9116" },
-	{ CHIP_9117, "LAN9117" },
-	{ CHIP_9118, "LAN9118" },
-	{ CHIP_9211, "LAN9211" },
-	{ CHIP_9215, "LAN9215" },
-	{ CHIP_9216, "LAN9216" },
-	{ CHIP_9217, "LAN9217" },
-	{ CHIP_9218, "LAN9218" },
-	{ 0, NULL },
-};
-
-#define DRIVERNAME "smc911x"
-
-u32 smc911x_get_mac_csr(u8 reg)
-{
-	while (smc911x_reg_read(MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
-		;
-	smc911x_reg_write(MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY | MAC_CSR_CMD_R_NOT_W | reg);
-	while (smc911x_reg_read(MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
-		;
-
-	return smc911x_reg_read(MAC_CSR_DATA);
-}
-
-void smc911x_set_mac_csr(u8 reg, u32 data)
-{
-	while (smc911x_reg_read(MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
-		;
-	smc911x_reg_write(MAC_CSR_DATA, data);
-	smc911x_reg_write(MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY | reg);
-	while (smc911x_reg_read(MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
-		;
-}
-
 static int smx911x_handle_mac_address(bd_t *bd)
 {
 	unsigned long addrh, addrl;
@@ -541,48 +146,6 @@ err_out:
 	printf(DRIVERNAME ": autonegotiation timed out\n");
 }
 
-static void smc911x_reset(void)
-{
-	int timeout;
-
-	/* Take out of PM setting first */
-	if (smc911x_reg_read(PMT_CTRL) & PMT_CTRL_READY) {
-		/* Write to the bytetest will take out of powerdown */
-		smc911x_reg_write(BYTE_TEST, 0x0);
-
-		timeout = 10;
-
-		while (timeout-- && !(smc911x_reg_read(PMT_CTRL) & PMT_CTRL_READY))
-			udelay(10);
-		if (!timeout) {
-			printf(DRIVERNAME
-				": timeout waiting for PM restore\n");
-			return;
-		}
-	}
-
-	/* Disable interrupts */
-	smc911x_reg_write(INT_EN, 0);
-
-	smc911x_reg_write(HW_CFG, HW_CFG_SRST);
-
-	timeout = 1000;
-	while (timeout-- && smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY)
-		udelay(10);
-
-	if (!timeout) {
-		printf(DRIVERNAME ": reset timeout\n");
-		return;
-	}
-
-	/* Reset the FIFO level and flow control settings */
-	smc911x_set_mac_csr(FLOW, FLOW_FCPT | FLOW_FCEN);
-	smc911x_reg_write(AFC_CFG, 0x0050287F);
-
-	/* Set to LED outputs */
-	smc911x_reg_write(GPIO_CFG, 0x70070000);
-}
-
 static void smc911x_enable(void)
 {
 	/* Enable TX */
@@ -601,26 +164,10 @@ static void smc911x_enable(void)
 
 int eth_init(bd_t *bd)
 {
-	unsigned long val, i;
-
 	printf(DRIVERNAME ": initializing\n");
 
-	val = smc911x_reg_read(BYTE_TEST);
-	if (val != 0x87654321) {
-		printf(DRIVERNAME ": Invalid chip endian 0x%08lx\n", val);
+	if (smc911x_detect_chip())
 		goto err_out;
-	}
-
-	val = smc911x_reg_read(ID_REV) >> 16;
-	for (i = 0; chip_ids[i].id != 0; i++) {
-		if (chip_ids[i].id == val) break;
-	}
-	if (!chip_ids[i].id) {
-		printf(DRIVERNAME ": Unknown chip ID %04lx\n", val);
-		goto err_out;
-	}
-
-	printf(DRIVERNAME ": detected %s controller\n", chip_ids[i].name);
 
 	smc911x_reset();
 

drivers/net/smc911x.h

@@ -0,0 +1,494 @@
+/*
+ * SMSC LAN9[12]1[567] Network driver
+ *
+ * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SMC911X_H_
+#define _SMC911X_H_
+
+#include <linux/types.h>
+
+#if defined (CONFIG_DRIVER_SMC911X_32_BIT) && \
+	defined (CONFIG_DRIVER_SMC911X_16_BIT)
+#error "SMC911X: Only one of CONFIG_DRIVER_SMC911X_32_BIT and \
+	CONFIG_DRIVER_SMC911X_16_BIT shall be set"
+#endif
+
+#if defined (CONFIG_DRIVER_SMC911X_32_BIT)
+static inline u32 __smc911x_reg_read(u32 addr)
+{
+	return *(volatile u32*)addr;
+}
+u32 smc911x_reg_read(u32 addr) __attribute__((weak, alias("__smc911x_reg_read")));
+
+static inline void __smc911x_reg_write(u32 addr, u32 val)
+{
+	*(volatile u32*)addr = val;
+}
+void smc911x_reg_write(u32 addr, u32 val) __attribute__((weak, alias("__smc911x_reg_write")));
+#elif defined (CONFIG_DRIVER_SMC911X_16_BIT)
+static inline u32 smc911x_reg_read(u32 addr)
+{
+	volatile u16 *addr_16 = (u16 *)addr;
+	return ((*addr_16 & 0x0000ffff) | (*(addr_16 + 1) << 16));
+}
+static inline void smc911x_reg_write(u32 addr, u32 val)
+{
+	*(volatile u16*)addr = (u16)val;
+	*(volatile u16*)(addr + 2) = (u16)(val >> 16);
+}
+#else
+#error "SMC911X: undefined bus width"
+#endif /* CONFIG_DRIVER_SMC911X_16_BIT */
+
+/* Below are the register offsets and bit definitions
+ * of the Lan911x memory space
+ */
+#define RX_DATA_FIFO		 (CONFIG_DRIVER_SMC911X_BASE + 0x00)
+
+#define TX_DATA_FIFO		 (CONFIG_DRIVER_SMC911X_BASE + 0x20)
+#define	TX_CMD_A_INT_ON_COMP			0x80000000
+#define	TX_CMD_A_INT_BUF_END_ALGN		0x03000000
+#define	TX_CMD_A_INT_4_BYTE_ALGN		0x00000000
+#define	TX_CMD_A_INT_16_BYTE_ALGN		0x01000000
+#define	TX_CMD_A_INT_32_BYTE_ALGN		0x02000000
+#define	TX_CMD_A_INT_DATA_OFFSET		0x001F0000
+#define	TX_CMD_A_INT_FIRST_SEG			0x00002000
+#define	TX_CMD_A_INT_LAST_SEG			0x00001000
+#define	TX_CMD_A_BUF_SIZE			0x000007FF
+#define	TX_CMD_B_PKT_TAG			0xFFFF0000
+#define	TX_CMD_B_ADD_CRC_DISABLE		0x00002000
+#define	TX_CMD_B_DISABLE_PADDING		0x00001000
+#define	TX_CMD_B_PKT_BYTE_LENGTH		0x000007FF
+
+#define RX_STATUS_FIFO		(CONFIG_DRIVER_SMC911X_BASE + 0x40)
+#define	RX_STS_PKT_LEN				0x3FFF0000
+#define	RX_STS_ES				0x00008000
+#define	RX_STS_BCST				0x00002000
+#define	RX_STS_LEN_ERR				0x00001000
+#define	RX_STS_RUNT_ERR				0x00000800
+#define	RX_STS_MCAST				0x00000400
+#define	RX_STS_TOO_LONG				0x00000080
+#define	RX_STS_COLL				0x00000040
+#define	RX_STS_ETH_TYPE				0x00000020
+#define	RX_STS_WDOG_TMT				0x00000010
+#define	RX_STS_MII_ERR				0x00000008
+#define	RX_STS_DRIBBLING			0x00000004
+#define	RX_STS_CRC_ERR				0x00000002
+#define RX_STATUS_FIFO_PEEK	(CONFIG_DRIVER_SMC911X_BASE + 0x44)
+#define TX_STATUS_FIFO		(CONFIG_DRIVER_SMC911X_BASE + 0x48)
+#define	TX_STS_TAG				0xFFFF0000
+#define	TX_STS_ES				0x00008000
+#define	TX_STS_LOC				0x00000800
+#define	TX_STS_NO_CARR				0x00000400
+#define	TX_STS_LATE_COLL			0x00000200
+#define	TX_STS_MANY_COLL			0x00000100
+#define	TX_STS_COLL_CNT				0x00000078
+#define	TX_STS_MANY_DEFER			0x00000004
+#define	TX_STS_UNDERRUN				0x00000002
+#define	TX_STS_DEFERRED				0x00000001
+#define TX_STATUS_FIFO_PEEK	(CONFIG_DRIVER_SMC911X_BASE + 0x4C)
+#define ID_REV			(CONFIG_DRIVER_SMC911X_BASE + 0x50)
+#define	ID_REV_CHIP_ID				0xFFFF0000  /* RO */
+#define	ID_REV_REV_ID				0x0000FFFF  /* RO */
+
+#define INT_CFG			(CONFIG_DRIVER_SMC911X_BASE + 0x54)
+#define	INT_CFG_INT_DEAS			0xFF000000  /* R/W */
+#define	INT_CFG_INT_DEAS_CLR			0x00004000
+#define	INT_CFG_INT_DEAS_STS			0x00002000
+#define	INT_CFG_IRQ_INT				0x00001000  /* RO */
+#define	INT_CFG_IRQ_EN				0x00000100  /* R/W */
+#define	INT_CFG_IRQ_POL				0x00000010  /* R/W Not Affected by SW Reset */
+#define	INT_CFG_IRQ_TYPE			0x00000001  /* R/W Not Affected by SW Reset */
+
+#define INT_STS			(CONFIG_DRIVER_SMC911X_BASE + 0x58)
+#define	INT_STS_SW_INT				0x80000000  /* R/WC */
+#define	INT_STS_TXSTOP_INT			0x02000000  /* R/WC */
+#define	INT_STS_RXSTOP_INT			0x01000000  /* R/WC */
+#define	INT_STS_RXDFH_INT			0x00800000  /* R/WC */
+#define	INT_STS_RXDF_INT			0x00400000  /* R/WC */
+#define	INT_STS_TX_IOC				0x00200000  /* R/WC */
+#define	INT_STS_RXD_INT				0x00100000  /* R/WC */
+#define	INT_STS_GPT_INT				0x00080000  /* R/WC */
+#define	INT_STS_PHY_INT				0x00040000  /* RO */
+#define	INT_STS_PME_INT				0x00020000  /* R/WC */
+#define	INT_STS_TXSO				0x00010000  /* R/WC */
+#define	INT_STS_RWT				0x00008000  /* R/WC */
+#define	INT_STS_RXE				0x00004000  /* R/WC */
+#define	INT_STS_TXE				0x00002000  /* R/WC */
+/*#define	INT_STS_ERX		0x00001000*/  /* R/WC */
+#define	INT_STS_TDFU				0x00000800  /* R/WC */
+#define	INT_STS_TDFO				0x00000400  /* R/WC */
+#define	INT_STS_TDFA				0x00000200  /* R/WC */
+#define	INT_STS_TSFF				0x00000100  /* R/WC */
+#define	INT_STS_TSFL				0x00000080  /* R/WC */
+/*#define	INT_STS_RXDF		0x00000040*/  /* R/WC */
+#define	INT_STS_RDFO				0x00000040  /* R/WC */
+#define	INT_STS_RDFL				0x00000020  /* R/WC */
+#define	INT_STS_RSFF				0x00000010  /* R/WC */
+#define	INT_STS_RSFL				0x00000008  /* R/WC */
+#define	INT_STS_GPIO2_INT			0x00000004  /* R/WC */
+#define	INT_STS_GPIO1_INT			0x00000002  /* R/WC */
+#define	INT_STS_GPIO0_INT			0x00000001  /* R/WC */
+#define INT_EN			(CONFIG_DRIVER_SMC911X_BASE + 0x5C)
+#define	INT_EN_SW_INT_EN			0x80000000  /* R/W */
+#define	INT_EN_TXSTOP_INT_EN			0x02000000  /* R/W */
+#define	INT_EN_RXSTOP_INT_EN			0x01000000  /* R/W */
+#define	INT_EN_RXDFH_INT_EN			0x00800000  /* R/W */
+/*#define	INT_EN_RXDF_INT_EN		0x00400000*/  /* R/W */
+#define	INT_EN_TIOC_INT_EN			0x00200000  /* R/W */
+#define	INT_EN_RXD_INT_EN			0x00100000  /* R/W */
+#define	INT_EN_GPT_INT_EN			0x00080000  /* R/W */
+#define	INT_EN_PHY_INT_EN			0x00040000  /* R/W */
+#define	INT_EN_PME_INT_EN			0x00020000  /* R/W */
+#define	INT_EN_TXSO_EN				0x00010000  /* R/W */
+#define	INT_EN_RWT_EN				0x00008000  /* R/W */
+#define	INT_EN_RXE_EN				0x00004000  /* R/W */
+#define	INT_EN_TXE_EN				0x00002000  /* R/W */
+/*#define	INT_EN_ERX_EN			0x00001000*/  /* R/W */
+#define	INT_EN_TDFU_EN				0x00000800  /* R/W */
+#define	INT_EN_TDFO_EN				0x00000400  /* R/W */
+#define	INT_EN_TDFA_EN				0x00000200  /* R/W */
+#define	INT_EN_TSFF_EN				0x00000100  /* R/W */
+#define	INT_EN_TSFL_EN				0x00000080  /* R/W */
+/*#define	INT_EN_RXDF_EN			0x00000040*/  /* R/W */
+#define	INT_EN_RDFO_EN				0x00000040  /* R/W */
+#define	INT_EN_RDFL_EN				0x00000020  /* R/W */
+#define	INT_EN_RSFF_EN				0x00000010  /* R/W */
+#define	INT_EN_RSFL_EN				0x00000008  /* R/W */
+#define	INT_EN_GPIO2_INT			0x00000004  /* R/W */
+#define	INT_EN_GPIO1_INT			0x00000002  /* R/W */
+#define	INT_EN_GPIO0_INT			0x00000001  /* R/W */
+
+#define BYTE_TEST		(CONFIG_DRIVER_SMC911X_BASE + 0x64)
+#define FIFO_INT		(CONFIG_DRIVER_SMC911X_BASE + 0x68)
+#define	FIFO_INT_TX_AVAIL_LEVEL			0xFF000000  /* R/W */
+#define	FIFO_INT_TX_STS_LEVEL			0x00FF0000  /* R/W */
+#define	FIFO_INT_RX_AVAIL_LEVEL			0x0000FF00  /* R/W */
+#define	FIFO_INT_RX_STS_LEVEL			0x000000FF  /* R/W */
+
+#define RX_CFG			(CONFIG_DRIVER_SMC911X_BASE + 0x6C)
+#define	RX_CFG_RX_END_ALGN			0xC0000000  /* R/W */
+#define		RX_CFG_RX_END_ALGN4		0x00000000  /* R/W */
+#define		RX_CFG_RX_END_ALGN16		0x40000000  /* R/W */
+#define		RX_CFG_RX_END_ALGN32		0x80000000  /* R/W */
+#define	RX_CFG_RX_DMA_CNT			0x0FFF0000  /* R/W */
+#define	RX_CFG_RX_DUMP				0x00008000  /* R/W */
+#define	RX_CFG_RXDOFF				0x00001F00  /* R/W */
+/*#define	RX_CFG_RXBAD			0x00000001*/  /* R/W */
+
+#define TX_CFG			(CONFIG_DRIVER_SMC911X_BASE + 0x70)
+/*#define	TX_CFG_TX_DMA_LVL		0xE0000000*/	 /* R/W */
+/*#define	TX_CFG_TX_DMA_CNT		0x0FFF0000*/	 /* R/W Self Clearing */
+#define	TX_CFG_TXS_DUMP				0x00008000  /* Self Clearing */
+#define	TX_CFG_TXD_DUMP				0x00004000  /* Self Clearing */
+#define	TX_CFG_TXSAO				0x00000004  /* R/W */
+#define	TX_CFG_TX_ON				0x00000002  /* R/W */
+#define	TX_CFG_STOP_TX				0x00000001  /* Self Clearing */
+
+#define HW_CFG			(CONFIG_DRIVER_SMC911X_BASE + 0x74)
+#define	HW_CFG_TTM				0x00200000  /* R/W */
+#define	HW_CFG_SF				0x00100000  /* R/W */
+#define	HW_CFG_TX_FIF_SZ			0x000F0000  /* R/W */
+#define	HW_CFG_TR				0x00003000  /* R/W */
+#define	HW_CFG_PHY_CLK_SEL			0x00000060  /* R/W */
+#define	HW_CFG_PHY_CLK_SEL_INT_PHY		0x00000000 /* R/W */
+#define	HW_CFG_PHY_CLK_SEL_EXT_PHY		0x00000020 /* R/W */
+#define	HW_CFG_PHY_CLK_SEL_CLK_DIS		0x00000040 /* R/W */
+#define	HW_CFG_SMI_SEL				0x00000010  /* R/W */
+#define	HW_CFG_EXT_PHY_DET			0x00000008  /* RO */
+#define	HW_CFG_EXT_PHY_EN			0x00000004  /* R/W */
+#define	HW_CFG_32_16_BIT_MODE			0x00000004  /* RO */
+#define	HW_CFG_SRST_TO				0x00000002  /* RO */
+#define	HW_CFG_SRST				0x00000001  /* Self Clearing */
+
+#define RX_DP_CTRL		(CONFIG_DRIVER_SMC911X_BASE + 0x78)
+#define	RX_DP_CTRL_RX_FFWD			0x80000000  /* R/W */
+#define	RX_DP_CTRL_FFWD_BUSY			0x80000000  /* RO */
+
+#define RX_FIFO_INF		(CONFIG_DRIVER_SMC911X_BASE + 0x7C)
+#define	 RX_FIFO_INF_RXSUSED			0x00FF0000  /* RO */
+#define	 RX_FIFO_INF_RXDUSED			0x0000FFFF  /* RO */
+
+#define TX_FIFO_INF		(CONFIG_DRIVER_SMC911X_BASE + 0x80)
+#define	TX_FIFO_INF_TSUSED			0x00FF0000  /* RO */
+#define	TX_FIFO_INF_TDFREE			0x0000FFFF  /* RO */
+
+#define PMT_CTRL		(CONFIG_DRIVER_SMC911X_BASE + 0x84)
+#define	PMT_CTRL_PM_MODE			0x00003000  /* Self Clearing */
+#define	PMT_CTRL_PHY_RST			0x00000400  /* Self Clearing */
+#define	PMT_CTRL_WOL_EN				0x00000200  /* R/W */
+#define	PMT_CTRL_ED_EN				0x00000100  /* R/W */
+#define	PMT_CTRL_PME_TYPE			0x00000040  /* R/W Not Affected by SW Reset */
+#define	PMT_CTRL_WUPS				0x00000030  /* R/WC */
+#define	PMT_CTRL_WUPS_NOWAKE			0x00000000  /* R/WC */
+#define	PMT_CTRL_WUPS_ED			0x00000010  /* R/WC */
+#define	PMT_CTRL_WUPS_WOL			0x00000020  /* R/WC */
+#define	PMT_CTRL_WUPS_MULTI			0x00000030  /* R/WC */
+#define	PMT_CTRL_PME_IND			0x00000008  /* R/W */
+#define	PMT_CTRL_PME_POL			0x00000004  /* R/W */
+#define	PMT_CTRL_PME_EN				0x00000002  /* R/W Not Affected by SW Reset */
+#define	PMT_CTRL_READY				0x00000001  /* RO */
+
+#define GPIO_CFG		(CONFIG_DRIVER_SMC911X_BASE + 0x88)
+#define	GPIO_CFG_LED3_EN			0x40000000  /* R/W */
+#define	GPIO_CFG_LED2_EN			0x20000000  /* R/W */
+#define	GPIO_CFG_LED1_EN			0x10000000  /* R/W */
+#define	GPIO_CFG_GPIO2_INT_POL			0x04000000  /* R/W */
+#define	GPIO_CFG_GPIO1_INT_POL			0x02000000  /* R/W */
+#define	GPIO_CFG_GPIO0_INT_POL			0x01000000  /* R/W */
+#define	GPIO_CFG_EEPR_EN			0x00700000  /* R/W */
+#define	GPIO_CFG_GPIOBUF2			0x00040000  /* R/W */
+#define	GPIO_CFG_GPIOBUF1			0x00020000  /* R/W */
+#define	GPIO_CFG_GPIOBUF0			0x00010000  /* R/W */
+#define	GPIO_CFG_GPIODIR2			0x00000400  /* R/W */
+#define	GPIO_CFG_GPIODIR1			0x00000200  /* R/W */
+#define	GPIO_CFG_GPIODIR0			0x00000100  /* R/W */
+#define	GPIO_CFG_GPIOD4				0x00000010  /* R/W */
+#define	GPIO_CFG_GPIOD3				0x00000008  /* R/W */
+#define	GPIO_CFG_GPIOD2				0x00000004  /* R/W */
+#define	GPIO_CFG_GPIOD1				0x00000002  /* R/W */
+#define	GPIO_CFG_GPIOD0				0x00000001  /* R/W */
+
+#define GPT_CFG			(CONFIG_DRIVER_SMC911X_BASE + 0x8C)
+#define	GPT_CFG_TIMER_EN			0x20000000  /* R/W */
+#define	GPT_CFG_GPT_LOAD			0x0000FFFF  /* R/W */
+
+#define GPT_CNT			(CONFIG_DRIVER_SMC911X_BASE + 0x90)
+#define	GPT_CNT_GPT_CNT				0x0000FFFF  /* RO */
+
+#define ENDIAN			(CONFIG_DRIVER_SMC911X_BASE + 0x98)
+#define FREE_RUN		(CONFIG_DRIVER_SMC911X_BASE + 0x9C)
+#define RX_DROP			(CONFIG_DRIVER_SMC911X_BASE + 0xA0)
+#define MAC_CSR_CMD		(CONFIG_DRIVER_SMC911X_BASE + 0xA4)
+#define	 MAC_CSR_CMD_CSR_BUSY			0x80000000  /* Self Clearing */
+#define	 MAC_CSR_CMD_R_NOT_W			0x40000000  /* R/W */
+#define	 MAC_CSR_CMD_CSR_ADDR			0x000000FF  /* R/W */
+
+#define MAC_CSR_DATA		(CONFIG_DRIVER_SMC911X_BASE + 0xA8)
+#define AFC_CFG			(CONFIG_DRIVER_SMC911X_BASE + 0xAC)
+#define		AFC_CFG_AFC_HI			0x00FF0000  /* R/W */
+#define		AFC_CFG_AFC_LO			0x0000FF00  /* R/W */
+#define		AFC_CFG_BACK_DUR		0x000000F0  /* R/W */
+#define		AFC_CFG_FCMULT			0x00000008  /* R/W */
+#define		AFC_CFG_FCBRD			0x00000004  /* R/W */
+#define		AFC_CFG_FCADD			0x00000002  /* R/W */
+#define		AFC_CFG_FCANY			0x00000001  /* R/W */
+
+#define E2P_CMD			(CONFIG_DRIVER_SMC911X_BASE + 0xB0)
+#define		E2P_CMD_EPC_BUSY		0x80000000  /* Self Clearing */
+#define		E2P_CMD_EPC_CMD			0x70000000  /* R/W */
+#define		E2P_CMD_EPC_CMD_READ		0x00000000  /* R/W */
+#define		E2P_CMD_EPC_CMD_EWDS		0x10000000  /* R/W */
+#define		E2P_CMD_EPC_CMD_EWEN		0x20000000  /* R/W */
+#define		E2P_CMD_EPC_CMD_WRITE		0x30000000  /* R/W */
+#define		E2P_CMD_EPC_CMD_WRAL		0x40000000  /* R/W */
+#define		E2P_CMD_EPC_CMD_ERASE		0x50000000  /* R/W */
+#define		E2P_CMD_EPC_CMD_ERAL		0x60000000  /* R/W */
+#define		E2P_CMD_EPC_CMD_RELOAD		0x70000000  /* R/W */
+#define		E2P_CMD_EPC_TIMEOUT		0x00000200  /* RO */
+#define		E2P_CMD_MAC_ADDR_LOADED		0x00000100  /* RO */
+#define		E2P_CMD_EPC_ADDR		0x000000FF  /* R/W */
+
+#define E2P_DATA		(CONFIG_DRIVER_SMC911X_BASE + 0xB4)
+#define	E2P_DATA_EEPROM_DATA			0x000000FF  /* R/W */
+/* end of LAN register offsets and bit definitions */
+
+/* MAC Control and Status registers */
+#define MAC_CR			0x01  /* R/W */
+
+/* MAC_CR - MAC Control Register */
+#define MAC_CR_RXALL			0x80000000
+/* TODO: delete this bit? It is not described in the data sheet. */
+#define MAC_CR_HBDIS			0x10000000
+#define MAC_CR_RCVOWN			0x00800000
+#define MAC_CR_LOOPBK			0x00200000
+#define MAC_CR_FDPX			0x00100000
+#define MAC_CR_MCPAS			0x00080000
+#define MAC_CR_PRMS			0x00040000
+#define MAC_CR_INVFILT			0x00020000
+#define MAC_CR_PASSBAD			0x00010000
+#define MAC_CR_HFILT			0x00008000
+#define MAC_CR_HPFILT			0x00002000
+#define MAC_CR_LCOLL			0x00001000
+#define MAC_CR_BCAST			0x00000800
+#define MAC_CR_DISRTY			0x00000400
+#define MAC_CR_PADSTR			0x00000100
+#define MAC_CR_BOLMT_MASK		0x000000C0
+#define MAC_CR_DFCHK			0x00000020
+#define MAC_CR_TXEN			0x00000008
+#define MAC_CR_RXEN			0x00000004
+
+#define ADDRH			0x02	  /* R/W mask 0x0000FFFFUL */
+#define ADDRL			0x03	  /* R/W mask 0xFFFFFFFFUL */
+#define HASHH			0x04	  /* R/W */
+#define HASHL			0x05	  /* R/W */
+
+#define MII_ACC			0x06	  /* R/W */
+#define MII_ACC_PHY_ADDR		0x0000F800
+#define MII_ACC_MIIRINDA		0x000007C0
+#define MII_ACC_MII_WRITE		0x00000002
+#define MII_ACC_MII_BUSY		0x00000001
+
+#define MII_DATA		0x07	  /* R/W mask 0x0000FFFFUL */
+
+#define FLOW			0x08	  /* R/W */
+#define FLOW_FCPT			0xFFFF0000
+#define FLOW_FCPASS			0x00000004
+#define FLOW_FCEN			0x00000002
+#define FLOW_FCBSY			0x00000001
+
+#define VLAN1			0x09	  /* R/W mask 0x0000FFFFUL */
+#define VLAN1_VTI1			0x0000ffff
+
+#define VLAN2			0x0A	  /* R/W mask 0x0000FFFFUL */
+#define VLAN2_VTI2			0x0000ffff
+
+#define WUFF			0x0B	  /* WO */
+
+#define WUCSR			0x0C	  /* R/W */
+#define WUCSR_GUE			0x00000200
+#define WUCSR_WUFR			0x00000040
+#define WUCSR_MPR			0x00000020
+#define WUCSR_WAKE_EN			0x00000004
+#define WUCSR_MPEN			0x00000002
+
+/* Chip ID values */
+#define CHIP_9115	0x115
+#define CHIP_9116	0x116
+#define CHIP_9117	0x117
+#define CHIP_9118	0x118
+#define CHIP_9211	0x9211
+#define CHIP_9215	0x115a
+#define CHIP_9216	0x116a
+#define CHIP_9217	0x117a
+#define CHIP_9218	0x118a
+
+struct chip_id {
+	u16 id;
+	char *name;
+};
+
+static const struct chip_id chip_ids[] =  {
+	{ CHIP_9115, "LAN9115" },
+	{ CHIP_9116, "LAN9116" },
+	{ CHIP_9117, "LAN9117" },
+	{ CHIP_9118, "LAN9118" },
+	{ CHIP_9211, "LAN9211" },
+	{ CHIP_9215, "LAN9215" },
+	{ CHIP_9216, "LAN9216" },
+	{ CHIP_9217, "LAN9217" },
+	{ CHIP_9218, "LAN9218" },
+	{ 0, NULL },
+};
+
+
+#define DRIVERNAME "smc911x"
+
+static u32 smc911x_get_mac_csr(u8 reg)
+{
+	while (smc911x_reg_read(MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
+		;
+	smc911x_reg_write(MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY | MAC_CSR_CMD_R_NOT_W | reg);
+	while (smc911x_reg_read(MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
+		;
+
+	return smc911x_reg_read(MAC_CSR_DATA);
+}
+
+static void smc911x_set_mac_csr(u8 reg, u32 data)
+{
+	while (smc911x_reg_read(MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
+		;
+	smc911x_reg_write(MAC_CSR_DATA, data);
+	smc911x_reg_write(MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY | reg);
+	while (smc911x_reg_read(MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
+		;
+}
+
+static int smc911x_detect_chip(void)
+{
+	unsigned long val, i;
+
+	val = smc911x_reg_read(BYTE_TEST);
+	if (val != 0x87654321) {
+		printf(DRIVERNAME ": Invalid chip endian 0x%08lx\n", val);
+		return -1;
+	}
+
+	val = smc911x_reg_read(ID_REV) >> 16;
+	for (i = 0; chip_ids[i].id != 0; i++) {
+		if (chip_ids[i].id == val) break;
+	}
+	if (!chip_ids[i].id) {
+		printf(DRIVERNAME ": Unknown chip ID %04lx\n", val);
+		return -1;
+	}
+
+	printf(DRIVERNAME ": detected %s controller\n", chip_ids[i].name);
+
+	return 0;
+}
+
+static void smc911x_reset(void)
+{
+	int timeout;
+
+	/* Take out of PM setting first */
+	if (smc911x_reg_read(PMT_CTRL) & PMT_CTRL_READY) {
+		/* Write to the bytetest will take out of powerdown */
+		smc911x_reg_write(BYTE_TEST, 0x0);
+
+		timeout = 10;
+
+		while (timeout-- && !(smc911x_reg_read(PMT_CTRL) & PMT_CTRL_READY))
+			udelay(10);
+		if (!timeout) {
+			printf(DRIVERNAME
+				": timeout waiting for PM restore\n");
+			return;
+		}
+	}
+
+	/* Disable interrupts */
+	smc911x_reg_write(INT_EN, 0);
+
+	smc911x_reg_write(HW_CFG, HW_CFG_SRST);
+
+	timeout = 1000;
+	while (timeout-- && smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY)
+		udelay(10);
+
+	if (!timeout) {
+		printf(DRIVERNAME ": reset timeout\n");
+		return;
+	}
+
+	/* Reset the FIFO level and flow control settings */
+	smc911x_set_mac_csr(FLOW, FLOW_FCPT | FLOW_FCEN);
+	smc911x_reg_write(AFC_CFG, 0x0050287F);
+
+	/* Set to LED outputs */
+	smc911x_reg_write(GPIO_CFG, 0x70070000);
+}
+
+#endif

drivers/net/tsec.c

@@ -1332,6 +1332,35 @@ struct phy_info phy_info_cis8201 = {
 			   {miim_end,}
 			   },
 };
+struct phy_info phy_info_VSC8211 = {
+	0xfc4b,
+	"Vitesse VSC8211",
+	4,
+	(struct phy_cmd[]) { /* config */
+			   /* Override PHY config settings */
+			   {MIIM_CIS8201_AUX_CONSTAT,
+			    MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
+			   /* Set up the interface mode */
+			   {MIIM_CIS8201_EXT_CON1,
+			    MIIM_CIS8201_EXTCON1_INIT, NULL},
+			   /* Configure some basic stuff */
+			   {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
+			   {miim_end,}
+			   },
+	(struct phy_cmd[]) { /* startup */
+			   /* Read the Status (2x to make sure link is right) */
+			   {MIIM_STATUS, miim_read, NULL},
+			   /* Auto-negotiate */
+			   {MIIM_STATUS, miim_read, &mii_parse_sr},
+			   /* Read the status */
+			   {MIIM_CIS8201_AUX_CONSTAT, miim_read,
+			    &mii_parse_cis8201},
+			   {miim_end,}
+			   },
+	(struct phy_cmd[]) { /* shutdown */
+			   {miim_end,}
+	},
+};
 struct phy_info phy_info_VSC8244 = {
 	0x3f1b,
 	"Vitesse VSC8244",
@@ -1590,11 +1619,12 @@ struct phy_info *phy_info[] = {
 	&phy_info_M88E1149S,
 	&phy_info_dm9161,
 	&phy_info_lxt971,
+	&phy_info_VSC8211,
 	&phy_info_VSC8244,
 	&phy_info_VSC8601,
 	&phy_info_dp83865,
 	&phy_info_rtl8211b,
-	&phy_info_generic,
+	&phy_info_generic,	/* must be last; has ID 0 and 32 bit mask */
 	NULL
 };
 
@@ -1626,9 +1656,8 @@ struct phy_info *get_phy_info(struct eth_device *dev)
 		}
 	}
 
-	if (theInfo == NULL) {
-		printf("%s: PHY id %x is not supported!\n", dev->name, phy_ID);
-		return NULL;
+	if (theInfo == &phy_info_generic) {
+		printf("%s: No support for PHY id %x; assuming generic\n", dev->name, phy_ID);
 	} else {
 		debug("%s: PHY is %s (%x)\n", dev->name, theInfo->name, phy_ID);
 	}

drivers/pci/pci.c

@@ -165,6 +165,19 @@ struct pci_controller *pci_bus_to_hose (int bus)
 	return NULL;
 }
 
+int pci_last_busno(void)
+{
+	struct pci_controller *hose = hose_head;
+
+	if (!hose)
+		return -1;
+
+	while (hose->next)
+		hose = hose->next;
+
+	return hose->last_busno;
+}
+
 #ifndef CONFIG_IXP425
 pci_dev_t pci_find_devices(struct pci_device_id *ids, int index)
 {

drivers/pci/pci_sh4.c

@@ -54,6 +54,16 @@ int pci_sh4_init(struct pci_controller *hose)
 		PCI_REGION_IO);
 	hose->region_count++;
 
+#if defined(CONFIG_PCI_SYS_BUS)
+	/* PCI System Memory space */
+	pci_set_region(hose->regions + 2,
+		CONFIG_PCI_SYS_BUS,
+		CONFIG_PCI_SYS_PHYS,
+		CONFIG_PCI_SYS_SIZE,
+		PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
+	hose->region_count++;
+#endif
+
 	udelay(1000);
 
 	pci_set_ops(hose,

drivers/pci/pci_sh7780.c

@@ -85,11 +85,11 @@ int pci_sh7780_init(struct pci_controller *hose)
 	p4_out(SH7780_PCICR_PREFIX, SH7780_PCICR);
 	p4_outw(0x0047, SH7780_PCICMD);
 
-	p4_out(0x07F00001, SH7780_PCILSR0);
-	p4_out(0x08000000, SH7780_PCILAR0);
+	p4_out(CONFIG_SH7780_PCI_LSR, SH7780_PCILSR0);
+	p4_out(CONFIG_SH7780_PCI_LAR, SH7780_PCILAR0);
 	p4_out(0x00000000, SH7780_PCILSR1);
 	p4_out(0, SH7780_PCILAR1);
-	p4_out(0x08000000, SH7780_PCIMBAR0);
+	p4_out(CONFIG_SH7780_PCI_BAR, SH7780_PCIMBAR0);
 	p4_out(0x00000000, SH7780_PCIMBAR1);
 
 	p4_out(0xFD000000, SH7780_PCIMBR0);

drivers/serial/usbtty.c

@@ -215,7 +215,7 @@ static struct acm_config_desc acm_configuration_descriptors[NUM_CONFIGS] = {
 			.bLength =
 				sizeof(struct usb_endpoint_descriptor),
 			.bDescriptorType	= USB_DT_ENDPOINT,
-			.bEndpointAddress	= 0x01 | USB_DIR_IN,
+			.bEndpointAddress	= UDC_INT_ENDPOINT | USB_DIR_IN,
 			.bmAttributes		= USB_ENDPOINT_XFER_INT,
 			.wMaxPacketSize
 				= cpu_to_le16(CONFIG_USBD_SERIAL_INT_PKTSIZE),
@@ -241,7 +241,7 @@ static struct acm_config_desc acm_configuration_descriptors[NUM_CONFIGS] = {
 				.bLength		=
 					sizeof(struct usb_endpoint_descriptor),
 				.bDescriptorType	= USB_DT_ENDPOINT,
-				.bEndpointAddress	= 0x02 | USB_DIR_OUT,
+				.bEndpointAddress	= UDC_OUT_ENDPOINT | USB_DIR_OUT,
 				.bmAttributes		=
 					USB_ENDPOINT_XFER_BULK,
 				.wMaxPacketSize		=
@@ -252,7 +252,7 @@ static struct acm_config_desc acm_configuration_descriptors[NUM_CONFIGS] = {
 				.bLength		=
 					sizeof(struct usb_endpoint_descriptor),
 				.bDescriptorType	= USB_DT_ENDPOINT,
-				.bEndpointAddress	= 0x03 | USB_DIR_IN,
+				.bEndpointAddress	= UDC_IN_ENDPOINT | USB_DIR_IN,
 				.bmAttributes		=
 					USB_ENDPOINT_XFER_BULK,
 				.wMaxPacketSize		=
@@ -321,7 +321,7 @@ gserial_configuration_descriptors[NUM_CONFIGS] ={
 				.bLength =
 					sizeof(struct usb_endpoint_descriptor),
 				.bDescriptorType =	USB_DT_ENDPOINT,
-				.bEndpointAddress =	0x01 | USB_DIR_OUT,
+				.bEndpointAddress =	UDC_OUT_ENDPOINT | USB_DIR_OUT,
 				.bmAttributes =		USB_ENDPOINT_XFER_BULK,
 				.wMaxPacketSize =
 					cpu_to_le16(CONFIG_USBD_SERIAL_OUT_PKTSIZE),
@@ -331,7 +331,7 @@ gserial_configuration_descriptors[NUM_CONFIGS] ={
 				.bLength =
 					sizeof(struct usb_endpoint_descriptor),
 				.bDescriptorType =	USB_DT_ENDPOINT,
-				.bEndpointAddress =	0x02 | USB_DIR_IN,
+				.bEndpointAddress =	UDC_IN_ENDPOINT | USB_DIR_IN,
 				.bmAttributes =		USB_ENDPOINT_XFER_BULK,
 				.wMaxPacketSize =
 					cpu_to_le16(CONFIG_USBD_SERIAL_IN_PKTSIZE),
@@ -341,7 +341,7 @@ gserial_configuration_descriptors[NUM_CONFIGS] ={
 				.bLength =
 					sizeof(struct usb_endpoint_descriptor),
 				.bDescriptorType =	USB_DT_ENDPOINT,
-				.bEndpointAddress =	0x03 | USB_DIR_IN,
+				.bEndpointAddress =	UDC_INT_ENDPOINT | USB_DIR_IN,
 				.bmAttributes =		USB_ENDPOINT_XFER_INT,
 				.wMaxPacketSize =
 					cpu_to_le16(CONFIG_USBD_SERIAL_INT_PKTSIZE),

drivers/spi/mxc_spi.c

@@ -21,6 +21,7 @@
 #include <common.h>
 #include <malloc.h>
 #include <spi.h>
+#include <asm/errno.h>
 #include <asm/io.h>
 
 #ifdef CONFIG_MX27
@@ -32,6 +33,8 @@
 
 #else
 
+#include <asm/arch/mx31.h>
+
 #define MXC_CSPIRXDATA		0x00
 #define MXC_CSPITXDATA		0x04
 #define MXC_CSPICTRL		0x08
@@ -68,6 +71,7 @@ struct mxc_spi_slave {
 	struct spi_slave slave;
 	unsigned long	base;
 	u32		ctrl_reg;
+	int		gpio;
 };
 
 static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave)
@@ -85,26 +89,33 @@ static inline void reg_write(unsigned long addr, u32 val)
 	*(volatile unsigned long*)addr = val;
 }
 
-static u32 spi_xchg_single(struct spi_slave *slave, u32 data, int bitlen)
+static u32 spi_xchg_single(struct spi_slave *slave, u32 data, int bitlen,
+			   unsigned long flags)
 {
 	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
 	unsigned int cfg_reg = reg_read(mxcs->base + MXC_CSPICTRL);
 
-	if (MXC_CSPICTRL_BITCOUNT(bitlen - 1) != (cfg_reg & MXC_CSPICTRL_BITCOUNT(31))) {
-		cfg_reg = (cfg_reg & ~MXC_CSPICTRL_BITCOUNT(31)) |
-			MXC_CSPICTRL_BITCOUNT(bitlen - 1);
-		reg_write(mxcs->base + MXC_CSPICTRL, cfg_reg);
-	}
+	mxcs->ctrl_reg = (mxcs->ctrl_reg & ~MXC_CSPICTRL_BITCOUNT(31)) |
+		MXC_CSPICTRL_BITCOUNT(bitlen - 1);
+
+	if (cfg_reg != mxcs->ctrl_reg)
+		reg_write(mxcs->base + MXC_CSPICTRL, mxcs->ctrl_reg);
+
+	if (mxcs->gpio > 0 && (flags & SPI_XFER_BEGIN))
+		mx31_gpio_set(mxcs->gpio, mxcs->ctrl_reg & MXC_CSPICTRL_SSPOL);
 
 	reg_write(mxcs->base + MXC_CSPITXDATA, data);
 
-	cfg_reg |= MXC_CSPICTRL_XCH;
-
-	reg_write(mxcs->base + MXC_CSPICTRL, cfg_reg);
+	reg_write(mxcs->base + MXC_CSPICTRL, mxcs->ctrl_reg | MXC_CSPICTRL_XCH);
 
 	while (reg_read(mxcs->base + MXC_CSPICTRL) & MXC_CSPICTRL_XCH)
 		;
 
+	if (mxcs->gpio > 0 && (flags & SPI_XFER_END)) {
+		mx31_gpio_set(mxcs->gpio,
+			      !(mxcs->ctrl_reg & MXC_CSPICTRL_SSPOL));
+	}
+
 	return reg_read(mxcs->base + MXC_CSPIRXDATA);
 }
 
@@ -122,8 +133,17 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
 
 	for (i = 0, in_l = (u32 *)din, out_l = (u32 *)dout;
 	     i < n_blks;
-	     i++, in_l++, out_l++, bitlen -= 32)
-		*in_l = spi_xchg_single(slave, *out_l, bitlen);
+	     i++, in_l++, out_l++, bitlen -= 32) {
+		u32 data = spi_xchg_single(slave, *out_l, bitlen, flags);
+
+		/* Check if we're only transfering 8 or 16 bits */
+		if (!i) {
+			if (bitlen < 9)
+				*(u8 *)din = data;
+			else if (bitlen < 17)
+				*(u16 *)din = data;
+		}
+	}
 
 	return 0;
 }
@@ -132,16 +152,55 @@ void spi_init(void)
 {
 }
 
+static int decode_cs(struct mxc_spi_slave *mxcs, unsigned int cs)
+{
+	int ret;
+
+	/*
+	 * Some SPI devices require active chip-select over multiple
+	 * transactions, we achieve this using a GPIO. Still, the SPI
+	 * controller has to be configured to use one of its own chipselects.
+	 * To use this feature you have to call spi_setup_slave() with
+	 * cs = internal_cs | (gpio << 8), and you have to use some unused
+	 * on this SPI controller cs between 0 and 3.
+	 */
+	if (cs > 3) {
+		mxcs->gpio = cs >> 8;
+		cs &= 3;
+		ret = mx31_gpio_direction(mxcs->gpio, MX31_GPIO_DIRECTION_OUT);
+		if (ret) {
+			printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio);
+			return -EINVAL;
+		}
+	} else {
+		mxcs->gpio = -1;
+	}
+
+	return cs;
+}
+
 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 			unsigned int max_hz, unsigned int mode)
 {
 	unsigned int ctrl_reg;
 	struct mxc_spi_slave *mxcs;
+	int ret;
 
-	if (bus >= sizeof(spi_bases) / sizeof(spi_bases[0]) ||
-	    cs > 3)
+	if (bus >= ARRAY_SIZE(spi_bases))
 		return NULL;
 
+	mxcs = malloc(sizeof(struct mxc_spi_slave));
+	if (!mxcs)
+		return NULL;
+
+	ret = decode_cs(mxcs, cs);
+	if (ret < 0) {
+		free(mxcs);
+		return NULL;
+	}
+
+	cs = ret;
+
 	ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) |
 		MXC_CSPICTRL_BITCOUNT(31) |
 		MXC_CSPICTRL_DATARATE(7) | /* FIXME: calculate data rate */
@@ -155,10 +214,6 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 	if (mode & SPI_CS_HIGH)
 		ctrl_reg |= MXC_CSPICTRL_SSPOL;
 
-	mxcs = malloc(sizeof(struct mxc_spi_slave));
-	if (!mxcs)
-		return NULL;
-
 	mxcs->slave.bus = bus;
 	mxcs->slave.cs = cs;
 	mxcs->base = spi_bases[bus];
@@ -169,7 +224,9 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 
 void spi_free_slave(struct spi_slave *slave)
 {
-	free(slave);
+	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
+
+	free(mxcs);
 }
 
 int spi_claim_bus(struct spi_slave *slave)

drivers/video/Makefile

@@ -28,8 +28,10 @@ LIB	:= $(obj)libvideo.a
 COBJS-$(CONFIG_ATI_RADEON_FB) += ati_radeon_fb.o
 COBJS-$(CONFIG_ATMEL_LCD) += atmel_lcdfb.o
 COBJS-$(CONFIG_CFB_CONSOLE) += cfb_console.o
+COBJS-$(CONFIG_S6E63D6) += s6e63d6.o
 COBJS-$(CONFIG_VIDEO_CT69000) += ct69000.o
 COBJS-$(CONFIG_VIDEO_MB862xx) += mb862xx.o
+COBJS-$(CONFIG_VIDEO_MX3) += mx3fb.o
 COBJS-$(CONFIG_VIDEO_SED13806) += sed13806.o
 COBJS-$(CONFIG_SED156X) += sed156x.o
 COBJS-$(CONFIG_VIDEO_SM501) += sm501.o

drivers/video/mx3fb.c

@@ -0,0 +1,856 @@
+/*
+ * Copyright (C) 2009
+ * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <lcd.h>
+#include <asm/arch/mx31.h>
+#include <asm/arch/mx31-regs.h>
+#include <asm/errno.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void *lcd_base;			/* Start of framebuffer memory	*/
+void *lcd_console_address;	/* Start of console buffer	*/
+
+int lcd_line_length;
+int lcd_color_fg;
+int lcd_color_bg;
+
+short console_col;
+short console_row;
+
+void lcd_initcolregs(void)
+{
+}
+
+void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
+{
+}
+
+void lcd_disable(void)
+{
+}
+
+void lcd_panel_disable(void)
+{
+}
+
+#define msleep(a) udelay(a * 1000)
+
+#define XRES		240
+#define YRES		320
+#define PANEL_TYPE	IPU_PANEL_TFT
+#define PIXEL_CLK	185925
+#define PIXEL_FMT	IPU_PIX_FMT_RGB666
+#define H_START_WIDTH	9		/* left_margin */
+#define H_SYNC_WIDTH	1		/* hsync_len */
+#define H_END_WIDTH	(16 + 1)	/* right_margin + hsync_len */
+#define V_START_WIDTH	7		/* upper_margin */
+#define V_SYNC_WIDTH	1		/* vsync_len */
+#define V_END_WIDTH	(9 + 1)		/* lower_margin + vsync_len */
+#define SIG_POL		(DI_D3_DRDY_SHARP_POL | DI_D3_CLK_POL)
+#define IF_CONF		0
+#define IF_CLK_DIV	0x175
+
+#define LCD_COLOR_IPU	LCD_COLOR16
+
+static ushort colormap[256];
+
+vidinfo_t panel_info = {
+	.vl_col		= XRES,
+	.vl_row		= YRES,
+	.vl_bpix	= LCD_COLOR_IPU,
+	.cmap		= colormap,
+};
+
+#define BIT_PER_PIXEL	NBITS(LCD_COLOR_IPU)
+
+/* IPU DMA Controller channel definitions. */
+enum ipu_channel {
+	IDMAC_IC_0 = 0,		/* IC (encoding task) to memory */
+	IDMAC_IC_1 = 1,		/* IC (viewfinder task) to memory */
+	IDMAC_ADC_0 = 1,
+	IDMAC_IC_2 = 2,
+	IDMAC_ADC_1 = 2,
+	IDMAC_IC_3 = 3,
+	IDMAC_IC_4 = 4,
+	IDMAC_IC_5 = 5,
+	IDMAC_IC_6 = 6,
+	IDMAC_IC_7 = 7,		/* IC (sensor data) to memory */
+	IDMAC_IC_8 = 8,
+	IDMAC_IC_9 = 9,
+	IDMAC_IC_10 = 10,
+	IDMAC_IC_11 = 11,
+	IDMAC_IC_12 = 12,
+	IDMAC_IC_13 = 13,
+	IDMAC_SDC_0 = 14,	/* Background synchronous display data */
+	IDMAC_SDC_1 = 15,	/* Foreground data (overlay) */
+	IDMAC_SDC_2 = 16,
+	IDMAC_SDC_3 = 17,
+	IDMAC_ADC_2 = 18,
+	IDMAC_ADC_3 = 19,
+	IDMAC_ADC_4 = 20,
+	IDMAC_ADC_5 = 21,
+	IDMAC_ADC_6 = 22,
+	IDMAC_ADC_7 = 23,
+	IDMAC_PF_0 = 24,
+	IDMAC_PF_1 = 25,
+	IDMAC_PF_2 = 26,
+	IDMAC_PF_3 = 27,
+	IDMAC_PF_4 = 28,
+	IDMAC_PF_5 = 29,
+	IDMAC_PF_6 = 30,
+	IDMAC_PF_7 = 31,
+};
+
+/* More formats can be copied from the Linux driver if needed */
+enum pixel_fmt {
+	/* 2 bytes */
+	IPU_PIX_FMT_RGB565,
+	IPU_PIX_FMT_RGB666,
+	IPU_PIX_FMT_BGR666,
+	/* 3 bytes */
+	IPU_PIX_FMT_RGB24,
+};
+
+struct pixel_fmt_cfg {
+	u32	b0;
+	u32	b1;
+	u32	b2;
+	u32	acc;
+};
+
+static struct pixel_fmt_cfg fmt_cfg[] = {
+	[IPU_PIX_FMT_RGB24] = {
+		0x1600AAAA, 0x00E05555, 0x00070000, 3,
+	},
+	[IPU_PIX_FMT_RGB666] = {
+		0x0005000F, 0x000B000F, 0x0011000F, 1,
+	},
+	[IPU_PIX_FMT_BGR666] = {
+		0x0011000F, 0x000B000F, 0x0005000F, 1,
+	},
+	[IPU_PIX_FMT_RGB565] = {
+		0x0004003F, 0x000A000F, 0x000F003F, 1,
+	}
+};
+
+enum ipu_panel {
+	IPU_PANEL_SHARP_TFT,
+	IPU_PANEL_TFT,
+};
+
+/* IPU Common registers */
+/* IPU_CONF and its bits already defined in mx31-regs.h */
+#define IPU_CHA_BUF0_RDY	(0x04 + IPU_BASE)
+#define IPU_CHA_BUF1_RDY	(0x08 + IPU_BASE)
+#define IPU_CHA_DB_MODE_SEL	(0x0C + IPU_BASE)
+#define IPU_CHA_CUR_BUF		(0x10 + IPU_BASE)
+#define IPU_FS_PROC_FLOW	(0x14 + IPU_BASE)
+#define IPU_FS_DISP_FLOW	(0x18 + IPU_BASE)
+#define IPU_TASKS_STAT		(0x1C + IPU_BASE)
+#define IPU_IMA_ADDR		(0x20 + IPU_BASE)
+#define IPU_IMA_DATA		(0x24 + IPU_BASE)
+#define IPU_INT_CTRL_1		(0x28 + IPU_BASE)
+#define IPU_INT_CTRL_2		(0x2C + IPU_BASE)
+#define IPU_INT_CTRL_3		(0x30 + IPU_BASE)
+#define IPU_INT_CTRL_4		(0x34 + IPU_BASE)
+#define IPU_INT_CTRL_5		(0x38 + IPU_BASE)
+#define IPU_INT_STAT_1		(0x3C + IPU_BASE)
+#define IPU_INT_STAT_2		(0x40 + IPU_BASE)
+#define IPU_INT_STAT_3		(0x44 + IPU_BASE)
+#define IPU_INT_STAT_4		(0x48 + IPU_BASE)
+#define IPU_INT_STAT_5		(0x4C + IPU_BASE)
+#define IPU_BRK_CTRL_1		(0x50 + IPU_BASE)
+#define IPU_BRK_CTRL_2		(0x54 + IPU_BASE)
+#define IPU_BRK_STAT		(0x58 + IPU_BASE)
+#define IPU_DIAGB_CTRL		(0x5C + IPU_BASE)
+
+/* Image Converter Registers */
+#define IC_CONF			(0x88 + IPU_BASE)
+#define IC_PRP_ENC_RSC		(0x8C + IPU_BASE)
+#define IC_PRP_VF_RSC		(0x90 + IPU_BASE)
+#define IC_PP_RSC		(0x94 + IPU_BASE)
+#define IC_CMBP_1		(0x98 + IPU_BASE)
+#define IC_CMBP_2		(0x9C + IPU_BASE)
+#define PF_CONF			(0xA0 + IPU_BASE)
+#define IDMAC_CONF		(0xA4 + IPU_BASE)
+#define IDMAC_CHA_EN		(0xA8 + IPU_BASE)
+#define IDMAC_CHA_PRI		(0xAC + IPU_BASE)
+#define IDMAC_CHA_BUSY		(0xB0 + IPU_BASE)
+
+/* Image Converter Register bits */
+#define IC_CONF_PRPENC_EN	0x00000001
+#define IC_CONF_PRPENC_CSC1	0x00000002
+#define IC_CONF_PRPENC_ROT_EN	0x00000004
+#define IC_CONF_PRPVF_EN	0x00000100
+#define IC_CONF_PRPVF_CSC1	0x00000200
+#define IC_CONF_PRPVF_CSC2	0x00000400
+#define IC_CONF_PRPVF_CMB	0x00000800
+#define IC_CONF_PRPVF_ROT_EN	0x00001000
+#define IC_CONF_PP_EN		0x00010000
+#define IC_CONF_PP_CSC1		0x00020000
+#define IC_CONF_PP_CSC2		0x00040000
+#define IC_CONF_PP_CMB		0x00080000
+#define IC_CONF_PP_ROT_EN	0x00100000
+#define IC_CONF_IC_GLB_LOC_A	0x10000000
+#define IC_CONF_KEY_COLOR_EN	0x20000000
+#define IC_CONF_RWS_EN		0x40000000
+#define IC_CONF_CSI_MEM_WR_EN	0x80000000
+
+/* SDC Registers */
+#define SDC_COM_CONF		(0xB4 + IPU_BASE)
+#define SDC_GW_CTRL		(0xB8 + IPU_BASE)
+#define SDC_FG_POS		(0xBC + IPU_BASE)
+#define SDC_BG_POS		(0xC0 + IPU_BASE)
+#define SDC_CUR_POS		(0xC4 + IPU_BASE)
+#define SDC_PWM_CTRL		(0xC8 + IPU_BASE)
+#define SDC_CUR_MAP		(0xCC + IPU_BASE)
+#define SDC_HOR_CONF		(0xD0 + IPU_BASE)
+#define SDC_VER_CONF		(0xD4 + IPU_BASE)
+#define SDC_SHARP_CONF_1	(0xD8 + IPU_BASE)
+#define SDC_SHARP_CONF_2	(0xDC + IPU_BASE)
+
+/* Register bits */
+#define SDC_COM_TFT_COLOR	0x00000001UL
+#define SDC_COM_FG_EN		0x00000010UL
+#define SDC_COM_GWSEL		0x00000020UL
+#define SDC_COM_GLB_A		0x00000040UL
+#define SDC_COM_KEY_COLOR_G	0x00000080UL
+#define SDC_COM_BG_EN		0x00000200UL
+#define SDC_COM_SHARP		0x00001000UL
+
+#define SDC_V_SYNC_WIDTH_L	0x00000001UL
+
+/* Display Interface registers */
+#define DI_DISP_IF_CONF		(0x0124 + IPU_BASE)
+#define DI_DISP_SIG_POL		(0x0128 + IPU_BASE)
+#define DI_SER_DISP1_CONF	(0x012C + IPU_BASE)
+#define DI_SER_DISP2_CONF	(0x0130 + IPU_BASE)
+#define DI_HSP_CLK_PER		(0x0134 + IPU_BASE)
+#define DI_DISP0_TIME_CONF_1	(0x0138 + IPU_BASE)
+#define DI_DISP0_TIME_CONF_2	(0x013C + IPU_BASE)
+#define DI_DISP0_TIME_CONF_3	(0x0140 + IPU_BASE)
+#define DI_DISP1_TIME_CONF_1	(0x0144 + IPU_BASE)
+#define DI_DISP1_TIME_CONF_2	(0x0148 + IPU_BASE)
+#define DI_DISP1_TIME_CONF_3	(0x014C + IPU_BASE)
+#define DI_DISP2_TIME_CONF_1	(0x0150 + IPU_BASE)
+#define DI_DISP2_TIME_CONF_2	(0x0154 + IPU_BASE)
+#define DI_DISP2_TIME_CONF_3	(0x0158 + IPU_BASE)
+#define DI_DISP3_TIME_CONF	(0x015C + IPU_BASE)
+#define DI_DISP0_DB0_MAP	(0x0160 + IPU_BASE)
+#define DI_DISP0_DB1_MAP	(0x0164 + IPU_BASE)
+#define DI_DISP0_DB2_MAP	(0x0168 + IPU_BASE)
+#define DI_DISP0_CB0_MAP	(0x016C + IPU_BASE)
+#define DI_DISP0_CB1_MAP	(0x0170 + IPU_BASE)
+#define DI_DISP0_CB2_MAP	(0x0174 + IPU_BASE)
+#define DI_DISP1_DB0_MAP	(0x0178 + IPU_BASE)
+#define DI_DISP1_DB1_MAP	(0x017C + IPU_BASE)
+#define DI_DISP1_DB2_MAP	(0x0180 + IPU_BASE)
+#define DI_DISP1_CB0_MAP	(0x0184 + IPU_BASE)
+#define DI_DISP1_CB1_MAP	(0x0188 + IPU_BASE)
+#define DI_DISP1_CB2_MAP	(0x018C + IPU_BASE)
+#define DI_DISP2_DB0_MAP	(0x0190 + IPU_BASE)
+#define DI_DISP2_DB1_MAP	(0x0194 + IPU_BASE)
+#define DI_DISP2_DB2_MAP	(0x0198 + IPU_BASE)
+#define DI_DISP2_CB0_MAP	(0x019C + IPU_BASE)
+#define DI_DISP2_CB1_MAP	(0x01A0 + IPU_BASE)
+#define DI_DISP2_CB2_MAP	(0x01A4 + IPU_BASE)
+#define DI_DISP3_B0_MAP		(0x01A8 + IPU_BASE)
+#define DI_DISP3_B1_MAP		(0x01AC + IPU_BASE)
+#define DI_DISP3_B2_MAP		(0x01B0 + IPU_BASE)
+#define DI_DISP_ACC_CC		(0x01B4 + IPU_BASE)
+#define DI_DISP_LLA_CONF	(0x01B8 + IPU_BASE)
+#define DI_DISP_LLA_DATA	(0x01BC + IPU_BASE)
+
+/* DI_DISP_SIG_POL bits */
+#define DI_D3_VSYNC_POL		(1 << 28)
+#define DI_D3_HSYNC_POL		(1 << 27)
+#define DI_D3_DRDY_SHARP_POL	(1 << 26)
+#define DI_D3_CLK_POL		(1 << 25)
+#define DI_D3_DATA_POL		(1 << 24)
+
+/* DI_DISP_IF_CONF bits */
+#define DI_D3_CLK_IDLE		(1 << 26)
+#define DI_D3_CLK_SEL		(1 << 25)
+#define DI_D3_DATAMSK		(1 << 24)
+
+#define IOMUX_PADNUM_MASK	0x1ff
+#define IOMUX_GPIONUM_SHIFT	9
+#define IOMUX_GPIONUM_MASK	(0xff << IOMUX_GPIONUM_SHIFT)
+
+#define IOMUX_PIN(gpionum, padnum) ((padnum) & IOMUX_PADNUM_MASK)
+
+#define IOMUX_MODE_L(pin, mode) IOMUX_MODE(((pin) + 0xc) ^ 3, mode)
+
+enum lcd_pin {
+	MX31_PIN_D3_SPL		= IOMUX_PIN(0xff,  19),
+	MX31_PIN_D3_CLS		= IOMUX_PIN(0xff,  20),
+	MX31_PIN_D3_REV		= IOMUX_PIN(0xff,  21),
+	MX31_PIN_CONTRAST	= IOMUX_PIN(0xff,  22),
+	MX31_PIN_VSYNC3		= IOMUX_PIN(0xff,  23),
+
+	MX31_PIN_DRDY0		= IOMUX_PIN(0xff,  33),
+	MX31_PIN_FPSHIFT	= IOMUX_PIN(0xff,  34),
+	MX31_PIN_HSYNC		= IOMUX_PIN(0xff,  35),
+
+	MX31_PIN_LD17		= IOMUX_PIN(0xff,  37),
+	MX31_PIN_LD16		= IOMUX_PIN(0xff,  38),
+	MX31_PIN_LD15		= IOMUX_PIN(0xff,  39),
+	MX31_PIN_LD14		= IOMUX_PIN(0xff,  40),
+	MX31_PIN_LD13		= IOMUX_PIN(0xff,  41),
+	MX31_PIN_LD12		= IOMUX_PIN(0xff,  42),
+	MX31_PIN_LD11		= IOMUX_PIN(0xff,  43),
+	MX31_PIN_LD10		= IOMUX_PIN(0xff,  44),
+	MX31_PIN_LD9		= IOMUX_PIN(0xff,  45),
+	MX31_PIN_LD8		= IOMUX_PIN(0xff,  46),
+	MX31_PIN_LD7		= IOMUX_PIN(0xff,  47),
+	MX31_PIN_LD6		= IOMUX_PIN(0xff,  48),
+	MX31_PIN_LD5		= IOMUX_PIN(0xff,  49),
+	MX31_PIN_LD4		= IOMUX_PIN(0xff,  50),
+	MX31_PIN_LD3		= IOMUX_PIN(0xff,  51),
+	MX31_PIN_LD2		= IOMUX_PIN(0xff,  52),
+	MX31_PIN_LD1		= IOMUX_PIN(0xff,  53),
+	MX31_PIN_LD0		= IOMUX_PIN(0xff,  54),
+};
+
+struct chan_param_mem_planar {
+	/* Word 0 */
+	u32	xv:10;
+	u32	yv:10;
+	u32	xb:12;
+
+	u32	yb:12;
+	u32	res1:2;
+	u32	nsb:1;
+	u32	lnpb:6;
+	u32	ubo_l:11;
+
+	u32	ubo_h:15;
+	u32	vbo_l:17;
+
+	u32	vbo_h:9;
+	u32	res2:3;
+	u32	fw:12;
+	u32	fh_l:8;
+
+	u32	fh_h:4;
+	u32	res3:28;
+
+	/* Word 1 */
+	u32	eba0;
+
+	u32	eba1;
+
+	u32	bpp:3;
+	u32	sl:14;
+	u32	pfs:3;
+	u32	bam:3;
+	u32	res4:2;
+	u32	npb:6;
+	u32	res5:1;
+
+	u32	sat:2;
+	u32	res6:30;
+} __attribute__ ((packed));
+
+struct chan_param_mem_interleaved {
+	/* Word 0 */
+	u32	xv:10;
+	u32	yv:10;
+	u32	xb:12;
+
+	u32	yb:12;
+	u32	sce:1;
+	u32	res1:1;
+	u32	nsb:1;
+	u32	lnpb:6;
+	u32	sx:10;
+	u32	sy_l:1;
+
+	u32	sy_h:9;
+	u32	ns:10;
+	u32	sm:10;
+	u32	sdx_l:3;
+
+	u32	sdx_h:2;
+	u32	sdy:5;
+	u32	sdrx:1;
+	u32	sdry:1;
+	u32	sdr1:1;
+	u32	res2:2;
+	u32	fw:12;
+	u32	fh_l:8;
+
+	u32	fh_h:4;
+	u32	res3:28;
+
+	/* Word 1 */
+	u32	eba0;
+
+	u32	eba1;
+
+	u32	bpp:3;
+	u32	sl:14;
+	u32	pfs:3;
+	u32	bam:3;
+	u32	res4:2;
+	u32	npb:6;
+	u32	res5:1;
+
+	u32	sat:2;
+	u32	scc:1;
+	u32	ofs0:5;
+	u32	ofs1:5;
+	u32	ofs2:5;
+	u32	ofs3:5;
+	u32	wid0:3;
+	u32	wid1:3;
+	u32	wid2:3;
+
+	u32	wid3:3;
+	u32	dec_sel:1;
+	u32	res6:28;
+} __attribute__ ((packed));
+
+union chan_param_mem {
+	struct chan_param_mem_planar		pp;
+	struct chan_param_mem_interleaved	ip;
+};
+
+static inline u32 reg_read(unsigned long reg)
+{
+	return __REG(reg);
+}
+
+static inline void reg_write(u32 value, unsigned long reg)
+{
+	__REG(reg) = value;
+}
+
+/*
+ * sdc_init_panel() - initialize a synchronous LCD panel.
+ * @width:		width of panel in pixels.
+ * @height:		height of panel in pixels.
+ * @pixel_fmt:		pixel format of buffer as FOURCC ASCII code.
+ * @return:		0 on success or negative error code on failure.
+ */
+static int sdc_init_panel(u16 width, u16 height, enum pixel_fmt pixel_fmt)
+{
+	u32 reg;
+	uint32_t old_conf;
+
+	/* Init panel size and blanking periods */
+	reg = ((H_SYNC_WIDTH - 1) << 26) |
+		((u32)(width + H_START_WIDTH + H_END_WIDTH - 1) << 16);
+	reg_write(reg, SDC_HOR_CONF);
+
+	reg = ((V_SYNC_WIDTH - 1) << 26) | SDC_V_SYNC_WIDTH_L |
+		((u32)(height + V_START_WIDTH + V_END_WIDTH - 1) << 16);
+	reg_write(reg, SDC_VER_CONF);
+
+	switch (PANEL_TYPE) {
+	case IPU_PANEL_SHARP_TFT:
+		reg_write(0x00FD0102L, SDC_SHARP_CONF_1);
+		reg_write(0x00F500F4L, SDC_SHARP_CONF_2);
+		reg_write(SDC_COM_SHARP | SDC_COM_TFT_COLOR, SDC_COM_CONF);
+		break;
+	case IPU_PANEL_TFT:
+		reg_write(SDC_COM_TFT_COLOR, SDC_COM_CONF);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	/* Init clocking */
+
+	/*
+	 * Calculate divider: fractional part is 4 bits so simply multiple by
+	 * 2^4 to get fractional part, as long as we stay under ~250MHz and on
+	 * i.MX31 it (HSP_CLK) is <= 178MHz. Currently 128.267MHz
+	 */
+
+	reg_write((((IF_CLK_DIV / 8) - 1) << 22) |
+			IF_CLK_DIV, DI_DISP3_TIME_CONF);
+
+	/* DI settings */
+	old_conf = reg_read(DI_DISP_IF_CONF) & 0x78FFFFFF;
+	reg_write(old_conf | IF_CONF, DI_DISP_IF_CONF);
+
+	old_conf = reg_read(DI_DISP_SIG_POL) & 0xE0FFFFFF;
+	reg_write(old_conf | SIG_POL, DI_DISP_SIG_POL);
+
+	reg_write(fmt_cfg[pixel_fmt].b0, DI_DISP3_B0_MAP);
+	reg_write(fmt_cfg[pixel_fmt].b1, DI_DISP3_B1_MAP);
+	reg_write(fmt_cfg[pixel_fmt].b2, DI_DISP3_B2_MAP);
+	reg_write(reg_read(DI_DISP_ACC_CC) |
+		  ((fmt_cfg[pixel_fmt].acc - 1) << 12), DI_DISP_ACC_CC);
+
+	return 0;
+}
+
+static void ipu_ch_param_set_size(union chan_param_mem *params,
+				  uint32_t pixel_fmt, uint16_t width,
+				  uint16_t height, uint16_t stride)
+{
+	params->pp.fw		= width - 1;
+	params->pp.fh_l		= height - 1;
+	params->pp.fh_h		= (height - 1) >> 8;
+	params->pp.sl		= stride - 1;
+
+	/* See above, for further formats see the Linux driver */
+	switch (pixel_fmt) {
+	case IPU_PIX_FMT_RGB565:
+		params->ip.bpp	= 2;
+		params->ip.pfs	= 4;
+		params->ip.npb	= 7;
+		params->ip.sat	= 2;		/* SAT = 32-bit access */
+		params->ip.ofs0	= 0;		/* Red bit offset */
+		params->ip.ofs1	= 5;		/* Green bit offset */
+		params->ip.ofs2	= 11;		/* Blue bit offset */
+		params->ip.ofs3	= 16;		/* Alpha bit offset */
+		params->ip.wid0	= 4;		/* Red bit width - 1 */
+		params->ip.wid1	= 5;		/* Green bit width - 1 */
+		params->ip.wid2	= 4;		/* Blue bit width - 1 */
+		break;
+	case IPU_PIX_FMT_RGB24:
+		params->ip.bpp	= 1;		/* 24 BPP & RGB PFS */
+		params->ip.pfs	= 4;
+		params->ip.npb	= 7;
+		params->ip.sat	= 2;		/* SAT = 32-bit access */
+		params->ip.ofs0	= 16;		/* Red bit offset */
+		params->ip.ofs1	= 8;		/* Green bit offset */
+		params->ip.ofs2	= 0;		/* Blue bit offset */
+		params->ip.ofs3	= 24;		/* Alpha bit offset */
+		params->ip.wid0	= 7;		/* Red bit width - 1 */
+		params->ip.wid1	= 7;		/* Green bit width - 1 */
+		params->ip.wid2	= 7;		/* Blue bit width - 1 */
+		break;
+	default:
+		break;
+	}
+
+	params->pp.nsb = 1;
+}
+
+static void ipu_ch_param_set_buffer(union chan_param_mem *params,
+				    void *buf0, void *buf1)
+{
+	params->pp.eba0 = (u32)buf0;
+	params->pp.eba1 = (u32)buf1;
+}
+
+static void ipu_write_param_mem(uint32_t addr, uint32_t *data,
+				uint32_t num_words)
+{
+	for (; num_words > 0; num_words--) {
+		reg_write(addr, IPU_IMA_ADDR);
+		reg_write(*data++, IPU_IMA_DATA);
+		addr++;
+		if ((addr & 0x7) == 5) {
+			addr &= ~0x7;	/* set to word 0 */
+			addr += 8;	/* increment to next row */
+		}
+	}
+}
+
+static uint32_t bpp_to_pixfmt(int bpp)
+{
+	switch (bpp) {
+	case 16:
+		return IPU_PIX_FMT_RGB565;
+	default:
+		return 0;
+	}
+}
+
+static uint32_t dma_param_addr(enum ipu_channel channel)
+{
+	/* Channel Parameter Memory */
+	return 0x10000 | (channel << 4);
+}
+
+static void ipu_init_channel_buffer(enum ipu_channel channel, void *fbmem)
+{
+	union chan_param_mem params = {};
+	uint32_t reg;
+	uint32_t stride_bytes;
+
+	stride_bytes = (XRES * ((BIT_PER_PIXEL + 7) / 8) + 3) & ~3;
+
+	/* Build parameter memory data for DMA channel */
+	ipu_ch_param_set_size(&params, bpp_to_pixfmt(BIT_PER_PIXEL),
+			      XRES, YRES, stride_bytes);
+	ipu_ch_param_set_buffer(&params, fbmem, NULL);
+	params.pp.bam = 0;
+	/* Some channels (rotation) have restriction on burst length */
+
+	switch (channel) {
+	case IDMAC_SDC_0:
+		/* In original code only IPU_PIX_FMT_RGB565 was setting burst */
+		params.pp.npb = 16 - 1;
+		break;
+	default:
+		break;
+	}
+
+	ipu_write_param_mem(dma_param_addr(channel), (uint32_t *)&params, 10);
+
+	/* Disable double-buffering */
+	reg = reg_read(IPU_CHA_DB_MODE_SEL);
+	reg &= ~(1UL << channel);
+	reg_write(reg, IPU_CHA_DB_MODE_SEL);
+}
+
+static void ipu_channel_set_priority(enum ipu_channel channel,
+				     int prio)
+{
+	u32 reg = reg_read(IDMAC_CHA_PRI);
+
+	if (prio)
+		reg |= 1UL << channel;
+	else
+		reg &= ~(1UL << channel);
+
+	reg_write(reg, IDMAC_CHA_PRI);
+}
+
+/*
+ * ipu_enable_channel() - enable an IPU channel.
+ * @channel:	channel ID.
+ * @return:	0 on success or negative error code on failure.
+ */
+static int ipu_enable_channel(enum ipu_channel channel)
+{
+	uint32_t reg;
+
+	/* Reset to buffer 0 */
+	reg_write(1UL << channel, IPU_CHA_CUR_BUF);
+
+	switch (channel) {
+	case IDMAC_SDC_0:
+		ipu_channel_set_priority(channel, 1);
+		break;
+	default:
+		break;
+	}
+
+	reg = reg_read(IDMAC_CHA_EN);
+	reg_write(reg | (1UL << channel), IDMAC_CHA_EN);
+
+	return 0;
+}
+
+static int ipu_update_channel_buffer(enum ipu_channel channel, void *buf)
+{
+	uint32_t reg;
+
+	reg = reg_read(IPU_CHA_BUF0_RDY);
+	if (reg & (1UL << channel))
+		return -EACCES;
+
+	/* 44.3.3.1.9 - Row Number 1 (WORD1, offset 0) */
+	reg_write(dma_param_addr(channel) + 0x0008UL, IPU_IMA_ADDR);
+	reg_write((u32)buf, IPU_IMA_DATA);
+
+	return 0;
+}
+
+static int idmac_tx_submit(enum ipu_channel channel, void *buf)
+{
+	int ret;
+
+	ipu_init_channel_buffer(channel, buf);
+
+
+	/* ipu_idmac.c::ipu_submit_channel_buffers() */
+	ret = ipu_update_channel_buffer(channel, buf);
+	if (ret < 0)
+		return ret;
+
+	/* ipu_idmac.c::ipu_select_buffer() */
+	/* Mark buffer 0 as ready. */
+	reg_write(1UL << channel, IPU_CHA_BUF0_RDY);
+
+
+	ret = ipu_enable_channel(channel);
+	return ret;
+}
+
+static void sdc_enable_channel(void *fbmem)
+{
+	int ret;
+	u32 reg;
+
+	ret = idmac_tx_submit(IDMAC_SDC_0, fbmem);
+
+	/* mx3fb.c::sdc_fb_init() */
+	if (ret >= 0) {
+		reg = reg_read(SDC_COM_CONF);
+		reg_write(reg | SDC_COM_BG_EN, SDC_COM_CONF);
+	}
+
+	/*
+	 * Attention! Without this msleep the channel keeps generating
+	 * interrupts. Next sdc_set_brightness() is going to be called
+	 * from mx3fb_blank().
+	 */
+	msleep(2);
+}
+
+/*
+ * mx3fb_set_par() - set framebuffer parameters and change the operating mode.
+ * @return:	0 on success or negative error code on failure.
+ */
+static int mx3fb_set_par(void)
+{
+	int ret;
+
+	ret = sdc_init_panel(XRES, YRES, PIXEL_FMT);
+	if (ret < 0)
+		return ret;
+
+	reg_write((H_START_WIDTH << 16) | V_START_WIDTH, SDC_BG_POS);
+
+	return 0;
+}
+
+/* References in this function refer to respective Linux kernel sources */
+void lcd_enable(void)
+{
+	u32 reg;
+
+	/* pcm037.c::mxc_board_init() */
+
+	/* Display Interface #3 */
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD0, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD1, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD2, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD3, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD4, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD5, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD6, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD7, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD8, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD9, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD10, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD11, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD12, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD13, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD14, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD15, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD16, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD17, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_VSYNC3, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_HSYNC, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_FPSHIFT, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_DRDY0, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_D3_REV, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_CONTRAST, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_D3_SPL, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_D3_CLS, MUX_CTL_FUNC));
+
+
+	/* ipu_idmac.c::ipu_probe() */
+
+	/* Start the clock */
+	__REG(CCM_CGR1) = __REG(CCM_CGR1) | (3 << 22);
+
+
+	/* ipu_idmac.c::ipu_idmac_init() */
+
+	/* Service request counter to maximum - shouldn't be needed */
+	reg_write(0x00000070, IDMAC_CONF);
+
+
+	/* ipu_idmac.c::ipu_init_channel() */
+
+	/* Enable IPU sub modules */
+	reg = reg_read(IPU_CONF) | IPU_CONF_SDC_EN | IPU_CONF_DI_EN;
+	reg_write(reg, IPU_CONF);
+
+
+	/* mx3fb.c::init_fb_chan() */
+
+	/* set Display Interface clock period */
+	reg_write(0x00100010L, DI_HSP_CLK_PER);
+	/* Might need to trigger HSP clock change - see 44.3.3.8.5 */
+
+
+	/* mx3fb.c::sdc_set_brightness() */
+
+	/* This might be board-specific */
+	reg_write(0x03000000UL | 255 << 16, SDC_PWM_CTRL);
+
+
+	/* mx3fb.c::sdc_set_global_alpha() */
+
+	/* Use global - not per-pixel - Alpha-blending */
+	reg = reg_read(SDC_GW_CTRL) & 0x00FFFFFFL;
+	reg_write(reg | ((uint32_t) 0xff << 24), SDC_GW_CTRL);
+
+	reg = reg_read(SDC_COM_CONF);
+	reg_write(reg | SDC_COM_GLB_A, SDC_COM_CONF);
+
+
+	/* mx3fb.c::sdc_set_color_key() */
+
+	/* Disable colour-keying for background */
+	reg = reg_read(SDC_COM_CONF) &
+		~(SDC_COM_GWSEL | SDC_COM_KEY_COLOR_G);
+	reg_write(reg, SDC_COM_CONF);
+
+
+	mx3fb_set_par();
+
+	sdc_enable_channel(lcd_base);
+
+	/*
+	 * Linux driver calls sdc_set_brightness() here again,
+	 * once is enough for us
+	 */
+}
+
+void lcd_ctrl_init(void *lcdbase)
+{
+	u32 mem_len = XRES * YRES * BIT_PER_PIXEL / 8;
+	/*
+	 * We rely on lcdbase being a physical address, i.e., either MMU off,
+	 * or 1-to-1 mapping. Might want to add some virt2phys here.
+	 */
+	if (!lcdbase)
+		return;
+
+	memset(lcdbase, 0, mem_len);
+}
+
+ulong calc_fbsize(void)
+{
+	return ((panel_info.vl_col * panel_info.vl_row *
+		NBITS(panel_info.vl_bpix)) / 8) + PAGE_SIZE;
+}
+
+int overwrite_console(void)
+{
+	/* Keep stdout / stderr on serial, our LCD is for splashscreen only */
+	return 1;
+}

drivers/video/s6e63d6.c

@@ -0,0 +1,76 @@
+/*
+ * Copyright (C) 2009
+ * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <spi.h>
+#include <s6e63d6.h>
+
+/*
+ * Each transfer is performed as:
+ * 1. chip-select active
+ * 2. send 8-bit start code
+ * 3. send 16-bit data
+ * 4. chip-select inactive
+ */
+static int send_word(struct s6e63d6 *data, u8 rs, u16 word)
+{
+	/*
+	 * The start byte looks like (binary):
+	 * 01110<ID><RS><R/W>
+	 * RS is 0 for index or 1 for data, and R/W is 0 for write.
+	 */
+	u32 buf8 = 0x70 | data->id | (rs & 2);
+	u32 buf16 = cpu_to_le16(word);
+	u32 buf_in;
+	int err;
+
+	err = spi_xfer(data->slave, 8, &buf8, &buf_in, SPI_XFER_BEGIN);
+	if (err)
+		return err;
+
+	return spi_xfer(data->slave, 16, &buf16, &buf_in, SPI_XFER_END);
+}
+
+/* Index and param differ in Register Select bit */
+int s6e63d6_index(struct s6e63d6 *data, u8 idx)
+{
+	return send_word(data, 0, idx);
+}
+
+int s6e63d6_param(struct s6e63d6 *data, u16 param)
+{
+	return send_word(data, 2, param);
+}
+
+int s6e63d6_init(struct s6e63d6 *data)
+{
+	if (data->id != 0 && data->id != 4) {
+		printf("s6e63d6: invalid ID %u\n", data->id);
+		return 1;
+	}
+
+	data->slave = spi_setup_slave(data->bus, data->cs, 100000, SPI_MODE_3);
+	if (!data->slave)
+		return 1;
+
+	return 0;
+}

examples/.gitignore

@@ -6,5 +6,6 @@
 /timer
 /sched
 /smc91111_eeprom
+/smc911x_eeprom
 *.bin
 *.srec

examples/Makefile

@@ -105,9 +105,10 @@ BIN	+= sched.bin
 endif
 
 ifeq ($(ARCH),blackfin)
-ELF	+= smc91111_eeprom
-SREC	+= smc91111_eeprom.srec
-BIN	+= smc91111_eeprom.bin
+BFIN_BIN = smc91111_eeprom smc911x_eeprom
+ELF	+= $(BFIN_BIN)
+SREC	+= $(addsuffix .srec,$(BFIN_BIN))
+BIN	+= $(addsuffix .bin,$(BFIN_BIN))
 endif
 
 # The following example is pretty 8xx specific...

examples/smc911x_eeprom.c

@@ -0,0 +1,383 @@
+/*
+ * smc911x_eeprom.c - EEPROM interface to SMC911x parts.
+ * Only tested on SMSC9118 though ...
+ *
+ * Copyright 2004-2008 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ *
+ * Based on smc91111_eeprom.c which:
+ * Heavily borrowed from the following peoples GPL'ed software:
+ *  - Wolfgang Denk, DENX Software Engineering, wd@denx.de
+ *       Das U-boot
+ *  - Ladislav Michl ladis@linux-mips.org
+ *       A rejected patch on the U-Boot mailing list
+ */
+
+#include <common.h>
+#include <exports.h>
+
+#ifdef CONFIG_DRIVER_SMC911X
+
+#include "../drivers/net/smc911x.h"
+
+/**
+ *	smsc_ctrlc - detect press of CTRL+C (common ctrlc() isnt exported!?)
+ */
+static int smsc_ctrlc(void)
+{
+	return (tstc() && getc() == 0x03);
+}
+
+/**
+ *	usage - dump usage information
+ */
+static void usage(void)
+{
+	puts(
+		"MAC/EEPROM Commands:\n"
+		" P : Print the MAC addresses\n"
+		" D : Dump the EEPROM contents\n"
+		" M : Dump the MAC contents\n"
+		" C : Copy the MAC address from the EEPROM to the MAC\n"
+		" W : Write a register in the EEPROM or in the MAC\n"
+		" Q : Quit\n"
+		"\n"
+		"Some commands take arguments:\n"
+		" W <E|M> <register> <value>\n"
+		"    E: EEPROM   M: MAC\n"
+	);
+}
+
+/**
+ *	dump_regs - dump the MAC registers
+ *
+ * Registers 0x00 - 0x50 are FIFOs.  The 0x50+ are the control registers
+ * and they're all 32bits long.  0xB8+ are reserved, so don't bother.
+ */
+static void dump_regs(void)
+{
+	u8 i, j = 0;
+	for (i = 0x50; i < 0xB8; i += sizeof(u32))
+		printf("%02x: 0x%08x %c", i,
+			smc911x_reg_read(CONFIG_DRIVER_SMC911X_BASE + i),
+			(j++ % 2 ? '\n' : ' '));
+}
+
+/**
+ *	do_eeprom_cmd - handle eeprom communication
+ */
+static int do_eeprom_cmd(int cmd, u8 reg)
+{
+	if (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY) {
+		printf("eeprom_cmd: busy at start (E2P_CMD = 0x%08x)\n",
+			smc911x_reg_read(E2P_CMD));
+		return -1;
+	}
+
+	smc911x_reg_write(E2P_CMD, E2P_CMD_EPC_BUSY | cmd | reg);
+
+	while (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY)
+		if (smsc_ctrlc()) {
+			printf("eeprom_cmd: timeout (E2P_CMD = 0x%08x)\n",
+				smc911x_reg_read(E2P_CMD));
+			return -1;
+		}
+
+	return 0;
+}
+
+/**
+ *	read_eeprom_reg - read specified register in EEPROM
+ */
+static u8 read_eeprom_reg(u8 reg)
+{
+	int ret = do_eeprom_cmd(E2P_CMD_EPC_CMD_READ, reg);
+	return (ret ? : smc911x_reg_read(E2P_DATA));
+}
+
+/**
+ *	write_eeprom_reg - write specified value into specified register in EEPROM
+ */
+static int write_eeprom_reg(u8 value, u8 reg)
+{
+	int ret;
+
+	/* enable erasing/writing */
+	ret = do_eeprom_cmd(E2P_CMD_EPC_CMD_EWEN, reg);
+	if (ret)
+		goto done;
+
+	/* erase the eeprom reg */
+	ret = do_eeprom_cmd(E2P_CMD_EPC_CMD_ERASE, reg);
+	if (ret)
+		goto done;
+
+	/* write the eeprom reg */
+	smc911x_reg_write(E2P_DATA, value);
+	ret = do_eeprom_cmd(E2P_CMD_EPC_CMD_WRITE, reg);
+	if (ret)
+		goto done;
+
+	/* disable erasing/writing */
+	ret = do_eeprom_cmd(E2P_CMD_EPC_CMD_EWDS, reg);
+
+ done:
+	return ret;
+}
+
+/**
+ *	skip_space - find first non-whitespace in given pointer
+ */
+static char *skip_space(char *buf)
+{
+	while (buf[0] == ' ' || buf[0] == '\t')
+		++buf;
+	return buf;
+}
+
+/**
+ *	write_stuff - handle writing of MAC registers / eeprom
+ */
+static void write_stuff(char *line)
+{
+	char dest;
+	char *endp;
+	u8 reg;
+	u32 value;
+
+	/* Skip over the "W " part of the command */
+	line = skip_space(line + 1);
+
+	/* Figure out destination */
+	switch (line[0]) {
+	case 'E':
+	case 'M':
+		dest = line[0];
+		break;
+	default:
+	invalid_usage:
+		printf("ERROR: Invalid write usage\n");
+		usage();
+		return;
+	}
+
+	/* Get the register to write */
+	line = skip_space(line + 1);
+	reg = simple_strtoul(line, &endp, 16);
+	if (line == endp)
+		goto invalid_usage;
+
+	/* Get the value to write */
+	line = skip_space(endp);
+	value = simple_strtoul(line, &endp, 16);
+	if (line == endp)
+		goto invalid_usage;
+
+	/* Check for trailing cruft */
+	line = skip_space(endp);
+	if (line[0])
+		goto invalid_usage;
+
+	/* Finally, execute the command */
+	if (dest == 'E') {
+		printf("Writing EEPROM register %02x with %02x\n", reg, value);
+		write_eeprom_reg(value, reg);
+	} else {
+		printf("Writing MAC register %02x with %08x\n", reg, value);
+		smc911x_reg_write(CONFIG_DRIVER_SMC911X_BASE + reg, value);
+	}
+}
+
+/**
+ *	copy_from_eeprom - copy MAC address in eeprom to address registers
+ */
+static void copy_from_eeprom(void)
+{
+	ulong addrl =
+		read_eeprom_reg(0x01) |
+		read_eeprom_reg(0x02) << 8 |
+		read_eeprom_reg(0x03) << 16 |
+		read_eeprom_reg(0x04) << 24;
+	ulong addrh =
+		read_eeprom_reg(0x05) |
+		read_eeprom_reg(0x06) << 8;
+	smc911x_set_mac_csr(ADDRL, addrl);
+	smc911x_set_mac_csr(ADDRH, addrh);
+	puts("EEPROM contents copied to MAC\n");
+}
+
+/**
+ *	print_macaddr - print MAC address registers and MAC address in eeprom
+ */
+static void print_macaddr(void)
+{
+	puts("Current MAC Address in MAC:     ");
+	ulong addrl = smc911x_get_mac_csr(ADDRL);
+	ulong addrh = smc911x_get_mac_csr(ADDRH);
+	printf("%02x:%02x:%02x:%02x:%02x:%02x\n",
+		(u8)(addrl), (u8)(addrl >> 8), (u8)(addrl >> 16),
+		(u8)(addrl >> 24), (u8)(addrh), (u8)(addrh >> 8));
+
+	puts("Current MAC Address in EEPROM:  ");
+	int i;
+	for (i = 1; i < 6; ++i)
+		printf("%02x:", read_eeprom_reg(i));
+	printf("%02x\n", read_eeprom_reg(i));
+}
+
+/**
+ *	dump_eeprom - dump the whole content of the EEPROM
+ */
+static void dump_eeprom(void)
+{
+	int i;
+	puts("EEPROM:\n");
+	for (i = 0; i < 7; ++i)
+		printf("%02x: 0x%02x\n", i, read_eeprom_reg(i));
+}
+
+/**
+ *	smc911x_init - get the MAC/EEPROM up and ready for use
+ */
+static int smc911x_init(void)
+{
+	/* See if there is anything there */
+	if (!smc911x_detect_chip())
+		return 1;
+
+	smc911x_reset();
+
+	/* Make sure we set EEDIO/EECLK to the EEPROM */
+	if (smc911x_reg_read(GPIO_CFG) & GPIO_CFG_EEPR_EN) {
+		while (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY)
+			if (smsc_ctrlc()) {
+				printf("init: timeout (E2P_CMD = 0x%08x)\n",
+					smc911x_reg_read(E2P_CMD));
+				return 1;
+			}
+		smc911x_reg_write(GPIO_CFG, smc911x_reg_read(GPIO_CFG) & ~GPIO_CFG_EEPR_EN);
+	}
+
+	return 0;
+}
+
+/**
+ *	getline - consume a line of input and handle some escape sequences
+ */
+static char *getline(void)
+{
+	static char buffer[100];
+	char c;
+	size_t i;
+
+	i = 0;
+	while (1) {
+		buffer[i] = '\0';
+		while (!tstc())
+			continue;
+
+		c = getc();
+		/* Convert to uppercase */
+		if (c >= 'a' && c <= 'z')
+			c -= ('a' - 'A');
+
+		switch (c) {
+		case '\r':	/* Enter/Return key */
+		case '\n':
+			puts("\n");
+			return buffer;
+
+		case 0x03:	/* ^C - break */
+			return NULL;
+
+		case 0x5F:
+		case 0x08:	/* ^H  - backspace */
+		case 0x7F:	/* DEL - backspace */
+			if (i) {
+				puts("\b \b");
+				i--;
+			}
+			break;
+
+		default:
+			/* Ignore control characters */
+			if (c < 0x20)
+				break;
+			/* Queue up all other characters */
+			buffer[i++] = c;
+			printf("%c", c);
+			break;
+		}
+	}
+}
+
+/**
+ *	smc911x_eeprom - our application's main() function
+ */
+int smc911x_eeprom(int argc, char *argv[])
+{
+	/* Print the ABI version */
+	app_startup(argv);
+	if (XF_VERSION != get_version()) {
+		printf("Expects ABI version %d\n", XF_VERSION);
+		printf("Actual U-Boot ABI version %lu\n", get_version());
+		printf("Can't run\n\n");
+		return 1;
+	}
+
+	/* Initialize the MAC/EEPROM somewhat */
+	puts("\n");
+	if (smc911x_init())
+		return 1;
+
+	/* Dump helpful usage information */
+	puts("\n");
+	usage();
+	puts("\n");
+
+	while (1) {
+		char *line;
+
+		/* Send the prompt and wait for a line */
+		puts("eeprom> ");
+		line = getline();
+
+		/* Got a ctrl+c */
+		if (!line)
+			return 0;
+
+		/* Eat leading space */
+		line = skip_space(line);
+
+		/* Empty line, try again */
+		if (!line[0])
+			continue;
+
+		/* Only accept 1 letter commands */
+		if (line[0] && line[1] && line[1] != ' ' && line[1] != '\t')
+			goto unknown_cmd;
+
+		/* Now parse the command */
+		switch (line[0]) {
+		case 'W': write_stuff(line);  break;
+		case 'D': dump_eeprom();      break;
+		case 'M': dump_regs();        break;
+		case 'C': copy_from_eeprom(); break;
+		case 'P': print_macaddr();    break;
+		unknown_cmd:
+		default:  puts("ERROR: Unknown command!\n\n");
+		case '?':
+		case 'H': usage();            break;
+		case 'Q': return 0;
+		}
+	}
+}
+
+#else
+int smc911x_eeprom(int argc, char *argv[])
+{
+	puts("Not supported for this board\n");
+	return 1;
+}
+#endif

include/asm-arm/arch-mx31/mx31-regs.h

@@ -134,7 +134,14 @@
 #define MUX_CTL_CSPI2_SS0	0x85
 #define MUX_CTL_CSPI2_SS1	0x86
 #define MUX_CTL_CSPI2_SS2	0x87
+#define MUX_CTL_CSPI1_SS2	0x88
+#define MUX_CTL_CSPI1_SCLK	0x89
+#define MUX_CTL_CSPI1_SPI_RDY	0x8a
 #define MUX_CTL_CSPI2_MOSI	0x8b
+#define MUX_CTL_CSPI1_MOSI	0x8c
+#define MUX_CTL_CSPI1_MISO	0x8d
+#define MUX_CTL_CSPI1_SS0	0x8e
+#define MUX_CTL_CSPI1_SS1	0x8f
 
 /*
  * Helper macros for the MUX_[contact name]__[pin function] macros
@@ -160,6 +167,15 @@
 	IOMUX_MODE(MUX_CTL_CSPI2_SPI_RDY, MUX_CTL_FUNC)
 #define MUX_CSPI2_SCLK__CSPI2_CLK IOMUX_MODE(MUX_CTL_CSPI2_SCLK, MUX_CTL_FUNC)
 
+#define MUX_CSPI1_SS0__CSPI1_SS0_B IOMUX_MODE(MUX_CTL_CSPI1_SS0, MUX_CTL_FUNC)
+#define MUX_CSPI1_SS1__CSPI1_SS1_B IOMUX_MODE(MUX_CTL_CSPI1_SS1, MUX_CTL_FUNC)
+#define MUX_CSPI1_SS2__CSPI1_SS2_B IOMUX_MODE(MUX_CTL_CSPI1_SS2, MUX_CTL_FUNC)
+#define MUX_CSPI1_MOSI__CSPI1_MOSI IOMUX_MODE(MUX_CTL_CSPI1_MOSI, MUX_CTL_FUNC)
+#define MUX_CSPI1_MISO__CSPI1_MISO IOMUX_MODE(MUX_CTL_CSPI1_MISO, MUX_CTL_FUNC)
+#define MUX_CSPI1_SPI_RDY__CSPI1_DATAREADY_B \
+	IOMUX_MODE(MUX_CTL_CSPI1_SPI_RDY, MUX_CTL_FUNC)
+#define MUX_CSPI1_SCLK__CSPI1_CLK IOMUX_MODE(MUX_CTL_CSPI1_SCLK, MUX_CTL_FUNC)
+
 #define MUX_CSPI2_MOSI__I2C2_SCL IOMUX_MODE(MUX_CTL_CSPI2_MOSI, MUX_CTL_ALT1)
 #define MUX_CSPI2_MISO__I2C2_SDA IOMUX_MODE(MUX_CTL_CSPI2_MISO, MUX_CTL_ALT1)
 

include/asm-arm/arch-mx31/mx31.h

@@ -27,4 +27,24 @@
 extern u32 mx31_get_ipg_clk(void);
 extern void mx31_gpio_mux(unsigned long mode);
 
+enum mx31_gpio_direction {
+	MX31_GPIO_DIRECTION_IN,
+	MX31_GPIO_DIRECTION_OUT,
+};
+
+#ifdef CONFIG_MX31_GPIO
+extern int mx31_gpio_direction(unsigned int gpio,
+			       enum mx31_gpio_direction direction);
+extern void mx31_gpio_set(unsigned int gpio, unsigned int value);
+#else
+static inline int mx31_gpio_direction(unsigned int gpio,
+				      enum mx31_gpio_direction direction)
+{
+	return 1;
+}
+static inline void mx31_gpio_set(unsigned int gpio, unsigned int value)
+{
+}
+#endif
+
 #endif /* __ASM_ARCH_MX31_H */

include/asm-arm/arch-omap3/cpu.h

@@ -60,6 +60,19 @@ typedef struct ctrl {
 #define OMAP3525		0x4c00
 #define OMAP3530		0x0c00
 
+#ifndef __ASSEMBLY__
+typedef struct ctrl_id {
+	unsigned char res1[0x4];
+	unsigned int idcode;		/* 0x04 */
+	unsigned int prod_id;		/* 0x08 */
+	unsigned char res2[0x0C];
+	unsigned int die_id_0;		/* 0x18 */
+	unsigned int die_id_1;		/* 0x1C */
+	unsigned int die_id_2;		/* 0x20 */
+	unsigned int die_id_3;		/* 0x24 */
+} ctrl_id_t;
+#endif /* __ASSEMBLY__ */
+
 /* device type */
 #define DEVICE_MASK		(0x7 << 8)
 #define SYSBOOT_MASK		0x1F

include/asm-arm/arch-omap3/omap3.h

@@ -43,6 +43,7 @@
  */
 #define OMAP34XX_CORE_L4_IO_BASE	0x48000000
 #define OMAP34XX_WAKEUP_L4_IO_BASE	0x48300000
+#define OMAP34XX_ID_L4_IO_BASE		0x4830A200
 #define OMAP34XX_L4_PER			0x49000000
 #define OMAP34XX_L4_IO_BASE		OMAP34XX_CORE_L4_IO_BASE
 

include/asm-arm/arch-omap3/sys_proto.h

@@ -66,5 +66,6 @@ void sdelay(unsigned long);
 void make_cs1_contiguous(void);
 void omap_nand_switch_ecc(int);
 void power_init_r(void);
+void dieid_num_r(void);
 
 #endif

include/asm-m68k/m5301x.h

@@ -601,4 +601,8 @@
 #define RTC_OCEN_OSCBYP			(0x00000010)
 #define RTC_OCEN_CLKEN			(0x00000008)
 
+/* SDRAM */
+#define SDRAMC_SDCR_CKE			(0x40000000)
+#define SDRAMC_SDCR_REF			(0x10000000)
+
 #endif				/* m5301x_h */

include/asm-ppc/config.h

@@ -22,7 +22,7 @@
 #define _ASM_CONFIG_H_
 
 #ifndef CONFIG_MAX_MEM_MAPPED
-#if defined(CONFIG_4xx) || defined(CONFIG_E500)
+#if defined(CONFIG_4xx) || defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
 #define CONFIG_MAX_MEM_MAPPED	((phys_size_t)2 << 30)
 #else
 #define CONFIG_MAX_MEM_MAPPED	(256 << 20)

include/asm-ppc/immap_85xx.h

@@ -1667,7 +1667,7 @@ typedef struct ccsr_gur {
 	uint	lbiuiplldcr0;	/* 0xe0f1c -- LBIU PLL Debug Reg 0 */
 	uint	lbiuiplldcr1;	/* 0xe0f20 -- LBIU PLL Debug Reg 1 */
 	uint	ddrioovcr;	/* 0xe0f24 - DDR IO Override Control */
-	uint	res14;		/* 0xe0f28 */
+	uint	tsec12ioovcr;	/* 0xe0f28 - eTSEC 1/2 IO override control */
 	uint	tsec34ioovcr;	/* 0xe0f2c - eTSEC 3/4 IO override control */
 	char	res15[61648];	/* 0xe0f30 to 0xefffff */
 } ccsr_gur_t;

include/asm-sh/cpu_sh4.h

@@ -54,4 +54,29 @@
 # error "Unknown SH4 variant"
 #endif
 
+#if defined(CONFIG_SH_32BIT)
+#define PMB_ADDR_ARRAY		0xf6100000
+#define PMB_ADDR_ENTRY		8
+#define PMB_VPN			24
+
+#define PMB_DATA_ARRAY		0xf7100000
+#define PMB_DATA_ENTRY		8
+#define PMB_PPN			24
+#define PMB_UB			9		/* Buffered write */
+#define PMB_V			8		/* Valid */
+#define PMB_SZ1			7		/* Page size (upper bit) */
+#define PMB_SZ0			4		/* Page size (lower bit) */
+#define PMB_C			3		/* Cacheability */
+#define PMB_WT			0		/* Write-through */
+
+#define PMB_ADDR_BASE(entry)	(PMB_ADDR_ARRAY + (entry << PMB_ADDR_ENTRY))
+#define PMB_DATA_BASE(entry)	(PMB_DATA_ARRAY + (entry << PMB_DATA_ENTRY))
+#define mk_pmb_addr_val(vpn)	((vpn << PMB_VPN))
+#define mk_pmb_data_val(ppn, ub, v, sz1, sz0, c, wt)	\
+				((ppn << PMB_PPN) | (ub << PMB_UB) | \
+				 (v << PMB_V) | (sz1 << PMB_SZ1) | \
+				 (sz0 << PMB_SZ0) | (c << PMB_C) | \
+				 (wt << PMB_WT))
+#endif
+
 #endif	/* _ASM_CPU_SH4_H_ */

include/common.h

@@ -269,6 +269,7 @@ void	forceenv     (char *, char *);
 #ifdef CONFIG_AUTO_COMPLETE
 int env_complete(char *var, int maxv, char *cmdv[], int maxsz, char *buf);
 #endif
+int get_env_id (void);
 
 void	pci_init      (void);
 void	pci_init_board(void);

include/commproc.h

@@ -1122,11 +1122,11 @@ typedef struct scc_enet {
 #define SICR_ENET_CLKRT	((uint)0x0000003d)
 #endif	/* CONFIG_MBX */
 
-/***  MGSUVD  *********************************************************/
+/***  KM8XX  *********************************************************/
 
-/* The MGSUVD Service Module uses SCC3 for Ethernet */
+/* The KM8XX Service Module uses SCC3 for Ethernet */
 
-#ifdef CONFIG_MGSUVD
+#ifdef CONFIG_KM8XX
 #define PROFF_ENET	PROFF_SCC3		/* Ethernet on SCC3 */
 #define CPM_CR_ENET	CPM_CR_CH_SCC3
 #define SCC_ENET	2
@@ -1145,7 +1145,7 @@ typedef struct scc_enet {
  */
 #define SICR_ENET_MASK	((uint)0x00FF0000)
 #define SICR_ENET_CLKRT	((uint)0x00250000)
-#endif	/* CONFIG_MGSUVD */
+#endif	/* CONFIG_KM8XX */
 
 
 /***  MHPC  ********************************************************/

include/configs/FLAGADM.h

@@ -173,6 +173,9 @@
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 #endif
+#define CONFIG_SYS_DELAYED_ICACHE	1	/* enable ICache not before
+						 * running in RAM.
+						 */
 
 /*-----------------------------------------------------------------------
  * SYPCR - System Protection Control				11-9

include/configs/IP860.h

@@ -209,6 +209,9 @@
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 #endif
+#define CONFIG_SYS_DELAYED_ICACHE	1	/* enable ICache not before
+						 * running in RAM.
+						 */
 
 /*-----------------------------------------------------------------------
  * SYPCR - System Protection Control				11-9